[thirdparty/u-boot.git] / drivers / serial / atmel_usart.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2004-2006 Atmel Corporation
 *
 * Modified to support C structur SoC access by
 * Andreas Bießmann <biessmann@corscience.de>
 */
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <watchdog.h>
#include <serial.h>
#include <debug_uart.h>
#include <asm/global_data.h>
#include <linux/compiler.h>
#include <linux/delay.h>

#include <asm/io.h>
#if CONFIG_IS_ENABLED(DM_SERIAL)
#include <asm/arch/atmel_serial.h>
#endif
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>

#include "atmel_usart.h"

DECLARE_GLOBAL_DATA_PTR;

#if !CONFIG_IS_ENABLED(DM_SERIAL)
static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
					 int baudrate)
{
	unsigned long divisor;
	unsigned long usart_hz;

	/*
	 *              Master Clock
	 * Baud Rate = --------------
	 *                16 * CD
	 */
	usart_hz = get_usart_clk_rate(id);
	divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
	writel(USART3_BF(CD, divisor), &usart->brgr);
}

static void atmel_serial_init_internal(atmel_usart3_t *usart)
{
	/*
	 * Just in case: drain transmitter register
	 * 1000us is enough for baudrate >= 9600
	 */
	if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
		__udelay(1000);

	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
}

static void atmel_serial_activate(atmel_usart3_t *usart)
{
	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
			   | USART3_BF(USCLKS, USART3_USCLKS_MCK)
			   | USART3_BF(CHRL, USART3_CHRL_8)
			   | USART3_BF(PAR, USART3_PAR_NONE)
			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
			   &usart->mr);
	writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
	/* 100us is enough for the new settings to be settled */
	__udelay(100);
}

static void atmel_serial_setbrg(void)
{
	atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE,
				     CFG_USART_ID, gd->baudrate);
}

static int atmel_serial_init(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;

	atmel_serial_init_internal(usart);
	serial_setbrg();
	atmel_serial_activate(usart);

	return 0;
}

static void atmel_serial_putc(char c)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;

	if (c == '\n')
		serial_putc('\r');

	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
	writel(c, &usart->thr);
}

static int atmel_serial_getc(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;

	while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
		 schedule();
	return readl(&usart->rhr);
}

static int atmel_serial_tstc(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;
	return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}

static struct serial_device atmel_serial_drv = {
	.name	= "atmel_serial",
	.start	= atmel_serial_init,
	.stop	= NULL,
	.setbrg	= atmel_serial_setbrg,
	.putc	= atmel_serial_putc,
	.puts	= default_serial_puts,
	.getc	= atmel_serial_getc,
	.tstc	= atmel_serial_tstc,
};

void atmel_serial_initialize(void)
{
	serial_register(&atmel_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &atmel_serial_drv;
}
#else
enum serial_clk_type {
	CLK_TYPE_NORMAL = 0,
	CLK_TYPE_DBGU,
};

struct atmel_serial_priv {
	atmel_usart3_t *usart;
	ulong usart_clk_rate;
};

static void _atmel_serial_set_brg(atmel_usart3_t *usart,
				  ulong usart_clk_rate, int baudrate)
{
	unsigned long divisor;

	divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
	writel(USART3_BF(CD, divisor), &usart->brgr);
}

void _atmel_serial_init(atmel_usart3_t *usart,
			ulong usart_clk_rate, int baudrate)
{
	writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);

	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
		USART3_BF(USCLKS, USART3_USCLKS_MCK) |
		USART3_BF(CHRL, USART3_CHRL_8) |
		USART3_BF(PAR, USART3_PAR_NONE) |
		USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);

	_atmel_serial_set_brg(usart, usart_clk_rate, baudrate);

	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
	writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
}

int atmel_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	_atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);

	return 0;
}

static int atmel_serial_getc(struct udevice *dev)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
		return -EAGAIN;

	return readl(&priv->usart->rhr);
}

static int atmel_serial_putc(struct udevice *dev, const char ch)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
		return -EAGAIN;

	writel(ch, &priv->usart->thr);

	return 0;
}

static int atmel_serial_pending(struct udevice *dev, bool input)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);
	uint32_t csr = readl(&priv->usart->csr);

	if (input)
		return csr & USART3_BIT(RXRDY) ? 1 : 0;
	else
		return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
}

static const struct dm_serial_ops atmel_serial_ops = {
	.putc = atmel_serial_putc,
	.pending = atmel_serial_pending,
	.getc = atmel_serial_getc,
	.setbrg = atmel_serial_setbrg,
};

#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
static int atmel_serial_enable_clk(struct udevice *dev)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);

	/* Use fixed clock value in SPL */
	priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;

	return 0;
}
#else
static int atmel_serial_enable_clk(struct udevice *dev)
{
	struct atmel_serial_priv *priv = dev_get_priv(dev);
	struct clk clk;
	ulong clk_rate;
	int ret;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret)
		return -EINVAL;

	if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
		ret = clk_enable(&clk);
		if (ret)
			return ret;
	}

	clk_rate = clk_get_rate(&clk);
	if (!clk_rate)
		return -EINVAL;

	priv->usart_clk_rate = clk_rate;

	return 0;
}
#endif

static int atmel_serial_probe(struct udevice *dev)
{
	struct atmel_serial_plat *plat = dev_get_plat(dev);
	struct atmel_serial_priv *priv = dev_get_priv(dev);
	int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL)
	fdt_addr_t addr_base;

	addr_base = dev_read_addr(dev);
	if (addr_base == FDT_ADDR_T_NONE)
		return -ENODEV;

	plat->base_addr = (uint32_t)addr_base;
#endif
	priv->usart = (atmel_usart3_t *)plat->base_addr;

	ret = atmel_serial_enable_clk(dev);
	if (ret)
		return ret;

	_atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);

	return 0;
}

#if CONFIG_IS_ENABLED(OF_CONTROL)
static const struct udevice_id atmel_serial_ids[] = {
	{
		.compatible = "atmel,at91sam9260-dbgu",
		.data = CLK_TYPE_DBGU,
	},
	{
		.compatible = "atmel,at91sam9260-usart",
		.data = CLK_TYPE_NORMAL,
	},
	{ }
};
#endif

U_BOOT_DRIVER(serial_atmel) = {
	.name	= "serial_atmel",
	.id	= UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
	.of_match = atmel_serial_ids,
	.plat_auto	= sizeof(struct atmel_serial_plat),
#endif
	.probe = atmel_serial_probe,
	.ops	= &atmel_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
	.flags = DM_FLAG_PRE_RELOC,
#endif
	.priv_auto	= sizeof(struct atmel_serial_priv),
};
#endif

#ifdef CONFIG_DEBUG_UART_ATMEL
static inline void _debug_uart_init(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);

	_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
}

static inline void _debug_uart_putc(int ch)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);

	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
		;

	writel(ch, &usart->thr);
}

DEBUG_UART_FUNCS
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f93ae788 WD	2	/*
	3	* Copyright (C) 2004-2006 Atmel Corporation
	4	*
125637c5 AB	5	* Modified to support C structur SoC access by
125637c5 AB	6	* Andreas Bießmann <biessmann@corscience.de>
f93ae788	7	*/
d678a59d	8	#include <common.h>
f8b7fff1	9	#include <clk.h>
0f65f48b SG	10	#include <dm.h>
0f65f48b SG	11	#include <errno.h>
336d4615	12	#include <malloc.h>
843a2654	13	#include <watchdog.h>
cfba4573	14	#include <serial.h>
998cf3c2	15	#include <debug_uart.h>
401d1c4f	16	#include <asm/global_data.h>
cfba4573	17	#include <linux/compiler.h>
c05ed00a	18	#include <linux/delay.h>
f93ae788	19
f93ae788	20	#include <asm/io.h>
0478dac6	21	#if CONFIG_IS_ENABLED(DM_SERIAL)
0f65f48b SG	22	#include <asm/arch/atmel_serial.h>
0f65f48b SG	23	#endif
df548d3c	24	#include <asm/arch/clk.h>
329f0f52	25	#include <asm/arch/hardware.h>
f93ae788 WD	26
	27	#include "atmel_usart.h"
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
0478dac6	31	#if !CONFIG_IS_ENABLED(DM_SERIAL)
62137fc0 SG	32	static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
62137fc0 SG	33	int baudrate)
f93ae788 WD	34	{
	35	unsigned long divisor;
	36	unsigned long usart_hz;
	37
	38	/*
	39	* Master Clock
	40	* Baud Rate = --------------
	41	* 16 * CD
	42	*/
62137fc0 SG	43	usart_hz = get_usart_clk_rate(id);
62137fc0 SG	44	divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
125637c5	45	writel(USART3_BF(CD, divisor), &usart->brgr);
f93ae788 WD	46	}
f93ae788 WD	47
62137fc0	48	static void atmel_serial_init_internal(atmel_usart3_t *usart)
f93ae788	49	{
1f4faedd XH	50	/*
	51	* Just in case: drain transmitter register
	52	* 1000us is enough for baudrate >= 9600
	53	*/
	54	if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
	55	__udelay(1000);
	56
125637c5	57	writel(USART3_BIT(RSTRX) \| USART3_BIT(RSTTX), &usart->cr);
62137fc0	58	}
f93ae788	59
62137fc0 SG	60	static void atmel_serial_activate(atmel_usart3_t *usart)
62137fc0 SG	61	{
125637c5	62	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
df548d3c HS	63	\| USART3_BF(USCLKS, USART3_USCLKS_MCK)
	64	\| USART3_BF(CHRL, USART3_CHRL_8)
	65	\| USART3_BF(PAR, USART3_PAR_NONE)
125637c5 AB	66	\| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
125637c5 AB	67	&usart->mr);
1f4faedd XH	68	writel(USART3_BIT(RXEN) \| USART3_BIT(TXEN), &usart->cr);
	69	/* 100us is enough for the new settings to be settled */
	70	__udelay(100);
62137fc0 SG	71	}
	72
	73	static void atmel_serial_setbrg(void)
	74	{
805482d1	75	atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE,
61693acb	76	CFG_USART_ID, gd->baudrate);
62137fc0 SG	77	}
	78
	79	static int atmel_serial_init(void)
	80	{
805482d1	81	atmel_usart3_t usart = (atmel_usart3_t )CFG_USART_BASE;
62137fc0 SG	82
	83	atmel_serial_init_internal(usart);
	84	serial_setbrg();
	85	atmel_serial_activate(usart);
f93ae788 WD	86
	87	return 0;
	88	}
	89
cfba4573	90	static void atmel_serial_putc(char c)
f93ae788	91	{
805482d1	92	atmel_usart3_t usart = (atmel_usart3_t )CFG_USART_BASE;
125637c5	93
f93ae788 WD	94	if (c == '\n')
	95	serial_putc('\r');
	96
125637c5 AB	97	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
125637c5 AB	98	writel(c, &usart->thr);
f93ae788 WD	99	}
f93ae788 WD	100
cfba4573	101	static int atmel_serial_getc(void)
f93ae788	102	{
805482d1	103	atmel_usart3_t usart = (atmel_usart3_t )CFG_USART_BASE;
125637c5 AB	104
125637c5 AB	105	while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
29caf930	106	schedule();
125637c5	107	return readl(&usart->rhr);
f93ae788 WD	108	}
f93ae788 WD	109
cfba4573	110	static int atmel_serial_tstc(void)
f93ae788	111	{
805482d1	112	atmel_usart3_t usart = (atmel_usart3_t )CFG_USART_BASE;
125637c5	113	return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
f93ae788	114	}
cfba4573	115
cfba4573 MV	116	static struct serial_device atmel_serial_drv = {
	117	.name = "atmel_serial",
	118	.start = atmel_serial_init,
	119	.stop = NULL,
	120	.setbrg = atmel_serial_setbrg,
	121	.putc = atmel_serial_putc,
ec3fd689	122	.puts = default_serial_puts,
cfba4573 MV	123	.getc = atmel_serial_getc,
	124	.tstc = atmel_serial_tstc,
	125	};
	126
	127	void atmel_serial_initialize(void)
	128	{
	129	serial_register(&atmel_serial_drv);
	130	}
	131
	132	__weak struct serial_device *default_serial_console(void)
	133	{
	134	return &atmel_serial_drv;
	135	}
0478dac6	136	#else
f8b7fff1 WY	137	enum serial_clk_type {
	138	CLK_TYPE_NORMAL = 0,
	139	CLK_TYPE_DBGU,
	140	};
0f65f48b SG	141
	142	struct atmel_serial_priv {
	143	atmel_usart3_t *usart;
f8b7fff1	144	ulong usart_clk_rate;
0f65f48b SG	145	};
0f65f48b SG	146
5f29e799 WY	147	static void _atmel_serial_set_brg(atmel_usart3_t *usart,
	148	ulong usart_clk_rate, int baudrate)
	149	{
	150	unsigned long divisor;
	151
	152	divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
	153	writel(USART3_BF(CD, divisor), &usart->brgr);
	154	}
	155
	156	void _atmel_serial_init(atmel_usart3_t *usart,
	157	ulong usart_clk_rate, int baudrate)
	158	{
	159	writel(USART3_BIT(RXDIS) \| USART3_BIT(TXDIS), &usart->cr);
	160
	161	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) \|
	162	USART3_BF(USCLKS, USART3_USCLKS_MCK) \|
	163	USART3_BF(CHRL, USART3_CHRL_8) \|
	164	USART3_BF(PAR, USART3_PAR_NONE) \|
	165	USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
	166
	167	_atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
	168
	169	writel(USART3_BIT(RSTRX) \| USART3_BIT(RSTTX), &usart->cr);
	170	writel(USART3_BIT(RXEN) \| USART3_BIT(TXEN), &usart->cr);
	171	}
	172
0f65f48b SG	173	int atmel_serial_setbrg(struct udevice *dev, int baudrate)
	174	{
	175	struct atmel_serial_priv *priv = dev_get_priv(dev);
	176
f8b7fff1	177	_atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
0f65f48b SG	178
	179	return 0;
	180	}
	181
	182	static int atmel_serial_getc(struct udevice *dev)
	183	{
	184	struct atmel_serial_priv *priv = dev_get_priv(dev);
	185
	186	if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
	187	return -EAGAIN;
	188
	189	return readl(&priv->usart->rhr);
	190	}
	191
	192	static int atmel_serial_putc(struct udevice *dev, const char ch)
	193	{
	194	struct atmel_serial_priv *priv = dev_get_priv(dev);
	195
	196	if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
	197	return -EAGAIN;
	198
	199	writel(ch, &priv->usart->thr);
	200
	201	return 0;
	202	}
	203
	204	static int atmel_serial_pending(struct udevice *dev, bool input)
	205	{
	206	struct atmel_serial_priv *priv = dev_get_priv(dev);
	207	uint32_t csr = readl(&priv->usart->csr);
	208
	209	if (input)
	210	return csr & USART3_BIT(RXRDY) ? 1 : 0;
	211	else
	212	return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
	213	}
	214
	215	static const struct dm_serial_ops atmel_serial_ops = {
	216	.putc = atmel_serial_putc,
	217	.pending = atmel_serial_pending,
	218	.getc = atmel_serial_getc,
	219	.setbrg = atmel_serial_setbrg,
	220	};
	221
e567dfb2 SR	222	#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
	223	static int atmel_serial_enable_clk(struct udevice *dev)
	224	{
	225	struct atmel_serial_priv *priv = dev_get_priv(dev);
	226
	227	/* Use fixed clock value in SPL */
	228	priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
	229
	230	return 0;
	231	}
	232	#else
f8b7fff1 WY	233	static int atmel_serial_enable_clk(struct udevice *dev)
	234	{
	235	struct atmel_serial_priv *priv = dev_get_priv(dev);
	236	struct clk clk;
	237	ulong clk_rate;
	238	int ret;
	239
	240	ret = clk_get_by_index(dev, 0, &clk);
	241	if (ret)
	242	return -EINVAL;
	243
	244	if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
	245	ret = clk_enable(&clk);
	246	if (ret)
	247	return ret;
	248	}
	249
	250	clk_rate = clk_get_rate(&clk);
	251	if (!clk_rate)
	252	return -EINVAL;
	253
	254	priv->usart_clk_rate = clk_rate;
	255
f8b7fff1 WY	256	return 0;
f8b7fff1 WY	257	}
e567dfb2	258	#endif
f8b7fff1	259
0f65f48b SG	260	static int atmel_serial_probe(struct udevice *dev)
0f65f48b SG	261	{
0fd3d911	262	struct atmel_serial_plat *plat = dev_get_plat(dev);
0f65f48b	263	struct atmel_serial_priv *priv = dev_get_priv(dev);
f8b7fff1	264	int ret;
c1631c8a WY	265	#if CONFIG_IS_ENABLED(OF_CONTROL)
c1631c8a WY	266	fdt_addr_t addr_base;
0f65f48b	267
2548493a	268	addr_base = dev_read_addr(dev);
c1631c8a WY	269	if (addr_base == FDT_ADDR_T_NONE)
	270	return -ENODEV;
	271
	272	plat->base_addr = (uint32_t)addr_base;
	273	#endif
0f65f48b	274	priv->usart = (atmel_usart3_t *)plat->base_addr;
5f29e799	275
f8b7fff1 WY	276	ret = atmel_serial_enable_clk(dev);
	277	if (ret)
	278	return ret;
	279
	280	_atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
0f65f48b SG	281
	282	return 0;
	283	}
	284
c1631c8a WY	285	#if CONFIG_IS_ENABLED(OF_CONTROL)
c1631c8a WY	286	static const struct udevice_id atmel_serial_ids[] = {
f8b7fff1 WY	287	{
	288	.compatible = "atmel,at91sam9260-dbgu",
	289	.data = CLK_TYPE_DBGU,
	290	},
	291	{
	292	.compatible = "atmel,at91sam9260-usart",
	293	.data = CLK_TYPE_NORMAL,
	294	},
c1631c8a WY	295	{ }
	296	};
	297	#endif
	298
0f65f48b SG	299	U_BOOT_DRIVER(serial_atmel) = {
	300	.name = "serial_atmel",
	301	.id = UCLASS_SERIAL,
c1631c8a WY	302	#if CONFIG_IS_ENABLED(OF_CONTROL)
c1631c8a WY	303	.of_match = atmel_serial_ids,
8a8d24bd	304	.plat_auto = sizeof(struct atmel_serial_plat),
c1631c8a	305	#endif
0f65f48b SG	306	.probe = atmel_serial_probe,
0f65f48b SG	307	.ops = &atmel_serial_ops,
46879196	308	#if !CONFIG_IS_ENABLED(OF_CONTROL)
0f65f48b	309	.flags = DM_FLAG_PRE_RELOC,
46879196	310	#endif
41575d8e	311	.priv_auto = sizeof(struct atmel_serial_priv),
0f65f48b SG	312	};
0f65f48b SG	313	#endif
998cf3c2 WY	314
	315	#ifdef CONFIG_DEBUG_UART_ATMEL
	316	static inline void _debug_uart_init(void)
	317	{
b62450cf	318	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_VAL(DEBUG_UART_BASE);
998cf3c2	319
5f29e799	320	_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
998cf3c2 WY	321	}
	322
	323	static inline void _debug_uart_putc(int ch)
	324	{
b62450cf	325	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_VAL(DEBUG_UART_BASE);
998cf3c2 WY	326
	327	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
	328	;
	329
	330	writel(ch, &usart->thr);
	331	}
	332
	333	DEBUG_UART_FUNCS
	334	#endif