[thirdparty/u-boot.git] / drivers / serial / serial_lpuart.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019 NXP
 * Copyright 2013 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <clock_legacy.h>
#include <clk.h>
#include <dm.h>
#include <fsl_lpuart.h>
#include <log.h>
#include <watchdog.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <serial.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

#define US1_TDRE	(1 << 7)
#define US1_RDRF	(1 << 5)
#define US1_OR		(1 << 3)
#define UC2_TE		(1 << 3)
#define UC2_RE		(1 << 2)
#define CFIFO_TXFLUSH	(1 << 7)
#define CFIFO_RXFLUSH	(1 << 6)
#define SFIFO_RXOF	(1 << 2)
#define SFIFO_RXUF	(1 << 0)

#define STAT_LBKDIF	(1 << 31)
#define STAT_RXEDGIF	(1 << 30)
#define STAT_TDRE	(1 << 23)
#define STAT_RDRF	(1 << 21)
#define STAT_IDLE	(1 << 20)
#define STAT_OR		(1 << 19)
#define STAT_NF		(1 << 18)
#define STAT_FE		(1 << 17)
#define STAT_PF		(1 << 16)
#define STAT_MA1F	(1 << 15)
#define STAT_MA2F	(1 << 14)
#define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
			 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)

#define CTRL_TE		(1 << 19)
#define CTRL_RE		(1 << 18)

#define FIFO_RXFLUSH		BIT(14)
#define FIFO_TXFLUSH		BIT(15)
#define FIFO_TXSIZE_MASK	0x70
#define FIFO_TXSIZE_OFF	4
#define FIFO_RXSIZE_MASK	0x7
#define FIFO_RXSIZE_OFF	0
#define FIFO_TXFE		0x80
#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
#define FIFO_RXFE		0x08
#else
#define FIFO_RXFE		0x40
#endif

#define WATER_TXWATER_OFF	0
#define WATER_RXWATER_OFF	16

DECLARE_GLOBAL_DATA_PTR;

#define LPUART_FLAG_REGMAP_32BIT_REG	BIT(0)
#define LPUART_FLAG_REGMAP_ENDIAN_BIG	BIT(1)

enum lpuart_devtype {
	DEV_VF610 = 1,
	DEV_LS1021A,
	DEV_MX7ULP,
	DEV_IMX8,
	DEV_IMXRT,
};

struct lpuart_serial_plat {
	void *reg;
	enum lpuart_devtype devtype;
	ulong flags;
};

static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
{
	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
		if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
			*(u32 *)val = in_be32(addr);
		else
			*(u32 *)val = in_le32(addr);
	}
}

static void lpuart_write32(u32 flags, u32 *addr, u32 val)
{
	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
		if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
			out_be32(addr, val);
		else
			out_le32(addr, val);
	}
}


u32 __weak get_lpuart_clk(void)
{
	return get_board_sys_clk();
}

#if CONFIG_IS_ENABLED(CLK)
static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk_rate)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct clk clk;
	ulong rate;
	int ret;
	char *name;

	if (plat->devtype == DEV_MX7ULP)
		name = "ipg";
	else
		name = "per";

	ret = clk_get_by_name(dev, name, &clk);
	if (ret) {
		dev_err(dev, "Failed to get clk: %d\n", ret);
		return ret;
	}

	rate = clk_get_rate(&clk);
	if ((long)rate <= 0) {
		dev_err(dev, "Failed to get clk rate: %ld\n", (long)rate);
		return ret;
	}
	*clk_rate = rate;
	return 0;
}
#else
static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk_rate)
{ return -ENOSYS; }
#endif

static bool is_lpuart32(struct udevice *dev)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);

	return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}

static void _lpuart_serial_setbrg(struct udevice *dev,
				  int baudrate)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct lpuart_fsl *base = plat->reg;
	u32 clk;
	u16 sbr;
	int ret;

	if (CONFIG_IS_ENABLED(CLK)) {
		ret = get_lpuart_clk_rate(dev, &clk);
		if (ret)
			return;
	} else {
		clk = get_lpuart_clk();
	}

	sbr = (u16)(clk / (16 * baudrate));

	/* place adjustment later - n/32 BRFA */
	__raw_writeb(sbr >> 8, &base->ubdh);
	__raw_writeb(sbr & 0xff, &base->ubdl);
}

static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
{
	struct lpuart_fsl *base = plat->reg;
	if (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
		return -EAGAIN;

	barrier();

	return __raw_readb(&base->ud);
}

static int _lpuart_serial_putc(struct lpuart_serial_plat *plat,
				const char c)
{
	struct lpuart_fsl *base = plat->reg;

	if (!(__raw_readb(&base->us1) & US1_TDRE))
		return -EAGAIN;

	__raw_writeb(c, &base->ud);
	return 0;
}

/* Test whether a character is in the RX buffer */
static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat)
{
	struct lpuart_fsl *base = plat->reg;

	if (__raw_readb(&base->urcfifo) == 0)
		return 0;

	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 */
static int _lpuart_serial_init(struct udevice *dev)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
	u8 ctrl;

	ctrl = __raw_readb(&base->uc2);
	ctrl &= ~UC2_RE;
	ctrl &= ~UC2_TE;
	__raw_writeb(ctrl, &base->uc2);

	__raw_writeb(0, &base->umodem);
	__raw_writeb(0, &base->uc1);

	/* Disable FIFO and flush buffer */
	__raw_writeb(0x0, &base->upfifo);
	__raw_writeb(0x0, &base->utwfifo);
	__raw_writeb(0x1, &base->urwfifo);
	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);

	/* provide data bits, parity, stop bit, etc */
	_lpuart_serial_setbrg(dev, gd->baudrate);

	__raw_writeb(UC2_RE | UC2_TE, &base->uc2);

	return 0;
}

static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
					 int baudrate)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
	u32 clk;
	int ret;

	if (CONFIG_IS_ENABLED(CLK)) {
		ret = get_lpuart_clk_rate(dev, &clk);
		if (ret)
			return;
	} else {
		clk = get_lpuart_clk();
	}

	baud_diff = baudrate;
	osr = 0;
	sbr = 0;

	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
		tmp_sbr = (clk / (baudrate * tmp_osr));

		if (tmp_sbr == 0)
			tmp_sbr = 1;

		/*calculate difference in actual buad w/ current values */
		tmp_diff = (clk / (tmp_osr * tmp_sbr));
		tmp_diff = tmp_diff - baudrate;

		/* select best values between sbr and sbr+1 */
		if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
			tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
			tmp_sbr++;
		}

		if (tmp_diff <= baud_diff) {
			baud_diff = tmp_diff;
			osr = tmp_osr;
			sbr = tmp_sbr;
		}
	}

	/*
	 * TODO: handle buadrate outside acceptable rate
	 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
	 * {
	 *   Unacceptable baud rate difference of more than 3%
	 *   return kStatus_LPUART_BaudrateNotSupport;
	 * }
	 */
	tmp = in_le32(&base->baud);

	if ((osr > 3) && (osr < 8))
		tmp |= LPUART_BAUD_BOTHEDGE_MASK;

	tmp &= ~LPUART_BAUD_OSR_MASK;
	tmp |= LPUART_BAUD_OSR(osr-1);

	tmp &= ~LPUART_BAUD_SBR_MASK;
	tmp |= LPUART_BAUD_SBR(sbr);

	/* explicitly disable 10 bit mode & set 1 stop bit */
	tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);

	out_le32(&base->baud, tmp);
}

static void _lpuart32_serial_setbrg(struct udevice *dev,
				    int baudrate)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 clk;
	u32 sbr;
	int ret;

	if (CONFIG_IS_ENABLED(CLK)) {
		ret = get_lpuart_clk_rate(dev, &clk);
		if (ret)
			return;
	} else {
		clk = get_lpuart_clk();
	}

	sbr = (clk / (16 * baudrate));

	/* place adjustment later - n/32 BRFA */
	lpuart_write32(plat->flags, &base->baud, sbr);
}

static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 stat, val;

	lpuart_read32(plat->flags, &base->stat, &stat);
	if ((stat & STAT_RDRF) == 0) {
		lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
		return -EAGAIN;
	}

	lpuart_read32(plat->flags, &base->data, &val);

	lpuart_read32(plat->flags, &base->stat, &stat);
	if (stat & STAT_OR)
		lpuart_write32(plat->flags, &base->stat, STAT_OR);

	return val & 0x3ff;
}

static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
				  const char c)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 stat;

	lpuart_read32(plat->flags, &base->stat, &stat);
	if (!(stat & STAT_TDRE))
		return -EAGAIN;

	lpuart_write32(plat->flags, &base->data, c);
	return 0;
}

/* Test whether a character is in the RX buffer */
static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
{
	struct lpuart_fsl_reg32 *base = plat->reg;
	u32 water;

	lpuart_read32(plat->flags, &base->water, &water);

	if ((water >> 24) == 0)
		return 0;

	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 */
static int _lpuart32_serial_init(struct udevice *dev)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
	u32 val, tx_fifo_size;

	lpuart_read32(plat->flags, &base->ctrl, &val);
	val &= ~CTRL_RE;
	val &= ~CTRL_TE;
	lpuart_write32(plat->flags, &base->ctrl, val);

	lpuart_write32(plat->flags, &base->modir, 0);

	lpuart_read32(plat->flags, &base->fifo, &val);
	tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
	/* Set the TX water to half of FIFO size */
	if (tx_fifo_size > 1)
		tx_fifo_size = tx_fifo_size >> 1;

	/* Set RX water to 0, to be triggered by any receive data */
	lpuart_write32(plat->flags, &base->water,
		       (tx_fifo_size << WATER_TXWATER_OFF));

	/* Enable TX and RX FIFO */
	val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
	lpuart_write32(plat->flags, &base->fifo, val);

	lpuart_write32(plat->flags, &base->match, 0);

	if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
	    plat->devtype == DEV_IMXRT) {
		_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
	} else {
		/* provide data bits, parity, stop bit, etc */
		_lpuart32_serial_setbrg(dev, gd->baudrate);
	}

	lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);

	return 0;
}

static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);

	if (is_lpuart32(dev)) {
		if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
		    plat->devtype == DEV_IMXRT)
			_lpuart32_serial_setbrg_7ulp(dev, baudrate);
		else
			_lpuart32_serial_setbrg(dev, baudrate);
	} else {
		_lpuart_serial_setbrg(dev, baudrate);
	}

	return 0;
}

static int lpuart_serial_getc(struct udevice *dev)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);

	if (is_lpuart32(dev))
		return _lpuart32_serial_getc(plat);

	return _lpuart_serial_getc(plat);
}

static int lpuart_serial_putc(struct udevice *dev, const char c)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);

	if (is_lpuart32(dev))
		return _lpuart32_serial_putc(plat, c);

	return _lpuart_serial_putc(plat, c);
}

static int lpuart_serial_pending(struct udevice *dev, bool input)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct lpuart_fsl *reg = plat->reg;
	struct lpuart_fsl_reg32 *reg32 = plat->reg;
	u32 stat;

	if (is_lpuart32(dev)) {
		if (input) {
			return _lpuart32_serial_tstc(plat);
		} else {
			lpuart_read32(plat->flags, &reg32->stat, &stat);
			return stat & STAT_TDRE ? 0 : 1;
		}
	}

	if (input)
		return _lpuart_serial_tstc(plat);
	else
		return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
}

static int lpuart_serial_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(CLK)
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	struct clk per_clk;
	struct clk ipg_clk;
	int ret;

	if (plat->devtype != DEV_MX7ULP) {
		ret = clk_get_by_name(dev, "per", &per_clk);
		if (!ret) {
			ret = clk_enable(&per_clk);
			if (ret) {
				dev_err(dev, "Failed to enable per clk: %d\n", ret);
				return ret;
			}
		} else {
			debug("%s: Failed to get per clk: %d\n", __func__, ret);
		}
	}

	ret = clk_get_by_name(dev, "ipg", &ipg_clk);
	if (!ret) {
		ret = clk_enable(&ipg_clk);
		if (ret) {
			dev_err(dev, "Failed to enable ipg clk: %d\n", ret);
			return ret;
		}
	} else {
		debug("%s: Failed to get ipg clk: %d\n", __func__, ret);
	}
#endif

	if (is_lpuart32(dev))
		return _lpuart32_serial_init(dev);
	else
		return _lpuart_serial_init(dev);
}

static int lpuart_serial_of_to_plat(struct udevice *dev)
{
	struct lpuart_serial_plat *plat = dev_get_plat(dev);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	fdt_addr_t addr;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->reg = (void *)addr;
	plat->flags = dev_get_driver_data(dev);

	if (fdtdec_get_bool(blob, node, "little-endian"))
		plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;

	if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
		plat->devtype = DEV_LS1021A;
	else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
		plat->devtype = DEV_MX7ULP;
	else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
		plat->devtype = DEV_VF610;
	else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
		plat->devtype = DEV_IMX8;
	else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
		plat->devtype = DEV_IMXRT;

	return 0;
}

static const struct dm_serial_ops lpuart_serial_ops = {
	.putc = lpuart_serial_putc,
	.pending = lpuart_serial_pending,
	.getc = lpuart_serial_getc,
	.setbrg = lpuart_serial_setbrg,
};

static const struct udevice_id lpuart_serial_ids[] = {
	{ .compatible = "fsl,ls1021a-lpuart", .data =
		LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
	{ .compatible = "fsl,ls1028a-lpuart",
		.data = LPUART_FLAG_REGMAP_32BIT_REG },
	{ .compatible = "fsl,imx7ulp-lpuart",
		.data = LPUART_FLAG_REGMAP_32BIT_REG },
	{ .compatible = "fsl,vf610-lpuart"},
	{ .compatible = "fsl,imx8qm-lpuart",
		.data = LPUART_FLAG_REGMAP_32BIT_REG },
	{ .compatible = "fsl,imxrt-lpuart",
		.data = LPUART_FLAG_REGMAP_32BIT_REG },
	{ }
};

U_BOOT_DRIVER(serial_lpuart) = {
	.name	= "serial_lpuart",
	.id	= UCLASS_SERIAL,
	.of_match = lpuart_serial_ids,
	.of_to_plat = lpuart_serial_of_to_plat,
	.plat_auto	= sizeof(struct lpuart_serial_plat),
	.probe = lpuart_serial_probe,
	.ops	= &lpuart_serial_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
427eba70	2	/*
1edc5688	3	* Copyright 2019 NXP
427eba70	4	* Copyright 2013 Freescale Semiconductor, Inc.
427eba70 AW	5	*/
427eba70 AW	6
d678a59d	7	#include <common.h>
2f8a6db5	8	#include <clock_legacy.h>
8f5b6299	9	#include <clk.h>
fdbae099	10	#include <dm.h>
c40d612b	11	#include <fsl_lpuart.h>
f7ae49fc	12	#include <log.h>
427eba70	13	#include <watchdog.h>
401d1c4f	14	#include <asm/global_data.h>
427eba70 AW	15	#include <asm/io.h>
427eba70 AW	16	#include <serial.h>
336d4615	17	#include <dm/device_compat.h>
cd93d625	18	#include <linux/bitops.h>
427eba70 AW	19	#include <linux/compiler.h>
	20	#include <asm/arch/imx-regs.h>
	21	#include <asm/arch/clock.h>
	22
47f1bfca BM	23	#define US1_TDRE (1 << 7)
	24	#define US1_RDRF (1 << 5)
	25	#define US1_OR (1 << 3)
	26	#define UC2_TE (1 << 3)
	27	#define UC2_RE (1 << 2)
	28	#define CFIFO_TXFLUSH (1 << 7)
	29	#define CFIFO_RXFLUSH (1 << 6)
	30	#define SFIFO_RXOF (1 << 2)
	31	#define SFIFO_RXUF (1 << 0)
427eba70	32
6209e14c JL	33	#define STAT_LBKDIF (1 << 31)
	34	#define STAT_RXEDGIF (1 << 30)
	35	#define STAT_TDRE (1 << 23)
	36	#define STAT_RDRF (1 << 21)
	37	#define STAT_IDLE (1 << 20)
	38	#define STAT_OR (1 << 19)
	39	#define STAT_NF (1 << 18)
	40	#define STAT_FE (1 << 17)
	41	#define STAT_PF (1 << 16)
	42	#define STAT_MA1F (1 << 15)
	43	#define STAT_MA2F (1 << 14)
	44	#define STAT_FLAGS (STAT_LBKDIF \| STAT_RXEDGIF \| STAT_IDLE \| STAT_OR \| \
47f1bfca	45	STAT_NF \| STAT_FE \| STAT_PF \| STAT_MA1F \| STAT_MA2F)
6209e14c JL	46
	47	#define CTRL_TE (1 << 19)
	48	#define CTRL_RE (1 << 18)
	49
cdc16f61 YL	50	#define FIFO_RXFLUSH BIT(14)
	51	#define FIFO_TXFLUSH BIT(15)
	52	#define FIFO_TXSIZE_MASK 0x70
	53	#define FIFO_TXSIZE_OFF 4
	54	#define FIFO_RXSIZE_MASK 0x7
	55	#define FIFO_RXSIZE_OFF 0
6209e14c	56	#define FIFO_TXFE 0x80
c32449a1	57	#if defined(CONFIG_ARCH_IMX8) \|\| defined(CONFIG_ARCH_IMXRT)
126f8849 PF	58	#define FIFO_RXFE 0x08
126f8849 PF	59	#else
6209e14c	60	#define FIFO_RXFE 0x40
126f8849	61	#endif
6209e14c	62
cdc16f61	63	#define WATER_TXWATER_OFF 0
6209e14c JL	64	#define WATER_RXWATER_OFF 16
6209e14c JL	65
427eba70 AW	66	DECLARE_GLOBAL_DATA_PTR;
427eba70 AW	67
c40d612b PF	68	#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
	69	#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
	70
7edf5c45 PF	71	enum lpuart_devtype {
	72	DEV_VF610 = 1,
	73	DEV_LS1021A,
126f8849	74	DEV_MX7ULP,
c32449a1 GB	75	DEV_IMX8,
c32449a1 GB	76	DEV_IMXRT,
7edf5c45 PF	77	};
7edf5c45 PF	78
8a8d24bd	79	struct lpuart_serial_plat {
c40d612b	80	void *reg;
7edf5c45	81	enum lpuart_devtype devtype;
c40d612b	82	ulong flags;
fdbae099 BM	83	};
fdbae099 BM	84
c40d612b PF	85	static void lpuart_read32(u32 flags, u32 addr, u32 val)
	86	{
	87	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
	88	if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
	89	(u32 )val = in_be32(addr);
	90	else
	91	(u32 )val = in_le32(addr);
	92	}
	93	}
	94
	95	static void lpuart_write32(u32 flags, u32 *addr, u32 val)
	96	{
	97	if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
	98	if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
	99	out_be32(addr, val);
	100	else
	101	out_le32(addr, val);
	102	}
	103	}
	104
	105
c40d612b	106	u32 __weak get_lpuart_clk(void)
427eba70	107	{
2f8a6db5	108	return get_board_sys_clk();
c40d612b PF	109	}
c40d612b PF	110
af325e95	111	#if CONFIG_IS_ENABLED(CLK)
1e635a31	112	static int get_lpuart_clk_rate(struct udevice dev, u32 clk_rate)
8f5b6299	113	{
1e635a31 PF	114	struct lpuart_serial_plat *plat = dev_get_plat(dev);
1e635a31 PF	115	struct clk clk;
8f5b6299 PF	116	ulong rate;
8f5b6299 PF	117	int ret;
1e635a31	118	char *name;
8f5b6299	119
1e635a31 PF	120	if (plat->devtype == DEV_MX7ULP)
	121	name = "ipg";
	122	else
	123	name = "per";
	124
	125	ret = clk_get_by_name(dev, name, &clk);
8f5b6299	126	if (ret) {
1e635a31	127	dev_err(dev, "Failed to get clk: %d\n", ret);
8f5b6299 PF	128	return ret;
	129	}
	130
1e635a31	131	rate = clk_get_rate(&clk);
8f5b6299	132	if ((long)rate <= 0) {
1e635a31	133	dev_err(dev, "Failed to get clk rate: %ld\n", (long)rate);
8f5b6299 PF	134	return ret;
8f5b6299 PF	135	}
1e635a31	136	*clk_rate = rate;
8f5b6299 PF	137	return 0;
	138	}
	139	#else
1e635a31	140	static inline int get_lpuart_clk_rate(struct udevice dev, u32 clk_rate)
8f5b6299 PF	141	{ return -ENOSYS; }
	142	#endif
	143
c40d612b PF	144	static bool is_lpuart32(struct udevice *dev)
c40d612b PF	145	{
0fd3d911	146	struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b PF	147
	148	return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
	149	}
	150
8f5b6299	151	static void _lpuart_serial_setbrg(struct udevice *dev,
c40d612b PF	152	int baudrate)
c40d612b PF	153	{
8a8d24bd	154	struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b	155	struct lpuart_fsl *base = plat->reg;
8f5b6299	156	u32 clk;
427eba70	157	u16 sbr;
8f5b6299 PF	158	int ret;
8f5b6299 PF	159
af325e95	160	if (CONFIG_IS_ENABLED(CLK)) {
8f5b6299 PF	161	ret = get_lpuart_clk_rate(dev, &clk);
	162	if (ret)
	163	return;
	164	} else {
	165	clk = get_lpuart_clk();
	166	}
427eba70	167
6ca13b12	168	sbr = (u16)(clk / (16 * baudrate));
427eba70	169
47f1bfca	170	/* place adjustment later - n/32 BRFA */
427eba70 AW	171	__raw_writeb(sbr >> 8, &base->ubdh);
	172	__raw_writeb(sbr & 0xff, &base->ubdl);
	173	}
	174
8a8d24bd	175	static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
427eba70	176	{
c40d612b	177	struct lpuart_fsl *base = plat->reg;
1138bbe0 T	178	if (!(__raw_readb(&base->us1) & (US1_RDRF \| US1_OR)))
1138bbe0 T	179	return -EAGAIN;
427eba70	180
a3db78d8	181	barrier();
427eba70 AW	182
	183	return __raw_readb(&base->ud);
	184	}
	185
1138bbe0	186	static int _lpuart_serial_putc(struct lpuart_serial_plat *plat,
c40d612b	187	const char c)
427eba70	188	{
c40d612b PF	189	struct lpuart_fsl *base = plat->reg;
c40d612b PF	190
1138bbe0 T	191	if (!(__raw_readb(&base->us1) & US1_TDRE))
1138bbe0 T	192	return -EAGAIN;
427eba70 AW	193
427eba70 AW	194	__raw_writeb(c, &base->ud);
1138bbe0	195	return 0;
427eba70 AW	196	}
427eba70 AW	197
47f1bfca	198	/* Test whether a character is in the RX buffer */
8a8d24bd	199	static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat)
427eba70	200	{
c40d612b PF	201	struct lpuart_fsl *base = plat->reg;
c40d612b PF	202
427eba70 AW	203	if (__raw_readb(&base->urcfifo) == 0)
	204	return 0;
	205
	206	return 1;
	207	}
	208
	209	/*
	210	* Initialise the serial port with the given baudrate. The settings
	211	* are always 8 data bits, no parity, 1 stop bit, no start bits.
	212	*/
8f5b6299	213	static int _lpuart_serial_init(struct udevice *dev)
427eba70	214	{
8a8d24bd	215	struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b	216	struct lpuart_fsl base = (struct lpuart_fsl )plat->reg;
427eba70 AW	217	u8 ctrl;
	218
	219	ctrl = __raw_readb(&base->uc2);
	220	ctrl &= ~UC2_RE;
	221	ctrl &= ~UC2_TE;
	222	__raw_writeb(ctrl, &base->uc2);
	223
	224	__raw_writeb(0, &base->umodem);
	225	__raw_writeb(0, &base->uc1);
	226
89e69fd4 SA	227	/* Disable FIFO and flush buffer */
	228	__raw_writeb(0x0, &base->upfifo);
	229	__raw_writeb(0x0, &base->utwfifo);
	230	__raw_writeb(0x1, &base->urwfifo);
	231	__raw_writeb(CFIFO_TXFLUSH \| CFIFO_RXFLUSH, &base->ucfifo);
	232
427eba70	233	/* provide data bits, parity, stop bit, etc */
8f5b6299	234	_lpuart_serial_setbrg(dev, gd->baudrate);
427eba70 AW	235
	236	__raw_writeb(UC2_RE \| UC2_TE, &base->uc2);
	237
	238	return 0;
	239	}
	240
8f5b6299	241	static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
7edf5c45 PF	242	int baudrate)
7edf5c45 PF	243	{
8a8d24bd	244	struct lpuart_serial_plat *plat = dev_get_plat(dev);
7edf5c45 PF	245	struct lpuart_fsl_reg32 *base = plat->reg;
7edf5c45 PF	246	u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
8f5b6299 PF	247	u32 clk;
	248	int ret;
	249
af325e95	250	if (CONFIG_IS_ENABLED(CLK)) {
8f5b6299 PF	251	ret = get_lpuart_clk_rate(dev, &clk);
	252	if (ret)
	253	return;
	254	} else {
	255	clk = get_lpuart_clk();
	256	}
7edf5c45 PF	257
	258	baud_diff = baudrate;
	259	osr = 0;
	260	sbr = 0;
	261
	262	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
	263	tmp_sbr = (clk / (baudrate * tmp_osr));
	264
	265	if (tmp_sbr == 0)
	266	tmp_sbr = 1;
	267
	268	/calculate difference in actual buad w/ current values /
	269	tmp_diff = (clk / (tmp_osr * tmp_sbr));
	270	tmp_diff = tmp_diff - baudrate;
	271
	272	/* select best values between sbr and sbr+1 */
	273	if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
	274	tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
	275	tmp_sbr++;
	276	}
	277
	278	if (tmp_diff <= baud_diff) {
	279	baud_diff = tmp_diff;
	280	osr = tmp_osr;
	281	sbr = tmp_sbr;
	282	}
	283	}
	284
	285	/*
	286	* TODO: handle buadrate outside acceptable rate
	287	* if (baudDiff > ((config->baudRate_Bps / 100) * 3))
	288	* {
	289	* Unacceptable baud rate difference of more than 3%
	290	* return kStatus_LPUART_BaudrateNotSupport;
	291	* }
	292	*/
	293	tmp = in_le32(&base->baud);
	294
	295	if ((osr > 3) && (osr < 8))
	296	tmp \|= LPUART_BAUD_BOTHEDGE_MASK;
	297
	298	tmp &= ~LPUART_BAUD_OSR_MASK;
	299	tmp \|= LPUART_BAUD_OSR(osr-1);
	300
	301	tmp &= ~LPUART_BAUD_SBR_MASK;
	302	tmp \|= LPUART_BAUD_SBR(sbr);
	303
	304	/* explicitly disable 10 bit mode & set 1 stop bit */
	305	tmp &= ~(LPUART_BAUD_M10_MASK \| LPUART_BAUD_SBNS_MASK);
	306
	307	out_le32(&base->baud, tmp);
	308	}
	309
8f5b6299	310	static void _lpuart32_serial_setbrg(struct udevice *dev,
c40d612b	311	int baudrate)
6209e14c	312	{
8a8d24bd	313	struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b	314	struct lpuart_fsl_reg32 *base = plat->reg;
8f5b6299	315	u32 clk;
6209e14c	316	u32 sbr;
8f5b6299 PF	317	int ret;
8f5b6299 PF	318
af325e95	319	if (CONFIG_IS_ENABLED(CLK)) {
8f5b6299 PF	320	ret = get_lpuart_clk_rate(dev, &clk);
	321	if (ret)
	322	return;
	323	} else {
	324	clk = get_lpuart_clk();
	325	}
6209e14c	326
6ca13b12	327	sbr = (clk / (16 * baudrate));
6209e14c	328
47f1bfca	329	/* place adjustment later - n/32 BRFA */
c40d612b	330	lpuart_write32(plat->flags, &base->baud, sbr);
6209e14c JL	331	}
6209e14c JL	332
8a8d24bd	333	static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
6209e14c	334	{
c40d612b	335	struct lpuart_fsl_reg32 *base = plat->reg;
7edf5c45	336	u32 stat, val;
6209e14c	337
c40d612b	338	lpuart_read32(plat->flags, &base->stat, &stat);
1138bbe0	339	if ((stat & STAT_RDRF) == 0) {
c40d612b	340	lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
1138bbe0	341	return -EAGAIN;
6209e14c JL	342	}
6209e14c JL	343
7edf5c45	344	lpuart_read32(plat->flags, &base->data, &val);
c40d612b	345
a2bbfc54 SD	346	lpuart_read32(plat->flags, &base->stat, &stat);
	347	if (stat & STAT_OR)
	348	lpuart_write32(plat->flags, &base->stat, STAT_OR);
7edf5c45 PF	349
7edf5c45 PF	350	return val & 0x3ff;
6209e14c JL	351	}
6209e14c JL	352
1138bbe0	353	static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
c40d612b	354	const char c)
6209e14c	355	{
c40d612b PF	356	struct lpuart_fsl_reg32 *base = plat->reg;
	357	u32 stat;
	358
1138bbe0 T	359	lpuart_read32(plat->flags, &base->stat, &stat);
	360	if (!(stat & STAT_TDRE))
	361	return -EAGAIN;
6209e14c	362
c40d612b	363	lpuart_write32(plat->flags, &base->data, c);
1138bbe0	364	return 0;
6209e14c JL	365	}
6209e14c JL	366
47f1bfca	367	/* Test whether a character is in the RX buffer */
8a8d24bd	368	static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
6209e14c	369	{
c40d612b PF	370	struct lpuart_fsl_reg32 *base = plat->reg;
	371	u32 water;
	372
	373	lpuart_read32(plat->flags, &base->water, &water);
	374
	375	if ((water >> 24) == 0)
6209e14c JL	376	return 0;
	377
	378	return 1;
	379	}
	380
	381	/*
	382	* Initialise the serial port with the given baudrate. The settings
	383	* are always 8 data bits, no parity, 1 stop bit, no start bits.
	384	*/
8f5b6299	385	static int _lpuart32_serial_init(struct udevice *dev)
6209e14c	386	{
8a8d24bd	387	struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b	388	struct lpuart_fsl_reg32 base = (struct lpuart_fsl_reg32 )plat->reg;
cdc16f61	389	u32 val, tx_fifo_size;
6209e14c	390
cdc16f61 YL	391	lpuart_read32(plat->flags, &base->ctrl, &val);
	392	val &= ~CTRL_RE;
	393	val &= ~CTRL_TE;
	394	lpuart_write32(plat->flags, &base->ctrl, val);
6209e14c	395
c40d612b	396	lpuart_write32(plat->flags, &base->modir, 0);
cdc16f61 YL	397
	398	lpuart_read32(plat->flags, &base->fifo, &val);
	399	tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
	400	/* Set the TX water to half of FIFO size */
	401	if (tx_fifo_size > 1)
	402	tx_fifo_size = tx_fifo_size >> 1;
	403
	404	/* Set RX water to 0, to be triggered by any receive data */
	405	lpuart_write32(plat->flags, &base->water,
	406	(tx_fifo_size << WATER_TXWATER_OFF));
	407
	408	/* Enable TX and RX FIFO */
	409	val \|= (FIFO_TXFE \| FIFO_RXFE \| FIFO_TXFLUSH \| FIFO_RXFLUSH);
	410	lpuart_write32(plat->flags, &base->fifo, val);
6209e14c	411
c40d612b	412	lpuart_write32(plat->flags, &base->match, 0);
6209e14c	413
c32449a1 GB	414	if (plat->devtype == DEV_MX7ULP \|\| plat->devtype == DEV_IMX8 \|\|
c32449a1 GB	415	plat->devtype == DEV_IMXRT) {
8f5b6299	416	_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
7edf5c45 PF	417	} else {
7edf5c45 PF	418	/* provide data bits, parity, stop bit, etc */
8f5b6299	419	_lpuart32_serial_setbrg(dev, gd->baudrate);
7edf5c45	420	}
6209e14c	421
c40d612b	422	lpuart_write32(plat->flags, &base->ctrl, CTRL_RE \| CTRL_TE);
6209e14c JL	423
	424	return 0;
	425	}
	426
c40d612b	427	static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
fdbae099	428	{
8a8d24bd	429	struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099	430
7edf5c45	431	if (is_lpuart32(dev)) {
c32449a1 GB	432	if (plat->devtype == DEV_MX7ULP \|\| plat->devtype == DEV_IMX8 \|\|
c32449a1 GB	433	plat->devtype == DEV_IMXRT)
8f5b6299	434	_lpuart32_serial_setbrg_7ulp(dev, baudrate);
7edf5c45	435	else
8f5b6299	436	_lpuart32_serial_setbrg(dev, baudrate);
7edf5c45	437	} else {
8f5b6299	438	_lpuart_serial_setbrg(dev, baudrate);
7edf5c45	439	}
fdbae099 BM	440
	441	return 0;
	442	}
	443
c40d612b	444	static int lpuart_serial_getc(struct udevice *dev)
fdbae099	445	{
0fd3d911	446	struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099	447
c40d612b PF	448	if (is_lpuart32(dev))
	449	return _lpuart32_serial_getc(plat);
	450
	451	return _lpuart_serial_getc(plat);
fdbae099 BM	452	}
fdbae099 BM	453
c40d612b	454	static int lpuart_serial_putc(struct udevice *dev, const char c)
fdbae099	455	{
0fd3d911	456	struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099	457
c40d612b	458	if (is_lpuart32(dev))
1138bbe0	459	return _lpuart32_serial_putc(plat, c);
fdbae099	460
1138bbe0	461	return _lpuart_serial_putc(plat, c);
fdbae099 BM	462	}
fdbae099 BM	463
c40d612b	464	static int lpuart_serial_pending(struct udevice *dev, bool input)
fdbae099	465	{
0fd3d911	466	struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099	467	struct lpuart_fsl *reg = plat->reg;
c40d612b PF	468	struct lpuart_fsl_reg32 *reg32 = plat->reg;
	469	u32 stat;
	470
	471	if (is_lpuart32(dev)) {
	472	if (input) {
	473	return _lpuart32_serial_tstc(plat);
	474	} else {
	475	lpuart_read32(plat->flags, &reg32->stat, &stat);
	476	return stat & STAT_TDRE ? 0 : 1;
	477	}
	478	}
fdbae099 BM	479
fdbae099 BM	480	if (input)
c40d612b	481	return _lpuart_serial_tstc(plat);
fdbae099	482	else
c40d612b	483	return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
fdbae099 BM	484	}
fdbae099 BM	485
c40d612b	486	static int lpuart_serial_probe(struct udevice *dev)
fdbae099	487	{
55631db8	488	#if CONFIG_IS_ENABLED(CLK)
1e635a31	489	struct lpuart_serial_plat *plat = dev_get_plat(dev);
55631db8	490	struct clk per_clk;
cc7df0b9	491	struct clk ipg_clk;
55631db8 GB	492	int ret;
55631db8 GB	493
1e635a31 PF	494	if (plat->devtype != DEV_MX7ULP) {
	495	ret = clk_get_by_name(dev, "per", &per_clk);
	496	if (!ret) {
	497	ret = clk_enable(&per_clk);
	498	if (ret) {
	499	dev_err(dev, "Failed to enable per clk: %d\n", ret);
	500	return ret;
	501	}
	502	} else {
	503	debug("%s: Failed to get per clk: %d\n", __func__, ret);
55631db8	504	}
55631db8	505	}
cc7df0b9 YL	506
	507	ret = clk_get_by_name(dev, "ipg", &ipg_clk);
	508	if (!ret) {
	509	ret = clk_enable(&ipg_clk);
	510	if (ret) {
	511	dev_err(dev, "Failed to enable ipg clk: %d\n", ret);
	512	return ret;
	513	}
	514	} else {
	515	debug("%s: Failed to get ipg clk: %d\n", __func__, ret);
	516	}
55631db8 GB	517	#endif
55631db8 GB	518
c40d612b	519	if (is_lpuart32(dev))
8f5b6299	520	return _lpuart32_serial_init(dev);
c40d612b	521	else
8f5b6299	522	return _lpuart_serial_init(dev);
fdbae099	523	}
427eba70	524
d1998a9f	525	static int lpuart_serial_of_to_plat(struct udevice *dev)
fdbae099	526	{
0fd3d911	527	struct lpuart_serial_plat *plat = dev_get_plat(dev);
7edf5c45	528	const void *blob = gd->fdt_blob;
da409ccc	529	int node = dev_of_offset(dev);
fdbae099 BM	530	fdt_addr_t addr;
fdbae099 BM	531
2548493a	532	addr = dev_read_addr(dev);
fdbae099 BM	533	if (addr == FDT_ADDR_T_NONE)
	534	return -EINVAL;
	535
c40d612b PF	536	plat->reg = (void *)addr;
c40d612b PF	537	plat->flags = dev_get_driver_data(dev);
fdbae099	538
1edc5688 VS	539	if (fdtdec_get_bool(blob, node, "little-endian"))
	540	plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
	541
7edf5c45 PF	542	if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
	543	plat->devtype = DEV_LS1021A;
	544	else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
	545	plat->devtype = DEV_MX7ULP;
	546	else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
	547	plat->devtype = DEV_VF610;
126f8849 PF	548	else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
126f8849 PF	549	plat->devtype = DEV_IMX8;
c32449a1 GB	550	else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
c32449a1 GB	551	plat->devtype = DEV_IMXRT;
7edf5c45	552
fdbae099 BM	553	return 0;
	554	}
	555
fdbae099 BM	556	static const struct dm_serial_ops lpuart_serial_ops = {
	557	.putc = lpuart_serial_putc,
	558	.pending = lpuart_serial_pending,
	559	.getc = lpuart_serial_getc,
	560	.setbrg = lpuart_serial_setbrg,
	561	};
	562
	563	static const struct udevice_id lpuart_serial_ids[] = {
c40d612b PF	564	{ .compatible = "fsl,ls1021a-lpuart", .data =
c40d612b PF	565	LPUART_FLAG_REGMAP_32BIT_REG \| LPUART_FLAG_REGMAP_ENDIAN_BIG },
c9bf9af9 MW	566	{ .compatible = "fsl,ls1028a-lpuart",
c9bf9af9 MW	567	.data = LPUART_FLAG_REGMAP_32BIT_REG },
7edf5c45 PF	568	{ .compatible = "fsl,imx7ulp-lpuart",
7edf5c45 PF	569	.data = LPUART_FLAG_REGMAP_32BIT_REG },
c40d612b	570	{ .compatible = "fsl,vf610-lpuart"},
126f8849 PF	571	{ .compatible = "fsl,imx8qm-lpuart",
126f8849 PF	572	.data = LPUART_FLAG_REGMAP_32BIT_REG },
c32449a1 GB	573	{ .compatible = "fsl,imxrt-lpuart",
c32449a1 GB	574	.data = LPUART_FLAG_REGMAP_32BIT_REG },
fdbae099 BM	575	{ }
	576	};
	577
	578	U_BOOT_DRIVER(serial_lpuart) = {
	579	.name = "serial_lpuart",
	580	.id = UCLASS_SERIAL,
	581	.of_match = lpuart_serial_ids,
d1998a9f	582	.of_to_plat = lpuart_serial_of_to_plat,
8a8d24bd	583	.plat_auto = sizeof(struct lpuart_serial_plat),
fdbae099 BM	584	.probe = lpuart_serial_probe,
fdbae099 BM	585	.ops = &lpuart_serial_ops,
fdbae099	586	};