[thirdparty/u-boot.git] / drivers / serial / serial_mpc8xx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 */

#include <common.h>
#include <command.h>
#include <dm.h>
#include <serial.h>
#include <watchdog.h>
#include <asm/cpm_8xx.h>
#include <asm/global_data.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_8xx_CONS_SMC1)	/* Console on SMC1 */
#define	SMC_INDEX	0
#define PROFF_SMC	PROFF_SMC1
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
#define IOPINS		0xc0

#elif defined(CONFIG_8xx_CONS_SMC2)	/* Console on SMC2 */
#define SMC_INDEX	1
#define PROFF_SMC	PROFF_SMC2
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC2
#define IOPINS		0xc00

#endif /* CONFIG_8xx_CONS_SMCx */

struct serialbuffer {
	cbd_t	rxbd;		/* Rx BD */
	cbd_t	txbd;		/* Tx BD */
	uint	rxindex;	/* index for next character to read */
	uchar	rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	uchar	txbuf;	/* tx buffers */
};

static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
{
	int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;

	if (divisor / 16 > 0x1000) {
		/* bad divisor, assume 50MHz clock and 9600 baud */
		divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
	}

	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;

	if (divisor <= 0x1000)
		out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
	else
		out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
			 CPM_BRG_DIV16);
}

/*
 * Minimal serial functions needed to use one of the SMC ports
 * as serial console interface.
 */

static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
{
	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t __iomem *cp = &(im->im_cpm);

	/* Set up the baud rate generator.
	 * See 8xx_io/commproc.c for details.
	 *
	 * Wire BRG1 to SMCx
	 */

	out_be32(&cp->cp_simode, 0);

	serial_setdivisor(cp, baudrate);

	return 0;
}

static int serial_mpc8xx_probe(struct udevice *dev)
{
	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	smc_t __iomem *sp;
	smc_uart_t __iomem *up;
	u16 smc_rpbase;
	cpm8xx_t __iomem *cp = &(im->im_cpm);
	struct serialbuffer __iomem *rtx;

	/* initialize pointers to SMC */

	sp = cp->cp_smc + SMC_INDEX;
	up = (smc_uart_t __iomem *)&cp->cp_dpmem[PROFF_SMC];

	smc_rpbase = in_be16(&up->smc_rpbase);
	if (smc_rpbase)
		up = (smc_uart_t __iomem *)&cp->cp_dpmem[smc_rpbase];

	/* Disable transmitter/receiver. */
	clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	/* Enable SDMA. */
	out_be32(&im->im_siu_conf.sc_sdcr, 1);

	/* clear error conditions */
	out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);

	/* clear SDMA interrupt mask */
	out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);

	/* Use Port B for SMCx instead of other functions. */
	setbits_be32(&cp->cp_pbpar, IOPINS);
	clrbits_be32(&cp->cp_pbdir, IOPINS);
	clrbits_be16(&cp->cp_pbodr, IOPINS);

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
	/* Allocate space for two buffer descriptors in the DP ram.
	 * For now, this address seems OK, but it may have to
	 * change with newer versions of the firmware.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
	out_be16(&rtx->rxbd.cbd_sc, 0);

	out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
	out_be16(&rtx->txbd.cbd_sc, 0);

	/* Set up the uart parameters in the parameter ram. */
	out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
	out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
	out_8(&up->smc_rfcr, SMC_EB);
	out_8(&up->smc_tfcr, SMC_EB);

	/* Set UART mode, 8 bit, no parity, one stop.
	 * Enable receive and transmit.
	 */
	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);

	/* Mask all interrupts and remove anything pending.
	*/
	out_8(&sp->smc_smcm, 0);
	out_8(&sp->smc_smce, 0xff);

	/* Set up the baud rate generator */
	serial_mpc8xx_setbrg(dev, gd->baudrate);

	/* Make the first buffer the only buffer. */
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);

	/* single/multi character receive. */
	out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
	out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
	out_be32(&rtx->rxindex, 0);

	out_be32(&up->smc_rstate, 0);
	out_be32(&up->smc_tstate, 0);
	out_be16(&up->smc_rbptr, CPM_SERIAL_BASE);
	out_be16(&up->smc_tbptr, CPM_SERIAL_BASE + sizeof(cbd_t));
	out_be16(&up->smc_brkcr, 1);
	out_be16(&up->smc_brkec, 0);

	/* Enable transmitter/receiver.	*/
	setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	return 0;
}

static int serial_mpc8xx_putc(struct udevice *dev, const char c)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
		return -EAGAIN;

	out_8(&rtx->txbuf, c);
	out_be16(&rtx->txbd.cbd_datlen, 1);
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);

	return 0;
}

static int serial_mpc8xx_getc(struct udevice *dev)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;
	unsigned char  c;
	uint rxindex;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
		return -EAGAIN;

	/* the characters are read one by one,
	 * use the rxindex to know the next char to deliver
	 */
	rxindex = in_be32(&rtx->rxindex);
	c = in_8(rtx->rxbuf + rxindex);
	rxindex++;

	/* check if all char are readout, then make prepare for next receive */
	if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
		rxindex = 0;
		setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
	}
	out_be32(&rtx->rxindex, rxindex);
	return c;
}

static int serial_mpc8xx_pending(struct udevice *dev, bool input)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;

	if (!input)
		return 0;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}

static const struct dm_serial_ops serial_mpc8xx_ops = {
	.putc = serial_mpc8xx_putc,
	.pending = serial_mpc8xx_pending,
	.getc = serial_mpc8xx_getc,
	.setbrg = serial_mpc8xx_setbrg,
};

static const struct udevice_id serial_mpc8xx_ids[] = {
	{ .compatible = "fsl,pq1-smc" },
	{ }
};

U_BOOT_DRIVER(serial_mpc8xx) = {
	.name	= "serial_mpc8xx",
	.id	= UCLASS_SERIAL,
	.of_match = serial_mpc8xx_ids,
	.probe = serial_mpc8xx_probe,
	.ops	= &serial_mpc8xx_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
907208c4 CL	2	/*
	3	* (C) Copyright 2000
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
907208c4 CL	5	*/
907208c4 CL	6
d678a59d	7	#include <common.h>
907208c4	8	#include <command.h>
bdfa11eb	9	#include <dm.h>
907208c4 CL	10	#include <serial.h>
907208c4 CL	11	#include <watchdog.h>
18f8d4c6	12	#include <asm/cpm_8xx.h>
401d1c4f	13	#include <asm/global_data.h>
907208c4 CL	14	#include <linux/compiler.h>
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
907208c4 CL	18	#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
	19	#define SMC_INDEX 0
	20	#define PROFF_SMC PROFF_SMC1
	21	#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
ba3da734	22	#define IOPINS 0xc0
907208c4 CL	23
	24	#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
	25	#define SMC_INDEX 1
	26	#define PROFF_SMC PROFF_SMC2
	27	#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
ba3da734	28	#define IOPINS 0xc00
907208c4 CL	29
	30	#endif /* CONFIG_8xx_CONS_SMCx */
	31
ba3da734	32	struct serialbuffer {
907208c4 CL	33	cbd_t rxbd; /* Rx BD */
	34	cbd_t txbd; /* Tx BD */
	35	uint rxindex; /* index for next character to read */
ba3da734 CL	36	uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	37	uchar txbuf; /* tx buffers */
	38	};
907208c4	39
bdfa11eb	40	static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
907208c4	41	{
bdfa11eb	42	int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;
907208c4	43
70fd0710	44	if (divisor / 16 > 0x1000) {
907208c4	45	/* bad divisor, assume 50MHz clock and 9600 baud */
70fd0710	46	divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
907208c4 CL	47	}
907208c4 CL	48
907208c4	49	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
907208c4	50
ba3da734 CL	51	if (divisor <= 0x1000)
	52	out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) \| CPM_BRG_EN);
	53	else
	54	out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) \| CPM_BRG_EN \|
	55	CPM_BRG_DIV16);
907208c4 CL	56	}
	57
	58	/*
	59	* Minimal serial functions needed to use one of the SMC ports
	60	* as serial console interface.
	61	*/
	62
42b54013	63	static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
907208c4	64	{
ba3da734 CL	65	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
ba3da734 CL	66	cpm8xx_t __iomem *cp = &(im->im_cpm);
907208c4 CL	67
	68	/* Set up the baud rate generator.
	69	* See 8xx_io/commproc.c for details.
	70	*
	71	* Wire BRG1 to SMCx
	72	*/
	73
ba3da734	74	out_be32(&cp->cp_simode, 0);
907208c4	75
42b54013 CL	76	serial_setdivisor(cp, baudrate);
	77
	78	return 0;
907208c4 CL	79	}
907208c4 CL	80
42b54013	81	static int serial_mpc8xx_probe(struct udevice *dev)
907208c4	82	{
ba3da734 CL	83	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	84	smc_t __iomem *sp;
	85	smc_uart_t __iomem *up;
388cb1a1	86	u16 smc_rpbase;
ba3da734 CL	87	cpm8xx_t __iomem *cp = &(im->im_cpm);
ba3da734 CL	88	struct serialbuffer __iomem *rtx;
907208c4 CL	89
	90	/* initialize pointers to SMC */
	91
ba3da734	92	sp = cp->cp_smc + SMC_INDEX;
fdd243d8	93	up = (smc_uart_t __iomem *)&cp->cp_dpmem[PROFF_SMC];
388cb1a1 CL	94
	95	smc_rpbase = in_be16(&up->smc_rpbase);
	96	if (smc_rpbase)
	97	up = (smc_uart_t __iomem *)&cp->cp_dpmem[smc_rpbase];
907208c4 CL	98
907208c4 CL	99	/* Disable transmitter/receiver. */
ba3da734	100	clrbits_be16(&sp->smc_smcmr, SMCMR_REN \| SMCMR_TEN);
907208c4 CL	101
907208c4 CL	102	/* Enable SDMA. */
ba3da734	103	out_be32(&im->im_siu_conf.sc_sdcr, 1);
907208c4 CL	104
907208c4 CL	105	/* clear error conditions */
ba3da734	106	out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
907208c4 CL	107
907208c4 CL	108	/* clear SDMA interrupt mask */
ba3da734	109	out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
907208c4	110
ba3da734 CL	111	/* Use Port B for SMCx instead of other functions. */
	112	setbits_be32(&cp->cp_pbpar, IOPINS);
	113	clrbits_be32(&cp->cp_pbdir, IOPINS);
	114	clrbits_be16(&cp->cp_pbodr, IOPINS);
907208c4 CL	115
	116	/* Set the physical address of the host memory buffers in
	117	* the buffer descriptors.
	118	*/
ba3da734	119	rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
907208c4 CL	120	/* Allocate space for two buffer descriptors in the DP ram.
	121	* For now, this address seems OK, but it may have to
	122	* change with newer versions of the firmware.
	123	* damm: allocating space after the two buffers for rx/tx data
	124	*/
	125
ba3da734 CL	126	out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
ba3da734 CL	127	out_be16(&rtx->rxbd.cbd_sc, 0);
907208c4	128
ba3da734 CL	129	out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
ba3da734 CL	130	out_be16(&rtx->txbd.cbd_sc, 0);
907208c4 CL	131
907208c4 CL	132	/* Set up the uart parameters in the parameter ram. */
ba3da734 CL	133	out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
	134	out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
	135	out_8(&up->smc_rfcr, SMC_EB);
	136	out_8(&up->smc_tfcr, SMC_EB);
907208c4 CL	137
	138	/* Set UART mode, 8 bit, no parity, one stop.
	139	* Enable receive and transmit.
	140	*/
ba3da734	141	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) \| SMCMR_SM_UART);
907208c4 CL	142
	143	/* Mask all interrupts and remove anything pending.
	144	*/
ba3da734 CL	145	out_8(&sp->smc_smcm, 0);
ba3da734 CL	146	out_8(&sp->smc_smce, 0xff);
907208c4 CL	147
907208c4 CL	148	/* Set up the baud rate generator */
42b54013	149	serial_mpc8xx_setbrg(dev, gd->baudrate);
907208c4 CL	150
907208c4 CL	151	/* Make the first buffer the only buffer. */
ba3da734 CL	152	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
ba3da734 CL	153	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY \| BD_SC_WRAP);
907208c4 CL	154
907208c4 CL	155	/* single/multi character receive. */
ba3da734 CL	156	out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
	157	out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
	158	out_be32(&rtx->rxindex, 0);
907208c4	159
388cb1a1 CL	160	out_be32(&up->smc_rstate, 0);
	161	out_be32(&up->smc_tstate, 0);
	162	out_be16(&up->smc_rbptr, CPM_SERIAL_BASE);
	163	out_be16(&up->smc_tbptr, CPM_SERIAL_BASE + sizeof(cbd_t));
	164	out_be16(&up->smc_brkcr, 1);
	165	out_be16(&up->smc_brkec, 0);
907208c4 CL	166
907208c4 CL	167	/* Enable transmitter/receiver. */
ba3da734	168	setbits_be16(&sp->smc_smcmr, SMCMR_REN \| SMCMR_TEN);
907208c4	169
70fd0710	170	return 0;
907208c4 CL	171	}
907208c4 CL	172
42b54013	173	static int serial_mpc8xx_putc(struct udevice *dev, const char c)
907208c4	174	{
ba3da734 CL	175	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	176	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	177	struct serialbuffer __iomem *rtx;
907208c4	178
ba3da734	179	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4	180
1138bbe0 T	181	if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
	182	return -EAGAIN;
	183
ba3da734 CL	184	out_8(&rtx->txbuf, c);
	185	out_be16(&rtx->txbd.cbd_datlen, 1);
	186	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
907208c4	187
42b54013	188	return 0;
907208c4 CL	189	}
907208c4 CL	190
42b54013	191	static int serial_mpc8xx_getc(struct udevice *dev)
907208c4	192	{
ba3da734 CL	193	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	194	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	195	struct serialbuffer __iomem *rtx;
907208c4	196	unsigned char c;
ba3da734	197	uint rxindex;
907208c4	198
ba3da734	199	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4	200
1138bbe0 T	201	if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
1138bbe0 T	202	return -EAGAIN;
907208c4 CL	203
	204	/* the characters are read one by one,
	205	* use the rxindex to know the next char to deliver
	206	*/
ba3da734 CL	207	rxindex = in_be32(&rtx->rxindex);
	208	c = in_8(rtx->rxbuf + rxindex);
	209	rxindex++;
907208c4 CL	210
907208c4 CL	211	/* check if all char are readout, then make prepare for next receive */
ba3da734 CL	212	if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
	213	rxindex = 0;
	214	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
907208c4	215	}
ba3da734	216	out_be32(&rtx->rxindex, rxindex);
70fd0710	217	return c;
907208c4 CL	218	}
907208c4 CL	219
42b54013	220	static int serial_mpc8xx_pending(struct udevice *dev, bool input)
907208c4	221	{
ba3da734 CL	222	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	223	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	224	struct serialbuffer __iomem *rtx;
907208c4	225
42b54013 CL	226	if (!input)
	227	return 0;
	228
ba3da734	229	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4	230
ba3da734	231	return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
907208c4 CL	232	}
907208c4 CL	233
bdfa11eb CL	234	static const struct dm_serial_ops serial_mpc8xx_ops = {
	235	.putc = serial_mpc8xx_putc,
	236	.pending = serial_mpc8xx_pending,
	237	.getc = serial_mpc8xx_getc,
	238	.setbrg = serial_mpc8xx_setbrg,
	239	};
	240
	241	static const struct udevice_id serial_mpc8xx_ids[] = {
	242	{ .compatible = "fsl,pq1-smc" },
	243	{ }
	244	};
	245
	246	U_BOOT_DRIVER(serial_mpc8xx) = {
	247	.name = "serial_mpc8xx",
	248	.id = UCLASS_SERIAL,
	249	.of_match = serial_mpc8xx_ids,
	250	.probe = serial_mpc8xx_probe,
	251	.ops = &serial_mpc8xx_ops,
	252	.flags = DM_FLAG_PRE_RELOC,
	253	};