[thirdparty/u-boot.git] / drivers / spi / cf_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * Support for DM and DT, non-DM code removed.
 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
 *
 * TODO: fsl_dspi.c should work as a driver for the DSPI module.
 */

#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/global_data.h>
#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
#include <asm/coldfire/dspi.h>
#include <asm/io.h>

struct coldfire_spi_priv {
	struct dspi *regs;
	uint baudrate;
	int mode;
	int charbit;
};

DECLARE_GLOBAL_DATA_PTR;

#ifndef SPI_IDLE_VAL
#if defined(CONFIG_SPI_MMC)
#define SPI_IDLE_VAL	0xFFFF
#else
#define SPI_IDLE_VAL	0x0
#endif
#endif

/*
 * DSPI specific mode
 *
 * bit 31 - 28: Transfer size 3 to 16 bits
 *     27 - 26: PCS to SCK delay prescaler
 *     25 - 24: After SCK delay prescaler
 *     23 - 22: Delay after transfer prescaler
 *     21     : Allow overwrite for bit 31-22 and bit 20-8
 *     20     : Double baud rate
 *     19 - 16: PCS to SCK delay scaler
 *     15 - 12: After SCK delay scaler
 *     11 -  8: Delay after transfer scaler
 *      7 -  0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
 */
#define SPI_MODE_MOD			0x00200000
#define SPI_MODE_DBLRATE		0x00100000

#define SPI_MODE_XFER_SZ_MASK		0xf0000000
#define SPI_MODE_DLY_PRE_MASK		0x0fc00000
#define SPI_MODE_DLY_SCA_MASK		0x000fff00

#define MCF_FRM_SZ_16BIT		DSPI_CTAR_TRSZ(0xf)
#define MCF_DSPI_SPEED_BESTMATCH	0x7FFFFFFF
#define MCF_DSPI_MAX_CTAR_REGS		8

/* Default values */
#define MCF_DSPI_DEFAULT_SCK_FREQ	10000000
#define MCF_DSPI_DEFAULT_MAX_CS		4
#define MCF_DSPI_DEFAULT_MODE		0

#define MCF_DSPI_DEFAULT_CTAR		(DSPI_CTAR_TRSZ(7) | \
					DSPI_CTAR_PCSSCK_1CLK | \
					DSPI_CTAR_PASC(0) | \
					DSPI_CTAR_PDT(0) | \
					DSPI_CTAR_CSSCK(0) | \
					DSPI_CTAR_ASC(0) | \
					DSPI_CTAR_DT(1) | \
					DSPI_CTAR_BR(6))

#define MCF_CTAR_MODE_MASK		(MCF_FRM_SZ_16BIT | \
					DSPI_CTAR_PCSSCK(3) | \
					DSPI_CTAR_PASC_7CLK | \
					DSPI_CTAR_PDT(3) | \
					DSPI_CTAR_CSSCK(0x0f) | \
					DSPI_CTAR_ASC(0x0f) | \
					DSPI_CTAR_DT(0x0f))

#define setup_ctrl(ctrl, cs)	((ctrl & 0xFF000000) | ((1 << cs) << 16))

static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
			    u32 ctrl, u16 data)
{
	/*
	 * Need to check fifo level here
	 */
	while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
		;

	writel(ctrl | data, &cfspi->regs->tfr);
}

static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
{

	while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
		;

	return readw(&cfspi->regs->rfr);
}

static int coldfire_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
		return -1;

	/* Clear FIFO and resume transfer */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	dspi_chip_select(slave_plat->cs);

	return 0;
}

static int coldfire_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	/* Clear FIFO */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	dspi_chip_unselect(slave_plat->cs);

	return 0;
}

static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
			     const void *dout, void *din,
			     unsigned long flags)
{
	struct udevice *bus = dev_get_parent(dev);
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
	u8 *spi_rd = NULL, *spi_wr = NULL;
	static u32 ctrl;
	uint len = bitlen >> 3;

	if (cfspi->charbit == 16) {
		bitlen >>= 1;
		spi_wr16 = (u16 *)dout;
		spi_rd16 = (u16 *)din;
	} else {
		spi_wr = (u8 *)dout;
		spi_rd = (u8 *)din;
	}

	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
		ctrl |= DSPI_TFR_CONT;

	ctrl = setup_ctrl(ctrl, slave_plat->cs);

	if (len > 1) {
		int tmp_len = len - 1;

		while (tmp_len--) {
			if (dout) {
				if (cfspi->charbit == 16)
					cfspi_tx(cfspi, ctrl, *spi_wr16++);
				else
					cfspi_tx(cfspi, ctrl, *spi_wr++);
				cfspi_rx(cfspi);
			}

			if (din) {
				cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
				if (cfspi->charbit == 16)
					*spi_rd16++ = cfspi_rx(cfspi);
				else
					*spi_rd++ = cfspi_rx(cfspi);
			}
		}

		len = 1;	/* remaining byte */
	}

	if (flags & SPI_XFER_END)
		ctrl &= ~DSPI_TFR_CONT;

	if (len) {
		if (dout) {
			if (cfspi->charbit == 16)
				cfspi_tx(cfspi, ctrl, *spi_wr16);
			else
				cfspi_tx(cfspi, ctrl, *spi_wr);
			cfspi_rx(cfspi);
		}

		if (din) {
			cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
			if (cfspi->charbit == 16)
				*spi_rd16 = cfspi_rx(cfspi);
			else
				*spi_rd = cfspi_rx(cfspi);
		}
	} else {
		/* dummy read */
		cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
		cfspi_rx(cfspi);
	}

	return 0;
}

static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
{
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	int prescaler[] = { 2, 3, 5, 7 };
	int scaler[] = {
		2, 4, 6, 8,
		16, 32, 64, 128,
		256, 512, 1024, 2048,
		4096, 8192, 16384, 32768
	};
	int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
	int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
	u32 bus_setup;

	cfspi->baudrate = max_hz;

	/* Read current setup */
	bus_setup = readl(&dspi->ctar[dev_seq(bus)]);

	tmp = (prescaler[3] * scaler[15]);
	/* Maximum and minimum baudrate it can handle */
	if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
	    (cfspi->baudrate < (gd->bus_clk / tmp))) {
		printf("Exceed baudrate limitation: Max %d - Min %d\n",
		       (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
		return -1;
	}

	/* Activate Double Baud when it exceed 1/4 the bus clk */
	if ((bus_setup & DSPI_CTAR_DBR) ||
	    (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
		bus_setup |= DSPI_CTAR_DBR;
		dbr = 1;
	}

	/* Overwrite default value set in platform configuration file */
	if (cfspi->mode & SPI_MODE_MOD) {
		/*
		 * Check to see if it is enabled by default in platform
		 * config, or manual setting passed by mode parameter
		 */
		if (cfspi->mode & SPI_MODE_DBLRATE) {
			bus_setup |= DSPI_CTAR_DBR;
			dbr = 1;
		}
	}

	pbrcnt = sizeof(prescaler) / sizeof(int);
	brcnt = sizeof(scaler) / sizeof(int);

	/* baudrate calculation - to closer value, may not be exact match */
	for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
		baud_speed = gd->bus_clk / prescaler[i];
		for (j = 0; j < brcnt; j++) {
			tmp = (baud_speed / scaler[j]) * (1 + dbr);

			if (tmp > cfspi->baudrate)
				diff = tmp - cfspi->baudrate;
			else
				diff = cfspi->baudrate - tmp;

			if (diff < bestmatch) {
				bestmatch = diff;
				best_i = i;
				best_j = j;
			}
		}
	}

	bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
	bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
	writel(bus_setup, &dspi->ctar[dev_seq(bus)]);

	return 0;
}

static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
{
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	u32 bus_setup = 0;

	cfspi->mode = mode;

	if (cfspi->mode & SPI_CPOL)
		bus_setup |= DSPI_CTAR_CPOL;
	if (cfspi->mode & SPI_CPHA)
		bus_setup |= DSPI_CTAR_CPHA;
	if (cfspi->mode & SPI_LSB_FIRST)
		bus_setup |= DSPI_CTAR_LSBFE;

	/* Overwrite default value set in platform configuration file */
	if (cfspi->mode & SPI_MODE_MOD) {
		if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
			bus_setup |=
			    readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
		else
			bus_setup |=
			    ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);

		/* PSCSCK, PASC, PDT */
		bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
		/* CSSCK, ASC, DT */
		bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
	} else {
		bus_setup |=
			(readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
	}

	cfspi->charbit =
		((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
			MCF_FRM_SZ_16BIT) ? 16 : 8;

	setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);

	return 0;
}

static int coldfire_spi_probe(struct udevice *bus)
{
	struct coldfire_spi_plat *plat = dev_get_plat(bus);
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	int i;

	cfspi->regs = (struct dspi *)plat->regs_addr;

	cfspi->baudrate = plat->speed_hz;
	cfspi->mode = plat->mode;

	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
		unsigned int ctar = 0;

		if (plat->ctar[i][0] == 0)
			break;

		ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
			DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
			DSPI_CTAR_PASC(plat->ctar[i][2]) |
			DSPI_CTAR_PDT(plat->ctar[i][3]) |
			DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
			DSPI_CTAR_ASC(plat->ctar[i][5]) |
			DSPI_CTAR_DT(plat->ctar[i][6]) |
			DSPI_CTAR_BR(plat->ctar[i][7]);

		writel(ctar, &cfspi->regs->ctar[i]);
	}

	/* Default CTARs */
	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
		writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);

	dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
	    DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
	    DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
	    DSPI_MCR_CRXF | DSPI_MCR_CTXF;

	return 0;
}

#if CONFIG_IS_ENABLED(OF_REAL)
static int coldfire_dspi_of_to_plat(struct udevice *bus)
{
	fdt_addr_t addr;
	struct coldfire_spi_plat *plat = dev_get_plat(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);
	int *ctar, len;

	addr = dev_read_addr(bus);
	if (addr == FDT_ADDR_T_NONE)
		return -ENOMEM;

	plat->regs_addr = addr;

	plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
				      MCF_DSPI_DEFAULT_MAX_CS);

	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
					MCF_DSPI_DEFAULT_SCK_FREQ);

	plat->mode = fdtdec_get_int(blob, node, "spi-mode",
				    MCF_DSPI_DEFAULT_MODE);

	memset(plat->ctar, 0, sizeof(plat->ctar));

	ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);

	if (ctar && len) {
		int i, q, ctar_regs;

		ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;

		if (ctar_regs > MAX_CTAR_REGS)
			ctar_regs = MAX_CTAR_REGS;

		for (i = 0; i < ctar_regs; i++) {
			for (q = 0; q < MAX_CTAR_FIELDS; q++)
				plat->ctar[i][q] = *ctar++;
		}
	}

	debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
	      (void *)plat->regs_addr,
	       plat->speed_hz, plat->num_cs, plat->mode);

	return 0;
}

static const struct udevice_id coldfire_spi_ids[] = {
	{ .compatible = "fsl,mcf-dspi" },
	{ }
};
#endif

static const struct dm_spi_ops coldfire_spi_ops = {
	.claim_bus	= coldfire_spi_claim_bus,
	.release_bus	= coldfire_spi_release_bus,
	.xfer		= coldfire_spi_xfer,
	.set_speed	= coldfire_spi_set_speed,
	.set_mode	= coldfire_spi_set_mode,
};

U_BOOT_DRIVER(coldfire_spi) = {
	.name = "spi_coldfire",
	.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_REAL)
	.of_match = coldfire_spi_ids,
	.of_to_plat = coldfire_dspi_of_to_plat,
	.plat_auto	= sizeof(struct coldfire_spi_plat),
#endif
	.probe = coldfire_spi_probe,
	.ops = &coldfire_spi_ops,
	.priv_auto	= sizeof(struct coldfire_spi_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dec61c78 TL	2	/*
	3	*
	4	* (C) Copyright 2000-2003
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
	8	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5ea37664 AD	9	*
	10	* Support for DM and DT, non-DM code removed.
	11	* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
	12	*
	13	* TODO: fsl_dspi.c should work as a driver for the DSPI module.
dec61c78 TL	14	*/
dec61c78 TL	15
d678a59d	16	#include <common.h>
5ea37664	17	#include <dm.h>
f7ae49fc	18	#include <log.h>
401d1c4f	19	#include <asm/global_data.h>
5ea37664	20	#include <dm/platform_data/spi_coldfire.h>
dec61c78 TL	21	#include <spi.h>
dec61c78 TL	22	#include <malloc.h>
5ea37664 AD	23	#include <asm/coldfire/dspi.h>
5ea37664 AD	24	#include <asm/io.h>
dec61c78	25
5ea37664 AD	26	struct coldfire_spi_priv {
5ea37664 AD	27	struct dspi *regs;
dec61c78	28	uint baudrate;
5ea37664	29	int mode;
dec61c78 TL	30	int charbit;
	31	};
	32
dec61c78 TL	33	DECLARE_GLOBAL_DATA_PTR;
dec61c78 TL	34
648d675a	35	#ifndef SPI_IDLE_VAL
b97e0cd7	36	#if defined(CONFIG_SPI_MMC)
648d675a	37	#define SPI_IDLE_VAL 0xFFFF
b97e0cd7	38	#else
648d675a	39	#define SPI_IDLE_VAL 0x0
b97e0cd7 WW	40	#endif
	41	#endif
	42
5ea37664 AD	43	/*
	44	* DSPI specific mode
	45	*
	46	* bit 31 - 28: Transfer size 3 to 16 bits
	47	* 27 - 26: PCS to SCK delay prescaler
	48	* 25 - 24: After SCK delay prescaler
	49	* 23 - 22: Delay after transfer prescaler
	50	* 21 : Allow overwrite for bit 31-22 and bit 20-8
	51	* 20 : Double baud rate
	52	* 19 - 16: PCS to SCK delay scaler
	53	* 15 - 12: After SCK delay scaler
	54	* 11 - 8: Delay after transfer scaler
	55	* 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
	56	*/
	57	#define SPI_MODE_MOD 0x00200000
	58	#define SPI_MODE_DBLRATE 0x00100000
	59
	60	#define SPI_MODE_XFER_SZ_MASK 0xf0000000
	61	#define SPI_MODE_DLY_PRE_MASK 0x0fc00000
	62	#define SPI_MODE_DLY_SCA_MASK 0x000fff00
	63
	64	#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
	65	#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
	66	#define MCF_DSPI_MAX_CTAR_REGS 8
	67
	68	/* Default values */
	69	#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
	70	#define MCF_DSPI_DEFAULT_MAX_CS 4
	71	#define MCF_DSPI_DEFAULT_MODE 0
	72
	73	#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) \| \
	74	DSPI_CTAR_PCSSCK_1CLK \| \
	75	DSPI_CTAR_PASC(0) \| \
	76	DSPI_CTAR_PDT(0) \| \
	77	DSPI_CTAR_CSSCK(0) \| \
	78	DSPI_CTAR_ASC(0) \| \
	79	DSPI_CTAR_DT(1) \| \
	80	DSPI_CTAR_BR(6))
	81
	82	#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT \| \
	83	DSPI_CTAR_PCSSCK(3) \| \
	84	DSPI_CTAR_PASC_7CLK \| \
	85	DSPI_CTAR_PDT(3) \| \
	86	DSPI_CTAR_CSSCK(0x0f) \| \
	87	DSPI_CTAR_ASC(0x0f) \| \
	88	DSPI_CTAR_DT(0x0f))
	89
	90	#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) \| ((1 << cs) << 16))
	91
	92	static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
	93	u32 ctrl, u16 data)
bb166276	94	{
5ea37664 AD	95	/*
	96	* Need to check fifo level here
	97	*/
	98	while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
	99	;
	100
	101	writel(ctrl \| data, &cfspi->regs->tfr);
bb166276 AL	102	}
bb166276 AL	103
5ea37664	104	static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
dec61c78	105	{
dec61c78	106
5ea37664 AD	107	while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
5ea37664 AD	108	;
dec61c78	109
5ea37664	110	return readw(&cfspi->regs->rfr);
dec61c78 TL	111	}
dec61c78 TL	112
5ea37664	113	static int coldfire_spi_claim_bus(struct udevice *dev)
dec61c78	114	{
5ea37664 AD	115	struct udevice *bus = dev->parent;
	116	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	117	struct dspi *dspi = cfspi->regs;
8a8d24bd	118	struct dm_spi_slave_plat *slave_plat =
caa4daa2	119	dev_get_parent_plat(dev);
dec61c78	120
5ea37664 AD	121	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
5ea37664 AD	122	return -1;
dec61c78	123
5ea37664 AD	124	/* Clear FIFO and resume transfer */
	125	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
	126
	127	dspi_chip_select(slave_plat->cs);
	128
	129	return 0;
dec61c78 TL	130	}
dec61c78 TL	131
5ea37664	132	static int coldfire_spi_release_bus(struct udevice *dev)
dec61c78	133	{
5ea37664 AD	134	struct udevice *bus = dev->parent;
	135	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	136	struct dspi *dspi = cfspi->regs;
8a8d24bd	137	struct dm_spi_slave_plat *slave_plat =
caa4daa2	138	dev_get_parent_plat(dev);
dec61c78	139
5ea37664 AD	140	/* Clear FIFO */
5ea37664 AD	141	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
dec61c78	142
5ea37664 AD	143	dspi_chip_unselect(slave_plat->cs);
	144
	145	return 0;
dec61c78 TL	146	}
dec61c78 TL	147
5ea37664 AD	148	static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
	149	const void dout, void din,
	150	unsigned long flags)
dec61c78	151	{
5ea37664 AD	152	struct udevice *bus = dev_get_parent(dev);
5ea37664 AD	153	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
8a8d24bd	154	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
dec61c78 TL	155	u16 spi_rd16 = NULL, spi_wr16 = NULL;
dec61c78 TL	156	u8 spi_rd = NULL, spi_wr = NULL;
5ea37664	157	static u32 ctrl;
dec61c78 TL	158	uint len = bitlen >> 3;
dec61c78 TL	159
5ea37664	160	if (cfspi->charbit == 16) {
dec61c78	161	bitlen >>= 1;
5ea37664 AD	162	spi_wr16 = (u16 *)dout;
5ea37664 AD	163	spi_rd16 = (u16 *)din;
dec61c78	164	} else {
5ea37664 AD	165	spi_wr = (u8 *)dout;
5ea37664 AD	166	spi_rd = (u8 *)din;
dec61c78 TL	167	}
	168
	169	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
	170	ctrl \|= DSPI_TFR_CONT;
	171
5ea37664	172	ctrl = setup_ctrl(ctrl, slave_plat->cs);
dec61c78 TL	173
	174	if (len > 1) {
	175	int tmp_len = len - 1;
5ea37664	176
dec61c78	177	while (tmp_len--) {
5ea37664 AD	178	if (dout) {
	179	if (cfspi->charbit == 16)
	180	cfspi_tx(cfspi, ctrl, *spi_wr16++);
dec61c78	181	else
5ea37664 AD	182	cfspi_tx(cfspi, ctrl, *spi_wr++);
5ea37664 AD	183	cfspi_rx(cfspi);
dec61c78 TL	184	}
dec61c78 TL	185
5ea37664	186	if (din) {
648d675a	187	cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
5ea37664 AD	188	if (cfspi->charbit == 16)
5ea37664 AD	189	*spi_rd16++ = cfspi_rx(cfspi);
dec61c78	190	else
5ea37664	191	*spi_rd++ = cfspi_rx(cfspi);
dec61c78 TL	192	}
	193	}
	194
	195	len = 1; /* remaining byte */
	196	}
	197
5ea37664	198	if (flags & SPI_XFER_END)
dec61c78 TL	199	ctrl &= ~DSPI_TFR_CONT;
	200
	201	if (len) {
5ea37664 AD	202	if (dout) {
	203	if (cfspi->charbit == 16)
	204	cfspi_tx(cfspi, ctrl, *spi_wr16);
dec61c78	205	else
5ea37664 AD	206	cfspi_tx(cfspi, ctrl, *spi_wr);
5ea37664 AD	207	cfspi_rx(cfspi);
dec61c78 TL	208	}
dec61c78 TL	209
5ea37664	210	if (din) {
648d675a	211	cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
5ea37664 AD	212	if (cfspi->charbit == 16)
5ea37664 AD	213	*spi_rd16 = cfspi_rx(cfspi);
dec61c78	214	else
5ea37664	215	*spi_rd = cfspi_rx(cfspi);
dec61c78 TL	216	}
	217	} else {
	218	/* dummy read */
648d675a	219	cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
5ea37664	220	cfspi_rx(cfspi);
dec61c78 TL	221	}
	222
	223	return 0;
	224	}
	225
5ea37664	226	static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
dec61c78	227	{
5ea37664 AD	228	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
5ea37664 AD	229	struct dspi *dspi = cfspi->regs;
dec61c78 TL	230	int prescaler[] = { 2, 3, 5, 7 };
	231	int scaler[] = {
	232	2, 4, 6, 8,
	233	16, 32, 64, 128,
	234	256, 512, 1024, 2048,
	235	4096, 8192, 16384, 32768
	236	};
	237	int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
5ea37664 AD	238	int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
	239	u32 bus_setup;
	240
	241	cfspi->baudrate = max_hz;
	242
	243	/* Read current setup */
8b85dfc6	244	bus_setup = readl(&dspi->ctar[dev_seq(bus)]);
dec61c78 TL	245
	246	tmp = (prescaler[3] * scaler[15]);
	247	/* Maximum and minimum baudrate it can handle */
5ea37664 AD	248	if ((cfspi->baudrate > (gd->bus_clk >> 1)) \|\|
5ea37664 AD	249	(cfspi->baudrate < (gd->bus_clk / tmp))) {
dec61c78 TL	250	printf("Exceed baudrate limitation: Max %d - Min %d\n",
dec61c78 TL	251	(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
5ea37664	252	return -1;
dec61c78 TL	253	}
	254
	255	/* Activate Double Baud when it exceed 1/4 the bus clk */
5ea37664 AD	256	if ((bus_setup & DSPI_CTAR_DBR) \|\|
5ea37664 AD	257	(cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
dec61c78 TL	258	bus_setup \|= DSPI_CTAR_DBR;
	259	dbr = 1;
	260	}
	261
dec61c78	262	/* Overwrite default value set in platform configuration file */
5ea37664	263	if (cfspi->mode & SPI_MODE_MOD) {
dec61c78 TL	264	/*
	265	* Check to see if it is enabled by default in platform
	266	* config, or manual setting passed by mode parameter
	267	*/
5ea37664	268	if (cfspi->mode & SPI_MODE_DBLRATE) {
dec61c78 TL	269	bus_setup \|= DSPI_CTAR_DBR;
	270	dbr = 1;
	271	}
5ea37664	272	}
dec61c78 TL	273
	274	pbrcnt = sizeof(prescaler) / sizeof(int);
	275	brcnt = sizeof(scaler) / sizeof(int);
	276
	277	/* baudrate calculation - to closer value, may not be exact match */
	278	for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
	279	baud_speed = gd->bus_clk / prescaler[i];
	280	for (j = 0; j < brcnt; j++) {
	281	tmp = (baud_speed / scaler[j]) * (1 + dbr);
	282
5ea37664 AD	283	if (tmp > cfspi->baudrate)
5ea37664 AD	284	diff = tmp - cfspi->baudrate;
dec61c78	285	else
5ea37664	286	diff = cfspi->baudrate - tmp;
dec61c78 TL	287
	288	if (diff < bestmatch) {
	289	bestmatch = diff;
	290	best_i = i;
	291	best_j = j;
	292	}
	293	}
	294	}
5ea37664 AD	295
5ea37664 AD	296	bus_setup &= ~(DSPI_CTAR_PBR(0x03) \| DSPI_CTAR_BR(0x0f));
dec61c78	297	bus_setup \|= (DSPI_CTAR_PBR(best_i) \| DSPI_CTAR_BR(best_j));
8b85dfc6	298	writel(bus_setup, &dspi->ctar[dev_seq(bus)]);
dec61c78	299
5ea37664	300	return 0;
dec61c78	301	}
dec61c78	302
5ea37664	303	static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
dec61c78	304	{
5ea37664 AD	305	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	306	struct dspi *dspi = cfspi->regs;
	307	u32 bus_setup = 0;
dec61c78	308
5ea37664	309	cfspi->mode = mode;
dec61c78	310
5ea37664 AD	311	if (cfspi->mode & SPI_CPOL)
	312	bus_setup \|= DSPI_CTAR_CPOL;
	313	if (cfspi->mode & SPI_CPHA)
	314	bus_setup \|= DSPI_CTAR_CPHA;
	315	if (cfspi->mode & SPI_LSB_FIRST)
	316	bus_setup \|= DSPI_CTAR_LSBFE;
dec61c78	317
5ea37664 AD	318	/* Overwrite default value set in platform configuration file */
	319	if (cfspi->mode & SPI_MODE_MOD) {
	320	if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
	321	bus_setup \|=
8b85dfc6	322	readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
5ea37664 AD	323	else
	324	bus_setup \|=
	325	((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
dec61c78	326
5ea37664 AD	327	/* PSCSCK, PASC, PDT */
	328	bus_setup \|= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
	329	/* CSSCK, ASC, DT */
	330	bus_setup \|= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
	331	} else {
	332	bus_setup \|=
8b85dfc6	333	(readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
5ea37664 AD	334	}
	335
	336	cfspi->charbit =
8b85dfc6	337	((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
5ea37664	338	MCF_FRM_SZ_16BIT) ? 16 : 8;
dec61c78	339
8b85dfc6	340	setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);
dec61c78	341
5ea37664	342	return 0;
dec61c78 TL	343	}
dec61c78 TL	344
5ea37664	345	static int coldfire_spi_probe(struct udevice *bus)
dec61c78	346	{
8a8d24bd	347	struct coldfire_spi_plat *plat = dev_get_plat(bus);
5ea37664 AD	348	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	349	struct dspi *dspi = cfspi->regs;
	350	int i;
bb166276	351
5ea37664	352	cfspi->regs = (struct dspi *)plat->regs_addr;
dec61c78	353
5ea37664 AD	354	cfspi->baudrate = plat->speed_hz;
	355	cfspi->mode = plat->mode;
	356
	357	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
	358	unsigned int ctar = 0;
	359
	360	if (plat->ctar[i][0] == 0)
	361	break;
	362
	363	ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) \|
	364	DSPI_CTAR_PCSSCK(plat->ctar[i][1]) \|
	365	DSPI_CTAR_PASC(plat->ctar[i][2]) \|
	366	DSPI_CTAR_PDT(plat->ctar[i][3]) \|
	367	DSPI_CTAR_CSSCK(plat->ctar[i][4]) \|
	368	DSPI_CTAR_ASC(plat->ctar[i][5]) \|
	369	DSPI_CTAR_DT(plat->ctar[i][6]) \|
	370	DSPI_CTAR_BR(plat->ctar[i][7]);
	371
	372	writel(ctar, &cfspi->regs->ctar[i]);
	373	}
	374
	375	/* Default CTARs */
	376	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
	377	writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
	378
	379	dspi->mcr = DSPI_MCR_MSTR \| DSPI_MCR_CSIS7 \| DSPI_MCR_CSIS6 \|
	380	DSPI_MCR_CSIS5 \| DSPI_MCR_CSIS4 \| DSPI_MCR_CSIS3 \|
	381	DSPI_MCR_CSIS2 \| DSPI_MCR_CSIS1 \| DSPI_MCR_CSIS0 \|
	382	DSPI_MCR_CRXF \| DSPI_MCR_CTXF;
	383
	384	return 0;
dec61c78 TL	385	}
dec61c78 TL	386
414cc151	387	#if CONFIG_IS_ENABLED(OF_REAL)
d1998a9f	388	static int coldfire_dspi_of_to_plat(struct udevice *bus)
dec61c78	389	{
5ea37664	390	fdt_addr_t addr;
0fd3d911	391	struct coldfire_spi_plat *plat = dev_get_plat(bus);
5ea37664 AD	392	const void *blob = gd->fdt_blob;
	393	int node = dev_of_offset(bus);
	394	int *ctar, len;
	395
2548493a	396	addr = dev_read_addr(bus);
5ea37664 AD	397	if (addr == FDT_ADDR_T_NONE)
	398	return -ENOMEM;
	399
	400	plat->regs_addr = addr;
	401
	402	plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
	403	MCF_DSPI_DEFAULT_MAX_CS);
	404
	405	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
	406	MCF_DSPI_DEFAULT_SCK_FREQ);
	407
	408	plat->mode = fdtdec_get_int(blob, node, "spi-mode",
	409	MCF_DSPI_DEFAULT_MODE);
	410
	411	memset(plat->ctar, 0, sizeof(plat->ctar));
	412
	413	ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
	414
	415	if (ctar && len) {
	416	int i, q, ctar_regs;
	417
	418	ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
	419
	420	if (ctar_regs > MAX_CTAR_REGS)
	421	ctar_regs = MAX_CTAR_REGS;
	422
	423	for (i = 0; i < ctar_regs; i++) {
	424	for (q = 0; q < MAX_CTAR_FIELDS; q++)
	425	plat->ctar[i][q] = *ctar++;
	426	}
	427	}
	428
	429	debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
	430	(void *)plat->regs_addr,
	431	plat->speed_hz, plat->num_cs, plat->mode);
	432
	433	return 0;
dec61c78	434	}
5ea37664 AD	435
	436	static const struct udevice_id coldfire_spi_ids[] = {
	437	{ .compatible = "fsl,mcf-dspi" },
	438	{ }
	439	};
	440	#endif
	441
	442	static const struct dm_spi_ops coldfire_spi_ops = {
	443	.claim_bus = coldfire_spi_claim_bus,
	444	.release_bus = coldfire_spi_release_bus,
	445	.xfer = coldfire_spi_xfer,
	446	.set_speed = coldfire_spi_set_speed,
	447	.set_mode = coldfire_spi_set_mode,
	448	};
	449
	450	U_BOOT_DRIVER(coldfire_spi) = {
	451	.name = "spi_coldfire",
	452	.id = UCLASS_SPI,
414cc151	453	#if CONFIG_IS_ENABLED(OF_REAL)
5ea37664	454	.of_match = coldfire_spi_ids,
d1998a9f	455	.of_to_plat = coldfire_dspi_of_to_plat,
8a8d24bd	456	.plat_auto = sizeof(struct coldfire_spi_plat),
5ea37664 AD	457	#endif
	458	.probe = coldfire_spi_probe,
	459	.ops = &coldfire_spi_ops,
41575d8e	460	.priv_auto = sizeof(struct coldfire_spi_priv),
5ea37664	461	};