[people/ms/u-boot.git] / drivers / spi / mxc_spi.c

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
"See linux mxc_spi driver from Freescale for details."

#else

#define MXC_CSPIRXDATA		0x00
#define MXC_CSPITXDATA		0x04
#define MXC_CSPICTRL		0x08
#define MXC_CSPIINT		0x0C
#define MXC_CSPIDMA		0x10
#define MXC_CSPISTAT		0x14
#define MXC_CSPIPERIOD		0x18
#define MXC_CSPITEST		0x1C
#define MXC_CSPIRESET		0x00

#define MXC_CSPICTRL_EN		(1 << 0)
#define MXC_CSPICTRL_MODE	(1 << 1)
#define MXC_CSPICTRL_XCH	(1 << 2)
#define MXC_CSPICTRL_SMC	(1 << 3)
#define MXC_CSPICTRL_POL	(1 << 4)
#define MXC_CSPICTRL_PHA	(1 << 5)
#define MXC_CSPICTRL_SSCTL	(1 << 6)
#define MXC_CSPICTRL_SSPOL	(1 << 7)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)

#define MXC_CSPIPERIOD_32KHZ	(1 << 15)

static unsigned long spi_bases[] = {
	0x43fa4000,
	0x50010000,
	0x53f84000,
};

#endif

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

static inline u32 reg_read(unsigned long addr)
{
	return *(volatile unsigned long*)addr;
}

static inline void reg_write(unsigned long addr, u32 val)
{
	*(volatile unsigned long*)addr = val;
}

static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);

	if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
		cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
			MXC_CSPICTRL_BITCOUNT(bitlen - 1);
		reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
	}

	reg_write(mxcs->base + MXC_CSPITXDATA, data);

	cfg_reg |= MXC_CSPICTRL_XCH;

	reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);

	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
		;

	return reg_read(mxcs->base + MXC_CSPIRXDATA);
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	int n_blks = (bitlen + 31) / 32;
	u32 *out_l, *in_l;
	int i;

	if ((int)dout & 3 || (int)din & 3) {
		printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
		return 1;
	}

	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
	     i < n_blks;
	     i++, in_l++, out_l++, bitlen -= 32)
		*in_l = spi_xchg_single(slave, *out_l, bitlen);

	return 0;
}

void spi_init(void)
{
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	unsigned int ctrl_reg;
	struct mxc_spi_slave *mxcs;

	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
	    cs > 3)
		return NULL;

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(31) |
		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
		MXC_CSPICTRL_EN |
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (!(mode & SPI_CPOL))
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;

	mxcs = malloc(sizeof(struct mxc_spi_slave));
	if (!mxcs)
		return NULL;

	mxcs->slave.bus = bus;
	mxcs->slave.cs = cs;
	mxcs->base = spi_bases[bus];
	mxcs->ctrl_reg = ctrl_reg;

	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	free(slave);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	reg_write(mxcs->base + MXC_CSPIRESET, 1);
	udelay(1);
	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
	reg_write(mxcs->base + MXC_CSPIPERIOD,
		  MXC_CSPIPERIOD_32KHZ);
	reg_write(mxcs->base + MXC_CSPIINT, 0);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
Commit	Line	Data
38254f45 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*
	19	*/
	20
	21	#include <common.h>
d255bb0e	22	#include <malloc.h>
38254f45 GL	23	#include <spi.h>
	24	#include <asm/io.h>
	25
	26	#ifdef CONFIG_MX27
	27	/* i.MX27 has a completely wrong register layout and register definitions in the
	28	* datasheet, the correct one is in the Freescale's Linux driver */
	29
	30	#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
	31	"See linux mxc_spi driver from Freescale for details."
	32
	33	#else
	34
	35	#define MXC_CSPIRXDATA 0x00
	36	#define MXC_CSPITXDATA 0x04
	37	#define MXC_CSPICTRL 0x08
	38	#define MXC_CSPIINT 0x0C
	39	#define MXC_CSPIDMA 0x10
	40	#define MXC_CSPISTAT 0x14
	41	#define MXC_CSPIPERIOD 0x18
	42	#define MXC_CSPITEST 0x1C
	43	#define MXC_CSPIRESET 0x00
	44
	45	#define MXC_CSPICTRL_EN (1 << 0)
	46	#define MXC_CSPICTRL_MODE (1 << 1)
	47	#define MXC_CSPICTRL_XCH (1 << 2)
	48	#define MXC_CSPICTRL_SMC (1 << 3)
	49	#define MXC_CSPICTRL_POL (1 << 4)
	50	#define MXC_CSPICTRL_PHA (1 << 5)
	51	#define MXC_CSPICTRL_SSCTL (1 << 6)
53677ef1	52	#define MXC_CSPICTRL_SSPOL (1 << 7)
38254f45 GL	53	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
	54	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
	55	#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
	56
	57	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
	58
	59	static unsigned long spi_bases[] = {
	60	0x43fa4000,
	61	0x50010000,
	62	0x53f84000,
	63	};
	64
38254f45 GL	65	#endif
38254f45 GL	66
d255bb0e HS	67	struct mxc_spi_slave {
	68	struct spi_slave slave;
	69	unsigned long base;
	70	u32 ctrl_reg;
38254f45	71	};
d255bb0e HS	72
	73	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	74	{
	75	return container_of(slave, struct mxc_spi_slave, slave);
	76	}
38254f45 GL	77
	78	static inline u32 reg_read(unsigned long addr)
	79	{
	80	return (volatile unsigned long)addr;
	81	}
	82
	83	static inline void reg_write(unsigned long addr, u32 val)
	84	{
	85	(volatile unsigned long)addr = val;
	86	}
	87
d255bb0e	88	static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
38254f45	89	{
d255bb0e HS	90	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
d255bb0e HS	91	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
38254f45 GL	92
	93	if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
	94	cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) \|
	95	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
d255bb0e	96	reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
38254f45 GL	97	}
38254f45 GL	98
d255bb0e	99	reg_write(mxcs->base + MXC_CSPITXDATA, data);
38254f45 GL	100
	101	cfg_reg \|= MXC_CSPICTRL_XCH;
	102
d255bb0e	103	reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
38254f45	104
d255bb0e	105	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
38254f45 GL	106	;
38254f45 GL	107
d255bb0e	108	return reg_read(mxcs->base + MXC_CSPIRXDATA);
38254f45 GL	109	}
38254f45 GL	110
d255bb0e HS	111	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
d255bb0e HS	112	void *din, unsigned long flags)
38254f45 GL	113	{
	114	int n_blks = (bitlen + 31) / 32;
	115	u32 out_l, in_l;
	116	int i;
	117
	118	if ((int)dout & 3 \|\| (int)din & 3) {
	119	printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
	120	return 1;
	121	}
	122
38254f45 GL	123	for (i = 0, in_l = (u32 )din, out_l = (u32 )dout;
	124	i < n_blks;
	125	i++, in_l++, out_l++, bitlen -= 32)
d255bb0e	126	in_l = spi_xchg_single(slave, out_l, bitlen);
38254f45 GL	127
	128	return 0;
	129	}
	130
	131	void spi_init(void)
	132	{
	133	}
	134
d255bb0e HS	135	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	136	unsigned int max_hz, unsigned int mode)
38254f45 GL	137	{
38254f45 GL	138	unsigned int ctrl_reg;
d255bb0e	139	struct mxc_spi_slave *mxcs;
38254f45 GL	140
38254f45 GL	141	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) \|\|
d255bb0e HS	142	cs > 3)
d255bb0e HS	143	return NULL;
38254f45	144
d255bb0e	145	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
38254f45 GL	146	MXC_CSPICTRL_BITCOUNT(31) \|
	147	MXC_CSPICTRL_DATARATE(7) \| /* FIXME: calculate data rate */
	148	MXC_CSPICTRL_EN \|
	149	MXC_CSPICTRL_MODE;
	150
	151	if (mode & SPI_CPHA)
	152	ctrl_reg \|= MXC_CSPICTRL_PHA;
	153	if (!(mode & SPI_CPOL))
	154	ctrl_reg \|= MXC_CSPICTRL_POL;
	155	if (mode & SPI_CS_HIGH)
	156	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	157
d255bb0e HS	158	mxcs = malloc(sizeof(struct mxc_spi_slave));
	159	if (!mxcs)
	160	return NULL;
	161
	162	mxcs->slave.bus = bus;
	163	mxcs->slave.cs = cs;
	164	mxcs->base = spi_bases[bus];
	165	mxcs->ctrl_reg = ctrl_reg;
	166
	167	return &mxcs->slave;
	168	}
	169
	170	void spi_free_slave(struct spi_slave *slave)
	171	{
	172	free(slave);
	173	}
	174
	175	int spi_claim_bus(struct spi_slave *slave)
	176	{
	177	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	178
	179	reg_write(mxcs->base + MXC_CSPIRESET, 1);
38254f45	180	udelay(1);
d255bb0e HS	181	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
d255bb0e HS	182	reg_write(mxcs->base + MXC_CSPIPERIOD,
38254f45	183	MXC_CSPIPERIOD_32KHZ);
d255bb0e	184	reg_write(mxcs->base + MXC_CSPIINT, 0);
38254f45 GL	185
	186	return 0;
	187	}
d255bb0e HS	188
	189	void spi_release_bus(struct spi_slave *slave)
	190	{
	191	/* TODO: Shut the controller down */
	192	}