[people/ms/u-boot.git] / drivers / spi / mxc_spi.c

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
#endif

static unsigned long spi_bases[] = {
	MXC_SPI_BASE_ADDRESSES
};

#define OUT	MXC_GPIO_DIRECTION_OUT

#define reg_read readl
#define reg_write(a, v) writel(v, a)

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
#if defined(MXC_ECSPI)
	u32		cfg_reg;
#endif
	int		gpio;
	int		ss_pol;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

void spi_cs_activate(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio, mxcs->ss_pol);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	if (mxcs->gpio > 0)
		gpio_set_value(mxcs->gpio,
			      !(mxcs->ss_pol));
}

u32 get_cspi_div(u32 div)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (div <= (4 << i))
			return i;
	}
	return i;
}

#ifdef MXC_CSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	unsigned int ctrl_reg;
	u32 clk_src;
	u32 div;

	clk_src = mxc_get_clock(MXC_CSPI_CLK);

	div = DIV_ROUND_UP(clk_src, max_hz);
	div = get_cspi_div(div);

	debug("clk %d Hz, div %d, real clk %d Hz\n",
		max_hz, div, clk_src / (4 << div));

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
		MXC_CSPICTRL_DATARATE(div) |
		MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
		MXC_CSPICTRL_SSCTL |
#endif
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (mode & SPI_CPOL)
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;
	mxcs->ctrl_reg = ctrl_reg;

	return 0;
}
#endif

#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	s32 reg_ctrl, reg_config;
	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
	u32 pre_div = 0, post_div = 0;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	if (max_hz == 0) {
		printf("Error: desired clock is 0\n");
		return -1;
	}

	/*
	 * Reset SPI and set all CSs to master mode, if toggling
	 * between slave and master mode we might see a glitch
	 * on the clock line
	 */
	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	reg_write(&regs->ctrl, reg_ctrl);
	reg_ctrl |=  MXC_CSPICTRL_EN;
	reg_write(&regs->ctrl, reg_ctrl);

	if (clk_src > max_hz) {
		pre_div = (clk_src - 1) / max_hz;
		/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
		post_div = fls(pre_div);
		if (post_div > 4) {
			post_div -= 4;
			if (post_div >= 16) {
				printf("Error: no divider for the freq: %d\n",
					max_hz);
				return -1;
			}
			pre_div >>= post_div;
		} else {
			post_div = 0;
		}
	}

	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
		MXC_CSPICTRL_SELCHAN(cs);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
		MXC_CSPICTRL_PREDIV(pre_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
		MXC_CSPICTRL_POSTDIV(post_div);

	/* We need to disable SPI before changing registers */
	reg_ctrl &= ~MXC_CSPICTRL_EN;

	if (mode & SPI_CS_HIGH)
		ss_pol = 1;

	if (mode & SPI_CPOL) {
		sclkpol = 1;
		sclkctl = 1;
	}

	if (mode & SPI_CPHA)
		sclkpha = 1;

	reg_config = reg_read(&regs->cfg);

	/*
	 * Configuration register setup
	 * The MX51 supports different setup for each SS
	 */
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
		(ss_pol << (cs + MXC_CSPICON_SSPOL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
		(sclkpol << (cs + MXC_CSPICON_POL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
		(sclkctl << (cs + MXC_CSPICON_CTL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
		(sclkpha << (cs + MXC_CSPICON_PHA));

	debug("reg_ctrl = 0x%x\n", reg_ctrl);
	reg_write(&regs->ctrl, reg_ctrl);
	debug("reg_config = 0x%x\n", reg_config);
	reg_write(&regs->cfg, reg_config);

	/* save config register and control register */
	mxcs->ctrl_reg = reg_ctrl;
	mxcs->cfg_reg = reg_config;

	/* clear interrupt reg */
	reg_write(&regs->intr, 0);
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	return 0;
}
#endif

int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
	const u8 *dout, u8 *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	int nbytes = DIV_ROUND_UP(bitlen, 8);
	u32 data, cnt, i;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
		__func__, bitlen, (u32)dout, (u32)din);

	mxcs->ctrl_reg = (mxcs->ctrl_reg &
		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef MXC_ECSPI
	reg_write(&regs->cfg, mxcs->cfg_reg);
#endif

	/* Clear interrupt register */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	/*
	 * The SPI controller works only with words,
	 * check if less than a word is sent.
	 * Access to the FIFO is only 32 bit
	 */
	if (bitlen % 32) {
		data = 0;
		cnt = (bitlen % 32) / 8;
		if (dout) {
			for (i = 0; i < cnt; i++) {
				data = (data << 8) | (*dout++ & 0xFF);
			}
		}
		debug("Sending SPI 0x%x\n", data);

		reg_write(&regs->txdata, data);
		nbytes -= cnt;
	}

	data = 0;

	while (nbytes > 0) {
		data = 0;
		if (dout) {
			/* Buffer is not 32-bit aligned */
			if ((unsigned long)dout & 0x03) {
				data = 0;
				for (i = 0; i < 4; i++)
					data = (data << 8) | (*dout++ & 0xFF);
			} else {
				data = *(u32 *)dout;
				data = cpu_to_be32(data);
				dout += 4;
			}
		}
		debug("Sending SPI 0x%x\n", data);
		reg_write(&regs->txdata, data);
		nbytes -= 4;
	}

	/* FIFO is written, now starts the transfer setting the XCH bit */
	reg_write(&regs->ctrl, mxcs->ctrl_reg |
		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

	/* Wait until the TC (Transfer completed) bit is set */
	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
		;

	/* Transfer completed, clear any pending request */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	nbytes = DIV_ROUND_UP(bitlen, 8);

	cnt = nbytes % 32;

	if (bitlen % 32) {
		data = reg_read(&regs->rxdata);
		cnt = (bitlen % 32) / 8;
		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
		debug("SPI Rx unaligned: 0x%x\n", data);
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	while (nbytes > 0) {
		u32 tmp;
		tmp = reg_read(&regs->rxdata);
		data = cpu_to_be32(tmp);
		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
		cnt = min(nbytes, sizeof(data));
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	return 0;

}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	int n_bytes = DIV_ROUND_UP(bitlen, 8);
	int n_bits;
	int ret;
	u32 blk_size;
	u8 *p_outbuf = (u8 *)dout;
	u8 *p_inbuf = (u8 *)din;

	if (!slave)
		return -1;

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(slave);

	while (n_bytes > 0) {
		if (n_bytes < MAX_SPI_BYTES)
			blk_size = n_bytes;
		else
			blk_size = MAX_SPI_BYTES;

		n_bits = blk_size * 8;

		ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);

		if (ret)
			return ret;
		if (dout)
			p_outbuf += blk_size;
		if (din)
			p_inbuf += blk_size;
		n_bytes -= blk_size;
	}

	if (flags & SPI_XFER_END) {
		spi_cs_deactivate(slave);
	}

	return 0;
}

void spi_init(void)
{
}

static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	int ret;

	/*
	 * Some SPI devices require active chip-select over multiple
	 * transactions, we achieve this using a GPIO. Still, the SPI
	 * controller has to be configured to use one of its own chipselects.
	 * To use this feature you have to call spi_setup_slave() with
	 * cs = internal_cs | (gpio << 8), and you have to use some unused
	 * on this SPI controller cs between 0 and 3.
	 */
	if (cs > 3) {
		mxcs->gpio = cs >> 8;
		cs &= 3;
		ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
		if (ret) {
			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
			return -EINVAL;
		}
	} else {
		mxcs->gpio = -1;
	}

	return cs;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
	if (!mxcs) {
		puts("mxc_spi: SPI Slave not allocated !\n");
		return NULL;
	}

	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	ret = decode_cs(mxcs, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	cs = ret;

	mxcs->base = spi_bases[bus];

	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
	if (ret) {
		printf("mxc_spi: cannot setup SPI controller\n");
		free(mxcs);
		return NULL;
	}
	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	reg_write(&regs->rxdata, 1);
	udelay(1);
	reg_write(&regs->ctrl, mxcs->ctrl_reg);
	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	reg_write(&regs->intr, 0);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
Commit	Line	Data
38254f45 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
38254f45 GL	5	*/
	6
	7	#include <common.h>
d255bb0e	8	#include <malloc.h>
38254f45	9	#include <spi.h>
fc7a93c8	10	#include <asm/errno.h>
38254f45	11	#include <asm/io.h>
d8e0ca85	12	#include <asm/gpio.h>
86271115 SB	13	#include <asm/arch/imx-regs.h>
86271115 SB	14	#include <asm/arch/clock.h>
38254f45 GL	15
	16	#ifdef CONFIG_MX27
	17	/* i.MX27 has a completely wrong register layout and register definitions in the
	18	* datasheet, the correct one is in the Freescale's Linux driver */
	19
61a58a16	20	#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
38254f45	21	"See linux mxc_spi driver from Freescale for details."
08c61a58	22	#endif
c9d59c7f SB	23
c9d59c7f SB	24	static unsigned long spi_bases[] = {
08c61a58	25	MXC_SPI_BASE_ADDRESSES
c9d59c7f SB	26	};
c9d59c7f SB	27
c4ea1424 SB	28	#define OUT MXC_GPIO_DIRECTION_OUT
c4ea1424 SB	29
ac87c17d SB	30	#define reg_read readl
	31	#define reg_write(a, v) writel(v, a)
	32
d255bb0e HS	33	struct mxc_spi_slave {
	34	struct spi_slave slave;
	35	unsigned long base;
	36	u32 ctrl_reg;
08c61a58	37	#if defined(MXC_ECSPI)
d205ddcf SB	38	u32 cfg_reg;
d205ddcf SB	39	#endif
fc7a93c8	40	int gpio;
c4ea1424	41	int ss_pol;
38254f45	42	};
d255bb0e HS	43
	44	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	45	{
	46	return container_of(slave, struct mxc_spi_slave, slave);
	47	}
38254f45	48
d205ddcf SB	49	void spi_cs_activate(struct spi_slave *slave)
	50	{
	51	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	52	if (mxcs->gpio > 0)
d8e0ca85	53	gpio_set_value(mxcs->gpio, mxcs->ss_pol);
d205ddcf SB	54	}
	55
	56	void spi_cs_deactivate(struct spi_slave *slave)
	57	{
	58	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	59	if (mxcs->gpio > 0)
d8e0ca85	60	gpio_set_value(mxcs->gpio,
c4ea1424	61	!(mxcs->ss_pol));
d205ddcf SB	62	}
d205ddcf SB	63
afaa9f65 AG	64	u32 get_cspi_div(u32 div)
	65	{
	66	int i;
	67
	68	for (i = 0; i < 8; i++) {
	69	if (div <= (4 << i))
	70	return i;
	71	}
	72	return i;
	73	}
	74
08c61a58	75	#ifdef MXC_CSPI
c9d59c7f SB	76	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
	77	unsigned int max_hz, unsigned int mode)
	78	{
	79	unsigned int ctrl_reg;
afaa9f65 AG	80	u32 clk_src;
	81	u32 div;
	82
	83	clk_src = mxc_get_clock(MXC_CSPI_CLK);
	84
cd200403	85	div = DIV_ROUND_UP(clk_src, max_hz);
afaa9f65 AG	86	div = get_cspi_div(div);
	87
	88	debug("clk %d Hz, div %d, real clk %d Hz\n",
	89	max_hz, div, clk_src / (4 << div));
c9d59c7f SB	90
	91	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
	92	MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) \|
afaa9f65	93	MXC_CSPICTRL_DATARATE(div) \|
c9d59c7f SB	94	MXC_CSPICTRL_EN \|
	95	#ifdef CONFIG_MX35
	96	MXC_CSPICTRL_SSCTL \|
	97	#endif
	98	MXC_CSPICTRL_MODE;
	99
	100	if (mode & SPI_CPHA)
	101	ctrl_reg \|= MXC_CSPICTRL_PHA;
	102	if (mode & SPI_CPOL)
	103	ctrl_reg \|= MXC_CSPICTRL_POL;
	104	if (mode & SPI_CS_HIGH)
	105	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	106	mxcs->ctrl_reg = ctrl_reg;
	107
	108	return 0;
	109	}
	110	#endif
	111
08c61a58	112	#ifdef MXC_ECSPI
c9d59c7f	113	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
d205ddcf SB	114	unsigned int max_hz, unsigned int mode)
	115	{
	116	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
9a30903b	117	s32 reg_ctrl, reg_config;
5d584cce MN	118	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
5d584cce MN	119	u32 pre_div = 0, post_div = 0;
ac87c17d	120	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
d205ddcf SB	121
	122	if (max_hz == 0) {
	123	printf("Error: desired clock is 0\n");
	124	return -1;
	125	}
	126
0f1411bc FE	127	/*
	128	* Reset SPI and set all CSs to master mode, if toggling
	129	* between slave and master mode we might see a glitch
	130	* on the clock line
	131	*/
	132	reg_ctrl = MXC_CSPICTRL_MODE_MASK;
	133	reg_write(&regs->ctrl, reg_ctrl);
	134	reg_ctrl \|= MXC_CSPICTRL_EN;
	135	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	136
d205ddcf	137	if (clk_src > max_hz) {
9a30903b DB	138	pre_div = (clk_src - 1) / max_hz;
	139	/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
	140	post_div = fls(pre_div);
	141	if (post_div > 4) {
	142	post_div -= 4;
	143	if (post_div >= 16) {
d205ddcf SB	144	printf("Error: no divider for the freq: %d\n",
	145	max_hz);
	146	return -1;
	147	}
9a30903b DB	148	pre_div >>= post_div;
	149	} else {
	150	post_div = 0;
d205ddcf SB	151	}
	152	}
	153
	154	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	155	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) \|
	156	MXC_CSPICTRL_SELCHAN(cs);
	157	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) \|
	158	MXC_CSPICTRL_PREDIV(pre_div);
	159	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) \|
	160	MXC_CSPICTRL_POSTDIV(post_div);
	161
d205ddcf SB	162	/* We need to disable SPI before changing registers */
	163	reg_ctrl &= ~MXC_CSPICTRL_EN;
	164
	165	if (mode & SPI_CS_HIGH)
	166	ss_pol = 1;
	167
5d584cce	168	if (mode & SPI_CPOL) {
d205ddcf	169	sclkpol = 1;
5d584cce MN	170	sclkctl = 1;
5d584cce MN	171	}
d205ddcf SB	172
	173	if (mode & SPI_CPHA)
	174	sclkpha = 1;
	175
ac87c17d	176	reg_config = reg_read(&regs->cfg);
d205ddcf SB	177
	178	/*
	179	* Configuration register setup
c9d59c7f	180	* The MX51 supports different setup for each SS
d205ddcf SB	181	*/
	182	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) \|
	183	(ss_pol << (cs + MXC_CSPICON_SSPOL));
	184	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
	185	(sclkpol << (cs + MXC_CSPICON_POL));
5d584cce MN	186	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) \|
5d584cce MN	187	(sclkctl << (cs + MXC_CSPICON_CTL));
d205ddcf SB	188	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
	189	(sclkpha << (cs + MXC_CSPICON_PHA));
	190
	191	debug("reg_ctrl = 0x%x\n", reg_ctrl);
ac87c17d	192	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	193	debug("reg_config = 0x%x\n", reg_config);
ac87c17d	194	reg_write(&regs->cfg, reg_config);
d205ddcf SB	195
	196	/* save config register and control register */
	197	mxcs->ctrl_reg = reg_ctrl;
	198	mxcs->cfg_reg = reg_config;
	199
	200	/* clear interrupt reg */
ac87c17d SB	201	reg_write(&regs->intr, 0);
ac87c17d SB	202	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf SB	203
	204	return 0;
	205	}
	206	#endif
	207
2f721d17 SB	208	int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
2f721d17 SB	209	const u8 dout, u8 din, unsigned long flags)
38254f45	210	{
d255bb0e	211	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
9675fed4	212	int nbytes = DIV_ROUND_UP(bitlen, 8);
2f721d17	213	u32 data, cnt, i;
ac87c17d	214	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
38254f45	215
2f721d17 SB	216	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
2f721d17 SB	217	__func__, bitlen, (u32)dout, (u32)din);
d205ddcf SB	218
	219	mxcs->ctrl_reg = (mxcs->ctrl_reg &
	220	~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) \|
f9b6a157	221	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	222
ac87c17d	223	reg_write(&regs->ctrl, mxcs->ctrl_reg \| MXC_CSPICTRL_EN);
08c61a58	224	#ifdef MXC_ECSPI
ac87c17d	225	reg_write(&regs->cfg, mxcs->cfg_reg);
d205ddcf	226	#endif
38254f45	227
d205ddcf	228	/* Clear interrupt register */
ac87c17d	229	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
fc7a93c8	230
2f721d17 SB	231	/*
	232	* The SPI controller works only with words,
	233	* check if less than a word is sent.
	234	* Access to the FIFO is only 32 bit
	235	*/
	236	if (bitlen % 32) {
	237	data = 0;
	238	cnt = (bitlen % 32) / 8;
	239	if (dout) {
	240	for (i = 0; i < cnt; i++) {
	241	data = (data << 8) \| (*dout++ & 0xFF);
	242	}
	243	}
	244	debug("Sending SPI 0x%x\n", data);
	245
ac87c17d	246	reg_write(&regs->txdata, data);
2f721d17 SB	247	nbytes -= cnt;
	248	}
	249
	250	data = 0;
	251
	252	while (nbytes > 0) {
	253	data = 0;
	254	if (dout) {
	255	/* Buffer is not 32-bit aligned */
	256	if ((unsigned long)dout & 0x03) {
	257	data = 0;
dff01094	258	for (i = 0; i < 4; i++)
2f721d17	259	data = (data << 8) \| (*dout++ & 0xFF);
2f721d17 SB	260	} else {
	261	data = (u32 )dout;
	262	data = cpu_to_be32(data);
6d5ce1bd	263	dout += 4;
2f721d17	264	}
2f721d17 SB	265	}
2f721d17 SB	266	debug("Sending SPI 0x%x\n", data);
ac87c17d	267	reg_write(&regs->txdata, data);
2f721d17 SB	268	nbytes -= 4;
2f721d17 SB	269	}
38254f45	270
d205ddcf	271	/* FIFO is written, now starts the transfer setting the XCH bit */
ac87c17d	272	reg_write(&regs->ctrl, mxcs->ctrl_reg \|
d205ddcf	273	MXC_CSPICTRL_EN \| MXC_CSPICTRL_XCH);
38254f45	274
d205ddcf	275	/* Wait until the TC (Transfer completed) bit is set */
ac87c17d	276	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
38254f45 GL	277	;
38254f45 GL	278
d205ddcf	279	/* Transfer completed, clear any pending request */
ac87c17d	280	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf	281
9675fed4	282	nbytes = DIV_ROUND_UP(bitlen, 8);
d205ddcf	283
2f721d17	284	cnt = nbytes % 32;
d205ddcf	285
2f721d17	286	if (bitlen % 32) {
ac87c17d	287	data = reg_read(&regs->rxdata);
2f721d17	288	cnt = (bitlen % 32) / 8;
dff01094	289	data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
2f721d17 SB	290	debug("SPI Rx unaligned: 0x%x\n", data);
2f721d17 SB	291	if (din) {
dff01094 AG	292	memcpy(din, &data, cnt);
dff01094 AG	293	din += cnt;
2f721d17 SB	294	}
	295	nbytes -= cnt;
	296	}
	297
	298	while (nbytes > 0) {
	299	u32 tmp;
ac87c17d	300	tmp = reg_read(&regs->rxdata);
2f721d17 SB	301	data = cpu_to_be32(tmp);
	302	debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
	303	cnt = min(nbytes, sizeof(data));
	304	if (din) {
	305	memcpy(din, &data, cnt);
	306	din += cnt;
	307	}
	308	nbytes -= cnt;
	309	}
	310
	311	return 0;
fc7a93c8	312
38254f45 GL	313	}
38254f45 GL	314
d255bb0e HS	315	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
d255bb0e HS	316	void *din, unsigned long flags)
38254f45	317	{
9675fed4	318	int n_bytes = DIV_ROUND_UP(bitlen, 8);
2f721d17 SB	319	int n_bits;
	320	int ret;
	321	u32 blk_size;
	322	u8 p_outbuf = (u8 )dout;
	323	u8 p_inbuf = (u8 )din;
38254f45	324
2f721d17 SB	325	if (!slave)
2f721d17 SB	326	return -1;
38254f45	327
2f721d17 SB	328	if (flags & SPI_XFER_BEGIN)
	329	spi_cs_activate(slave);
	330
	331	while (n_bytes > 0) {
2f721d17 SB	332	if (n_bytes < MAX_SPI_BYTES)
	333	blk_size = n_bytes;
	334	else
	335	blk_size = MAX_SPI_BYTES;
	336
	337	n_bits = blk_size * 8;
	338
	339	ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
	340
	341	if (ret)
	342	return ret;
	343	if (dout)
	344	p_outbuf += blk_size;
	345	if (din)
	346	p_inbuf += blk_size;
	347	n_bytes -= blk_size;
eff536be ML	348	}
eff536be ML	349
2f721d17 SB	350	if (flags & SPI_XFER_END) {
2f721d17 SB	351	spi_cs_deactivate(slave);
f9b6a157	352	}
38254f45 GL	353
	354	return 0;
	355	}
	356
	357	void spi_init(void)
	358	{
	359	}
	360
fc7a93c8 GL	361	static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
	362	{
	363	int ret;
	364
	365	/*
	366	* Some SPI devices require active chip-select over multiple
	367	* transactions, we achieve this using a GPIO. Still, the SPI
	368	* controller has to be configured to use one of its own chipselects.
	369	* To use this feature you have to call spi_setup_slave() with
	370	* cs = internal_cs \| (gpio << 8), and you have to use some unused
	371	* on this SPI controller cs between 0 and 3.
	372	*/
	373	if (cs > 3) {
	374	mxcs->gpio = cs >> 8;
	375	cs &= 3;
de5bf02c	376	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
fc7a93c8 GL	377	if (ret) {
	378	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	379	return -EINVAL;
	380	}
	381	} else {
	382	mxcs->gpio = -1;
	383	}
	384
	385	return cs;
	386	}
	387
d255bb0e HS	388	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	389	unsigned int max_hz, unsigned int mode)
38254f45	390	{
d255bb0e	391	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	392	int ret;
	393
	394	if (bus >= ARRAY_SIZE(spi_bases))
	395	return NULL;
	396
d3504fee	397	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
2f721d17 SB	398	if (!mxcs) {
2f721d17 SB	399	puts("mxc_spi: SPI Slave not allocated !\n");
fc7a93c8	400	return NULL;
2f721d17	401	}
38254f45	402
de5bf02c FE	403	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
de5bf02c FE	404
fc7a93c8 GL	405	ret = decode_cs(mxcs, cs);
	406	if (ret < 0) {
	407	free(mxcs);
d255bb0e	408	return NULL;
fc7a93c8 GL	409	}
	410
	411	cs = ret;
38254f45	412
d205ddcf SB	413	mxcs->base = spi_bases[bus];
d205ddcf SB	414
c9d59c7f	415	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
d205ddcf SB	416	if (ret) {
	417	printf("mxc_spi: cannot setup SPI controller\n");
	418	free(mxcs);
	419	return NULL;
	420	}
d255bb0e HS	421	return &mxcs->slave;
	422	}
	423
	424	void spi_free_slave(struct spi_slave *slave)
	425	{
f9b6a157 GL	426	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	427
	428	free(mxcs);
d255bb0e HS	429	}
	430
	431	int spi_claim_bus(struct spi_slave *slave)
	432	{
	433	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
ac87c17d	434	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
d255bb0e	435
ac87c17d	436	reg_write(&regs->rxdata, 1);
38254f45	437	udelay(1);
ac87c17d SB	438	reg_write(&regs->ctrl, mxcs->ctrl_reg);
	439	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	440	reg_write(&regs->intr, 0);
38254f45 GL	441
	442	return 0;
	443	}
d255bb0e HS	444
	445	void spi_release_bus(struct spi_slave *slave)
	446	{
	447	/* TODO: Shut the controller down */
	448	}