[people/ms/u-boot.git] / drivers / spi / mxs_spi.c

/*
 * Freescale i.MX28 SPI driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * NOTE: This driver only supports the SPI-controller chipselects,
 *       GPIO driven chipselects are not supported.
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>

#define	MXS_SPI_MAX_TIMEOUT	1000000
#define	MXS_SPI_PORT_OFFSET	0x2000
#define MXS_SSP_CHIPSELECT_MASK		0x00300000
#define MXS_SSP_CHIPSELECT_SHIFT	20

#define MXSSSP_SMALL_TRANSFER	512

/*
 * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
 *                            host. Use with utmost caution!
 *
 *                            Enabling this is not yet recommended since this
 *                            still doesn't support transfers to/from unaligned
 *                            addresses. Therefore this driver will not work
 *                            for example with saving environment. This is
 *                            caused by DMA alignment constraints on MXS.
 */

struct mxs_spi_slave {
	struct spi_slave	slave;
	uint32_t		max_khz;
	uint32_t		mode;
	struct mxs_ssp_regs	*regs;
	struct mxs_dma_desc	*desc;
};

static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxs_spi_slave, slave);
}

void spi_init(void)
{
}

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	/* MXS SPI: 4 ports and 3 chip selects maximum */
	if (bus > 3 || cs > 2)
		return 0;
	else
		return 1;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				  unsigned int max_hz, unsigned int mode)
{
	struct mxs_spi_slave *mxs_slave;
	uint32_t addr;
	struct mxs_ssp_regs *ssp_regs;
	int reg;
	struct mxs_dma_desc *desc;

	if (!spi_cs_is_valid(bus, cs)) {
		printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
		return NULL;
	}

	mxs_slave = malloc(sizeof(struct mxs_spi_slave));
	if (!mxs_slave)
		return NULL;

	desc = mxs_dma_desc_alloc();
	if (!desc)
		goto err_desc;

	if (mxs_dma_init_channel(bus))
		goto err_init;

	addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);

	mxs_slave->slave.bus = bus;
	mxs_slave->slave.cs = cs;
	mxs_slave->max_khz = max_hz / 1000;
	mxs_slave->mode = mode;
	mxs_slave->regs = (struct mxs_ssp_regs *)addr;
	mxs_slave->desc = desc;
	ssp_regs = mxs_slave->regs;

	reg = readl(&ssp_regs->hw_ssp_ctrl0);
	reg &= ~(MXS_SSP_CHIPSELECT_MASK);
	reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;

	writel(reg, &ssp_regs->hw_ssp_ctrl0);
	return &mxs_slave->slave;

err_init:
	mxs_dma_desc_free(desc);
err_desc:
	free(mxs_slave);
	return NULL;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	mxs_dma_desc_free(mxs_slave->desc);
	free(mxs_slave);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
	uint32_t reg = 0;

	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

	writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);

	reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	writel(reg, &ssp_regs->hw_ssp_ctrl1);

	writel(0, &ssp_regs->hw_ssp_cmd0);

	mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
}

static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
}

static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
{
	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
}

static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
			char *data, int length, int write, unsigned long flags)
{
	struct mxs_ssp_regs *ssp_regs = slave->regs;

	if (flags & SPI_XFER_BEGIN)
		mxs_spi_start_xfer(ssp_regs);

	while (length--) {
		/* We transfer 1 byte */
		writel(1, &ssp_regs->hw_ssp_xfer_size);

		if ((flags & SPI_XFER_END) && !length)
			mxs_spi_end_xfer(ssp_regs);

		if (write)
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
		else
			writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);

		writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);

		if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for start\n");
			return -ETIMEDOUT;
		}

		if (write)
			writel(*data++, &ssp_regs->hw_ssp_data);

		writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);

		if (!write) {
			if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
				SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
				printf("MXS SPI: Timeout waiting for data\n");
				return -ETIMEDOUT;
			}

			*data = readl(&ssp_regs->hw_ssp_data);
			data++;
		}

		if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
			SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
			printf("MXS SPI: Timeout waiting for finish\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
			char *data, int length, int write, unsigned long flags)
{
	struct mxs_dma_desc *desc = slave->desc;
	struct mxs_ssp_regs *ssp_regs = slave->regs;
	uint32_t ctrl0 = SSP_CTRL0_DATA_XFER;
	uint32_t cache_data_count;
	int dmach;

	memset(desc, 0, sizeof(struct mxs_dma_desc));
	desc->address = (dma_addr_t)desc;

	if (flags & SPI_XFER_BEGIN)
		ctrl0 |= SSP_CTRL0_LOCK_CS;
	if (flags & SPI_XFER_END)
		ctrl0 |= SSP_CTRL0_IGNORE_CRC;
	if (!write)
		ctrl0 |= SSP_CTRL0_READ;

	writel(length, &ssp_regs->hw_ssp_xfer_size);

	if (length % ARCH_DMA_MINALIGN)
		cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
	else
		cache_data_count = length;

	if (!write) {
		slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
		slave->desc->cmd.address = (dma_addr_t)data;
	} else {
		slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
		slave->desc->cmd.address = (dma_addr_t)data;

		/* Flush data to DRAM so DMA can pick them up */
		flush_dcache_range((uint32_t)data,
			(uint32_t)(data + cache_data_count));
	}

	slave->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
				(length << MXS_DMA_DESC_BYTES_OFFSET) |
				(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
				MXS_DMA_DESC_WAIT4END;

	slave->desc->cmd.pio_words[0] = ctrl0;

	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
	mxs_dma_desc_append(dmach, slave->desc);
	if (mxs_dma_go(dmach))
		return -EINVAL;

	/* The data arrived into DRAM, invalidate cache over them */
	if (!write) {
		invalidate_dcache_range((uint32_t)data,
			(uint32_t)(data + cache_data_count));
	}

	return 0;
}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
	int len = bitlen / 8;
	char dummy;
	int write = 0;
	char *data = NULL;

#ifdef CONFIG_MXS_SPI_DMA_ENABLE
	int dma = 1;
#else
	int dma = 0;
#endif

	if (bitlen == 0) {
		if (flags & SPI_XFER_END) {
			din = (void *)&dummy;
			len = 1;
		} else
			return 0;
	}

	/* Half-duplex only */
	if (din && dout)
		return -EINVAL;
	/* No data */
	if (!din && !dout)
		return 0;

	if (dout) {
		data = (char *)dout;
		write = 1;
	} else if (din) {
		data = (char *)din;
		write = 0;
	}

	/*
	 * Check for alignment, if the buffer is aligned, do DMA transfer,
	 * PIO otherwise. This is a temporary workaround until proper bounce
	 * buffer is in place.
	 */
	if (dma) {
		if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
			dma = 0;
		if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
			dma = 0;
	}

	if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
		return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
	} else {
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
		return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
	}
}
Commit	Line	Data
ec33de3d MV	1	/*
	2	* Freescale i.MX28 SPI driver
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	* NOTE: This driver only supports the SPI-controller chipselects,
	23	* GPIO driven chipselects are not supported.
	24	*/
	25
	26	#include <common.h>
	27	#include <malloc.h>
	28	#include <spi.h>
	29	#include <asm/errno.h>
	30	#include <asm/io.h>
	31	#include <asm/arch/clock.h>
	32	#include <asm/arch/imx-regs.h>
	33	#include <asm/arch/sys_proto.h>
7c5e6f7a	34	#include <asm/arch/dma.h>
ec33de3d MV	35
	36	#define MXS_SPI_MAX_TIMEOUT 1000000
	37	#define MXS_SPI_PORT_OFFSET 0x2000
148ca64f FE	38	#define MXS_SSP_CHIPSELECT_MASK 0x00300000
148ca64f FE	39	#define MXS_SSP_CHIPSELECT_SHIFT 20
ec33de3d	40
7c5e6f7a MV	41	#define MXSSSP_SMALL_TRANSFER 512
	42
	43	/*
	44	* CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
	45	* host. Use with utmost caution!
	46	*
	47	* Enabling this is not yet recommended since this
	48	* still doesn't support transfers to/from unaligned
	49	* addresses. Therefore this driver will not work
	50	* for example with saving environment. This is
	51	* caused by DMA alignment constraints on MXS.
	52	*/
	53
ec33de3d MV	54	struct mxs_spi_slave {
	55	struct spi_slave slave;
	56	uint32_t max_khz;
	57	uint32_t mode;
9c471142	58	struct mxs_ssp_regs *regs;
7c5e6f7a	59	struct mxs_dma_desc *desc;
ec33de3d MV	60	};
	61
	62	static inline struct mxs_spi_slave to_mxs_slave(struct spi_slave slave)
	63	{
	64	return container_of(slave, struct mxs_spi_slave, slave);
	65	}
	66
	67	void spi_init(void)
	68	{
	69	}
	70
79cb14ab FE	71	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	72	{
	73	/* MXS SPI: 4 ports and 3 chip selects maximum */
	74	if (bus > 3 \|\| cs > 2)
	75	return 0;
	76	else
	77	return 1;
	78	}
	79
ec33de3d MV	80	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
	81	unsigned int max_hz, unsigned int mode)
	82	{
	83	struct mxs_spi_slave *mxs_slave;
	84	uint32_t addr;
9c471142	85	struct mxs_ssp_regs *ssp_regs;
148ca64f	86	int reg;
7c5e6f7a	87	struct mxs_dma_desc *desc;
ec33de3d	88
79cb14ab FE	89	if (!spi_cs_is_valid(bus, cs)) {
79cb14ab FE	90	printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
ec33de3d MV	91	return NULL;
	92	}
	93
	94	mxs_slave = malloc(sizeof(struct mxs_spi_slave));
	95	if (!mxs_slave)
	96	return NULL;
	97
7c5e6f7a MV	98	desc = mxs_dma_desc_alloc();
	99	if (!desc)
	100	goto err_desc;
	101
	102	if (mxs_dma_init_channel(bus))
	103	goto err_init;
	104
ec33de3d MV	105	addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
	106
	107	mxs_slave->slave.bus = bus;
	108	mxs_slave->slave.cs = cs;
	109	mxs_slave->max_khz = max_hz / 1000;
	110	mxs_slave->mode = mode;
9c471142	111	mxs_slave->regs = (struct mxs_ssp_regs *)addr;
7c5e6f7a	112	mxs_slave->desc = desc;
148ca64f	113	ssp_regs = mxs_slave->regs;
ec33de3d	114
148ca64f FE	115	reg = readl(&ssp_regs->hw_ssp_ctrl0);
	116	reg &= ~(MXS_SSP_CHIPSELECT_MASK);
	117	reg \|= cs << MXS_SSP_CHIPSELECT_SHIFT;
	118
	119	writel(reg, &ssp_regs->hw_ssp_ctrl0);
ec33de3d	120	return &mxs_slave->slave;
7c5e6f7a MV	121
	122	err_init:
	123	mxs_dma_desc_free(desc);
	124	err_desc:
	125	free(mxs_slave);
	126	return NULL;
ec33de3d MV	127	}
	128
	129	void spi_free_slave(struct spi_slave *slave)
	130	{
	131	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
7c5e6f7a	132	mxs_dma_desc_free(mxs_slave->desc);
ec33de3d MV	133	free(mxs_slave);
	134	}
	135
	136	int spi_claim_bus(struct spi_slave *slave)
	137	{
	138	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
9c471142	139	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
ec33de3d MV	140	uint32_t reg = 0;
	141
	142	mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
	143
	144	writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
	145
	146	reg = SSP_CTRL1_SSP_MODE_SPI \| SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
	147	reg \|= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
	148	reg \|= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
	149	writel(reg, &ssp_regs->hw_ssp_ctrl1);
	150
	151	writel(0, &ssp_regs->hw_ssp_cmd0);
	152
	153	mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
	154
	155	return 0;
	156	}
	157
	158	void spi_release_bus(struct spi_slave *slave)
	159	{
	160	}
	161
9c471142	162	static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
ec33de3d MV	163	{
	164	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
	165	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
	166	}
	167
9c471142	168	static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
ec33de3d MV	169	{
	170	writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
	171	writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
	172	}
	173
ccd4d5a0 MV	174	static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
ccd4d5a0 MV	175	char *data, int length, int write, unsigned long flags)
ec33de3d	176	{
9c471142	177	struct mxs_ssp_regs *ssp_regs = slave->regs;
c7065fa8	178
ec33de3d MV	179	if (flags & SPI_XFER_BEGIN)
	180	mxs_spi_start_xfer(ssp_regs);
	181
ccd4d5a0	182	while (length--) {
ec33de3d MV	183	/* We transfer 1 byte */
	184	writel(1, &ssp_regs->hw_ssp_xfer_size);
	185
ccd4d5a0	186	if ((flags & SPI_XFER_END) && !length)
ec33de3d MV	187	mxs_spi_end_xfer(ssp_regs);
ec33de3d MV	188
c7065fa8	189	if (write)
ec33de3d MV	190	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
	191	else
	192	writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
	193
	194	writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
	195
	196	if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
	197	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
	198	printf("MXS SPI: Timeout waiting for start\n");
d9fb6a4c	199	return -ETIMEDOUT;
ec33de3d MV	200	}
ec33de3d MV	201
c7065fa8 MV	202	if (write)
c7065fa8 MV	203	writel(*data++, &ssp_regs->hw_ssp_data);
ec33de3d MV	204
	205	writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
	206
c7065fa8	207	if (!write) {
ec33de3d MV	208	if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
	209	SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
	210	printf("MXS SPI: Timeout waiting for data\n");
d9fb6a4c	211	return -ETIMEDOUT;
ec33de3d MV	212	}
ec33de3d MV	213
c7065fa8 MV	214	*data = readl(&ssp_regs->hw_ssp_data);
c7065fa8 MV	215	data++;
ec33de3d MV	216	}
	217
	218	if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
	219	SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
	220	printf("MXS SPI: Timeout waiting for finish\n");
d9fb6a4c	221	return -ETIMEDOUT;
ec33de3d MV	222	}
	223	}
	224
	225	return 0;
ccd4d5a0 MV	226	}
ccd4d5a0 MV	227
7c5e6f7a MV	228	static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
	229	char *data, int length, int write, unsigned long flags)
	230	{
	231	struct mxs_dma_desc *desc = slave->desc;
9c471142	232	struct mxs_ssp_regs *ssp_regs = slave->regs;
7c5e6f7a MV	233	uint32_t ctrl0 = SSP_CTRL0_DATA_XFER;
	234	uint32_t cache_data_count;
	235	int dmach;
	236
	237	memset(desc, 0, sizeof(struct mxs_dma_desc));
	238	desc->address = (dma_addr_t)desc;
	239
	240	if (flags & SPI_XFER_BEGIN)
	241	ctrl0 \|= SSP_CTRL0_LOCK_CS;
	242	if (flags & SPI_XFER_END)
	243	ctrl0 \|= SSP_CTRL0_IGNORE_CRC;
	244	if (!write)
	245	ctrl0 \|= SSP_CTRL0_READ;
	246
	247	writel(length, &ssp_regs->hw_ssp_xfer_size);
	248
	249	if (length % ARCH_DMA_MINALIGN)
	250	cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
	251	else
	252	cache_data_count = length;
	253
	254	if (!write) {
	255	slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
	256	slave->desc->cmd.address = (dma_addr_t)data;
	257	} else {
	258	slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
	259	slave->desc->cmd.address = (dma_addr_t)data;
	260
	261	/* Flush data to DRAM so DMA can pick them up */
	262	flush_dcache_range((uint32_t)data,
	263	(uint32_t)(data + cache_data_count));
	264	}
	265
	266	slave->desc->cmd.data \|= MXS_DMA_DESC_IRQ \| MXS_DMA_DESC_DEC_SEM \|
	267	(length << MXS_DMA_DESC_BYTES_OFFSET) \|
	268	(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) \|
	269	MXS_DMA_DESC_WAIT4END;
	270
	271	slave->desc->cmd.pio_words[0] = ctrl0;
	272
	273	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
	274	mxs_dma_desc_append(dmach, slave->desc);
	275	if (mxs_dma_go(dmach))
	276	return -EINVAL;
	277
	278	/* The data arrived into DRAM, invalidate cache over them */
	279	if (!write) {
	280	invalidate_dcache_range((uint32_t)data,
	281	(uint32_t)(data + cache_data_count));
	282	}
	283
	284	return 0;
	285	}
	286
ccd4d5a0 MV	287	int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	288	const void dout, void din, unsigned long flags)
	289	{
	290	struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
9c471142	291	struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
ccd4d5a0 MV	292	int len = bitlen / 8;
	293	char dummy;
	294	int write = 0;
	295	char *data = NULL;
	296
7c5e6f7a MV	297	#ifdef CONFIG_MXS_SPI_DMA_ENABLE
	298	int dma = 1;
	299	#else
	300	int dma = 0;
	301	#endif
	302
ccd4d5a0 MV	303	if (bitlen == 0) {
	304	if (flags & SPI_XFER_END) {
	305	din = (void *)&dummy;
	306	len = 1;
	307	} else
	308	return 0;
	309	}
	310
	311	/* Half-duplex only */
	312	if (din && dout)
	313	return -EINVAL;
	314	/* No data */
	315	if (!din && !dout)
	316	return 0;
	317
	318	if (dout) {
	319	data = (char *)dout;
	320	write = 1;
	321	} else if (din) {
	322	data = (char *)din;
	323	write = 0;
	324	}
	325
7c5e6f7a MV	326	/*
	327	* Check for alignment, if the buffer is aligned, do DMA transfer,
	328	* PIO otherwise. This is a temporary workaround until proper bounce
	329	* buffer is in place.
	330	*/
	331	if (dma) {
	332	if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
	333	dma = 0;
	334	if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
	335	dma = 0;
	336	}
	337
	338	if (!dma \|\| (len < MXSSSP_SMALL_TRANSFER)) {
	339	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
	340	return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
	341	} else {
	342	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
	343	return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
	344	}
ec33de3d	345	}