[people/ms/u-boot.git] / drivers / spi / omap3_spi.h

/*
 * Register definitions for the OMAP3 McSPI Controller
 *
 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
 *
 * Parts taken from linux/drivers/spi/omap2_mcspi.c
 * Copyright (C) 2005, 2006 Nokia Corporation
 *
 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _OMAP3_SPI_H_
#define _OMAP3_SPI_H_

#ifdef CONFIG_AM33XX
#define OMAP3_MCSPI1_BASE	0x48030100
#define OMAP3_MCSPI2_BASE	0x481A0100
#else
#define OMAP3_MCSPI1_BASE	0x48098000
#define OMAP3_MCSPI2_BASE	0x4809A000
#define OMAP3_MCSPI3_BASE	0x480B8000
#define OMAP3_MCSPI4_BASE	0x480BA000
#endif

#define OMAP3_MCSPI_MAX_FREQ	48000000

/* OMAP3 McSPI registers */
struct mcspi_channel {
	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
};

struct mcspi {
	unsigned char res1[0x10];
	unsigned int sysconfig;		/* 0x10 */
	unsigned int sysstatus;		/* 0x14 */
	unsigned int irqstatus;		/* 0x18 */
	unsigned int irqenable;		/* 0x1C */
	unsigned int wakeupenable;	/* 0x20 */
	unsigned int syst;		/* 0x24 */
	unsigned int modulctrl;		/* 0x28 */
	struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
					/* channel1: 0x40 - 0x50, bus 0 & 1 */
					/* channel2: 0x54 - 0x64, bus 0 & 1 */
					/* channel3: 0x68 - 0x78, bus 0 */
};

/* per-register bitmasks */
#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	(1 << 0)
#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)

#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)

#define OMAP3_MCSPI_MODULCTRL_SINGLE	(1 << 0)
#define OMAP3_MCSPI_MODULCTRL_MS	(1 << 2)
#define OMAP3_MCSPI_MODULCTRL_STEST	(1 << 3)

#define OMAP3_MCSPI_CHCONF_PHA		(1 << 0)
#define OMAP3_MCSPI_CHCONF_POL		(1 << 1)
#define OMAP3_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
#define OMAP3_MCSPI_CHCONF_EPOL		(1 << 6)
#define OMAP3_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	(0x01 << 12)
#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	(0x02 << 12)
#define OMAP3_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
#define OMAP3_MCSPI_CHCONF_DMAW		(1 << 14)
#define OMAP3_MCSPI_CHCONF_DMAR		(1 << 15)
#define OMAP3_MCSPI_CHCONF_DPE0		(1 << 16)
#define OMAP3_MCSPI_CHCONF_DPE1		(1 << 17)
#define OMAP3_MCSPI_CHCONF_IS		(1 << 18)
#define OMAP3_MCSPI_CHCONF_TURBO	(1 << 19)
#define OMAP3_MCSPI_CHCONF_FORCE	(1 << 20)

#define OMAP3_MCSPI_CHSTAT_RXS		(1 << 0)
#define OMAP3_MCSPI_CHSTAT_TXS		(1 << 1)
#define OMAP3_MCSPI_CHSTAT_EOT		(1 << 2)

#define OMAP3_MCSPI_CHCTRL_EN		(1 << 0)
#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)

#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	(1 << 0)

struct omap3_spi_slave {
	struct spi_slave slave;
	struct mcspi *regs;
	unsigned int freq;
	unsigned int mode;
};

static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
{
	return container_of(slave, struct omap3_spi_slave, slave);
}

int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp,
			u8 *rxp, unsigned long flags);
int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
		    unsigned long flags);
int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
		   unsigned long flags);

#endif /* _OMAP3_SPI_H_ */
Commit	Line	Data
53736baa DB	1	/*
	2	* Register definitions for the OMAP3 McSPI Controller
	3	*
	4	* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
	5	*
	6	* Parts taken from linux/drivers/spi/omap2_mcspi.c
	7	* Copyright (C) 2005, 2006 Nokia Corporation
	8	*
	9	* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
53736baa DB	12	*/
	13
	14	#ifndef _OMAP3_SPI_H_
	15	#define _OMAP3_SPI_H_
	16
4c0620bf TR	17	#ifdef CONFIG_AM33XX
	18	#define OMAP3_MCSPI1_BASE 0x48030100
	19	#define OMAP3_MCSPI2_BASE 0x481A0100
	20	#else
53736baa DB	21	#define OMAP3_MCSPI1_BASE 0x48098000
	22	#define OMAP3_MCSPI2_BASE 0x4809A000
	23	#define OMAP3_MCSPI3_BASE 0x480B8000
	24	#define OMAP3_MCSPI4_BASE 0x480BA000
4c0620bf	25	#endif
53736baa DB	26
	27	#define OMAP3_MCSPI_MAX_FREQ 48000000
	28
	29	/* OMAP3 McSPI registers */
	30	struct mcspi_channel {
	31	unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
	32	unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
	33	unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
	34	unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
	35	unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
	36	};
	37
	38	struct mcspi {
	39	unsigned char res1[0x10];
	40	unsigned int sysconfig; /* 0x10 */
	41	unsigned int sysstatus; /* 0x14 */
	42	unsigned int irqstatus; /* 0x18 */
	43	unsigned int irqenable; /* 0x1C */
	44	unsigned int wakeupenable; /* 0x20 */
	45	unsigned int syst; /* 0x24 */
	46	unsigned int modulctrl; /* 0x28 */
	47	struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
	48	/* channel1: 0x40 - 0x50, bus 0 & 1 */
	49	/* channel2: 0x54 - 0x64, bus 0 & 1 */
	50	/* channel3: 0x68 - 0x78, bus 0 */
	51	};
	52
	53	/* per-register bitmasks */
	54	#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
	55	#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
	56	#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
	57	#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
	58
	59	#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
	60
	61	#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0)
	62	#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2)
	63	#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3)
	64
	65	#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
	66	#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
	67	#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
	68	#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6)
	69	#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
	70	#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
	71	#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
	72	#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
	73	#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14)
	74	#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15)
	75	#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16)
	76	#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17)
	77	#define OMAP3_MCSPI_CHCONF_IS (1 << 18)
	78	#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19)
	79	#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20)
	80
	81	#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
	82	#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
	83	#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
	84
	85	#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
cc1182be	86	#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
53736baa DB	87
	88	#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
	89
	90	struct omap3_spi_slave {
	91	struct spi_slave slave;
	92	struct mcspi *regs;
	93	unsigned int freq;
	94	unsigned int mode;
	95	};
	96
	97	static inline struct omap3_spi_slave to_omap3_spi(struct spi_slave slave)
	98	{
	99	return container_of(slave, struct omap3_spi_slave, slave);
	100	}
	101
08b5ab07	102	int omap3_spi_txrx(struct spi_slave slave, unsigned int len, const u8 txp,
08b5ab07	103	u8 *rxp, unsigned long flags);
53736baa DB	104	int omap3_spi_write(struct spi_slave slave, unsigned int len, const u8 txp,
	105	unsigned long flags);
	106	int omap3_spi_read(struct spi_slave slave, unsigned int len, u8 rxp,
	107	unsigned long flags);
	108
	109	#endif /* _OMAP3_SPI_H_ */