[thirdparty/u-boot.git] / drivers / spi / pl022_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2012
 * Armando Visconti, STMicroelectronics, armando.visconti@st.com.
 *
 * (C) Copyright 2018
 * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
 *
 * Driver for ARM PL022 SPI Controller.
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <fdtdec.h>
#include <linux/io.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <spi.h>
#include <linux/printk.h>

#define SSP_CR0		0x000
#define SSP_CR1		0x004
#define SSP_DR		0x008
#define SSP_SR		0x00C
#define SSP_CPSR	0x010
#define SSP_IMSC	0x014
#define SSP_RIS		0x018
#define SSP_MIS		0x01C
#define SSP_ICR		0x020
#define SSP_DMACR	0x024
#define SSP_CSR		0x030 /* vendor extension */
#define SSP_ITCR	0x080
#define SSP_ITIP	0x084
#define SSP_ITOP	0x088
#define SSP_TDR		0x08C

#define SSP_PID0	0xFE0
#define SSP_PID1	0xFE4
#define SSP_PID2	0xFE8
#define SSP_PID3	0xFEC

#define SSP_CID0	0xFF0
#define SSP_CID1	0xFF4
#define SSP_CID2	0xFF8
#define SSP_CID3	0xFFC

/* SSP Control Register 0  - SSP_CR0 */
#define SSP_CR0_SPO		(0x1 << 6)
#define SSP_CR0_SPH		(0x1 << 7)
#define SSP_CR0_BIT_MODE(x)	((x) - 1)
#define SSP_SCR_MIN		(0x00)
#define SSP_SCR_MAX		(0xFF)
#define SSP_SCR_SHFT		8
#define DFLT_CLKRATE		2

/* SSP Control Register 1  - SSP_CR1 */
#define SSP_CR1_MASK_SSE	(0x1 << 1)

#define SSP_CPSR_MIN		(0x02)
#define SSP_CPSR_MAX		(0xFE)
#define DFLT_PRESCALE		(0x40)

/* SSP Status Register - SSP_SR */
#define SSP_SR_MASK_TFE		(0x1 << 0) /* Transmit FIFO empty */
#define SSP_SR_MASK_TNF		(0x1 << 1) /* Transmit FIFO not full */
#define SSP_SR_MASK_RNE		(0x1 << 2) /* Receive FIFO not empty */
#define SSP_SR_MASK_RFF		(0x1 << 3) /* Receive FIFO full */
#define SSP_SR_MASK_BSY		(0x1 << 4) /* Busy Flag */

struct pl022_spi_pdata {
	fdt_addr_t addr;
	fdt_size_t size;
	unsigned int freq;
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct gpio_desc cs_gpio;
#endif
};

struct pl022_spi_slave {
	void *base;
	unsigned int freq;
};

/*
 * ARM PL022 exists in different 'flavors'.
 * This drivers currently support the standard variant (0x00041022), that has a
 * 16bit wide and 8 locations deep TX/RX FIFO.
 */
static int pl022_is_supported(struct pl022_spi_slave *ps)
{
	/* PL022 version is 0x00041022 */
	if ((readw(ps->base + SSP_PID0) == 0x22) &&
	    (readw(ps->base + SSP_PID1) == 0x10) &&
	    ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
	    (readw(ps->base + SSP_PID3) == 0x00))
		return 1;

	return 0;
}

static int pl022_spi_probe(struct udevice *bus)
{
	struct pl022_spi_pdata *plat = dev_get_plat(bus);
	struct pl022_spi_slave *ps = dev_get_priv(bus);

	ps->base = ioremap(plat->addr, plat->size);
	ps->freq = plat->freq;

	/* Check the PL022 version */
	if (!pl022_is_supported(ps))
		return -ENOTSUPP;

	/* 8 bits per word, high polarity and default clock rate */
	writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
	writew(DFLT_PRESCALE, ps->base + SSP_CPSR);

	return 0;
}

static void pl022_spi_flush(struct pl022_spi_slave *ps)
{
	do {
		while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
			readw(ps->base + SSP_DR);
	} while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
}

static int pl022_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 reg;

	/* Enable the SPI hardware */
	reg = readw(ps->base + SSP_CR1);
	reg |= SSP_CR1_MASK_SSE;
	writew(reg, ps->base + SSP_CR1);

	pl022_spi_flush(ps);

	return 0;
}

static int pl022_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 reg;

	pl022_spi_flush(ps);

	/* Disable the SPI hardware */
	reg = readw(ps->base + SSP_CR1);
	reg &= ~SSP_CR1_MASK_SSE;
	writew(reg, ps->base + SSP_CR1);

	return 0;
}

static void pl022_spi_set_cs(struct udevice *dev, bool on)
{
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct udevice *bus = dev->parent;
	struct pl022_spi_pdata *plat = dev_get_plat(bus);

	if (dm_gpio_is_valid(&plat->cs_gpio))
		dm_gpio_set_value(&plat->cs_gpio, on ? 1 : 0);
#endif
}

static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
			  const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u32		len_tx = 0, len_rx = 0, len;
	u32		ret = 0;
	const u8	*txp = dout;
	u8		*rxp = din, value;

	if (bitlen == 0)
		/* Finish any previously submitted transfers */
		goto done;

	/*
	 * TODO: The controller can do non-multiple-of-8 bit
	 * transfers, but this driver currently doesn't support it.
	 *
	 * It's also not clear how such transfers are supposed to be
	 * represented as a stream of bytes...this is a limitation of
	 * the current SPI interface.
	 */
	if (bitlen % 8) {
		/* Errors always terminate an ongoing transfer */
		flags |= SPI_XFER_END;
		ret = -1;
		goto done;
	}

	if (flags & SPI_XFER_BEGIN)
		pl022_spi_set_cs(dev, true);

	len = bitlen / 8;

	while (len_tx < len) {
		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
			value = txp ? *txp++ : 0;
			writew(value, ps->base + SSP_DR);
			len_tx++;
		}

		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
			value = readw(ps->base + SSP_DR);
			if (rxp)
				*rxp++ = value;
			len_rx++;
		}
	}

	while (len_rx < len_tx) {
		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
			value = readw(ps->base + SSP_DR);
			if (rxp)
				*rxp++ = value;
			len_rx++;
		}
	}

done:
	if (flags & SPI_XFER_END)
		pl022_spi_set_cs(dev, false);

	return ret;
}

static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
{
	return rate / (cpsdvsr * (1 + scr));
}

static int pl022_spi_set_speed(struct udevice *bus, uint speed)
{
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
	    best_cpsr = cpsr;
	u32 min, max, best_freq = 0, tmp;
	u32 rate = ps->freq;
	bool found = false;

	max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
	min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);

	if (speed > max || speed < min) {
		pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
		       speed, min, max);
		return -EINVAL;
	}

	while (cpsr <= SSP_CPSR_MAX && !found) {
		while (scr <= SSP_SCR_MAX) {
			tmp = spi_rate(rate, cpsr, scr);

			if (abs(speed - tmp) < abs(speed - best_freq)) {
				best_freq = tmp;
				best_cpsr = cpsr;
				best_scr = scr;

				if (tmp == speed) {
					found = true;
					break;
				}
			}

			scr++;
		}
		cpsr += 2;
		scr = SSP_SCR_MIN;
	}

	writew(best_cpsr, ps->base + SSP_CPSR);
	cr0 = readw(ps->base + SSP_CR0);
	writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);

	return 0;
}

static int pl022_spi_set_mode(struct udevice *bus, uint mode)
{
	struct pl022_spi_slave *ps = dev_get_priv(bus);
	u16 reg;

	reg = readw(ps->base + SSP_CR0);
	reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
	if (mode & SPI_CPHA)
		reg |= SSP_CR0_SPH;
	if (mode & SPI_CPOL)
		reg |= SSP_CR0_SPO;
	writew(reg, ps->base + SSP_CR0);

	return 0;
}

static int pl022_cs_info(struct udevice *bus, uint cs,
			 struct spi_cs_info *info)
{
	return 0;
}

static const struct dm_spi_ops pl022_spi_ops = {
	.claim_bus      = pl022_spi_claim_bus,
	.release_bus    = pl022_spi_release_bus,
	.xfer           = pl022_spi_xfer,
	.set_speed      = pl022_spi_set_speed,
	.set_mode       = pl022_spi_set_mode,
	.cs_info        = pl022_cs_info,
};

#if CONFIG_IS_ENABLED(OF_REAL)
static int pl022_spi_of_to_plat(struct udevice *bus)
{
	struct pl022_spi_pdata *plat = dev_get_plat(bus);
	const void *fdt = gd->fdt_blob;
	int node = dev_of_offset(bus);
	struct clk clkdev;
	int ret;

	plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);

	ret = clk_get_by_index(bus, 0, &clkdev);
	if (ret)
		return ret;

	plat->freq = clk_get_rate(&clkdev);

#if CONFIG_IS_ENABLED(DM_GPIO)
	ret = gpio_request_by_name(bus, "cs-gpios", 0, &plat->cs_gpio,
				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
	if (ret < 0 && ret != -ENOENT)
		return ret;
#endif

	return 0;
}

static const struct udevice_id pl022_spi_ids[] = {
	{ .compatible = "arm,pl022" },
	{ }
};
#endif

U_BOOT_DRIVER(pl022_spi) = {
	.name   = "pl022_spi",
	.id     = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_REAL)
	.of_match = pl022_spi_ids,
	.of_to_plat = pl022_spi_of_to_plat,
#endif
	.ops    = &pl022_spi_ops,
	.plat_auto	= sizeof(struct pl022_spi_pdata),
	.priv_auto	= sizeof(struct pl022_spi_slave),
	.probe  = pl022_spi_probe,
};
Commit	Line	Data
8a4791fa QS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2012
eae488b7	4	* Armando Visconti, STMicroelectronics, armando.visconti@st.com.
8a4791fa QS	5	*
	6	* (C) Copyright 2018
	7	* Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
	8	*
	9	* Driver for ARM PL022 SPI Controller.
	10	*/
	11
8a4791fa	12	#include <clk.h>
d678a59d	13	#include <common.h>
8a4791fa	14	#include <dm.h>
47d9ae54	15	#include <dm/device_compat.h>
03612861	16	#include <fdtdec.h>
8a4791fa	17	#include <linux/io.h>
401d1c4f	18	#include <asm/global_data.h>
47d9ae54	19	#include <asm/gpio.h>
8a4791fa	20	#include <spi.h>
1e94b46f	21	#include <linux/printk.h>
8a4791fa QS	22
	23	#define SSP_CR0 0x000
	24	#define SSP_CR1 0x004
	25	#define SSP_DR 0x008
	26	#define SSP_SR 0x00C
	27	#define SSP_CPSR 0x010
	28	#define SSP_IMSC 0x014
	29	#define SSP_RIS 0x018
	30	#define SSP_MIS 0x01C
	31	#define SSP_ICR 0x020
	32	#define SSP_DMACR 0x024
	33	#define SSP_CSR 0x030 /* vendor extension */
	34	#define SSP_ITCR 0x080
	35	#define SSP_ITIP 0x084
	36	#define SSP_ITOP 0x088
	37	#define SSP_TDR 0x08C
	38
	39	#define SSP_PID0 0xFE0
	40	#define SSP_PID1 0xFE4
	41	#define SSP_PID2 0xFE8
	42	#define SSP_PID3 0xFEC
	43
	44	#define SSP_CID0 0xFF0
	45	#define SSP_CID1 0xFF4
	46	#define SSP_CID2 0xFF8
	47	#define SSP_CID3 0xFFC
	48
	49	/* SSP Control Register 0 - SSP_CR0 */
	50	#define SSP_CR0_SPO (0x1 << 6)
	51	#define SSP_CR0_SPH (0x1 << 7)
	52	#define SSP_CR0_BIT_MODE(x) ((x) - 1)
	53	#define SSP_SCR_MIN (0x00)
	54	#define SSP_SCR_MAX (0xFF)
	55	#define SSP_SCR_SHFT 8
	56	#define DFLT_CLKRATE 2
	57
	58	/* SSP Control Register 1 - SSP_CR1 */
	59	#define SSP_CR1_MASK_SSE (0x1 << 1)
	60
	61	#define SSP_CPSR_MIN (0x02)
	62	#define SSP_CPSR_MAX (0xFE)
	63	#define DFLT_PRESCALE (0x40)
	64
	65	/* SSP Status Register - SSP_SR */
	66	#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
	67	#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
	68	#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
	69	#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
	70	#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
	71
03612861 SH	72	struct pl022_spi_pdata {
	73	fdt_addr_t addr;
	74	fdt_size_t size;
	75	unsigned int freq;
47d9ae54 LF	76	#if CONFIG_IS_ENABLED(DM_GPIO)
	77	struct gpio_desc cs_gpio;
	78	#endif
03612861 SH	79	};
03612861 SH	80
8a4791fa QS	81	struct pl022_spi_slave {
8a4791fa QS	82	void *base;
8a4791fa	83	unsigned int freq;
8a4791fa QS	84	};
	85
	86	/*
	87	* ARM PL022 exists in different 'flavors'.
	88	* This drivers currently support the standard variant (0x00041022), that has a
	89	* 16bit wide and 8 locations deep TX/RX FIFO.
	90	*/
	91	static int pl022_is_supported(struct pl022_spi_slave *ps)
	92	{
	93	/* PL022 version is 0x00041022 */
	94	if ((readw(ps->base + SSP_PID0) == 0x22) &&
	95	(readw(ps->base + SSP_PID1) == 0x10) &&
	96	((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
	97	(readw(ps->base + SSP_PID3) == 0x00))
	98	return 1;
	99
	100	return 0;
	101	}
	102
8a4791fa QS	103	static int pl022_spi_probe(struct udevice *bus)
8a4791fa QS	104	{
c69cda25	105	struct pl022_spi_pdata *plat = dev_get_plat(bus);
8a4791fa QS	106	struct pl022_spi_slave *ps = dev_get_priv(bus);
	107
	108	ps->base = ioremap(plat->addr, plat->size);
8a4791fa	109	ps->freq = plat->freq;
8a4791fa QS	110
	111	/* Check the PL022 version */
	112	if (!pl022_is_supported(ps))
	113	return -ENOTSUPP;
	114
	115	/* 8 bits per word, high polarity and default clock rate */
	116	writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
	117	writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
	118
	119	return 0;
	120	}
	121
47c32734	122	static void pl022_spi_flush(struct pl022_spi_slave *ps)
8a4791fa QS	123	{
	124	do {
	125	while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
	126	readw(ps->base + SSP_DR);
	127	} while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
	128	}
	129
	130	static int pl022_spi_claim_bus(struct udevice *dev)
	131	{
	132	struct udevice *bus = dev->parent;
	133	struct pl022_spi_slave *ps = dev_get_priv(bus);
	134	u16 reg;
	135
	136	/* Enable the SPI hardware */
	137	reg = readw(ps->base + SSP_CR1);
	138	reg \|= SSP_CR1_MASK_SSE;
	139	writew(reg, ps->base + SSP_CR1);
	140
47c32734	141	pl022_spi_flush(ps);
8a4791fa QS	142
	143	return 0;
	144	}
	145
	146	static int pl022_spi_release_bus(struct udevice *dev)
	147	{
	148	struct udevice *bus = dev->parent;
	149	struct pl022_spi_slave *ps = dev_get_priv(bus);
	150	u16 reg;
	151
47c32734	152	pl022_spi_flush(ps);
8a4791fa QS	153
	154	/* Disable the SPI hardware */
	155	reg = readw(ps->base + SSP_CR1);
	156	reg &= ~SSP_CR1_MASK_SSE;
	157	writew(reg, ps->base + SSP_CR1);
	158
	159	return 0;
	160	}
	161
47d9ae54 LF	162	static void pl022_spi_set_cs(struct udevice *dev, bool on)
	163	{
	164	#if CONFIG_IS_ENABLED(DM_GPIO)
	165	struct udevice *bus = dev->parent;
	166	struct pl022_spi_pdata *plat = dev_get_plat(bus);
	167
	168	if (dm_gpio_is_valid(&plat->cs_gpio))
	169	dm_gpio_set_value(&plat->cs_gpio, on ? 1 : 0);
	170	#endif
	171	}
	172
8a4791fa QS	173	static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
	174	const void dout, void din, unsigned long flags)
	175	{
	176	struct udevice *bus = dev->parent;
	177	struct pl022_spi_slave *ps = dev_get_priv(bus);
	178	u32 len_tx = 0, len_rx = 0, len;
	179	u32 ret = 0;
	180	const u8 *txp = dout;
	181	u8 *rxp = din, value;
	182
	183	if (bitlen == 0)
	184	/* Finish any previously submitted transfers */
47d9ae54	185	goto done;
8a4791fa QS	186
	187	/*
	188	* TODO: The controller can do non-multiple-of-8 bit
	189	* transfers, but this driver currently doesn't support it.
	190	*
	191	* It's also not clear how such transfers are supposed to be
	192	* represented as a stream of bytes...this is a limitation of
	193	* the current SPI interface.
	194	*/
	195	if (bitlen % 8) {
	196	/* Errors always terminate an ongoing transfer */
	197	flags \|= SPI_XFER_END;
47d9ae54 LF	198	ret = -1;
47d9ae54 LF	199	goto done;
8a4791fa QS	200	}
8a4791fa QS	201
47d9ae54 LF	202	if (flags & SPI_XFER_BEGIN)
	203	pl022_spi_set_cs(dev, true);
	204
8a4791fa QS	205	len = bitlen / 8;
	206
	207	while (len_tx < len) {
	208	if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
	209	value = txp ? *txp++ : 0;
	210	writew(value, ps->base + SSP_DR);
	211	len_tx++;
	212	}
	213
	214	if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
	215	value = readw(ps->base + SSP_DR);
	216	if (rxp)
	217	*rxp++ = value;
	218	len_rx++;
	219	}
	220	}
	221
	222	while (len_rx < len_tx) {
	223	if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
	224	value = readw(ps->base + SSP_DR);
	225	if (rxp)
	226	*rxp++ = value;
	227	len_rx++;
	228	}
	229	}
	230
47d9ae54 LF	231	done:
	232	if (flags & SPI_XFER_END)
	233	pl022_spi_set_cs(dev, false);
	234
8a4791fa QS	235	return ret;
	236	}
	237
	238	static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
	239	{
	240	return rate / (cpsdvsr * (1 + scr));
	241	}
	242
	243	static int pl022_spi_set_speed(struct udevice *bus, uint speed)
	244	{
	245	struct pl022_spi_slave *ps = dev_get_priv(bus);
	246	u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
	247	best_cpsr = cpsr;
	248	u32 min, max, best_freq = 0, tmp;
8a4791fa	249	u32 rate = ps->freq;
8a4791fa QS	250	bool found = false;
	251
	252	max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
	253	min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
	254
	255	if (speed > max \|\| speed < min) {
	256	pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
	257	speed, min, max);
	258	return -EINVAL;
	259	}
	260
	261	while (cpsr <= SSP_CPSR_MAX && !found) {
	262	while (scr <= SSP_SCR_MAX) {
	263	tmp = spi_rate(rate, cpsr, scr);
	264
	265	if (abs(speed - tmp) < abs(speed - best_freq)) {
	266	best_freq = tmp;
	267	best_cpsr = cpsr;
	268	best_scr = scr;
	269
	270	if (tmp == speed) {
	271	found = true;
	272	break;
	273	}
	274	}
	275
	276	scr++;
	277	}
	278	cpsr += 2;
	279	scr = SSP_SCR_MIN;
	280	}
	281
	282	writew(best_cpsr, ps->base + SSP_CPSR);
	283	cr0 = readw(ps->base + SSP_CR0);
	284	writew(cr0 \| (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
	285
	286	return 0;
	287	}
	288
	289	static int pl022_spi_set_mode(struct udevice *bus, uint mode)
	290	{
	291	struct pl022_spi_slave *ps = dev_get_priv(bus);
	292	u16 reg;
	293
	294	reg = readw(ps->base + SSP_CR0);
	295	reg &= ~(SSP_CR0_SPH \| SSP_CR0_SPO);
	296	if (mode & SPI_CPHA)
	297	reg \|= SSP_CR0_SPH;
	298	if (mode & SPI_CPOL)
	299	reg \|= SSP_CR0_SPO;
	300	writew(reg, ps->base + SSP_CR0);
	301
	302	return 0;
	303	}
	304
	305	static int pl022_cs_info(struct udevice *bus, uint cs,
	306	struct spi_cs_info *info)
	307	{
	308	return 0;
	309	}
	310
	311	static const struct dm_spi_ops pl022_spi_ops = {
	312	.claim_bus = pl022_spi_claim_bus,
	313	.release_bus = pl022_spi_release_bus,
314	.xfer = pl022_spi_xfer,
315	.set_speed = pl022_spi_set_speed,
316	.set_mode = pl022_spi_set_mode,
317	.cs_info = pl022_cs_info,
318	};
319
95397385	320	#if CONFIG_IS_ENABLED(OF_REAL)
d1998a9f	321	static int pl022_spi_of_to_plat(struct udevice *bus)
3deb1f73	322	{
0fd3d911	323	struct pl022_spi_pdata *plat = dev_get_plat(bus);
3deb1f73 JT	324	const void *fdt = gd->fdt_blob;
	325	int node = dev_of_offset(bus);
	326	struct clk clkdev;
	327	int ret;
	328
	329	plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
	330
	331	ret = clk_get_by_index(bus, 0, &clkdev);
	332	if (ret)
	333	return ret;
	334
	335	plat->freq = clk_get_rate(&clkdev);
	336
47d9ae54 LF	337	#if CONFIG_IS_ENABLED(DM_GPIO)
	338	ret = gpio_request_by_name(bus, "cs-gpios", 0, &plat->cs_gpio,
	339	GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
	340	if (ret < 0 && ret != -ENOENT)
	341	return ret;
	342	#endif
	343
3deb1f73 JT	344	return 0;
	345	}
	346
8a4791fa	347	static const struct udevice_id pl022_spi_ids[] = {
ad77009d	348	{ .compatible = "arm,pl022" },
8a4791fa QS	349	{ }
	350	};
	351	#endif
	352
	353	U_BOOT_DRIVER(pl022_spi) = {
	354	.name = "pl022_spi",
	355	.id = UCLASS_SPI,
95397385	356	#if CONFIG_IS_ENABLED(OF_REAL)
8a4791fa	357	.of_match = pl022_spi_ids,
d1998a9f	358	.of_to_plat = pl022_spi_of_to_plat,
8a4791fa	359	#endif
3deb1f73	360	.ops = &pl022_spi_ops,
caa4daa2	361	.plat_auto = sizeof(struct pl022_spi_pdata),
41575d8e	362	.priv_auto = sizeof(struct pl022_spi_slave),
8a4791fa QS	363	.probe = pl022_spi_probe,
8a4791fa QS	364	};