[people/ms/u-boot.git] / drivers / spi / rk_spi.c

/*
 * spi driver for rockchip
 *
 * (C) Copyright 2015 Google, Inc
 *
 * (C) Copyright 2008-2013 Rockchip Electronics
 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"

DECLARE_GLOBAL_DATA_PTR;

/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI	0

struct rockchip_spi_platdata {
	int periph_id;
	struct udevice *pinctrl;
	s32 frequency;		/* Default clock frequency, -1 for none */
	fdt_addr_t base;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
};

struct rockchip_spi_priv {
	struct rockchip_spi *regs;
	struct udevice *clk;
	int clk_id;
	unsigned int max_freq;
	unsigned int mode;
	ulong last_transaction_us;	/* Time of last transaction end */
	u8 bits_per_word;		/* max 16 bits per word */
	u8 n_bytes;
	unsigned int speed_hz;
	unsigned int last_speed_hz;
	unsigned int tmode;
	uint input_rate;
};

#define SPI_FIFO_DEPTH		32

static void rkspi_dump_regs(struct rockchip_spi *regs)
{
	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
}

static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
{
	writel(enable ? 1 : 0, &regs->enr);
}

static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
	uint clk_div;

	clk_div = clk_get_divisor(priv->input_rate, speed);
	debug("spi speed %u, div %u\n", speed, clk_div);

	writel(clk_div, &priv->regs->baudr);
	priv->last_speed_hz = speed;
}

static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
{
	unsigned long start;

	start = get_timer(0);
	while (readl(&regs->sr) & SR_BUSY) {
		if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
			debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static void spi_cs_activate(struct rockchip_spi *regs, uint cs)
{
	debug("activate cs%u\n", cs);
	writel(1 << cs, &regs->ser);
}

static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs)
{
	debug("deactivate cs%u\n", cs);
	writel(0, &regs->ser);
}

static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = bus->of_offset;
	int ret;

	plat->base = dev_get_addr(bus);
	ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl);
	if (ret)
		return ret;
	ret = pinctrl_get_periph_id(plat->pinctrl, bus);

	if (ret < 0) {
		debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
		      bus->name, ret);
		return ret;
	}
	plat->periph_id = ret;
	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret < 0) {
		debug("%s: Could not get clock for %s: %d\n", __func__,
		      bus->name, ret);
		return ret;
	}
	priv->clk_id = ret;

	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
					 50000000);
	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, (uint)plat->base, plat->periph_id, plat->frequency,
	      plat->deactivate_delay_us);

	return 0;
}

static int rockchip_spi_probe(struct udevice *bus)
{
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	int ret;

	debug("%s: probe\n", __func__);
	priv->regs = (struct rockchip_spi *)plat->base;

	priv->last_transaction_us = timer_get_us();
	priv->max_freq = plat->frequency;

	/*
	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
	 * is the assumed speed for CLK_GENERAL.
	 */
	ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
	if (ret < 0) {
		debug("%s: Failed to set clock: %d\n", __func__, ret);
		return ret;
	}
	priv->input_rate = ret;
	debug("%s: rate = %u\n", __func__, priv->input_rate);
	priv->bits_per_word = 8;
	priv->tmode = TMOD_TR; /* Tx & Rx */

	return 0;
}

static int rockchip_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	u8 spi_dfs, spi_tf;
	uint ctrlr0;
#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	int ret;
#endif

	/* Disable the SPI hardware */
	rkspi_enable_chip(regs, 0);

	switch (priv->bits_per_word) {
	case 8:
		priv->n_bytes = 1;
		spi_dfs = DFS_8BIT;
		spi_tf = HALF_WORD_OFF;
		break;
	case 16:
		priv->n_bytes = 2;
		spi_dfs = DFS_16BIT;
		spi_tf = HALF_WORD_ON;
		break;
	default:
		debug("%s: unsupported bits: %dbits\n", __func__,
		      priv->bits_per_word);
		return -EPROTONOSUPPORT;
	}

	if (priv->speed_hz != priv->last_speed_hz)
		rkspi_set_clk(priv, priv->speed_hz);

	/* Operation Mode */
	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;

	/* Data Frame Size */
	ctrlr0 |= spi_dfs << DFS_SHIFT;

	/* set SPI mode 0..3 */
	if (priv->mode & SPI_CPOL)
		ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
	if (priv->mode & SPI_CPHA)
		ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;

	/* Chip Select Mode */
	ctrlr0 |= CSM_KEEP << CSM_SHIFT;

	/* SSN to Sclk_out delay */
	ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;

	/* Serial Endian Mode */
	ctrlr0 |= SEM_LITTLE << SEM_SHIFT;

	/* First Bit Mode */
	ctrlr0 |= FBM_MSB << FBM_SHIFT;

	/* Byte and Halfword Transform */
	ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;

	/* Rxd Sample Delay */
	ctrlr0 |= 0 << RXDSD_SHIFT;

	/* Frame Format */
	ctrlr0 |= FRF_SPI << FRF_SHIFT;

	/* Tx and Rx mode */
	ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;

	writel(ctrlr0, &regs->ctrlr0);
#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
	ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
	if (ret) {
		debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
		return ret;
	}
#endif

	return 0;
}

static int rockchip_spi_release_bus(struct udevice *dev)
{
	return 0;
}

static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
			   const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	int len = bitlen >> 3;
	const u8 *out = dout;
	u8 *in = din;
	int toread, towrite;
	int ret;

	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	      len, flags);
	if (DEBUG_RK_SPI)
		rkspi_dump_regs(regs);

	/* Assert CS before transfer */
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(regs, slave_plat->cs);

	while (len > 0) {
		int todo = min(len, 0xffff);

		rkspi_enable_chip(regs, true);
		writel(todo - 1, &regs->ctrlr1);
		rkspi_enable_chip(regs, true);

		toread = todo;
		towrite = todo;
		while (toread || towrite) {
			u32 status = readl(&regs->sr);

			if (towrite && !(status & SR_TF_FULL)) {
				writel(out ? *out++ : 0, regs->txdr);
				towrite--;
			}
			if (toread && !(status & SR_RF_EMPT)) {
				u32 byte = readl(regs->rxdr);

				if (in)
					*in++ = byte;
				toread--;
			}
		}
		ret = rkspi_wait_till_not_busy(regs);
		if (ret)
			break;
		len -= todo;
	}

	/* Deassert CS after transfer */
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(regs, slave_plat->cs);

	rkspi_enable_chip(regs, false);

	return ret;
}

static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	if (speed > ROCKCHIP_SPI_MAX_RATE)
		return -EINVAL;
	if (speed > priv->max_freq)
		speed = priv->max_freq;
	priv->speed_hz = speed;

	return 0;
}

static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	priv->mode = mode;

	return 0;
}

static const struct dm_spi_ops rockchip_spi_ops = {
	.claim_bus	= rockchip_spi_claim_bus,
	.release_bus	= rockchip_spi_release_bus,
	.xfer		= rockchip_spi_xfer,
	.set_speed	= rockchip_spi_set_speed,
	.set_mode	= rockchip_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id rockchip_spi_ids[] = {
	{ .compatible = "rockchip,rk3288-spi" },
	{ }
};

U_BOOT_DRIVER(rockchip_spi) = {
	.name	= "rockchip_spi",
	.id	= UCLASS_SPI,
	.of_match = rockchip_spi_ids,
	.ops	= &rockchip_spi_ops,
	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
	.probe	= rockchip_spi_probe,
};
Commit	Line	Data
1b2fd5bf SG	1	/*
	2	* spi driver for rockchip
	3	*
	4	* (C) Copyright 2015 Google, Inc
	5	*
	6	* (C) Copyright 2008-2013 Rockchip Electronics
	7	* Peter, Software Engineering, <superpeter.cai@gmail.com>.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
	13	#include <clk.h>
	14	#include <dm.h>
	15	#include <errno.h>
	16	#include <spi.h>
	17	#include <asm/errno.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/periph.h>
	21	#include <dm/pinctrl.h>
	22	#include "rk_spi.h"
	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	/* Change to 1 to output registers at the start of each transaction */
	27	#define DEBUG_RK_SPI 0
	28
	29	struct rockchip_spi_platdata {
71037d1c	30	int periph_id;
1b2fd5bf SG	31	struct udevice *pinctrl;
	32	s32 frequency; /* Default clock frequency, -1 for none */
	33	fdt_addr_t base;
	34	uint deactivate_delay_us; /* Delay to wait after deactivate */
	35	};
	36
	37	struct rockchip_spi_priv {
	38	struct rockchip_spi *regs;
71037d1c SG	39	struct udevice *clk;
71037d1c SG	40	int clk_id;
1b2fd5bf SG	41	unsigned int max_freq;
1b2fd5bf SG	42	unsigned int mode;
1b2fd5bf SG	43	ulong last_transaction_us; /* Time of last transaction end */
	44	u8 bits_per_word; /* max 16 bits per word */
	45	u8 n_bytes;
	46	unsigned int speed_hz;
28a943c1	47	unsigned int last_speed_hz;
1b2fd5bf SG	48	unsigned int tmode;
	49	uint input_rate;
	50	};
	51
	52	#define SPI_FIFO_DEPTH 32
	53
	54	static void rkspi_dump_regs(struct rockchip_spi *regs)
	55	{
	56	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	57	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	58	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	59	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	60	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	61	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	62	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	63	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	64	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	65	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	66	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	67	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	68	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	69	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	70	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
	71	}
	72
	73	static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
	74	{
	75	writel(enable ? 1 : 0, &regs->enr);
	76	}
	77
	78	static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
	79	{
	80	uint clk_div;
	81
	82	clk_div = clk_get_divisor(priv->input_rate, speed);
	83	debug("spi speed %u, div %u\n", speed, clk_div);
	84
	85	writel(clk_div, &priv->regs->baudr);
28a943c1	86	priv->last_speed_hz = speed;
1b2fd5bf SG	87	}
	88
	89	static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
	90	{
	91	unsigned long start;
	92
	93	start = get_timer(0);
	94	while (readl(&regs->sr) & SR_BUSY) {
	95	if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
	96	debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
	97	return -ETIMEDOUT;
	98	}
	99	}
	100
	101	return 0;
	102	}
	103
	104	static void spi_cs_activate(struct rockchip_spi *regs, uint cs)
	105	{
	106	debug("activate cs%u\n", cs);
	107	writel(1 << cs, &regs->ser);
	108	}
	109
	110	static void spi_cs_deactivate(struct rockchip_spi *regs, uint cs)
	111	{
	112	debug("deactivate cs%u\n", cs);
	113	writel(0, &regs->ser);
	114	}
	115
	116	static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
	117	{
	118	struct rockchip_spi_platdata *plat = bus->platdata;
71037d1c	119	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	120	const void *blob = gd->fdt_blob;
	121	int node = bus->of_offset;
	122	int ret;
	123
	124	plat->base = dev_get_addr(bus);
	125	ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl);
	126	if (ret)
	127	return ret;
	128	ret = pinctrl_get_periph_id(plat->pinctrl, bus);
	129
	130	if (ret < 0) {
	131	debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
	132	bus->name, ret);
71037d1c	133	return ret;
1b2fd5bf SG	134	}
1b2fd5bf SG	135	plat->periph_id = ret;
71037d1c SG	136	ret = clk_get_by_index(bus, 0, &priv->clk);
	137	if (ret < 0) {
	138	debug("%s: Could not get clock for %s: %d\n", __func__,
	139	bus->name, ret);
	140	return ret;
	141	}
	142	priv->clk_id = ret;
1b2fd5bf SG	143
1b2fd5bf SG	144	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
71037d1c	145	50000000);
1b2fd5bf SG	146	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
1b2fd5bf SG	147	"spi-deactivate-delay", 0);
71037d1c SG	148	debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
71037d1c SG	149	__func__, (uint)plat->base, plat->periph_id, plat->frequency,
1b2fd5bf SG	150	plat->deactivate_delay_us);
	151
	152	return 0;
	153	}
	154
	155	static int rockchip_spi_probe(struct udevice *bus)
	156	{
	157	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	158	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	159	int ret;
	160
	161	debug("%s: probe\n", __func__);
	162	priv->regs = (struct rockchip_spi *)plat->base;
	163
	164	priv->last_transaction_us = timer_get_us();
	165	priv->max_freq = plat->frequency;
1b2fd5bf SG	166
	167	/*
	168	* Use 99 MHz as our clock since it divides nicely into 594 MHz which
	169	* is the assumed speed for CLK_GENERAL.
	170	*/
71037d1c	171	ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
1b2fd5bf SG	172	if (ret < 0) {
	173	debug("%s: Failed to set clock: %d\n", __func__, ret);
	174	return ret;
	175	}
	176	priv->input_rate = ret;
	177	debug("%s: rate = %u\n", __func__, priv->input_rate);
	178	priv->bits_per_word = 8;
	179	priv->tmode = TMOD_TR; /* Tx & Rx */
	180
	181	return 0;
	182	}
	183
	184	static int rockchip_spi_claim_bus(struct udevice *dev)
	185	{
	186	struct udevice *bus = dev->parent;
1b2fd5bf SG	187	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	188	struct rockchip_spi *regs = priv->regs;
1b2fd5bf SG	189	u8 spi_dfs, spi_tf;
1b2fd5bf SG	190	uint ctrlr0;
6d97786b SG	191	#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
	192	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	193	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1b2fd5bf	194	int ret;
6d97786b	195	#endif
1b2fd5bf SG	196
	197	/* Disable the SPI hardware */
	198	rkspi_enable_chip(regs, 0);
	199
	200	switch (priv->bits_per_word) {
	201	case 8:
	202	priv->n_bytes = 1;
	203	spi_dfs = DFS_8BIT;
	204	spi_tf = HALF_WORD_OFF;
	205	break;
	206	case 16:
	207	priv->n_bytes = 2;
	208	spi_dfs = DFS_16BIT;
	209	spi_tf = HALF_WORD_ON;
	210	break;
	211	default:
	212	debug("%s: unsupported bits: %dbits\n", __func__,
	213	priv->bits_per_word);
	214	return -EPROTONOSUPPORT;
	215	}
	216
28a943c1 SG	217	if (priv->speed_hz != priv->last_speed_hz)
28a943c1 SG	218	rkspi_set_clk(priv, priv->speed_hz);
1b2fd5bf SG	219
	220	/* Operation Mode */
	221	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
	222
	223	/* Data Frame Size */
2b9fe111	224	ctrlr0 \|= spi_dfs << DFS_SHIFT;
1b2fd5bf SG	225
	226	/* set SPI mode 0..3 */
	227	if (priv->mode & SPI_CPOL)
	228	ctrlr0 \|= SCOL_HIGH << SCOL_SHIFT;
	229	if (priv->mode & SPI_CPHA)
	230	ctrlr0 \|= SCPH_TOGSTA << SCPH_SHIFT;
	231
	232	/* Chip Select Mode */
	233	ctrlr0 \|= CSM_KEEP << CSM_SHIFT;
	234
	235	/* SSN to Sclk_out delay */
	236	ctrlr0 \|= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
	237
	238	/* Serial Endian Mode */
	239	ctrlr0 \|= SEM_LITTLE << SEM_SHIFT;
	240
	241	/* First Bit Mode */
	242	ctrlr0 \|= FBM_MSB << FBM_SHIFT;
	243
	244	/* Byte and Halfword Transform */
2b9fe111	245	ctrlr0 \|= spi_tf << HALF_WORD_TX_SHIFT;
1b2fd5bf SG	246
	247	/* Rxd Sample Delay */
	248	ctrlr0 \|= 0 << RXDSD_SHIFT;
	249
	250	/* Frame Format */
	251	ctrlr0 \|= FRF_SPI << FRF_SHIFT;
	252
	253	/* Tx and Rx mode */
	254	ctrlr0 \|= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
	255
	256	writel(ctrlr0, &regs->ctrlr0);
6d97786b	257	#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
71037d1c	258	ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
1b2fd5bf SG	259	if (ret) {
	260	debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
	261	return ret;
	262	}
6d97786b	263	#endif
1b2fd5bf SG	264
	265	return 0;
	266	}
	267
	268	static int rockchip_spi_release_bus(struct udevice *dev)
	269	{
	270	return 0;
	271	}
	272
	273	static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
	274	const void dout, void din, unsigned long flags)
	275	{
	276	struct udevice *bus = dev->parent;
	277	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	278	struct rockchip_spi *regs = priv->regs;
	279	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	280	int len = bitlen >> 3;
	281	const u8 *out = dout;
	282	u8 *in = din;
	283	int toread, towrite;
	284	int ret;
	285
	286	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	287	len, flags);
	288	if (DEBUG_RK_SPI)
	289	rkspi_dump_regs(regs);
	290
	291	/* Assert CS before transfer */
	292	if (flags & SPI_XFER_BEGIN)
	293	spi_cs_activate(regs, slave_plat->cs);
	294
	295	while (len > 0) {
	296	int todo = min(len, 0xffff);
	297
	298	rkspi_enable_chip(regs, true);
	299	writel(todo - 1, &regs->ctrlr1);
	300	rkspi_enable_chip(regs, true);
	301
	302	toread = todo;
	303	towrite = todo;
	304	while (toread \|\| towrite) {
	305	u32 status = readl(&regs->sr);
	306
	307	if (towrite && !(status & SR_TF_FULL)) {
	308	writel(out ? *out++ : 0, regs->txdr);
	309	towrite--;
	310	}
	311	if (toread && !(status & SR_RF_EMPT)) {
	312	u32 byte = readl(regs->rxdr);
	313
	314	if (in)
	315	*in++ = byte;
	316	toread--;
	317	}
	318	}
	319	ret = rkspi_wait_till_not_busy(regs);
	320	if (ret)
	321	break;
	322	len -= todo;
	323	}
	324
	325	/* Deassert CS after transfer */
	326	if (flags & SPI_XFER_END)
	327	spi_cs_deactivate(regs, slave_plat->cs);
328
329	rkspi_enable_chip(regs, false);
330
331	return ret;
332	}
333
334	static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
335	{
336	struct rockchip_spi_priv *priv = dev_get_priv(bus);
337
338	if (speed > ROCKCHIP_SPI_MAX_RATE)
339	return -EINVAL;
340	if (speed > priv->max_freq)
341	speed = priv->max_freq;
342	priv->speed_hz = speed;
343
344	return 0;
345	}
346
347	static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
348	{
349	struct rockchip_spi_priv *priv = dev_get_priv(bus);
350
351	priv->mode = mode;
352
353	return 0;
354	}
355
356	static const struct dm_spi_ops rockchip_spi_ops = {
357	.claim_bus = rockchip_spi_claim_bus,
358	.release_bus = rockchip_spi_release_bus,
359	.xfer = rockchip_spi_xfer,
360	.set_speed = rockchip_spi_set_speed,
361	.set_mode = rockchip_spi_set_mode,
362	/*
363	* cs_info is not needed, since we require all chip selects to be
364	* in the device tree explicitly
365	*/
366	};
367
368	static const struct udevice_id rockchip_spi_ids[] = {
369	{ .compatible = "rockchip,rk3288-spi" },
370	{ }
371	};
372
373	U_BOOT_DRIVER(rockchip_spi) = {
374	.name = "rockchip_spi",
375	.id = UCLASS_SPI,
376	.of_match = rockchip_spi_ids,
377	.ops = &rockchip_spi_ops,
378	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
379	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
380	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
381	.probe = rockchip_spi_probe,
382	};