[people/ms/u-boot.git] / drivers / spi / rk_spi.c

/*
 * spi driver for rockchip
 *
 * (C) Copyright 2015 Google, Inc
 *
 * (C) Copyright 2008-2013 Rockchip Electronics
 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <spi.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"

DECLARE_GLOBAL_DATA_PTR;

/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI	0

struct rockchip_spi_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct dtd_rockchip_rk3288_spi of_plat;
#endif
	s32 frequency;		/* Default clock frequency, -1 for none */
	fdt_addr_t base;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
	uint activate_delay_us;		/* Delay to wait after activate */
};

struct rockchip_spi_priv {
	struct rockchip_spi *regs;
	struct clk clk;
	unsigned int max_freq;
	unsigned int mode;
	ulong last_transaction_us;	/* Time of last transaction end */
	u8 bits_per_word;		/* max 16 bits per word */
	u8 n_bytes;
	unsigned int speed_hz;
	unsigned int last_speed_hz;
	unsigned int tmode;
	uint input_rate;
};

#define SPI_FIFO_DEPTH		32

static void rkspi_dump_regs(struct rockchip_spi *regs)
{
	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
}

static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
{
	writel(enable ? 1 : 0, &regs->enr);
}

static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
	uint clk_div;

	clk_div = clk_get_divisor(priv->input_rate, speed);
	debug("spi speed %u, div %u\n", speed, clk_div);

	writel(clk_div, &priv->regs->baudr);
	priv->last_speed_hz = speed;
}

static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
{
	unsigned long start;

	start = get_timer(0);
	while (readl(&regs->sr) & SR_BUSY) {
		if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
			debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static void spi_cs_activate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	debug("activate cs%u\n", cs);
	writel(1 << cs, &regs->ser);
	if (plat->activate_delay_us)
		udelay(plat->activate_delay_us);
}

static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	debug("deactivate cs%u\n", cs);
	writel(0, &regs->ser);

	/* Remember time of this transaction so we can honour the bus delay */
	if (plat->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();
}

#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_platdata(struct udevice *dev)
{
	struct rockchip_spi_platdata *plat = dev->platdata;
	struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
	struct rockchip_spi_priv *priv = dev_get_priv(dev);
	int ret;

	plat->base = dtplat->reg[0];
	plat->frequency = 20000000;
	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
	if (ret < 0)
		return ret;
	dev->req_seq = 0;

	return 0;
}
#endif

static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = bus->of_offset;
	int ret;

	plat->base = dev_get_addr(bus);

	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret < 0) {
		debug("%s: Could not get clock for %s: %d\n", __func__,
		      bus->name, ret);
		return ret;
	}

	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
					 50000000);
	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	plat->activate_delay_us = fdtdec_get_int(blob, node,
						 "spi-activate-delay", 0);
	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, (uint)plat->base, plat->frequency,
	      plat->deactivate_delay_us);
#endif

	return 0;
}

static int rockchip_spi_probe(struct udevice *bus)
{
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	int ret;

	debug("%s: probe\n", __func__);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	ret = conv_of_platdata(bus);
	if (ret)
		return ret;
#endif
	priv->regs = (struct rockchip_spi *)plat->base;

	priv->last_transaction_us = timer_get_us();
	priv->max_freq = plat->frequency;

	/*
	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
	 * is the assumed speed for CLK_GENERAL.
	 */
	ret = clk_set_rate(&priv->clk, 99000000);
	if (ret < 0) {
		debug("%s: Failed to set clock: %d\n", __func__, ret);
		return ret;
	}
	priv->input_rate = ret;
	debug("%s: rate = %u\n", __func__, priv->input_rate);
	priv->bits_per_word = 8;
	priv->tmode = TMOD_TR; /* Tx & Rx */

	return 0;
}

static int rockchip_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	u8 spi_dfs, spi_tf;
	uint ctrlr0;

	/* Disable the SPI hardware */
	rkspi_enable_chip(regs, 0);

	switch (priv->bits_per_word) {
	case 8:
		priv->n_bytes = 1;
		spi_dfs = DFS_8BIT;
		spi_tf = HALF_WORD_OFF;
		break;
	case 16:
		priv->n_bytes = 2;
		spi_dfs = DFS_16BIT;
		spi_tf = HALF_WORD_ON;
		break;
	default:
		debug("%s: unsupported bits: %dbits\n", __func__,
		      priv->bits_per_word);
		return -EPROTONOSUPPORT;
	}

	if (priv->speed_hz != priv->last_speed_hz)
		rkspi_set_clk(priv, priv->speed_hz);

	/* Operation Mode */
	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;

	/* Data Frame Size */
	ctrlr0 |= spi_dfs << DFS_SHIFT;

	/* set SPI mode 0..3 */
	if (priv->mode & SPI_CPOL)
		ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
	if (priv->mode & SPI_CPHA)
		ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;

	/* Chip Select Mode */
	ctrlr0 |= CSM_KEEP << CSM_SHIFT;

	/* SSN to Sclk_out delay */
	ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;

	/* Serial Endian Mode */
	ctrlr0 |= SEM_LITTLE << SEM_SHIFT;

	/* First Bit Mode */
	ctrlr0 |= FBM_MSB << FBM_SHIFT;

	/* Byte and Halfword Transform */
	ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;

	/* Rxd Sample Delay */
	ctrlr0 |= 0 << RXDSD_SHIFT;

	/* Frame Format */
	ctrlr0 |= FRF_SPI << FRF_SHIFT;

	/* Tx and Rx mode */
	ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;

	writel(ctrlr0, &regs->ctrlr0);

	return 0;
}

static int rockchip_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	rkspi_enable_chip(priv->regs, false);

	return 0;
}

static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
			   const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	int len = bitlen >> 3;
	const u8 *out = dout;
	u8 *in = din;
	int toread, towrite;
	int ret;

	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	      len, flags);
	if (DEBUG_RK_SPI)
		rkspi_dump_regs(regs);

	/* Assert CS before transfer */
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev, slave_plat->cs);

	while (len > 0) {
		int todo = min(len, 0xffff);

		rkspi_enable_chip(regs, false);
		writel(todo - 1, &regs->ctrlr1);
		rkspi_enable_chip(regs, true);

		toread = todo;
		towrite = todo;
		while (toread || towrite) {
			u32 status = readl(&regs->sr);

			if (towrite && !(status & SR_TF_FULL)) {
				writel(out ? *out++ : 0, regs->txdr);
				towrite--;
			}
			if (toread && !(status & SR_RF_EMPT)) {
				u32 byte = readl(regs->rxdr);

				if (in)
					*in++ = byte;
				toread--;
			}
		}
		ret = rkspi_wait_till_not_busy(regs);
		if (ret)
			break;
		len -= todo;
	}

	/* Deassert CS after transfer */
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev, slave_plat->cs);

	rkspi_enable_chip(regs, false);

	return ret;
}

static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	if (speed > ROCKCHIP_SPI_MAX_RATE)
		return -EINVAL;
	if (speed > priv->max_freq)
		speed = priv->max_freq;
	priv->speed_hz = speed;

	return 0;
}

static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	priv->mode = mode;

	return 0;
}

static const struct dm_spi_ops rockchip_spi_ops = {
	.claim_bus	= rockchip_spi_claim_bus,
	.release_bus	= rockchip_spi_release_bus,
	.xfer		= rockchip_spi_xfer,
	.set_speed	= rockchip_spi_set_speed,
	.set_mode	= rockchip_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id rockchip_spi_ids[] = {
	{ .compatible = "rockchip,rk3288-spi" },
	{ }
};

U_BOOT_DRIVER(rockchip_spi) = {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	.name	= "rockchip_rk3288_spi",
#else
	.name	= "rockchip_spi",
#endif
	.id	= UCLASS_SPI,
	.of_match = rockchip_spi_ids,
	.ops	= &rockchip_spi_ops,
	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
	.probe	= rockchip_spi_probe,
};
Commit	Line	Data
1b2fd5bf SG	1	/*
	2	* spi driver for rockchip
	3	*
	4	* (C) Copyright 2015 Google, Inc
	5	*
	6	* (C) Copyright 2008-2013 Rockchip Electronics
	7	* Peter, Software Engineering, <superpeter.cai@gmail.com>.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
	13	#include <clk.h>
	14	#include <dm.h>
6e019c4f	15	#include <dt-structs.h>
1b2fd5bf SG	16	#include <errno.h>
1b2fd5bf SG	17	#include <spi.h>
1221ce45	18	#include <linux/errno.h>
1b2fd5bf SG	19	#include <asm/io.h>
	20	#include <asm/arch/clock.h>
	21	#include <asm/arch/periph.h>
	22	#include <dm/pinctrl.h>
	23	#include "rk_spi.h"
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
	27	/* Change to 1 to output registers at the start of each transaction */
	28	#define DEBUG_RK_SPI 0
	29
	30	struct rockchip_spi_platdata {
6e019c4f SG	31	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	32	struct dtd_rockchip_rk3288_spi of_plat;
	33	#endif
1b2fd5bf SG	34	s32 frequency; /* Default clock frequency, -1 for none */
	35	fdt_addr_t base;
	36	uint deactivate_delay_us; /* Delay to wait after deactivate */
183a3a0f	37	uint activate_delay_us; /* Delay to wait after activate */
1b2fd5bf SG	38	};
	39
	40	struct rockchip_spi_priv {
	41	struct rockchip_spi *regs;
135aa950	42	struct clk clk;
1b2fd5bf SG	43	unsigned int max_freq;
1b2fd5bf SG	44	unsigned int mode;
1b2fd5bf SG	45	ulong last_transaction_us; /* Time of last transaction end */
	46	u8 bits_per_word; /* max 16 bits per word */
	47	u8 n_bytes;
	48	unsigned int speed_hz;
28a943c1	49	unsigned int last_speed_hz;
1b2fd5bf SG	50	unsigned int tmode;
	51	uint input_rate;
	52	};
	53
	54	#define SPI_FIFO_DEPTH 32
	55
	56	static void rkspi_dump_regs(struct rockchip_spi *regs)
	57	{
	58	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	59	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	60	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	61	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	62	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	63	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	64	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	65	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	66	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	67	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	68	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	69	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	70	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	71	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	72	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
	73	}
	74
	75	static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
	76	{
	77	writel(enable ? 1 : 0, &regs->enr);
	78	}
	79
	80	static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
	81	{
	82	uint clk_div;
	83
	84	clk_div = clk_get_divisor(priv->input_rate, speed);
	85	debug("spi speed %u, div %u\n", speed, clk_div);
	86
	87	writel(clk_div, &priv->regs->baudr);
28a943c1	88	priv->last_speed_hz = speed;
1b2fd5bf SG	89	}
	90
	91	static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
	92	{
	93	unsigned long start;
	94
	95	start = get_timer(0);
	96	while (readl(&regs->sr) & SR_BUSY) {
	97	if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
	98	debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
	99	return -ETIMEDOUT;
	100	}
	101	}
	102
	103	return 0;
	104	}
	105
183a3a0f	106	static void spi_cs_activate(struct udevice *dev, uint cs)
1b2fd5bf	107	{
183a3a0f SG	108	struct udevice *bus = dev->parent;
	109	struct rockchip_spi_platdata *plat = bus->platdata;
	110	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	111	struct rockchip_spi *regs = priv->regs;
	112
1b2fd5bf SG	113	debug("activate cs%u\n", cs);
1b2fd5bf SG	114	writel(1 << cs, &regs->ser);
183a3a0f SG	115	if (plat->activate_delay_us)
183a3a0f SG	116	udelay(plat->activate_delay_us);
1b2fd5bf SG	117	}
1b2fd5bf SG	118
183a3a0f	119	static void spi_cs_deactivate(struct udevice *dev, uint cs)
1b2fd5bf	120	{
183a3a0f SG	121	struct udevice *bus = dev->parent;
	122	struct rockchip_spi_platdata *plat = bus->platdata;
	123	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	124	struct rockchip_spi *regs = priv->regs;
	125
1b2fd5bf SG	126	debug("deactivate cs%u\n", cs);
1b2fd5bf SG	127	writel(0, &regs->ser);
183a3a0f SG	128
	129	/* Remember time of this transaction so we can honour the bus delay */
	130	if (plat->deactivate_delay_us)
	131	priv->last_transaction_us = timer_get_us();
1b2fd5bf SG	132	}
1b2fd5bf SG	133
6e019c4f SG	134	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	135	static int conv_of_platdata(struct udevice *dev)
	136	{
	137	struct rockchip_spi_platdata *plat = dev->platdata;
	138	struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
	139	struct rockchip_spi_priv *priv = dev_get_priv(dev);
	140	int ret;
	141
	142	plat->base = dtplat->reg[0];
	143	plat->frequency = 20000000;
	144	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
	145	if (ret < 0)
	146	return ret;
	147	dev->req_seq = 0;
	148
	149	return 0;
	150	}
	151	#endif
	152
1b2fd5bf SG	153	static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
1b2fd5bf SG	154	{
6e019c4f SG	155	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
6e019c4f SG	156	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
71037d1c	157	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	158	const void *blob = gd->fdt_blob;
	159	int node = bus->of_offset;
	160	int ret;
	161
	162	plat->base = dev_get_addr(bus);
1b2fd5bf	163
71037d1c SG	164	ret = clk_get_by_index(bus, 0, &priv->clk);
	165	if (ret < 0) {
	166	debug("%s: Could not get clock for %s: %d\n", __func__,
	167	bus->name, ret);
	168	return ret;
	169	}
1b2fd5bf SG	170
1b2fd5bf SG	171	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
71037d1c	172	50000000);
1b2fd5bf SG	173	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
1b2fd5bf SG	174	"spi-deactivate-delay", 0);
183a3a0f SG	175	plat->activate_delay_us = fdtdec_get_int(blob, node,
183a3a0f SG	176	"spi-activate-delay", 0);
90a28470 SG	177	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
90a28470 SG	178	__func__, (uint)plat->base, plat->frequency,
1b2fd5bf	179	plat->deactivate_delay_us);
6e019c4f	180	#endif
1b2fd5bf SG	181
	182	return 0;
	183	}
	184
	185	static int rockchip_spi_probe(struct udevice *bus)
	186	{
	187	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	188	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	189	int ret;
	190
	191	debug("%s: probe\n", __func__);
6e019c4f SG	192	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	193	ret = conv_of_platdata(bus);
	194	if (ret)
	195	return ret;
	196	#endif
1b2fd5bf SG	197	priv->regs = (struct rockchip_spi *)plat->base;
	198
	199	priv->last_transaction_us = timer_get_us();
	200	priv->max_freq = plat->frequency;
1b2fd5bf SG	201
	202	/*
	203	* Use 99 MHz as our clock since it divides nicely into 594 MHz which
	204	* is the assumed speed for CLK_GENERAL.
	205	*/
135aa950	206	ret = clk_set_rate(&priv->clk, 99000000);
1b2fd5bf SG	207	if (ret < 0) {
	208	debug("%s: Failed to set clock: %d\n", __func__, ret);
	209	return ret;
	210	}
	211	priv->input_rate = ret;
	212	debug("%s: rate = %u\n", __func__, priv->input_rate);
	213	priv->bits_per_word = 8;
	214	priv->tmode = TMOD_TR; /* Tx & Rx */
	215
	216	return 0;
	217	}
	218
	219	static int rockchip_spi_claim_bus(struct udevice *dev)
	220	{
	221	struct udevice *bus = dev->parent;
1b2fd5bf SG	222	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	223	struct rockchip_spi *regs = priv->regs;
1b2fd5bf SG	224	u8 spi_dfs, spi_tf;
1b2fd5bf SG	225	uint ctrlr0;
1b2fd5bf SG	226
	227	/* Disable the SPI hardware */
	228	rkspi_enable_chip(regs, 0);
	229
	230	switch (priv->bits_per_word) {
	231	case 8:
	232	priv->n_bytes = 1;
	233	spi_dfs = DFS_8BIT;
	234	spi_tf = HALF_WORD_OFF;
	235	break;
	236	case 16:
	237	priv->n_bytes = 2;
	238	spi_dfs = DFS_16BIT;
	239	spi_tf = HALF_WORD_ON;
	240	break;
	241	default:
	242	debug("%s: unsupported bits: %dbits\n", __func__,
	243	priv->bits_per_word);
	244	return -EPROTONOSUPPORT;
	245	}
	246
28a943c1 SG	247	if (priv->speed_hz != priv->last_speed_hz)
28a943c1 SG	248	rkspi_set_clk(priv, priv->speed_hz);
1b2fd5bf SG	249
	250	/* Operation Mode */
	251	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
	252
	253	/* Data Frame Size */
2b9fe111	254	ctrlr0 \|= spi_dfs << DFS_SHIFT;
1b2fd5bf SG	255
	256	/* set SPI mode 0..3 */
	257	if (priv->mode & SPI_CPOL)
	258	ctrlr0 \|= SCOL_HIGH << SCOL_SHIFT;
	259	if (priv->mode & SPI_CPHA)
	260	ctrlr0 \|= SCPH_TOGSTA << SCPH_SHIFT;
	261
	262	/* Chip Select Mode */
	263	ctrlr0 \|= CSM_KEEP << CSM_SHIFT;
	264
	265	/* SSN to Sclk_out delay */
	266	ctrlr0 \|= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
	267
	268	/* Serial Endian Mode */
	269	ctrlr0 \|= SEM_LITTLE << SEM_SHIFT;
	270
	271	/* First Bit Mode */
	272	ctrlr0 \|= FBM_MSB << FBM_SHIFT;
	273
	274	/* Byte and Halfword Transform */
2b9fe111	275	ctrlr0 \|= spi_tf << HALF_WORD_TX_SHIFT;
1b2fd5bf SG	276
	277	/* Rxd Sample Delay */
	278	ctrlr0 \|= 0 << RXDSD_SHIFT;
	279
	280	/* Frame Format */
	281	ctrlr0 \|= FRF_SPI << FRF_SHIFT;
	282
	283	/* Tx and Rx mode */
	284	ctrlr0 \|= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
	285
	286	writel(ctrlr0, &regs->ctrlr0);
1b2fd5bf SG	287
	288	return 0;
	289	}
	290
	291	static int rockchip_spi_release_bus(struct udevice *dev)
	292	{
e15af8e2 SG	293	struct udevice *bus = dev->parent;
	294	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	295
	296	rkspi_enable_chip(priv->regs, false);
	297
1b2fd5bf SG	298	return 0;
	299	}
	300
	301	static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
	302	const void dout, void din, unsigned long flags)
	303	{
	304	struct udevice *bus = dev->parent;
	305	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	306	struct rockchip_spi *regs = priv->regs;
	307	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	308	int len = bitlen >> 3;
	309	const u8 *out = dout;
	310	u8 *in = din;
	311	int toread, towrite;
	312	int ret;
	313
	314	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	315	len, flags);
	316	if (DEBUG_RK_SPI)
	317	rkspi_dump_regs(regs);
	318
	319	/* Assert CS before transfer */
	320	if (flags & SPI_XFER_BEGIN)
183a3a0f	321	spi_cs_activate(dev, slave_plat->cs);
1b2fd5bf SG	322
	323	while (len > 0) {
	324	int todo = min(len, 0xffff);
	325
e15af8e2	326	rkspi_enable_chip(regs, false);
1b2fd5bf SG	327	writel(todo - 1, &regs->ctrlr1);
	328	rkspi_enable_chip(regs, true);
	329
	330	toread = todo;
	331	towrite = todo;
	332	while (toread \|\| towrite) {
	333	u32 status = readl(&regs->sr);
	334
	335	if (towrite && !(status & SR_TF_FULL)) {
	336	writel(out ? *out++ : 0, regs->txdr);
	337	towrite--;
	338	}
	339	if (toread && !(status & SR_RF_EMPT)) {
	340	u32 byte = readl(regs->rxdr);
	341
	342	if (in)
	343	*in++ = byte;
	344	toread--;
	345	}
	346	}
	347	ret = rkspi_wait_till_not_busy(regs);
	348	if (ret)
	349	break;
	350	len -= todo;
	351	}
	352
	353	/* Deassert CS after transfer */
	354	if (flags & SPI_XFER_END)
183a3a0f	355	spi_cs_deactivate(dev, slave_plat->cs);
1b2fd5bf SG	356
	357	rkspi_enable_chip(regs, false);
	358
	359	return ret;
	360	}
	361
	362	static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
	363	{
	364	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	365
	366	if (speed > ROCKCHIP_SPI_MAX_RATE)
	367	return -EINVAL;
	368	if (speed > priv->max_freq)
	369	speed = priv->max_freq;
	370	priv->speed_hz = speed;
	371
	372	return 0;
	373	}
	374
	375	static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
	376	{
	377	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	378
	379	priv->mode = mode;
	380
	381	return 0;
	382	}
	383
	384	static const struct dm_spi_ops rockchip_spi_ops = {
	385	.claim_bus = rockchip_spi_claim_bus,
	386	.release_bus = rockchip_spi_release_bus,
	387	.xfer = rockchip_spi_xfer,
	388	.set_speed = rockchip_spi_set_speed,
	389	.set_mode = rockchip_spi_set_mode,
	390	/*
	391	* cs_info is not needed, since we require all chip selects to be
	392	* in the device tree explicitly
	393	*/
	394	};
	395
	396	static const struct udevice_id rockchip_spi_ids[] = {
	397	{ .compatible = "rockchip,rk3288-spi" },
	398	{ }
	399	};
	400
	401	U_BOOT_DRIVER(rockchip_spi) = {
6e019c4f SG	402	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	403	.name = "rockchip_rk3288_spi",
	404	#else
1b2fd5bf	405	.name = "rockchip_spi",
6e019c4f	406	#endif
1b2fd5bf SG	407	.id = UCLASS_SPI,
	408	.of_match = rockchip_spi_ids,
	409	.ops = &rockchip_spi_ops,
	410	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	411	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
	412	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
	413	.probe = rockchip_spi_probe,
	414	};