[people/ms/u-boot.git] / drivers / spi / rk_spi.c

/*
 * spi driver for rockchip
 *
 * (C) Copyright 2015 Google, Inc
 *
 * (C) Copyright 2008-2013 Rockchip Electronics
 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <spi.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"

DECLARE_GLOBAL_DATA_PTR;

/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI	0

struct rockchip_spi_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct dtd_rockchip_rk3288_spi of_plat;
#endif
	s32 frequency;		/* Default clock frequency, -1 for none */
	fdt_addr_t base;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
	uint activate_delay_us;		/* Delay to wait after activate */
};

struct rockchip_spi_priv {
	struct rockchip_spi *regs;
	struct clk clk;
	unsigned int max_freq;
	unsigned int mode;
	ulong last_transaction_us;	/* Time of last transaction end */
	u8 bits_per_word;		/* max 16 bits per word */
	u8 n_bytes;
	unsigned int speed_hz;
	unsigned int last_speed_hz;
	unsigned int tmode;
	uint input_rate;
};

#define SPI_FIFO_DEPTH		32

static void rkspi_dump_regs(struct rockchip_spi *regs)
{
	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
}

static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
{
	writel(enable ? 1 : 0, &regs->enr);
}

static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
	/*
	 * We should try not to exceed the speed requested by the caller:
	 * when selecting a divider, we need to make sure we round up.
	 */
	uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);

	/* The baudrate register (BAUDR) is defined as a 32bit register where
	 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
	 * 16bits with 'Fsclk_out' defined as follows:
	 *
	 *   Fsclk_out = Fspi_clk/ SCKDV
	 *   Where SCKDV is any even value between 2 and 65534.
	 */
	if (clk_div > 0xfffe) {
		clk_div = 0xfffe;
		debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
		      __func__, speed, priv->input_rate / clk_div);
	}

	/* Round up to the next even 16bit number */
	clk_div = (clk_div + 1) & 0xfffe;

	debug("spi speed %u, div %u\n", speed, clk_div);

	clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
	priv->last_speed_hz = speed;
}

static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
{
	unsigned long start;

	start = get_timer(0);
	while (readl(&regs->sr) & SR_BUSY) {
		if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
			debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static void spi_cs_activate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	/* If it's too soon to do another transaction, wait */
	if (plat->deactivate_delay_us && priv->last_transaction_us) {
		ulong delay_us;		/* The delay completed so far */
		delay_us = timer_get_us() - priv->last_transaction_us;
		if (delay_us < plat->deactivate_delay_us)
			udelay(plat->deactivate_delay_us - delay_us);
	}

	debug("activate cs%u\n", cs);
	writel(1 << cs, &regs->ser);
	if (plat->activate_delay_us)
		udelay(plat->activate_delay_us);
}

static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	debug("deactivate cs%u\n", cs);
	writel(0, &regs->ser);

	/* Remember time of this transaction so we can honour the bus delay */
	if (plat->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();
}

#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_platdata(struct udevice *dev)
{
	struct rockchip_spi_platdata *plat = dev->platdata;
	struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
	struct rockchip_spi_priv *priv = dev_get_priv(dev);
	int ret;

	plat->base = dtplat->reg[0];
	plat->frequency = 20000000;
	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
	if (ret < 0)
		return ret;
	dev->req_seq = 0;

	return 0;
}
#endif

static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);
	int ret;

	plat->base = dev_get_addr(bus);

	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret < 0) {
		debug("%s: Could not get clock for %s: %d\n", __func__,
		      bus->name, ret);
		return ret;
	}

	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
					 50000000);
	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	plat->activate_delay_us = fdtdec_get_int(blob, node,
						 "spi-activate-delay", 0);
	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, (uint)plat->base, plat->frequency,
	      plat->deactivate_delay_us);
#endif

	return 0;
}

static int rockchip_spi_calc_modclk(ulong max_freq)
{
	unsigned div;
	const unsigned long gpll_hz = 594000000UL;

	/*
	 * We need to find an input clock that provides at least twice
	 * the maximum frequency and can be generated from the assumed
	 * speed of GPLL (594MHz) using an integer divider.
	 *
	 * To give us more achievable bitrates at higher speeds (these
	 * are generated by dividing by an even 16-bit integer from
	 * this frequency), we try to have an input frequency of at
	 * least 4x our max_freq.
	 */

	div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
	return gpll_hz / div;
}

static int rockchip_spi_probe(struct udevice *bus)
{
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	int ret;

	debug("%s: probe\n", __func__);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	ret = conv_of_platdata(bus);
	if (ret)
		return ret;
#endif
	priv->regs = (struct rockchip_spi *)plat->base;

	priv->last_transaction_us = timer_get_us();
	priv->max_freq = plat->frequency;

	/* Clamp the value from the DTS against any hardware limits */
	if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
		priv->max_freq = ROCKCHIP_SPI_MAX_RATE;

	/* Find a module-input clock that fits with the max_freq setting */
	ret = clk_set_rate(&priv->clk,
			   rockchip_spi_calc_modclk(priv->max_freq));
	if (ret < 0) {
		debug("%s: Failed to set clock: %d\n", __func__, ret);
		return ret;
	}
	priv->input_rate = ret;
	debug("%s: rate = %u\n", __func__, priv->input_rate);
	priv->bits_per_word = 8;
	priv->tmode = TMOD_TR; /* Tx & Rx */

	return 0;
}

static int rockchip_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	u8 spi_dfs, spi_tf;
	uint ctrlr0;

	/* Disable the SPI hardware */
	rkspi_enable_chip(regs, 0);

	switch (priv->bits_per_word) {
	case 8:
		priv->n_bytes = 1;
		spi_dfs = DFS_8BIT;
		spi_tf = HALF_WORD_OFF;
		break;
	case 16:
		priv->n_bytes = 2;
		spi_dfs = DFS_16BIT;
		spi_tf = HALF_WORD_ON;
		break;
	default:
		debug("%s: unsupported bits: %dbits\n", __func__,
		      priv->bits_per_word);
		return -EPROTONOSUPPORT;
	}

	if (priv->speed_hz != priv->last_speed_hz)
		rkspi_set_clk(priv, priv->speed_hz);

	/* Operation Mode */
	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;

	/* Data Frame Size */
	ctrlr0 |= spi_dfs << DFS_SHIFT;

	/* set SPI mode 0..3 */
	if (priv->mode & SPI_CPOL)
		ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
	if (priv->mode & SPI_CPHA)
		ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;

	/* Chip Select Mode */
	ctrlr0 |= CSM_KEEP << CSM_SHIFT;

	/* SSN to Sclk_out delay */
	ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;

	/* Serial Endian Mode */
	ctrlr0 |= SEM_LITTLE << SEM_SHIFT;

	/* First Bit Mode */
	ctrlr0 |= FBM_MSB << FBM_SHIFT;

	/* Byte and Halfword Transform */
	ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;

	/* Rxd Sample Delay */
	ctrlr0 |= 0 << RXDSD_SHIFT;

	/* Frame Format */
	ctrlr0 |= FRF_SPI << FRF_SHIFT;

	/* Tx and Rx mode */
	ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;

	writel(ctrlr0, &regs->ctrlr0);

	return 0;
}

static int rockchip_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	rkspi_enable_chip(priv->regs, false);

	return 0;
}

static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
			   const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	int len = bitlen >> 3;
	const u8 *out = dout;
	u8 *in = din;
	int toread, towrite;
	int ret;

	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	      len, flags);
	if (DEBUG_RK_SPI)
		rkspi_dump_regs(regs);

	/* Assert CS before transfer */
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev, slave_plat->cs);

	while (len > 0) {
		int todo = min(len, 0xffff);

		rkspi_enable_chip(regs, false);
		writel(todo - 1, &regs->ctrlr1);
		rkspi_enable_chip(regs, true);

		toread = todo;
		towrite = todo;
		while (toread || towrite) {
			u32 status = readl(&regs->sr);

			if (towrite && !(status & SR_TF_FULL)) {
				writel(out ? *out++ : 0, regs->txdr);
				towrite--;
			}
			if (toread && !(status & SR_RF_EMPT)) {
				u32 byte = readl(regs->rxdr);

				if (in)
					*in++ = byte;
				toread--;
			}
		}
		ret = rkspi_wait_till_not_busy(regs);
		if (ret)
			break;
		len -= todo;
	}

	/* Deassert CS after transfer */
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev, slave_plat->cs);

	rkspi_enable_chip(regs, false);

	return ret;
}

static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	/* Clamp to the maximum frequency specified in the DTS */
	if (speed > priv->max_freq)
		speed = priv->max_freq;

	priv->speed_hz = speed;

	return 0;
}

static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	priv->mode = mode;

	return 0;
}

static const struct dm_spi_ops rockchip_spi_ops = {
	.claim_bus	= rockchip_spi_claim_bus,
	.release_bus	= rockchip_spi_release_bus,
	.xfer		= rockchip_spi_xfer,
	.set_speed	= rockchip_spi_set_speed,
	.set_mode	= rockchip_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id rockchip_spi_ids[] = {
	{ .compatible = "rockchip,rk3288-spi" },
	{ }
};

U_BOOT_DRIVER(rockchip_spi) = {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	.name	= "rockchip_rk3288_spi",
#else
	.name	= "rockchip_spi",
#endif
	.id	= UCLASS_SPI,
	.of_match = rockchip_spi_ids,
	.ops	= &rockchip_spi_ops,
	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
	.probe	= rockchip_spi_probe,
};
Commit	Line	Data
1b2fd5bf SG	1	/*
	2	* spi driver for rockchip
	3	*
	4	* (C) Copyright 2015 Google, Inc
	5	*
	6	* (C) Copyright 2008-2013 Rockchip Electronics
	7	* Peter, Software Engineering, <superpeter.cai@gmail.com>.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
	13	#include <clk.h>
	14	#include <dm.h>
6e019c4f	15	#include <dt-structs.h>
1b2fd5bf SG	16	#include <errno.h>
1b2fd5bf SG	17	#include <spi.h>
1221ce45	18	#include <linux/errno.h>
1b2fd5bf SG	19	#include <asm/io.h>
	20	#include <asm/arch/clock.h>
	21	#include <asm/arch/periph.h>
	22	#include <dm/pinctrl.h>
	23	#include "rk_spi.h"
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
	27	/* Change to 1 to output registers at the start of each transaction */
	28	#define DEBUG_RK_SPI 0
	29
	30	struct rockchip_spi_platdata {
6e019c4f SG	31	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	32	struct dtd_rockchip_rk3288_spi of_plat;
	33	#endif
1b2fd5bf SG	34	s32 frequency; /* Default clock frequency, -1 for none */
	35	fdt_addr_t base;
	36	uint deactivate_delay_us; /* Delay to wait after deactivate */
183a3a0f	37	uint activate_delay_us; /* Delay to wait after activate */
1b2fd5bf SG	38	};
	39
	40	struct rockchip_spi_priv {
	41	struct rockchip_spi *regs;
135aa950	42	struct clk clk;
1b2fd5bf SG	43	unsigned int max_freq;
1b2fd5bf SG	44	unsigned int mode;
1b2fd5bf SG	45	ulong last_transaction_us; /* Time of last transaction end */
	46	u8 bits_per_word; /* max 16 bits per word */
	47	u8 n_bytes;
	48	unsigned int speed_hz;
28a943c1	49	unsigned int last_speed_hz;
1b2fd5bf SG	50	unsigned int tmode;
	51	uint input_rate;
	52	};
	53
	54	#define SPI_FIFO_DEPTH 32
	55
	56	static void rkspi_dump_regs(struct rockchip_spi *regs)
	57	{
	58	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	59	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	60	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	61	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	62	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	63	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	64	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	65	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	66	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	67	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	68	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	69	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	70	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	71	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	72	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
	73	}
	74
	75	static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
	76	{
	77	writel(enable ? 1 : 0, &regs->enr);
	78	}
	79
	80	static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
	81	{
9fc354e2 PT	82	/*
	83	* We should try not to exceed the speed requested by the caller:
	84	* when selecting a divider, we need to make sure we round up.
	85	*/
	86	uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
	87
	88	/* The baudrate register (BAUDR) is defined as a 32bit register where
	89	* the upper 16bit are reserved and having 'Fsclk_out' in the lower
	90	* 16bits with 'Fsclk_out' defined as follows:
	91	*
	92	* Fsclk_out = Fspi_clk/ SCKDV
	93	* Where SCKDV is any even value between 2 and 65534.
	94	*/
	95	if (clk_div > 0xfffe) {
	96	clk_div = 0xfffe;
	97	debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
	98	__func__, speed, priv->input_rate / clk_div);
	99	}
	100
	101	/* Round up to the next even 16bit number */
	102	clk_div = (clk_div + 1) & 0xfffe;
1b2fd5bf	103
1b2fd5bf SG	104	debug("spi speed %u, div %u\n", speed, clk_div);
1b2fd5bf SG	105
9fc354e2	106	clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
28a943c1	107	priv->last_speed_hz = speed;
1b2fd5bf SG	108	}
	109
	110	static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
	111	{
	112	unsigned long start;
	113
	114	start = get_timer(0);
	115	while (readl(&regs->sr) & SR_BUSY) {
	116	if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
	117	debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
	118	return -ETIMEDOUT;
	119	}
	120	}
	121
	122	return 0;
	123	}
	124
183a3a0f	125	static void spi_cs_activate(struct udevice *dev, uint cs)
1b2fd5bf	126	{
183a3a0f SG	127	struct udevice *bus = dev->parent;
	128	struct rockchip_spi_platdata *plat = bus->platdata;
	129	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	130	struct rockchip_spi *regs = priv->regs;
	131
b4252474 SG	132	/* If it's too soon to do another transaction, wait */
	133	if (plat->deactivate_delay_us && priv->last_transaction_us) {
	134	ulong delay_us; /* The delay completed so far */
	135	delay_us = timer_get_us() - priv->last_transaction_us;
	136	if (delay_us < plat->deactivate_delay_us)
	137	udelay(plat->deactivate_delay_us - delay_us);
	138	}
	139
1b2fd5bf SG	140	debug("activate cs%u\n", cs);
1b2fd5bf SG	141	writel(1 << cs, &regs->ser);
183a3a0f SG	142	if (plat->activate_delay_us)
183a3a0f SG	143	udelay(plat->activate_delay_us);
1b2fd5bf SG	144	}
1b2fd5bf SG	145
183a3a0f	146	static void spi_cs_deactivate(struct udevice *dev, uint cs)
1b2fd5bf	147	{
183a3a0f SG	148	struct udevice *bus = dev->parent;
	149	struct rockchip_spi_platdata *plat = bus->platdata;
	150	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	151	struct rockchip_spi *regs = priv->regs;
	152
1b2fd5bf SG	153	debug("deactivate cs%u\n", cs);
1b2fd5bf SG	154	writel(0, &regs->ser);
183a3a0f SG	155
	156	/* Remember time of this transaction so we can honour the bus delay */
	157	if (plat->deactivate_delay_us)
	158	priv->last_transaction_us = timer_get_us();
1b2fd5bf SG	159	}
1b2fd5bf SG	160
6e019c4f SG	161	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	162	static int conv_of_platdata(struct udevice *dev)
	163	{
	164	struct rockchip_spi_platdata *plat = dev->platdata;
	165	struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
	166	struct rockchip_spi_priv *priv = dev_get_priv(dev);
	167	int ret;
	168
	169	plat->base = dtplat->reg[0];
	170	plat->frequency = 20000000;
	171	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
	172	if (ret < 0)
	173	return ret;
	174	dev->req_seq = 0;
	175
	176	return 0;
	177	}
	178	#endif
	179
1b2fd5bf SG	180	static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
1b2fd5bf SG	181	{
6e019c4f SG	182	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
6e019c4f SG	183	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
71037d1c	184	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf	185	const void *blob = gd->fdt_blob;
e160f7d4	186	int node = dev_of_offset(bus);
1b2fd5bf SG	187	int ret;
	188
	189	plat->base = dev_get_addr(bus);
1b2fd5bf	190
71037d1c SG	191	ret = clk_get_by_index(bus, 0, &priv->clk);
	192	if (ret < 0) {
	193	debug("%s: Could not get clock for %s: %d\n", __func__,
	194	bus->name, ret);
	195	return ret;
	196	}
1b2fd5bf SG	197
1b2fd5bf SG	198	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
71037d1c	199	50000000);
1b2fd5bf SG	200	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
1b2fd5bf SG	201	"spi-deactivate-delay", 0);
183a3a0f SG	202	plat->activate_delay_us = fdtdec_get_int(blob, node,
183a3a0f SG	203	"spi-activate-delay", 0);
90a28470 SG	204	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
90a28470 SG	205	__func__, (uint)plat->base, plat->frequency,
1b2fd5bf	206	plat->deactivate_delay_us);
6e019c4f	207	#endif
1b2fd5bf SG	208
	209	return 0;
	210	}
	211
bd376714 PT	212	static int rockchip_spi_calc_modclk(ulong max_freq)
	213	{
	214	unsigned div;
	215	const unsigned long gpll_hz = 594000000UL;
	216
	217	/*
	218	* We need to find an input clock that provides at least twice
	219	* the maximum frequency and can be generated from the assumed
	220	* speed of GPLL (594MHz) using an integer divider.
	221	*
	222	* To give us more achievable bitrates at higher speeds (these
	223	* are generated by dividing by an even 16-bit integer from
	224	* this frequency), we try to have an input frequency of at
	225	* least 4x our max_freq.
	226	*/
	227
	228	div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
	229	return gpll_hz / div;
	230	}
	231
1b2fd5bf SG	232	static int rockchip_spi_probe(struct udevice *bus)
	233	{
	234	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	235	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	236	int ret;
	237
	238	debug("%s: probe\n", __func__);
6e019c4f SG	239	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	240	ret = conv_of_platdata(bus);
	241	if (ret)
	242	return ret;
	243	#endif
1b2fd5bf SG	244	priv->regs = (struct rockchip_spi *)plat->base;
	245
	246	priv->last_transaction_us = timer_get_us();
	247	priv->max_freq = plat->frequency;
1b2fd5bf	248
bd376714 PT	249	/* Clamp the value from the DTS against any hardware limits */
	250	if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
	251	priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
	252
	253	/* Find a module-input clock that fits with the max_freq setting */
	254	ret = clk_set_rate(&priv->clk,
	255	rockchip_spi_calc_modclk(priv->max_freq));
1b2fd5bf SG	256	if (ret < 0) {
	257	debug("%s: Failed to set clock: %d\n", __func__, ret);
	258	return ret;
	259	}
	260	priv->input_rate = ret;
	261	debug("%s: rate = %u\n", __func__, priv->input_rate);
	262	priv->bits_per_word = 8;
	263	priv->tmode = TMOD_TR; /* Tx & Rx */
	264
	265	return 0;
	266	}
	267
	268	static int rockchip_spi_claim_bus(struct udevice *dev)
	269	{
	270	struct udevice *bus = dev->parent;
1b2fd5bf SG	271	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	272	struct rockchip_spi *regs = priv->regs;
1b2fd5bf SG	273	u8 spi_dfs, spi_tf;
1b2fd5bf SG	274	uint ctrlr0;
1b2fd5bf SG	275
	276	/* Disable the SPI hardware */
	277	rkspi_enable_chip(regs, 0);
	278
	279	switch (priv->bits_per_word) {
	280	case 8:
	281	priv->n_bytes = 1;
	282	spi_dfs = DFS_8BIT;
	283	spi_tf = HALF_WORD_OFF;
	284	break;
	285	case 16:
	286	priv->n_bytes = 2;
	287	spi_dfs = DFS_16BIT;
	288	spi_tf = HALF_WORD_ON;
	289	break;
	290	default:
	291	debug("%s: unsupported bits: %dbits\n", __func__,
	292	priv->bits_per_word);
	293	return -EPROTONOSUPPORT;
	294	}
	295
28a943c1 SG	296	if (priv->speed_hz != priv->last_speed_hz)
28a943c1 SG	297	rkspi_set_clk(priv, priv->speed_hz);
1b2fd5bf SG	298
	299	/* Operation Mode */
	300	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
	301
	302	/* Data Frame Size */
2b9fe111	303	ctrlr0 \|= spi_dfs << DFS_SHIFT;
1b2fd5bf SG	304
	305	/* set SPI mode 0..3 */
	306	if (priv->mode & SPI_CPOL)
	307	ctrlr0 \|= SCOL_HIGH << SCOL_SHIFT;
	308	if (priv->mode & SPI_CPHA)
	309	ctrlr0 \|= SCPH_TOGSTA << SCPH_SHIFT;
	310
	311	/* Chip Select Mode */
	312	ctrlr0 \|= CSM_KEEP << CSM_SHIFT;
	313
	314	/* SSN to Sclk_out delay */
	315	ctrlr0 \|= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
	316
	317	/* Serial Endian Mode */
	318	ctrlr0 \|= SEM_LITTLE << SEM_SHIFT;
	319
	320	/* First Bit Mode */
	321	ctrlr0 \|= FBM_MSB << FBM_SHIFT;
	322
	323	/* Byte and Halfword Transform */
2b9fe111	324	ctrlr0 \|= spi_tf << HALF_WORD_TX_SHIFT;
1b2fd5bf SG	325
	326	/* Rxd Sample Delay */
	327	ctrlr0 \|= 0 << RXDSD_SHIFT;
	328
	329	/* Frame Format */
	330	ctrlr0 \|= FRF_SPI << FRF_SHIFT;
	331
	332	/* Tx and Rx mode */
	333	ctrlr0 \|= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
	334
	335	writel(ctrlr0, &regs->ctrlr0);
1b2fd5bf SG	336
	337	return 0;
	338	}
	339
	340	static int rockchip_spi_release_bus(struct udevice *dev)
	341	{
e15af8e2 SG	342	struct udevice *bus = dev->parent;
	343	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	344
	345	rkspi_enable_chip(priv->regs, false);
	346
1b2fd5bf SG	347	return 0;
	348	}
	349
	350	static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
	351	const void dout, void din, unsigned long flags)
	352	{
	353	struct udevice *bus = dev->parent;
	354	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	355	struct rockchip_spi *regs = priv->regs;
	356	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	357	int len = bitlen >> 3;
	358	const u8 *out = dout;
	359	u8 *in = din;
	360	int toread, towrite;
	361	int ret;
	362
	363	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	364	len, flags);
	365	if (DEBUG_RK_SPI)
	366	rkspi_dump_regs(regs);
	367
	368	/* Assert CS before transfer */
	369	if (flags & SPI_XFER_BEGIN)
183a3a0f	370	spi_cs_activate(dev, slave_plat->cs);
1b2fd5bf SG	371
	372	while (len > 0) {
	373	int todo = min(len, 0xffff);
	374
e15af8e2	375	rkspi_enable_chip(regs, false);
1b2fd5bf SG	376	writel(todo - 1, &regs->ctrlr1);
	377	rkspi_enable_chip(regs, true);
	378
	379	toread = todo;
	380	towrite = todo;
	381	while (toread \|\| towrite) {
	382	u32 status = readl(&regs->sr);
	383
	384	if (towrite && !(status & SR_TF_FULL)) {
	385	writel(out ? *out++ : 0, regs->txdr);
	386	towrite--;
	387	}
	388	if (toread && !(status & SR_RF_EMPT)) {
	389	u32 byte = readl(regs->rxdr);
	390
	391	if (in)
	392	*in++ = byte;
	393	toread--;
	394	}
	395	}
	396	ret = rkspi_wait_till_not_busy(regs);
	397	if (ret)
	398	break;
	399	len -= todo;
	400	}
	401
	402	/* Deassert CS after transfer */
	403	if (flags & SPI_XFER_END)
183a3a0f	404	spi_cs_deactivate(dev, slave_plat->cs);
1b2fd5bf SG	405
	406	rkspi_enable_chip(regs, false);
	407
	408	return ret;
	409	}
	410
	411	static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
	412	{
	413	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	414
bd376714	415	/* Clamp to the maximum frequency specified in the DTS */
1b2fd5bf SG	416	if (speed > priv->max_freq)
1b2fd5bf SG	417	speed = priv->max_freq;
bd376714	418
1b2fd5bf SG	419	priv->speed_hz = speed;
	420
	421	return 0;
	422	}
	423
	424	static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
	425	{
	426	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	427
	428	priv->mode = mode;
	429
	430	return 0;
	431	}
	432
	433	static const struct dm_spi_ops rockchip_spi_ops = {
	434	.claim_bus = rockchip_spi_claim_bus,
	435	.release_bus = rockchip_spi_release_bus,
	436	.xfer = rockchip_spi_xfer,
	437	.set_speed = rockchip_spi_set_speed,
	438	.set_mode = rockchip_spi_set_mode,
	439	/*
	440	* cs_info is not needed, since we require all chip selects to be
	441	* in the device tree explicitly
	442	*/
	443	};
	444
	445	static const struct udevice_id rockchip_spi_ids[] = {
	446	{ .compatible = "rockchip,rk3288-spi" },
	447	{ }
	448	};
	449
	450	U_BOOT_DRIVER(rockchip_spi) = {
6e019c4f SG	451	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	452	.name = "rockchip_rk3288_spi",
	453	#else
1b2fd5bf	454	.name = "rockchip_spi",
6e019c4f	455	#endif
1b2fd5bf SG	456	.id = UCLASS_SPI,
	457	.of_match = rockchip_spi_ids,
	458	.ops = &rockchip_spi_ops,
	459	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	460	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
	461	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
	462	.probe = rockchip_spi_probe,
	463	};