[thirdparty/u-boot.git] / drivers / spi / ti_qspi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * TI QSPI driver
 *
 * Copyright (C) 2013, Texas Instruments, Incorporated
 */

#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
#include <spi-mem.h>
#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <regmap.h>
#include <syscon.h>

DECLARE_GLOBAL_DATA_PTR;

/* ti qpsi register bit masks */
#define QSPI_TIMEOUT                    2000000
/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */
#define QSPI_FCLK                       (192000000 / 4)
#define QSPI_DRA7XX_FCLK                76800000
#define QSPI_WLEN_MAX_BITS		128
#define QSPI_WLEN_MAX_BYTES		(QSPI_WLEN_MAX_BITS >> 3)
#define QSPI_WLEN_MASK			QSPI_WLEN(QSPI_WLEN_MAX_BITS)
/* clock control */
#define QSPI_CLK_EN                     BIT(31)
#define QSPI_CLK_DIV_MAX                0xffff
/* command */
#define QSPI_EN_CS(n)                   (n << 28)
#define QSPI_WLEN(n)                    ((n-1) << 19)
#define QSPI_3_PIN                      BIT(18)
#define QSPI_RD_SNGL                    BIT(16)
#define QSPI_WR_SNGL                    (2 << 16)
#define QSPI_INVAL                      (4 << 16)
#define QSPI_RD_QUAD                    (7 << 16)
/* device control */
#define QSPI_CKPHA(n)                   (1 << (2 + n*8))
#define QSPI_CSPOL(n)                   (1 << (1 + n*8))
#define QSPI_CKPOL(n)                   (1 << (n*8))
/* status */
#define QSPI_WC                         BIT(1)
#define QSPI_BUSY                       BIT(0)
#define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE                  QSPI_WC
#define MM_SWITCH                       0x01
#define MEM_CS(cs)                      ((cs + 1) << 8)
#define MEM_CS_UNSELECT                 0xfffff8ff

#define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
#define QSPI_SETUP0_ADDR_SHIFT		(8)
#define QSPI_SETUP0_DBITS_SHIFT		(10)

#define TI_QSPI_SETUP_REG(priv, cs)	(&(priv)->base->setup0 + (cs))

/* ti qspi register set */
struct ti_qspi_regs {
	u32 pid;
	u32 pad0[3];
	u32 sysconfig;
	u32 pad1[3];
	u32 int_stat_raw;
	u32 int_stat_en;
	u32 int_en_set;
	u32 int_en_ctlr;
	u32 intc_eoi;
	u32 pad2[3];
	u32 clk_ctrl;
	u32 dc;
	u32 cmd;
	u32 status;
	u32 data;
	u32 setup0;
	u32 setup1;
	u32 setup2;
	u32 setup3;
	u32 memswitch;
	u32 data1;
	u32 data2;
	u32 data3;
};

/* ti qspi priv */
struct ti_qspi_priv {
	void *memory_map;
	size_t mmap_size;
	uint max_hz;
	u32 num_cs;
	struct ti_qspi_regs *base;
	void *ctrl_mod_mmap;
	ulong fclk;
	unsigned int mode;
	u32 cmd;
	u32 dc;
};

static int ti_qspi_set_speed(struct udevice *bus, uint hz)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	uint clk_div;

	if (!hz)
		clk_div = 0;
	else
		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;

	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	if (clk_div > QSPI_CLK_DIV_MAX)
		clk_div = QSPI_CLK_DIV_MAX;

	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);

	/* disable SCLK */
	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
	       &priv->base->clk_ctrl);
	/* enable SCLK and program the clk divider */
	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);

	return 0;
}

static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
	/* dummy readl to ensure bus sync */
	readl(&priv->base->cmd);
}

static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
	u32 val;

	val = readl(ctrl_mod_mmap);
	if (enable)
		val |= MEM_CS(cs);
	else
		val &= MEM_CS_UNSELECT;
	writel(val, ctrl_mod_mmap);
}

static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
			const void *dout, void *din, unsigned long flags)
{
	struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;
	uint words = bitlen >> 3; /* fixed 8-bit word length */
	const uchar *txp = dout;
	uchar *rxp = din;
	uint status;
	int timeout;
	unsigned int cs = slave->cs;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	if (bitlen == 0)
		return -1;

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	/* Setup command reg */
	priv->cmd = 0;
	priv->cmd |= QSPI_WLEN(8);
	priv->cmd |= QSPI_EN_CS(cs);
	if (priv->mode & SPI_3WIRE)
		priv->cmd |= QSPI_3_PIN;
	priv->cmd |= 0xfff;

	while (words) {
		u8 xfer_len = 0;

		if (txp) {
			u32 cmd = priv->cmd;

			if (words >= QSPI_WLEN_MAX_BYTES) {
				u32 *txbuf = (u32 *)txp;
				u32 data;

				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data3);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data2);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data1);
				data = cpu_to_be32(*txbuf++);
				writel(data, &priv->base->data);
				cmd &= ~QSPI_WLEN_MASK;
				cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
				xfer_len = QSPI_WLEN_MAX_BYTES;
			} else {
				writeb(*txp, &priv->base->data);
				xfer_len = 1;
			}
			debug("tx cmd %08x dc %08x\n",
			      cmd | QSPI_WR_SNGL, priv->dc);
			writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: TX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			txp += xfer_len;
			debug("tx done, status %08x\n", status);
		}
		if (rxp) {
			debug("rx cmd %08x dc %08x\n",
			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
			status = readl(&priv->base->status);
			timeout = QSPI_TIMEOUT;
			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
				if (--timeout < 0) {
					printf("spi_xfer: RX timeout!\n");
					return -1;
				}
				status = readl(&priv->base->status);
			}
			*rxp++ = readl(&priv->base->data);
			xfer_len = 1;
			debug("rx done, status %08x, read %02x\n",
			      status, *(rxp-1));
		}
		words -= xfer_len;
	}

	/* Terminate frame */
	if (flags & SPI_XFER_END)
		ti_qspi_cs_deactivate(priv);

	return 0;
}

/* TODO: control from sf layer to here through dm-spi */
static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
{
#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
	unsigned int			addr = (unsigned int) (data);
	unsigned int			edma_slot_num = 1;

	/* Invalidate the area, so no writeback into the RAM races with DMA */
	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));

	/* enable edma3 clocks */
	enable_edma3_clocks();

	/* Call edma3 api to do actual DMA transfer	*/
	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);

	/* disable edma3 clocks */
	disable_edma3_clocks();
#else
	memcpy_fromio(data, offset, len);
#endif

	*((unsigned int *)offset) += len;
}

static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
				    u8 opcode, u8 data_nbits, u8 addr_width,
				    u8 dummy_bytes)
{
	u32 memval = opcode;

	switch (data_nbits) {
	case 4:
		memval |= QSPI_SETUP0_READ_QUAD;
		break;
	case 2:
		memval |= QSPI_SETUP0_READ_DUAL;
		break;
	default:
		memval |= QSPI_SETUP0_READ_NORMAL;
		break;
	}

	memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
		   dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);

	writel(memval, TI_QSPI_SETUP_REG(priv, cs));
}

static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	priv->dc = 0;
	if (mode & SPI_CPHA)
		priv->dc |= QSPI_CKPHA(0);
	if (mode & SPI_CPOL)
		priv->dc |= QSPI_CKPOL(0);
	if (mode & SPI_CS_HIGH)
		priv->dc |= QSPI_CSPOL(0);

	return 0;
}

static int ti_qspi_exec_mem_op(struct spi_slave *slave,
			       const struct spi_mem_op *op)
{
	struct dm_spi_slave_plat *slave_plat;
	struct ti_qspi_priv *priv;
	struct udevice *bus;
	u32 from = 0;
	int ret = 0;

	bus = slave->dev->parent;
	priv = dev_get_priv(bus);
	slave_plat = dev_get_parent_plat(slave->dev);

	/* Only optimize read path. */
	if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
	    !op->addr.nbytes || op->addr.nbytes > 4)
		return -ENOTSUPP;

	/* Address exceeds MMIO window size, fall back to regular mode. */
	from = op->addr.val;
	if (from + op->data.nbytes > priv->mmap_size)
		return -ENOTSUPP;

	ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
				op->data.buswidth, op->addr.nbytes,
				op->dummy.nbytes);

	ti_qspi_copy_mmap((void *)op->data.buf.in,
			  (void *)priv->memory_map + from, op->data.nbytes);

	return ret;
}

static int ti_qspi_claim_bus(struct udevice *dev)
{
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	if (slave_plat->cs > priv->num_cs) {
		debug("invalid qspi chip select\n");
		return -EINVAL;
	}

	writel(MM_SWITCH, &priv->base->memswitch);
	if (priv->ctrl_mod_mmap)
		ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
				       slave_plat->cs, true);

	writel(priv->dc, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);

	priv->dc <<= slave_plat->cs * 8;
	writel(priv->dc, &priv->base->dc);

	return 0;
}

static int ti_qspi_release_bus(struct udevice *dev)
{
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	struct ti_qspi_priv *priv;
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	writel(~MM_SWITCH, &priv->base->memswitch);
	if (priv->ctrl_mod_mmap)
		ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
				       slave_plat->cs, false);

	writel(0, &priv->base->dc);
	writel(0, &priv->base->cmd);
	writel(0, &priv->base->data);
	writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));

	return 0;
}

static int ti_qspi_probe(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);

	priv->fclk = dev_get_driver_data(bus);

	return 0;
}

static void *map_syscon_chipselects(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(SYSCON)
	struct udevice *syscon;
	struct regmap *regmap;
	const fdt32_t *cell;
	int len, err;

	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
					   "syscon-chipselects", &syscon);
	if (err) {
		debug("%s: unable to find syscon device (%d)\n", __func__,
		      err);
		return NULL;
	}

	regmap = syscon_get_regmap(syscon);
	if (IS_ERR(regmap)) {
		debug("%s: unable to find regmap (%ld)\n", __func__,
		      PTR_ERR(regmap));
		return NULL;
	}

	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
			   "syscon-chipselects", &len);
	if (len < 2*sizeof(fdt32_t)) {
		debug("%s: offset not available\n", __func__);
		return NULL;
	}

	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
#else
	fdt_addr_t addr;
	addr = devfdt_get_addr_index(bus, 2);
	return (addr == FDT_ADDR_T_NONE) ? NULL :
		map_physmem(addr, 0, MAP_NOCACHE);
#endif
}

static int ti_qspi_of_to_plat(struct udevice *bus)
{
	struct ti_qspi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);
	fdt_addr_t mmap_addr;
	fdt_addr_t mmap_size;

	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
	priv->base = map_physmem(dev_read_addr(bus),
				 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
	mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
	priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
	priv->mmap_size = mmap_size;

	priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
	if (!priv->max_hz) {
		debug("Error: Max frequency missing\n");
		return -ENODEV;
	}
	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);

	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	      (int)priv->base, priv->max_hz);

	return 0;
}

static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
	.exec_op = ti_qspi_exec_mem_op,
};

static const struct dm_spi_ops ti_qspi_ops = {
	.claim_bus	= ti_qspi_claim_bus,
	.release_bus	= ti_qspi_release_bus,
	.xfer		= ti_qspi_xfer,
	.set_speed	= ti_qspi_set_speed,
	.set_mode	= ti_qspi_set_mode,
	.mem_ops        = &ti_qspi_mem_ops,
};

static const struct udevice_id ti_qspi_ids[] = {
	{ .compatible = "ti,dra7xxx-qspi",	.data = QSPI_DRA7XX_FCLK},
	{ .compatible = "ti,am4372-qspi",	.data = QSPI_FCLK},
	{ }
};

U_BOOT_DRIVER(ti_qspi) = {
	.name	= "ti_qspi",
	.id	= UCLASS_SPI,
	.of_match = ti_qspi_ids,
	.ops	= &ti_qspi_ops,
	.of_to_plat = ti_qspi_of_to_plat,
	.priv_auto	= sizeof(struct ti_qspi_priv),
	.probe	= ti_qspi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1d0933ea MP	2	/*
	3	* TI QSPI driver
	4	*
	5	* Copyright (C) 2013, Texas Instruments, Incorporated
1d0933ea MP	6	*/
1d0933ea MP	7
d678a59d	8	#include <common.h>
1eb69ae4	9	#include <cpu_func.h>
f7ae49fc	10	#include <log.h>
90526e9f	11	#include <asm/cache.h>
401d1c4f	12	#include <asm/global_data.h>
1d0933ea MP	13	#include <asm/io.h>
	14	#include <asm/arch/omap.h>
	15	#include <malloc.h>
	16	#include <spi.h>
4c96c612	17	#include <spi-mem.h>
106f8139	18	#include <dm.h>
570533b8 SP	19	#include <asm/gpio.h>
570533b8 SP	20	#include <asm/omap_gpio.h>
8ddd9c48 V	21	#include <asm/omap_common.h>
8ddd9c48 V	22	#include <asm/ti-common/ti-edma3.h>
cd93d625	23	#include <linux/bitops.h>
61b29b82	24	#include <linux/err.h>
948b8bbd	25	#include <linux/kernel.h>
b06a381a JJH	26	#include <regmap.h>
b06a381a JJH	27	#include <syscon.h>
1d0933ea	28
106f8139 M	29	DECLARE_GLOBAL_DATA_PTR;
106f8139 M	30
1d0933ea MP	31	/* ti qpsi register bit masks */
1d0933ea MP	32	#define QSPI_TIMEOUT 2000000
a6e562fe SM	33	/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */
a6e562fe SM	34	#define QSPI_FCLK (192000000 / 4)
a6f56ad1	35	#define QSPI_DRA7XX_FCLK 76800000
26036850 V	36	#define QSPI_WLEN_MAX_BITS 128
	37	#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
	38	#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
1d0933ea	39	/* clock control */
847720c4	40	#define QSPI_CLK_EN BIT(31)
1d0933ea MP	41	#define QSPI_CLK_DIV_MAX 0xffff
	42	/* command */
	43	#define QSPI_EN_CS(n) (n << 28)
	44	#define QSPI_WLEN(n) ((n-1) << 19)
847720c4 JT	45	#define QSPI_3_PIN BIT(18)
847720c4 JT	46	#define QSPI_RD_SNGL BIT(16)
1d0933ea MP	47	#define QSPI_WR_SNGL (2 << 16)
	48	#define QSPI_INVAL (4 << 16)
	49	#define QSPI_RD_QUAD (7 << 16)
	50	/* device control */
1d0933ea MP	51	#define QSPI_CKPHA(n) (1 << (2 + n*8))
	52	#define QSPI_CSPOL(n) (1 << (1 + n*8))
	53	#define QSPI_CKPOL(n) (1 << (n*8))
	54	/* status */
847720c4 JT	55	#define QSPI_WC BIT(1)
847720c4 JT	56	#define QSPI_BUSY BIT(0)
1d0933ea MP	57	#define QSPI_WC_BUSY (QSPI_WC \| QSPI_BUSY)
	58	#define QSPI_XFER_DONE QSPI_WC
	59	#define MM_SWITCH 0x01
ec712f49	60	#define MEM_CS(cs) ((cs + 1) << 8)
8dfd6e21	61	#define MEM_CS_UNSELECT 0xfffff8ff
1d0933ea	62
1d0933ea	63	#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
106f8139	64	#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
1d0933ea	65	#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
4c96c612 VR	66	#define QSPI_SETUP0_ADDR_SHIFT (8)
4c96c612 VR	67	#define QSPI_SETUP0_DBITS_SHIFT (10)
1d0933ea	68
5502c88e VR	69	#define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
5502c88e VR	70
1d0933ea MP	71	/* ti qspi register set */
	72	struct ti_qspi_regs {
	73	u32 pid;
	74	u32 pad0[3];
	75	u32 sysconfig;
	76	u32 pad1[3];
	77	u32 int_stat_raw;
	78	u32 int_stat_en;
	79	u32 int_en_set;
	80	u32 int_en_ctlr;
	81	u32 intc_eoi;
	82	u32 pad2[3];
	83	u32 clk_ctrl;
	84	u32 dc;
	85	u32 cmd;
	86	u32 status;
	87	u32 data;
	88	u32 setup0;
	89	u32 setup1;
	90	u32 setup2;
	91	u32 setup3;
	92	u32 memswitch;
	93	u32 data1;
	94	u32 data2;
	95	u32 data3;
	96	};
	97
9c42558a M	98	/* ti qspi priv */
9c42558a M	99	struct ti_qspi_priv {
106f8139	100	void *memory_map;
4c96c612	101	size_t mmap_size;
106f8139 M	102	uint max_hz;
106f8139 M	103	u32 num_cs;
1d0933ea	104	struct ti_qspi_regs *base;
22309144	105	void *ctrl_mod_mmap;
a6f56ad1	106	ulong fclk;
1d0933ea MP	107	unsigned int mode;
	108	u32 cmd;
	109	u32 dc;
	110	};
	111
61ae9782	112	static int ti_qspi_set_speed(struct udevice *bus, uint hz)
1d0933ea	113	{
61ae9782	114	struct ti_qspi_priv *priv = dev_get_priv(bus);
1d0933ea MP	115	uint clk_div;
1d0933ea MP	116
1d0933ea MP	117	if (!hz)
	118	clk_div = 0;
	119	else
948b8bbd V	120	clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
	121
	122	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
	123	if (clk_div > QSPI_CLK_DIV_MAX)
	124	clk_div = QSPI_CLK_DIV_MAX;
1d0933ea	125
c595a285 V	126	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
c595a285 V	127
1d0933ea	128	/* disable SCLK */
9c42558a M	129	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
9c42558a M	130	&priv->base->clk_ctrl);
948b8bbd	131	/* enable SCLK and program the clk divider */
9c42558a	132	writel(QSPI_CLK_EN \| clk_div, &priv->base->clk_ctrl);
61ae9782 VR	133
61ae9782 VR	134	return 0;
1d0933ea MP	135	}
1d0933ea MP	136
22309144	137	static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
1d0933ea	138	{
9c42558a	139	writel(priv->cmd \| QSPI_INVAL, &priv->base->cmd);
857db48e	140	/* dummy readl to ensure bus sync */
22309144	141	readl(&priv->base->cmd);
1d0933ea MP	142	}
1d0933ea MP	143
22309144 M	144	static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
	145	{
	146	u32 val;
	147
	148	val = readl(ctrl_mod_mmap);
	149	if (enable)
	150	val \|= MEM_CS(cs);
	151	else
	152	val &= MEM_CS_UNSELECT;
	153	writel(val, ctrl_mod_mmap);
	154	}
	155
61ae9782 VR	156	static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
61ae9782 VR	157	const void dout, void din, unsigned long flags)
1d0933ea	158	{
8a8d24bd	159	struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
61ae9782 VR	160	struct ti_qspi_priv *priv;
61ae9782 VR	161	struct udevice *bus;
1d0933ea MP	162	uint words = bitlen >> 3; /* fixed 8-bit word length */
	163	const uchar *txp = dout;
	164	uchar *rxp = din;
	165	uint status;
570533b8	166	int timeout;
61ae9782 VR	167	unsigned int cs = slave->cs;
	168
	169	bus = dev->parent;
	170	priv = dev_get_priv(bus);
	171
	172	if (cs > priv->num_cs) {
	173	debug("invalid qspi chip select\n");
	174	return -EINVAL;
	175	}
570533b8	176
1d0933ea MP	177	if (bitlen == 0)
	178	return -1;
	179
	180	if (bitlen % 8) {
	181	debug("spi_xfer: Non byte aligned SPI transfer\n");
	182	return -1;
	183	}
	184
	185	/* Setup command reg */
9c42558a M	186	priv->cmd = 0;
9c42558a M	187	priv->cmd \|= QSPI_WLEN(8);
22309144	188	priv->cmd \|= QSPI_EN_CS(cs);
9c42558a M	189	if (priv->mode & SPI_3WIRE)
	190	priv->cmd \|= QSPI_3_PIN;
	191	priv->cmd \|= 0xfff;
1d0933ea	192
26036850 V	193	while (words) {
	194	u8 xfer_len = 0;
	195
1d0933ea	196	if (txp) {
26036850 V	197	u32 cmd = priv->cmd;
	198
	199	if (words >= QSPI_WLEN_MAX_BYTES) {
	200	u32 txbuf = (u32 )txp;
	201	u32 data;
	202
	203	data = cpu_to_be32(*txbuf++);
	204	writel(data, &priv->base->data3);
	205	data = cpu_to_be32(*txbuf++);
	206	writel(data, &priv->base->data2);
	207	data = cpu_to_be32(*txbuf++);
	208	writel(data, &priv->base->data1);
	209	data = cpu_to_be32(*txbuf++);
	210	writel(data, &priv->base->data);
	211	cmd &= ~QSPI_WLEN_MASK;
	212	cmd \|= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
	213	xfer_len = QSPI_WLEN_MAX_BYTES;
	214	} else {
	215	writeb(*txp, &priv->base->data);
	216	xfer_len = 1;
	217	}
	218	debug("tx cmd %08x dc %08x\n",
	219	cmd \| QSPI_WR_SNGL, priv->dc);
	220	writel(cmd \| QSPI_WR_SNGL, &priv->base->cmd);
9c42558a	221	status = readl(&priv->base->status);
1d0933ea MP	222	timeout = QSPI_TIMEOUT;
	223	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	224	if (--timeout < 0) {
	225	printf("spi_xfer: TX timeout!\n");
	226	return -1;
	227	}
9c42558a	228	status = readl(&priv->base->status);
1d0933ea	229	}
26036850	230	txp += xfer_len;
1d0933ea MP	231	debug("tx done, status %08x\n", status);
	232	}
	233	if (rxp) {
1d0933ea	234	debug("rx cmd %08x dc %08x\n",
69eeefaa	235	((u32)(priv->cmd \| QSPI_RD_SNGL)), priv->dc);
69eeefaa	236	writel(priv->cmd \| QSPI_RD_SNGL, &priv->base->cmd);
9c42558a	237	status = readl(&priv->base->status);
1d0933ea MP	238	timeout = QSPI_TIMEOUT;
	239	while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
	240	if (--timeout < 0) {
	241	printf("spi_xfer: RX timeout!\n");
	242	return -1;
	243	}
9c42558a	244	status = readl(&priv->base->status);
1d0933ea	245	}
9c42558a	246	*rxp++ = readl(&priv->base->data);
26036850	247	xfer_len = 1;
1d0933ea MP	248	debug("rx done, status %08x, read %02x\n",
	249	status, *(rxp-1));
	250	}
26036850	251	words -= xfer_len;
1d0933ea MP	252	}
	253
	254	/* Terminate frame */
	255	if (flags & SPI_XFER_END)
22309144	256	ti_qspi_cs_deactivate(priv);
1d0933ea MP	257
	258	return 0;
	259	}
8ddd9c48 V	260
8ddd9c48 V	261	/* TODO: control from sf layer to here through dm-spi */
4c96c612	262	static void ti_qspi_copy_mmap(void data, void offset, size_t len)
8ddd9c48	263	{
4c96c612	264	#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
8ddd9c48 V	265	unsigned int addr = (unsigned int) (data);
	266	unsigned int edma_slot_num = 1;
	267
	268	/* Invalidate the area, so no writeback into the RAM races with DMA */
	269	invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
	270
	271	/* enable edma3 clocks */
	272	enable_edma3_clocks();
	273
	274	/* Call edma3 api to do actual DMA transfer */
	275	edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
	276
	277	/* disable edma3 clocks */
	278	disable_edma3_clocks();
4c96c612 VR	279	#else
	280	memcpy_fromio(data, offset, len);
	281	#endif
8ddd9c48 V	282
	283	((unsigned int )offset) += len;
	284	}
22309144	285
5502c88e VR	286	static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
5502c88e VR	287	u8 opcode, u8 data_nbits, u8 addr_width,
4c96c612	288	u8 dummy_bytes)
106f8139	289	{
4c96c612	290	u32 memval = opcode;
106f8139	291
4c96c612 VR	292	switch (data_nbits) {
4c96c612 VR	293	case 4:
106f8139	294	memval \|= QSPI_SETUP0_READ_QUAD;
106f8139	295	break;
4c96c612	296	case 2:
106f8139 M	297	memval \|= QSPI_SETUP0_READ_DUAL;
	298	break;
	299	default:
106f8139 M	300	memval \|= QSPI_SETUP0_READ_NORMAL;
	301	break;
	302	}
	303
4c96c612 VR	304	memval \|= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT \|
	305	dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
	306
5502c88e	307	writel(memval, TI_QSPI_SETUP_REG(priv, cs));
106f8139 M	308	}
106f8139 M	309
61ae9782	310	static int ti_qspi_set_mode(struct udevice *bus, uint mode)
106f8139 M	311	{
	312	struct ti_qspi_priv *priv = dev_get_priv(bus);
	313
61ae9782 VR	314	priv->dc = 0;
	315	if (mode & SPI_CPHA)
	316	priv->dc \|= QSPI_CKPHA(0);
	317	if (mode & SPI_CPOL)
	318	priv->dc \|= QSPI_CKPOL(0);
	319	if (mode & SPI_CS_HIGH)
	320	priv->dc \|= QSPI_CSPOL(0);
106f8139 M	321
	322	return 0;
	323	}
	324
4c96c612 VR	325	static int ti_qspi_exec_mem_op(struct spi_slave *slave,
	326	const struct spi_mem_op *op)
	327	{
8a8d24bd	328	struct dm_spi_slave_plat *slave_plat;
4c96c612 VR	329	struct ti_qspi_priv *priv;
4c96c612 VR	330	struct udevice *bus;
5502c88e VR	331	u32 from = 0;
5502c88e VR	332	int ret = 0;
4c96c612 VR	333
	334	bus = slave->dev->parent;
	335	priv = dev_get_priv(bus);
caa4daa2	336	slave_plat = dev_get_parent_plat(slave->dev);
4c96c612 VR	337
	338	/* Only optimize read path. */
	339	if (!op->data.nbytes \|\| op->data.dir != SPI_MEM_DATA_IN \|\|
	340	!op->addr.nbytes \|\| op->addr.nbytes > 4)
	341	return -ENOTSUPP;
	342
	343	/* Address exceeds MMIO window size, fall back to regular mode. */
	344	from = op->addr.val;
	345	if (from + op->data.nbytes > priv->mmap_size)
	346	return -ENOTSUPP;
	347
5502c88e VR	348	ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
	349	op->data.buswidth, op->addr.nbytes,
	350	op->dummy.nbytes);
4c96c612 VR	351
	352	ti_qspi_copy_mmap((void *)op->data.buf.in,
	353	(void *)priv->memory_map + from, op->data.nbytes);
	354
	355	return ret;
	356	}
	357
106f8139 M	358	static int ti_qspi_claim_bus(struct udevice *dev)
106f8139 M	359	{
8a8d24bd	360	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
106f8139 M	361	struct ti_qspi_priv *priv;
	362	struct udevice *bus;
	363
	364	bus = dev->parent;
	365	priv = dev_get_priv(bus);
	366
	367	if (slave_plat->cs > priv->num_cs) {
	368	debug("invalid qspi chip select\n");
	369	return -EINVAL;
	370	}
	371
4c96c612 VR	372	writel(MM_SWITCH, &priv->base->memswitch);
	373	if (priv->ctrl_mod_mmap)
	374	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
	375	slave_plat->cs, true);
106f8139	376
61ae9782 VR	377	writel(priv->dc, &priv->base->dc);
	378	writel(0, &priv->base->cmd);
	379	writel(0, &priv->base->data);
	380
	381	priv->dc <<= slave_plat->cs * 8;
	382	writel(priv->dc, &priv->base->dc);
	383
	384	return 0;
106f8139 M	385	}
	386
	387	static int ti_qspi_release_bus(struct udevice *dev)
	388	{
8a8d24bd	389	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
106f8139 M	390	struct ti_qspi_priv *priv;
	391	struct udevice *bus;
	392
	393	bus = dev->parent;
	394	priv = dev_get_priv(bus);
	395
4c96c612 VR	396	writel(~MM_SWITCH, &priv->base->memswitch);
	397	if (priv->ctrl_mod_mmap)
	398	ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
	399	slave_plat->cs, false);
106f8139	400
61ae9782 VR	401	writel(0, &priv->base->dc);
	402	writel(0, &priv->base->cmd);
	403	writel(0, &priv->base->data);
5502c88e	404	writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
106f8139	405
61ae9782	406	return 0;
106f8139 M	407	}
	408
	409	static int ti_qspi_probe(struct udevice *bus)
	410	{
a6f56ad1 V	411	struct ti_qspi_priv *priv = dev_get_priv(bus);
	412
	413	priv->fclk = dev_get_driver_data(bus);
	414
106f8139 M	415	return 0;
	416	}
	417
b06a381a JJH	418	static void map_syscon_chipselects(struct udevice bus)
	419	{
	420	#if CONFIG_IS_ENABLED(SYSCON)
	421	struct udevice *syscon;
	422	struct regmap *regmap;
	423	const fdt32_t *cell;
	424	int len, err;
	425
	426	err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
	427	"syscon-chipselects", &syscon);
	428	if (err) {
	429	debug("%s: unable to find syscon device (%d)\n", __func__,
	430	err);
	431	return NULL;
	432	}
	433
	434	regmap = syscon_get_regmap(syscon);
	435	if (IS_ERR(regmap)) {
	436	debug("%s: unable to find regmap (%ld)\n", __func__,
	437	PTR_ERR(regmap));
	438	return NULL;
	439	}
	440
da409ccc SG	441	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
da409ccc SG	442	"syscon-chipselects", &len);
b06a381a JJH	443	if (len < 2*sizeof(fdt32_t)) {
	444	debug("%s: offset not available\n", __func__);
	445	return NULL;
	446	}
	447
	448	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
	449	#else
	450	fdt_addr_t addr;
a821c4af	451	addr = devfdt_get_addr_index(bus, 2);
b06a381a JJH	452	return (addr == FDT_ADDR_T_NONE) ? NULL :
	453	map_physmem(addr, 0, MAP_NOCACHE);
	454	#endif
	455	}
	456
d1998a9f	457	static int ti_qspi_of_to_plat(struct udevice *bus)
106f8139 M	458	{
	459	struct ti_qspi_priv *priv = dev_get_priv(bus);
	460	const void *blob = gd->fdt_blob;
e160f7d4	461	int node = dev_of_offset(bus);
4c96c612 VR	462	fdt_addr_t mmap_addr;
4c96c612 VR	463	fdt_addr_t mmap_size;
106f8139	464
b06a381a	465	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
2548493a	466	priv->base = map_physmem(dev_read_addr(bus),
a821c4af	467	sizeof(struct ti_qspi_regs), MAP_NOCACHE);
4c96c612 VR	468	mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
	469	priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
	470	priv->mmap_size = mmap_size;
106f8139	471
705082d4 OP	472	priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
705082d4 OP	473	if (!priv->max_hz) {
106f8139 M	474	debug("Error: Max frequency missing\n");
	475	return -ENODEV;
	476	}
	477	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
	478
	479	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
	480	(int)priv->base, priv->max_hz);
	481
	482	return 0;
	483	}
	484
4c96c612 VR	485	static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
	486	.exec_op = ti_qspi_exec_mem_op,
	487	};
106f8139 M	488
	489	static const struct dm_spi_ops ti_qspi_ops = {
	490	.claim_bus = ti_qspi_claim_bus,
	491	.release_bus = ti_qspi_release_bus,
	492	.xfer = ti_qspi_xfer,
	493	.set_speed = ti_qspi_set_speed,
	494	.set_mode = ti_qspi_set_mode,
4c96c612	495	.mem_ops = &ti_qspi_mem_ops,
106f8139 M	496	};
	497
	498	static const struct udevice_id ti_qspi_ids[] = {
a6f56ad1 V	499	{ .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
a6f56ad1 V	500	{ .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
106f8139 M	501	{ }
	502	};
	503
	504	U_BOOT_DRIVER(ti_qspi) = {
	505	.name = "ti_qspi",
	506	.id = UCLASS_SPI,
	507	.of_match = ti_qspi_ids,
	508	.ops = &ti_qspi_ops,
d1998a9f	509	.of_to_plat = ti_qspi_of_to_plat,
41575d8e	510	.priv_auto = sizeof(struct ti_qspi_priv),
106f8139	511	.probe = ti_qspi_probe,
106f8139	512	};