[thirdparty/u-boot.git] / drivers / spi / zynq_spi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013 Xilinx, Inc.
 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
 *
 * Xilinx Zynq PS SPI controller driver (master mode only)
 */

#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
#include <time.h>
#include <clk.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>

DECLARE_GLOBAL_DATA_PTR;

/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
#define ZYNQ_SPI_CR_CS_MASK		GENMASK(13, 10)	/* Chip select */
#define ZYNQ_SPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
#define ZYNQ_SPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */

#define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
#define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
#define ZYNQ_SPI_CR_SS_SHIFT		10	/* Slave select shift */

#define ZYNQ_SPI_FIFO_DEPTH		128
#define ZYNQ_SPI_WAIT			(CONFIG_SYS_HZ / 100)	/* 10 ms */

/* zynq spi register set */
struct zynq_spi_regs {
	u32 cr;		/* 0x00 */
	u32 isr;	/* 0x04 */
	u32 ier;	/* 0x08 */
	u32 idr;	/* 0x0C */
	u32 imr;	/* 0x10 */
	u32 enr;	/* 0x14 */
	u32 dr;		/* 0x18 */
	u32 txdr;	/* 0x1C */
	u32 rxdr;	/* 0x20 */
};


/* zynq spi platform data */
struct zynq_spi_plat {
	struct zynq_spi_regs *regs;
	u32 frequency;		/* input frequency */
	u32 speed_hz;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
	uint activate_delay_us;		/* Delay to wait after activate */
};

/* zynq spi priv */
struct zynq_spi_priv {
	struct zynq_spi_regs *regs;
	u8 cs;
	u8 mode;
	ulong last_transaction_us;	/* Time of last transaction end */
	u8 fifo_depth;
	u32 freq;		/* required frequency */
};

static int zynq_spi_of_to_plat(struct udevice *bus)
{
	struct zynq_spi_plat *plat = dev_get_plat(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	plat->regs = dev_read_addr_ptr(bus);

	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	plat->activate_delay_us = fdtdec_get_int(blob, node,
						 "spi-activate-delay", 0);

	return 0;
}

static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
{
	struct zynq_spi_regs *regs = priv->regs;
	u32 confr;

	/* Disable SPI */
	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
	writel(~confr, &regs->enr);

	/* Disable Interrupts */
	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);

	/* Clear RX FIFO */
	while (readl(&regs->isr) &
			ZYNQ_SPI_IXR_RXNEMPTY_MASK)
		readl(&regs->rxdr);

	/* Clear Interrupts */
	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);

	/* Manual slave select and Auto start */
	confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
		ZYNQ_SPI_CR_MSTREN_MASK;
	confr &= ~ZYNQ_SPI_CR_MSA_MASK;
	writel(confr, &regs->cr);

	/* Enable SPI */
	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
}

static int zynq_spi_probe(struct udevice *bus)
{
	struct zynq_spi_plat *plat = dev_get_plat(bus);
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct clk clk;
	unsigned long clock;
	int ret;

	priv->regs = plat->regs;
	priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;

	ret = clk_get_by_name(bus, "ref_clk", &clk);
	if (ret < 0) {
		dev_err(bus, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk);
	if (IS_ERR_VALUE(clock)) {
		dev_err(bus, "failed to get rate\n");
		return clock;
	}

	ret = clk_enable(&clk);
	if (ret) {
		dev_err(bus, "failed to enable clock\n");
		return ret;
	}

	/* init the zynq spi hw */
	zynq_spi_init_hw(priv);

	plat->frequency = clock;
	plat->speed_hz = plat->frequency / 2;

	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);

	return 0;
}

static void spi_cs_activate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_plat *plat = dev_get_plat(bus);
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	u32 cr;

	/* If it's too soon to do another transaction, wait */
	if (plat->deactivate_delay_us && priv->last_transaction_us) {
		ulong delay_us;		/* The delay completed so far */
		delay_us = timer_get_us() - priv->last_transaction_us;
		if (delay_us < plat->deactivate_delay_us)
			udelay(plat->deactivate_delay_us - delay_us);
	}

	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
	cr = readl(&regs->cr);
	/*
	 * CS cal logic: CS[13:10]
	 * xxx0	- cs0
	 * xx01	- cs1
	 * x011 - cs2
	 */
	cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
	writel(cr, &regs->cr);

	if (plat->activate_delay_us)
		udelay(plat->activate_delay_us);
}

static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_plat *plat = dev_get_plat(bus);
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;

	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);

	/* Remember time of this transaction so we can honour the bus delay */
	if (plat->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();
}

static int zynq_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;

	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);

	return 0;
}

static int zynq_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	u32 confr;

	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
	writel(~confr, &regs->enr);

	return 0;
}

static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
			    const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	u32 len = bitlen / 8;
	u32 tx_len = len, rx_len = len, tx_tvl;
	const u8 *tx_buf = dout;
	u8 *rx_buf = din, buf;
	u32 ts, status;

	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
	      dev_seq(bus), slave_plat->cs, bitlen, len, flags);

	if (bitlen % 8) {
		debug("spi_xfer: Non byte aligned SPI transfer\n");
		return -1;
	}

	priv->cs = slave_plat->cs;
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev);

	while (rx_len > 0) {
		/* Write the data into TX FIFO - tx threshold is fifo_depth */
		tx_tvl = 0;
		while ((tx_tvl < priv->fifo_depth) && tx_len) {
			if (tx_buf)
				buf = *tx_buf++;
			else
				buf = 0;
			writel(buf, &regs->txdr);
			tx_len--;
			tx_tvl++;
		}

		/* Check TX FIFO completion */
		ts = get_timer(0);
		status = readl(&regs->isr);
		while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
			if (get_timer(ts) > ZYNQ_SPI_WAIT) {
				printf("spi_xfer: Timeout! TX FIFO not full\n");
				return -1;
			}
			status = readl(&regs->isr);
		}

		/* Read the data from RX FIFO */
		status = readl(&regs->isr);
		while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
			buf = readl(&regs->rxdr);
			if (rx_buf)
				*rx_buf++ = buf;
			status = readl(&regs->isr);
			rx_len--;
		}
	}

	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev);

	return 0;
}

static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
	struct zynq_spi_plat *plat = dev_get_plat(bus);
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	uint32_t confr;
	u8 baud_rate_val = 0;

	if (speed > plat->frequency)
		speed = plat->frequency;

	/* Set the clock frequency */
	confr = readl(&regs->cr);
	if (speed == 0) {
		/* Set baudrate x8, if the freq is 0 */
		baud_rate_val = 0x2;
	} else if (plat->speed_hz != speed) {
		while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
				((plat->frequency /
				(2 << baud_rate_val)) > speed))
			baud_rate_val++;
		plat->speed_hz = speed / (2 << baud_rate_val);
	}
	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);

	writel(confr, &regs->cr);
	priv->freq = speed;

	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
	      priv->regs, priv->freq);

	return 0;
}

static int zynq_spi_set_mode(struct udevice *bus, uint mode)
{
	struct zynq_spi_priv *priv = dev_get_priv(bus);
	struct zynq_spi_regs *regs = priv->regs;
	uint32_t confr;

	/* Set the SPI Clock phase and polarities */
	confr = readl(&regs->cr);
	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);

	if (mode & SPI_CPHA)
		confr |= ZYNQ_SPI_CR_CPHA_MASK;
	if (mode & SPI_CPOL)
		confr |= ZYNQ_SPI_CR_CPOL_MASK;

	writel(confr, &regs->cr);
	priv->mode = mode;

	debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops zynq_spi_ops = {
	.claim_bus	= zynq_spi_claim_bus,
	.release_bus	= zynq_spi_release_bus,
	.xfer		= zynq_spi_xfer,
	.set_speed	= zynq_spi_set_speed,
	.set_mode	= zynq_spi_set_mode,
};

static const struct udevice_id zynq_spi_ids[] = {
	{ .compatible = "xlnx,zynq-spi-r1p6" },
	{ .compatible = "cdns,spi-r1p6" },
	{ }
};

U_BOOT_DRIVER(zynq_spi) = {
	.name	= "zynq_spi",
	.id	= UCLASS_SPI,
	.of_match = zynq_spi_ids,
	.ops	= &zynq_spi_ops,
	.of_to_plat = zynq_spi_of_to_plat,
	.plat_auto	= sizeof(struct zynq_spi_plat),
	.priv_auto	= sizeof(struct zynq_spi_priv),
	.probe	= zynq_spi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1465d055	2	/*
86e99b98	3	* (C) Copyright 2013 Xilinx, Inc.
b1c82da2	4	* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
1465d055 JT	5	*
1465d055 JT	6	* Xilinx Zynq PS SPI controller driver (master mode only)
1465d055 JT	7	*/
1465d055 JT	8
d678a59d	9	#include <common.h>
b1c82da2	10	#include <dm.h>
b79a7030	11	#include <dm/device_compat.h>
f7ae49fc	12	#include <log.h>
1465d055 JT	13	#include <malloc.h>
1465d055 JT	14	#include <spi.h>
1045315d	15	#include <time.h>
b79a7030	16	#include <clk.h>
401d1c4f	17	#include <asm/global_data.h>
1465d055	18	#include <asm/io.h>
cd93d625	19	#include <linux/bitops.h>
c05ed00a	20	#include <linux/delay.h>
1465d055	21
cdc9dd07 JT	22	DECLARE_GLOBAL_DATA_PTR;
cdc9dd07 JT	23
1465d055	24	/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
736b4df1 JT	25	#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
736b4df1 JT	26	#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
9cf2ffb3 JT	27	#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
9cf2ffb3 JT	28	#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
736b4df1 JT	29	#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
	30	#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
	31	#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
	32	#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
	33	#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
9cf2ffb3	34	#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
736b4df1	35	#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
1465d055	36
46ab8a6a JT	37	#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
	38	#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
	39	#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
	40
1465d055	41	#define ZYNQ_SPI_FIFO_DEPTH 128
f44bd3bc	42	#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
1465d055 JT	43
	44	/* zynq spi register set */
	45	struct zynq_spi_regs {
	46	u32 cr; /* 0x00 */
	47	u32 isr; /* 0x04 */
	48	u32 ier; /* 0x08 */
	49	u32 idr; /* 0x0C */
	50	u32 imr; /* 0x10 */
	51	u32 enr; /* 0x14 */
	52	u32 dr; /* 0x18 */
	53	u32 txdr; /* 0x1C */
	54	u32 rxdr; /* 0x20 */
	55	};
	56
b1c82da2 JT	57
b1c82da2 JT	58	/* zynq spi platform data */
8a8d24bd	59	struct zynq_spi_plat {
b1c82da2 JT	60	struct zynq_spi_regs *regs;
b1c82da2 JT	61	u32 frequency; /* input frequency */
1465d055	62	u32 speed_hz;
ac6991fb MF	63	uint deactivate_delay_us; /* Delay to wait after deactivate */
ac6991fb MF	64	uint activate_delay_us; /* Delay to wait after activate */
1465d055 JT	65	};
1465d055 JT	66
b1c82da2 JT	67	/* zynq spi priv */
	68	struct zynq_spi_priv {
	69	struct zynq_spi_regs *regs;
19126998	70	u8 cs;
b1c82da2	71	u8 mode;
ac6991fb	72	ulong last_transaction_us; /* Time of last transaction end */
b1c82da2 JT	73	u8 fifo_depth;
	74	u32 freq; /* required frequency */
	75	};
1465d055	76
d1998a9f	77	static int zynq_spi_of_to_plat(struct udevice *bus)
1465d055	78	{
0fd3d911	79	struct zynq_spi_plat *plat = dev_get_plat(bus);
cdc9dd07	80	const void *blob = gd->fdt_blob;
e160f7d4	81	int node = dev_of_offset(bus);
cdc9dd07	82
8613c8d8	83	plat->regs = dev_read_addr_ptr(bus);
b1c82da2	84
ac6991fb MF	85	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
	86	"spi-deactivate-delay", 0);
	87	plat->activate_delay_us = fdtdec_get_int(blob, node,
	88	"spi-activate-delay", 0);
cdc9dd07	89
b1c82da2 JT	90	return 0;
	91	}
	92
	93	static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
	94	{
	95	struct zynq_spi_regs *regs = priv->regs;
1465d055 JT	96	u32 confr;
	97
	98	/* Disable SPI */
5f647c22 MS	99	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
5f647c22 MS	100	writel(~confr, &regs->enr);
1465d055 JT	101
1465d055 JT	102	/* Disable Interrupts */
b1c82da2	103	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
1465d055 JT	104
1465d055 JT	105	/* Clear RX FIFO */
b1c82da2	106	while (readl(&regs->isr) &
1465d055	107	ZYNQ_SPI_IXR_RXNEMPTY_MASK)
b1c82da2	108	readl(&regs->rxdr);
1465d055 JT	109
1465d055 JT	110	/* Clear Interrupts */
b1c82da2	111	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
1465d055 JT	112
	113	/* Manual slave select and Auto start */
	114	confr = ZYNQ_SPI_CR_MCS_MASK \| ZYNQ_SPI_CR_CS_MASK \|
	115	ZYNQ_SPI_CR_MSTREN_MASK;
	116	confr &= ~ZYNQ_SPI_CR_MSA_MASK;
b1c82da2	117	writel(confr, &regs->cr);
1465d055 JT	118
1465d055 JT	119	/* Enable SPI */
b1c82da2	120	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
1465d055 JT	121	}
1465d055 JT	122
b1c82da2	123	static int zynq_spi_probe(struct udevice *bus)
1465d055	124	{
8a8d24bd	125	struct zynq_spi_plat *plat = dev_get_plat(bus);
b1c82da2	126	struct zynq_spi_priv *priv = dev_get_priv(bus);
b79a7030 KR	127	struct clk clk;
	128	unsigned long clock;
	129	int ret;
b1c82da2 JT	130
	131	priv->regs = plat->regs;
	132	priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
	133
b79a7030 KR	134	ret = clk_get_by_name(bus, "ref_clk", &clk);
	135	if (ret < 0) {
	136	dev_err(bus, "failed to get clock\n");
	137	return ret;
	138	}
	139
	140	clock = clk_get_rate(&clk);
	141	if (IS_ERR_VALUE(clock)) {
	142	dev_err(bus, "failed to get rate\n");
	143	return clock;
	144	}
	145
	146	ret = clk_enable(&clk);
9b7aac75	147	if (ret) {
b79a7030 KR	148	dev_err(bus, "failed to enable clock\n");
	149	return ret;
	150	}
	151
b1c82da2 JT	152	/* init the zynq spi hw */
	153	zynq_spi_init_hw(priv);
	154
b79a7030 KR	155	plat->frequency = clock;
	156	plat->speed_hz = plat->frequency / 2;
	157
	158	debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
	159
b1c82da2	160	return 0;
1465d055 JT	161	}
1465d055 JT	162
19126998	163	static void spi_cs_activate(struct udevice *dev)
1465d055	164	{
b1c82da2	165	struct udevice *bus = dev->parent;
0fd3d911	166	struct zynq_spi_plat *plat = dev_get_plat(bus);
b1c82da2 JT	167	struct zynq_spi_priv *priv = dev_get_priv(bus);
b1c82da2 JT	168	struct zynq_spi_regs *regs = priv->regs;
1465d055 JT	169	u32 cr;
1465d055 JT	170
ac6991fb MF	171	/* If it's too soon to do another transaction, wait */
	172	if (plat->deactivate_delay_us && priv->last_transaction_us) {
	173	ulong delay_us; /* The delay completed so far */
	174	delay_us = timer_get_us() - priv->last_transaction_us;
	175	if (delay_us < plat->deactivate_delay_us)
	176	udelay(plat->deactivate_delay_us - delay_us);
	177	}
	178
b1c82da2 JT	179	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
b1c82da2 JT	180	cr = readl(&regs->cr);
1465d055 JT	181	/*
	182	* CS cal logic: CS[13:10]
	183	* xxx0 - cs0
	184	* xx01 - cs1
	185	* x011 - cs2
	186	*/
19126998	187	cr \|= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
b1c82da2	188	writel(cr, &regs->cr);
ac6991fb MF	189
	190	if (plat->activate_delay_us)
	191	udelay(plat->activate_delay_us);
1465d055 JT	192	}
1465d055 JT	193
b1c82da2	194	static void spi_cs_deactivate(struct udevice *dev)
1465d055	195	{
b1c82da2	196	struct udevice *bus = dev->parent;
0fd3d911	197	struct zynq_spi_plat *plat = dev_get_plat(bus);
b1c82da2 JT	198	struct zynq_spi_priv *priv = dev_get_priv(bus);
b1c82da2 JT	199	struct zynq_spi_regs *regs = priv->regs;
1465d055	200
b1c82da2	201	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
ac6991fb MF	202
	203	/* Remember time of this transaction so we can honour the bus delay */
	204	if (plat->deactivate_delay_us)
	205	priv->last_transaction_us = timer_get_us();
1465d055 JT	206	}
1465d055 JT	207
b1c82da2	208	static int zynq_spi_claim_bus(struct udevice *dev)
1465d055	209	{
b1c82da2 JT	210	struct udevice *bus = dev->parent;
	211	struct zynq_spi_priv *priv = dev_get_priv(bus);
	212	struct zynq_spi_regs *regs = priv->regs;
1465d055	213
b1c82da2	214	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
1465d055	215
b1c82da2	216	return 0;
1465d055 JT	217	}
1465d055 JT	218
b1c82da2	219	static int zynq_spi_release_bus(struct udevice *dev)
1465d055	220	{
b1c82da2 JT	221	struct udevice *bus = dev->parent;
	222	struct zynq_spi_priv *priv = dev_get_priv(bus);
	223	struct zynq_spi_regs *regs = priv->regs;
5f647c22	224	u32 confr;
1465d055	225
5f647c22 MS	226	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
5f647c22 MS	227	writel(~confr, &regs->enr);
1465d055 JT	228
	229	return 0;
	230	}
	231
b1c82da2 JT	232	static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
b1c82da2 JT	233	const void dout, void din, unsigned long flags)
1465d055	234	{
b1c82da2 JT	235	struct udevice *bus = dev->parent;
	236	struct zynq_spi_priv *priv = dev_get_priv(bus);
	237	struct zynq_spi_regs *regs = priv->regs;
8a8d24bd	238	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
1465d055 JT	239	u32 len = bitlen / 8;
	240	u32 tx_len = len, rx_len = len, tx_tvl;
	241	const u8 *tx_buf = dout;
	242	u8 *rx_buf = din, buf;
	243	u32 ts, status;
	244
	245	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
8b85dfc6	246	dev_seq(bus), slave_plat->cs, bitlen, len, flags);
1465d055	247
1465d055 JT	248	if (bitlen % 8) {
	249	debug("spi_xfer: Non byte aligned SPI transfer\n");
	250	return -1;
	251	}
	252
19126998	253	priv->cs = slave_plat->cs;
1465d055	254	if (flags & SPI_XFER_BEGIN)
19126998	255	spi_cs_activate(dev);
1465d055 JT	256
	257	while (rx_len > 0) {
	258	/* Write the data into TX FIFO - tx threshold is fifo_depth */
	259	tx_tvl = 0;
b1c82da2	260	while ((tx_tvl < priv->fifo_depth) && tx_len) {
1465d055 JT	261	if (tx_buf)
	262	buf = *tx_buf++;
	263	else
	264	buf = 0;
b1c82da2	265	writel(buf, &regs->txdr);
1465d055 JT	266	tx_len--;
	267	tx_tvl++;
	268	}
	269
	270	/* Check TX FIFO completion */
	271	ts = get_timer(0);
b1c82da2	272	status = readl(&regs->isr);
1465d055	273	while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
f44bd3bc	274	if (get_timer(ts) > ZYNQ_SPI_WAIT) {
1465d055 JT	275	printf("spi_xfer: Timeout! TX FIFO not full\n");
	276	return -1;
	277	}
b1c82da2	278	status = readl(&regs->isr);
1465d055 JT	279	}
	280
	281	/* Read the data from RX FIFO */
b1c82da2	282	status = readl(&regs->isr);
d2998286	283	while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
b1c82da2	284	buf = readl(&regs->rxdr);
1465d055 JT	285	if (rx_buf)
1465d055 JT	286	*rx_buf++ = buf;
b1c82da2	287	status = readl(&regs->isr);
1465d055 JT	288	rx_len--;
	289	}
	290	}
	291
	292	if (flags & SPI_XFER_END)
b1c82da2 JT	293	spi_cs_deactivate(dev);
	294
	295	return 0;
	296	}
	297
	298	static int zynq_spi_set_speed(struct udevice *bus, uint speed)
	299	{
0fd3d911	300	struct zynq_spi_plat *plat = dev_get_plat(bus);
b1c82da2 JT	301	struct zynq_spi_priv *priv = dev_get_priv(bus);
	302	struct zynq_spi_regs *regs = priv->regs;
	303	uint32_t confr;
	304	u8 baud_rate_val = 0;
	305
	306	if (speed > plat->frequency)
	307	speed = plat->frequency;
	308
	309	/* Set the clock frequency */
	310	confr = readl(&regs->cr);
	311	if (speed == 0) {
	312	/* Set baudrate x8, if the freq is 0 */
	313	baud_rate_val = 0x2;
	314	} else if (plat->speed_hz != speed) {
46ab8a6a	315	while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
b1c82da2 JT	316	((plat->frequency /
	317	(2 << baud_rate_val)) > speed))
	318	baud_rate_val++;
	319	plat->speed_hz = speed / (2 << baud_rate_val);
	320	}
dda6241a	321	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
46ab8a6a	322	confr \|= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
b1c82da2 JT	323
	324	writel(confr, &regs->cr);
	325	priv->freq = speed;
	326
a22bba81 JT	327	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
a22bba81 JT	328	priv->regs, priv->freq);
b1c82da2 JT	329
	330	return 0;
	331	}
	332
	333	static int zynq_spi_set_mode(struct udevice *bus, uint mode)
	334	{
	335	struct zynq_spi_priv *priv = dev_get_priv(bus);
	336	struct zynq_spi_regs *regs = priv->regs;
	337	uint32_t confr;
	338
	339	/* Set the SPI Clock phase and polarities */
	340	confr = readl(&regs->cr);
	341	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK \| ZYNQ_SPI_CR_CPOL_MASK);
	342
a22bba81	343	if (mode & SPI_CPHA)
b1c82da2	344	confr \|= ZYNQ_SPI_CR_CPHA_MASK;
a22bba81	345	if (mode & SPI_CPOL)
b1c82da2 JT	346	confr \|= ZYNQ_SPI_CR_CPOL_MASK;
	347
	348	writel(confr, &regs->cr);
	349	priv->mode = mode;
	350
	351	debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
1465d055 JT	352
	353	return 0;
	354	}
b1c82da2 JT	355
	356	static const struct dm_spi_ops zynq_spi_ops = {
	357	.claim_bus = zynq_spi_claim_bus,
	358	.release_bus = zynq_spi_release_bus,
	359	.xfer = zynq_spi_xfer,
	360	.set_speed = zynq_spi_set_speed,
	361	.set_mode = zynq_spi_set_mode,
	362	};
	363
	364	static const struct udevice_id zynq_spi_ids[] = {
40b383fa	365	{ .compatible = "xlnx,zynq-spi-r1p6" },
23ef5aea	366	{ .compatible = "cdns,spi-r1p6" },
b1c82da2 JT	367	{ }
	368	};
	369
	370	U_BOOT_DRIVER(zynq_spi) = {
	371	.name = "zynq_spi",
	372	.id = UCLASS_SPI,
	373	.of_match = zynq_spi_ids,
	374	.ops = &zynq_spi_ops,
d1998a9f	375	.of_to_plat = zynq_spi_of_to_plat,
8a8d24bd	376	.plat_auto = sizeof(struct zynq_spi_plat),
41575d8e	377	.priv_auto = sizeof(struct zynq_spi_priv),
b1c82da2 JT	378	.probe = zynq_spi_probe,
b1c82da2 JT	379	};