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057b6139 SG |
1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* | |
3 | * Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net> | |
4 | * | |
5 | * Based on arch/arm/cpu/armv7/u8500/timer.c: | |
6 | * Copyright (C) 2010 Linaro Limited | |
7 | * John Rigby <john.rigby@linaro.org> | |
8 | * | |
9 | * Based on Linux kernel source and internal ST-Ericsson U-Boot source: | |
10 | * Copyright (C) 2009 Alessandro Rubini | |
11 | * Copyright (C) 2010 ST-Ericsson | |
12 | * Copyright (C) 2010 Linus Walleij for ST-Ericsson | |
13 | */ | |
14 | ||
d678a59d | 15 | #include <common.h> |
057b6139 SG |
16 | #include <dm.h> |
17 | #include <timer.h> | |
18 | #include <asm/io.h> | |
cd93d625 | 19 | #include <linux/bitops.h> |
057b6139 SG |
20 | |
21 | #define MTU_NUM_TIMERS 4 | |
22 | ||
23 | /* The timers */ | |
24 | struct nomadik_mtu_timer_regs { | |
25 | u32 lr; /* Load register */ | |
26 | u32 cv; /* Current value */ | |
27 | u32 cr; /* Control register */ | |
28 | u32 bglr; /* Background load register */ | |
29 | }; | |
30 | ||
31 | /* The MTU that contains the timers */ | |
32 | struct nomadik_mtu_regs { | |
33 | u32 imsc; /* Interrupt mask set/clear */ | |
34 | u32 ris; /* Raw interrupt status */ | |
35 | u32 mis; /* Masked interrupt status */ | |
36 | u32 icr; /* Interrupt clear register */ | |
37 | ||
38 | struct nomadik_mtu_timer_regs timers[MTU_NUM_TIMERS]; | |
39 | }; | |
40 | ||
41 | /* Bits for the control register */ | |
42 | #define MTU_CR_ONESHOT BIT(0) /* if 0 = wraps reloading from BGLR */ | |
43 | #define MTU_CR_32BITS BIT(1) /* if 0 = 16-bit counter */ | |
44 | ||
45 | #define MTU_CR_PRESCALE_SHIFT 2 | |
46 | #define MTU_CR_PRESCALE_1 (0 << MTU_CR_PRESCALE_SHIFT) | |
47 | #define MTU_CR_PRESCALE_16 (1 << MTU_CR_PRESCALE_SHIFT) | |
48 | #define MTU_CR_PRESCALE_256 (2 << MTU_CR_PRESCALE_SHIFT) | |
49 | ||
50 | #define MTU_CR_PERIODIC BIT(6) /* if 0 = free-running */ | |
51 | #define MTU_CR_ENABLE BIT(7) | |
52 | ||
53 | struct nomadik_mtu_priv { | |
54 | struct nomadik_mtu_timer_regs *timer; | |
55 | }; | |
56 | ||
8af7bb91 | 57 | static u64 nomadik_mtu_get_count(struct udevice *dev) |
057b6139 SG |
58 | { |
59 | struct nomadik_mtu_priv *priv = dev_get_priv(dev); | |
60 | ||
61 | /* Decrementing counter: invert the value */ | |
8af7bb91 | 62 | return timer_conv_64(~readl(&priv->timer->cv)); |
057b6139 SG |
63 | } |
64 | ||
65 | static int nomadik_mtu_probe(struct udevice *dev) | |
66 | { | |
67 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); | |
68 | struct nomadik_mtu_priv *priv = dev_get_priv(dev); | |
69 | struct nomadik_mtu_regs *mtu; | |
057b6139 SG |
70 | u32 prescale; |
71 | ||
0e6956cc SG |
72 | mtu = dev_read_addr_ptr(dev); |
73 | if (!mtu) | |
057b6139 | 74 | return -EINVAL; |
057b6139 SG |
75 | priv->timer = mtu->timers; /* Use first timer */ |
76 | ||
77 | if (!uc_priv->clock_rate) | |
78 | return -EINVAL; | |
79 | ||
80 | /* Use divide-by-16 counter if tick rate is more than 32 MHz */ | |
81 | if (uc_priv->clock_rate > 32000000) { | |
82 | uc_priv->clock_rate /= 16; | |
83 | prescale = MTU_CR_PRESCALE_16; | |
84 | } else { | |
85 | prescale = MTU_CR_PRESCALE_1; | |
86 | } | |
87 | ||
88 | /* Configure a free-running, auto-wrap counter with selected prescale */ | |
89 | writel(MTU_CR_ENABLE | prescale | MTU_CR_32BITS, &priv->timer->cr); | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
94 | static const struct timer_ops nomadik_mtu_ops = { | |
95 | .get_count = nomadik_mtu_get_count, | |
96 | }; | |
97 | ||
98 | static const struct udevice_id nomadik_mtu_ids[] = { | |
99 | { .compatible = "st,nomadik-mtu" }, | |
100 | {} | |
101 | }; | |
102 | ||
103 | U_BOOT_DRIVER(nomadik_mtu) = { | |
104 | .name = "nomadik_mtu", | |
105 | .id = UCLASS_TIMER, | |
106 | .of_match = nomadik_mtu_ids, | |
41575d8e | 107 | .priv_auto = sizeof(struct nomadik_mtu_priv), |
057b6139 SG |
108 | .probe = nomadik_mtu_probe, |
109 | .ops = &nomadik_mtu_ops, | |
110 | }; |