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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / timer / rockchip_timer.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
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2/*
3 * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
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4 */
5
d678a59d 6#include <common.h>
52f24238 7#include <bootstage.h>
1168d2dd 8#include <dm.h>
691d719d 9#include <init.h>
f7ae49fc 10#include <log.h>
401d1c4f 11#include <asm/global_data.h>
cc7ce94e 12#include <dm/ofnode.h>
1168d2dd 13#include <mapmem.h>
15f09a1a 14#include <asm/arch-rockchip/timer.h>
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15#include <dt-structs.h>
16#include <timer.h>
17#include <asm/io.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#if CONFIG_IS_ENABLED(OF_PLATDATA)
22struct rockchip_timer_plat {
791c7ac7 23 struct dtd_rockchip_rk3288_timer dtd;
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24};
25#endif
26
27/* Driver private data. Contains timer id. Could be either 0 or 1. */
28struct rockchip_timer_priv {
29 struct rk_timer *timer;
30};
31
cc7ce94e 32static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
1168d2dd 33{
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34 uint64_t timebase_h, timebase_l;
35 uint64_t cntr;
36
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37 timebase_l = readl(&timer->timer_curr_value0);
38 timebase_h = readl(&timer->timer_curr_value1);
1168d2dd 39
1168d2dd 40 cntr = timebase_h << 32 | timebase_l;
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41 return cntr;
42}
43
44#if CONFIG_IS_ENABLED(BOOTSTAGE)
45ulong timer_get_boot_us(void)
46{
47 uint64_t ticks = 0;
48 uint32_t rate;
49 uint64_t us;
50 int ret;
51
52 ret = dm_timer_init();
53
54 if (!ret) {
55 /* The timer is available */
56 rate = timer_get_rate(gd->timer);
57 timer_get_count(gd->timer, &ticks);
dcfc42b1 58 } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
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59 /* We have been called so early that the DM is not ready,... */
60 ofnode node = offset_to_ofnode(-1);
61 struct rk_timer *timer = NULL;
62
63 /*
64 * ... so we try to access the raw timer, if it is specified
65 * via the tick-timer property in /chosen.
66 */
67 node = ofnode_get_chosen_node("tick-timer");
68 if (!ofnode_valid(node)) {
69 debug("%s: no /chosen/tick-timer\n", __func__);
70 return 0;
71 }
72
73 timer = (struct rk_timer *)ofnode_get_addr(node);
74
75 /* This timer is down-counting */
76 ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
77 if (ofnode_read_u32(node, "clock-frequency", &rate)) {
78 debug("%s: could not read clock-frequency\n", __func__);
79 return 0;
80 }
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81 } else {
82 return 0;
83 }
84
85 us = (ticks * 1000) / rate;
86 return us;
87}
88#endif
89
8af7bb91 90static u64 rockchip_timer_get_count(struct udevice *dev)
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91{
92 struct rockchip_timer_priv *priv = dev_get_priv(dev);
93 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
94
95 /* timers are down-counting */
8af7bb91 96 return ~0ull - cntr;
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97}
98
d1998a9f 99static int rockchip_clk_of_to_plat(struct udevice *dev)
1168d2dd 100{
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101 if (CONFIG_IS_ENABLED(OF_REAL)) {
102 struct rockchip_timer_priv *priv = dev_get_priv(dev);
1168d2dd 103
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104 priv->timer = dev_read_addr_ptr(dev);
105 if (!priv->timer)
106 return -ENOENT;
107 }
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108
109 return 0;
110}
111
112static int rockchip_timer_start(struct udevice *dev)
113{
114 struct rockchip_timer_priv *priv = dev_get_priv(dev);
115 const uint64_t reload_val = ~0uLL;
116 const uint32_t reload_val_l = reload_val & 0xffffffff;
117 const uint32_t reload_val_h = reload_val >> 32;
118
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119 /* don't reinit, if the timer is already running and set up */
120 if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
121 (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
122 (readl(&priv->timer->timer_load_count1) == reload_val_h))
123 return 0;
124
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125 /* disable timer and reset all control */
126 writel(0, &priv->timer->timer_ctrl_reg);
127 /* write reload value */
128 writel(reload_val_l, &priv->timer->timer_load_count0);
129 writel(reload_val_h, &priv->timer->timer_load_count1);
130 /* enable timer */
131 writel(1, &priv->timer->timer_ctrl_reg);
132
133 return 0;
134}
135
136static int rockchip_timer_probe(struct udevice *dev)
137{
138#if CONFIG_IS_ENABLED(OF_PLATDATA)
139 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
140 struct rockchip_timer_priv *priv = dev_get_priv(dev);
c69cda25 141 struct rockchip_timer_plat *plat = dev_get_plat(dev);
1168d2dd 142
8158a848 143 priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
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144 uc_priv->clock_rate = plat->dtd.clock_frequency;
145#endif
146
147 return rockchip_timer_start(dev);
148}
149
150static const struct timer_ops rockchip_timer_ops = {
151 .get_count = rockchip_timer_get_count,
152};
153
154static const struct udevice_id rockchip_timer_ids[] = {
e0e1d3f9 155 { .compatible = "rockchip,rk3288-timer" },
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156 {}
157};
158
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159U_BOOT_DRIVER(rockchip_rk3288_timer) = {
160 .name = "rockchip_rk3288_timer",
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161 .id = UCLASS_TIMER,
162 .of_match = rockchip_timer_ids,
163 .probe = rockchip_timer_probe,
164 .ops = &rockchip_timer_ops,
41575d8e 165 .priv_auto = sizeof(struct rockchip_timer_priv),
1168d2dd 166#if CONFIG_IS_ENABLED(OF_PLATDATA)
caa4daa2 167 .plat_auto = sizeof(struct rockchip_timer_plat),
1168d2dd 168#endif
d1998a9f 169 .of_to_plat = rockchip_clk_of_to_plat,
1168d2dd 170};