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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / ufs / ufs.h
CommitLineData
7feafb0a
FA		 1/* SPDX-License-Identifier: GPL-2.0+ */
2#ifndef __UFS_H
3#define __UFS_H
4
7feafb0a
FA		 5#include "unipro.h"
6
98eb4ce5
SG		 7struct udevice;
8
7feafb0a
FA		 9#define UFS_CDB_SIZE 16
10#define UPIU_TRANSACTION_UIC_CMD 0x1F
11#define UIC_CMD_SIZE (sizeof(u32) * 4)
12#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
13#define UFS_MAX_LUNS 0x7F
14
15enum {
16 TASK_REQ_UPIU_SIZE_DWORDS = 8,
17 TASK_RSP_UPIU_SIZE_DWORDS = 8,
18 ALIGNED_UPIU_SIZE = 512,
19};
20
21/* UFS device power modes */
22enum ufs_dev_pwr_mode {
23 UFS_ACTIVE_PWR_MODE = 1,
24 UFS_SLEEP_PWR_MODE = 2,
25 UFS_POWERDOWN_PWR_MODE = 3,
26};
27
28enum ufs_notify_change_status {
29 PRE_CHANGE,
30 POST_CHANGE,
31};
32
33struct ufs_pa_layer_attr {
34 u32 gear_rx;
35 u32 gear_tx;
36 u32 lane_rx;
37 u32 lane_tx;
38 u32 pwr_rx;
39 u32 pwr_tx;
40 u32 hs_rate;
41};
42
43struct ufs_pwr_mode_info {
44 bool is_valid;
45 struct ufs_pa_layer_attr info;
46};
47
48enum ufs_desc_def_size {
49 QUERY_DESC_DEVICE_DEF_SIZE = 0x40,
50 QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90,
51 QUERY_DESC_UNIT_DEF_SIZE = 0x23,
52 QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06,
53 QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48,
54 QUERY_DESC_POWER_DEF_SIZE = 0x62,
55 QUERY_DESC_HEALTH_DEF_SIZE = 0x25,
56};
57
58struct ufs_desc_size {
59 int dev_desc;
60 int pwr_desc;
61 int geom_desc;
62 int interc_desc;
63 int unit_desc;
64 int conf_desc;
65 int hlth_desc;
66};
67
68/*
69 * Request Descriptor Definitions
70 */
71
72/* Transfer request command type */
73enum {
74 UTP_CMD_TYPE_SCSI = 0x0,
75 UTP_CMD_TYPE_UFS = 0x1,
76 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
77};
78
79/* UTP Transfer Request Command Offset */
80#define UPIU_COMMAND_TYPE_OFFSET 28
81
82/* Offset of the response code in the UPIU header */
83#define UPIU_RSP_CODE_OFFSET 8
84
85/* To accommodate UFS2.0 required Command type */
86enum {
87 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
88};
89
90enum {
91 UTP_SCSI_COMMAND = 0x00000000,
92 UTP_NATIVE_UFS_COMMAND = 0x10000000,
93 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
94 UTP_REQ_DESC_INT_CMD = 0x01000000,
95};
96
97/* UTP Transfer Request Data Direction (DD) */
98enum {
99 UTP_NO_DATA_TRANSFER = 0x00000000,
100 UTP_HOST_TO_DEVICE = 0x02000000,
101 UTP_DEVICE_TO_HOST = 0x04000000,
102};
103
104/* Overall command status values */
105enum {
106 OCS_SUCCESS = 0x0,
107 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
108 OCS_INVALID_PRDT_ATTR = 0x2,
109 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
110 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
111 OCS_PEER_COMM_FAILURE = 0x5,
112 OCS_ABORTED = 0x6,
113 OCS_FATAL_ERROR = 0x7,
114 OCS_INVALID_COMMAND_STATUS = 0x0F,
115 MASK_OCS = 0x0F,
116};
117
118/* The maximum length of the data byte count field in the PRDT is 256KB */
119#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
120/* The granularity of the data byte count field in the PRDT is 32-bit */
121#define PRDT_DATA_BYTE_COUNT_PAD 4
122
123#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
124#define QUERY_DESC_MAX_SIZE 255
125#define QUERY_DESC_MIN_SIZE 2
126#define QUERY_DESC_HDR_SIZE 2
127#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
128 (sizeof(struct utp_upiu_header)))
129#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
130#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
131 cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
132 (byte1 << 8) | (byte0))
133/*
134 * UFS Protocol Information Unit related definitions
135 */
136
137/* Task management functions */
138enum {
139 UFS_ABORT_TASK = 0x01,
140 UFS_ABORT_TASK_SET = 0x02,
141 UFS_CLEAR_TASK_SET = 0x04,
142 UFS_LOGICAL_RESET = 0x08,
143 UFS_QUERY_TASK = 0x80,
144 UFS_QUERY_TASK_SET = 0x81,
145};
146
147/* UTP UPIU Transaction Codes Initiator to Target */
148enum {
149 UPIU_TRANSACTION_NOP_OUT = 0x00,
150 UPIU_TRANSACTION_COMMAND = 0x01,
151 UPIU_TRANSACTION_DATA_OUT = 0x02,
152 UPIU_TRANSACTION_TASK_REQ = 0x04,
153 UPIU_TRANSACTION_QUERY_REQ = 0x16,
154};
155
156/* UTP UPIU Transaction Codes Target to Initiator */
157enum {
158 UPIU_TRANSACTION_NOP_IN = 0x20,
159 UPIU_TRANSACTION_RESPONSE = 0x21,
160 UPIU_TRANSACTION_DATA_IN = 0x22,
161 UPIU_TRANSACTION_TASK_RSP = 0x24,
162 UPIU_TRANSACTION_READY_XFER = 0x31,
163 UPIU_TRANSACTION_QUERY_RSP = 0x36,
164 UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
165};
166
167/* UPIU Read/Write flags */
168enum {
169 UPIU_CMD_FLAGS_NONE = 0x00,
170 UPIU_CMD_FLAGS_WRITE = 0x20,
171 UPIU_CMD_FLAGS_READ = 0x40,
172};
173
174/* UPIU Task Attributes */
175enum {
176 UPIU_TASK_ATTR_SIMPLE = 0x00,
177 UPIU_TASK_ATTR_ORDERED = 0x01,
178 UPIU_TASK_ATTR_HEADQ = 0x02,
179 UPIU_TASK_ATTR_ACA = 0x03,
180};
181
182/* UPIU Query request function */
183enum {
184 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
185 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
186};
187
188/* Offset of the response code in the UPIU header */
189#define UPIU_RSP_CODE_OFFSET 8
190
191enum {
192 MASK_SCSI_STATUS = 0xFF,
193 MASK_TASK_RESPONSE = 0xFF00,
194 MASK_RSP_UPIU_RESULT = 0xFFFF,
195 MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
196 MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
197 MASK_RSP_EXCEPTION_EVENT = 0x10000,
198 MASK_TM_SERVICE_RESP = 0xFF,
199 MASK_TM_FUNC = 0xFF,
200};
201
202/* UTP QUERY Transaction Specific Fields OpCode */
203enum query_opcode {
204 UPIU_QUERY_OPCODE_NOP = 0x0,
205 UPIU_QUERY_OPCODE_READ_DESC = 0x1,
206 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
207 UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
208 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
209 UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
210 UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
211 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
212 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
213};
214
215/* Query response result code */
216enum {
217 QUERY_RESULT_SUCCESS = 0x00,
218 QUERY_RESULT_NOT_READABLE = 0xF6,
219 QUERY_RESULT_NOT_WRITEABLE = 0xF7,
220 QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
221 QUERY_RESULT_INVALID_LENGTH = 0xF9,
222 QUERY_RESULT_INVALID_VALUE = 0xFA,
223 QUERY_RESULT_INVALID_SELECTOR = 0xFB,
224 QUERY_RESULT_INVALID_INDEX = 0xFC,
225 QUERY_RESULT_INVALID_IDN = 0xFD,
226 QUERY_RESULT_INVALID_OPCODE = 0xFE,
227 QUERY_RESULT_GENERAL_FAILURE = 0xFF,
228};
229
230enum {
231 UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
232 UPIU_COMMAND_SET_TYPE_UFS = 0x1,
233 UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
234};
235
236/* Flag idn for Query Requests*/
237enum flag_idn {
238 QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
239 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
240 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
241 QUERY_FLAG_IDN_BKOPS_EN = 0x04,
242 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
243 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
244 QUERY_FLAG_IDN_RESERVED2 = 0x07,
245 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
246 QUERY_FLAG_IDN_BUSY_RTC = 0x09,
247 QUERY_FLAG_IDN_RESERVED3 = 0x0A,
248 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
249};
250
251/* Attribute idn for Query requests */
252enum attr_idn {
253 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
254 QUERY_ATTR_IDN_RESERVED = 0x01,
255 QUERY_ATTR_IDN_POWER_MODE = 0x02,
256 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
257 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
258 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
259 QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
260 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
261 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
262 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
263 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
264 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
265 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
266 QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
267 QUERY_ATTR_IDN_EE_STATUS = 0x0E,
268 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
269 QUERY_ATTR_IDN_CNTX_CONF = 0x10,
270 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
271 QUERY_ATTR_IDN_RESERVED2 = 0x12,
272 QUERY_ATTR_IDN_RESERVED3 = 0x13,
273 QUERY_ATTR_IDN_FFU_STATUS = 0x14,
274 QUERY_ATTR_IDN_PSA_STATE = 0x15,
275 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
276};
277
278/* Descriptor idn for Query requests */
279enum desc_idn {
280 QUERY_DESC_IDN_DEVICE = 0x0,
281 QUERY_DESC_IDN_CONFIGURATION = 0x1,
282 QUERY_DESC_IDN_UNIT = 0x2,
283 QUERY_DESC_IDN_RFU_0 = 0x3,
284 QUERY_DESC_IDN_INTERCONNECT = 0x4,
285 QUERY_DESC_IDN_STRING = 0x5,
286 QUERY_DESC_IDN_RFU_1 = 0x6,
287 QUERY_DESC_IDN_GEOMETRY = 0x7,
288 QUERY_DESC_IDN_POWER = 0x8,
289 QUERY_DESC_IDN_HEALTH = 0x9,
290 QUERY_DESC_IDN_MAX,
291};
292
293enum desc_header_offset {
294 QUERY_DESC_LENGTH_OFFSET = 0x00,
295 QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
296};
297
298struct ufshcd_sg_entry {
299 __le32 base_addr;
300 __le32 upper_addr;
301 __le32 reserved;
302 __le32 size;
303};
304
305#define MAX_BUFF 128
306/**
307 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
308 * @command_upiu: Command UPIU Frame address
309 * @response_upiu: Response UPIU Frame address
310 * @prd_table: Physical Region Descriptor
311 */
312struct utp_transfer_cmd_desc {
313 u8 command_upiu[ALIGNED_UPIU_SIZE];
314 u8 response_upiu[ALIGNED_UPIU_SIZE];
315 struct ufshcd_sg_entry prd_table[MAX_BUFF];
316};
317
318/**
319 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
320 * @dword0: Descriptor Header DW0
321 * @dword1: Descriptor Header DW1
322 * @dword2: Descriptor Header DW2
323 * @dword3: Descriptor Header DW3
324 */
325struct request_desc_header {
326 __le32 dword_0;
327 __le32 dword_1;
328 __le32 dword_2;
329 __le32 dword_3;
330};
331
332/**
333 * struct utp_transfer_req_desc - UTRD structure
334 * @header: UTRD header DW-0 to DW-3
335 * @command_desc_base_addr_lo: UCD base address low DW-4
336 * @command_desc_base_addr_hi: UCD base address high DW-5
337 * @response_upiu_length: response UPIU length DW-6
338 * @response_upiu_offset: response UPIU offset DW-6
339 * @prd_table_length: Physical region descriptor length DW-7
340 * @prd_table_offset: Physical region descriptor offset DW-7
341 */
342struct utp_transfer_req_desc {
343 /* DW 0-3 */
344 struct request_desc_header header;
345
346 /* DW 4-5*/
347 __le32 command_desc_base_addr_lo;
348 __le32 command_desc_base_addr_hi;
349
350 /* DW 6 */
351 __le16 response_upiu_length;
352 __le16 response_upiu_offset;
353
354 /* DW 7 */
355 __le16 prd_table_length;
356 __le16 prd_table_offset;
357};
358
359/**
360 * struct utp_upiu_header - UPIU header structure
361 * @dword_0: UPIU header DW-0
362 * @dword_1: UPIU header DW-1
363 * @dword_2: UPIU header DW-2
364 */
365struct utp_upiu_header {
366 __be32 dword_0;
367 __be32 dword_1;
368 __be32 dword_2;
369};
370
371/**
372 * struct utp_upiu_query - upiu request buffer structure for
373 * query request.
374 * @opcode: command to perform B-0
375 * @idn: a value that indicates the particular type of data B-1
376 * @index: Index to further identify data B-2
377 * @selector: Index to further identify data B-3
378 * @reserved_osf: spec reserved field B-4,5
379 * @length: number of descriptor bytes to read/write B-6,7
380 * @value: Attribute value to be written DW-5
381 * @reserved: spec reserved DW-6,7
382 */
383struct utp_upiu_query {
384 __u8 opcode;
385 __u8 idn;
386 __u8 index;
387 __u8 selector;
388 __be16 reserved_osf;
389 __be16 length;
390 __be32 value;
391 __be32 reserved[2];
392};
393
394/**
395 * struct utp_upiu_cmd - Command UPIU structure
396 * @data_transfer_len: Data Transfer Length DW-3
397 * @cdb: Command Descriptor Block CDB DW-4 to DW-7
398 */
399struct utp_upiu_cmd {
400 __be32 exp_data_transfer_len;
401 u8 cdb[UFS_CDB_SIZE];
402};
403
404/*
405 * UTMRD structure.
406 */
407struct utp_task_req_desc {
408 /* DW 0-3 */
409 struct request_desc_header header;
410
411 /* DW 4-11 - Task request UPIU structure */
412 struct utp_upiu_header req_header;
413 __be32 input_param1;
414 __be32 input_param2;
415 __be32 input_param3;
416 __be32 __reserved1[2];
417
418 /* DW 12-19 - Task Management Response UPIU structure */
419 struct utp_upiu_header rsp_header;
420 __be32 output_param1;
421 __be32 output_param2;
422 __be32 __reserved2[3];
423};
424
425/**
426 * struct utp_upiu_req - general upiu request structure
427 * @header:UPIU header structure DW-0 to DW-2
428 * @sc: fields structure for scsi command DW-3 to DW-7
429 * @qr: fields structure for query request DW-3 to DW-7
430 */
431struct utp_upiu_req {
432 struct utp_upiu_header header;
433 union {
434 struct utp_upiu_cmd sc;
435 struct utp_upiu_query qr;
436 struct utp_upiu_query tr;
437 /* use utp_upiu_query to host the 4 dwords of uic command */
438 struct utp_upiu_query uc;
439 };
440};
441
442/**
443 * struct utp_cmd_rsp - Response UPIU structure
444 * @residual_transfer_count: Residual transfer count DW-3
445 * @reserved: Reserved double words DW-4 to DW-7
446 * @sense_data_len: Sense data length DW-8 U16
447 * @sense_data: Sense data field DW-8 to DW-12
448 */
449struct utp_cmd_rsp {
450 __be32 residual_transfer_count;
451 __be32 reserved[4];
452 __be16 sense_data_len;
453 u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH];
454};
455
456/**
457 * struct utp_upiu_rsp - general upiu response structure
458 * @header: UPIU header structure DW-0 to DW-2
459 * @sr: fields structure for scsi command DW-3 to DW-12
460 * @qr: fields structure for query request DW-3 to DW-7
461 */
462struct utp_upiu_rsp {
463 struct utp_upiu_header header;
464 union {
465 struct utp_cmd_rsp sr;
466 struct utp_upiu_query qr;
467 };
468};
469
470#define MAX_MODEL_LEN 16
471/**
472 * ufs_dev_desc - ufs device details from the device descriptor
473 *
474 * @wmanufacturerid: card details
475 * @model: card model
476 */
477struct ufs_dev_desc {
478 u16 wmanufacturerid;
479 char model[MAX_MODEL_LEN + 1];
480};
481
482/* Device descriptor parameters offsets in bytes*/
483enum device_desc_param {
484 DEVICE_DESC_PARAM_LEN = 0x0,
485 DEVICE_DESC_PARAM_TYPE = 0x1,
486 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
487 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
488 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
489 DEVICE_DESC_PARAM_PRTCL = 0x5,
490 DEVICE_DESC_PARAM_NUM_LU = 0x6,
491 DEVICE_DESC_PARAM_NUM_WLU = 0x7,
492 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
493 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
494 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
495 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
496 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
497 DEVICE_DESC_PARAM_SEC_LU = 0xD,
498 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
499 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
500 DEVICE_DESC_PARAM_SPEC_VER = 0x10,
501 DEVICE_DESC_PARAM_MANF_DATE = 0x12,
502 DEVICE_DESC_PARAM_MANF_NAME = 0x14,
503 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
504 DEVICE_DESC_PARAM_SN = 0x16,
505 DEVICE_DESC_PARAM_OEM_ID = 0x17,
506 DEVICE_DESC_PARAM_MANF_ID = 0x18,
507 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
508 DEVICE_DESC_PARAM_UD_LEN = 0x1B,
509 DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
510 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
511 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
512 DEVICE_DESC_PARAM_FFU_TMT = 0x20,
513 DEVICE_DESC_PARAM_Q_DPTH = 0x21,
514 DEVICE_DESC_PARAM_DEV_VER = 0x22,
515 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
516 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
517 DEVICE_DESC_PARAM_PSA_TMT = 0x29,
518 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
519};
520
521struct ufs_hba;
522
523enum {
524 UFSHCD_MAX_CHANNEL = 0,
525 UFSHCD_MAX_ID = 1,
526};
527
528enum dev_cmd_type {
529 DEV_CMD_TYPE_NOP = 0x0,
530 DEV_CMD_TYPE_QUERY = 0x1,
531};
532
533/**
534 * struct uic_command - UIC command structure
535 * @command: UIC command
536 * @argument1: UIC command argument 1
537 * @argument2: UIC command argument 2
538 * @argument3: UIC command argument 3
539 * @cmd_active: Indicate if UIC command is outstanding
540 * @result: UIC command result
541 * @done: UIC command completion
542 */
543struct uic_command {
544 u32 command;
545 u32 argument1;
546 u32 argument2;
547 u32 argument3;
548 int cmd_active;
549 int result;
550};
551
552/* GenSelectorIndex calculation macros for M-PHY attributes */
553#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
554#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
555
556#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
557 ((sel) & 0xFFFF))
558#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
559#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
560#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
561
562/* Link Status*/
563enum link_status {
564 UFSHCD_LINK_IS_DOWN = 1,
565 UFSHCD_LINK_IS_UP = 2,
566};
567
568#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
569 ((sel) & 0xFFFF))
570#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
571#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
572#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
573
574/* UIC Commands */
575enum uic_cmd_dme {
576 UIC_CMD_DME_GET = 0x01,
577 UIC_CMD_DME_SET = 0x02,
578 UIC_CMD_DME_PEER_GET = 0x03,
579 UIC_CMD_DME_PEER_SET = 0x04,
580 UIC_CMD_DME_POWERON = 0x10,
581 UIC_CMD_DME_POWEROFF = 0x11,
582 UIC_CMD_DME_ENABLE = 0x12,
583 UIC_CMD_DME_RESET = 0x14,
584 UIC_CMD_DME_END_PT_RST = 0x15,
585 UIC_CMD_DME_LINK_STARTUP = 0x16,
586 UIC_CMD_DME_HIBER_ENTER = 0x17,
587 UIC_CMD_DME_HIBER_EXIT = 0x18,
588 UIC_CMD_DME_TEST_MODE = 0x1A,
589};
590
591/* UIC Config result code / Generic error code */
592enum {
593 UIC_CMD_RESULT_SUCCESS = 0x00,
594 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
595 UIC_CMD_RESULT_FAILURE = 0x01,
596 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
597 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
598 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
599 UIC_CMD_RESULT_BAD_INDEX = 0x05,
600 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
601 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
602 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
603 UIC_CMD_RESULT_BUSY = 0x09,
604 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
605};
606
607#define MASK_UIC_COMMAND_RESULT 0xFF
608
609/* Host <-> Device UniPro Link state */
610enum uic_link_state {
611 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
612 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
613 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
614};
615
616/* UIC command interfaces for DME primitives */
617#define DME_LOCAL 0
618#define DME_PEER 1
619#define ATTR_SET_NOR 0 /* NORMAL */
620#define ATTR_SET_ST 1 /* STATIC */
621
622int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
623 u8 attr_set, u32 mib_val, u8 peer);
624int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
625 u32 *mib_val, u8 peer);
626
627static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
628 u32 mib_val)
629{
630 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
631 mib_val, DME_LOCAL);
632}
633
634static inline int ufshcd_dme_get(struct ufs_hba *hba,
635 u32 attr_sel, u32 *mib_val)
636{
637 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
638}
639
640static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
641 u32 attr_sel, u32 *mib_val)
642{
643 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
644}
645
646static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
647 u32 mib_val)
648{
649 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
650 mib_val, DME_PEER);
651}
652
653/**
654 * struct ufs_query_req - parameters for building a query request
655 * @query_func: UPIU header query function
656 * @upiu_req: the query request data
657 */
658struct ufs_query_req {
659 u8 query_func;
660 struct utp_upiu_query upiu_req;
661};
662
663/**
664 * struct ufs_query_resp - UPIU QUERY
665 * @response: device response code
666 * @upiu_res: query response data
667 */
668struct ufs_query_res {
669 u8 response;
670 struct utp_upiu_query upiu_res;
671};
672
673/**
674 * struct ufs_query - holds relevant data structures for query request
675 * @request: request upiu and function
676 * @descriptor: buffer for sending/receiving descriptor
677 * @response: response upiu and response
678 */
679struct ufs_query {
680 struct ufs_query_req request;
681 u8 *descriptor;
682 struct ufs_query_res response;
683};
684
685/**
686 * struct ufs_dev_cmd - all assosiated fields with device management commands
687 * @type: device management command type - Query, NOP OUT
688 * @tag_wq: wait queue until free command slot is available
689 */
690struct ufs_dev_cmd {
691 enum dev_cmd_type type;
692 struct ufs_query query;
693};
694
695struct ufs_hba_ops {
696 int (*init)(struct ufs_hba *hba);
697 int (*hce_enable_notify)(struct ufs_hba *hba,
698 enum ufs_notify_change_status);
699 int (*link_startup_notify)(struct ufs_hba *hba,
700 enum ufs_notify_change_status);
701 int (*phy_initialization)(struct ufs_hba *hba);
702};
703
704struct ufs_hba {
705 struct udevice *dev;
706 void __iomem *mmio_base;
707 struct ufs_hba_ops *ops;
708 struct ufs_desc_size desc_size;
709 u32 capabilities;
710 u32 version;
711 u32 intr_mask;
712 u32 quirks;
713/*
714 * If UFS host controller is having issue in processing LCC (Line
715 * Control Command) coming from device then enable this quirk.
716 * When this quirk is enabled, host controller driver should disable
717 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
718 * attribute of device to 0).
719 */
5dab730c 720#define UFSHCD_QUIRK_BROKEN_LCC BIT(0)
7feafb0a 721
91913a1a
MV		 722/*
723 * This quirk needs to be enabled if the host controller has
724 * 64-bit addressing supported capability but it doesn't work.
725 */
726#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1)
727
f430151e
MV		 728/*
729 * This quirk needs to be enabled if the host controller has
730 * auto-hibernate capability but it's FASTAUTO only.
731 */
732#define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2)
733
7feafb0a
FA		 734 /* Virtual memory reference */
735 struct utp_transfer_cmd_desc *ucdl;
736 struct utp_transfer_req_desc *utrdl;
737 /* TODO: Add Task Manegement Support */
738 struct utp_task_req_desc *utmrdl;
739
740 struct utp_upiu_req *ucd_req_ptr;
741 struct utp_upiu_rsp *ucd_rsp_ptr;
742 struct ufshcd_sg_entry *ucd_prdt_ptr;
743
744 /* Power Mode information */
745 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
746 struct ufs_pa_layer_attr pwr_info;
747 struct ufs_pwr_mode_info max_pwr_info;
748
749 struct ufs_dev_cmd dev_cmd;
750};
751
752static inline int ufshcd_ops_init(struct ufs_hba *hba)
753{
754 if (hba->ops && hba->ops->init)
755 return hba->ops->init(hba);
756
757 return 0;
758}
759
760static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
761 bool status)
762{
763 if (hba->ops && hba->ops->hce_enable_notify)
764 return hba->ops->hce_enable_notify(hba, status);
765
766 return 0;
767}
768
769static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba,
770 bool status)
771{
772 if (hba->ops && hba->ops->link_startup_notify)
773 return hba->ops->link_startup_notify(hba, status);
774
775 return 0;
776}
777
778/* Controller UFSHCI version */
779enum {
780 UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
781 UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
782 UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
783 UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
2ff810ae 784 UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
5b2d25a2 785 UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
7feafb0a
FA		 786};
787
788/* Interrupt disable masks */
789enum {
790 /* Interrupt disable mask for UFSHCI v1.0 */
791 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
792 INTERRUPT_MASK_RW_VER_10 = 0x30000,
793
794 /* Interrupt disable mask for UFSHCI v1.1 */
795 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
796
797 /* Interrupt disable mask for UFSHCI v2.1 */
798 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
799};
800
801/* UFSHCI Registers */
802enum {
803 REG_CONTROLLER_CAPABILITIES = 0x00,
804 REG_UFS_VERSION = 0x08,
805 REG_CONTROLLER_DEV_ID = 0x10,
806 REG_CONTROLLER_PROD_ID = 0x14,
807 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
808 REG_INTERRUPT_STATUS = 0x20,
809 REG_INTERRUPT_ENABLE = 0x24,
810 REG_CONTROLLER_STATUS = 0x30,
811 REG_CONTROLLER_ENABLE = 0x34,
812 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
813 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
814 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
815 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
816 REG_UIC_ERROR_CODE_DME = 0x48,
817 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
818 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
819 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
820 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
821 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
822 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
823 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
824 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
825 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
826 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
827 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
828 REG_UIC_COMMAND = 0x90,
829 REG_UIC_COMMAND_ARG_1 = 0x94,
830 REG_UIC_COMMAND_ARG_2 = 0x98,
831 REG_UIC_COMMAND_ARG_3 = 0x9C,
832
833 UFSHCI_REG_SPACE_SIZE = 0xA0,
834
835 REG_UFS_CCAP = 0x100,
836 REG_UFS_CRYPTOCAP = 0x104,
837
838 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
839};
840
841/* Controller capability masks */
842enum {
843 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
844 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
845 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
846 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
847 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
848 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
849};
850
851/* Interrupt Status 20h */
852#define UTP_TRANSFER_REQ_COMPL 0x1
853#define UIC_DME_END_PT_RESET 0x2
854#define UIC_ERROR 0x4
855#define UIC_TEST_MODE 0x8
856#define UIC_POWER_MODE 0x10
857#define UIC_HIBERNATE_EXIT 0x20
858#define UIC_HIBERNATE_ENTER 0x40
859#define UIC_LINK_LOST 0x80
860#define UIC_LINK_STARTUP 0x100
861#define UTP_TASK_REQ_COMPL 0x200
862#define UIC_COMMAND_COMPL 0x400
863#define DEVICE_FATAL_ERROR 0x800
864#define CONTROLLER_FATAL_ERROR 0x10000
865#define SYSTEM_BUS_FATAL_ERROR 0x20000
866
867#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
868 UIC_HIBERNATE_EXIT |\
869 UIC_POWER_MODE)
870
871#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
872
873#define UFSHCD_ERROR_MASK (UIC_ERROR |\
874 DEVICE_FATAL_ERROR |\
875 CONTROLLER_FATAL_ERROR |\
876 SYSTEM_BUS_FATAL_ERROR)
877
878#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
879 CONTROLLER_FATAL_ERROR |\
880 SYSTEM_BUS_FATAL_ERROR)
881
882/* Host Controller Enable 0x34h */
883#define CONTROLLER_ENABLE 0x1
884#define CONTROLLER_DISABLE 0x0
885/* HCS - Host Controller Status 30h */
886#define DEVICE_PRESENT 0x1
887#define UTP_TRANSFER_REQ_LIST_READY 0x2
888#define UTP_TASK_REQ_LIST_READY 0x4
889#define UIC_COMMAND_READY 0x8
890#define HOST_ERROR_INDICATOR 0x10
891#define DEVICE_ERROR_INDICATOR 0x20
892#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
893
894#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
895 UTP_TASK_REQ_LIST_READY |\
896 UIC_COMMAND_READY)
897
898enum {
899 PWR_OK = 0x0,
900 PWR_LOCAL = 0x01,
901 PWR_REMOTE = 0x02,
902 PWR_BUSY = 0x03,
903 PWR_ERROR_CAP = 0x04,
904 PWR_FATAL_ERROR = 0x05,
905};
906
907/* UICCMD - UIC Command */
908#define COMMAND_OPCODE_MASK 0xFF
909#define GEN_SELECTOR_INDEX_MASK 0xFFFF
910
911#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
912#define RESET_LEVEL 0xFF
913
914#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
6e7df1d1 915#define CFG_RESULT_CODE_MASK 0xFF
7feafb0a
FA		 916#define GENERIC_ERROR_CODE_MASK 0xFF
917
918#define ufshcd_writel(hba, val, reg) \
919 writel((val), (hba)->mmio_base + (reg))
920#define ufshcd_readl(hba, reg) \
921 readl((hba)->mmio_base + (reg))
922
923/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
924#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
925
926/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
927#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
928
929int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
930
931#endif
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