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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
85d5e707 KVA |
2 | /** |
3 | * core.h - DesignWare USB3 DRD Core Header | |
4 | * | |
a94a4071 | 5 | * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com |
85d5e707 KVA |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
9 | * | |
30c31d58 KVA |
10 | * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported |
11 | * to uboot. | |
12 | * | |
13 | * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable | |
14 | * | |
85d5e707 KVA |
15 | */ |
16 | ||
17 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
18 | #define __DRIVERS_USB_DWC3_CORE_H | |
19 | ||
cd93d625 | 20 | #include <linux/bitops.h> |
85d5e707 | 21 | #include <linux/ioport.h> |
85d5e707 KVA |
22 | |
23 | #include <linux/usb/ch9.h> | |
85d5e707 | 24 | #include <linux/usb/otg.h> |
64697942 | 25 | #include <linux/usb/phy.h> |
85d5e707 | 26 | |
85d5e707 KVA |
27 | #define DWC3_MSG_MAX 500 |
28 | ||
29 | /* Global constants */ | |
30 | #define DWC3_EP0_BOUNCE_SIZE 512 | |
31 | #define DWC3_ENDPOINTS_NUM 32 | |
32 | #define DWC3_XHCI_RESOURCES_NUM 2 | |
33 | ||
34 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ | |
35 | #define DWC3_EVENT_SIZE 4 /* bytes */ | |
36 | #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ | |
37 | #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) | |
38 | #define DWC3_EVENT_TYPE_MASK 0xfe | |
39 | ||
40 | #define DWC3_EVENT_TYPE_DEV 0 | |
41 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
42 | #define DWC3_EVENT_TYPE_I2C 4 | |
43 | ||
44 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
45 | #define DWC3_DEVICE_EVENT_RESET 1 | |
46 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
47 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
48 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
49 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 | |
50 | #define DWC3_DEVICE_EVENT_EOPF 6 | |
51 | #define DWC3_DEVICE_EVENT_SOF 7 | |
52 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
53 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
54 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
55 | ||
56 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
57 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
58 | #define DWC3_GSNPSREV_MASK 0xffff | |
59 | ||
60 | /* DWC3 registers memory space boundries */ | |
61 | #define DWC3_XHCI_REGS_START 0x0 | |
62 | #define DWC3_XHCI_REGS_END 0x7fff | |
63 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
64 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
65 | #define DWC3_DEVICE_REGS_START 0xc700 | |
66 | #define DWC3_DEVICE_REGS_END 0xcbff | |
67 | #define DWC3_OTG_REGS_START 0xcc00 | |
68 | #define DWC3_OTG_REGS_END 0xccff | |
69 | ||
70 | /* Global Registers */ | |
71 | #define DWC3_GSBUSCFG0 0xc100 | |
72 | #define DWC3_GSBUSCFG1 0xc104 | |
73 | #define DWC3_GTXTHRCFG 0xc108 | |
74 | #define DWC3_GRXTHRCFG 0xc10c | |
75 | #define DWC3_GCTL 0xc110 | |
76 | #define DWC3_GEVTEN 0xc114 | |
77 | #define DWC3_GSTS 0xc118 | |
dc18413a | 78 | #define DWC3_GUCTL1 0xc11c |
85d5e707 KVA |
79 | #define DWC3_GSNPSID 0xc120 |
80 | #define DWC3_GGPIO 0xc124 | |
81 | #define DWC3_GUID 0xc128 | |
82 | #define DWC3_GUCTL 0xc12c | |
83 | #define DWC3_GBUSERRADDR0 0xc130 | |
84 | #define DWC3_GBUSERRADDR1 0xc134 | |
85 | #define DWC3_GPRTBIMAP0 0xc138 | |
86 | #define DWC3_GPRTBIMAP1 0xc13c | |
87 | #define DWC3_GHWPARAMS0 0xc140 | |
88 | #define DWC3_GHWPARAMS1 0xc144 | |
89 | #define DWC3_GHWPARAMS2 0xc148 | |
90 | #define DWC3_GHWPARAMS3 0xc14c | |
91 | #define DWC3_GHWPARAMS4 0xc150 | |
92 | #define DWC3_GHWPARAMS5 0xc154 | |
93 | #define DWC3_GHWPARAMS6 0xc158 | |
94 | #define DWC3_GHWPARAMS7 0xc15c | |
95 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
96 | #define DWC3_GDBGLTSSM 0xc164 | |
97 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
98 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
99 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
100 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
101 | ||
102 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) | |
103 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
104 | ||
105 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
106 | ||
107 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
108 | ||
109 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
110 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
111 | ||
112 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
113 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
114 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
115 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
116 | ||
117 | #define DWC3_GHWPARAMS8 0xc600 | |
d274cbbc | 118 | #define DWC3_GFLADJ 0xc630 |
85d5e707 KVA |
119 | |
120 | /* Device Registers */ | |
121 | #define DWC3_DCFG 0xc700 | |
122 | #define DWC3_DCTL 0xc704 | |
123 | #define DWC3_DEVTEN 0xc708 | |
124 | #define DWC3_DSTS 0xc70c | |
125 | #define DWC3_DGCMDPAR 0xc710 | |
126 | #define DWC3_DGCMD 0xc714 | |
127 | #define DWC3_DALEPENA 0xc720 | |
128 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
129 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
130 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
131 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
132 | ||
133 | /* OTG Registers */ | |
134 | #define DWC3_OCFG 0xcc00 | |
135 | #define DWC3_OCTL 0xcc04 | |
136 | #define DWC3_OEVT 0xcc08 | |
137 | #define DWC3_OEVTEN 0xcc0C | |
138 | #define DWC3_OSTS 0xcc10 | |
139 | ||
140 | /* Bit fields */ | |
141 | ||
f150b8d2 MW |
142 | /* Global SoC Bus Configuration INCRx Register 0 */ |
143 | #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ | |
144 | #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ | |
145 | #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ | |
146 | #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ | |
147 | #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ | |
148 | #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ | |
149 | #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ | |
150 | #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ | |
151 | #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff | |
152 | ||
85d5e707 KVA |
153 | /* Global Configuration Register */ |
154 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) | |
155 | #define DWC3_GCTL_U2RSTECN (1 << 16) | |
156 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) | |
157 | #define DWC3_GCTL_CLK_BUS (0) | |
158 | #define DWC3_GCTL_CLK_PIPE (1) | |
159 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
160 | #define DWC3_GCTL_CLK_MASK (3) | |
161 | ||
162 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) | |
163 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) | |
164 | #define DWC3_GCTL_PRTCAP_HOST 1 | |
165 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
166 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
167 | ||
168 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) | |
169 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) | |
170 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) | |
171 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
172 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) | |
173 | #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) | |
174 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) | |
175 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) | |
176 | ||
fafaa022 JT |
177 | /* Global User Control Register */ |
178 | #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) | |
179 | ||
dc18413a JT |
180 | /* Global User Control 1 Register */ |
181 | #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) | |
182 | #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) | |
183 | ||
85d5e707 KVA |
184 | /* Global USB2 PHY Configuration Register */ |
185 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) | |
b34f8b5d | 186 | #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) |
85d5e707 | 187 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) |
7bb62708 | 188 | #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) |
5c207282 JT |
189 | #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) |
190 | #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) | |
191 | #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) | |
192 | #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) | |
193 | #define USBTRDTIM_UTMI_8_BIT 9 | |
194 | #define USBTRDTIM_UTMI_16_BIT 5 | |
195 | #define UTMI_PHYIF_16_BIT 1 | |
196 | #define UTMI_PHYIF_8_BIT 0 | |
85d5e707 KVA |
197 | |
198 | /* Global USB3 PIPE Control Register */ | |
199 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) | |
200 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) | |
201 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) | |
202 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) | |
203 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) | |
204 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) | |
205 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) | |
206 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) | |
207 | #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) | |
208 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) | |
209 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) | |
210 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) | |
211 | ||
212 | /* Global TX Fifo Size Register */ | |
213 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) | |
214 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) | |
215 | ||
216 | /* Global Event Size Registers */ | |
217 | #define DWC3_GEVNTSIZ_INTMASK (1 << 31) | |
218 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) | |
219 | ||
220 | /* Global HWPARAMS1 Register */ | |
221 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) | |
222 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 | |
223 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
224 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 | |
225 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
226 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
227 | ||
228 | /* Global HWPARAMS3 Register */ | |
229 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) | |
230 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 | |
231 | #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 | |
232 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) | |
233 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 | |
234 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 | |
235 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 | |
236 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 | |
237 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) | |
238 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 | |
239 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 | |
240 | ||
241 | /* Global HWPARAMS4 Register */ | |
242 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
243 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
244 | ||
245 | /* Global HWPARAMS6 Register */ | |
246 | #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) | |
247 | ||
d274cbbc MW |
248 | /* Global Frame Length Adjustment Register */ |
249 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) | |
250 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f | |
c55ac51a SA |
251 | #define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8) |
252 | #define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24) | |
253 | #define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31) | |
d274cbbc | 254 | |
57548e8b BP |
255 | /* Global User Control Register*/ |
256 | #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 | |
257 | #define DWC3_GUCTL_REFCLKPER_SEL 22 | |
258 | ||
85d5e707 KVA |
259 | /* Device Configuration Register */ |
260 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
261 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
262 | ||
263 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
264 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
265 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
266 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
267 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
268 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
269 | ||
270 | #define DWC3_DCFG_LPM_CAP (1 << 22) | |
271 | ||
272 | /* Device Control Register */ | |
273 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
274 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
275 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
276 | ||
277 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
278 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) | |
279 | ||
280 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
281 | ||
282 | /* These apply for core versions 1.87a and earlier */ | |
283 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
284 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
285 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
286 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
287 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
288 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
289 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
290 | ||
291 | /* These apply for core versions 1.94a and later */ | |
292 | #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) | |
293 | #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) | |
294 | ||
295 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) | |
296 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) | |
297 | #define DWC3_DCTL_CRS (1 << 17) | |
298 | #define DWC3_DCTL_CSS (1 << 16) | |
299 | ||
300 | #define DWC3_DCTL_INITU2ENA (1 << 12) | |
301 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
302 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
303 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
304 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
305 | ||
306 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
307 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
308 | ||
309 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
310 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
311 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
312 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
313 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
314 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
315 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
316 | ||
317 | /* Device Event Enable Register */ | |
318 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
319 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
320 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
321 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
322 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
323 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
324 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) | |
325 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) | |
326 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
327 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
328 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
329 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
330 | ||
331 | /* Device Status Register */ | |
332 | #define DWC3_DSTS_DCNRD (1 << 29) | |
333 | ||
334 | /* This applies for core versions 1.87a and earlier */ | |
335 | #define DWC3_DSTS_PWRUPREQ (1 << 24) | |
336 | ||
337 | /* These apply for core versions 1.94a and later */ | |
338 | #define DWC3_DSTS_RSS (1 << 25) | |
339 | #define DWC3_DSTS_SSS (1 << 24) | |
340 | ||
341 | #define DWC3_DSTS_COREIDLE (1 << 23) | |
342 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
343 | ||
344 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
345 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
346 | ||
347 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
348 | ||
349 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) | |
350 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) | |
351 | ||
352 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
353 | ||
354 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
355 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
356 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
357 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
358 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
359 | ||
360 | /* Device Generic Command Register */ | |
361 | #define DWC3_DGCMD_SET_LMP 0x01 | |
362 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
363 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
364 | ||
365 | /* These apply for core versions 1.94a and later */ | |
366 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
367 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
368 | ||
369 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 | |
370 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
371 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
372 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
373 | ||
374 | #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) | |
375 | #define DWC3_DGCMD_CMDACT (1 << 10) | |
376 | #define DWC3_DGCMD_CMDIOC (1 << 8) | |
377 | ||
378 | /* Device Generic Command Parameter Register */ | |
379 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) | |
380 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) | |
381 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
382 | #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) | |
383 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) | |
384 | #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) | |
385 | ||
386 | /* Device Endpoint Command Register */ | |
387 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
388 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) | |
389 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) | |
390 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) | |
391 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) | |
392 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
393 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
394 | ||
395 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
396 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
397 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
398 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
399 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
400 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
401 | /* This applies for core versions 1.90a and earlier */ | |
402 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) | |
403 | /* This applies for core versions 1.94a and later */ | |
404 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
405 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) | |
406 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
407 | ||
95b4d655 FB |
408 | #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) |
409 | ||
85d5e707 KVA |
410 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
411 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
412 | ||
413 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
414 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
415 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
416 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
417 | ||
418 | /* Structures */ | |
419 | ||
420 | struct dwc3_trb; | |
421 | ||
422 | /** | |
423 | * struct dwc3_event_buffer - Software event buffer representation | |
424 | * @buf: _THE_ buffer | |
425 | * @length: size of this buffer | |
426 | * @lpos: event offset | |
427 | * @count: cache of last read event count register | |
428 | * @flags: flags related to this event buffer | |
429 | * @dma: dma_addr_t | |
430 | * @dwc: pointer to DWC controller | |
431 | */ | |
432 | struct dwc3_event_buffer { | |
433 | void *buf; | |
434 | unsigned length; | |
435 | unsigned int lpos; | |
436 | unsigned int count; | |
437 | unsigned int flags; | |
438 | ||
2252d150 | 439 | #define DWC3_EVENT_PENDING (1UL << 0) |
85d5e707 KVA |
440 | |
441 | dma_addr_t dma; | |
442 | ||
443 | struct dwc3 *dwc; | |
444 | }; | |
445 | ||
446 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
447 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
448 | ||
449 | #define DWC3_EP_DIRECTION_TX true | |
450 | #define DWC3_EP_DIRECTION_RX false | |
451 | ||
452 | #define DWC3_TRB_NUM 32 | |
453 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
454 | ||
455 | /** | |
456 | * struct dwc3_ep - device side endpoint representation | |
457 | * @endpoint: usb endpoint | |
458 | * @request_list: list of requests for this endpoint | |
459 | * @req_queued: list of requests on this ep which have TRBs setup | |
460 | * @trb_pool: array of transaction buffers | |
461 | * @trb_pool_dma: dma address of @trb_pool | |
462 | * @free_slot: next slot which is going to be used | |
463 | * @busy_slot: first slot which is owned by HW | |
464 | * @desc: usb_endpoint_descriptor pointer | |
465 | * @dwc: pointer to DWC controller | |
466 | * @saved_state: ep state saved during hibernation | |
467 | * @flags: endpoint flags (wedged, stalled, ...) | |
468 | * @current_trb: index of current used trb | |
469 | * @number: endpoint number (1 - 15) | |
470 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
471 | * @resource_index: Resource transfer index | |
472 | * @interval: the interval on which the ISOC transfer is started | |
473 | * @name: a human readable name e.g. ep1out-bulk | |
474 | * @direction: true for TX, false for RX | |
475 | * @stream_capable: true when streams are enabled | |
476 | */ | |
477 | struct dwc3_ep { | |
478 | struct usb_ep endpoint; | |
479 | struct list_head request_list; | |
480 | struct list_head req_queued; | |
481 | ||
482 | struct dwc3_trb *trb_pool; | |
483 | dma_addr_t trb_pool_dma; | |
484 | u32 free_slot; | |
485 | u32 busy_slot; | |
486 | const struct usb_ss_ep_comp_descriptor *comp_desc; | |
487 | struct dwc3 *dwc; | |
488 | ||
489 | u32 saved_state; | |
490 | unsigned flags; | |
491 | #define DWC3_EP_ENABLED (1 << 0) | |
492 | #define DWC3_EP_STALL (1 << 1) | |
493 | #define DWC3_EP_WEDGE (1 << 2) | |
494 | #define DWC3_EP_BUSY (1 << 4) | |
495 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
496 | #define DWC3_EP_MISSED_ISOC (1 << 6) | |
497 | ||
498 | /* This last one is specific to EP0 */ | |
499 | #define DWC3_EP0_DIR_IN (1 << 31) | |
500 | ||
501 | unsigned current_trb; | |
502 | ||
503 | u8 number; | |
504 | u8 type; | |
505 | u8 resource_index; | |
506 | u32 interval; | |
507 | ||
508 | char name[20]; | |
509 | ||
510 | unsigned direction:1; | |
511 | unsigned stream_capable:1; | |
512 | }; | |
513 | ||
514 | enum dwc3_phy { | |
515 | DWC3_PHY_UNKNOWN = 0, | |
516 | DWC3_PHY_USB3, | |
517 | DWC3_PHY_USB2, | |
518 | }; | |
519 | ||
520 | enum dwc3_ep0_next { | |
521 | DWC3_EP0_UNKNOWN = 0, | |
522 | DWC3_EP0_COMPLETE, | |
523 | DWC3_EP0_NRDY_DATA, | |
524 | DWC3_EP0_NRDY_STATUS, | |
525 | }; | |
526 | ||
527 | enum dwc3_ep0_state { | |
528 | EP0_UNCONNECTED = 0, | |
529 | EP0_SETUP_PHASE, | |
530 | EP0_DATA_PHASE, | |
531 | EP0_STATUS_PHASE, | |
532 | }; | |
533 | ||
534 | enum dwc3_link_state { | |
535 | /* In SuperSpeed */ | |
536 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
537 | DWC3_LINK_STATE_U1 = 0x01, | |
538 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
539 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
540 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
541 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
542 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
543 | DWC3_LINK_STATE_POLL = 0x07, | |
544 | DWC3_LINK_STATE_RECOV = 0x08, | |
545 | DWC3_LINK_STATE_HRESET = 0x09, | |
546 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
547 | DWC3_LINK_STATE_LPBK = 0x0b, | |
548 | DWC3_LINK_STATE_RESET = 0x0e, | |
549 | DWC3_LINK_STATE_RESUME = 0x0f, | |
550 | DWC3_LINK_STATE_MASK = 0x0f, | |
551 | }; | |
552 | ||
553 | /* TRB Length, PCM and Status */ | |
554 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
555 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
556 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
557 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) | |
558 | ||
559 | #define DWC3_TRBSTS_OK 0 | |
560 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
561 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
562 | #define DWC3_TRB_STS_XFER_IN_PROG 4 | |
563 | ||
564 | /* TRB Control */ | |
565 | #define DWC3_TRB_CTRL_HWO (1 << 0) | |
566 | #define DWC3_TRB_CTRL_LST (1 << 1) | |
567 | #define DWC3_TRB_CTRL_CHN (1 << 2) | |
568 | #define DWC3_TRB_CTRL_CSP (1 << 3) | |
569 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) | |
570 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) | |
571 | #define DWC3_TRB_CTRL_IOC (1 << 11) | |
572 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) | |
573 | ||
574 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) | |
575 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
576 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
577 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
578 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
579 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
580 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
581 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
582 | ||
583 | /** | |
584 | * struct dwc3_trb - transfer request block (hw format) | |
585 | * @bpl: DW0-3 | |
586 | * @bph: DW4-7 | |
587 | * @size: DW8-B | |
588 | * @trl: DWC-F | |
589 | */ | |
590 | struct dwc3_trb { | |
591 | u32 bpl; | |
592 | u32 bph; | |
593 | u32 size; | |
594 | u32 ctrl; | |
595 | } __packed; | |
596 | ||
597 | /** | |
598 | * dwc3_hwparams - copy of HWPARAMS registers | |
599 | * @hwparams0 - GHWPARAMS0 | |
600 | * @hwparams1 - GHWPARAMS1 | |
601 | * @hwparams2 - GHWPARAMS2 | |
602 | * @hwparams3 - GHWPARAMS3 | |
603 | * @hwparams4 - GHWPARAMS4 | |
604 | * @hwparams5 - GHWPARAMS5 | |
605 | * @hwparams6 - GHWPARAMS6 | |
606 | * @hwparams7 - GHWPARAMS7 | |
607 | * @hwparams8 - GHWPARAMS8 | |
608 | */ | |
609 | struct dwc3_hwparams { | |
610 | u32 hwparams0; | |
611 | u32 hwparams1; | |
612 | u32 hwparams2; | |
613 | u32 hwparams3; | |
614 | u32 hwparams4; | |
615 | u32 hwparams5; | |
616 | u32 hwparams6; | |
617 | u32 hwparams7; | |
618 | u32 hwparams8; | |
619 | }; | |
620 | ||
621 | /* HWPARAMS0 */ | |
622 | #define DWC3_MODE(n) ((n) & 0x7) | |
623 | ||
624 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) | |
625 | ||
626 | /* HWPARAMS1 */ | |
627 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) | |
628 | ||
629 | /* HWPARAMS3 */ | |
630 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
631 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
632 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
633 | (DWC3_NUM_EPS_MASK)) >> 12) | |
634 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
635 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
636 | ||
637 | /* HWPARAMS7 */ | |
638 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
639 | ||
640 | struct dwc3_request { | |
641 | struct usb_request request; | |
642 | struct list_head list; | |
643 | struct dwc3_ep *dep; | |
644 | u32 start_slot; | |
645 | ||
646 | u8 epnum; | |
647 | struct dwc3_trb *trb; | |
648 | dma_addr_t trb_dma; | |
649 | ||
650 | unsigned direction:1; | |
651 | unsigned mapped:1; | |
652 | unsigned queued:1; | |
653 | }; | |
654 | ||
655 | /* | |
656 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
657 | * (format defined by hw) | |
658 | */ | |
659 | struct dwc3_scratchpad_array { | |
660 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
661 | }; | |
662 | ||
663 | /** | |
664 | * struct dwc3 - representation of our controller | |
665 | * @ctrl_req: usb control request which is used for ep0 | |
666 | * @ep0_trb: trb which is used for the ctrl_req | |
667 | * @ep0_bounce: bounce buffer for ep0 | |
668 | * @setup_buf: used while precessing STD USB requests | |
669 | * @ctrl_req_addr: dma address of ctrl_req | |
670 | * @ep0_trb: dma address of ep0_trb | |
671 | * @ep0_usb_req: dummy req used while handling STD USB requests | |
672 | * @ep0_bounce_addr: dma address of ep0_bounce | |
673 | * @scratch_addr: dma address of scratchbuf | |
674 | * @lock: for synchronizing | |
675 | * @dev: pointer to our struct device | |
676 | * @xhci: pointer to our xHCI child | |
677 | * @event_buffer_list: a list of event buffers | |
678 | * @gadget: device side representation of the peripheral controller | |
679 | * @gadget_driver: pointer to the gadget driver | |
8ae84e64 | 680 | * @ref_clk: reference clock |
85d5e707 KVA |
681 | * @regs: base address for our registers |
682 | * @regs_size: address space size | |
57548e8b | 683 | * @ref_clk_per: reference clock period configuration |
85d5e707 KVA |
684 | * @nr_scratch: number of scratch buffers |
685 | * @num_event_buffers: calculated number of event buffers | |
686 | * @u1u2: only used on revisions <1.83a for workaround | |
687 | * @maximum_speed: maximum speed requested (mainly for testing purposes) | |
688 | * @revision: revision register contents | |
689 | * @dr_mode: requested mode of operation | |
64697942 FW |
690 | * @hsphy_mode: UTMI phy mode, one of following: |
691 | * - USBPHY_INTERFACE_MODE_UTMI | |
692 | * - USBPHY_INTERFACE_MODE_UTMIW | |
85d5e707 KVA |
693 | * @dcfg: saved contents of DCFG register |
694 | * @gctl: saved contents of GCTL register | |
695 | * @isoch_delay: wValue from Set Isochronous Delay request; | |
696 | * @u2sel: parameter from Set SEL request. | |
697 | * @u2pel: parameter from Set SEL request. | |
698 | * @u1sel: parameter from Set SEL request. | |
699 | * @u1pel: parameter from Set SEL request. | |
700 | * @num_out_eps: number of out endpoints | |
701 | * @num_in_eps: number of in endpoints | |
702 | * @ep0_next_event: hold the next expected event | |
703 | * @ep0state: state of endpoint zero | |
704 | * @link_state: link state | |
705 | * @speed: device speed (super, high, full, low) | |
706 | * @mem: points to start of memory which is used for this struct. | |
707 | * @hwparams: copy of hwparams registers | |
708 | * @root: debugfs root folder pointer | |
709 | * @regset: debugfs pointer to regdump file | |
710 | * @test_mode: true when we're entering a USB test mode | |
711 | * @test_mode_nr: test feature selector | |
712 | * @lpm_nyet_threshold: LPM NYET response threshold | |
713 | * @hird_threshold: HIRD threshold | |
714 | * @delayed_status: true when gadget driver asks for delayed status | |
715 | * @ep0_bounced: true when we used bounce buffer | |
716 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
717 | * @has_hibernation: true when dwc3 was configured with Hibernation | |
718 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that | |
719 | * there's now way for software to detect this in runtime. | |
720 | * @is_utmi_l1_suspend: the core asserts output signal | |
0cf207ec WD |
721 | * 0 - utmi_sleep_n |
722 | * 1 - utmi_l1_suspend_n | |
85d5e707 KVA |
723 | * @is_selfpowered: true when we are selfpowered |
724 | * @is_fpga: true when we are using the FPGA board | |
725 | * @needs_fifo_resize: not all users might want fifo resizing, flag it | |
726 | * @pullups_connected: true when Run/Stop bit is set | |
727 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | |
728 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround | |
729 | * @start_config_issued: true when StartConfig command has been issued | |
730 | * @three_stage_setup: set if we perform a three phase setup | |
731 | * @disable_scramble_quirk: set if we enable the disable scramble quirk | |
732 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk | |
733 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk | |
734 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk | |
735 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk | |
736 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk | |
737 | * @lfps_filter_quirk: set if we enable LFPS filter quirk | |
738 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk | |
739 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy | |
740 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy | |
741 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk | |
742 | * @tx_de_emphasis: Tx de-emphasis value | |
0cf207ec WD |
743 | * 0 - -6dB de-emphasis |
744 | * 1 - -3.5dB de-emphasis | |
745 | * 2 - No de-emphasis | |
746 | * 3 - Reserved | |
793d347f KVA |
747 | * @index: index of _this_ controller |
748 | * @list: to maintain the list of dwc3 controllers | |
85d5e707 KVA |
749 | */ |
750 | struct dwc3 { | |
751 | struct usb_ctrlrequest *ctrl_req; | |
752 | struct dwc3_trb *ep0_trb; | |
753 | void *ep0_bounce; | |
754 | void *scratchbuf; | |
755 | u8 *setup_buf; | |
756 | dma_addr_t ctrl_req_addr; | |
757 | dma_addr_t ep0_trb_addr; | |
758 | dma_addr_t ep0_bounce_addr; | |
759 | dma_addr_t scratch_addr; | |
760 | struct dwc3_request ep0_usb_req; | |
761 | ||
762 | /* device lock */ | |
763 | spinlock_t lock; | |
764 | ||
fd09c205 | 765 | #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB) |
23ba2d63 M |
766 | struct udevice *dev; |
767 | #else | |
85d5e707 | 768 | struct device *dev; |
23ba2d63 | 769 | #endif |
85d5e707 KVA |
770 | |
771 | struct platform_device *xhci; | |
772 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; | |
773 | ||
774 | struct dwc3_event_buffer **ev_buffs; | |
775 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; | |
776 | ||
777 | struct usb_gadget gadget; | |
778 | struct usb_gadget_driver *gadget_driver; | |
779 | ||
8ae84e64 MV |
780 | struct clk *ref_clk; |
781 | ||
85d5e707 KVA |
782 | void __iomem *regs; |
783 | size_t regs_size; | |
784 | ||
785 | enum usb_dr_mode dr_mode; | |
64697942 | 786 | enum usb_phy_interface hsphy_mode; |
85d5e707 KVA |
787 | |
788 | /* used for suspend/resume */ | |
789 | u32 dcfg; | |
790 | u32 gctl; | |
791 | ||
792 | u32 nr_scratch; | |
793 | u32 num_event_buffers; | |
794 | u32 u1u2; | |
795 | u32 maximum_speed; | |
796 | u32 revision; | |
797 | ||
798 | #define DWC3_REVISION_173A 0x5533173a | |
799 | #define DWC3_REVISION_175A 0x5533175a | |
800 | #define DWC3_REVISION_180A 0x5533180a | |
801 | #define DWC3_REVISION_183A 0x5533183a | |
802 | #define DWC3_REVISION_185A 0x5533185a | |
803 | #define DWC3_REVISION_187A 0x5533187a | |
804 | #define DWC3_REVISION_188A 0x5533188a | |
805 | #define DWC3_REVISION_190A 0x5533190a | |
806 | #define DWC3_REVISION_194A 0x5533194a | |
807 | #define DWC3_REVISION_200A 0x5533200a | |
808 | #define DWC3_REVISION_202A 0x5533202a | |
809 | #define DWC3_REVISION_210A 0x5533210a | |
810 | #define DWC3_REVISION_220A 0x5533220a | |
811 | #define DWC3_REVISION_230A 0x5533230a | |
812 | #define DWC3_REVISION_240A 0x5533240a | |
813 | #define DWC3_REVISION_250A 0x5533250a | |
814 | #define DWC3_REVISION_260A 0x5533260a | |
815 | #define DWC3_REVISION_270A 0x5533270a | |
816 | #define DWC3_REVISION_280A 0x5533280a | |
dc18413a | 817 | #define DWC3_REVISION_290A 0x5533290a |
85d5e707 KVA |
818 | |
819 | enum dwc3_ep0_next ep0_next_event; | |
820 | enum dwc3_ep0_state ep0state; | |
821 | enum dwc3_link_state link_state; | |
822 | ||
823 | u16 isoch_delay; | |
824 | u16 u2sel; | |
825 | u16 u2pel; | |
826 | u8 u1sel; | |
827 | u8 u1pel; | |
828 | ||
829 | u8 speed; | |
830 | ||
831 | u8 num_out_eps; | |
832 | u8 num_in_eps; | |
833 | ||
834 | void *mem; | |
835 | ||
836 | struct dwc3_hwparams hwparams; | |
837 | struct dentry *root; | |
838 | struct debugfs_regset32 *regset; | |
839 | ||
840 | u8 test_mode; | |
841 | u8 test_mode_nr; | |
842 | u8 lpm_nyet_threshold; | |
843 | u8 hird_threshold; | |
d274cbbc | 844 | u32 fladj; |
57548e8b | 845 | u32 ref_clk_per; |
f150b8d2 MW |
846 | u8 incrx_mode; |
847 | u32 incrx_size; | |
85d5e707 KVA |
848 | |
849 | unsigned delayed_status:1; | |
850 | unsigned ep0_bounced:1; | |
851 | unsigned ep0_expect_in:1; | |
852 | unsigned has_hibernation:1; | |
853 | unsigned has_lpm_erratum:1; | |
854 | unsigned is_utmi_l1_suspend:1; | |
855 | unsigned is_selfpowered:1; | |
856 | unsigned is_fpga:1; | |
857 | unsigned needs_fifo_resize:1; | |
858 | unsigned pullups_connected:1; | |
859 | unsigned resize_fifos:1; | |
860 | unsigned setup_packet_pending:1; | |
861 | unsigned start_config_issued:1; | |
862 | unsigned three_stage_setup:1; | |
863 | ||
864 | unsigned disable_scramble_quirk:1; | |
865 | unsigned u2exit_lfps_quirk:1; | |
866 | unsigned u2ss_inp3_quirk:1; | |
867 | unsigned req_p1p2p3_quirk:1; | |
868 | unsigned del_p1p2p3_quirk:1; | |
869 | unsigned del_phy_power_chg_quirk:1; | |
870 | unsigned lfps_filter_quirk:1; | |
871 | unsigned rx_detect_poll_quirk:1; | |
872 | unsigned dis_u3_susphy_quirk:1; | |
873 | unsigned dis_u2_susphy_quirk:1; | |
73ca0140 | 874 | unsigned dis_del_phy_power_chg_quirk:1; |
dc18413a | 875 | unsigned dis_tx_ipgap_linecheck_quirk:1; |
7bb62708 | 876 | unsigned dis_enblslpm_quirk:1; |
b34f8b5d | 877 | unsigned dis_u2_freeclk_exists_quirk:1; |
85d5e707 KVA |
878 | |
879 | unsigned tx_de_emphasis_quirk:1; | |
880 | unsigned tx_de_emphasis:2; | |
793d347f KVA |
881 | int index; |
882 | struct list_head list; | |
85d5e707 KVA |
883 | }; |
884 | ||
f150b8d2 MW |
885 | #define INCRX_BURST_MODE 0 |
886 | #define INCRX_UNDEF_LENGTH_BURST_MODE 1 | |
887 | ||
85d5e707 KVA |
888 | /* -------------------------------------------------------------------------- */ |
889 | ||
890 | /* -------------------------------------------------------------------------- */ | |
891 | ||
892 | struct dwc3_event_type { | |
893 | u32 is_devspec:1; | |
894 | u32 type:7; | |
895 | u32 reserved8_31:24; | |
896 | } __packed; | |
897 | ||
898 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
899 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
900 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
901 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
902 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
903 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
904 | ||
b6d959ac KVA |
905 | /** |
906 | * dwc3_ep_event_string - returns event name | |
907 | * @event: then event code | |
908 | */ | |
909 | static inline const char *dwc3_ep_event_string(u8 event) | |
910 | { | |
911 | switch (event) { | |
912 | case DWC3_DEPEVT_XFERCOMPLETE: | |
913 | return "Transfer Complete"; | |
914 | case DWC3_DEPEVT_XFERINPROGRESS: | |
915 | return "Transfer In-Progress"; | |
916 | case DWC3_DEPEVT_XFERNOTREADY: | |
917 | return "Transfer Not Ready"; | |
918 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
919 | return "FIFO"; | |
920 | case DWC3_DEPEVT_STREAMEVT: | |
921 | return "Stream"; | |
922 | case DWC3_DEPEVT_EPCMDCMPLT: | |
923 | return "Endpoint Command Complete"; | |
924 | } | |
925 | ||
926 | return "UNKNOWN"; | |
927 | } | |
928 | ||
85d5e707 KVA |
929 | /** |
930 | * struct dwc3_event_depvt - Device Endpoint Events | |
931 | * @one_bit: indicates this is an endpoint event (not used) | |
932 | * @endpoint_number: number of the endpoint | |
933 | * @endpoint_event: The event we have: | |
934 | * 0x00 - Reserved | |
935 | * 0x01 - XferComplete | |
936 | * 0x02 - XferInProgress | |
937 | * 0x03 - XferNotReady | |
938 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
939 | * 0x05 - Reserved | |
940 | * 0x06 - StreamEvt | |
941 | * 0x07 - EPCmdCmplt | |
942 | * @reserved11_10: Reserved, don't use. | |
943 | * @status: Indicates the status of the event. Refer to databook for | |
944 | * more information. | |
945 | * @parameters: Parameters of the current event. Refer to databook for | |
946 | * more information. | |
947 | */ | |
948 | struct dwc3_event_depevt { | |
949 | u32 one_bit:1; | |
950 | u32 endpoint_number:5; | |
951 | u32 endpoint_event:4; | |
952 | u32 reserved11_10:2; | |
953 | u32 status:4; | |
954 | ||
955 | /* Within XferNotReady */ | |
956 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) | |
957 | ||
958 | /* Within XferComplete */ | |
959 | #define DEPEVT_STATUS_BUSERR (1 << 0) | |
960 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
961 | #define DEPEVT_STATUS_IOC (1 << 2) | |
962 | #define DEPEVT_STATUS_LST (1 << 3) | |
963 | ||
964 | /* Stream event only */ | |
965 | #define DEPEVT_STREAMEVT_FOUND 1 | |
966 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
967 | ||
968 | /* Control-only Status */ | |
969 | #define DEPEVT_STATUS_CONTROL_DATA 1 | |
970 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
971 | ||
972 | u32 parameters:16; | |
973 | } __packed; | |
974 | ||
975 | /** | |
976 | * struct dwc3_event_devt - Device Events | |
977 | * @one_bit: indicates this is a non-endpoint event (not used) | |
978 | * @device_event: indicates it's a device event. Should read as 0x00 | |
979 | * @type: indicates the type of device event. | |
980 | * 0 - DisconnEvt | |
981 | * 1 - USBRst | |
982 | * 2 - ConnectDone | |
983 | * 3 - ULStChng | |
984 | * 4 - WkUpEvt | |
985 | * 5 - Reserved | |
986 | * 6 - EOPF | |
987 | * 7 - SOF | |
988 | * 8 - Reserved | |
989 | * 9 - ErrticErr | |
990 | * 10 - CmdCmplt | |
991 | * 11 - EvntOverflow | |
992 | * 12 - VndrDevTstRcved | |
993 | * @reserved15_12: Reserved, not used | |
994 | * @event_info: Information about this event | |
995 | * @reserved31_25: Reserved, not used | |
996 | */ | |
997 | struct dwc3_event_devt { | |
998 | u32 one_bit:1; | |
999 | u32 device_event:7; | |
1000 | u32 type:4; | |
1001 | u32 reserved15_12:4; | |
1002 | u32 event_info:9; | |
1003 | u32 reserved31_25:7; | |
1004 | } __packed; | |
1005 | ||
1006 | /** | |
1007 | * struct dwc3_event_gevt - Other Core Events | |
1008 | * @one_bit: indicates this is a non-endpoint event (not used) | |
1009 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
1010 | * @phy_port_number: self-explanatory | |
1011 | * @reserved31_12: Reserved, not used. | |
1012 | */ | |
1013 | struct dwc3_event_gevt { | |
1014 | u32 one_bit:1; | |
1015 | u32 device_event:7; | |
1016 | u32 phy_port_number:4; | |
1017 | u32 reserved31_12:20; | |
1018 | } __packed; | |
1019 | ||
1020 | /** | |
1021 | * union dwc3_event - representation of Event Buffer contents | |
1022 | * @raw: raw 32-bit event | |
1023 | * @type: the type of the event | |
1024 | * @depevt: Device Endpoint Event | |
1025 | * @devt: Device Event | |
1026 | * @gevt: Global Event | |
1027 | */ | |
1028 | union dwc3_event { | |
1029 | u32 raw; | |
1030 | struct dwc3_event_type type; | |
1031 | struct dwc3_event_depevt depevt; | |
1032 | struct dwc3_event_devt devt; | |
1033 | struct dwc3_event_gevt gevt; | |
1034 | }; | |
1035 | ||
1036 | /** | |
1037 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command | |
1038 | * parameters | |
1039 | * @param2: third parameter | |
1040 | * @param1: second parameter | |
1041 | * @param0: first parameter | |
1042 | */ | |
1043 | struct dwc3_gadget_ep_cmd_params { | |
1044 | u32 param2; | |
1045 | u32 param1; | |
1046 | u32 param0; | |
1047 | }; | |
1048 | ||
1049 | /* | |
1050 | * DWC3 Features to be used as Driver Data | |
1051 | */ | |
1052 | ||
1053 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
1054 | #define DWC3_HAS_XHCI BIT(1) | |
1055 | #define DWC3_HAS_OTG BIT(3) | |
1056 | ||
1057 | /* prototypes */ | |
85d5e707 | 1058 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
ba6c5f7a | 1059 | void dwc3_of_parse(struct dwc3 *dwc); |
23ba2d63 M |
1060 | int dwc3_init(struct dwc3 *dwc); |
1061 | void dwc3_remove(struct dwc3 *dwc); | |
85d5e707 | 1062 | |
85d5e707 KVA |
1063 | static inline int dwc3_host_init(struct dwc3 *dwc) |
1064 | { return 0; } | |
1065 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
1066 | { } | |
85d5e707 | 1067 | |
9848e574 | 1068 | #ifdef CONFIG_USB_DWC3_GADGET |
85d5e707 KVA |
1069 | int dwc3_gadget_init(struct dwc3 *dwc); |
1070 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
1071 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); | |
1072 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); | |
1073 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); | |
1074 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, | |
1075 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); | |
1076 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); | |
1077 | #else | |
1078 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
1079 | { return 0; } | |
1080 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
1081 | { } | |
1082 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
1083 | { return 0; } | |
1084 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
1085 | { return 0; } | |
1086 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, | |
1087 | enum dwc3_link_state state) | |
1088 | { return 0; } | |
1089 | ||
1090 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, | |
1091 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
1092 | { return 0; } | |
1093 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, | |
1094 | int cmd, u32 param) | |
1095 | { return 0; } | |
1096 | #endif | |
1097 | ||
85d5e707 | 1098 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |