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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
33 | #include "core.h" | |
34 | #include "gadget.h" | |
35 | #include "io.h" | |
36 | ||
04a9bfcd FB |
37 | /** |
38 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
39 | * @dwc: pointer to our context structure | |
40 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
41 | * | |
42 | * Caller should take care of locking. This function will | |
43 | * return 0 on success or -EINVAL if wrong Test Selector | |
44 | * is passed | |
45 | */ | |
46 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
47 | { | |
48 | u32 reg; | |
49 | ||
50 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
51 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
52 | ||
53 | switch (mode) { | |
54 | case TEST_J: | |
55 | case TEST_K: | |
56 | case TEST_SE0_NAK: | |
57 | case TEST_PACKET: | |
58 | case TEST_FORCE_EN: | |
59 | reg |= mode << 1; | |
60 | break; | |
61 | default: | |
62 | return -EINVAL; | |
63 | } | |
64 | ||
65 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
8598bde7 FB |
70 | /** |
71 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
72 | * @dwc: pointer to our context structure | |
73 | * @state: the state to put link into | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
aee63e3c | 76 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
77 | */ |
78 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
79 | { | |
aee63e3c | 80 | int retries = 10000; |
8598bde7 FB |
81 | u32 reg; |
82 | ||
802fde98 PZ |
83 | /* |
84 | * Wait until device controller is ready. Only applies to 1.94a and | |
85 | * later RTL. | |
86 | */ | |
87 | if (dwc->revision >= DWC3_REVISION_194A) { | |
88 | while (--retries) { | |
89 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
90 | if (reg & DWC3_DSTS_DCNRD) | |
91 | udelay(5); | |
92 | else | |
93 | break; | |
94 | } | |
95 | ||
96 | if (retries <= 0) | |
97 | return -ETIMEDOUT; | |
98 | } | |
99 | ||
8598bde7 FB |
100 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
101 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
102 | ||
103 | /* set requested state */ | |
104 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
105 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
106 | ||
802fde98 PZ |
107 | /* |
108 | * The following code is racy when called from dwc3_gadget_wakeup, | |
109 | * and is not needed, at least on newer versions | |
110 | */ | |
111 | if (dwc->revision >= DWC3_REVISION_194A) | |
112 | return 0; | |
113 | ||
8598bde7 | 114 | /* wait for a change in DSTS */ |
aed430e5 | 115 | retries = 10000; |
8598bde7 FB |
116 | while (--retries) { |
117 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
118 | ||
8598bde7 FB |
119 | if (DWC3_DSTS_USBLNKST(reg) == state) |
120 | return 0; | |
121 | ||
aee63e3c | 122 | udelay(5); |
8598bde7 FB |
123 | } |
124 | ||
125 | dev_vdbg(dwc->dev, "link state change request timed out\n"); | |
126 | ||
127 | return -ETIMEDOUT; | |
128 | } | |
129 | ||
457e84b6 FB |
130 | /** |
131 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
132 | * @dwc: pointer to our context structure | |
133 | * | |
134 | * This function will a best effort FIFO allocation in order | |
135 | * to improve FIFO usage and throughput, while still allowing | |
136 | * us to enable as many endpoints as possible. | |
137 | * | |
138 | * Keep in mind that this operation will be highly dependent | |
139 | * on the configured size for RAM1 - which contains TxFifo -, | |
140 | * the amount of endpoints enabled on coreConsultant tool, and | |
141 | * the width of the Master Bus. | |
142 | * | |
143 | * In the ideal world, we would always be able to satisfy the | |
144 | * following equation: | |
145 | * | |
146 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
147 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
148 | * | |
149 | * Unfortunately, due to many variables that's not always the case. | |
150 | */ | |
151 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
152 | { | |
153 | int last_fifo_depth = 0; | |
154 | int ram1_depth; | |
155 | int fifo_size; | |
156 | int mdwidth; | |
157 | int num; | |
158 | ||
159 | if (!dwc->needs_fifo_resize) | |
160 | return 0; | |
161 | ||
162 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
163 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
164 | ||
165 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
166 | mdwidth >>= 3; | |
167 | ||
168 | /* | |
169 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
170 | * for each enabled endpoint, later patches will come to | |
171 | * improve this algorithm so that we better use the internal | |
172 | * FIFO space | |
173 | */ | |
174 | for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { | |
175 | struct dwc3_ep *dep = dwc->eps[num]; | |
176 | int fifo_number = dep->number >> 1; | |
2e81c36a | 177 | int mult = 1; |
457e84b6 FB |
178 | int tmp; |
179 | ||
180 | if (!(dep->number & 1)) | |
181 | continue; | |
182 | ||
183 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
184 | continue; | |
185 | ||
16e78db7 IS |
186 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
187 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
188 | mult = 3; |
189 | ||
190 | /* | |
191 | * REVISIT: the following assumes we will always have enough | |
192 | * space available on the FIFO RAM for all possible use cases. | |
193 | * Make sure that's true somehow and change FIFO allocation | |
194 | * accordingly. | |
195 | * | |
196 | * If we have Bulk or Isochronous endpoints, we want | |
197 | * them to be able to be very, very fast. So we're giving | |
198 | * those endpoints a fifo_size which is enough for 3 full | |
199 | * packets | |
200 | */ | |
201 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
202 | tmp += mdwidth; |
203 | ||
204 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 205 | |
457e84b6 FB |
206 | fifo_size |= (last_fifo_depth << 16); |
207 | ||
208 | dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", | |
209 | dep->name, last_fifo_depth, fifo_size & 0xffff); | |
210 | ||
211 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), | |
212 | fifo_size); | |
213 | ||
214 | last_fifo_depth += (fifo_size & 0xffff); | |
215 | } | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
72246da4 FB |
220 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
221 | int status) | |
222 | { | |
223 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 224 | int i; |
72246da4 FB |
225 | |
226 | if (req->queued) { | |
e5ba5ec8 PA |
227 | i = 0; |
228 | do { | |
eeb720fb | 229 | dep->busy_slot++; |
e5ba5ec8 PA |
230 | /* |
231 | * Skip LINK TRB. We can't use req->trb and check for | |
232 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we | |
233 | * just completed (not the LINK TRB). | |
234 | */ | |
235 | if (((dep->busy_slot & DWC3_TRB_MASK) == | |
236 | DWC3_TRB_NUM- 1) && | |
16e78db7 | 237 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
e5ba5ec8 PA |
238 | dep->busy_slot++; |
239 | } while(++i < req->request.num_mapped_sgs); | |
c9fda7d6 | 240 | req->queued = false; |
72246da4 FB |
241 | } |
242 | list_del(&req->list); | |
eeb720fb | 243 | req->trb = NULL; |
72246da4 FB |
244 | |
245 | if (req->request.status == -EINPROGRESS) | |
246 | req->request.status = status; | |
247 | ||
0416e494 PA |
248 | if (dwc->ep0_bounced && dep->number == 0) |
249 | dwc->ep0_bounced = false; | |
250 | else | |
251 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
252 | req->direction); | |
72246da4 FB |
253 | |
254 | dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", | |
255 | req, dep->name, req->request.actual, | |
256 | req->request.length, status); | |
257 | ||
258 | spin_unlock(&dwc->lock); | |
0fc9a1be | 259 | req->request.complete(&dep->endpoint, &req->request); |
72246da4 FB |
260 | spin_lock(&dwc->lock); |
261 | } | |
262 | ||
263 | static const char *dwc3_gadget_ep_cmd_string(u8 cmd) | |
264 | { | |
265 | switch (cmd) { | |
266 | case DWC3_DEPCMD_DEPSTARTCFG: | |
267 | return "Start New Configuration"; | |
268 | case DWC3_DEPCMD_ENDTRANSFER: | |
269 | return "End Transfer"; | |
270 | case DWC3_DEPCMD_UPDATETRANSFER: | |
271 | return "Update Transfer"; | |
272 | case DWC3_DEPCMD_STARTTRANSFER: | |
273 | return "Start Transfer"; | |
274 | case DWC3_DEPCMD_CLEARSTALL: | |
275 | return "Clear Stall"; | |
276 | case DWC3_DEPCMD_SETSTALL: | |
277 | return "Set Stall"; | |
802fde98 PZ |
278 | case DWC3_DEPCMD_GETEPSTATE: |
279 | return "Get Endpoint State"; | |
72246da4 FB |
280 | case DWC3_DEPCMD_SETTRANSFRESOURCE: |
281 | return "Set Endpoint Transfer Resource"; | |
282 | case DWC3_DEPCMD_SETEPCONFIG: | |
283 | return "Set Endpoint Configuration"; | |
284 | default: | |
285 | return "UNKNOWN command"; | |
286 | } | |
287 | } | |
288 | ||
b09bb642 FB |
289 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) |
290 | { | |
291 | u32 timeout = 500; | |
292 | u32 reg; | |
293 | ||
294 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
295 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
296 | ||
297 | do { | |
298 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
299 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
300 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", | |
301 | DWC3_DGCMD_STATUS(reg)); | |
302 | return 0; | |
303 | } | |
304 | ||
305 | /* | |
306 | * We can't sleep here, because it's also called from | |
307 | * interrupt context. | |
308 | */ | |
309 | timeout--; | |
310 | if (!timeout) | |
311 | return -ETIMEDOUT; | |
312 | udelay(1); | |
313 | } while (1); | |
314 | } | |
315 | ||
72246da4 FB |
316 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
317 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
318 | { | |
319 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 320 | u32 timeout = 500; |
72246da4 FB |
321 | u32 reg; |
322 | ||
323 | dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", | |
324 | dep->name, | |
dc1c70a7 FB |
325 | dwc3_gadget_ep_cmd_string(cmd), params->param0, |
326 | params->param1, params->param2); | |
72246da4 | 327 | |
dc1c70a7 FB |
328 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
329 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
330 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
331 | |
332 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
333 | do { | |
334 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
335 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
164f6e14 FB |
336 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", |
337 | DWC3_DEPCMD_STATUS(reg)); | |
72246da4 FB |
338 | return 0; |
339 | } | |
340 | ||
341 | /* | |
72246da4 FB |
342 | * We can't sleep here, because it is also called from |
343 | * interrupt context. | |
344 | */ | |
345 | timeout--; | |
346 | if (!timeout) | |
347 | return -ETIMEDOUT; | |
348 | ||
61d58242 | 349 | udelay(1); |
72246da4 FB |
350 | } while (1); |
351 | } | |
352 | ||
353 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 354 | struct dwc3_trb *trb) |
72246da4 | 355 | { |
c439ef87 | 356 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
357 | |
358 | return dep->trb_pool_dma + offset; | |
359 | } | |
360 | ||
361 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
362 | { | |
363 | struct dwc3 *dwc = dep->dwc; | |
364 | ||
365 | if (dep->trb_pool) | |
366 | return 0; | |
367 | ||
368 | if (dep->number == 0 || dep->number == 1) | |
369 | return 0; | |
370 | ||
371 | dep->trb_pool = dma_alloc_coherent(dwc->dev, | |
372 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
373 | &dep->trb_pool_dma, GFP_KERNEL); | |
374 | if (!dep->trb_pool) { | |
375 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
376 | dep->name); | |
377 | return -ENOMEM; | |
378 | } | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
384 | { | |
385 | struct dwc3 *dwc = dep->dwc; | |
386 | ||
387 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
388 | dep->trb_pool, dep->trb_pool_dma); | |
389 | ||
390 | dep->trb_pool = NULL; | |
391 | dep->trb_pool_dma = 0; | |
392 | } | |
393 | ||
394 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
395 | { | |
396 | struct dwc3_gadget_ep_cmd_params params; | |
397 | u32 cmd; | |
398 | ||
399 | memset(¶ms, 0x00, sizeof(params)); | |
400 | ||
401 | if (dep->number != 1) { | |
402 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
403 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
404 | if (dep->number > 1) { |
405 | if (dwc->start_config_issued) | |
406 | return 0; | |
407 | dwc->start_config_issued = true; | |
72246da4 | 408 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 409 | } |
72246da4 FB |
410 | |
411 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
412 | } | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 418 | const struct usb_endpoint_descriptor *desc, |
4b345c9a FB |
419 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
420 | bool ignore) | |
72246da4 FB |
421 | { |
422 | struct dwc3_gadget_ep_cmd_params params; | |
423 | ||
424 | memset(¶ms, 0x00, sizeof(params)); | |
425 | ||
dc1c70a7 | 426 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
427 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
428 | ||
429 | /* Burst size is only needed in SuperSpeed mode */ | |
430 | if (dwc->gadget.speed == USB_SPEED_SUPER) { | |
431 | u32 burst = dep->endpoint.maxburst - 1; | |
432 | ||
433 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); | |
434 | } | |
72246da4 | 435 | |
4b345c9a FB |
436 | if (ignore) |
437 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
438 | ||
dc1c70a7 FB |
439 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
440 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 441 | |
18b7ede5 | 442 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
443 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
444 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
445 | dep->stream_capable = true; |
446 | } | |
447 | ||
72246da4 | 448 | if (usb_endpoint_xfer_isoc(desc)) |
dc1c70a7 | 449 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
450 | |
451 | /* | |
452 | * We are doing 1:1 mapping for endpoints, meaning | |
453 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
454 | * so on. We consider the direction bit as part of the physical | |
455 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
456 | */ | |
dc1c70a7 | 457 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
458 | |
459 | /* | |
460 | * We must use the lower 16 TX FIFOs even though | |
461 | * HW might have more | |
462 | */ | |
463 | if (dep->direction) | |
dc1c70a7 | 464 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
465 | |
466 | if (desc->bInterval) { | |
dc1c70a7 | 467 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
468 | dep->interval = 1 << (desc->bInterval - 1); |
469 | } | |
470 | ||
471 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
472 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
473 | } | |
474 | ||
475 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
476 | { | |
477 | struct dwc3_gadget_ep_cmd_params params; | |
478 | ||
479 | memset(¶ms, 0x00, sizeof(params)); | |
480 | ||
dc1c70a7 | 481 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
482 | |
483 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
484 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
485 | } | |
486 | ||
487 | /** | |
488 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
489 | * @dep: endpoint to be initialized | |
490 | * @desc: USB Endpoint Descriptor | |
491 | * | |
492 | * Caller should take care of locking | |
493 | */ | |
494 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 495 | const struct usb_endpoint_descriptor *desc, |
4b345c9a FB |
496 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
497 | bool ignore) | |
72246da4 FB |
498 | { |
499 | struct dwc3 *dwc = dep->dwc; | |
500 | u32 reg; | |
501 | int ret = -ENOMEM; | |
502 | ||
ff62d6b6 FB |
503 | dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); |
504 | ||
72246da4 FB |
505 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
506 | ret = dwc3_gadget_start_config(dwc, dep); | |
507 | if (ret) | |
508 | return ret; | |
509 | } | |
510 | ||
4b345c9a | 511 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore); |
72246da4 FB |
512 | if (ret) |
513 | return ret; | |
514 | ||
515 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
516 | struct dwc3_trb *trb_st_hw; |
517 | struct dwc3_trb *trb_link; | |
72246da4 FB |
518 | |
519 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
520 | if (ret) | |
521 | return ret; | |
522 | ||
16e78db7 | 523 | dep->endpoint.desc = desc; |
c90bfaec | 524 | dep->comp_desc = comp_desc; |
72246da4 FB |
525 | dep->type = usb_endpoint_type(desc); |
526 | dep->flags |= DWC3_EP_ENABLED; | |
527 | ||
528 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
529 | reg |= DWC3_DALEPENA_EP(dep->number); | |
530 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
531 | ||
532 | if (!usb_endpoint_xfer_isoc(desc)) | |
533 | return 0; | |
534 | ||
1d046793 | 535 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
536 | trb_st_hw = &dep->trb_pool[0]; |
537 | ||
f6bafc6a | 538 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
ee3e596a | 539 | memset(trb_link, 0, sizeof(*trb_link)); |
72246da4 | 540 | |
f6bafc6a FB |
541 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
542 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
543 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
544 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
545 | } |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
624407f9 SAS |
550 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); |
551 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) | |
72246da4 FB |
552 | { |
553 | struct dwc3_request *req; | |
554 | ||
ea53b882 | 555 | if (!list_empty(&dep->req_queued)) { |
624407f9 SAS |
556 | dwc3_stop_active_transfer(dwc, dep->number); |
557 | ||
57911504 | 558 | /* - giveback all requests to gadget driver */ |
1591633e PA |
559 | while (!list_empty(&dep->req_queued)) { |
560 | req = next_request(&dep->req_queued); | |
561 | ||
562 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
563 | } | |
ea53b882 FB |
564 | } |
565 | ||
72246da4 FB |
566 | while (!list_empty(&dep->request_list)) { |
567 | req = next_request(&dep->request_list); | |
568 | ||
624407f9 | 569 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 570 | } |
72246da4 FB |
571 | } |
572 | ||
573 | /** | |
574 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
575 | * @dep: the endpoint to disable | |
576 | * | |
624407f9 SAS |
577 | * This function also removes requests which are currently processed ny the |
578 | * hardware and those which are not yet scheduled. | |
579 | * Caller should take care of locking. | |
72246da4 | 580 | */ |
72246da4 FB |
581 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
582 | { | |
583 | struct dwc3 *dwc = dep->dwc; | |
584 | u32 reg; | |
585 | ||
624407f9 | 586 | dwc3_remove_requests(dwc, dep); |
72246da4 | 587 | |
0d8b12fc FB |
588 | /* make sure HW endpoint isn't stalled */ |
589 | if (dep->flags & DWC3_EP_STALL) | |
55016b9e | 590 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
0d8b12fc | 591 | |
72246da4 FB |
592 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
593 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
594 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
595 | ||
879631aa | 596 | dep->stream_capable = false; |
f9c56cdd | 597 | dep->endpoint.desc = NULL; |
c90bfaec | 598 | dep->comp_desc = NULL; |
72246da4 | 599 | dep->type = 0; |
879631aa | 600 | dep->flags = 0; |
72246da4 FB |
601 | |
602 | return 0; | |
603 | } | |
604 | ||
605 | /* -------------------------------------------------------------------------- */ | |
606 | ||
607 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
608 | const struct usb_endpoint_descriptor *desc) | |
609 | { | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
613 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
614 | { | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
618 | /* -------------------------------------------------------------------------- */ | |
619 | ||
620 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
621 | const struct usb_endpoint_descriptor *desc) | |
622 | { | |
623 | struct dwc3_ep *dep; | |
624 | struct dwc3 *dwc; | |
625 | unsigned long flags; | |
626 | int ret; | |
627 | ||
628 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
629 | pr_debug("dwc3: invalid parameters\n"); | |
630 | return -EINVAL; | |
631 | } | |
632 | ||
633 | if (!desc->wMaxPacketSize) { | |
634 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
635 | return -EINVAL; | |
636 | } | |
637 | ||
638 | dep = to_dwc3_ep(ep); | |
639 | dwc = dep->dwc; | |
640 | ||
c6f83f38 FB |
641 | if (dep->flags & DWC3_EP_ENABLED) { |
642 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
643 | dep->name); | |
644 | return 0; | |
645 | } | |
646 | ||
72246da4 FB |
647 | switch (usb_endpoint_type(desc)) { |
648 | case USB_ENDPOINT_XFER_CONTROL: | |
27a78d6a | 649 | strlcat(dep->name, "-control", sizeof(dep->name)); |
72246da4 FB |
650 | break; |
651 | case USB_ENDPOINT_XFER_ISOC: | |
27a78d6a | 652 | strlcat(dep->name, "-isoc", sizeof(dep->name)); |
72246da4 FB |
653 | break; |
654 | case USB_ENDPOINT_XFER_BULK: | |
27a78d6a | 655 | strlcat(dep->name, "-bulk", sizeof(dep->name)); |
72246da4 FB |
656 | break; |
657 | case USB_ENDPOINT_XFER_INT: | |
27a78d6a | 658 | strlcat(dep->name, "-int", sizeof(dep->name)); |
72246da4 FB |
659 | break; |
660 | default: | |
661 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
662 | } | |
663 | ||
72246da4 | 664 | spin_lock_irqsave(&dwc->lock, flags); |
4b345c9a | 665 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false); |
72246da4 FB |
666 | spin_unlock_irqrestore(&dwc->lock, flags); |
667 | ||
668 | return ret; | |
669 | } | |
670 | ||
671 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
672 | { | |
673 | struct dwc3_ep *dep; | |
674 | struct dwc3 *dwc; | |
675 | unsigned long flags; | |
676 | int ret; | |
677 | ||
678 | if (!ep) { | |
679 | pr_debug("dwc3: invalid parameters\n"); | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | dep = to_dwc3_ep(ep); | |
684 | dwc = dep->dwc; | |
685 | ||
686 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
687 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
688 | dep->name); | |
689 | return 0; | |
690 | } | |
691 | ||
692 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", | |
693 | dep->number >> 1, | |
694 | (dep->number & 1) ? "in" : "out"); | |
695 | ||
696 | spin_lock_irqsave(&dwc->lock, flags); | |
697 | ret = __dwc3_gadget_ep_disable(dep); | |
698 | spin_unlock_irqrestore(&dwc->lock, flags); | |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
703 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
704 | gfp_t gfp_flags) | |
705 | { | |
706 | struct dwc3_request *req; | |
707 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
708 | struct dwc3 *dwc = dep->dwc; | |
709 | ||
710 | req = kzalloc(sizeof(*req), gfp_flags); | |
711 | if (!req) { | |
712 | dev_err(dwc->dev, "not enough memory\n"); | |
713 | return NULL; | |
714 | } | |
715 | ||
716 | req->epnum = dep->number; | |
717 | req->dep = dep; | |
72246da4 FB |
718 | |
719 | return &req->request; | |
720 | } | |
721 | ||
722 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
723 | struct usb_request *request) | |
724 | { | |
725 | struct dwc3_request *req = to_dwc3_request(request); | |
726 | ||
727 | kfree(req); | |
728 | } | |
729 | ||
c71fc37c FB |
730 | /** |
731 | * dwc3_prepare_one_trb - setup one TRB from one request | |
732 | * @dep: endpoint for which this request is prepared | |
733 | * @req: dwc3_request pointer | |
734 | */ | |
68e823e2 | 735 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 736 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 737 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 738 | { |
eeb720fb | 739 | struct dwc3 *dwc = dep->dwc; |
f6bafc6a | 740 | struct dwc3_trb *trb; |
c71fc37c | 741 | |
eeb720fb FB |
742 | dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", |
743 | dep->name, req, (unsigned long long) dma, | |
744 | length, last ? " last" : "", | |
745 | chain ? " chain" : ""); | |
746 | ||
c71fc37c | 747 | /* Skip the LINK-TRB on ISOC */ |
915e202a | 748 | if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && |
16e78db7 | 749 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
915e202a PA |
750 | dep->free_slot++; |
751 | ||
752 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; | |
c71fc37c | 753 | |
eeb720fb FB |
754 | if (!req->trb) { |
755 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
756 | req->trb = trb; |
757 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e5ba5ec8 | 758 | req->start_slot = dep->free_slot & DWC3_TRB_MASK; |
eeb720fb | 759 | } |
c71fc37c | 760 | |
e5ba5ec8 PA |
761 | dep->free_slot++; |
762 | ||
f6bafc6a FB |
763 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
764 | trb->bpl = lower_32_bits(dma); | |
765 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 766 | |
16e78db7 | 767 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 768 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 769 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
770 | break; |
771 | ||
772 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
773 | if (!node) |
774 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
775 | else | |
776 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
c71fc37c | 777 | |
e5ba5ec8 | 778 | if (!req->request.no_interrupt && !chain) |
f6bafc6a | 779 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
c71fc37c FB |
780 | break; |
781 | ||
782 | case USB_ENDPOINT_XFER_BULK: | |
783 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 784 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
785 | break; |
786 | default: | |
787 | /* | |
788 | * This is only possible with faulty memory because we | |
789 | * checked it already :) | |
790 | */ | |
791 | BUG(); | |
792 | } | |
793 | ||
16e78db7 | 794 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
795 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
796 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
e5ba5ec8 PA |
797 | } else if (last) { |
798 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
f6bafc6a | 799 | } |
c71fc37c | 800 | |
e5ba5ec8 PA |
801 | if (chain) |
802 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
803 | ||
16e78db7 | 804 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 805 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 806 | |
f6bafc6a | 807 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
c71fc37c FB |
808 | } |
809 | ||
72246da4 FB |
810 | /* |
811 | * dwc3_prepare_trbs - setup TRBs from requests | |
812 | * @dep: endpoint for which requests are being prepared | |
813 | * @starting: true if the endpoint is idle and no requests are queued. | |
814 | * | |
1d046793 PZ |
815 | * The function goes through the requests list and sets up TRBs for the |
816 | * transfers. The function returns once there are no more TRBs available or | |
817 | * it runs out of requests. | |
72246da4 | 818 | */ |
68e823e2 | 819 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 820 | { |
68e823e2 | 821 | struct dwc3_request *req, *n; |
72246da4 | 822 | u32 trbs_left; |
8d62cd65 | 823 | u32 max; |
c71fc37c | 824 | unsigned int last_one = 0; |
72246da4 FB |
825 | |
826 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
827 | ||
828 | /* the first request must not be queued */ | |
829 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 830 | |
8d62cd65 | 831 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 832 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
833 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
834 | if (trbs_left > max) | |
835 | trbs_left = max; | |
836 | } | |
837 | ||
72246da4 | 838 | /* |
1d046793 PZ |
839 | * If busy & slot are equal than it is either full or empty. If we are |
840 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
841 | * full and don't do anything |
842 | */ | |
843 | if (!trbs_left) { | |
844 | if (!starting) | |
68e823e2 | 845 | return; |
72246da4 FB |
846 | trbs_left = DWC3_TRB_NUM; |
847 | /* | |
848 | * In case we start from scratch, we queue the ISOC requests | |
849 | * starting from slot 1. This is done because we use ring | |
850 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 851 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
852 | * after the first request so we start at slot 1 and have |
853 | * 7 requests proceed before we hit the first IOC. | |
854 | * Other transfer types don't use the ring buffer and are | |
855 | * processed from the first TRB until the last one. Since we | |
856 | * don't wrap around we have to start at the beginning. | |
857 | */ | |
16e78db7 | 858 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
859 | dep->busy_slot = 1; |
860 | dep->free_slot = 1; | |
861 | } else { | |
862 | dep->busy_slot = 0; | |
863 | dep->free_slot = 0; | |
864 | } | |
865 | } | |
866 | ||
867 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 868 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 869 | return; |
72246da4 FB |
870 | |
871 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
872 | unsigned length; |
873 | dma_addr_t dma; | |
e5ba5ec8 | 874 | last_one = false; |
72246da4 | 875 | |
eeb720fb FB |
876 | if (req->request.num_mapped_sgs > 0) { |
877 | struct usb_request *request = &req->request; | |
878 | struct scatterlist *sg = request->sg; | |
879 | struct scatterlist *s; | |
880 | int i; | |
72246da4 | 881 | |
eeb720fb FB |
882 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
883 | unsigned chain = true; | |
72246da4 | 884 | |
eeb720fb FB |
885 | length = sg_dma_len(s); |
886 | dma = sg_dma_address(s); | |
72246da4 | 887 | |
1d046793 PZ |
888 | if (i == (request->num_mapped_sgs - 1) || |
889 | sg_is_last(s)) { | |
0f1f031c | 890 | if (list_empty(&dep->request_list)) |
e5ba5ec8 | 891 | last_one = true; |
eeb720fb FB |
892 | chain = false; |
893 | } | |
72246da4 | 894 | |
eeb720fb FB |
895 | trbs_left--; |
896 | if (!trbs_left) | |
897 | last_one = true; | |
72246da4 | 898 | |
eeb720fb FB |
899 | if (last_one) |
900 | chain = false; | |
72246da4 | 901 | |
eeb720fb | 902 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 903 | last_one, chain, i); |
72246da4 | 904 | |
eeb720fb FB |
905 | if (last_one) |
906 | break; | |
907 | } | |
72246da4 | 908 | } else { |
eeb720fb FB |
909 | dma = req->request.dma; |
910 | length = req->request.length; | |
911 | trbs_left--; | |
72246da4 | 912 | |
eeb720fb FB |
913 | if (!trbs_left) |
914 | last_one = 1; | |
879631aa | 915 | |
eeb720fb FB |
916 | /* Is this the last request? */ |
917 | if (list_is_last(&req->list, &dep->request_list)) | |
918 | last_one = 1; | |
72246da4 | 919 | |
eeb720fb | 920 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 921 | last_one, false, 0); |
72246da4 | 922 | |
eeb720fb FB |
923 | if (last_one) |
924 | break; | |
72246da4 | 925 | } |
72246da4 | 926 | } |
72246da4 FB |
927 | } |
928 | ||
929 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
930 | int start_new) | |
931 | { | |
932 | struct dwc3_gadget_ep_cmd_params params; | |
933 | struct dwc3_request *req; | |
934 | struct dwc3 *dwc = dep->dwc; | |
935 | int ret; | |
936 | u32 cmd; | |
937 | ||
938 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
939 | dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); | |
940 | return -EBUSY; | |
941 | } | |
942 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
943 | ||
944 | /* | |
945 | * If we are getting here after a short-out-packet we don't enqueue any | |
946 | * new requests as we try to set the IOC bit only on the last request. | |
947 | */ | |
948 | if (start_new) { | |
949 | if (list_empty(&dep->req_queued)) | |
950 | dwc3_prepare_trbs(dep, start_new); | |
951 | ||
952 | /* req points to the first request which will be sent */ | |
953 | req = next_request(&dep->req_queued); | |
954 | } else { | |
68e823e2 FB |
955 | dwc3_prepare_trbs(dep, start_new); |
956 | ||
72246da4 | 957 | /* |
1d046793 | 958 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 959 | */ |
68e823e2 | 960 | req = next_request(&dep->req_queued); |
72246da4 FB |
961 | } |
962 | if (!req) { | |
963 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
964 | return 0; | |
965 | } | |
966 | ||
967 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 968 | |
1877d6c9 PA |
969 | if (start_new) { |
970 | params.param0 = upper_32_bits(req->trb_dma); | |
971 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 972 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 973 | } else { |
72246da4 | 974 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 975 | } |
72246da4 FB |
976 | |
977 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
978 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
979 | if (ret < 0) { | |
980 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
981 | ||
982 | /* | |
983 | * FIXME we need to iterate over the list of requests | |
984 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 985 | * requests instead of what we do now. |
72246da4 | 986 | */ |
0fc9a1be FB |
987 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
988 | req->direction); | |
72246da4 FB |
989 | list_del(&req->list); |
990 | return ret; | |
991 | } | |
992 | ||
993 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 994 | |
f898ae09 | 995 | if (start_new) { |
b4996a86 | 996 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
f898ae09 | 997 | dep->number); |
b4996a86 | 998 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 999 | } |
25b8ff68 | 1000 | |
72246da4 FB |
1001 | return 0; |
1002 | } | |
1003 | ||
d6d6ec7b PA |
1004 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1005 | struct dwc3_ep *dep, u32 cur_uf) | |
1006 | { | |
1007 | u32 uf; | |
1008 | ||
1009 | if (list_empty(&dep->request_list)) { | |
1010 | dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", | |
1011 | dep->name); | |
f4a53c55 | 1012 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1013 | return; |
1014 | } | |
1015 | ||
1016 | /* 4 micro frames in the future */ | |
1017 | uf = cur_uf + dep->interval * 4; | |
1018 | ||
1019 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1020 | } | |
1021 | ||
1022 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1023 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1024 | { | |
1025 | u32 cur_uf, mask; | |
1026 | ||
1027 | mask = ~(dep->interval - 1); | |
1028 | cur_uf = event->parameters & mask; | |
1029 | ||
1030 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1031 | } | |
1032 | ||
72246da4 FB |
1033 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1034 | { | |
0fc9a1be FB |
1035 | struct dwc3 *dwc = dep->dwc; |
1036 | int ret; | |
1037 | ||
72246da4 FB |
1038 | req->request.actual = 0; |
1039 | req->request.status = -EINPROGRESS; | |
1040 | req->direction = dep->direction; | |
1041 | req->epnum = dep->number; | |
1042 | ||
1043 | /* | |
1044 | * We only add to our list of requests now and | |
1045 | * start consuming the list once we get XferNotReady | |
1046 | * IRQ. | |
1047 | * | |
1048 | * That way, we avoid doing anything that we don't need | |
1049 | * to do now and defer it until the point we receive a | |
1050 | * particular token from the Host side. | |
1051 | * | |
1052 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1053 | * many NAKs. |
72246da4 | 1054 | */ |
0fc9a1be FB |
1055 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1056 | dep->direction); | |
1057 | if (ret) | |
1058 | return ret; | |
1059 | ||
72246da4 FB |
1060 | list_add_tail(&req->list, &dep->request_list); |
1061 | ||
1062 | /* | |
b511e5e7 | 1063 | * There are a few special cases: |
72246da4 | 1064 | * |
f898ae09 PZ |
1065 | * 1. XferNotReady with empty list of requests. We need to kick the |
1066 | * transfer here in that situation, otherwise we will be NAKing | |
1067 | * forever. If we get XferNotReady before gadget driver has a | |
1068 | * chance to queue a request, we will ACK the IRQ but won't be | |
1069 | * able to receive the data until the next request is queued. | |
1070 | * The following code is handling exactly that. | |
72246da4 | 1071 | * |
72246da4 FB |
1072 | */ |
1073 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1074 | /* |
1075 | * If xfernotready is already elapsed and it is a case | |
1076 | * of isoc transfer, then issue END TRANSFER, so that | |
1077 | * you can receive xfernotready again and can have | |
1078 | * notion of current microframe. | |
1079 | */ | |
1080 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
cdc359dd PA |
1081 | if (list_empty(&dep->req_queued)) { |
1082 | dwc3_stop_active_transfer(dwc, dep->number); | |
1083 | dep->flags = DWC3_EP_ENABLED; | |
1084 | } | |
f4a53c55 PA |
1085 | return 0; |
1086 | } | |
1087 | ||
b511e5e7 | 1088 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
348e026f | 1089 | if (ret && ret != -EBUSY) |
b511e5e7 FB |
1090 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1091 | dep->name); | |
15f86bde | 1092 | return ret; |
b511e5e7 | 1093 | } |
72246da4 | 1094 | |
b511e5e7 FB |
1095 | /* |
1096 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1097 | * kick the transfer here after queuing a request, otherwise the | |
1098 | * core may not see the modified TRB(s). | |
1099 | */ | |
1100 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1101 | (dep->flags & DWC3_EP_BUSY) && |
1102 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 FB |
1103 | WARN_ON_ONCE(!dep->resource_index); |
1104 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, | |
b511e5e7 | 1105 | false); |
348e026f | 1106 | if (ret && ret != -EBUSY) |
72246da4 FB |
1107 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1108 | dep->name); | |
15f86bde | 1109 | return ret; |
a0925324 | 1110 | } |
72246da4 FB |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1116 | gfp_t gfp_flags) | |
1117 | { | |
1118 | struct dwc3_request *req = to_dwc3_request(request); | |
1119 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1120 | struct dwc3 *dwc = dep->dwc; | |
1121 | ||
1122 | unsigned long flags; | |
1123 | ||
1124 | int ret; | |
1125 | ||
16e78db7 | 1126 | if (!dep->endpoint.desc) { |
72246da4 FB |
1127 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
1128 | request, ep->name); | |
1129 | return -ESHUTDOWN; | |
1130 | } | |
1131 | ||
1132 | dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", | |
1133 | request, ep->name, request->length); | |
1134 | ||
1135 | spin_lock_irqsave(&dwc->lock, flags); | |
1136 | ret = __dwc3_gadget_ep_queue(dep, req); | |
1137 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1138 | ||
1139 | return ret; | |
1140 | } | |
1141 | ||
1142 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1143 | struct usb_request *request) | |
1144 | { | |
1145 | struct dwc3_request *req = to_dwc3_request(request); | |
1146 | struct dwc3_request *r = NULL; | |
1147 | ||
1148 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1149 | struct dwc3 *dwc = dep->dwc; | |
1150 | ||
1151 | unsigned long flags; | |
1152 | int ret = 0; | |
1153 | ||
1154 | spin_lock_irqsave(&dwc->lock, flags); | |
1155 | ||
1156 | list_for_each_entry(r, &dep->request_list, list) { | |
1157 | if (r == req) | |
1158 | break; | |
1159 | } | |
1160 | ||
1161 | if (r != req) { | |
1162 | list_for_each_entry(r, &dep->req_queued, list) { | |
1163 | if (r == req) | |
1164 | break; | |
1165 | } | |
1166 | if (r == req) { | |
1167 | /* wait until it is processed */ | |
1168 | dwc3_stop_active_transfer(dwc, dep->number); | |
e8d4e8be | 1169 | goto out1; |
72246da4 FB |
1170 | } |
1171 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1172 | request, ep->name); | |
1173 | ret = -EINVAL; | |
1174 | goto out0; | |
1175 | } | |
1176 | ||
e8d4e8be | 1177 | out1: |
72246da4 FB |
1178 | /* giveback the request */ |
1179 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1180 | ||
1181 | out0: | |
1182 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1183 | ||
1184 | return ret; | |
1185 | } | |
1186 | ||
55016b9e | 1187 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1188 | { |
1189 | struct dwc3_gadget_ep_cmd_params params; | |
1190 | struct dwc3 *dwc = dep->dwc; | |
1191 | int ret; | |
1192 | ||
1193 | memset(¶ms, 0x00, sizeof(params)); | |
1194 | ||
1195 | if (value) { | |
55016b9e FB |
1196 | if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) || |
1197 | (!list_empty(&dep->req_queued) || | |
1198 | !list_empty(&dep->request_list)))) { | |
1199 | dev_dbg(dwc->dev, "%s: pending request, cannot halt\n", | |
1200 | dep->name); | |
1201 | return -EAGAIN; | |
1202 | } | |
1203 | ||
72246da4 FB |
1204 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1205 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1206 | if (ret) | |
1207 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1208 | value ? "set" : "clear", | |
1209 | dep->name); | |
1210 | else | |
1211 | dep->flags |= DWC3_EP_STALL; | |
1212 | } else { | |
1213 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1214 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1215 | if (ret) | |
1216 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1217 | value ? "set" : "clear", | |
1218 | dep->name); | |
1219 | else | |
a535d81c | 1220 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1221 | } |
5275455a | 1222 | |
72246da4 FB |
1223 | return ret; |
1224 | } | |
1225 | ||
1226 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1227 | { | |
1228 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1229 | struct dwc3 *dwc = dep->dwc; | |
1230 | ||
1231 | unsigned long flags; | |
1232 | ||
1233 | int ret; | |
1234 | ||
1235 | spin_lock_irqsave(&dwc->lock, flags); | |
1236 | ||
16e78db7 | 1237 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1238 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); |
1239 | ret = -EINVAL; | |
1240 | goto out; | |
1241 | } | |
1242 | ||
55016b9e | 1243 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1244 | out: |
1245 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1246 | ||
1247 | return ret; | |
1248 | } | |
1249 | ||
1250 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1251 | { | |
1252 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1253 | struct dwc3 *dwc = dep->dwc; |
1254 | unsigned long flags; | |
72246da4 | 1255 | |
249a4569 | 1256 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1257 | dep->flags |= DWC3_EP_WEDGE; |
249a4569 | 1258 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 | 1259 | |
08f0d966 PA |
1260 | if (dep->number == 0 || dep->number == 1) |
1261 | return dwc3_gadget_ep0_set_halt(ep, 1); | |
1262 | else | |
55016b9e | 1263 | return __dwc3_gadget_ep_set_halt(dep, 1, false); |
72246da4 FB |
1264 | } |
1265 | ||
1266 | /* -------------------------------------------------------------------------- */ | |
1267 | ||
1268 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1269 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1270 | .bDescriptorType = USB_DT_ENDPOINT, | |
1271 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1272 | }; | |
1273 | ||
1274 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1275 | .enable = dwc3_gadget_ep0_enable, | |
1276 | .disable = dwc3_gadget_ep0_disable, | |
1277 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1278 | .free_request = dwc3_gadget_ep_free_request, | |
1279 | .queue = dwc3_gadget_ep0_queue, | |
1280 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1281 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1282 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1283 | }; | |
1284 | ||
1285 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1286 | .enable = dwc3_gadget_ep_enable, | |
1287 | .disable = dwc3_gadget_ep_disable, | |
1288 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1289 | .free_request = dwc3_gadget_ep_free_request, | |
1290 | .queue = dwc3_gadget_ep_queue, | |
1291 | .dequeue = dwc3_gadget_ep_dequeue, | |
1292 | .set_halt = dwc3_gadget_ep_set_halt, | |
1293 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1294 | }; | |
1295 | ||
1296 | /* -------------------------------------------------------------------------- */ | |
1297 | ||
1298 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1299 | { | |
1300 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1301 | u32 reg; | |
1302 | ||
1303 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1304 | return DWC3_DSTS_SOFFN(reg); | |
1305 | } | |
1306 | ||
1307 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1308 | { | |
1309 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1310 | ||
1311 | unsigned long timeout; | |
1312 | unsigned long flags; | |
1313 | ||
1314 | u32 reg; | |
1315 | ||
1316 | int ret = 0; | |
1317 | ||
1318 | u8 link_state; | |
1319 | u8 speed; | |
1320 | ||
1321 | spin_lock_irqsave(&dwc->lock, flags); | |
1322 | ||
1323 | /* | |
1324 | * According to the Databook Remote wakeup request should | |
1325 | * be issued only when the device is in early suspend state. | |
1326 | * | |
1327 | * We can check that via USB Link State bits in DSTS register. | |
1328 | */ | |
1329 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1330 | ||
1331 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1332 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
1333 | dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); | |
1334 | ret = -EINVAL; | |
1335 | goto out; | |
1336 | } | |
1337 | ||
1338 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1339 | ||
1340 | switch (link_state) { | |
1341 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1342 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1343 | break; | |
1344 | default: | |
1345 | dev_dbg(dwc->dev, "can't wakeup from link state %d\n", | |
1346 | link_state); | |
1347 | ret = -EINVAL; | |
1348 | goto out; | |
1349 | } | |
1350 | ||
8598bde7 FB |
1351 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1352 | if (ret < 0) { | |
1353 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1354 | goto out; | |
1355 | } | |
72246da4 | 1356 | |
802fde98 PZ |
1357 | /* Recent versions do this automatically */ |
1358 | if (dwc->revision < DWC3_REVISION_194A) { | |
1359 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1360 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1361 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1362 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1363 | } | |
72246da4 | 1364 | |
1d046793 | 1365 | /* poll until Link State changes to ON */ |
72246da4 FB |
1366 | timeout = jiffies + msecs_to_jiffies(100); |
1367 | ||
1d046793 | 1368 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1369 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1370 | ||
1371 | /* in HS, means ON */ | |
1372 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1373 | break; | |
1374 | } | |
1375 | ||
1376 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1377 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1378 | ret = -EINVAL; | |
1379 | } | |
1380 | ||
1381 | out: | |
1382 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1383 | ||
1384 | return ret; | |
1385 | } | |
1386 | ||
1387 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1388 | int is_selfpowered) | |
1389 | { | |
1390 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1391 | unsigned long flags; |
72246da4 | 1392 | |
249a4569 | 1393 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1394 | dwc->is_selfpowered = !!is_selfpowered; |
249a4569 | 1395 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1396 | |
1397 | return 0; | |
1398 | } | |
1399 | ||
6f17f74b | 1400 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) |
72246da4 FB |
1401 | { |
1402 | u32 reg; | |
61d58242 | 1403 | u32 timeout = 500; |
72246da4 FB |
1404 | |
1405 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1406 | if (is_on) { |
802fde98 PZ |
1407 | if (dwc->revision <= DWC3_REVISION_187A) { |
1408 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1409 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1410 | } | |
1411 | ||
1412 | if (dwc->revision >= DWC3_REVISION_194A) | |
1413 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1414 | reg |= DWC3_DCTL_RUN_STOP; | |
9fcb3bd8 | 1415 | dwc->pullups_connected = true; |
8db7ed15 | 1416 | } else { |
72246da4 | 1417 | reg &= ~DWC3_DCTL_RUN_STOP; |
9fcb3bd8 | 1418 | dwc->pullups_connected = false; |
8db7ed15 | 1419 | } |
72246da4 FB |
1420 | |
1421 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1422 | ||
1423 | do { | |
1424 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1425 | if (is_on) { | |
1426 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1427 | break; | |
1428 | } else { | |
1429 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1430 | break; | |
1431 | } | |
72246da4 FB |
1432 | timeout--; |
1433 | if (!timeout) | |
6f17f74b | 1434 | return -ETIMEDOUT; |
61d58242 | 1435 | udelay(1); |
72246da4 FB |
1436 | } while (1); |
1437 | ||
1438 | dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", | |
1439 | dwc->gadget_driver | |
1440 | ? dwc->gadget_driver->function : "no-function", | |
1441 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1442 | |
1443 | return 0; | |
72246da4 FB |
1444 | } |
1445 | ||
1446 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1447 | { | |
1448 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1449 | unsigned long flags; | |
6f17f74b | 1450 | int ret; |
72246da4 FB |
1451 | |
1452 | is_on = !!is_on; | |
1453 | ||
1454 | spin_lock_irqsave(&dwc->lock, flags); | |
6f17f74b | 1455 | ret = dwc3_gadget_run_stop(dwc, is_on); |
72246da4 FB |
1456 | spin_unlock_irqrestore(&dwc->lock, flags); |
1457 | ||
6f17f74b | 1458 | return ret; |
72246da4 FB |
1459 | } |
1460 | ||
8698e2ac FB |
1461 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1462 | { | |
1463 | u32 reg; | |
1464 | ||
1465 | /* Enable all but Start and End of Frame IRQs */ | |
1466 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1467 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1468 | DWC3_DEVTEN_CMDCMPLTEN | | |
1469 | DWC3_DEVTEN_ERRTICERREN | | |
1470 | DWC3_DEVTEN_WKUPEVTEN | | |
1471 | DWC3_DEVTEN_ULSTCNGEN | | |
1472 | DWC3_DEVTEN_CONNECTDONEEN | | |
1473 | DWC3_DEVTEN_USBRSTEN | | |
1474 | DWC3_DEVTEN_DISCONNEVTEN); | |
1475 | ||
1476 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1477 | } | |
1478 | ||
1479 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1480 | { | |
1481 | /* mask all interrupts */ | |
1482 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1483 | } | |
1484 | ||
1485 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1486 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1487 | |
72246da4 FB |
1488 | static int dwc3_gadget_start(struct usb_gadget *g, |
1489 | struct usb_gadget_driver *driver) | |
1490 | { | |
1491 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1492 | struct dwc3_ep *dep; | |
1493 | unsigned long flags; | |
1494 | int ret = 0; | |
8698e2ac | 1495 | int irq; |
72246da4 FB |
1496 | u32 reg; |
1497 | ||
b0d7ffd4 FB |
1498 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1499 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
e8adfc30 | 1500 | IRQF_SHARED, "dwc3", dwc); |
b0d7ffd4 FB |
1501 | if (ret) { |
1502 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1503 | irq, ret); | |
1504 | goto err0; | |
1505 | } | |
1506 | ||
72246da4 FB |
1507 | spin_lock_irqsave(&dwc->lock, flags); |
1508 | ||
1509 | if (dwc->gadget_driver) { | |
1510 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1511 | dwc->gadget.name, | |
1512 | dwc->gadget_driver->driver.name); | |
1513 | ret = -EBUSY; | |
b0d7ffd4 | 1514 | goto err1; |
72246da4 FB |
1515 | } |
1516 | ||
1517 | dwc->gadget_driver = driver; | |
72246da4 | 1518 | |
72246da4 FB |
1519 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1520 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1521 | |
1522 | /** | |
1523 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1524 | * which would cause metastability state on Run/Stop | |
1525 | * bit if we try to force the IP to USB2-only mode. | |
1526 | * | |
1527 | * Because of that, we cannot configure the IP to any | |
1528 | * speed other than the SuperSpeed | |
1529 | * | |
1530 | * Refers to: | |
1531 | * | |
1532 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1533 | * USB 2.0 Mode | |
1534 | */ | |
f7e846f0 | 1535 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1536 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1537 | } else { |
1538 | switch (dwc->maximum_speed) { | |
1539 | case USB_SPEED_LOW: | |
1540 | reg |= DWC3_DSTS_LOWSPEED; | |
1541 | break; | |
1542 | case USB_SPEED_FULL: | |
1543 | reg |= DWC3_DSTS_FULLSPEED1; | |
1544 | break; | |
1545 | case USB_SPEED_HIGH: | |
1546 | reg |= DWC3_DSTS_HIGHSPEED; | |
1547 | break; | |
1548 | case USB_SPEED_SUPER: /* FALLTHROUGH */ | |
1549 | case USB_SPEED_UNKNOWN: /* FALTHROUGH */ | |
1550 | default: | |
1551 | reg |= DWC3_DSTS_SUPERSPEED; | |
1552 | } | |
1553 | } | |
72246da4 FB |
1554 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1555 | ||
b23c8439 PZ |
1556 | dwc->start_config_issued = false; |
1557 | ||
72246da4 FB |
1558 | /* Start with SuperSpeed Default */ |
1559 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1560 | ||
1561 | dep = dwc->eps[0]; | |
4b345c9a | 1562 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); |
72246da4 FB |
1563 | if (ret) { |
1564 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1565 | goto err2; |
72246da4 FB |
1566 | } |
1567 | ||
1568 | dep = dwc->eps[1]; | |
4b345c9a | 1569 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); |
72246da4 FB |
1570 | if (ret) { |
1571 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1572 | goto err3; |
72246da4 FB |
1573 | } |
1574 | ||
1575 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1576 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1577 | dwc3_ep0_out_start(dwc); |
1578 | ||
8698e2ac FB |
1579 | dwc3_gadget_enable_irq(dwc); |
1580 | ||
72246da4 FB |
1581 | spin_unlock_irqrestore(&dwc->lock, flags); |
1582 | ||
1583 | return 0; | |
1584 | ||
b0d7ffd4 | 1585 | err3: |
72246da4 FB |
1586 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1587 | ||
b0d7ffd4 | 1588 | err2: |
cdcedd69 | 1589 | dwc->gadget_driver = NULL; |
b0d7ffd4 FB |
1590 | |
1591 | err1: | |
72246da4 FB |
1592 | spin_unlock_irqrestore(&dwc->lock, flags); |
1593 | ||
b0d7ffd4 FB |
1594 | free_irq(irq, dwc); |
1595 | ||
1596 | err0: | |
72246da4 FB |
1597 | return ret; |
1598 | } | |
1599 | ||
1600 | static int dwc3_gadget_stop(struct usb_gadget *g, | |
1601 | struct usb_gadget_driver *driver) | |
1602 | { | |
1603 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1604 | unsigned long flags; | |
8698e2ac | 1605 | int irq; |
72246da4 FB |
1606 | |
1607 | spin_lock_irqsave(&dwc->lock, flags); | |
1608 | ||
8698e2ac | 1609 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1610 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1611 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1612 | ||
1613 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1614 | |
1615 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1616 | ||
b0d7ffd4 FB |
1617 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1618 | free_irq(irq, dwc); | |
1619 | ||
72246da4 FB |
1620 | return 0; |
1621 | } | |
802fde98 | 1622 | |
72246da4 FB |
1623 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1624 | .get_frame = dwc3_gadget_get_frame, | |
1625 | .wakeup = dwc3_gadget_wakeup, | |
1626 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1627 | .pullup = dwc3_gadget_pullup, | |
1628 | .udc_start = dwc3_gadget_start, | |
1629 | .udc_stop = dwc3_gadget_stop, | |
1630 | }; | |
1631 | ||
1632 | /* -------------------------------------------------------------------------- */ | |
1633 | ||
6a1e3ef4 FB |
1634 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1635 | u8 num, u32 direction) | |
72246da4 FB |
1636 | { |
1637 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1638 | u8 i; |
72246da4 | 1639 | |
6a1e3ef4 FB |
1640 | for (i = 0; i < num; i++) { |
1641 | u8 epnum = (i << 1) | (!!direction); | |
72246da4 | 1642 | |
72246da4 FB |
1643 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
1644 | if (!dep) { | |
1645 | dev_err(dwc->dev, "can't allocate endpoint %d\n", | |
1646 | epnum); | |
1647 | return -ENOMEM; | |
1648 | } | |
1649 | ||
1650 | dep->dwc = dwc; | |
1651 | dep->number = epnum; | |
9aa62ae4 | 1652 | dep->direction = !!direction; |
72246da4 FB |
1653 | dwc->eps[epnum] = dep; |
1654 | ||
1655 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1656 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1657 | |
72246da4 | 1658 | dep->endpoint.name = dep->name; |
72246da4 | 1659 | |
653df35e FB |
1660 | dev_vdbg(dwc->dev, "initializing %s\n", dep->name); |
1661 | ||
72246da4 | 1662 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1663 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1664 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1665 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1666 | if (!epnum) | |
1667 | dwc->gadget.ep0 = &dep->endpoint; | |
1668 | } else { | |
1669 | int ret; | |
1670 | ||
e117e742 | 1671 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1672 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1673 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1674 | list_add_tail(&dep->endpoint.ep_list, | |
1675 | &dwc->gadget.ep_list); | |
1676 | ||
1677 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1678 | if (ret) |
72246da4 | 1679 | return ret; |
72246da4 | 1680 | } |
25b8ff68 | 1681 | |
72246da4 FB |
1682 | INIT_LIST_HEAD(&dep->request_list); |
1683 | INIT_LIST_HEAD(&dep->req_queued); | |
1684 | } | |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
6a1e3ef4 FB |
1689 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1690 | { | |
1691 | int ret; | |
1692 | ||
1693 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1694 | ||
1695 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1696 | if (ret < 0) { | |
1697 | dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); | |
1698 | return ret; | |
1699 | } | |
1700 | ||
1701 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1702 | if (ret < 0) { | |
1703 | dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); | |
1704 | return ret; | |
1705 | } | |
1706 | ||
1707 | return 0; | |
1708 | } | |
1709 | ||
72246da4 FB |
1710 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1711 | { | |
1712 | struct dwc3_ep *dep; | |
1713 | u8 epnum; | |
1714 | ||
1715 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1716 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1717 | if (!dep) |
1718 | continue; | |
5bf8fae3 GC |
1719 | /* |
1720 | * Physical endpoints 0 and 1 are special; they form the | |
1721 | * bi-directional USB endpoint 0. | |
1722 | * | |
1723 | * For those two physical endpoints, we don't allocate a TRB | |
1724 | * pool nor do we add them the endpoints list. Due to that, we | |
1725 | * shouldn't do these two operations otherwise we would end up | |
1726 | * with all sorts of bugs when removing dwc3.ko. | |
1727 | */ | |
1728 | if (epnum != 0 && epnum != 1) { | |
1729 | dwc3_free_trb_pool(dep); | |
72246da4 | 1730 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1731 | } |
72246da4 FB |
1732 | |
1733 | kfree(dep); | |
1734 | } | |
1735 | } | |
1736 | ||
72246da4 | 1737 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1738 | |
e5ba5ec8 PA |
1739 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1740 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1741 | const struct dwc3_event_depevt *event, int status) |
1742 | { | |
72246da4 FB |
1743 | unsigned int count; |
1744 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1745 | unsigned int trb_status; |
72246da4 | 1746 | |
e5ba5ec8 PA |
1747 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1748 | /* | |
1749 | * We continue despite the error. There is not much we | |
1750 | * can do. If we don't clean it up we loop forever. If | |
1751 | * we skip the TRB then it gets overwritten after a | |
1752 | * while since we use them in a ring buffer. A BUG() | |
1753 | * would help. Lets hope that if this occurs, someone | |
1754 | * fixes the root cause instead of looking away :) | |
1755 | */ | |
1756 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1757 | dep->name, trb); | |
1758 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1759 | ||
1760 | if (dep->direction) { | |
1761 | if (count) { | |
1762 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1763 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
1764 | dev_dbg(dwc->dev, "incomplete IN transfer %s\n", | |
1765 | dep->name); | |
1766 | /* | |
1767 | * If missed isoc occurred and there is | |
1768 | * no request queued then issue END | |
1769 | * TRANSFER, so that core generates | |
1770 | * next xfernotready and we will issue | |
1771 | * a fresh START TRANSFER. | |
1772 | * If there are still queued request | |
1773 | * then wait, do not issue either END | |
1774 | * or UPDATE TRANSFER, just attach next | |
1775 | * request in request_list during | |
1776 | * giveback.If any future queued request | |
1777 | * is successfully transferred then we | |
1778 | * will issue UPDATE TRANSFER for all | |
1779 | * request in the request_list. | |
1780 | */ | |
1781 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1782 | } else { | |
1783 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1784 | dep->name); | |
1785 | status = -ECONNRESET; | |
1786 | } | |
1787 | } else { | |
1788 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1789 | } | |
1790 | } else { | |
1791 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1792 | s_pkt = 1; | |
1793 | } | |
1794 | ||
1795 | /* | |
1796 | * We assume here we will always receive the entire data block | |
1797 | * which we should receive. Meaning, if we program RX to | |
1798 | * receive 4K but we receive only 2K, we assume that's all we | |
1799 | * should receive and we simply bounce the request back to the | |
1800 | * gadget driver for further processing. | |
1801 | */ | |
1802 | req->request.actual += req->request.length - count; | |
1803 | if (s_pkt) | |
1804 | return 1; | |
1805 | if ((event->status & DEPEVT_STATUS_LST) && | |
1806 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1807 | DWC3_TRB_CTRL_HWO))) | |
1808 | return 1; | |
1809 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1810 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1811 | return 1; | |
1812 | return 0; | |
1813 | } | |
1814 | ||
1815 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1816 | const struct dwc3_event_depevt *event, int status) | |
1817 | { | |
1818 | struct dwc3_request *req; | |
1819 | struct dwc3_trb *trb; | |
1820 | unsigned int slot; | |
1821 | unsigned int i; | |
1822 | int ret; | |
1823 | ||
72246da4 FB |
1824 | do { |
1825 | req = next_request(&dep->req_queued); | |
d39ee7be SAS |
1826 | if (!req) { |
1827 | WARN_ON_ONCE(1); | |
1828 | return 1; | |
1829 | } | |
e5ba5ec8 PA |
1830 | i = 0; |
1831 | do { | |
1832 | slot = req->start_slot + i; | |
1833 | if ((slot == DWC3_TRB_NUM - 1) && | |
1834 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
1835 | slot++; | |
1836 | slot %= DWC3_TRB_NUM; | |
1837 | trb = &dep->trb_pool[slot]; | |
72246da4 | 1838 | |
e5ba5ec8 PA |
1839 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
1840 | event, status); | |
1841 | if (ret) | |
1842 | break; | |
1843 | }while (++i < req->request.num_mapped_sgs); | |
72246da4 | 1844 | |
72246da4 | 1845 | dwc3_gadget_giveback(dep, req, status); |
e5ba5ec8 PA |
1846 | |
1847 | if (ret) | |
72246da4 FB |
1848 | break; |
1849 | } while (1); | |
1850 | ||
cdc359dd PA |
1851 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
1852 | list_empty(&dep->req_queued)) { | |
1853 | if (list_empty(&dep->request_list)) { | |
1854 | /* | |
1855 | * If there is no entry in request list then do | |
1856 | * not issue END TRANSFER now. Just set PENDING | |
1857 | * flag, so that END TRANSFER is issued when an | |
1858 | * entry is added into request list. | |
1859 | */ | |
1860 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
1861 | } else { | |
1862 | dwc3_stop_active_transfer(dwc, dep->number); | |
1863 | dep->flags = DWC3_EP_ENABLED; | |
1864 | } | |
7efea86c PA |
1865 | return 1; |
1866 | } | |
1867 | ||
f6bafc6a FB |
1868 | if ((event->status & DEPEVT_STATUS_IOC) && |
1869 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
72246da4 FB |
1870 | return 0; |
1871 | return 1; | |
1872 | } | |
1873 | ||
1874 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
1875 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event, | |
1876 | int start_new) | |
1877 | { | |
1878 | unsigned status = 0; | |
1879 | int clean_busy; | |
1880 | ||
1881 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1882 | status = -ECONNRESET; | |
1883 | ||
1d046793 | 1884 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
c2df85ca | 1885 | if (clean_busy) |
72246da4 | 1886 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1887 | |
1888 | /* | |
1889 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1890 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1891 | */ | |
1892 | if (dwc->revision < DWC3_REVISION_183A) { | |
1893 | u32 reg; | |
1894 | int i; | |
1895 | ||
1896 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 1897 | dep = dwc->eps[i]; |
fae2b904 FB |
1898 | |
1899 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1900 | continue; | |
1901 | ||
1902 | if (!list_empty(&dep->req_queued)) | |
1903 | return; | |
1904 | } | |
1905 | ||
1906 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1907 | reg |= dwc->u1u2; | |
1908 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1909 | ||
1910 | dwc->u1u2 = 0; | |
1911 | } | |
72246da4 FB |
1912 | } |
1913 | ||
72246da4 FB |
1914 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
1915 | const struct dwc3_event_depevt *event) | |
1916 | { | |
1917 | struct dwc3_ep *dep; | |
1918 | u8 epnum = event->endpoint_number; | |
1919 | ||
1920 | dep = dwc->eps[epnum]; | |
1921 | ||
3336abb5 FB |
1922 | if (!(dep->flags & DWC3_EP_ENABLED)) |
1923 | return; | |
1924 | ||
72246da4 FB |
1925 | dev_vdbg(dwc->dev, "%s: %s\n", dep->name, |
1926 | dwc3_ep_event_string(event->endpoint_event)); | |
1927 | ||
1928 | if (epnum == 0 || epnum == 1) { | |
1929 | dwc3_ep0_interrupt(dwc, event); | |
1930 | return; | |
1931 | } | |
1932 | ||
1933 | switch (event->endpoint_event) { | |
1934 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 1935 | dep->resource_index = 0; |
c2df85ca | 1936 | |
16e78db7 | 1937 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1938 | dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", |
1939 | dep->name); | |
1940 | return; | |
1941 | } | |
1942 | ||
1943 | dwc3_endpoint_transfer_complete(dwc, dep, event, 1); | |
1944 | break; | |
1945 | case DWC3_DEPEVT_XFERINPROGRESS: | |
16e78db7 | 1946 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1947 | dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", |
1948 | dep->name); | |
1949 | return; | |
1950 | } | |
1951 | ||
1952 | dwc3_endpoint_transfer_complete(dwc, dep, event, 0); | |
1953 | break; | |
1954 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 1955 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1956 | dwc3_gadget_start_isoc(dwc, dep, event); |
1957 | } else { | |
1958 | int ret; | |
1959 | ||
1960 | dev_vdbg(dwc->dev, "%s: reason %s\n", | |
40aa41fb FB |
1961 | dep->name, event->status & |
1962 | DEPEVT_STATUS_TRANSFER_ACTIVE | |
72246da4 FB |
1963 | ? "Transfer Active" |
1964 | : "Transfer Not Active"); | |
1965 | ||
1966 | ret = __dwc3_gadget_kick_transfer(dep, 0, 1); | |
1967 | if (!ret || ret == -EBUSY) | |
1968 | return; | |
1969 | ||
1970 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1971 | dep->name); | |
1972 | } | |
1973 | ||
879631aa FB |
1974 | break; |
1975 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 1976 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
1977 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
1978 | dep->name); | |
1979 | return; | |
1980 | } | |
1981 | ||
1982 | switch (event->status) { | |
1983 | case DEPEVT_STREAMEVT_FOUND: | |
1984 | dev_vdbg(dwc->dev, "Stream %d found and started\n", | |
1985 | event->parameters); | |
1986 | ||
1987 | break; | |
1988 | case DEPEVT_STREAMEVT_NOTFOUND: | |
1989 | /* FALLTHROUGH */ | |
1990 | default: | |
1991 | dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); | |
1992 | } | |
72246da4 FB |
1993 | break; |
1994 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1995 | dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); | |
1996 | break; | |
72246da4 | 1997 | case DWC3_DEPEVT_EPCMDCMPLT: |
ea53b882 | 1998 | dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); |
72246da4 FB |
1999 | break; |
2000 | } | |
2001 | } | |
2002 | ||
2003 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2004 | { | |
2005 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2006 | spin_unlock(&dwc->lock); | |
2007 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2008 | spin_lock(&dwc->lock); | |
2009 | } | |
2010 | } | |
2011 | ||
2012 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) | |
2013 | { | |
2014 | struct dwc3_ep *dep; | |
2015 | struct dwc3_gadget_ep_cmd_params params; | |
2016 | u32 cmd; | |
2017 | int ret; | |
2018 | ||
2019 | dep = dwc->eps[epnum]; | |
2020 | ||
b4996a86 | 2021 | if (!dep->resource_index) |
3daf74d7 PA |
2022 | return; |
2023 | ||
57911504 PA |
2024 | /* |
2025 | * NOTICE: We are violating what the Databook says about the | |
2026 | * EndTransfer command. Ideally we would _always_ wait for the | |
2027 | * EndTransfer Command Completion IRQ, but that's causing too | |
2028 | * much trouble synchronizing between us and gadget driver. | |
2029 | * | |
2030 | * We have discussed this with the IP Provider and it was | |
2031 | * suggested to giveback all requests here, but give HW some | |
2032 | * extra time to synchronize with the interconnect. We're using | |
2033 | * an arbitraty 100us delay for that. | |
2034 | * | |
2035 | * Note also that a similar handling was tested by Synopsys | |
2036 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2037 | * In short, what we're doing is: | |
2038 | * | |
2039 | * - Issue EndTransfer WITH CMDIOC bit set | |
2040 | * - Wait 100us | |
2041 | */ | |
2042 | ||
3daf74d7 PA |
2043 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
2044 | cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2045 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 PA |
2046 | memset(¶ms, 0, sizeof(params)); |
2047 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
2048 | WARN_ON_ONCE(ret); | |
b4996a86 | 2049 | dep->resource_index = 0; |
041d81f4 | 2050 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2051 | udelay(100); |
72246da4 FB |
2052 | } |
2053 | ||
2054 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2055 | { | |
2056 | u32 epnum; | |
2057 | ||
2058 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2059 | struct dwc3_ep *dep; | |
2060 | ||
2061 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2062 | if (!dep) |
2063 | continue; | |
2064 | ||
72246da4 FB |
2065 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2066 | continue; | |
2067 | ||
624407f9 | 2068 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2069 | } |
2070 | } | |
2071 | ||
2072 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2073 | { | |
2074 | u32 epnum; | |
2075 | ||
2076 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2077 | struct dwc3_ep *dep; | |
2078 | struct dwc3_gadget_ep_cmd_params params; | |
2079 | int ret; | |
2080 | ||
2081 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2082 | if (!dep) |
2083 | continue; | |
72246da4 FB |
2084 | |
2085 | if (!(dep->flags & DWC3_EP_STALL)) | |
2086 | continue; | |
2087 | ||
2088 | dep->flags &= ~DWC3_EP_STALL; | |
2089 | ||
2090 | memset(¶ms, 0, sizeof(params)); | |
2091 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
2092 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
2093 | WARN_ON_ONCE(ret); | |
2094 | } | |
2095 | } | |
2096 | ||
2097 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2098 | { | |
c4430a26 FB |
2099 | int reg; |
2100 | ||
72246da4 | 2101 | dev_vdbg(dwc->dev, "%s\n", __func__); |
72246da4 FB |
2102 | |
2103 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2104 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2105 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2106 | ||
2107 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2108 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2109 | |
72246da4 | 2110 | dwc3_disconnect_gadget(dwc); |
b23c8439 | 2111 | dwc->start_config_issued = false; |
72246da4 FB |
2112 | |
2113 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2114 | dwc->setup_packet_pending = false; |
72246da4 FB |
2115 | } |
2116 | ||
72246da4 FB |
2117 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2118 | { | |
2119 | u32 reg; | |
2120 | ||
2121 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2122 | ||
df62df56 FB |
2123 | /* |
2124 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2125 | * would cause a missing Disconnect Event if there's a | |
2126 | * pending Setup Packet in the FIFO. | |
2127 | * | |
2128 | * There's no suggested workaround on the official Bug | |
2129 | * report, which states that "unless the driver/application | |
2130 | * is doing any special handling of a disconnect event, | |
2131 | * there is no functional issue". | |
2132 | * | |
2133 | * Unfortunately, it turns out that we _do_ some special | |
2134 | * handling of a disconnect event, namely complete all | |
2135 | * pending transfers, notify gadget driver of the | |
2136 | * disconnection, and so on. | |
2137 | * | |
2138 | * Our suggested workaround is to follow the Disconnect | |
2139 | * Event steps here, instead, based on a setup_packet_pending | |
2140 | * flag. Such flag gets set whenever we have a XferNotReady | |
2141 | * event on EP0 and gets cleared on XferComplete for the | |
2142 | * same endpoint. | |
2143 | * | |
2144 | * Refers to: | |
2145 | * | |
2146 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2147 | * generated if setup packet pending in FIFO | |
2148 | */ | |
2149 | if (dwc->revision < DWC3_REVISION_188A) { | |
2150 | if (dwc->setup_packet_pending) | |
2151 | dwc3_gadget_disconnect_interrupt(dwc); | |
2152 | } | |
2153 | ||
961906ed | 2154 | /* after reset -> Default State */ |
14cd592f | 2155 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
961906ed | 2156 | |
72246da4 FB |
2157 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) |
2158 | dwc3_disconnect_gadget(dwc); | |
2159 | ||
2160 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2161 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2162 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2163 | dwc->test_mode = false; |
72246da4 FB |
2164 | |
2165 | dwc3_stop_active_transfers(dwc); | |
2166 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 2167 | dwc->start_config_issued = false; |
72246da4 FB |
2168 | |
2169 | /* Reset device address to zero */ | |
2170 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2171 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2172 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2173 | } |
2174 | ||
2175 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2176 | { | |
2177 | u32 reg; | |
2178 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2179 | ||
2180 | /* | |
2181 | * We change the clock only at SS but I dunno why I would want to do | |
2182 | * this. Maybe it becomes part of the power saving plan. | |
2183 | */ | |
2184 | ||
2185 | if (speed != DWC3_DSTS_SUPERSPEED) | |
2186 | return; | |
2187 | ||
2188 | /* | |
2189 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2190 | * each time on Connect Done. | |
2191 | */ | |
2192 | if (!usb30_clock) | |
2193 | return; | |
2194 | ||
2195 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2196 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2197 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2198 | } | |
2199 | ||
72246da4 FB |
2200 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2201 | { | |
72246da4 FB |
2202 | struct dwc3_ep *dep; |
2203 | int ret; | |
2204 | u32 reg; | |
2205 | u8 speed; | |
2206 | ||
2207 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2208 | ||
72246da4 FB |
2209 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2210 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2211 | dwc->speed = speed; | |
2212 | ||
2213 | dwc3_update_ram_clk_sel(dwc, speed); | |
2214 | ||
2215 | switch (speed) { | |
2216 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2217 | /* |
2218 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2219 | * would cause a missing USB3 Reset event. | |
2220 | * | |
2221 | * In such situations, we should force a USB3 Reset | |
2222 | * event by calling our dwc3_gadget_reset_interrupt() | |
2223 | * routine. | |
2224 | * | |
2225 | * Refers to: | |
2226 | * | |
2227 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2228 | * not be generated always when the link enters poll | |
2229 | */ | |
2230 | if (dwc->revision < DWC3_REVISION_190A) | |
2231 | dwc3_gadget_reset_interrupt(dwc); | |
2232 | ||
72246da4 FB |
2233 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2234 | dwc->gadget.ep0->maxpacket = 512; | |
2235 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2236 | break; | |
2237 | case DWC3_DCFG_HIGHSPEED: | |
2238 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2239 | dwc->gadget.ep0->maxpacket = 64; | |
2240 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2241 | break; | |
2242 | case DWC3_DCFG_FULLSPEED2: | |
2243 | case DWC3_DCFG_FULLSPEED1: | |
2244 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2245 | dwc->gadget.ep0->maxpacket = 64; | |
2246 | dwc->gadget.speed = USB_SPEED_FULL; | |
2247 | break; | |
2248 | case DWC3_DCFG_LOWSPEED: | |
2249 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2250 | dwc->gadget.ep0->maxpacket = 8; | |
2251 | dwc->gadget.speed = USB_SPEED_LOW; | |
2252 | break; | |
2253 | } | |
2254 | ||
2b758350 PA |
2255 | /* Enable USB2 LPM Capability */ |
2256 | ||
2257 | if ((dwc->revision > DWC3_REVISION_194A) | |
2258 | && (speed != DWC3_DCFG_SUPERSPEED)) { | |
2259 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2260 | reg |= DWC3_DCFG_LPM_CAP; | |
2261 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2262 | ||
2263 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2264 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2265 | ||
1a947746 FB |
2266 | /* |
2267 | * TODO: This should be configurable. For now using | |
2268 | * maximum allowed HIRD threshold value of 0b1100 | |
2269 | */ | |
2270 | reg |= DWC3_DCTL_HIRD_THRES(12); | |
2b758350 PA |
2271 | |
2272 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2273 | } | |
2274 | ||
72246da4 | 2275 | dep = dwc->eps[0]; |
4b345c9a | 2276 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); |
72246da4 FB |
2277 | if (ret) { |
2278 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2279 | return; | |
2280 | } | |
2281 | ||
2282 | dep = dwc->eps[1]; | |
4b345c9a | 2283 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); |
72246da4 FB |
2284 | if (ret) { |
2285 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2286 | return; | |
2287 | } | |
2288 | ||
2289 | /* | |
2290 | * Configure PHY via GUSB3PIPECTLn if required. | |
2291 | * | |
2292 | * Update GTXFIFOSIZn | |
2293 | * | |
2294 | * In both cases reset values should be sufficient. | |
2295 | */ | |
2296 | } | |
2297 | ||
2298 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2299 | { | |
2300 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2301 | ||
2302 | /* | |
2303 | * TODO take core out of low power mode when that's | |
2304 | * implemented. | |
2305 | */ | |
2306 | ||
2307 | dwc->gadget_driver->resume(&dwc->gadget); | |
2308 | } | |
2309 | ||
2310 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2311 | unsigned int evtinfo) | |
2312 | { | |
fae2b904 | 2313 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2314 | unsigned int pwropt; |
2315 | ||
2316 | /* | |
2317 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2318 | * Hibernation mode enabled which would show up when device detects | |
2319 | * host-initiated U3 exit. | |
2320 | * | |
2321 | * In that case, device will generate a Link State Change Interrupt | |
2322 | * from U3 to RESUME which is only necessary if Hibernation is | |
2323 | * configured in. | |
2324 | * | |
2325 | * There are no functional changes due to such spurious event and we | |
2326 | * just need to ignore it. | |
2327 | * | |
2328 | * Refers to: | |
2329 | * | |
2330 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2331 | * operational mode | |
2332 | */ | |
2333 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2334 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2335 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2336 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2337 | (next == DWC3_LINK_STATE_RESUME)) { | |
2338 | dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); | |
2339 | return; | |
2340 | } | |
2341 | } | |
fae2b904 FB |
2342 | |
2343 | /* | |
2344 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2345 | * on the link partner, the USB session might do multiple entry/exit | |
2346 | * of low power states before a transfer takes place. | |
2347 | * | |
2348 | * Due to this problem, we might experience lower throughput. The | |
2349 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2350 | * transitioning from U1/U2 to U0 and enable those bits again | |
2351 | * after a transfer completes and there are no pending transfers | |
2352 | * on any of the enabled endpoints. | |
2353 | * | |
2354 | * This is the first half of that workaround. | |
2355 | * | |
2356 | * Refers to: | |
2357 | * | |
2358 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2359 | * core send LGO_Ux entering U0 | |
2360 | */ | |
2361 | if (dwc->revision < DWC3_REVISION_183A) { | |
2362 | if (next == DWC3_LINK_STATE_U0) { | |
2363 | u32 u1u2; | |
2364 | u32 reg; | |
2365 | ||
2366 | switch (dwc->link_state) { | |
2367 | case DWC3_LINK_STATE_U1: | |
2368 | case DWC3_LINK_STATE_U2: | |
2369 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2370 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2371 | | DWC3_DCTL_ACCEPTU2ENA | |
2372 | | DWC3_DCTL_INITU1ENA | |
2373 | | DWC3_DCTL_ACCEPTU1ENA); | |
2374 | ||
2375 | if (!dwc->u1u2) | |
2376 | dwc->u1u2 = reg & u1u2; | |
2377 | ||
2378 | reg &= ~u1u2; | |
2379 | ||
2380 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2381 | break; | |
2382 | default: | |
2383 | /* do nothing */ | |
2384 | break; | |
2385 | } | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | dwc->link_state = next; | |
019ac832 FB |
2390 | |
2391 | dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); | |
72246da4 FB |
2392 | } |
2393 | ||
2394 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, | |
2395 | const struct dwc3_event_devt *event) | |
2396 | { | |
2397 | switch (event->type) { | |
2398 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2399 | dwc3_gadget_disconnect_interrupt(dwc); | |
2400 | break; | |
2401 | case DWC3_DEVICE_EVENT_RESET: | |
2402 | dwc3_gadget_reset_interrupt(dwc); | |
2403 | break; | |
2404 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2405 | dwc3_gadget_conndone_interrupt(dwc); | |
2406 | break; | |
2407 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2408 | dwc3_gadget_wakeup_interrupt(dwc); | |
2409 | break; | |
2410 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: | |
2411 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2412 | break; | |
2413 | case DWC3_DEVICE_EVENT_EOPF: | |
2414 | dev_vdbg(dwc->dev, "End of Periodic Frame\n"); | |
2415 | break; | |
2416 | case DWC3_DEVICE_EVENT_SOF: | |
2417 | dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); | |
2418 | break; | |
2419 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
2420 | dev_vdbg(dwc->dev, "Erratic Error\n"); | |
2421 | break; | |
2422 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
2423 | dev_vdbg(dwc->dev, "Command Complete\n"); | |
2424 | break; | |
2425 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
2426 | dev_vdbg(dwc->dev, "Overflow\n"); | |
2427 | break; | |
2428 | default: | |
2429 | dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); | |
2430 | } | |
2431 | } | |
2432 | ||
2433 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2434 | const union dwc3_event *event) | |
2435 | { | |
2436 | /* Endpoint IRQ, handle it and return early */ | |
2437 | if (event->type.is_devspec == 0) { | |
2438 | /* depevt */ | |
2439 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2440 | } | |
2441 | ||
2442 | switch (event->type.type) { | |
2443 | case DWC3_EVENT_TYPE_DEV: | |
2444 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2445 | break; | |
2446 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2447 | default: | |
2448 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2449 | } | |
2450 | } | |
2451 | ||
f42f2447 | 2452 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) |
b15a762f | 2453 | { |
f42f2447 | 2454 | struct dwc3_event_buffer *evt; |
b15a762f | 2455 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2456 | int left; |
e8adfc30 | 2457 | u32 reg; |
b15a762f | 2458 | |
f42f2447 FB |
2459 | evt = dwc->ev_buffs[buf]; |
2460 | left = evt->count; | |
b15a762f | 2461 | |
f42f2447 FB |
2462 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2463 | return IRQ_NONE; | |
b15a762f | 2464 | |
f42f2447 FB |
2465 | while (left > 0) { |
2466 | union dwc3_event event; | |
b15a762f | 2467 | |
f42f2447 | 2468 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2469 | |
f42f2447 | 2470 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2471 | |
f42f2447 FB |
2472 | /* |
2473 | * FIXME we wrap around correctly to the next entry as | |
2474 | * almost all entries are 4 bytes in size. There is one | |
2475 | * entry which has 12 bytes which is a regular entry | |
2476 | * followed by 8 bytes data. ATM I don't know how | |
2477 | * things are organized if we get next to the a | |
2478 | * boundary so I worry about that once we try to handle | |
2479 | * that. | |
2480 | */ | |
2481 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2482 | left -= 4; | |
b15a762f | 2483 | |
f42f2447 FB |
2484 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); |
2485 | } | |
b15a762f | 2486 | |
f42f2447 FB |
2487 | evt->count = 0; |
2488 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2489 | ret = IRQ_HANDLED; | |
b15a762f | 2490 | |
f42f2447 FB |
2491 | /* Unmask interrupt */ |
2492 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2493 | reg &= ~DWC3_GEVNTSIZ_INTMASK; | |
2494 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
b15a762f | 2495 | |
f42f2447 FB |
2496 | return ret; |
2497 | } | |
e8adfc30 | 2498 | |
f42f2447 FB |
2499 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) |
2500 | { | |
2501 | struct dwc3 *dwc = _dwc; | |
2502 | unsigned long flags; | |
2503 | irqreturn_t ret = IRQ_NONE; | |
2504 | int i; | |
2505 | ||
2506 | spin_lock_irqsave(&dwc->lock, flags); | |
2507 | ||
2508 | for (i = 0; i < dwc->num_event_buffers; i++) | |
2509 | ret |= dwc3_process_event_buf(dwc, i); | |
b15a762f FB |
2510 | |
2511 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2512 | ||
2513 | return ret; | |
2514 | } | |
2515 | ||
7f97aa98 | 2516 | static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) |
72246da4 FB |
2517 | { |
2518 | struct dwc3_event_buffer *evt; | |
72246da4 | 2519 | u32 count; |
e8adfc30 | 2520 | u32 reg; |
72246da4 | 2521 | |
b15a762f FB |
2522 | evt = dwc->ev_buffs[buf]; |
2523 | ||
72246da4 FB |
2524 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); |
2525 | count &= DWC3_GEVNTCOUNT_MASK; | |
2526 | if (!count) | |
2527 | return IRQ_NONE; | |
2528 | ||
b15a762f FB |
2529 | evt->count = count; |
2530 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2531 | |
e8adfc30 FB |
2532 | /* Mask interrupt */ |
2533 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2534 | reg |= DWC3_GEVNTSIZ_INTMASK; | |
2535 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
2536 | ||
b15a762f | 2537 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2538 | } |
2539 | ||
2540 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2541 | { | |
2542 | struct dwc3 *dwc = _dwc; | |
2543 | int i; | |
2544 | irqreturn_t ret = IRQ_NONE; | |
2545 | ||
2546 | spin_lock(&dwc->lock); | |
2547 | ||
9f622b2a | 2548 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2549 | irqreturn_t status; |
2550 | ||
7f97aa98 | 2551 | status = dwc3_check_event_buf(dwc, i); |
b15a762f | 2552 | if (status == IRQ_WAKE_THREAD) |
72246da4 FB |
2553 | ret = status; |
2554 | } | |
2555 | ||
2556 | spin_unlock(&dwc->lock); | |
2557 | ||
2558 | return ret; | |
2559 | } | |
2560 | ||
2561 | /** | |
2562 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2563 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2564 | * |
2565 | * Returns 0 on success otherwise negative errno. | |
2566 | */ | |
41ac7b3a | 2567 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2568 | { |
72246da4 | 2569 | int ret; |
72246da4 FB |
2570 | |
2571 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2572 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2573 | if (!dwc->ctrl_req) { | |
2574 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2575 | ret = -ENOMEM; | |
2576 | goto err0; | |
2577 | } | |
2578 | ||
2579 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2580 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
2581 | if (!dwc->ep0_trb) { | |
2582 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2583 | ret = -ENOMEM; | |
2584 | goto err1; | |
2585 | } | |
2586 | ||
3ef35faf | 2587 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 FB |
2588 | if (!dwc->setup_buf) { |
2589 | dev_err(dwc->dev, "failed to allocate setup buffer\n"); | |
2590 | ret = -ENOMEM; | |
2591 | goto err2; | |
2592 | } | |
2593 | ||
5812b1c2 | 2594 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2595 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2596 | GFP_KERNEL); | |
5812b1c2 FB |
2597 | if (!dwc->ep0_bounce) { |
2598 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2599 | ret = -ENOMEM; | |
2600 | goto err3; | |
2601 | } | |
2602 | ||
72246da4 | 2603 | dwc->gadget.ops = &dwc3_gadget_ops; |
d327ab5b | 2604 | dwc->gadget.max_speed = USB_SPEED_SUPER; |
72246da4 | 2605 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2606 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2607 | dwc->gadget.name = "dwc3-gadget"; |
2608 | ||
a4b9d94b DC |
2609 | /* |
2610 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2611 | * on ep out. | |
2612 | */ | |
2613 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2614 | ||
72246da4 FB |
2615 | /* |
2616 | * REVISIT: Here we should clear all pending IRQs to be | |
2617 | * sure we're starting from a well known location. | |
2618 | */ | |
2619 | ||
2620 | ret = dwc3_gadget_init_endpoints(dwc); | |
2621 | if (ret) | |
5812b1c2 | 2622 | goto err4; |
72246da4 | 2623 | |
72246da4 FB |
2624 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2625 | if (ret) { | |
2626 | dev_err(dwc->dev, "failed to register udc\n"); | |
e1f80467 | 2627 | goto err4; |
72246da4 FB |
2628 | } |
2629 | ||
2630 | return 0; | |
2631 | ||
5812b1c2 | 2632 | err4: |
e1f80467 | 2633 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2634 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2635 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2636 | |
72246da4 | 2637 | err3: |
0fc9a1be | 2638 | kfree(dwc->setup_buf); |
72246da4 FB |
2639 | |
2640 | err2: | |
2641 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2642 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2643 | ||
2644 | err1: | |
2645 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2646 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2647 | ||
2648 | err0: | |
2649 | return ret; | |
2650 | } | |
2651 | ||
7415f17c FB |
2652 | /* -------------------------------------------------------------------------- */ |
2653 | ||
72246da4 FB |
2654 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2655 | { | |
72246da4 | 2656 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2657 | |
72246da4 FB |
2658 | dwc3_gadget_free_endpoints(dwc); |
2659 | ||
3ef35faf FB |
2660 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2661 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2662 | |
0fc9a1be | 2663 | kfree(dwc->setup_buf); |
72246da4 FB |
2664 | |
2665 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2666 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2667 | ||
2668 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2669 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2670 | } |
7415f17c FB |
2671 | |
2672 | int dwc3_gadget_prepare(struct dwc3 *dwc) | |
2673 | { | |
2674 | if (dwc->pullups_connected) | |
2675 | dwc3_gadget_disable_irq(dwc); | |
2676 | ||
2677 | return 0; | |
2678 | } | |
2679 | ||
2680 | void dwc3_gadget_complete(struct dwc3 *dwc) | |
2681 | { | |
2682 | if (dwc->pullups_connected) { | |
2683 | dwc3_gadget_enable_irq(dwc); | |
2684 | dwc3_gadget_run_stop(dwc, true); | |
2685 | } | |
2686 | } | |
2687 | ||
2688 | int dwc3_gadget_suspend(struct dwc3 *dwc) | |
2689 | { | |
2690 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2691 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
2692 | ||
2693 | dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2694 | ||
2695 | return 0; | |
2696 | } | |
2697 | ||
2698 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
2699 | { | |
2700 | struct dwc3_ep *dep; | |
2701 | int ret; | |
2702 | ||
2703 | /* Start with SuperSpeed Default */ | |
2704 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2705 | ||
2706 | dep = dwc->eps[0]; | |
2707 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); | |
2708 | if (ret) | |
2709 | goto err0; | |
2710 | ||
2711 | dep = dwc->eps[1]; | |
2712 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); | |
2713 | if (ret) | |
2714 | goto err1; | |
2715 | ||
2716 | /* begin to receive SETUP packets */ | |
2717 | dwc->ep0state = EP0_SETUP_PHASE; | |
2718 | dwc3_ep0_out_start(dwc); | |
2719 | ||
2720 | dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); | |
2721 | ||
2722 | return 0; | |
2723 | ||
2724 | err1: | |
2725 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2726 | ||
2727 | err0: | |
2728 | return ret; | |
2729 | } |