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usb: dwc2: simplify wait_for_chhltd
[people/ms/u-boot.git] / drivers / usb / host / dwc2.c
CommitLineData
6e9e0626
OT		 1/*
2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <errno.h>
10#include <usb.h>
11#include <malloc.h>
12#include <usbroothubdes.h>
13#include <asm/io.h>
14
15#include "dwc2.h"
16
17/* Use only HC channel 0. */
18#define DWC2_HC_CHANNEL 0
19
20#define DWC2_STATUS_BUF_SIZE 64
21#define DWC2_DATA_BUF_SIZE (64 * 1024)
22
23/* We need doubleword-aligned buffers for DMA transfers */
24DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
25DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
26
27#define MAX_DEVICE 16
28#define MAX_ENDPOINT 16
29static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
6e9e0626
OT		 30
31static int root_hub_devnum;
32
33static struct dwc2_core_regs *regs =
34 (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
35
36/*
37 * DWC2 IP interface
38 */
39static int wait_for_bit(void *reg, const uint32_t mask, bool set)
40{
41 unsigned int timeout = 1000000;
42 uint32_t val;
43
44 while (--timeout) {
45 val = readl(reg);
46 if (!set)
47 val = ~val;
48
49 if ((val & mask) == mask)
50 return 0;
51
52 udelay(1);
53 }
54
55 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
56 __func__, reg, mask, set);
57
58 return -ETIMEDOUT;
59}
60
61/*
62 * Initializes the FSLSPClkSel field of the HCFG register
63 * depending on the PHY type.
64 */
65static void init_fslspclksel(struct dwc2_core_regs *regs)
66{
67 uint32_t phyclk;
68
69#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
70 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
71#else
72 /* High speed PHY running at full speed or high speed */
73 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
74#endif
75
76#ifdef CONFIG_DWC2_ULPI_FS_LS
77 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
78 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
79 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
80 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
81 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
82
83 if (hval == 2 && fval == 1)
84 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
85#endif
86
87 clrsetbits_le32(&regs->host_regs.hcfg,
88 DWC2_HCFG_FSLSPCLKSEL_MASK,
89 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
90}
91
92/*
93 * Flush a Tx FIFO.
94 *
95 * @param regs Programming view of DWC_otg controller.
96 * @param num Tx FIFO to flush.
97 */
98static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
99{
100 int ret;
101
102 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
103 &regs->grstctl);
104 ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
105 if (ret)
106 printf("%s: Timeout!\n", __func__);
107
108 /* Wait for 3 PHY Clocks */
109 udelay(1);
110}
111
112/*
113 * Flush Rx FIFO.
114 *
115 * @param regs Programming view of DWC_otg controller.
116 */
117static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
118{
119 int ret;
120
121 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
122 ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
123 if (ret)
124 printf("%s: Timeout!\n", __func__);
125
126 /* Wait for 3 PHY Clocks */
127 udelay(1);
128}
129
130/*
131 * Do core a soft reset of the core. Be careful with this because it
132 * resets all the internal state machines of the core.
133 */
134static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
135{
136 int ret;
137
138 /* Wait for AHB master IDLE state. */
139 ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
140 if (ret)
141 printf("%s: Timeout!\n", __func__);
142
143 /* Core Soft Reset */
144 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
145 ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
146 if (ret)
147 printf("%s: Timeout!\n", __func__);
148
149 /*
150 * Wait for core to come out of reset.
151 * NOTE: This long sleep is _very_ important, otherwise the core will
152 * not stay in host mode after a connector ID change!
153 */
154 mdelay(100);
155}
156
157/*
158 * This function initializes the DWC_otg controller registers for
159 * host mode.
160 *
161 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
162 * request queues. Host channels are reset to ensure that they are ready for
163 * performing transfers.
164 *
165 * @param regs Programming view of DWC_otg controller
166 *
167 */
168static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
169{
170 uint32_t nptxfifosize = 0;
171 uint32_t ptxfifosize = 0;
172 uint32_t hprt0 = 0;
173 int i, ret, num_channels;
174
175 /* Restart the Phy Clock */
176 writel(0, &regs->pcgcctl);
177
178 /* Initialize Host Configuration Register */
179 init_fslspclksel(regs);
180#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
181 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
182#endif
183
184 /* Configure data FIFO sizes */
185#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
186 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
187 /* Rx FIFO */
188 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
189
190 /* Non-periodic Tx FIFO */
191 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
192 DWC2_FIFOSIZE_DEPTH_OFFSET;
193 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
194 DWC2_FIFOSIZE_STARTADDR_OFFSET;
195 writel(nptxfifosize, &regs->gnptxfsiz);
196
197 /* Periodic Tx FIFO */
198 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
199 DWC2_FIFOSIZE_DEPTH_OFFSET;
200 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
201 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
202 DWC2_FIFOSIZE_STARTADDR_OFFSET;
203 writel(ptxfifosize, &regs->hptxfsiz);
204 }
205#endif
206
207 /* Clear Host Set HNP Enable in the OTG Control Register */
208 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
209
210 /* Make sure the FIFOs are flushed. */
211 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
212 dwc_otg_flush_rx_fifo(regs);
213
214 /* Flush out any leftover queued requests. */
215 num_channels = readl(&regs->ghwcfg2);
216 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
217 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
218 num_channels += 1;
219
220 for (i = 0; i < num_channels; i++)
221 clrsetbits_le32(&regs->hc_regs[i].hcchar,
222 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
223 DWC2_HCCHAR_CHDIS);
224
225 /* Halt all channels to put them into a known state. */
226 for (i = 0; i < num_channels; i++) {
227 clrsetbits_le32(&regs->hc_regs[i].hcchar,
228 DWC2_HCCHAR_EPDIR,
229 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
230 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
231 DWC2_HCCHAR_CHEN, 0);
232 if (ret)
233 printf("%s: Timeout!\n", __func__);
234 }
235
236 /* Turn on the vbus power. */
237 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
238 hprt0 = readl(&regs->hprt0);
239 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
240 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
241 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
242 hprt0 |= DWC2_HPRT0_PRTPWR;
243 writel(hprt0, &regs->hprt0);
244 }
245 }
246}
247
248/*
249 * This function initializes the DWC_otg controller registers and
250 * prepares the core for device mode or host mode operation.
251 *
252 * @param regs Programming view of the DWC_otg controller
253 */
254static void dwc_otg_core_init(struct dwc2_core_regs *regs)
255{
256 uint32_t ahbcfg = 0;
257 uint32_t usbcfg = 0;
258 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
259
260 /* Common Initialization */
261 usbcfg = readl(&regs->gusbcfg);
262
263 /* Program the ULPI External VBUS bit if needed */
264#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
265 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
266#else
267 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
268#endif
269
270 /* Set external TS Dline pulsing */
271#ifdef CONFIG_DWC2_TS_DLINE
272 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
273#else
274 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
275#endif
276 writel(usbcfg, &regs->gusbcfg);
277
278 /* Reset the Controller */
279 dwc_otg_core_reset(regs);
280
281 /*
282 * This programming sequence needs to happen in FS mode before
283 * any other programming occurs
284 */
285#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
286 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
287 /* If FS mode with FS PHY */
288 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
289
290 /* Reset after a PHY select */
291 dwc_otg_core_reset(regs);
292
293 /*
294 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
295 * Also do this on HNP Dev/Host mode switches (done in dev_init
296 * and host_init).
297 */
298 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
299 init_fslspclksel(regs);
300
301#ifdef CONFIG_DWC2_I2C_ENABLE
302 /* Program GUSBCFG.OtgUtmifsSel to I2C */
303 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
304
305 /* Program GI2CCTL.I2CEn */
306 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
307 DWC2_GI2CCTL_I2CDEVADDR_MASK,
308 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
309 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
310#endif
311
312#else
313 /* High speed PHY. */
314
315 /*
316 * HS PHY parameters. These parameters are preserved during
317 * soft reset so only program the first time. Do a soft reset
318 * immediately after setting phyif.
319 */
320 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
321 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
322
323 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
324#ifdef CONFIG_DWC2_PHY_ULPI_DDR
325 usbcfg |= DWC2_GUSBCFG_DDRSEL;
326#else
327 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
328#endif
329 } else { /* UTMI+ interface */
330#if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
331 usbcfg |= DWC2_GUSBCFG_PHYIF;
332#endif
333 }
334
335 writel(usbcfg, &regs->gusbcfg);
336
337 /* Reset after setting the PHY parameters */
338 dwc_otg_core_reset(regs);
339#endif
340
341 usbcfg = readl(&regs->gusbcfg);
342 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
343#ifdef CONFIG_DWC2_ULPI_FS_LS
344 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
345 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
346 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
347 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
348 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
349 if (hval == 2 && fval == 1) {
350 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
351 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
352 }
353#endif
354 writel(usbcfg, &regs->gusbcfg);
355
356 /* Program the GAHBCFG Register. */
357 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
358 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
359 break;
360 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
361 while (brst_sz > 1) {
362 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
363 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
364 brst_sz >>= 1;
365 }
366
367#ifdef CONFIG_DWC2_DMA_ENABLE
368 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
369#endif
370 break;
371
372 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
373 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
374#ifdef CONFIG_DWC2_DMA_ENABLE
375 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
376#endif
377 break;
378 }
379
380 writel(ahbcfg, &regs->gahbcfg);
381
382 /* Program the GUSBCFG register for HNP/SRP. */
383 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
384
385#ifdef CONFIG_DWC2_IC_USB_CAP
386 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
387#endif
388}
389
390/*
391 * Prepares a host channel for transferring packets to/from a specific
392 * endpoint. The HCCHARn register is set up with the characteristics specified
393 * in _hc. Host channel interrupts that may need to be serviced while this
394 * transfer is in progress are enabled.
395 *
396 * @param regs Programming view of DWC_otg controller
397 * @param hc Information needed to initialize the host channel
398 */
399static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
400 uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in,
401 uint8_t ep_type, uint16_t max_packet)
402{
403 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
404 const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
405 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
406 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
407 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
408 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
409
410 /* Clear old interrupt conditions for this host channel. */
411 writel(0x3fff, &hc_regs->hcint);
412
413 /*
414 * Program the HCCHARn register with the endpoint characteristics
415 * for the current transfer.
416 */
417 writel(hcchar, &hc_regs->hcchar);
418
419 /* Program the HCSPLIT register for SPLITs */
420 writel(0, &hc_regs->hcsplt);
421}
422
423/*
424 * DWC2 to USB API interface
425 */
426/* Direction: In ; Request: Status */
427static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
428 int txlen, struct devrequest *cmd)
429{
430 uint32_t hprt0 = 0;
431 uint32_t port_status = 0;
432 uint32_t port_change = 0;
433 int len = 0;
434 int stat = 0;
435
436 switch (cmd->requesttype & ~USB_DIR_IN) {
437 case 0:
438 *(uint16_t *)buffer = cpu_to_le16(1);
439 len = 2;
440 break;
441 case USB_RECIP_INTERFACE:
442 case USB_RECIP_ENDPOINT:
443 *(uint16_t *)buffer = cpu_to_le16(0);
444 len = 2;
445 break;
446 case USB_TYPE_CLASS:
447 *(uint32_t *)buffer = cpu_to_le32(0);
448 len = 4;
449 break;
450 case USB_RECIP_OTHER | USB_TYPE_CLASS:
451 hprt0 = readl(&regs->hprt0);
452 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
453 port_status |= USB_PORT_STAT_CONNECTION;
454 if (hprt0 & DWC2_HPRT0_PRTENA)
455 port_status |= USB_PORT_STAT_ENABLE;
456 if (hprt0 & DWC2_HPRT0_PRTSUSP)
457 port_status |= USB_PORT_STAT_SUSPEND;
458 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
459 port_status |= USB_PORT_STAT_OVERCURRENT;
460 if (hprt0 & DWC2_HPRT0_PRTRST)
461 port_status |= USB_PORT_STAT_RESET;
462 if (hprt0 & DWC2_HPRT0_PRTPWR)
463 port_status |= USB_PORT_STAT_POWER;
464
465 port_status |= USB_PORT_STAT_HIGH_SPEED;
466
467 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
468 port_change |= USB_PORT_STAT_C_ENABLE;
469 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
470 port_change |= USB_PORT_STAT_C_CONNECTION;
471 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
472 port_change |= USB_PORT_STAT_C_OVERCURRENT;
473
474 *(uint32_t *)buffer = cpu_to_le32(port_status |
475 (port_change << 16));
476 len = 4;
477 break;
478 default:
479 puts("unsupported root hub command\n");
480 stat = USB_ST_STALLED;
481 }
482
483 dev->act_len = min(len, txlen);
484 dev->status = stat;
485
486 return stat;
487}
488
489/* Direction: In ; Request: Descriptor */
490static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
491 void *buffer, int txlen,
492 struct devrequest *cmd)
493{
494 unsigned char data[32];
495 uint32_t dsc;
496 int len = 0;
497 int stat = 0;
498 uint16_t wValue = cpu_to_le16(cmd->value);
499 uint16_t wLength = cpu_to_le16(cmd->length);
500
501 switch (cmd->requesttype & ~USB_DIR_IN) {
502 case 0:
503 switch (wValue & 0xff00) {
504 case 0x0100: /* device descriptor */
b4141195 505 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
6e9e0626
OT		 506 memcpy(buffer, root_hub_dev_des, len);
507 break;
508 case 0x0200: /* configuration descriptor */
b4141195 509 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
6e9e0626
OT		 510 memcpy(buffer, root_hub_config_des, len);
511 break;
512 case 0x0300: /* string descriptors */
513 switch (wValue & 0xff) {
514 case 0x00:
b4141195
MY		 515 len = min3(txlen, (int)sizeof(root_hub_str_index0),
516 (int)wLength);
6e9e0626
OT		 517 memcpy(buffer, root_hub_str_index0, len);
518 break;
519 case 0x01:
b4141195
MY		 520 len = min3(txlen, (int)sizeof(root_hub_str_index1),
521 (int)wLength);
6e9e0626
OT		 522 memcpy(buffer, root_hub_str_index1, len);
523 break;
524 }
525 break;
526 default:
527 stat = USB_ST_STALLED;
528 }
529 break;
530
531 case USB_TYPE_CLASS:
532 /* Root port config, set 1 port and nothing else. */
533 dsc = 0x00000001;
534
535 data[0] = 9; /* min length; */
536 data[1] = 0x29;
537 data[2] = dsc & RH_A_NDP;
538 data[3] = 0;
539 if (dsc & RH_A_PSM)
540 data[3] |= 0x1;
541 if (dsc & RH_A_NOCP)
542 data[3] |= 0x10;
543 else if (dsc & RH_A_OCPM)
544 data[3] |= 0x8;
545
546 /* corresponds to data[4-7] */
547 data[5] = (dsc & RH_A_POTPGT) >> 24;
548 data[7] = dsc & RH_B_DR;
549 if (data[2] < 7) {
550 data[8] = 0xff;
551 } else {
552 data[0] += 2;
553 data[8] = (dsc & RH_B_DR) >> 8;
554 data[9] = 0xff;
555 data[10] = data[9];
556 }
557
b4141195 558 len = min3(txlen, (int)data[0], (int)wLength);
6e9e0626
OT		 559 memcpy(buffer, data, len);
560 break;
561 default:
562 puts("unsupported root hub command\n");
563 stat = USB_ST_STALLED;
564 }
565
566 dev->act_len = min(len, txlen);
567 dev->status = stat;
568
569 return stat;
570}
571
572/* Direction: In ; Request: Configuration */
573static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
574 void *buffer, int txlen,
575 struct devrequest *cmd)
576{
577 int len = 0;
578 int stat = 0;
579
580 switch (cmd->requesttype & ~USB_DIR_IN) {
581 case 0:
582 *(uint8_t *)buffer = 0x01;
583 len = 1;
584 break;
585 default:
586 puts("unsupported root hub command\n");
587 stat = USB_ST_STALLED;
588 }
589
590 dev->act_len = min(len, txlen);
591 dev->status = stat;
592
593 return stat;
594}
595
596/* Direction: In */
597static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
598 void *buffer, int txlen,
599 struct devrequest *cmd)
600{
601 switch (cmd->request) {
602 case USB_REQ_GET_STATUS:
603 return dwc_otg_submit_rh_msg_in_status(dev, buffer,
604 txlen, cmd);
605 case USB_REQ_GET_DESCRIPTOR:
606 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
607 txlen, cmd);
608 case USB_REQ_GET_CONFIGURATION:
609 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
610 txlen, cmd);
611 default:
612 puts("unsupported root hub command\n");
613 return USB_ST_STALLED;
614 }
615}
616
617/* Direction: Out */
618static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
619 void *buffer, int txlen,
620 struct devrequest *cmd)
621{
622 int len = 0;
623 int stat = 0;
624 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
625 uint16_t wValue = cpu_to_le16(cmd->value);
626
627 switch (bmrtype_breq & ~USB_DIR_IN) {
628 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
629 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
630 break;
631
632 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
633 switch (wValue) {
634 case USB_PORT_FEAT_C_CONNECTION:
635 setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
636 break;
637 }
638 break;
639
640 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
641 switch (wValue) {
642 case USB_PORT_FEAT_SUSPEND:
643 break;
644
645 case USB_PORT_FEAT_RESET:
646 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
647 DWC2_HPRT0_PRTCONNDET |
648 DWC2_HPRT0_PRTENCHNG |
649 DWC2_HPRT0_PRTOVRCURRCHNG,
650 DWC2_HPRT0_PRTRST);
651 mdelay(50);
652 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
653 break;
654
655 case USB_PORT_FEAT_POWER:
656 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
657 DWC2_HPRT0_PRTCONNDET |
658 DWC2_HPRT0_PRTENCHNG |
659 DWC2_HPRT0_PRTOVRCURRCHNG,
660 DWC2_HPRT0_PRTRST);
661 break;
662
663 case USB_PORT_FEAT_ENABLE:
664 break;
665 }
666 break;
667 case (USB_REQ_SET_ADDRESS << 8):
668 root_hub_devnum = wValue;
669 break;
670 case (USB_REQ_SET_CONFIGURATION << 8):
671 break;
672 default:
673 puts("unsupported root hub command\n");
674 stat = USB_ST_STALLED;
675 }
676
677 len = min(len, txlen);
678
679 dev->act_len = len;
680 dev->status = stat;
681
682 return stat;
683}
684
685static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
686 void *buffer, int txlen,
687 struct devrequest *cmd)
688{
689 int stat = 0;
690
691 if (usb_pipeint(pipe)) {
692 puts("Root-Hub submit IRQ: NOT implemented\n");
693 return 0;
694 }
695
696 if (cmd->requesttype & USB_DIR_IN)
697 stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
698 else
699 stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
700
701 mdelay(1);
702
703 return stat;
704}
705
4a1d21fc
SW		 706int wait_for_chhltd(uint32_t *sub, int *toggle)
707{
708 const uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP |
709 DWC2_HCINT_CHHLTD | DWC2_HCINT_ACK;
710 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
711 int ret;
712 uint32_t hcint, hctsiz;
713
714 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
715 if (ret)
716 return ret;
717
718 hcint = readl(&hc_regs->hcint);
719 if (hcint != hcint_comp_hlt_ack) {
720 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
721 return -EINVAL;
722 }
723
724 hctsiz = readl(&hc_regs->hctsiz);
725 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
726 DWC2_HCTSIZ_XFERSIZE_OFFSET;
66ffc875 727 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
4a1d21fc 728
66ffc875 729 debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
4a1d21fc
SW		 730
731 return 0;
732}
733
7b5e504d
SW		 734static int dwc2_eptype[] = {
735 DWC2_HCCHAR_EPTYPE_ISOC,
736 DWC2_HCCHAR_EPTYPE_INTR,
737 DWC2_HCCHAR_EPTYPE_CONTROL,
738 DWC2_HCCHAR_EPTYPE_BULK,
739};
740
741int chunk_msg(struct usb_device *dev, unsigned long pipe, int *pid, int in,
742 void *buffer, int len)
6e9e0626 743{
7b5e504d 744 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
6e9e0626
OT		 745 int devnum = usb_pipedevice(pipe);
746 int ep = usb_pipeendpoint(pipe);
747 int max = usb_maxpacket(dev, pipe);
7b5e504d 748 int eptype = dwc2_eptype[usb_pipetype(pipe)];
6e9e0626 749 int done = 0;
4a1d21fc
SW		 750 int ret;
751 uint32_t sub;
6e9e0626
OT		 752 uint32_t xfer_len;
753 uint32_t num_packets;
754 int stop_transfer = 0;
6e9e0626 755
7b5e504d
SW		 756 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
757 in, len);
6e9e0626
OT		 758
759 if (len > DWC2_DATA_BUF_SIZE) {
760 printf("%s: %d is more then available buffer size (%d)\n",
761 __func__, len, DWC2_DATA_BUF_SIZE);
762 dev->status = 0;
763 dev->act_len = 0;
764 return -EINVAL;
765 }
766
ee837554 767 do {
6e9e0626 768 /* Initialize channel */
7b5e504d
SW		 769 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, in, eptype,
770 max);
6e9e0626
OT		 771
772 xfer_len = len - done;
773 /* Make sure that xfer_len is a multiple of max packet size. */
774 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
775 xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
776
777 if (xfer_len > 0) {
778 num_packets = (xfer_len + max - 1) / max;
779 if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
780 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
781 xfer_len = num_packets * max;
782 }
783 } else {
784 num_packets = 1;
785 }
786
7b5e504d 787 if (in)
6e9e0626
OT		 788 xfer_len = num_packets * max;
789
7b5e504d
SW		 790 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
791 *pid, xfer_len, num_packets);
792
6e9e0626
OT		 793 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
794 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
7b5e504d 795 (*pid << DWC2_HCTSIZ_PID_OFFSET),
6e9e0626
OT		 796 &hc_regs->hctsiz);
797
798 memcpy(aligned_buffer, (char *)buffer + done, len - done);
799 writel((uint32_t)aligned_buffer, &hc_regs->hcdma);
800
801 /* Set host channel enable after all other setup is complete. */
802 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
803 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
804 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
805 DWC2_HCCHAR_CHEN);
806
7b5e504d 807 ret = wait_for_chhltd(&sub, pid);
4a1d21fc
SW		 808 if (ret) {
809 stop_transfer = 1;
810 break;
811 }
6e9e0626 812
4a1d21fc 813 done += xfer_len;
7b5e504d 814 if (in) {
4a1d21fc
SW		 815 done -= sub;
816 if (sub)
6e9e0626 817 stop_transfer = 1;
6e9e0626 818 }
ee837554 819 } while ((done < len) && !stop_transfer);
6e9e0626 820
7b5e504d 821 if (done && in)
6e9e0626
OT		 822 memcpy(buffer, aligned_buffer, done);
823
824 writel(0, &hc_regs->hcintmsk);
825 writel(0xFFFFFFFF, &hc_regs->hcint);
826
827 dev->status = 0;
828 dev->act_len = done;
829
830 return 0;
831}
832
7b5e504d
SW		 833/* U-Boot USB transmission interface */
834int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
835 int len)
836{
837 int devnum = usb_pipedevice(pipe);
838 int ep = usb_pipeendpoint(pipe);
839
840 if (devnum == root_hub_devnum) {
841 dev->status = 0;
842 return -EINVAL;
843 }
844
845 return chunk_msg(dev, pipe, &bulk_data_toggle[devnum][ep],
846 usb_pipein(pipe), buffer, len);
847}
848
6e9e0626
OT		 849int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
850 int len, struct devrequest *setup)
851{
6e9e0626 852 int devnum = usb_pipedevice(pipe);
ee837554 853 int pid, ret, act_len;
6e9e0626
OT		 854 /* For CONTROL endpoint pid should start with DATA1 */
855 int status_direction;
856
857 if (devnum == root_hub_devnum) {
858 dev->status = 0;
859 dev->speed = USB_SPEED_HIGH;
860 return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
861 }
862
ee837554
SW		 863 pid = DWC2_HC_PID_SETUP;
864 ret = chunk_msg(dev, pipe, &pid, 0, setup, 8);
865 if (ret)
866 return ret;
6e9e0626
OT		 867
868 if (buffer) {
282685e0
SW		 869 pid = DWC2_HC_PID_DATA1;
870 ret = chunk_msg(dev, pipe, &pid, usb_pipein(pipe), buffer,
871 len);
ee837554
SW		 872 if (ret)
873 return ret;
874 act_len = dev->act_len;
6e9e0626 875 } /* End of DATA stage */
ee837554
SW		 876 else
877 act_len = 0;
6e9e0626
OT		 878
879 /* STATUS stage */
880 if ((len == 0) || usb_pipeout(pipe))
881 status_direction = 1;
882 else
883 status_direction = 0;
884
ee837554
SW		 885 pid = DWC2_HC_PID_DATA1;
886 ret = chunk_msg(dev, pipe, &pid, status_direction, status_buffer, 0);
887 if (ret)
888 return ret;
6e9e0626 889
ee837554 890 dev->act_len = act_len;
6e9e0626 891
4a1d21fc 892 return 0;
6e9e0626
OT		 893}
894
895int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
896 int len, int interval)
897{
898 printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
899 dev, pipe, buffer, len, interval);
900 return -ENOSYS;
901}
902
903/* U-Boot USB control interface */
904int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
905{
906 uint32_t snpsid;
907 int i, j;
908
909 root_hub_devnum = 0;
910
911 snpsid = readl(&regs->gsnpsid);
912 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
913
914 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
915 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
916 return -ENODEV;
917 }
918
919 dwc_otg_core_init(regs);
920 dwc_otg_core_host_init(regs);
921
922 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
923 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
924 DWC2_HPRT0_PRTOVRCURRCHNG,
925 DWC2_HPRT0_PRTRST);
926 mdelay(50);
927 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
928 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
929 DWC2_HPRT0_PRTRST);
930
931 for (i = 0; i < MAX_DEVICE; i++) {
282685e0 932 for (j = 0; j < MAX_ENDPOINT; j++)
6e9e0626 933 bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
6e9e0626
OT		 934 }
935
936 return 0;
937}
938
939int usb_lowlevel_stop(int index)
940{
941 /* Put everything in reset. */
942 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
943 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
944 DWC2_HPRT0_PRTOVRCURRCHNG,
945 DWC2_HPRT0_PRTRST);
946 return 0;
947}
"Das U-Boot" Source Tree