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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
40d1a31e PC |
2 | /* |
3 | * STiH407 family DWC3 specific Glue layer | |
4 | * | |
fb48bc44 | 5 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
0f8106f8 | 6 | * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. |
40d1a31e PC |
7 | */ |
8 | ||
d678a59d | 9 | #include <common.h> |
f7ae49fc | 10 | #include <log.h> |
401d1c4f | 11 | #include <asm/global_data.h> |
40d1a31e PC |
12 | #include <asm/io.h> |
13 | #include <dm.h> | |
14 | #include <errno.h> | |
40d1a31e PC |
15 | #include <dm/lists.h> |
16 | #include <regmap.h> | |
17 | #include <reset-uclass.h> | |
18 | #include <syscon.h> | |
19 | #include <usb.h> | |
1e94b46f | 20 | #include <linux/printk.h> |
40d1a31e PC |
21 | |
22 | #include <linux/usb/dwc3.h> | |
23 | #include <linux/usb/otg.h> | |
24 | #include <dwc3-sti-glue.h> | |
25 | ||
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
28 | /* | |
8a8d24bd | 29 | * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure |
40d1a31e PC |
30 | * @syscfg_base: addr for the glue syscfg |
31 | * @glue_base: addr for the glue registers | |
32 | * @syscfg_offset: usb syscfg control offset | |
33 | * @powerdown_ctl: rest controller for powerdown signal | |
34 | * @softreset_ctl: reset controller for softreset signal | |
35 | * @mode: drd static host/device config | |
36 | */ | |
8a8d24bd | 37 | struct sti_dwc3_glue_plat { |
40d1a31e PC |
38 | phys_addr_t syscfg_base; |
39 | phys_addr_t glue_base; | |
40 | phys_addr_t syscfg_offset; | |
41 | struct reset_ctl powerdown_ctl; | |
42 | struct reset_ctl softreset_ctl; | |
43 | enum usb_dr_mode mode; | |
44 | }; | |
45 | ||
8a8d24bd | 46 | static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat) |
40d1a31e PC |
47 | { |
48 | unsigned long val; | |
49 | ||
50 | val = readl(plat->syscfg_base + plat->syscfg_offset); | |
51 | ||
52 | val &= USB3_CONTROL_MASK; | |
53 | ||
54 | switch (plat->mode) { | |
55 | case USB_DR_MODE_PERIPHERAL: | |
56 | val &= ~(USB3_DELAY_VBUSVALID | |
57 | | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) | |
58 | | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 | |
59 | | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); | |
60 | ||
61 | val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; | |
62 | break; | |
63 | ||
64 | case USB_DR_MODE_HOST: | |
65 | val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID | |
66 | | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) | |
67 | | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 | |
68 | | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); | |
69 | ||
70 | val |= USB3_DELAY_VBUSVALID; | |
71 | break; | |
72 | ||
73 | default: | |
9b643e31 | 74 | pr_err("Unsupported mode of operation %d\n", plat->mode); |
40d1a31e PC |
75 | return -EINVAL; |
76 | } | |
77 | writel(val, plat->syscfg_base + plat->syscfg_offset); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
8a8d24bd | 82 | static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat) |
40d1a31e PC |
83 | { |
84 | unsigned long reg; | |
85 | ||
86 | reg = readl(plat->glue_base + CLKRST_CTRL); | |
87 | ||
88 | reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; | |
89 | reg &= ~SW_PIPEW_RESET_N; | |
90 | ||
91 | writel(reg, plat->glue_base + CLKRST_CTRL); | |
92 | ||
93 | /* configure mux for vbus, powerpresent and bvalid signals */ | |
94 | reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1); | |
95 | ||
96 | reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | | |
97 | SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | | |
98 | SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); | |
99 | ||
100 | writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1); | |
101 | ||
102 | setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); | |
103 | } | |
104 | ||
d1998a9f | 105 | static int sti_dwc3_glue_of_to_plat(struct udevice *dev) |
40d1a31e | 106 | { |
8a8d24bd | 107 | struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); |
40d1a31e PC |
108 | struct udevice *syscon; |
109 | struct regmap *regmap; | |
110 | int ret; | |
111 | u32 reg[4]; | |
112 | ||
f10643cf SG |
113 | ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg, |
114 | ARRAY_SIZE(reg)); | |
40d1a31e | 115 | if (ret) { |
9b643e31 | 116 | pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret); |
40d1a31e PC |
117 | return ret; |
118 | } | |
119 | ||
120 | plat->glue_base = reg[0]; | |
121 | plat->syscfg_offset = reg[2]; | |
122 | ||
123 | /* get corresponding syscon phandle */ | |
124 | ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg", | |
125 | &syscon); | |
126 | if (ret) { | |
9b643e31 | 127 | pr_err("unable to find syscon device (%d)\n", ret); |
40d1a31e PC |
128 | return ret; |
129 | } | |
130 | ||
131 | /* get syscfg-reg base address */ | |
132 | regmap = syscon_get_regmap(syscon); | |
133 | if (!regmap) { | |
9b643e31 | 134 | pr_err("unable to find regmap\n"); |
40d1a31e PC |
135 | return -ENODEV; |
136 | } | |
8c1de5e0 | 137 | plat->syscfg_base = regmap->ranges[0].start; |
40d1a31e PC |
138 | |
139 | /* get powerdown reset */ | |
140 | ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl); | |
141 | if (ret) { | |
9b643e31 | 142 | pr_err("can't get powerdown reset for %s (%d)", dev->name, ret); |
40d1a31e PC |
143 | return ret; |
144 | } | |
145 | ||
146 | /* get softreset reset */ | |
147 | ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl); | |
148 | if (ret) | |
9b643e31 | 149 | pr_err("can't get soft reset for %s (%d)", dev->name, ret); |
40d1a31e PC |
150 | |
151 | return ret; | |
152 | }; | |
153 | ||
154 | static int sti_dwc3_glue_bind(struct udevice *dev) | |
155 | { | |
8a8d24bd | 156 | struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); |
ac28e59a | 157 | ofnode node, dwc3_node; |
40d1a31e | 158 | |
ac28e59a | 159 | /* Find snps,dwc3 node from subnode */ |
f10643cf | 160 | ofnode_for_each_subnode(node, dev_ofnode(dev)) { |
ac28e59a KY |
161 | if (ofnode_device_is_compatible(node, "snps,dwc3")) |
162 | dwc3_node = node; | |
40d1a31e PC |
163 | } |
164 | ||
f3858ce0 | 165 | if (!ofnode_valid(dwc3_node)) { |
9b643e31 | 166 | pr_err("Can't find dwc3 subnode for %s\n", dev->name); |
40d1a31e PC |
167 | return -ENODEV; |
168 | } | |
169 | ||
170 | /* retrieve the DWC3 dual role mode */ | |
171 | plat->mode = usb_get_dr_mode(dwc3_node); | |
172 | if (plat->mode == USB_DR_MODE_UNKNOWN) | |
173 | /* by default set dual role mode to HOST */ | |
174 | plat->mode = USB_DR_MODE_HOST; | |
175 | ||
176 | return dm_scan_fdt_dev(dev); | |
177 | } | |
178 | ||
179 | static int sti_dwc3_glue_probe(struct udevice *dev) | |
180 | { | |
8a8d24bd | 181 | struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); |
40d1a31e PC |
182 | int ret; |
183 | ||
184 | /* deassert both powerdown and softreset */ | |
185 | ret = reset_deassert(&plat->powerdown_ctl); | |
186 | if (ret < 0) { | |
9b643e31 | 187 | pr_err("DWC3 powerdown reset deassert failed: %d", ret); |
40d1a31e PC |
188 | return ret; |
189 | } | |
190 | ||
191 | ret = reset_deassert(&plat->softreset_ctl); | |
192 | if (ret < 0) { | |
9b643e31 | 193 | pr_err("DWC3 soft reset deassert failed: %d", ret); |
40d1a31e PC |
194 | goto softreset_err; |
195 | } | |
196 | ||
197 | ret = sti_dwc3_glue_drd_init(plat); | |
198 | if (ret) | |
199 | goto init_err; | |
200 | ||
201 | sti_dwc3_glue_init(plat); | |
202 | ||
203 | return 0; | |
204 | ||
205 | init_err: | |
206 | ret = reset_assert(&plat->softreset_ctl); | |
207 | if (ret < 0) { | |
9b643e31 | 208 | pr_err("DWC3 soft reset deassert failed: %d", ret); |
40d1a31e PC |
209 | return ret; |
210 | } | |
211 | ||
212 | softreset_err: | |
213 | ret = reset_assert(&plat->powerdown_ctl); | |
214 | if (ret < 0) | |
9b643e31 | 215 | pr_err("DWC3 powerdown reset deassert failed: %d", ret); |
40d1a31e PC |
216 | |
217 | return ret; | |
218 | } | |
219 | ||
220 | static int sti_dwc3_glue_remove(struct udevice *dev) | |
221 | { | |
8a8d24bd | 222 | struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); |
40d1a31e PC |
223 | int ret; |
224 | ||
225 | /* assert both powerdown and softreset */ | |
226 | ret = reset_assert(&plat->powerdown_ctl); | |
227 | if (ret < 0) { | |
9b643e31 | 228 | pr_err("DWC3 powerdown reset deassert failed: %d", ret); |
40d1a31e PC |
229 | return ret; |
230 | } | |
231 | ||
232 | ret = reset_assert(&plat->softreset_ctl); | |
233 | if (ret < 0) | |
9b643e31 | 234 | pr_err("DWC3 soft reset deassert failed: %d", ret); |
40d1a31e PC |
235 | |
236 | return ret; | |
237 | } | |
238 | ||
239 | static const struct udevice_id sti_dwc3_glue_ids[] = { | |
240 | { .compatible = "st,stih407-dwc3" }, | |
241 | { } | |
242 | }; | |
243 | ||
244 | U_BOOT_DRIVER(dwc3_sti_glue) = { | |
245 | .name = "dwc3_sti_glue", | |
f3bc736e | 246 | .id = UCLASS_NOP, |
40d1a31e | 247 | .of_match = sti_dwc3_glue_ids, |
d1998a9f | 248 | .of_to_plat = sti_dwc3_glue_of_to_plat, |
40d1a31e PC |
249 | .probe = sti_dwc3_glue_probe, |
250 | .remove = sti_dwc3_glue_remove, | |
251 | .bind = sti_dwc3_glue_bind, | |
8a8d24bd | 252 | .plat_auto = sizeof(struct sti_dwc3_glue_plat), |
40d1a31e PC |
253 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
254 | }; |