[people/ms/u-boot.git] / drivers / usb / host / ehci-fsl.c

/*
 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
 *
 * Author: Tor Krill tor@excito.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <pci.h>
#include <usb.h>
#include <asm/io.h>
#include <usb/ehci-fsl.h>
#include <hwconfig.h>
#include <fsl_usb.h>
#include <fdt_support.h>

#include "ehci.h"

#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif

static void set_txfifothresh(struct usb_ehci *, u32);

/* Check USB PHY clock valid */
static int usb_phy_clk_valid(struct usb_ehci *ehci)
{
	if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
			in_be32(&ehci->prictrl))) {
		printf("USB PHY clock invalid!\n");
		return 0;
	} else {
		return 1;
	}
}

/*
 * Create the appropriate control structures to manage
 * a new EHCI host controller.
 *
 * Excerpts from linux ehci fsl driver.
 */
int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci = NULL;
	const char *phy_type = NULL;
	size_t len;
	char current_usb_controller[5];
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
	char usb_phy[5];

	usb_phy[0] = '\0';
#endif
	if (has_erratum_a007075()) {
		/*
		 * A 5ms delay is needed after applying soft-reset to the
		 * controller to let external ULPI phy come out of reset.
		 * This delay needs to be added before re-initializing
		 * the controller after soft-resetting completes
		 */
		mdelay(5);
	}
	memset(current_usb_controller, '\0', 5);
	snprintf(current_usb_controller, 4, "usb%d", index+1);

	switch (index) {
	case 0:
		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
		break;
	case 1:
		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
		break;
	default:
		printf("ERROR: wrong controller index!!\n");
		break;
	};

	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

	/* Set to Host mode */
	setbits_le32(&ehci->usbmode, CM_HOST);

	out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
	out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);

	/* Init phy */
	if (hwconfig_sub(current_usb_controller, "phy_type"))
		phy_type = hwconfig_subarg(current_usb_controller,
				"phy_type", &len);
	else
		phy_type = getenv("usb_phy_type");

	if (!phy_type) {
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
		/* if none specified assume internal UTMI */
		strcpy(usb_phy, "utmi");
		phy_type = usb_phy;
#else
		printf("WARNING: USB phy type not defined !!\n");
		return -1;
#endif
	}

	if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				PHY_CLK_SEL_UTMI);
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				UTMI_PHY_EN);
		udelay(1000); /* delay required for PHY Clk to appear */
#endif
		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				USB_EN);
	} else {
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				PHY_CLK_SEL_ULPI);
		clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
				CONTROL_REGISTER_W1C_MASK, USB_EN);
		udelay(1000); /* delay required for PHY Clk to appear */
		if (!usb_phy_clk_valid(ehci))
			return -EINVAL;
		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
	}

	out_be32(&ehci->prictrl, 0x0000000c);
	out_be32(&ehci->age_cnt_limit, 0x00000040);
	out_be32(&ehci->sictrl, 0x00000001);

	in_le32(&ehci->usbmode);

	if (has_erratum_a007798())
		set_txfifothresh(ehci, TXFIFOTHRESH);

	return 0;
}

/*
 * Destroy the appropriate control structures corresponding
 * the the EHCI host controller.
 */
int ehci_hcd_stop(int index)
{
	return 0;
}

/*
 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
 * to counter DDR latencies in writing data into Tx buffer.
 * This prevents Tx buffer from getting underrun
 */
static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
{
	u32 cmd;
	cmd = ehci_readl(&ehci->txfilltuning);
	cmd &= ~TXFIFO_THRESH_MASK;
	cmd |= TXFIFO_THRESH(txfifo_thresh);
	ehci_writel(&ehci->txfilltuning, cmd);
}

#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
				       const char *phy_type, int start_offset)
{
	const char *compat_dr = "fsl-usb2-dr";
	const char *compat_mph = "fsl-usb2-mph";
	const char *prop_mode = "dr_mode";
	const char *prop_type = "phy_type";
	const char *node_type = NULL;
	int node_offset;
	int err;

	node_offset = fdt_node_offset_by_compatible(blob,
						    start_offset, compat_mph);
	if (node_offset < 0) {
		node_offset = fdt_node_offset_by_compatible(blob,
							    start_offset,
							    compat_dr);
		if (node_offset < 0) {
			printf("WARNING: could not find compatible node: %s",
			       fdt_strerror(node_offset));
			return -1;
		}
		node_type = compat_dr;
	} else {
		node_type = compat_mph;
	}

	if (mode) {
		err = fdt_setprop(blob, node_offset, prop_mode, mode,
				  strlen(mode) + 1);
		if (err < 0)
			printf("WARNING: could not set %s for %s: %s.\n",
			       prop_mode, node_type, fdt_strerror(err));
	}

	if (phy_type) {
		err = fdt_setprop(blob, node_offset, prop_type, phy_type,
				  strlen(phy_type) + 1);
		if (err < 0)
			printf("WARNING: could not set %s for %s: %s.\n",
			       prop_type, node_type, fdt_strerror(err));
	}

	return node_offset;
}

void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
	static const char * const modes[] = { "host", "peripheral", "otg" };
	static const char * const phys[] = { "ulpi", "utmi" };
	int usb_mode_off = -1;
	int usb_phy_off = -1;
	char str[5];
	int i, j;

	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
		const char *dr_mode_type = NULL;
		const char *dr_phy_type = NULL;
		int mode_idx = -1, phy_idx = -1;

		snprintf(str, 5, "%s%d", "usb", i);
		if (hwconfig(str)) {
			for (j = 0; j < ARRAY_SIZE(modes); j++) {
				if (hwconfig_subarg_cmp(str, "dr_mode",
							modes[j])) {
					mode_idx = j;
					break;
				}
			}

			for (j = 0; j < ARRAY_SIZE(phys); j++) {
				if (hwconfig_subarg_cmp(str, "phy_type",
							phys[j])) {
					phy_idx = j;
					break;
				}
			}

			if (mode_idx < 0 && phy_idx < 0) {
				printf("WARNING: invalid phy or mode\n");
				return;
			}

			if (mode_idx > -1)
				dr_mode_type = modes[mode_idx];

			if (phy_idx > -1)
				dr_phy_type = phys[phy_idx];
		}

		usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
							   dr_mode_type, NULL,
							   usb_mode_off);

		if (usb_mode_off < 0)
			return;

		usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
							  NULL, dr_phy_type,
							  usb_phy_off);

		if (usb_phy_off < 0)
			return;
	}
}
#endif
Commit	Line	Data
6b92487d	1	/*
1b719e66	2	* (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
4ef01010	3	*
6b92487d MT	4	* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
	5	*
	6	* Author: Tor Krill tor@excito.com
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
6b92487d MT	9	*/
	10
	11	#include <common.h>
	12	#include <pci.h>
	13	#include <usb.h>
6b92487d	14	#include <asm/io.h>
4ef01010	15	#include <usb/ehci-fsl.h>
1b719e66	16	#include <hwconfig.h>
c26c80a1	17	#include <fsl_usb.h>
a1c04e27	18	#include <fdt_support.h>
6b92487d	19
2731b9a8	20	#include "ehci.h"
6b92487d	21
a1c04e27 NB	22	#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
	23	#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
	24	#endif
	25
896720ce NB	26	static void set_txfifothresh(struct usb_ehci *, u32);
896720ce NB	27
047cea36 SL	28	/* Check USB PHY clock valid */
	29	static int usb_phy_clk_valid(struct usb_ehci *ehci)
	30	{
	31	if (!((in_be32(&ehci->control) & PHY_CLK_VALID) \|\|
	32	in_be32(&ehci->prictrl))) {
	33	printf("USB PHY clock invalid!\n");
	34	return 0;
	35	} else {
	36	return 1;
	37	}
	38	}
	39
6b92487d MT	40	/*
	41	* Create the appropriate control structures to manage
	42	* a new EHCI host controller.
	43	*
	44	* Excerpts from linux ehci fsl driver.
	45	*/
127efc4f TK	46	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	47	struct ehci_hccr hccr, struct ehci_hcor hcor)
6b92487d	48	{
77354e9d	49	struct usb_ehci *ehci = NULL;
1b719e66 RM	50	const char *phy_type = NULL;
1b719e66 RM	51	size_t len;
0ecb15c8	52	char current_usb_controller[5];
dd22f7cf KG	53	#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
dd22f7cf KG	54	char usb_phy[5];
1b719e66 RM	55
1b719e66 RM	56	usb_phy[0] = '\0';
dd22f7cf	57	#endif
11856919 NB	58	if (has_erratum_a007075()) {
	59	/*
	60	* A 5ms delay is needed after applying soft-reset to the
	61	* controller to let external ULPI phy come out of reset.
	62	* This delay needs to be added before re-initializing
	63	* the controller after soft-resetting completes
	64	*/
	65	mdelay(5);
	66	}
0ecb15c8 NB	67	memset(current_usb_controller, '\0', 5);
0ecb15c8 NB	68	snprintf(current_usb_controller, 4, "usb%d", index+1);
6b92487d	69
77354e9d	70	switch (index) {
	71	case 0:
	72	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
	73	break;
	74	case 1:
	75	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
	76	break;
	77	default:
	78	printf("ERROR: wrong controller index!!\n");
	79	break;
	80	};
	81
676ae068 LS	82	hccr = (struct ehci_hccr )((uint32_t)&ehci->caplength);
	83	hcor = (struct ehci_hcor )((uint32_t) *hccr +
	84	HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
6b92487d	85
6b92487d	86	/* Set to Host mode */
08066152	87	setbits_le32(&ehci->usbmode, CM_HOST);
6b92487d	88
08066152 VM	89	out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
08066152 VM	90	out_be32(&ehci->snoop2, 0x80000000 \| SNOOP_SIZE_2GB);
6b92487d MT	91
6b92487d MT	92	/* Init phy */
0ecb15c8 NB	93	if (hwconfig_sub(current_usb_controller, "phy_type"))
	94	phy_type = hwconfig_subarg(current_usb_controller,
	95	"phy_type", &len);
4ef01010	96	else
1b719e66 RM	97	phy_type = getenv("usb_phy_type");
	98
	99	if (!phy_type) {
	100	#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
	101	/* if none specified assume internal UTMI */
	102	strcpy(usb_phy, "utmi");
	103	phy_type = usb_phy;
	104	#else
	105	printf("WARNING: USB phy type not defined !!\n");
	106	return -1;
	107	#endif
	108	}
	109
91d7746d	110	if (!strncmp(phy_type, "utmi", 4)) {
1b719e66	111	#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
15231f6d NB	112	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
	113	PHY_CLK_SEL_UTMI);
	114	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
	115	UTMI_PHY_EN);
1b719e66 RM	116	udelay(1000); /* delay required for PHY Clk to appear */
1b719e66 RM	117	#endif
676ae068	118	out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
15231f6d NB	119	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
15231f6d NB	120	USB_EN);
1b719e66	121	} else {
15231f6d NB	122	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
	123	PHY_CLK_SEL_ULPI);
	124	clrsetbits_be32(&ehci->control, UTMI_PHY_EN \|
	125	CONTROL_REGISTER_W1C_MASK, USB_EN);
1b719e66	126	udelay(1000); /* delay required for PHY Clk to appear */
047cea36 SL	127	if (!usb_phy_clk_valid(ehci))
047cea36 SL	128	return -EINVAL;
676ae068	129	out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
1b719e66	130	}
6b92487d	131
08066152 VM	132	out_be32(&ehci->prictrl, 0x0000000c);
	133	out_be32(&ehci->age_cnt_limit, 0x00000040);
	134	out_be32(&ehci->sictrl, 0x00000001);
6b92487d	135
08066152	136	in_le32(&ehci->usbmode);
6b92487d	137
f3dff695	138	if (has_erratum_a007798())
896720ce NB	139	set_txfifothresh(ehci, TXFIFOTHRESH);
896720ce NB	140
6b92487d MT	141	return 0;
	142	}
	143
	144	/*
	145	* Destroy the appropriate control structures corresponding
	146	* the the EHCI host controller.
	147	*/
676ae068	148	int ehci_hcd_stop(int index)
6b92487d MT	149	{
	150	return 0;
	151	}
896720ce NB	152
	153	/*
	154	* Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
	155	* to counter DDR latencies in writing data into Tx buffer.
	156	* This prevents Tx buffer from getting underrun
	157	*/
	158	static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
	159	{
	160	u32 cmd;
	161	cmd = ehci_readl(&ehci->txfilltuning);
	162	cmd &= ~TXFIFO_THRESH_MASK;
	163	cmd \|= TXFIFO_THRESH(txfifo_thresh);
	164	ehci_writel(&ehci->txfilltuning, cmd);
	165	}
a1c04e27 NB	166
	167	#if defined(CONFIG_HAS_FSL_DR_USB) \|\| defined(CONFIG_HAS_FSL_MPH_USB)
	168	static int fdt_fixup_usb_mode_phy_type(void blob, const char mode,
	169	const char *phy_type, int start_offset)
	170	{
	171	const char *compat_dr = "fsl-usb2-dr";
	172	const char *compat_mph = "fsl-usb2-mph";
	173	const char *prop_mode = "dr_mode";
	174	const char *prop_type = "phy_type";
	175	const char *node_type = NULL;
	176	int node_offset;
	177	int err;
	178
	179	node_offset = fdt_node_offset_by_compatible(blob,
	180	start_offset, compat_mph);
	181	if (node_offset < 0) {
	182	node_offset = fdt_node_offset_by_compatible(blob,
	183	start_offset,
	184	compat_dr);
	185	if (node_offset < 0) {
	186	printf("WARNING: could not find compatible node: %s",
	187	fdt_strerror(node_offset));
	188	return -1;
	189	}
	190	node_type = compat_dr;
	191	} else {
	192	node_type = compat_mph;
	193	}
	194
	195	if (mode) {
	196	err = fdt_setprop(blob, node_offset, prop_mode, mode,
	197	strlen(mode) + 1);
	198	if (err < 0)
	199	printf("WARNING: could not set %s for %s: %s.\n",
	200	prop_mode, node_type, fdt_strerror(err));
	201	}
	202
	203	if (phy_type) {
	204	err = fdt_setprop(blob, node_offset, prop_type, phy_type,
	205	strlen(phy_type) + 1);
	206	if (err < 0)
	207	printf("WARNING: could not set %s for %s: %s.\n",
	208	prop_type, node_type, fdt_strerror(err));
	209	}
	210
	211	return node_offset;
	212	}
	213
	214	void fdt_fixup_dr_usb(void blob, bd_t bd)
	215	{
	216	static const char * const modes[] = { "host", "peripheral", "otg" };
	217	static const char * const phys[] = { "ulpi", "utmi" };
	218	int usb_mode_off = -1;
	219	int usb_phy_off = -1;
	220	char str[5];
	221	int i, j;
	222
	223	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
	224	const char *dr_mode_type = NULL;
	225	const char *dr_phy_type = NULL;
	226	int mode_idx = -1, phy_idx = -1;
	227
	228	snprintf(str, 5, "%s%d", "usb", i);
	229	if (hwconfig(str)) {
230	for (j = 0; j < ARRAY_SIZE(modes); j++) {
231	if (hwconfig_subarg_cmp(str, "dr_mode",
232	modes[j])) {
233	mode_idx = j;
234	break;
235	}
236	}
237
238	for (j = 0; j < ARRAY_SIZE(phys); j++) {
239	if (hwconfig_subarg_cmp(str, "phy_type",
240	phys[j])) {
241	phy_idx = j;
242	break;
243	}
244	}
245
246	if (mode_idx < 0 && phy_idx < 0) {
247	printf("WARNING: invalid phy or mode\n");
248	return;
249	}
250
251	if (mode_idx > -1)
252	dr_mode_type = modes[mode_idx];
253
254	if (phy_idx > -1)
255	dr_phy_type = phys[phy_idx];
256	}
257
258	usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
259	dr_mode_type, NULL,
260	usb_mode_off);
261
262	if (usb_mode_off < 0)
263	return;
264
265	usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
266	NULL, dr_phy_type,
267	usb_phy_off);
268
269	if (usb_phy_off < 0)
270	return;
271	}
272	}
273	#endif