[thirdparty/u-boot.git] / drivers / usb / host / ehci-mxs.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale i.MX28 USB Host driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <errno.h>
#include <linux/delay.h>
#include <dm.h>
#include <power/regulator.h>

#include "ehci.h"

/* This DIGCTL register ungates clock to USB */
#define	HW_DIGCTL_CTRL			0x8001c000
#define	HW_DIGCTL_CTRL_USB0_CLKGATE	(1 << 2)
#define	HW_DIGCTL_CTRL_USB1_CLKGATE	(1 << 16)

struct ehci_mxs_port {
	uint32_t		usb_regs;
	struct mxs_usbphy_regs	*phy_regs;

	struct mxs_register_32	*pll;
	uint32_t		pll_en_bits;
	uint32_t		pll_dis_bits;
	uint32_t		gate_bits;
};

static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
{
	struct mxs_register_32 *digctl_ctrl =
		(struct mxs_register_32 *)HW_DIGCTL_CTRL;
	int pll_offset, dig_offset;

	if (enable) {
		pll_offset = offsetof(struct mxs_register_32, reg_set);
		dig_offset = offsetof(struct mxs_register_32, reg_clr);
		writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
		writel(port->pll_en_bits, (u32)port->pll + pll_offset);
	} else {
		pll_offset = offsetof(struct mxs_register_32, reg_clr);
		dig_offset = offsetof(struct mxs_register_32, reg_set);
		writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
		writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
	}

	return 0;
}

static int __ehci_hcd_init(struct ehci_mxs_port *port, enum usb_init_type init,
			   struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	u32 usb_base, cap_base;
	int ret;

	/* Reset the PHY block */
	writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
	udelay(10);
	writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
	       &port->phy_regs->hw_usbphy_ctrl_clr);

	/* Enable USB clock */
	ret = ehci_mxs_toggle_clock(port, 1);
	if (ret)
		return ret;

	/* Start USB PHY */
	writel(0, &port->phy_regs->hw_usbphy_pwd);

	/* Enable UTMI+ Level 2 and Level 3 compatibility */
	writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
	       &port->phy_regs->hw_usbphy_ctrl_set);

	usb_base = port->usb_regs + 0x100;
	*hccr = (struct ehci_hccr *)usb_base;

	cap_base = ehci_readl(&(*hccr)->cr_capbase);
	*hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));

	return 0;
}

static int __ehci_hcd_stop(struct ehci_mxs_port *port)
{
	u32 usb_base, cap_base, tmp;
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;

	/* Stop the USB port */
	usb_base = port->usb_regs + 0x100;
	hccr = (struct ehci_hccr *)usb_base;
	cap_base = ehci_readl(&hccr->cr_capbase);
	hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));

	tmp = ehci_readl(&hcor->or_usbcmd);
	tmp &= ~CMD_RUN;
	ehci_writel(&hcor->or_usbcmd, tmp);

	/* Disable the PHY */
	tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
		USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
		USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
		USBPHY_PWD_TXPWDFS;
	writel(tmp, &port->phy_regs->hw_usbphy_pwd);

	/* Disable USB clock */
	return ehci_mxs_toggle_clock(port, 0);
}

struct ehci_mxs_priv_data {
	struct ehci_ctrl ctrl;
	struct usb_ehci *ehci;
	struct udevice *vbus_supply;
	struct ehci_mxs_port port;
	enum usb_init_type init_type;
};

/*
 * Below defines correspond to imx28 clk Linux (v5.15.y)
 * clock driver to provide proper offset for PHY[01]
 * devices.
 */
#define CLK_USB_PHY0 62
#define CLK_USB_PHY1 63
#define PLL0CTRL0(base) ((base) + 0x0000)
#define PLL1CTRL0(base) ((base) + 0x0020)

static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
	struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
	struct usb_plat *plat = dev_get_plat(dev);
	struct ehci_mxs_port *port = &priv->port;
	u32 phandle, phy_reg, clk_reg, clk_id;
	ofnode np = dev_ofnode(dev);
	ofnode phy_node, clk_node;
	const char *mode;
	int ret;

	mode = ofnode_read_string(np, "dr_mode");
	if (mode) {
		if (strcmp(mode, "peripheral") == 0)
			plat->init_type = USB_INIT_DEVICE;
		else if (strcmp(mode, "host") == 0)
			plat->init_type = USB_INIT_HOST;
		else
			return -EINVAL;
	}

	/* Read base address of the USB IP block */
	ret = ofnode_read_u32(np, "reg", &port->usb_regs);
	if (ret)
		return ret;

	/* Read base address of the USB PHY IP block */
	ret = ofnode_read_u32(np, "fsl,usbphy", &phandle);
	if (ret)
		return ret;

	phy_node = ofnode_get_by_phandle(phandle);
	if (!ofnode_valid(phy_node))
		return -ENODEV;

	ret = ofnode_read_u32(phy_node, "reg", &phy_reg);
	if (ret)
		return ret;

	port->phy_regs = (struct mxs_usbphy_regs *)phy_reg;

	/* Read base address of the CLK IP block and proper ID */
	ret = ofnode_read_u32_index(phy_node, "clocks", 0, &phandle);
	if (ret)
		return ret;

	ret = ofnode_read_u32_index(phy_node, "clocks", 1, &clk_id);
	if (ret)
		return ret;

	clk_node = ofnode_get_by_phandle(phandle);
	if (!ofnode_valid(clk_node))
		return -ENODEV;

	ret = ofnode_read_u32(clk_node, "reg", &clk_reg);
	if (ret)
		return ret;

	port->pll = (struct mxs_register_32 *)clk_reg;

	/* Provide proper offset for USB PHY clocks */
	if (clk_id == CLK_USB_PHY0)
		port->pll = PLL0CTRL0(port->pll);

	if (clk_id == CLK_USB_PHY1)
		port->pll = PLL1CTRL0(port->pll);

	debug("%s: pll_reg: 0x%p clk_id: %d\n", __func__, port->pll, clk_id);
	/*
	 * On the imx28 the values provided by CLKCTRL_PLL0* defines to are the
	 * same as ones for CLKCTRL_PLL1*. As a result the former can be used
	 * for both ports - i.e. (usb[01]).
	 */
	port->pll_en_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS |
		CLKCTRL_PLL0CTRL0_POWER;
	port->pll_dis_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS;
	port->gate_bits = HW_DIGCTL_CTRL_USB0_CLKGATE;

	return 0;
}

static int ehci_usb_probe(struct udevice *dev)
{
	struct usb_plat *plat = dev_get_plat(dev);
	struct usb_ehci *ehci = dev_read_addr_ptr(dev);
	struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
	struct ehci_mxs_port *port = &priv->port;
	enum usb_init_type type = plat->init_type;
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;
	int ret;

	priv->ehci = ehci;
	priv->init_type = type;

	debug("%s: USB type: %s  reg: 0x%x phy_reg 0x%p\n", __func__,
	      type == USB_INIT_HOST ? "HOST" : "DEVICE", port->usb_regs,
	      (uint32_t *)port->phy_regs);

#if CONFIG_IS_ENABLED(DM_REGULATOR)
	ret = device_get_supply_regulator(dev, "vbus-supply",
					  &priv->vbus_supply);
	if (ret)
		debug("%s: No vbus supply\n", dev->name);

	if (!ret && priv->vbus_supply) {
		ret = regulator_set_enable_if_allowed(priv->vbus_supply,
						      (type == USB_INIT_DEVICE) ?
						      false : true);
		if (ret) {
			puts("Error enabling VBUS supply\n");
			return ret;
		}
	}
#endif
	ret = __ehci_hcd_init(port, type, &hccr, &hcor);
	if (ret)
		return ret;

	mdelay(10);
	return ehci_register(dev, hccr, hcor, NULL, 0, priv->init_type);
}

static int ehci_usb_remove(struct udevice *dev)
{
	struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
	struct ehci_mxs_port *port = &priv->port;
	int ret;

	ret =  ehci_deregister(dev);
	if (ret)
		return ret;

#if CONFIG_IS_ENABLED(DM_REGULATOR)
	if (priv->vbus_supply) {
		ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
		if (ret) {
			puts("Error disabling VBUS supply\n");
			return ret;
		}
	}
#endif
	return __ehci_hcd_stop(port);
}

static const struct udevice_id mxs_usb_ids[] = {
	{ .compatible = "fsl,imx28-usb" },
	{ }
};

U_BOOT_DRIVER(usb_mxs) = {
	.name	= "ehci_mxs",
	.id	= UCLASS_USB,
	.of_match = mxs_usb_ids,
	.of_to_plat = ehci_usb_ofdata_to_platdata,
	.probe	= ehci_usb_probe,
	.remove = ehci_usb_remove,
	.ops	= &ehci_usb_ops,
	.plat_auto = sizeof(struct usb_plat),
	.priv_auto = sizeof(struct ehci_mxs_priv_data),
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dbb8f279 MV	2	/*
	3	* Freescale i.MX28 USB Host driver
	4	*
	5	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	6	* on behalf of DENX Software Engineering GmbH
dbb8f279 MV	7	*/
dbb8f279 MV	8
d678a59d	9	#include <common.h>
dbb8f279	10	#include <asm/io.h>
47f13315	11	#include <asm/arch/imx-regs.h>
afa87210	12	#include <errno.h>
c05ed00a	13	#include <linux/delay.h>
07791e8d LM	14	#include <dm.h>
07791e8d LM	15	#include <power/regulator.h>
dbb8f279	16
dbb8f279 MV	17	#include "ehci.h"
dbb8f279 MV	18
afa87210 MV	19	/* This DIGCTL register ungates clock to USB */
	20	#define HW_DIGCTL_CTRL 0x8001c000
	21	#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
	22	#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
dbb8f279	23
afa87210 MV	24	struct ehci_mxs_port {
afa87210 MV	25	uint32_t usb_regs;
9c471142	26	struct mxs_usbphy_regs *phy_regs;
dbb8f279	27
afa87210 MV	28	struct mxs_register_32 *pll;
	29	uint32_t pll_en_bits;
	30	uint32_t pll_dis_bits;
	31	uint32_t gate_bits;
	32	};
	33
fc313d34 LM	34	static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
	35	{
	36	struct mxs_register_32 *digctl_ctrl =
	37	(struct mxs_register_32 *)HW_DIGCTL_CTRL;
	38	int pll_offset, dig_offset;
	39
	40	if (enable) {
	41	pll_offset = offsetof(struct mxs_register_32, reg_set);
	42	dig_offset = offsetof(struct mxs_register_32, reg_clr);
	43	writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
	44	writel(port->pll_en_bits, (u32)port->pll + pll_offset);
	45	} else {
	46	pll_offset = offsetof(struct mxs_register_32, reg_clr);
	47	dig_offset = offsetof(struct mxs_register_32, reg_set);
	48	writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
	49	writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
	50	}
	51
	52	return 0;
	53	}
	54
2d431e33 LM	55	static int __ehci_hcd_init(struct ehci_mxs_port *port, enum usb_init_type init,
	56	struct ehci_hccr hccr, struct ehci_hcor hcor)
	57	{
	58	u32 usb_base, cap_base;
	59	int ret;
	60
	61	/* Reset the PHY block */
	62	writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
	63	udelay(10);
	64	writel(USBPHY_CTRL_SFTRST \| USBPHY_CTRL_CLKGATE,
	65	&port->phy_regs->hw_usbphy_ctrl_clr);
	66
	67	/* Enable USB clock */
	68	ret = ehci_mxs_toggle_clock(port, 1);
	69	if (ret)
	70	return ret;
	71
	72	/* Start USB PHY */
	73	writel(0, &port->phy_regs->hw_usbphy_pwd);
	74
	75	/* Enable UTMI+ Level 2 and Level 3 compatibility */
	76	writel(USBPHY_CTRL_ENUTMILEVEL3 \| USBPHY_CTRL_ENUTMILEVEL2 \| 1,
	77	&port->phy_regs->hw_usbphy_ctrl_set);
	78
	79	usb_base = port->usb_regs + 0x100;
	80	hccr = (struct ehci_hccr )usb_base;
	81
	82	cap_base = ehci_readl(&(*hccr)->cr_capbase);
	83	hcor = (struct ehci_hcor )(usb_base + HC_LENGTH(cap_base));
	84
	85	return 0;
	86	}
	87
	88	static int __ehci_hcd_stop(struct ehci_mxs_port *port)
	89	{
	90	u32 usb_base, cap_base, tmp;
	91	struct ehci_hccr *hccr;
	92	struct ehci_hcor *hcor;
	93
	94	/* Stop the USB port */
	95	usb_base = port->usb_regs + 0x100;
	96	hccr = (struct ehci_hccr *)usb_base;
	97	cap_base = ehci_readl(&hccr->cr_capbase);
	98	hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
	99
	100	tmp = ehci_readl(&hcor->or_usbcmd);
	101	tmp &= ~CMD_RUN;
	102	ehci_writel(&hcor->or_usbcmd, tmp);
	103
	104	/* Disable the PHY */
	105	tmp = USBPHY_PWD_RXPWDRX \| USBPHY_PWD_RXPWDDIFF \|
	106	USBPHY_PWD_RXPWD1PT1 \| USBPHY_PWD_RXPWDENV \|
	107	USBPHY_PWD_TXPWDV2I \| USBPHY_PWD_TXPWDIBIAS \|
	108	USBPHY_PWD_TXPWDFS;
	109	writel(tmp, &port->phy_regs->hw_usbphy_pwd);
	110
	111	/* Disable USB clock */
	112	return ehci_mxs_toggle_clock(port, 0);
	113	}
	114
07791e8d LM	115	struct ehci_mxs_priv_data {
	116	struct ehci_ctrl ctrl;
	117	struct usb_ehci *ehci;
	118	struct udevice *vbus_supply;
	119	struct ehci_mxs_port port;
	120	enum usb_init_type init_type;
	121	};
	122
	123	/*
	124	* Below defines correspond to imx28 clk Linux (v5.15.y)
	125	* clock driver to provide proper offset for PHY[01]
	126	* devices.
	127	*/
	128	#define CLK_USB_PHY0 62
	129	#define CLK_USB_PHY1 63
	130	#define PLL0CTRL0(base) ((base) + 0x0000)
	131	#define PLL1CTRL0(base) ((base) + 0x0020)
	132
	133	static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
	134	{
	135	struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
	136	struct usb_plat *plat = dev_get_plat(dev);
	137	struct ehci_mxs_port *port = &priv->port;
	138	u32 phandle, phy_reg, clk_reg, clk_id;
2bcfae22	139	ofnode np = dev_ofnode(dev);
07791e8d LM	140	ofnode phy_node, clk_node;
	141	const char *mode;
	142	int ret;
	143
2bcfae22	144	mode = ofnode_read_string(np, "dr_mode");
07791e8d LM	145	if (mode) {
	146	if (strcmp(mode, "peripheral") == 0)
	147	plat->init_type = USB_INIT_DEVICE;
	148	else if (strcmp(mode, "host") == 0)
	149	plat->init_type = USB_INIT_HOST;
	150	else
	151	return -EINVAL;
	152	}
	153
	154	/* Read base address of the USB IP block */
2bcfae22	155	ret = ofnode_read_u32(np, "reg", &port->usb_regs);
07791e8d LM	156	if (ret)
	157	return ret;
	158
	159	/* Read base address of the USB PHY IP block */
2bcfae22	160	ret = ofnode_read_u32(np, "fsl,usbphy", &phandle);
07791e8d LM	161	if (ret)
	162	return ret;
	163
	164	phy_node = ofnode_get_by_phandle(phandle);
	165	if (!ofnode_valid(phy_node))
	166	return -ENODEV;
	167
	168	ret = ofnode_read_u32(phy_node, "reg", &phy_reg);
	169	if (ret)
	170	return ret;
	171
	172	port->phy_regs = (struct mxs_usbphy_regs *)phy_reg;
	173
	174	/* Read base address of the CLK IP block and proper ID */
	175	ret = ofnode_read_u32_index(phy_node, "clocks", 0, &phandle);
	176	if (ret)
	177	return ret;
	178
	179	ret = ofnode_read_u32_index(phy_node, "clocks", 1, &clk_id);
	180	if (ret)
	181	return ret;
	182
	183	clk_node = ofnode_get_by_phandle(phandle);
	184	if (!ofnode_valid(clk_node))
	185	return -ENODEV;
	186
	187	ret = ofnode_read_u32(clk_node, "reg", &clk_reg);
	188	if (ret)
	189	return ret;
	190
	191	port->pll = (struct mxs_register_32 *)clk_reg;
	192
	193	/* Provide proper offset for USB PHY clocks */
	194	if (clk_id == CLK_USB_PHY0)
	195	port->pll = PLL0CTRL0(port->pll);
	196
	197	if (clk_id == CLK_USB_PHY1)
	198	port->pll = PLL1CTRL0(port->pll);
	199
	200	debug("%s: pll_reg: 0x%p clk_id: %d\n", __func__, port->pll, clk_id);
	201	/*
	202	* On the imx28 the values provided by CLKCTRL_PLL0* defines to are the
	203	* same as ones for CLKCTRL_PLL1*. As a result the former can be used
	204	* for both ports - i.e. (usb[01]).
	205	*/
	206	port->pll_en_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS \|
	207	CLKCTRL_PLL0CTRL0_POWER;
	208	port->pll_dis_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS;
	209	port->gate_bits = HW_DIGCTL_CTRL_USB0_CLKGATE;
	210
	211	return 0;
	212	}
	213
	214	static int ehci_usb_probe(struct udevice *dev)
	215	{
	216	struct usb_plat *plat = dev_get_plat(dev);
	217	struct usb_ehci *ehci = dev_read_addr_ptr(dev);
	218	struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
	219	struct ehci_mxs_port *port = &priv->port;
	220	enum usb_init_type type = plat->init_type;
	221	struct ehci_hccr *hccr;
	222	struct ehci_hcor *hcor;
	223	int ret;
	224
225	priv->ehci = ehci;
226	priv->init_type = type;
227
228	debug("%s: USB type: %s reg: 0x%x phy_reg 0x%p\n", __func__,
229	type == USB_INIT_HOST ? "HOST" : "DEVICE", port->usb_regs,
230	(uint32_t *)port->phy_regs);
231
232	#if CONFIG_IS_ENABLED(DM_REGULATOR)
233	ret = device_get_supply_regulator(dev, "vbus-supply",
234	&priv->vbus_supply);
235	if (ret)
236	debug("%s: No vbus supply\n", dev->name);
237
238	if (!ret && priv->vbus_supply) {
7478c84f FE	239	ret = regulator_set_enable_if_allowed(priv->vbus_supply,
	240	(type == USB_INIT_DEVICE) ?
	241	false : true);
07791e8d LM	242	if (ret) {
	243	puts("Error enabling VBUS supply\n");
	244	return ret;
	245	}
	246	}
	247	#endif
	248	ret = __ehci_hcd_init(port, type, &hccr, &hcor);
	249	if (ret)
	250	return ret;
	251
	252	mdelay(10);
	253	return ehci_register(dev, hccr, hcor, NULL, 0, priv->init_type);
	254	}
	255
	256	static int ehci_usb_remove(struct udevice *dev)
	257	{
	258	struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
	259	struct ehci_mxs_port *port = &priv->port;
	260	int ret;
	261
	262	ret = ehci_deregister(dev);
	263	if (ret)
	264	return ret;
	265
	266	#if CONFIG_IS_ENABLED(DM_REGULATOR)
	267	if (priv->vbus_supply) {
7478c84f	268	ret = regulator_set_enable_if_allowed(priv->vbus_supply, false);
07791e8d LM	269	if (ret) {
	270	puts("Error disabling VBUS supply\n");
	271	return ret;
	272	}
	273	}
	274	#endif
	275	return __ehci_hcd_stop(port);
	276	}
	277
	278	static const struct udevice_id mxs_usb_ids[] = {
	279	{ .compatible = "fsl,imx28-usb" },
	280	{ }
	281	};
	282
	283	U_BOOT_DRIVER(usb_mxs) = {
	284	.name = "ehci_mxs",
	285	.id = UCLASS_USB,
	286	.of_match = mxs_usb_ids,
	287	.of_to_plat = ehci_usb_ofdata_to_platdata,
	288	.probe = ehci_usb_probe,
	289	.remove = ehci_usb_remove,
	290	.ops = &ehci_usb_ops,
	291	.plat_auto = sizeof(struct usb_plat),
	292	.priv_auto = sizeof(struct ehci_mxs_priv_data),
	293	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	294	};