[thirdparty/u-boot.git] / drivers / usb / host / xhci-rcar.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
 *
 * Renesas RCar USB HOST xHCI Controller
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <malloc.h>
#include <usb.h>
#include <wait_bit.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>

#include <usb/xhci.h>
#include "xhci-rcar-r8a779x_usb3_v3.h"

/* Register Offset */
#define RCAR_USB3_DL_CTRL	0x250	/* FW Download Control & Status */
#define RCAR_USB3_FW_DATA0	0x258	/* FW Data0 */

/* Register Settings */
/* FW Download Control & Status */
#define RCAR_USB3_DL_CTRL_ENABLE	BIT(0)
#define RCAR_USB3_DL_CTRL_FW_SUCCESS	BIT(4)
#define RCAR_USB3_DL_CTRL_FW_SET_DATA0	BIT(8)

struct rcar_xhci_plat {
	fdt_addr_t	hcd_base;
	struct clk	clk;
};

/**
 * Contains pointers to register base addresses
 * for the usb controller.
 */
struct rcar_xhci {
	struct xhci_ctrl ctrl;	/* Needs to come first in this struct! */
	struct usb_plat usb_plat;
	struct xhci_hccr *hcd;
};

static int xhci_rcar_download_fw(struct rcar_xhci *ctx, const u32 *fw_data,
				 const size_t fw_array_size)
{
	void __iomem *regs = (void __iomem *)ctx->hcd;
	int i, ret;

	/* Download R-Car USB3.0 firmware */
	setbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);

	for (i = 0; i < fw_array_size; i++) {
		writel(fw_data[i], regs + RCAR_USB3_FW_DATA0);
		setbits_le32(regs + RCAR_USB3_DL_CTRL,
			     RCAR_USB3_DL_CTRL_FW_SET_DATA0);

		ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
					RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
					10, false);
		if (ret)
			break;
	}

	clrbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);

	ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
				RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
				10, false);

	return ret;
}

static int xhci_rcar_probe(struct udevice *dev)
{
	struct rcar_xhci_plat *plat = dev_get_plat(dev);
	struct rcar_xhci *ctx = dev_get_priv(dev);
	struct xhci_hcor *hcor;
	int len, ret;

	ret = clk_get_by_index(dev, 0, &plat->clk);
	if (ret < 0) {
		dev_err(dev, "Failed to get USB3 clock\n");
		return ret;
	}

	ret = clk_enable(&plat->clk);
	if (ret) {
		dev_err(dev, "Failed to enable USB3 clock\n");
		return ret;
	}

	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
	len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
	hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);

	ret = xhci_rcar_download_fw(ctx, firmware_r8a779x_usb3_v3,
				    ARRAY_SIZE(firmware_r8a779x_usb3_v3));
	if (ret) {
		dev_err(dev, "Failed to download firmware\n");
		goto err_fw;
	}

	ret = xhci_register(dev, ctx->hcd, hcor);
	if (ret) {
		dev_err(dev, "Failed to register xHCI\n");
		goto err_fw;
	}

	return 0;

err_fw:
	clk_disable(&plat->clk);
	return ret;
}

static int xhci_rcar_deregister(struct udevice *dev)
{
	int ret;
	struct rcar_xhci_plat *plat = dev_get_plat(dev);

	ret = xhci_deregister(dev);

	clk_disable(&plat->clk);

	return ret;
}

static int xhci_rcar_of_to_plat(struct udevice *dev)
{
	struct rcar_xhci_plat *plat = dev_get_plat(dev);

	plat->hcd_base = dev_read_addr(dev);
	if (plat->hcd_base == FDT_ADDR_T_NONE) {
		debug("Can't get the XHCI register base address\n");
		return -ENXIO;
	}

	return 0;
}

static const struct udevice_id xhci_rcar_ids[] = {
	{ .compatible = "renesas,rcar-gen3-xhci" },
	{ .compatible = "renesas,xhci-r8a7795" },
	{ .compatible = "renesas,xhci-r8a7796" },
	{ .compatible = "renesas,xhci-r8a77965" },
	{ }
};

U_BOOT_DRIVER(usb_xhci) = {
	.name		= "xhci_rcar",
	.id		= UCLASS_USB,
	.probe		= xhci_rcar_probe,
	.remove		= xhci_rcar_deregister,
	.ops		= &xhci_usb_ops,
	.of_match	= xhci_rcar_ids,
	.of_to_plat = xhci_rcar_of_to_plat,
	.plat_auto	= sizeof(struct rcar_xhci_plat),
	.priv_auto	= sizeof(struct rcar_xhci),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e1cc60c0 MV	2	/*
	3	* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
	4	*
	5	* Renesas RCar USB HOST xHCI Controller
e1cc60c0 MV	6	*/
e1cc60c0 MV	7
d678a59d	8	#include <common.h>
e1cc60c0 MV	9	#include <clk.h>
	10	#include <dm.h>
	11	#include <fdtdec.h>
f7ae49fc	12	#include <log.h>
336d4615	13	#include <malloc.h>
e1cc60c0 MV	14	#include <usb.h>
e1cc60c0 MV	15	#include <wait_bit.h>
336d4615	16	#include <dm/device_compat.h>
cd93d625	17	#include <linux/bitops.h>
e1cc60c0	18
1708a123	19	#include <usb/xhci.h>
e1cc60c0 MV	20	#include "xhci-rcar-r8a779x_usb3_v3.h"
	21
	22	/* Register Offset */
	23	#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
	24	#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
	25
	26	/* Register Settings */
	27	/* FW Download Control & Status */
	28	#define RCAR_USB3_DL_CTRL_ENABLE BIT(0)
	29	#define RCAR_USB3_DL_CTRL_FW_SUCCESS BIT(4)
	30	#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 BIT(8)
	31
8a8d24bd	32	struct rcar_xhci_plat {
e1cc60c0 MV	33	fdt_addr_t hcd_base;
	34	struct clk clk;
	35	};
	36
	37	/**
	38	* Contains pointers to register base addresses
	39	* for the usb controller.
	40	*/
	41	struct rcar_xhci {
	42	struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
8a8d24bd	43	struct usb_plat usb_plat;
e1cc60c0 MV	44	struct xhci_hccr *hcd;
	45	};
	46
	47	static int xhci_rcar_download_fw(struct rcar_xhci ctx, const u32 fw_data,
	48	const size_t fw_array_size)
	49	{
	50	void __iomem regs = (void __iomem )ctx->hcd;
	51	int i, ret;
	52
	53	/* Download R-Car USB3.0 firmware */
	54	setbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
	55
	56	for (i = 0; i < fw_array_size; i++) {
	57	writel(fw_data[i], regs + RCAR_USB3_FW_DATA0);
	58	setbits_le32(regs + RCAR_USB3_DL_CTRL,
	59	RCAR_USB3_DL_CTRL_FW_SET_DATA0);
	60
48263504 ÁFR	61	ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
	62	RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
	63	10, false);
e1cc60c0 MV	64	if (ret)
	65	break;
	66	}
	67
	68	clrbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
	69
48263504 ÁFR	70	ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
	71	RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
	72	10, false);
e1cc60c0 MV	73
	74	return ret;
	75	}
	76
	77	static int xhci_rcar_probe(struct udevice *dev)
	78	{
8a8d24bd	79	struct rcar_xhci_plat *plat = dev_get_plat(dev);
e1cc60c0 MV	80	struct rcar_xhci *ctx = dev_get_priv(dev);
	81	struct xhci_hcor *hcor;
	82	int len, ret;
	83
	84	ret = clk_get_by_index(dev, 0, &plat->clk);
	85	if (ret < 0) {
	86	dev_err(dev, "Failed to get USB3 clock\n");
	87	return ret;
	88	}
	89
	90	ret = clk_enable(&plat->clk);
	91	if (ret) {
	92	dev_err(dev, "Failed to enable USB3 clock\n");
c9309f40	93	return ret;
e1cc60c0 MV	94	}
	95
	96	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
	97	len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
	98	hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
	99
	100	ret = xhci_rcar_download_fw(ctx, firmware_r8a779x_usb3_v3,
	101	ARRAY_SIZE(firmware_r8a779x_usb3_v3));
	102	if (ret) {
	103	dev_err(dev, "Failed to download firmware\n");
	104	goto err_fw;
	105	}
	106
	107	ret = xhci_register(dev, ctx->hcd, hcor);
	108	if (ret) {
	109	dev_err(dev, "Failed to register xHCI\n");
	110	goto err_fw;
	111	}
	112
	113	return 0;
	114
	115	err_fw:
	116	clk_disable(&plat->clk);
e1cc60c0 MV	117	return ret;
	118	}
	119
	120	static int xhci_rcar_deregister(struct udevice *dev)
	121	{
3f484226	122	int ret;
8a8d24bd	123	struct rcar_xhci_plat *plat = dev_get_plat(dev);
e1cc60c0	124
3f484226 MB	125	ret = xhci_deregister(dev);
3f484226 MB	126
e1cc60c0	127	clk_disable(&plat->clk);
e1cc60c0	128
3f484226	129	return ret;
e1cc60c0 MV	130	}
e1cc60c0 MV	131
d1998a9f	132	static int xhci_rcar_of_to_plat(struct udevice *dev)
e1cc60c0	133	{
8a8d24bd	134	struct rcar_xhci_plat *plat = dev_get_plat(dev);
e1cc60c0	135
2548493a	136	plat->hcd_base = dev_read_addr(dev);
e1cc60c0 MV	137	if (plat->hcd_base == FDT_ADDR_T_NONE) {
	138	debug("Can't get the XHCI register base address\n");
	139	return -ENXIO;
	140	}
	141
	142	return 0;
	143	}
	144
	145	static const struct udevice_id xhci_rcar_ids[] = {
e15e817f	146	{ .compatible = "renesas,rcar-gen3-xhci" },
e1cc60c0 MV	147	{ .compatible = "renesas,xhci-r8a7795" },
e1cc60c0 MV	148	{ .compatible = "renesas,xhci-r8a7796" },
4f0533ff	149	{ .compatible = "renesas,xhci-r8a77965" },
e1cc60c0 MV	150	{ }
	151	};
	152
	153	U_BOOT_DRIVER(usb_xhci) = {
	154	.name = "xhci_rcar",
	155	.id = UCLASS_USB,
	156	.probe = xhci_rcar_probe,
	157	.remove = xhci_rcar_deregister,
	158	.ops = &xhci_usb_ops,
	159	.of_match = xhci_rcar_ids,
d1998a9f	160	.of_to_plat = xhci_rcar_of_to_plat,
8a8d24bd	161	.plat_auto = sizeof(struct rcar_xhci_plat),
41575d8e	162	.priv_auto = sizeof(struct rcar_xhci),
e1cc60c0 MV	163	.flags = DM_FLAG_ALLOC_PRIV_DMA,
e1cc60c0 MV	164	};