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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / usb / musb-new / musb_core.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0
eb81955b
IY		 2/*
3 * MUSB OTG driver core code
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
eb81955b
IY		 8 */
9
10/*
11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
12 *
13 * This consists of a Host Controller Driver (HCD) and a peripheral
14 * controller driver implementing the "Gadget" API; OTG support is
15 * in the works. These are normal Linux-USB controller drivers which
16 * use IRQs and have no dedicated thread.
17 *
18 * This version of the driver has only been used with products from
19 * Texas Instruments. Those products integrate the Inventra logic
20 * with other DMA, IRQ, and bus modules, as well as other logic that
21 * needs to be reflected in this driver.
22 *
23 *
24 * NOTE: the original Mentor code here was pretty much a collection
25 * of mechanisms that don't seem to have been fully integrated/working
26 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
27 * Key open issues include:
28 *
29 * - Lack of host-side transaction scheduling, for all transfer types.
30 * The hardware doesn't do it; instead, software must.
31 *
32 * This is not an issue for OTG devices that don't support external
33 * hubs, but for more "normal" USB hosts it's a user issue that the
34 * "multipoint" support doesn't scale in the expected ways. That
35 * includes DaVinci EVM in a common non-OTG mode.
36 *
37 * * Control and bulk use dedicated endpoints, and there's as
38 * yet no mechanism to either (a) reclaim the hardware when
39 * peripherals are NAKing, which gets complicated with bulk
40 * endpoints, or (b) use more than a single bulk endpoint in
41 * each direction.
42 *
43 * RESULT: one device may be perceived as blocking another one.
44 *
45 * * Interrupt and isochronous will dynamically allocate endpoint
46 * hardware, but (a) there's no record keeping for bandwidth;
47 * (b) in the common case that few endpoints are available, there
48 * is no mechanism to reuse endpoints to talk to multiple devices.
49 *
50 * RESULT: At one extreme, bandwidth can be overcommitted in
51 * some hardware configurations, no faults will be reported.
52 * At the other extreme, the bandwidth capabilities which do
53 * exist tend to be severely undercommitted. You can't yet hook
54 * up both a keyboard and a mouse to an external USB hub.
55 */
56
57/*
58 * This gets many kinds of configuration information:
59 * - Kconfig for everything user-configurable
60 * - platform_device for addressing, irq, and platform_data
61 * - platform_data is mostly for board-specific informarion
62 * (plus recentrly, SOC or family details)
63 *
64 * Most of the conditional compilation will (someday) vanish.
65 */
66
eb81955b 67#ifndef __UBOOT__
f7ae49fc 68#include <log.h>
336d4615 69#include <dm/device_compat.h>
61b29b82 70#include <dm/devres.h>
eb81955b
IY		 71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/sched.h>
74#include <linux/slab.h>
75#include <linux/init.h>
76#include <linux/list.h>
77#include <linux/kobject.h>
78#include <linux/prefetch.h>
79#include <linux/platform_device.h>
80#include <linux/io.h>
81#else
d678a59d 82#include <common.h>
e010524b
SA		 83#include <dm.h>
84#include <dm/device_compat.h>
eb81955b 85#include <usb.h>
cd93d625 86#include <linux/bitops.h>
eb41d8a1 87#include <linux/bug.h>
1221ce45 88#include <linux/errno.h>
1e94b46f 89#include <linux/printk.h>
eb81955b
IY		 90#include <linux/usb/ch9.h>
91#include <linux/usb/gadget.h>
92#include <linux/usb/musb.h>
b2d2b787 93#include <linux/usb/usb_urb_compat.h>
eb81955b
IY		 94#include <asm/io.h>
95#include "linux-compat.h"
eb81955b
IY		 96#endif
97
98#include "musb_core.h"
99
100#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
101
102
103#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
104#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
105
106#define MUSB_VERSION "6.0"
107
108#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
109
110#define MUSB_DRIVER_NAME "musb-hdrc"
111const char musb_driver_name[] = MUSB_DRIVER_NAME;
112
113MODULE_DESCRIPTION(DRIVER_INFO);
114MODULE_AUTHOR(DRIVER_AUTHOR);
115MODULE_LICENSE("GPL");
116MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
117
118
119#ifndef __UBOOT__
120/*-------------------------------------------------------------------------*/
121
122static inline struct musb *dev_to_musb(struct device *dev)
123{
124 return dev_get_drvdata(dev);
125}
eb81955b
IY		 126
127/*-------------------------------------------------------------------------*/
128
eb81955b
IY		 129static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
130{
131 void __iomem *addr = phy->io_priv;
132 int i = 0;
133 u8 r;
134 u8 power;
135 int ret;
136
137 pm_runtime_get_sync(phy->io_dev);
138
139 /* Make sure the transceiver is not in low power mode */
140 power = musb_readb(addr, MUSB_POWER);
141 power &= ~MUSB_POWER_SUSPENDM;
142 musb_writeb(addr, MUSB_POWER, power);
143
144 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
145 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
146 */
147
148 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
149 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
150 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
151
152 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
153 & MUSB_ULPI_REG_CMPLT)) {
154 i++;
155 if (i == 10000) {
156 ret = -ETIMEDOUT;
157 goto out;
158 }
159
160 }
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164
165 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
166
167out:
168 pm_runtime_put(phy->io_dev);
169
170 return ret;
171}
172
173static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
174{
175 void __iomem *addr = phy->io_priv;
176 int i = 0;
177 u8 r = 0;
178 u8 power;
179 int ret = 0;
180
181 pm_runtime_get_sync(phy->io_dev);
182
183 /* Make sure the transceiver is not in low power mode */
184 power = musb_readb(addr, MUSB_POWER);
185 power &= ~MUSB_POWER_SUSPENDM;
186 musb_writeb(addr, MUSB_POWER, power);
187
188 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
189 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
190 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
191
192 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
193 & MUSB_ULPI_REG_CMPLT)) {
194 i++;
195 if (i == 10000) {
196 ret = -ETIMEDOUT;
197 goto out;
198 }
199 }
200
201 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
202 r &= ~MUSB_ULPI_REG_CMPLT;
203 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
204
205out:
206 pm_runtime_put(phy->io_dev);
207
208 return ret;
209}
eb81955b
IY		 210
211static struct usb_phy_io_ops musb_ulpi_access = {
212 .read = musb_ulpi_read,
213 .write = musb_ulpi_write,
214};
215#endif
216
217/*-------------------------------------------------------------------------*/
218
ea3310e8 219#if !defined(CONFIG_USB_MUSB_TUSB6010)
eb81955b
IY		 220
221/*
222 * Load an endpoint's FIFO
223 */
224void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
225{
226 struct musb *musb = hw_ep->musb;
227 void __iomem *fifo = hw_ep->fifo;
228
229 prefetch((u8 *)src);
230
231 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
232 'T', hw_ep->epnum, fifo, len, src);
233
234 /* we can't assume unaligned reads work */
235 if (likely((0x01 & (unsigned long) src) == 0)) {
236 u16 index = 0;
237
238 /* best case is 32bit-aligned source address */
239 if ((0x02 & (unsigned long) src) == 0) {
240 if (len >= 4) {
241 writesl(fifo, src + index, len >> 2);
242 index += len & ~0x03;
243 }
244 if (len & 0x02) {
245 musb_writew(fifo, 0, *(u16 *)&src[index]);
246 index += 2;
247 }
248 } else {
249 if (len >= 2) {
250 writesw(fifo, src + index, len >> 1);
251 index += len & ~0x01;
252 }
253 }
254 if (len & 0x01)
255 musb_writeb(fifo, 0, src[index]);
256 } else {
257 /* byte aligned */
258 writesb(fifo, src, len);
259 }
260}
261
03b8e046 262#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
eb81955b
IY		 263/*
264 * Unload an endpoint's FIFO
265 */
266void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
267{
268 struct musb *musb = hw_ep->musb;
269 void __iomem *fifo = hw_ep->fifo;
270
271 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
272 'R', hw_ep->epnum, fifo, len, dst);
273
274 /* we can't assume unaligned writes work */
275 if (likely((0x01 & (unsigned long) dst) == 0)) {
276 u16 index = 0;
277
278 /* best case is 32bit-aligned destination address */
279 if ((0x02 & (unsigned long) dst) == 0) {
280 if (len >= 4) {
281 readsl(fifo, dst, len >> 2);
282 index = len & ~0x03;
283 }
284 if (len & 0x02) {
285 *(u16 *)&dst[index] = musb_readw(fifo, 0);
286 index += 2;
287 }
288 } else {
289 if (len >= 2) {
290 readsw(fifo, dst, len >> 1);
291 index = len & ~0x01;
292 }
293 }
294 if (len & 0x01)
295 dst[index] = musb_readb(fifo, 0);
296 } else {
297 /* byte aligned */
298 readsb(fifo, dst, len);
299 }
300}
301#endif
302
303#endif /* normal PIO */
304
305
306/*-------------------------------------------------------------------------*/
307
308/* for high speed test mode; see USB 2.0 spec 7.1.20 */
309static const u8 musb_test_packet[53] = {
310 /* implicit SYNC then DATA0 to start */
311
312 /* JKJKJKJK x9 */
313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
314 /* JJKKJJKK x8 */
315 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
316 /* JJJJKKKK x8 */
317 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
318 /* JJJJJJJKKKKKKK x8 */
319 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
320 /* JJJJJJJK x8 */
321 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
322 /* JKKKKKKK x10, JK */
323 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
324
325 /* implicit CRC16 then EOP to end */
326};
327
328void musb_load_testpacket(struct musb *musb)
329{
330 void __iomem *regs = musb->endpoints[0].regs;
331
332 musb_ep_select(musb->mregs, 0);
333 musb_write_fifo(musb->control_ep,
334 sizeof(musb_test_packet), musb_test_packet);
335 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
336}
337
338#ifndef __UBOOT__
339/*-------------------------------------------------------------------------*/
340
341/*
342 * Handles OTG hnp timeouts, such as b_ase0_brst
343 */
344void musb_otg_timer_func(unsigned long data)
345{
346 struct musb *musb = (struct musb *)data;
347 unsigned long flags;
348
349 spin_lock_irqsave(&musb->lock, flags);
350 switch (musb->xceiv->state) {
351 case OTG_STATE_B_WAIT_ACON:
352 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
353 musb_g_disconnect(musb);
354 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
355 musb->is_active = 0;
356 break;
357 case OTG_STATE_A_SUSPEND:
358 case OTG_STATE_A_WAIT_BCON:
359 dev_dbg(musb->controller, "HNP: %s timeout\n",
360 otg_state_string(musb->xceiv->state));
361 musb_platform_set_vbus(musb, 0);
362 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
363 break;
364 default:
365 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
366 otg_state_string(musb->xceiv->state));
367 }
368 musb->ignore_disconnect = 0;
369 spin_unlock_irqrestore(&musb->lock, flags);
370}
371
372/*
373 * Stops the HNP transition. Caller must take care of locking.
374 */
375void musb_hnp_stop(struct musb *musb)
376{
377 struct usb_hcd *hcd = musb_to_hcd(musb);
378 void __iomem *mbase = musb->mregs;
379 u8 reg;
380
381 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
382
383 switch (musb->xceiv->state) {
384 case OTG_STATE_A_PERIPHERAL:
385 musb_g_disconnect(musb);
386 dev_dbg(musb->controller, "HNP: back to %s\n",
387 otg_state_string(musb->xceiv->state));
388 break;
389 case OTG_STATE_B_HOST:
390 dev_dbg(musb->controller, "HNP: Disabling HR\n");
391 hcd->self.is_b_host = 0;
392 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
393 MUSB_DEV_MODE(musb);
394 reg = musb_readb(mbase, MUSB_POWER);
395 reg |= MUSB_POWER_SUSPENDM;
396 musb_writeb(mbase, MUSB_POWER, reg);
397 /* REVISIT: Start SESSION_REQUEST here? */
398 break;
399 default:
400 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
401 otg_state_string(musb->xceiv->state));
402 }
403
404 /*
405 * When returning to A state after HNP, avoid hub_port_rebounce(),
406 * which cause occasional OPT A "Did not receive reset after connect"
407 * errors.
408 */
409 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
410}
411#endif
412
413/*
414 * Interrupt Service Routine to record USB "global" interrupts.
415 * Since these do not happen often and signify things of
416 * paramount importance, it seems OK to check them individually;
417 * the order of the tests is specified in the manual
418 *
419 * @param musb instance pointer
420 * @param int_usb register contents
421 * @param devctl
422 * @param power
423 */
424
425static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
426 u8 devctl, u8 power)
427{
428#ifndef __UBOOT__
429 struct usb_otg *otg = musb->xceiv->otg;
430#endif
431 irqreturn_t handled = IRQ_NONE;
432
433 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
434 int_usb);
435
436#ifndef __UBOOT__
437 /* in host mode, the peripheral may issue remote wakeup.
438 * in peripheral mode, the host may resume the link.
439 * spurious RESUME irqs happen too, paired with SUSPEND.
440 */
441 if (int_usb & MUSB_INTR_RESUME) {
442 handled = IRQ_HANDLED;
443 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
444
445 if (devctl & MUSB_DEVCTL_HM) {
446 void __iomem *mbase = musb->mregs;
447
448 switch (musb->xceiv->state) {
449 case OTG_STATE_A_SUSPEND:
450 /* remote wakeup? later, GetPortStatus
451 * will stop RESUME signaling
452 */
453
454 if (power & MUSB_POWER_SUSPENDM) {
455 /* spurious */
456 musb->int_usb &= ~MUSB_INTR_SUSPEND;
457 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
458 break;
459 }
460
461 power &= ~MUSB_POWER_SUSPENDM;
462 musb_writeb(mbase, MUSB_POWER,
463 power | MUSB_POWER_RESUME);
464
465 musb->port1_status |=
466 (USB_PORT_STAT_C_SUSPEND << 16)
467 | MUSB_PORT_STAT_RESUME;
468 musb->rh_timer = jiffies
469 + msecs_to_jiffies(20);
470
471 musb->xceiv->state = OTG_STATE_A_HOST;
472 musb->is_active = 1;
473 usb_hcd_resume_root_hub(musb_to_hcd(musb));
474 break;
475 case OTG_STATE_B_WAIT_ACON:
476 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
477 musb->is_active = 1;
478 MUSB_DEV_MODE(musb);
479 break;
480 default:
481 WARNING("bogus %s RESUME (%s)\n",
482 "host",
483 otg_state_string(musb->xceiv->state));
484 }
485 } else {
486 switch (musb->xceiv->state) {
487 case OTG_STATE_A_SUSPEND:
488 /* possibly DISCONNECT is upcoming */
489 musb->xceiv->state = OTG_STATE_A_HOST;
490 usb_hcd_resume_root_hub(musb_to_hcd(musb));
491 break;
492 case OTG_STATE_B_WAIT_ACON:
493 case OTG_STATE_B_PERIPHERAL:
494 /* disconnect while suspended? we may
495 * not get a disconnect irq...
496 */
497 if ((devctl & MUSB_DEVCTL_VBUS)
498 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
499 ) {
500 musb->int_usb |= MUSB_INTR_DISCONNECT;
501 musb->int_usb &= ~MUSB_INTR_SUSPEND;
502 break;
503 }
504 musb_g_resume(musb);
505 break;
506 case OTG_STATE_B_IDLE:
507 musb->int_usb &= ~MUSB_INTR_SUSPEND;
508 break;
509 default:
510 WARNING("bogus %s RESUME (%s)\n",
511 "peripheral",
512 otg_state_string(musb->xceiv->state));
513 }
514 }
515 }
516
517 /* see manual for the order of the tests */
518 if (int_usb & MUSB_INTR_SESSREQ) {
519 void __iomem *mbase = musb->mregs;
520
521 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
522 && (devctl & MUSB_DEVCTL_BDEVICE)) {
523 dev_dbg(musb->controller, "SessReq while on B state\n");
524 return IRQ_HANDLED;
525 }
526
527 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
528 otg_state_string(musb->xceiv->state));
529
530 /* IRQ arrives from ID pin sense or (later, if VBUS power
531 * is removed) SRP. responses are time critical:
532 * - turn on VBUS (with silicon-specific mechanism)
533 * - go through A_WAIT_VRISE
534 * - ... to A_WAIT_BCON.
535 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
536 */
537 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
538 musb->ep0_stage = MUSB_EP0_START;
539 musb->xceiv->state = OTG_STATE_A_IDLE;
540 MUSB_HST_MODE(musb);
541 musb_platform_set_vbus(musb, 1);
542
543 handled = IRQ_HANDLED;
544 }
545
546 if (int_usb & MUSB_INTR_VBUSERROR) {
547 int ignore = 0;
548
549 /* During connection as an A-Device, we may see a short
550 * current spikes causing voltage drop, because of cable
551 * and peripheral capacitance combined with vbus draw.
552 * (So: less common with truly self-powered devices, where
553 * vbus doesn't act like a power supply.)
554 *
555 * Such spikes are short; usually less than ~500 usec, max
556 * of ~2 msec. That is, they're not sustained overcurrent
557 * errors, though they're reported using VBUSERROR irqs.
558 *
559 * Workarounds: (a) hardware: use self powered devices.
560 * (b) software: ignore non-repeated VBUS errors.
561 *
562 * REVISIT: do delays from lots of DEBUG_KERNEL checks
563 * make trouble here, keeping VBUS < 4.4V ?
564 */
565 switch (musb->xceiv->state) {
566 case OTG_STATE_A_HOST:
567 /* recovery is dicey once we've gotten past the
568 * initial stages of enumeration, but if VBUS
569 * stayed ok at the other end of the link, and
570 * another reset is due (at least for high speed,
571 * to redo the chirp etc), it might work OK...
572 */
573 case OTG_STATE_A_WAIT_BCON:
574 case OTG_STATE_A_WAIT_VRISE:
575 if (musb->vbuserr_retry) {
576 void __iomem *mbase = musb->mregs;
577
578 musb->vbuserr_retry--;
579 ignore = 1;
580 devctl |= MUSB_DEVCTL_SESSION;
581 musb_writeb(mbase, MUSB_DEVCTL, devctl);
582 } else {
583 musb->port1_status |=
584 USB_PORT_STAT_OVERCURRENT
585 | (USB_PORT_STAT_C_OVERCURRENT << 16);
586 }
587 break;
588 default:
589 break;
590 }
591
592 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
593 otg_state_string(musb->xceiv->state),
594 devctl,
595 ({ char *s;
596 switch (devctl & MUSB_DEVCTL_VBUS) {
597 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
598 s = "<SessEnd"; break;
599 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
600 s = "<AValid"; break;
601 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
602 s = "<VBusValid"; break;
603 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
604 default:
605 s = "VALID"; break;
606 }; s; }),
607 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
608 musb->port1_status);
609
610 /* go through A_WAIT_VFALL then start a new session */
611 if (!ignore)
612 musb_platform_set_vbus(musb, 0);
613 handled = IRQ_HANDLED;
614 }
615
616 if (int_usb & MUSB_INTR_SUSPEND) {
617 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
618 otg_state_string(musb->xceiv->state), devctl, power);
619 handled = IRQ_HANDLED;
620
621 switch (musb->xceiv->state) {
622 case OTG_STATE_A_PERIPHERAL:
623 /* We also come here if the cable is removed, since
624 * this silicon doesn't report ID-no-longer-grounded.
625 *
626 * We depend on T(a_wait_bcon) to shut us down, and
627 * hope users don't do anything dicey during this
628 * undesired detour through A_WAIT_BCON.
629 */
630 musb_hnp_stop(musb);
631 usb_hcd_resume_root_hub(musb_to_hcd(musb));
632 musb_root_disconnect(musb);
633 musb_platform_try_idle(musb, jiffies
634 + msecs_to_jiffies(musb->a_wait_bcon
635 ? : OTG_TIME_A_WAIT_BCON));
636
637 break;
638 case OTG_STATE_B_IDLE:
639 if (!musb->is_active)
640 break;
641 case OTG_STATE_B_PERIPHERAL:
642 musb_g_suspend(musb);
643 musb->is_active = is_otg_enabled(musb)
644 && otg->gadget->b_hnp_enable;
645 if (musb->is_active) {
646 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
647 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
648 mod_timer(&musb->otg_timer, jiffies
649 + msecs_to_jiffies(
650 OTG_TIME_B_ASE0_BRST));
651 }
652 break;
653 case OTG_STATE_A_WAIT_BCON:
654 if (musb->a_wait_bcon != 0)
655 musb_platform_try_idle(musb, jiffies
656 + msecs_to_jiffies(musb->a_wait_bcon));
657 break;
658 case OTG_STATE_A_HOST:
659 musb->xceiv->state = OTG_STATE_A_SUSPEND;
660 musb->is_active = is_otg_enabled(musb)
661 && otg->host->b_hnp_enable;
662 break;
663 case OTG_STATE_B_HOST:
664 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
665 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
666 break;
667 default:
668 /* "should not happen" */
669 musb->is_active = 0;
670 break;
671 }
672 }
673#endif
674
675 if (int_usb & MUSB_INTR_CONNECT) {
676 struct usb_hcd *hcd = musb_to_hcd(musb);
677
678 handled = IRQ_HANDLED;
679 musb->is_active = 1;
680
681 musb->ep0_stage = MUSB_EP0_START;
682
683 /* flush endpoints when transitioning from Device Mode */
684 if (is_peripheral_active(musb)) {
685 /* REVISIT HNP; just force disconnect */
686 }
687 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
688 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
689 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
690#ifndef __UBOOT__
691 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
692 |USB_PORT_STAT_HIGH_SPEED
693 |USB_PORT_STAT_ENABLE
694 );
695 musb->port1_status |= USB_PORT_STAT_CONNECTION
696 |(USB_PORT_STAT_C_CONNECTION << 16);
697
698 /* high vs full speed is just a guess until after reset */
699 if (devctl & MUSB_DEVCTL_LSDEV)
700 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
701
702 /* indicate new connection to OTG machine */
703 switch (musb->xceiv->state) {
704 case OTG_STATE_B_PERIPHERAL:
705 if (int_usb & MUSB_INTR_SUSPEND) {
706 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
707 int_usb &= ~MUSB_INTR_SUSPEND;
708 goto b_host;
709 } else
710 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
711 break;
712 case OTG_STATE_B_WAIT_ACON:
713 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
714b_host:
715 musb->xceiv->state = OTG_STATE_B_HOST;
716 hcd->self.is_b_host = 1;
717 musb->ignore_disconnect = 0;
718 del_timer(&musb->otg_timer);
719 break;
720 default:
721 if ((devctl & MUSB_DEVCTL_VBUS)
722 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
723 musb->xceiv->state = OTG_STATE_A_HOST;
724 hcd->self.is_b_host = 0;
725 }
726 break;
727 }
728
729 /* poke the root hub */
730 MUSB_HST_MODE(musb);
731 if (hcd->status_urb)
732 usb_hcd_poll_rh_status(hcd);
733 else
734 usb_hcd_resume_root_hub(hcd);
735
736 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
737 otg_state_string(musb->xceiv->state), devctl);
738#endif
739 }
740
741#ifndef __UBOOT__
742 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
743 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
744 otg_state_string(musb->xceiv->state),
745 MUSB_MODE(musb), devctl);
746 handled = IRQ_HANDLED;
747
748 switch (musb->xceiv->state) {
749 case OTG_STATE_A_HOST:
750 case OTG_STATE_A_SUSPEND:
751 usb_hcd_resume_root_hub(musb_to_hcd(musb));
752 musb_root_disconnect(musb);
753 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_B_HOST:
758 /* REVISIT this behaves for "real disconnect"
759 * cases; make sure the other transitions from
760 * from B_HOST act right too. The B_HOST code
761 * in hnp_stop() is currently not used...
762 */
763 musb_root_disconnect(musb);
764 musb_to_hcd(musb)->self.is_b_host = 0;
765 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
766 MUSB_DEV_MODE(musb);
767 musb_g_disconnect(musb);
768 break;
769 case OTG_STATE_A_PERIPHERAL:
770 musb_hnp_stop(musb);
771 musb_root_disconnect(musb);
772 /* FALLTHROUGH */
773 case OTG_STATE_B_WAIT_ACON:
774 /* FALLTHROUGH */
775 case OTG_STATE_B_PERIPHERAL:
776 case OTG_STATE_B_IDLE:
777 musb_g_disconnect(musb);
778 break;
779 default:
780 WARNING("unhandled DISCONNECT transition (%s)\n",
781 otg_state_string(musb->xceiv->state));
782 break;
783 }
784 }
785
786 /* mentor saves a bit: bus reset and babble share the same irq.
787 * only host sees babble; only peripheral sees bus reset.
788 */
789 if (int_usb & MUSB_INTR_RESET) {
790 handled = IRQ_HANDLED;
791 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
792 /*
793 * Looks like non-HS BABBLE can be ignored, but
794 * HS BABBLE is an error condition. For HS the solution
795 * is to avoid babble in the first place and fix what
796 * caused BABBLE. When HS BABBLE happens we can only
797 * stop the session.
798 */
799 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
800 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
801 else {
802 ERR("Stopping host session -- babble\n");
803 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
804 }
805 } else if (is_peripheral_capable()) {
806 dev_dbg(musb->controller, "BUS RESET as %s\n",
807 otg_state_string(musb->xceiv->state));
808 switch (musb->xceiv->state) {
809 case OTG_STATE_A_SUSPEND:
810 /* We need to ignore disconnect on suspend
811 * otherwise tusb 2.0 won't reconnect after a
812 * power cycle, which breaks otg compliance.
813 */
814 musb->ignore_disconnect = 1;
815 musb_g_reset(musb);
816 /* FALLTHROUGH */
817 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
818 /* never use invalid T(a_wait_bcon) */
819 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
820 otg_state_string(musb->xceiv->state),
821 TA_WAIT_BCON(musb));
822 mod_timer(&musb->otg_timer, jiffies
823 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
824 break;
825 case OTG_STATE_A_PERIPHERAL:
826 musb->ignore_disconnect = 0;
827 del_timer(&musb->otg_timer);
828 musb_g_reset(musb);
829 break;
830 case OTG_STATE_B_WAIT_ACON:
831 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
832 otg_state_string(musb->xceiv->state));
833 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
834 musb_g_reset(musb);
835 break;
836 case OTG_STATE_B_IDLE:
837 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
838 /* FALLTHROUGH */
839 case OTG_STATE_B_PERIPHERAL:
840 musb_g_reset(musb);
841 break;
842 default:
843 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
844 otg_state_string(musb->xceiv->state));
845 }
846 }
847 }
848#endif
849
850#if 0
851/* REVISIT ... this would be for multiplexing periodic endpoints, or
852 * supporting transfer phasing to prevent exceeding ISO bandwidth
853 * limits of a given frame or microframe.
854 *
855 * It's not needed for peripheral side, which dedicates endpoints;
856 * though it _might_ use SOF irqs for other purposes.
857 *
858 * And it's not currently needed for host side, which also dedicates
859 * endpoints, relies on TX/RX interval registers, and isn't claimed
860 * to support ISO transfers yet.
861 */
862 if (int_usb & MUSB_INTR_SOF) {
863 void __iomem *mbase = musb->mregs;
864 struct musb_hw_ep *ep;
865 u8 epnum;
866 u16 frame;
867
868 dev_dbg(musb->controller, "START_OF_FRAME\n");
869 handled = IRQ_HANDLED;
870
871 /* start any periodic Tx transfers waiting for current frame */
872 frame = musb_readw(mbase, MUSB_FRAME);
873 ep = musb->endpoints;
874 for (epnum = 1; (epnum < musb->nr_endpoints)
875 && (musb->epmask >= (1 << epnum));
876 epnum++, ep++) {
877 /*
878 * FIXME handle framecounter wraps (12 bits)
879 * eliminate duplicated StartUrb logic
880 */
881 if (ep->dwWaitFrame >= frame) {
882 ep->dwWaitFrame = 0;
883 pr_debug("SOF --> periodic TX%s on %d\n",
884 ep->tx_channel ? " DMA" : "",
885 epnum);
886 if (!ep->tx_channel)
887 musb_h_tx_start(musb, epnum);
888 else
889 cppi_hostdma_start(musb, epnum);
890 }
891 } /* end of for loop */
892 }
893#endif
894
895 schedule_work(&musb->irq_work);
896
897 return handled;
898}
899
900/*-------------------------------------------------------------------------*/
901
902/*
903* Program the HDRC to start (enable interrupts, dma, etc.).
904*/
15837236 905#ifndef __UBOOT__
eb81955b 906void musb_start(struct musb *musb)
15837236
HG		 907#else
908int musb_start(struct musb *musb)
909#endif
eb81955b
IY		 910{
911 void __iomem *regs = musb->mregs;
912 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
15837236
HG		 913#ifdef __UBOOT__
914 int ret;
915#endif
eb81955b
IY		 916
917 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
918
919 /* Set INT enable registers, enable interrupts */
920 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
921 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
922 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
923
924 musb_writeb(regs, MUSB_TESTMODE, 0);
925
926 /* put into basic highspeed mode and start session */
927 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
928 | MUSB_POWER_HSENAB
929 /* ENSUSPEND wedges tusb */
930 /* | MUSB_POWER_ENSUSPEND */
931 );
932
933 musb->is_active = 0;
934 devctl = musb_readb(regs, MUSB_DEVCTL);
935 devctl &= ~MUSB_DEVCTL_SESSION;
936
937 if (is_otg_enabled(musb)) {
938#ifndef __UBOOT__
939 /* session started after:
940 * (a) ID-grounded irq, host mode;
941 * (b) vbus present/connect IRQ, peripheral mode;
942 * (c) peripheral initiates, using SRP
943 */
944 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
945 musb->is_active = 1;
946 else
947 devctl |= MUSB_DEVCTL_SESSION;
948#endif
949
950 } else if (is_host_enabled(musb)) {
951 /* assume ID pin is hard-wired to ground */
952 devctl |= MUSB_DEVCTL_SESSION;
953
954 } else /* peripheral is enabled */ {
955 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
956 musb->is_active = 1;
957 }
15837236
HG		 958
959#ifndef __UBOOT__
eb81955b 960 musb_platform_enable(musb);
15837236
HG		 961#else
962 ret = musb_platform_enable(musb);
963 if (ret) {
964 musb->is_active = 0;
965 return ret;
966 }
967#endif
eb81955b 968 musb_writeb(regs, MUSB_DEVCTL, devctl);
15837236
HG		 969
970#ifdef __UBOOT__
971 return 0;
972#endif
eb81955b
IY		 973}
974
975
976static void musb_generic_disable(struct musb *musb)
977{
978 void __iomem *mbase = musb->mregs;
979 u16 temp;
980
981 /* disable interrupts */
982 musb_writeb(mbase, MUSB_INTRUSBE, 0);
983 musb_writew(mbase, MUSB_INTRTXE, 0);
984 musb_writew(mbase, MUSB_INTRRXE, 0);
985
986 /* off */
987 musb_writeb(mbase, MUSB_DEVCTL, 0);
988
989 /* flush pending interrupts */
990 temp = musb_readb(mbase, MUSB_INTRUSB);
991 temp = musb_readw(mbase, MUSB_INTRTX);
992 temp = musb_readw(mbase, MUSB_INTRRX);
993
994}
995
996/*
997 * Make the HDRC stop (disable interrupts, etc.);
998 * reversible by musb_start
999 * called on gadget driver unregister
1000 * with controller locked, irqs blocked
1001 * acts as a NOP unless some role activated the hardware
1002 */
1003void musb_stop(struct musb *musb)
1004{
1005 /* stop IRQs, timers, ... */
1006 musb_platform_disable(musb);
1007 musb_generic_disable(musb);
1008 dev_dbg(musb->controller, "HDRC disabled\n");
1009
1010 /* FIXME
1011 * - mark host and/or peripheral drivers unusable/inactive
1012 * - disable DMA (and enable it in HdrcStart)
1013 * - make sure we can musb_start() after musb_stop(); with
1014 * OTG mode, gadget driver module rmmod/modprobe cycles that
1015 * - ...
1016 */
1017 musb_platform_try_idle(musb, 0);
12069bd0 1018 musb_platform_exit(musb);
eb81955b
IY		 1019}
1020
1021#ifndef __UBOOT__
1022static void musb_shutdown(struct platform_device *pdev)
1023{
1024 struct musb *musb = dev_to_musb(&pdev->dev);
1025 unsigned long flags;
1026
1027 pm_runtime_get_sync(musb->controller);
1028
1029 musb_gadget_cleanup(musb);
1030
1031 spin_lock_irqsave(&musb->lock, flags);
1032 musb_platform_disable(musb);
1033 musb_generic_disable(musb);
1034 spin_unlock_irqrestore(&musb->lock, flags);
1035
1036 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1037 usb_remove_hcd(musb_to_hcd(musb));
1038 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1039 musb_platform_exit(musb);
1040
1041 pm_runtime_put(musb->controller);
1042 /* FIXME power down */
1043}
1044#endif
1045
1046
1047/*-------------------------------------------------------------------------*/
1048
1049/*
1050 * The silicon either has hard-wired endpoint configurations, or else
1051 * "dynamic fifo" sizing. The driver has support for both, though at this
1052 * writing only the dynamic sizing is very well tested. Since we switched
1053 * away from compile-time hardware parameters, we can no longer rely on
1054 * dead code elimination to leave only the relevant one in the object file.
1055 *
1056 * We don't currently use dynamic fifo setup capability to do anything
1057 * more than selecting one of a bunch of predefined configurations.
1058 */
1059#if defined(CONFIG_USB_MUSB_TUSB6010) \
1060 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1061 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1062 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1063 || defined(CONFIG_USB_MUSB_AM35X) \
1064 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1065 || defined(CONFIG_USB_MUSB_DSPS) \
1066 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1067static ushort __devinitdata fifo_mode = 4;
1068#elif defined(CONFIG_USB_MUSB_UX500) \
1069 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1070static ushort __devinitdata fifo_mode = 5;
1071#else
1072static ushort __devinitdata fifo_mode = 2;
1073#endif
1074
1075/* "modprobe ... fifo_mode=1" etc */
1076module_param(fifo_mode, ushort, 0);
1077MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1078
1079/*
1080 * tables defining fifo_mode values. define more if you like.
1081 * for host side, make sure both halves of ep1 are set up.
1082 */
1083
1084/* mode 0 - fits in 2KB */
1085static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1086{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1087{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1088{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1089{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1090{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1091};
1092
1093/* mode 1 - fits in 4KB */
1094static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1095{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1096{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1097{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1098{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1099{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1100};
1101
1102/* mode 2 - fits in 4KB */
1103static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1104{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1105{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1106{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1107{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1108{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1109{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1110};
1111
1112/* mode 3 - fits in 4KB */
1113static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1114{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1115{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1116{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1117{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1118{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1119{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1120};
1121
1122/* mode 4 - fits in 16KB */
1123static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1124{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1125{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1126{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1127{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1128{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1129{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1130{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1131{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1132{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1133{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1134{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1135{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1136{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1137{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1138{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1139{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1140{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1141{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1142{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1143{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1144{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1145{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1146{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1147{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1148{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1149{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1150{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1151};
1152
1153/* mode 5 - fits in 8KB */
1154static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1155{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1156{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1157{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1158{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1159{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1160{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1161{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1164{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1165{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1166{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1167{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1168{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1169{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1170{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1171{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1172{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1173{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1174{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1175{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1176{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1177{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1178{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1179{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1180{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1181{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1182};
1183
1184/*
1185 * configure a fifo; for non-shared endpoints, this may be called
1186 * once for a tx fifo and once for an rx fifo.
1187 *
1188 * returns negative errno or offset for next fifo.
1189 */
1190static int __devinit
1191fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1192 const struct musb_fifo_cfg *cfg, u16 offset)
1193{
1194 void __iomem *mbase = musb->mregs;
1195 int size = 0;
1196 u16 maxpacket = cfg->maxpacket;
1197 u16 c_off = offset >> 3;
1198 u8 c_size;
1199
1200 /* expect hw_ep has already been zero-initialized */
1201
1202 size = ffs(max(maxpacket, (u16) 8)) - 1;
1203 maxpacket = 1 << size;
1204
1205 c_size = size - 3;
1206 if (cfg->mode == BUF_DOUBLE) {
1207 if ((offset + (maxpacket << 1)) >
1208 (1 << (musb->config->ram_bits + 2)))
1209 return -EMSGSIZE;
1210 c_size |= MUSB_FIFOSZ_DPB;
1211 } else {
1212 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1213 return -EMSGSIZE;
1214 }
1215
1216 /* configure the FIFO */
1217 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1218
1219 /* EP0 reserved endpoint for control, bidirectional;
1220 * EP1 reserved for bulk, two unidirection halves.
1221 */
1222 if (hw_ep->epnum == 1)
1223 musb->bulk_ep = hw_ep;
1224 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1225 switch (cfg->style) {
1226 case FIFO_TX:
1227 musb_write_txfifosz(mbase, c_size);
1228 musb_write_txfifoadd(mbase, c_off);
1229 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1230 hw_ep->max_packet_sz_tx = maxpacket;
1231 break;
1232 case FIFO_RX:
1233 musb_write_rxfifosz(mbase, c_size);
1234 musb_write_rxfifoadd(mbase, c_off);
1235 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1236 hw_ep->max_packet_sz_rx = maxpacket;
1237 break;
1238 case FIFO_RXTX:
1239 musb_write_txfifosz(mbase, c_size);
1240 musb_write_txfifoadd(mbase, c_off);
1241 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1242 hw_ep->max_packet_sz_rx = maxpacket;
1243
1244 musb_write_rxfifosz(mbase, c_size);
1245 musb_write_rxfifoadd(mbase, c_off);
1246 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1247 hw_ep->max_packet_sz_tx = maxpacket;
1248
1249 hw_ep->is_shared_fifo = true;
1250 break;
1251 }
1252
1253 /* NOTE rx and tx endpoint irqs aren't managed separately,
1254 * which happens to be ok
1255 */
1256 musb->epmask |= (1 << hw_ep->epnum);
1257
1258 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1259}
1260
1261static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1262 .style = FIFO_RXTX, .maxpacket = 64,
1263};
1264
1265static int __devinit ep_config_from_table(struct musb *musb)
1266{
1267 const struct musb_fifo_cfg *cfg;
1268 unsigned i, n;
1269 int offset;
1270 struct musb_hw_ep *hw_ep = musb->endpoints;
1271
1272 if (musb->config->fifo_cfg) {
1273 cfg = musb->config->fifo_cfg;
1274 n = musb->config->fifo_cfg_size;
1275 goto done;
1276 }
1277
1278 switch (fifo_mode) {
1279 default:
1280 fifo_mode = 0;
1281 /* FALLTHROUGH */
1282 case 0:
1283 cfg = mode_0_cfg;
1284 n = ARRAY_SIZE(mode_0_cfg);
1285 break;
1286 case 1:
1287 cfg = mode_1_cfg;
1288 n = ARRAY_SIZE(mode_1_cfg);
1289 break;
1290 case 2:
1291 cfg = mode_2_cfg;
1292 n = ARRAY_SIZE(mode_2_cfg);
1293 break;
1294 case 3:
1295 cfg = mode_3_cfg;
1296 n = ARRAY_SIZE(mode_3_cfg);
1297 break;
1298 case 4:
1299 cfg = mode_4_cfg;
1300 n = ARRAY_SIZE(mode_4_cfg);
1301 break;
1302 case 5:
1303 cfg = mode_5_cfg;
1304 n = ARRAY_SIZE(mode_5_cfg);
1305 break;
1306 }
1307
32f420b8 1308 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
eb81955b
IY		 1309
1310done:
1311 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1312 /* assert(offset > 0) */
1313
1314 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1315 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1316 */
1317
1318 for (i = 0; i < n; i++) {
1319 u8 epn = cfg->hw_ep_num;
1320
1321 if (epn >= musb->config->num_eps) {
1322 pr_debug("%s: invalid ep %d\n",
1323 musb_driver_name, epn);
1324 return -EINVAL;
1325 }
1326 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1327 if (offset < 0) {
1328 pr_debug("%s: mem overrun, ep %d\n",
1329 musb_driver_name, epn);
1330 return -EINVAL;
1331 }
1332 epn++;
1333 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1334 }
1335
32f420b8
LV		 1336 pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1,
1337 musb->config->num_eps * 2 - 1, offset,
1338 (1 << (musb->config->ram_bits + 2)));
eb81955b
IY		 1339
1340 if (!musb->bulk_ep) {
1341 pr_debug("%s: missing bulk\n", musb_driver_name);
1342 return -EINVAL;
1343 }
1344
1345 return 0;
1346}
1347
1348
1349/*
1350 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1351 * @param musb the controller
1352 */
1353static int __devinit ep_config_from_hw(struct musb *musb)
1354{
1355 u8 epnum = 0;
1356 struct musb_hw_ep *hw_ep;
1357 void *mbase = musb->mregs;
1358 int ret = 0;
1359
1360 dev_dbg(musb->controller, "<== static silicon ep config\n");
1361
1362 /* FIXME pick up ep0 maxpacket size */
1363
1364 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1365 musb_ep_select(mbase, epnum);
1366 hw_ep = musb->endpoints + epnum;
1367
1368 ret = musb_read_fifosize(musb, hw_ep, epnum);
1369 if (ret < 0)
1370 break;
1371
1372 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1373
1374 /* pick an RX/TX endpoint for bulk */
1375 if (hw_ep->max_packet_sz_tx < 512
1376 || hw_ep->max_packet_sz_rx < 512)
1377 continue;
1378
1379 /* REVISIT: this algorithm is lazy, we should at least
1380 * try to pick a double buffered endpoint.
1381 */
1382 if (musb->bulk_ep)
1383 continue;
1384 musb->bulk_ep = hw_ep;
1385 }
1386
1387 if (!musb->bulk_ep) {
1388 pr_debug("%s: missing bulk\n", musb_driver_name);
1389 return -EINVAL;
1390 }
1391
1392 return 0;
1393}
1394
1395enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1396
1397/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1398 * configure endpoints, or take their config from silicon
1399 */
1400static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1401{
1402 u8 reg;
1403 char *type;
1404 char aInfo[90], aRevision[32], aDate[12];
1405 void __iomem *mbase = musb->mregs;
1406 int status = 0;
1407 int i;
1408
1409 /* log core options (read using indexed model) */
1410 reg = musb_read_configdata(mbase);
1411
1412 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1413 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1414 strcat(aInfo, ", dyn FIFOs");
1415 musb->dyn_fifo = true;
1416 }
95de1e2f 1417#ifndef CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
eb81955b
IY		 1418 if (reg & MUSB_CONFIGDATA_MPRXE) {
1419 strcat(aInfo, ", bulk combine");
1420 musb->bulk_combine = true;
1421 }
1422 if (reg & MUSB_CONFIGDATA_MPTXE) {
1423 strcat(aInfo, ", bulk split");
1424 musb->bulk_split = true;
1425 }
4de602f2
BL		 1426#else
1427 musb->bulk_combine = false;
1428 musb->bulk_split = false;
1429#endif
eb81955b
IY		 1430 if (reg & MUSB_CONFIGDATA_HBRXE) {
1431 strcat(aInfo, ", HB-ISO Rx");
1432 musb->hb_iso_rx = true;
1433 }
1434 if (reg & MUSB_CONFIGDATA_HBTXE) {
1435 strcat(aInfo, ", HB-ISO Tx");
1436 musb->hb_iso_tx = true;
1437 }
1438 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1439 strcat(aInfo, ", SoftConn");
1440
32f420b8 1441 pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
eb81955b
IY		 1442
1443 aDate[0] = 0;
1444 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1445 musb->is_multipoint = 1;
1446 type = "M";
1447 } else {
1448 musb->is_multipoint = 0;
1449 type = "";
1450#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1451 printk(KERN_ERR
1452 "%s: kernel must blacklist external hubs\n",
1453 musb_driver_name);
1454#endif
1455 }
1456
1457 /* log release info */
1458 musb->hwvers = musb_read_hwvers(mbase);
1459 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1460 MUSB_HWVERS_MINOR(musb->hwvers),
1461 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
32f420b8
LV		 1462 pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type,
1463 aRevision, aDate);
eb81955b
IY		 1464
1465 /* configure ep0 */
1466 musb_configure_ep0(musb);
1467
1468 /* discover endpoint configuration */
1469 musb->nr_endpoints = 1;
1470 musb->epmask = 1;
1471
1472 if (musb->dyn_fifo)
1473 status = ep_config_from_table(musb);
1474 else
1475 status = ep_config_from_hw(musb);
1476
1477 if (status < 0)
1478 return status;
1479
1480 /* finish init, and print endpoint config */
1481 for (i = 0; i < musb->nr_endpoints; i++) {
1482 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1483
1484 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1485#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1486 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1487 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1488 hw_ep->fifo_sync_va =
1489 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1490
1491 if (i == 0)
1492 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1493 else
1494 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1495#endif
1496
1497 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1498 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1499 hw_ep->rx_reinit = 1;
1500 hw_ep->tx_reinit = 1;
1501
1502 if (hw_ep->max_packet_sz_tx) {
1503 dev_dbg(musb->controller,
1504 "%s: hw_ep %d%s, %smax %d\n",
1505 musb_driver_name, i,
1506 hw_ep->is_shared_fifo ? "shared" : "tx",
1507 hw_ep->tx_double_buffered
1508 ? "doublebuffer, " : "",
1509 hw_ep->max_packet_sz_tx);
1510 }
1511 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1512 dev_dbg(musb->controller,
1513 "%s: hw_ep %d%s, %smax %d\n",
1514 musb_driver_name, i,
1515 "rx",
1516 hw_ep->rx_double_buffered
1517 ? "doublebuffer, " : "",
1518 hw_ep->max_packet_sz_rx);
1519 }
1520 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1521 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1522 }
1523
1524 return 0;
1525}
1526
1527/*-------------------------------------------------------------------------*/
1528
6e7df1d1
TR		 1529#if defined(CONFIG_SOC_OMAP2430) || defined(CFG_SOC_OMAP3430) || \
1530 defined(CFG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
eb81955b
IY		 1531
1532static irqreturn_t generic_interrupt(int irq, void *__hci)
1533{
1534 unsigned long flags;
1535 irqreturn_t retval = IRQ_NONE;
1536 struct musb *musb = __hci;
1537
1538 spin_lock_irqsave(&musb->lock, flags);
1539
1540 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1541 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1542 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1543
1544 if (musb->int_usb || musb->int_tx || musb->int_rx)
1545 retval = musb_interrupt(musb);
1546
1547 spin_unlock_irqrestore(&musb->lock, flags);
1548
1549 return retval;
1550}
1551
1552#else
1553#define generic_interrupt NULL
1554#endif
1555
1556/*
1557 * handle all the irqs defined by the HDRC core. for now we expect: other
1558 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1559 * will be assigned, and the irq will already have been acked.
1560 *
1561 * called in irq context with spinlock held, irqs blocked
1562 */
1563irqreturn_t musb_interrupt(struct musb *musb)
1564{
1565 irqreturn_t retval = IRQ_NONE;
1566 u8 devctl, power;
1567 int ep_num;
1568 u32 reg;
1569
1570 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1571 power = musb_readb(musb->mregs, MUSB_POWER);
1572
1573 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1574 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1575 musb->int_usb, musb->int_tx, musb->int_rx);
1576
1577 /* the core can interrupt us for multiple reasons; docs have
1578 * a generic interrupt flowchart to follow
1579 */
1580 if (musb->int_usb)
1581 retval |= musb_stage0_irq(musb, musb->int_usb,
1582 devctl, power);
1583
1584 /* "stage 1" is handling endpoint irqs */
1585
1586 /* handle endpoint 0 first */
1587 if (musb->int_tx & 1) {
1588 if (devctl & MUSB_DEVCTL_HM) {
1589 if (is_host_capable())
1590 retval |= musb_h_ep0_irq(musb);
1591 } else {
1592 if (is_peripheral_capable())
1593 retval |= musb_g_ep0_irq(musb);
1594 }
1595 }
1596
1597 /* RX on endpoints 1-15 */
1598 reg = musb->int_rx >> 1;
1599 ep_num = 1;
1600 while (reg) {
1601 if (reg & 1) {
1602 /* musb_ep_select(musb->mregs, ep_num); */
1603 /* REVISIT just retval = ep->rx_irq(...) */
1604 retval = IRQ_HANDLED;
1605 if (devctl & MUSB_DEVCTL_HM) {
1606 if (is_host_capable())
1607 musb_host_rx(musb, ep_num);
1608 } else {
1609 if (is_peripheral_capable())
1610 musb_g_rx(musb, ep_num);
1611 }
1612 }
1613
1614 reg >>= 1;
1615 ep_num++;
1616 }
1617
1618 /* TX on endpoints 1-15 */
1619 reg = musb->int_tx >> 1;
1620 ep_num = 1;
1621 while (reg) {
1622 if (reg & 1) {
1623 /* musb_ep_select(musb->mregs, ep_num); */
1624 /* REVISIT just retval |= ep->tx_irq(...) */
1625 retval = IRQ_HANDLED;
1626 if (devctl & MUSB_DEVCTL_HM) {
1627 if (is_host_capable())
1628 musb_host_tx(musb, ep_num);
1629 } else {
1630 if (is_peripheral_capable())
1631 musb_g_tx(musb, ep_num);
1632 }
1633 }
1634 reg >>= 1;
1635 ep_num++;
1636 }
1637
1638 return retval;
1639}
1640EXPORT_SYMBOL_GPL(musb_interrupt);
1641
95de1e2f 1642#ifndef CONFIG_USB_MUSB_PIO_ONLY
eb81955b
IY		 1643static bool __devinitdata use_dma = 1;
1644
1645/* "modprobe ... use_dma=0" etc */
1646module_param(use_dma, bool, 0);
1647MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1648
1649void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1650{
1651 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1652
1653 /* called with controller lock already held */
1654
1655 if (!epnum) {
1656#ifndef CONFIG_USB_TUSB_OMAP_DMA
1657 if (!is_cppi_enabled()) {
1658 /* endpoint 0 */
1659 if (devctl & MUSB_DEVCTL_HM)
1660 musb_h_ep0_irq(musb);
1661 else
1662 musb_g_ep0_irq(musb);
1663 }
1664#endif
1665 } else {
1666 /* endpoints 1..15 */
1667 if (transmit) {
1668 if (devctl & MUSB_DEVCTL_HM) {
1669 if (is_host_capable())
1670 musb_host_tx(musb, epnum);
1671 } else {
1672 if (is_peripheral_capable())
1673 musb_g_tx(musb, epnum);
1674 }
1675 } else {
1676 /* receive */
1677 if (devctl & MUSB_DEVCTL_HM) {
1678 if (is_host_capable())
1679 musb_host_rx(musb, epnum);
1680 } else {
1681 if (is_peripheral_capable())
1682 musb_g_rx(musb, epnum);
1683 }
1684 }
1685 }
1686}
1687EXPORT_SYMBOL_GPL(musb_dma_completion);
1688
1689#else
1690#define use_dma 0
1691#endif
1692
1693/*-------------------------------------------------------------------------*/
1694
1695#ifdef CONFIG_SYSFS
1696
1697static ssize_t
1698musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1699{
1700 struct musb *musb = dev_to_musb(dev);
1701 unsigned long flags;
1702 int ret = -EINVAL;
1703
1704 spin_lock_irqsave(&musb->lock, flags);
1705 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1706 spin_unlock_irqrestore(&musb->lock, flags);
1707
1708 return ret;
1709}
1710
1711static ssize_t
1712musb_mode_store(struct device *dev, struct device_attribute *attr,
1713 const char *buf, size_t n)
1714{
1715 struct musb *musb = dev_to_musb(dev);
1716 unsigned long flags;
1717 int status;
1718
1719 spin_lock_irqsave(&musb->lock, flags);
1720 if (sysfs_streq(buf, "host"))
1721 status = musb_platform_set_mode(musb, MUSB_HOST);
1722 else if (sysfs_streq(buf, "peripheral"))
1723 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1724 else if (sysfs_streq(buf, "otg"))
1725 status = musb_platform_set_mode(musb, MUSB_OTG);
1726 else
1727 status = -EINVAL;
1728 spin_unlock_irqrestore(&musb->lock, flags);
1729
1730 return (status == 0) ? n : status;
1731}
1732static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1733
1734static ssize_t
1735musb_vbus_store(struct device *dev, struct device_attribute *attr,
1736 const char *buf, size_t n)
1737{
1738 struct musb *musb = dev_to_musb(dev);
1739 unsigned long flags;
1740 unsigned long val;
1741
1742 if (sscanf(buf, "%lu", &val) < 1) {
1743 dev_err(dev, "Invalid VBUS timeout ms value\n");
1744 return -EINVAL;
1745 }
1746
1747 spin_lock_irqsave(&musb->lock, flags);
1748 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1749 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1750 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1751 musb->is_active = 0;
1752 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1753 spin_unlock_irqrestore(&musb->lock, flags);
1754
1755 return n;
1756}
1757
1758static ssize_t
1759musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1760{
1761 struct musb *musb = dev_to_musb(dev);
1762 unsigned long flags;
1763 unsigned long val;
1764 int vbus;
1765
1766 spin_lock_irqsave(&musb->lock, flags);
1767 val = musb->a_wait_bcon;
1768 /* FIXME get_vbus_status() is normally #defined as false...
1769 * and is effectively TUSB-specific.
1770 */
1771 vbus = musb_platform_get_vbus_status(musb);
1772 spin_unlock_irqrestore(&musb->lock, flags);
1773
1774 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1775 vbus ? "on" : "off", val);
1776}
1777static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1778
1779/* Gadget drivers can't know that a host is connected so they might want
1780 * to start SRP, but users can. This allows userspace to trigger SRP.
1781 */
1782static ssize_t
1783musb_srp_store(struct device *dev, struct device_attribute *attr,
1784 const char *buf, size_t n)
1785{
1786 struct musb *musb = dev_to_musb(dev);
1787 unsigned short srp;
1788
1789 if (sscanf(buf, "%hu", &srp) != 1
1790 || (srp != 1)) {
1791 dev_err(dev, "SRP: Value must be 1\n");
1792 return -EINVAL;
1793 }
1794
1795 if (srp == 1)
1796 musb_g_wakeup(musb);
1797
1798 return n;
1799}
1800static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1801
1802static struct attribute *musb_attributes[] = {
1803 &dev_attr_mode.attr,
1804 &dev_attr_vbus.attr,
1805 &dev_attr_srp.attr,
1806 NULL
1807};
1808
1809static const struct attribute_group musb_attr_group = {
1810 .attrs = musb_attributes,
1811};
1812
1813#endif /* sysfs */
1814
1815#ifndef __UBOOT__
1816/* Only used to provide driver mode change events */
1817static void musb_irq_work(struct work_struct *data)
1818{
1819 struct musb *musb = container_of(data, struct musb, irq_work);
1820 static int old_state;
1821
1822 if (musb->xceiv->state != old_state) {
1823 old_state = musb->xceiv->state;
1824 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1825 }
1826}
1827#endif
1828
1829/* --------------------------------------------------------------------------
1830 * Init support
1831 */
1832
1833static struct musb *__devinit
1834allocate_instance(struct device *dev,
1835 struct musb_hdrc_config *config, void __iomem *mbase)
1836{
1837 struct musb *musb;
1838 struct musb_hw_ep *ep;
1839 int epnum;
1840#ifndef __UBOOT__
1841 struct usb_hcd *hcd;
1842
1843 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1844 if (!hcd)
1845 return NULL;
1846 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1847
1848 musb = hcd_to_musb(hcd);
1849#else
1850 musb = calloc(1, sizeof(*musb));
1851 if (!musb)
1852 return NULL;
1853#endif
1854 INIT_LIST_HEAD(&musb->control);
1855 INIT_LIST_HEAD(&musb->in_bulk);
1856 INIT_LIST_HEAD(&musb->out_bulk);
1857
1858#ifndef __UBOOT__
1859 hcd->uses_new_polling = 1;
1860 hcd->has_tt = 1;
1861#endif
1862
1863 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1864 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1865 dev_set_drvdata(dev, musb);
1866 musb->mregs = mbase;
1867 musb->ctrl_base = mbase;
1868 musb->nIrq = -ENODEV;
1869 musb->config = config;
1058eec0
SG		 1870#ifdef __UBOOT__
1871 assert_noisy(musb->config->num_eps <= MUSB_C_NUM_EPS);
1872#else
eb81955b 1873 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1058eec0 1874#endif
eb81955b
IY		 1875 for (epnum = 0, ep = musb->endpoints;
1876 epnum < musb->config->num_eps;
1877 epnum++, ep++) {
1878 ep->musb = musb;
1879 ep->epnum = epnum;
1880 }
1881
1882 musb->controller = dev;
1883
1884 return musb;
1885}
1886
1887static void musb_free(struct musb *musb)
1888{
1889 /* this has multiple entry modes. it handles fault cleanup after
1890 * probe(), where things may be partially set up, as well as rmmod
1891 * cleanup after everything's been de-activated.
1892 */
1893
1894#ifdef CONFIG_SYSFS
1895 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1896#endif
1897
1898 if (musb->nIrq >= 0) {
1899 if (musb->irq_wake)
1900 disable_irq_wake(musb->nIrq);
1901 free_irq(musb->nIrq, musb);
1902 }
1903 if (is_dma_capable() && musb->dma_controller) {
1904 struct dma_controller *c = musb->dma_controller;
1905
1906 (void) c->stop(c);
1907 dma_controller_destroy(c);
1908 }
1909
1910 kfree(musb);
1911}
1912
1913/*
1914 * Perform generic per-controller initialization.
1915 *
1916 * @pDevice: the controller (already clocked, etc)
1917 * @nIrq: irq
1918 * @mregs: virtual address of controller registers,
1919 * not yet corrected for platform-specific offsets
1920 */
1921#ifndef __UBOOT__
1922static int __devinit
1923musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1924#else
1925struct musb *
1926musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev,
1927 void *ctrl)
1928#endif
1929{
1930 int status;
1931 struct musb *musb;
1932#ifndef __UBOOT__
1933 struct musb_hdrc_platform_data *plat = dev->platform_data;
1934#else
1935 int nIrq = 0;
1936#endif
1937
1938 /* The driver might handle more features than the board; OK.
1939 * Fail when the board needs a feature that's not enabled.
1940 */
1941 if (!plat) {
1942 dev_dbg(dev, "no platform_data?\n");
1943 status = -ENODEV;
1944 goto fail0;
1945 }
1946
1947 /* allocate */
1948 musb = allocate_instance(dev, plat->config, ctrl);
1949 if (!musb) {
1950 status = -ENOMEM;
1951 goto fail0;
1952 }
1953
1954 pm_runtime_use_autosuspend(musb->controller);
1955 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1956 pm_runtime_enable(musb->controller);
1957
1958 spin_lock_init(&musb->lock);
1959 musb->board_mode = plat->mode;
1960 musb->board_set_power = plat->set_power;
1961 musb->min_power = plat->min_power;
1962 musb->ops = plat->platform_ops;
1963
1964 /* The musb_platform_init() call:
1965 * - adjusts musb->mregs and musb->isr if needed,
1966 * - may initialize an integrated tranceiver
1967 * - initializes musb->xceiv, usually by otg_get_phy()
1968 * - stops powering VBUS
1969 *
1970 * There are various transceiver configurations. Blackfin,
1971 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1972 * external/discrete ones in various flavors (twl4030 family,
1973 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1974 */
1975 musb->isr = generic_interrupt;
1976 status = musb_platform_init(musb);
1977 if (status < 0)
1978 goto fail1;
1979
1980 if (!musb->isr) {
1981 status = -ENODEV;
1982 goto fail2;
1983 }
1984
1985#ifndef __UBOOT__
1986 if (!musb->xceiv->io_ops) {
1987 musb->xceiv->io_dev = musb->controller;
1988 musb->xceiv->io_priv = musb->mregs;
1989 musb->xceiv->io_ops = &musb_ulpi_access;
1990 }
1991#endif
1992
1993 pm_runtime_get_sync(musb->controller);
1994
95de1e2f 1995#ifndef CONFIG_USB_MUSB_PIO_ONLY
eb81955b
IY		 1996 if (use_dma && dev->dma_mask) {
1997 struct dma_controller *c;
1998
1999 c = dma_controller_create(musb, musb->mregs);
2000 musb->dma_controller = c;
2001 if (c)
2002 (void) c->start(c);
2003 }
2004#endif
2005#ifndef __UBOOT__
2006 /* ideally this would be abstracted in platform setup */
2007 if (!is_dma_capable() || !musb->dma_controller)
2008 dev->dma_mask = NULL;
2009#endif
2010
2011 /* be sure interrupts are disabled before connecting ISR */
2012 musb_platform_disable(musb);
2013 musb_generic_disable(musb);
2014
2015 /* setup musb parts of the core (especially endpoints) */
2016 status = musb_core_init(plat->config->multipoint
2017 ? MUSB_CONTROLLER_MHDRC
2018 : MUSB_CONTROLLER_HDRC, musb);
2019 if (status < 0)
2020 goto fail3;
2021
2022 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2023
2024 /* Init IRQ workqueue before request_irq */
2025 INIT_WORK(&musb->irq_work, musb_irq_work);
2026
2027 /* attach to the IRQ */
2028 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2029 dev_err(dev, "request_irq %d failed!\n", nIrq);
2030 status = -ENODEV;
2031 goto fail3;
2032 }
2033 musb->nIrq = nIrq;
2034/* FIXME this handles wakeup irqs wrong */
2035 if (enable_irq_wake(nIrq) == 0) {
2036 musb->irq_wake = 1;
2037 device_init_wakeup(dev, 1);
2038 } else {
2039 musb->irq_wake = 0;
2040 }
2041
2042#ifndef __UBOOT__
2043 /* host side needs more setup */
2044 if (is_host_enabled(musb)) {
2045 struct usb_hcd *hcd = musb_to_hcd(musb);
2046
2047 otg_set_host(musb->xceiv->otg, &hcd->self);
2048
2049 if (is_otg_enabled(musb))
2050 hcd->self.otg_port = 1;
2051 musb->xceiv->otg->host = &hcd->self;
2052 hcd->power_budget = 2 * (plat->power ? : 250);
2053
2054 /* program PHY to use external vBus if required */
2055 if (plat->extvbus) {
2056 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2057 busctl |= MUSB_ULPI_USE_EXTVBUS;
2058 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2059 }
2060 }
2061#endif
2062
2063 /* For the host-only role, we can activate right away.
2064 * (We expect the ID pin to be forcibly grounded!!)
2065 * Otherwise, wait till the gadget driver hooks up.
2066 */
2067 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2068 struct usb_hcd *hcd = musb_to_hcd(musb);
2069
2070 MUSB_HST_MODE(musb);
2071#ifndef __UBOOT__
2072 musb->xceiv->otg->default_a = 1;
2073 musb->xceiv->state = OTG_STATE_A_IDLE;
2074
2075 status = usb_add_hcd(musb_to_hcd(musb), 0, 0);
2076
2077 hcd->self.uses_pio_for_control = 1;
2078 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2079 "HOST", status,
2080 musb_readb(musb->mregs, MUSB_DEVCTL),
2081 (musb_readb(musb->mregs, MUSB_DEVCTL)
2082 & MUSB_DEVCTL_BDEVICE
2083 ? 'B' : 'A'));
2084#endif
2085
2086 } else /* peripheral is enabled */ {
2087 MUSB_DEV_MODE(musb);
2088#ifndef __UBOOT__
2089 musb->xceiv->otg->default_a = 0;
2090 musb->xceiv->state = OTG_STATE_B_IDLE;
2091#endif
2092
2093 if (is_peripheral_capable())
2094 status = musb_gadget_setup(musb);
2095
2096#ifndef __UBOOT__
2097 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2098 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2099 status,
2100 musb_readb(musb->mregs, MUSB_DEVCTL));
2101#endif
2102
2103 }
2104 if (status < 0)
2105 goto fail3;
2106
2107 status = musb_init_debugfs(musb);
2108 if (status < 0)
2109 goto fail4;
2110
2111#ifdef CONFIG_SYSFS
2112 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2113 if (status)
2114 goto fail5;
2115#endif
2116
2117 pm_runtime_put(musb->controller);
2118
32f420b8 2119 pr_debug("USB %s mode controller at %p using %s, IRQ %d\n",
eb81955b
IY		 2120 ({char *s;
2121 switch (musb->board_mode) {
2122 case MUSB_HOST: s = "Host"; break;
2123 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2124 default: s = "OTG"; break;
2125 }; s; }),
2126 ctrl,
2127 (is_dma_capable() && musb->dma_controller)
2128 ? "DMA" : "PIO",
2129 musb->nIrq);
2130
2131#ifndef __UBOOT__
2132 return 0;
2133#else
2134 return status == 0 ? musb : NULL;
2135#endif
2136
2137fail5:
2138 musb_exit_debugfs(musb);
2139
2140fail4:
2141#ifndef __UBOOT__
2142 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2143 usb_remove_hcd(musb_to_hcd(musb));
2144 else
2145#endif
2146 musb_gadget_cleanup(musb);
2147
2148fail3:
2149 pm_runtime_put_sync(musb->controller);
2150
2151fail2:
2152 if (musb->irq_wake)
2153 device_init_wakeup(dev, 0);
2154 musb_platform_exit(musb);
2155
2156fail1:
2157 dev_err(musb->controller,
2158 "musb_init_controller failed with status %d\n", status);
2159
2160 musb_free(musb);
2161
2162fail0:
2163
2164#ifndef __UBOOT__
2165 return status;
2166#else
2167 return status == 0 ? musb : NULL;
2168#endif
2169
2170}
2171
2172/*-------------------------------------------------------------------------*/
2173
2174/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2175 * bridge to a platform device; this driver then suffices.
2176 */
2177
95de1e2f 2178#ifndef CONFIG_USB_MUSB_PIO_ONLY
eb81955b
IY		 2179static u64 *orig_dma_mask;
2180#endif
2181
2182#ifndef __UBOOT__
2183static int __devinit musb_probe(struct platform_device *pdev)
2184{
2185 struct device *dev = &pdev->dev;
2186 int irq = platform_get_irq_byname(pdev, "mc");
2187 int status;
2188 struct resource *iomem;
2189 void __iomem *base;
2190
2191 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2192 if (!iomem || irq <= 0)
2193 return -ENODEV;
2194
2195 base = ioremap(iomem->start, resource_size(iomem));
2196 if (!base) {
2197 dev_err(dev, "ioremap failed\n");
2198 return -ENOMEM;
2199 }
2200
95de1e2f 2201#ifndef CONFIG_USB_MUSB_PIO_ONLY
eb81955b
IY		 2202 /* clobbered by use_dma=n */
2203 orig_dma_mask = dev->dma_mask;
2204#endif
2205 status = musb_init_controller(dev, irq, base);
2206 if (status < 0)
2207 iounmap(base);
2208
2209 return status;
2210}
2211
2212static int __devexit musb_remove(struct platform_device *pdev)
2213{
2214 struct musb *musb = dev_to_musb(&pdev->dev);
2215 void __iomem *ctrl_base = musb->ctrl_base;
2216
2217 /* this gets called on rmmod.
2218 * - Host mode: host may still be active
2219 * - Peripheral mode: peripheral is deactivated (or never-activated)
2220 * - OTG mode: both roles are deactivated (or never-activated)
2221 */
2222 musb_exit_debugfs(musb);
2223 musb_shutdown(pdev);
2224
2225 musb_free(musb);
2226 iounmap(ctrl_base);
2227 device_init_wakeup(&pdev->dev, 0);
95de1e2f 2228#ifndef CONFIG_USB_MUSB_PIO_ONLY
eb81955b
IY		 2229 pdev->dev.dma_mask = orig_dma_mask;
2230#endif
2231 return 0;
2232}
2233
2234#ifdef CONFIG_PM
2235
2236static void musb_save_context(struct musb *musb)
2237{
2238 int i;
2239 void __iomem *musb_base = musb->mregs;
2240 void __iomem *epio;
2241
2242 if (is_host_enabled(musb)) {
2243 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2244 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2245 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2246 }
2247 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2248 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2249 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2250 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2251 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2252 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2253
2254 for (i = 0; i < musb->config->num_eps; ++i) {
2255 struct musb_hw_ep *hw_ep;
2256
2257 hw_ep = &musb->endpoints[i];
2258 if (!hw_ep)
2259 continue;
2260
2261 epio = hw_ep->regs;
2262 if (!epio)
2263 continue;
2264
2265 musb_writeb(musb_base, MUSB_INDEX, i);
2266 musb->context.index_regs[i].txmaxp =
2267 musb_readw(epio, MUSB_TXMAXP);
2268 musb->context.index_regs[i].txcsr =
2269 musb_readw(epio, MUSB_TXCSR);
2270 musb->context.index_regs[i].rxmaxp =
2271 musb_readw(epio, MUSB_RXMAXP);
2272 musb->context.index_regs[i].rxcsr =
2273 musb_readw(epio, MUSB_RXCSR);
2274
2275 if (musb->dyn_fifo) {
2276 musb->context.index_regs[i].txfifoadd =
2277 musb_read_txfifoadd(musb_base);
2278 musb->context.index_regs[i].rxfifoadd =
2279 musb_read_rxfifoadd(musb_base);
2280 musb->context.index_regs[i].txfifosz =
2281 musb_read_txfifosz(musb_base);
2282 musb->context.index_regs[i].rxfifosz =
2283 musb_read_rxfifosz(musb_base);
2284 }
2285 if (is_host_enabled(musb)) {
2286 musb->context.index_regs[i].txtype =
2287 musb_readb(epio, MUSB_TXTYPE);
2288 musb->context.index_regs[i].txinterval =
2289 musb_readb(epio, MUSB_TXINTERVAL);
2290 musb->context.index_regs[i].rxtype =
2291 musb_readb(epio, MUSB_RXTYPE);
2292 musb->context.index_regs[i].rxinterval =
2293 musb_readb(epio, MUSB_RXINTERVAL);
2294
2295 musb->context.index_regs[i].txfunaddr =
2296 musb_read_txfunaddr(musb_base, i);
2297 musb->context.index_regs[i].txhubaddr =
2298 musb_read_txhubaddr(musb_base, i);
2299 musb->context.index_regs[i].txhubport =
2300 musb_read_txhubport(musb_base, i);
2301
2302 musb->context.index_regs[i].rxfunaddr =
2303 musb_read_rxfunaddr(musb_base, i);
2304 musb->context.index_regs[i].rxhubaddr =
2305 musb_read_rxhubaddr(musb_base, i);
2306 musb->context.index_regs[i].rxhubport =
2307 musb_read_rxhubport(musb_base, i);
2308 }
2309 }
2310}
2311
2312static void musb_restore_context(struct musb *musb)
2313{
2314 int i;
2315 void __iomem *musb_base = musb->mregs;
2316 void __iomem *ep_target_regs;
2317 void __iomem *epio;
2318
2319 if (is_host_enabled(musb)) {
2320 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2321 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2322 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2323 }
2324 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2325 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2326 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2327 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2328 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2329
2330 for (i = 0; i < musb->config->num_eps; ++i) {
2331 struct musb_hw_ep *hw_ep;
2332
2333 hw_ep = &musb->endpoints[i];
2334 if (!hw_ep)
2335 continue;
2336
2337 epio = hw_ep->regs;
2338 if (!epio)
2339 continue;
2340
2341 musb_writeb(musb_base, MUSB_INDEX, i);
2342 musb_writew(epio, MUSB_TXMAXP,
2343 musb->context.index_regs[i].txmaxp);
2344 musb_writew(epio, MUSB_TXCSR,
2345 musb->context.index_regs[i].txcsr);
2346 musb_writew(epio, MUSB_RXMAXP,
2347 musb->context.index_regs[i].rxmaxp);
2348 musb_writew(epio, MUSB_RXCSR,
2349 musb->context.index_regs[i].rxcsr);
2350
2351 if (musb->dyn_fifo) {
2352 musb_write_txfifosz(musb_base,
2353 musb->context.index_regs[i].txfifosz);
2354 musb_write_rxfifosz(musb_base,
2355 musb->context.index_regs[i].rxfifosz);
2356 musb_write_txfifoadd(musb_base,
2357 musb->context.index_regs[i].txfifoadd);
2358 musb_write_rxfifoadd(musb_base,
2359 musb->context.index_regs[i].rxfifoadd);
2360 }
2361
2362 if (is_host_enabled(musb)) {
2363 musb_writeb(epio, MUSB_TXTYPE,
2364 musb->context.index_regs[i].txtype);
2365 musb_writeb(epio, MUSB_TXINTERVAL,
2366 musb->context.index_regs[i].txinterval);
2367 musb_writeb(epio, MUSB_RXTYPE,
2368 musb->context.index_regs[i].rxtype);
2369 musb_writeb(epio, MUSB_RXINTERVAL,
2370
2371 musb->context.index_regs[i].rxinterval);
2372 musb_write_txfunaddr(musb_base, i,
2373 musb->context.index_regs[i].txfunaddr);
2374 musb_write_txhubaddr(musb_base, i,
2375 musb->context.index_regs[i].txhubaddr);
2376 musb_write_txhubport(musb_base, i,
2377 musb->context.index_regs[i].txhubport);
2378
2379 ep_target_regs =
2380 musb_read_target_reg_base(i, musb_base);
2381
2382 musb_write_rxfunaddr(ep_target_regs,
2383 musb->context.index_regs[i].rxfunaddr);
2384 musb_write_rxhubaddr(ep_target_regs,
2385 musb->context.index_regs[i].rxhubaddr);
2386 musb_write_rxhubport(ep_target_regs,
2387 musb->context.index_regs[i].rxhubport);
2388 }
2389 }
2390 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2391}
2392
2393static int musb_suspend(struct device *dev)
2394{
2395 struct musb *musb = dev_to_musb(dev);
2396 unsigned long flags;
2397
2398 spin_lock_irqsave(&musb->lock, flags);
2399
2400 if (is_peripheral_active(musb)) {
2401 /* FIXME force disconnect unless we know USB will wake
2402 * the system up quickly enough to respond ...
2403 */
2404 } else if (is_host_active(musb)) {
2405 /* we know all the children are suspended; sometimes
2406 * they will even be wakeup-enabled.
2407 */
2408 }
2409
2410 spin_unlock_irqrestore(&musb->lock, flags);
2411 return 0;
2412}
2413
2414static int musb_resume_noirq(struct device *dev)
2415{
2416 /* for static cmos like DaVinci, register values were preserved
2417 * unless for some reason the whole soc powered down or the USB
2418 * module got reset through the PSC (vs just being disabled).
2419 */
2420 return 0;
2421}
2422
2423static int musb_runtime_suspend(struct device *dev)
2424{
2425 struct musb *musb = dev_to_musb(dev);
2426
2427 musb_save_context(musb);
2428
2429 return 0;
2430}
2431
2432static int musb_runtime_resume(struct device *dev)
2433{
2434 struct musb *musb = dev_to_musb(dev);
2435 static int first = 1;
2436
2437 /*
2438 * When pm_runtime_get_sync called for the first time in driver
2439 * init, some of the structure is still not initialized which is
2440 * used in restore function. But clock needs to be
2441 * enabled before any register access, so
2442 * pm_runtime_get_sync has to be called.
2443 * Also context restore without save does not make
2444 * any sense
2445 */
2446 if (!first)
2447 musb_restore_context(musb);
2448 first = 0;
2449
2450 return 0;
2451}
2452
2453static const struct dev_pm_ops musb_dev_pm_ops = {
2454 .suspend = musb_suspend,
2455 .resume_noirq = musb_resume_noirq,
2456 .runtime_suspend = musb_runtime_suspend,
2457 .runtime_resume = musb_runtime_resume,
2458};
2459
2460#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2461#else
2462#define MUSB_DEV_PM_OPS NULL
2463#endif
2464
2465static struct platform_driver musb_driver = {
2466 .driver = {
2467 .name = (char *)musb_driver_name,
2468 .bus = &platform_bus_type,
2469 .owner = THIS_MODULE,
2470 .pm = MUSB_DEV_PM_OPS,
2471 },
2472 .probe = musb_probe,
2473 .remove = __devexit_p(musb_remove),
2474 .shutdown = musb_shutdown,
2475};
2476
2477/*-------------------------------------------------------------------------*/
2478
2479static int __init musb_init(void)
2480{
2481 if (usb_disabled())
2482 return 0;
2483
2484 pr_info("%s: version " MUSB_VERSION ", "
2485 "?dma?"
2486 ", "
2487 "otg (peripheral+host)",
2488 musb_driver_name);
2489 return platform_driver_register(&musb_driver);
2490}
2491module_init(musb_init);
2492
2493static void __exit musb_cleanup(void)
2494{
2495 platform_driver_unregister(&musb_driver);
2496}
2497module_exit(musb_cleanup);
2498#endif
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