[thirdparty/u-boot.git] / drivers / video / anx9804.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) 2015 Hans de Goede <hdegoede@redhat.com>
 */

/*
 * Support for the ANX9804 bridge chip, which can take pixel data coming
 * from a parallel LCD interface and translate it on the flight into a DP
 * interface for driving eDP TFT displays.
 */

#include <common.h>
#include <i2c.h>
#include <linux/delay.h>
#include "anx98xx-edp.h"
#include "anx9804.h"

/**
 * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
 *
 * This function will init an anx9804 parallel lcd to dp bridge chip
 * using the passed in parameters.
 *
 * @i2c_bus:	Device of the i2c bus to which the anx9804 is connected.
 * @lanes:	Number of displayport lanes to use
 * @data_rate:	Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
 * @bpp:	Bits per pixel, must be 18 or 24
 */
void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
{
	struct udevice *chip0, *chip1;
	int c, colordepth, i, ret;

	ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
	if (ret)
		return;

	ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
	if (ret)
		return;

	if (bpp == 18)
		colordepth = 0x00; /* 6 bit */
	else
		colordepth = 0x10; /* 8 bit */

	/* Reset */
	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
	mdelay(100);
	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);

	/* Write 0 to the powerdown reg (powerup everything) */
	dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);

	c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
	if (c != 0x98) {
		printf("Error anx9804 chipid mismatch\n");
		return;
	}

	for (i = 0; i < 100; i++) {
		c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
		dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
		c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
		if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
			break;

		mdelay(5);
	}
	if (i == 100)
		printf("Error anx9804 clock is not stable\n");

	dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);

	/* Set a bunch of analog related register values */
	dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
	dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
	dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
	dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
	dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
	dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
	dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
	dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);

	/* Force HPD */
	dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
			 ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);

	/* Power up and configure lanes */
	dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);

	/* Reset AUX CH */
	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
			 ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
			 ANX9804_RST_CTRL2_AC_MODE);

	/* Powerdown audio and some other unused bits */
	dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
	dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
	dm_i2c_reg_write(chip0, 0xa7, 0x00);

	/* Set data-rate / lanes */
	dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
	dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);

	/* Link training */
	dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
			 ANX9804_LINK_TRAINING_CTRL_EN);
	mdelay(5);
	for (i = 0; i < 100; i++) {
		c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
		if ((c & 0x01) == 0)
			break;

		mdelay(5);
	}
	if(i == 100) {
		printf("Error anx9804 link training timeout\n");
		return;
	}

	/* Enable */
	dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
			 ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
	/* Force stream valid */
	dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
			 ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
			 ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
66525bb7 HG	2	/*
66525bb7 HG	3	* (C) 2015 Hans de Goede <hdegoede@redhat.com>
66525bb7 HG	4	*/
	5
	6	/*
	7	* Support for the ANX9804 bridge chip, which can take pixel data coming
	8	* from a parallel LCD interface and translate it on the flight into a DP
	9	* interface for driving eDP TFT displays.
	10	*/
	11
d678a59d	12	#include <common.h>
66525bb7	13	#include <i2c.h>
c05ed00a	14	#include <linux/delay.h>
24bf59d0	15	#include "anx98xx-edp.h"
66525bb7 HG	16	#include "anx9804.h"
66525bb7 HG	17
66525bb7 HG	18	/**
	19	* anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
	20	*
	21	* This function will init an anx9804 parallel lcd to dp bridge chip
	22	* using the passed in parameters.
	23	*
2421497c	24	* @i2c_bus: Device of the i2c bus to which the anx9804 is connected.
66525bb7 HG	25	* @lanes: Number of displayport lanes to use
	26	* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
	27	* @bpp: Bits per pixel, must be 18 or 24
	28	*/
2421497c	29	void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
66525bb7	30	{
2421497c SH	31	struct udevice chip0, chip1;
2421497c SH	32	int c, colordepth, i, ret;
66525bb7	33
2421497c SH	34	ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
	35	if (ret)
	36	return;
	37
	38	ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
	39	if (ret)
	40	return;
66525bb7 HG	41
	42	if (bpp == 18)
	43	colordepth = 0x00; /* 6 bit */
	44	else
	45	colordepth = 0x10; /* 8 bit */
	46
	47	/* Reset */
2421497c	48	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
66525bb7	49	mdelay(100);
2421497c	50	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);
66525bb7 HG	51
66525bb7 HG	52	/* Write 0 to the powerdown reg (powerup everything) */
2421497c	53	dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);
66525bb7	54
2421497c	55	c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
66525bb7 HG	56	if (c != 0x98) {
66525bb7 HG	57	printf("Error anx9804 chipid mismatch\n");
66525bb7 HG	58	return;
	59	}
	60
	61	for (i = 0; i < 100; i++) {
2421497c SH	62	c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
	63	dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
	64	c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
66525bb7 HG	65	if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
	66	break;
	67
	68	mdelay(5);
	69	}
	70	if (i == 100)
	71	printf("Error anx9804 clock is not stable\n");
	72
2421497c	73	dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);
0a50b3c9	74
66525bb7	75	/* Set a bunch of analog related register values */
2421497c SH	76	dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
	77	dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
	78	dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
	79	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
	80	dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
	81	dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
	82	dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
	83	dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
	84	dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);
66525bb7 HG	85
66525bb7 HG	86	/* Force HPD */
2421497c SH	87	dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
2421497c SH	88	ANX9804_SYS_CTRL3_F_HPD \| ANX9804_SYS_CTRL3_HPD_CTRL);
66525bb7 HG	89
66525bb7 HG	90	/* Power up and configure lanes */
2421497c SH	91	dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
	92	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
	93	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
	94	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
	95	dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
66525bb7 HG	96
66525bb7 HG	97	/* Reset AUX CH */
2421497c SH	98	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
	99	ANX9804_RST_CTRL2_AC_MODE \| ANX9804_RST_CTRL2_AUX);
	100	dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
	101	ANX9804_RST_CTRL2_AC_MODE);
66525bb7 HG	102
66525bb7 HG	103	/* Powerdown audio and some other unused bits */
2421497c SH	104	dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
	105	dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
	106	dm_i2c_reg_write(chip0, 0xa7, 0x00);
66525bb7 HG	107
66525bb7 HG	108	/* Set data-rate / lanes */
2421497c SH	109	dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
2421497c SH	110	dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
66525bb7	111
0a50b3c9	112	/* Link training */
2421497c SH	113	dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
2421497c SH	114	ANX9804_LINK_TRAINING_CTRL_EN);
66525bb7 HG	115	mdelay(5);
66525bb7 HG	116	for (i = 0; i < 100; i++) {
2421497c	117	c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
66525bb7 HG	118	if ((c & 0x01) == 0)
	119	break;
	120
	121	mdelay(5);
	122	}
	123	if(i == 100) {
	124	printf("Error anx9804 link training timeout\n");
66525bb7 HG	125	return;
	126	}
	127
	128	/* Enable */
2421497c SH	129	dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
2421497c SH	130	ANX9804_VID_CTRL1_VID_EN \| ANX9804_VID_CTRL1_EDGE);
66525bb7	131	/* Force stream valid */
2421497c SH	132	dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
	133	ANX9804_SYS_CTRL3_F_HPD \| ANX9804_SYS_CTRL3_HPD_CTRL \|
	134	ANX9804_SYS_CTRL3_F_VALID \| ANX9804_SYS_CTRL3_VALID_CTRL);
66525bb7	135	}