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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / video / ivybridge_igd.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0
2c943804
SG		 2/*
3 * Copyright (C) 2016 Google, Inc
2c943804
SG		 4 */
5
d678a59d 6#include <common.h>
2c943804
SG		 7#include <bios_emul.h>
8#include <dm.h>
9#include <errno.h>
10#include <fdtdec.h>
f7ae49fc 11#include <log.h>
2c943804 12#include <pci_rom.h>
cafe8712 13#include <vesa.h>
a67b0db2 14#include <video.h>
401d1c4f 15#include <asm/global_data.h>
2c943804
SG		 16#include <asm/intel_regs.h>
17#include <asm/io.h>
18#include <asm/mtrr.h>
19#include <asm/pci.h>
20#include <asm/arch/pch.h>
21#include <asm/arch/sandybridge.h>
c05ed00a 22#include <linux/delay.h>
2c943804 23
05af050e
SG		 24DECLARE_GLOBAL_DATA_PTR;
25
2c943804
SG		 26struct gt_powermeter {
27 u16 reg;
28 u32 value;
29};
30
31/* These are magic values - unfortunately the meaning is unknown */
32static const struct gt_powermeter snb_pm_gt1[] = {
33 { 0xa200, 0xcc000000 },
34 { 0xa204, 0x07000040 },
35 { 0xa208, 0x0000fe00 },
36 { 0xa20c, 0x00000000 },
37 { 0xa210, 0x17000000 },
38 { 0xa214, 0x00000021 },
39 { 0xa218, 0x0817fe19 },
40 { 0xa21c, 0x00000000 },
41 { 0xa220, 0x00000000 },
42 { 0xa224, 0xcc000000 },
43 { 0xa228, 0x07000040 },
44 { 0xa22c, 0x0000fe00 },
45 { 0xa230, 0x00000000 },
46 { 0xa234, 0x17000000 },
47 { 0xa238, 0x00000021 },
48 { 0xa23c, 0x0817fe19 },
49 { 0xa240, 0x00000000 },
50 { 0xa244, 0x00000000 },
51 { 0xa248, 0x8000421e },
52 { 0 }
53};
54
55static const struct gt_powermeter snb_pm_gt2[] = {
56 { 0xa200, 0x330000a6 },
57 { 0xa204, 0x402d0031 },
58 { 0xa208, 0x00165f83 },
59 { 0xa20c, 0xf1000000 },
60 { 0xa210, 0x00000000 },
61 { 0xa214, 0x00160016 },
62 { 0xa218, 0x002a002b },
63 { 0xa21c, 0x00000000 },
64 { 0xa220, 0x00000000 },
65 { 0xa224, 0x330000a6 },
66 { 0xa228, 0x402d0031 },
67 { 0xa22c, 0x00165f83 },
68 { 0xa230, 0xf1000000 },
69 { 0xa234, 0x00000000 },
70 { 0xa238, 0x00160016 },
71 { 0xa23c, 0x002a002b },
72 { 0xa240, 0x00000000 },
73 { 0xa244, 0x00000000 },
74 { 0xa248, 0x8000421e },
75 { 0 }
76};
77
78static const struct gt_powermeter ivb_pm_gt1[] = {
79 { 0xa800, 0x00000000 },
80 { 0xa804, 0x00021c00 },
81 { 0xa808, 0x00000403 },
82 { 0xa80c, 0x02001700 },
83 { 0xa810, 0x05000200 },
84 { 0xa814, 0x00000000 },
85 { 0xa818, 0x00690500 },
86 { 0xa81c, 0x0000007f },
87 { 0xa820, 0x01002501 },
88 { 0xa824, 0x00000300 },
89 { 0xa828, 0x01000331 },
90 { 0xa82c, 0x0000000c },
91 { 0xa830, 0x00010016 },
92 { 0xa834, 0x01100101 },
93 { 0xa838, 0x00010103 },
94 { 0xa83c, 0x00041300 },
95 { 0xa840, 0x00000b30 },
96 { 0xa844, 0x00000000 },
97 { 0xa848, 0x7f000000 },
98 { 0xa84c, 0x05000008 },
99 { 0xa850, 0x00000001 },
100 { 0xa854, 0x00000004 },
101 { 0xa858, 0x00000007 },
102 { 0xa85c, 0x00000000 },
103 { 0xa860, 0x00010000 },
104 { 0xa248, 0x0000221e },
105 { 0xa900, 0x00000000 },
106 { 0xa904, 0x00001c00 },
107 { 0xa908, 0x00000000 },
108 { 0xa90c, 0x06000000 },
109 { 0xa910, 0x09000200 },
110 { 0xa914, 0x00000000 },
111 { 0xa918, 0x00590000 },
112 { 0xa91c, 0x00000000 },
113 { 0xa920, 0x04002501 },
114 { 0xa924, 0x00000100 },
115 { 0xa928, 0x03000410 },
116 { 0xa92c, 0x00000000 },
117 { 0xa930, 0x00020000 },
118 { 0xa934, 0x02070106 },
119 { 0xa938, 0x00010100 },
120 { 0xa93c, 0x00401c00 },
121 { 0xa940, 0x00000000 },
122 { 0xa944, 0x00000000 },
123 { 0xa948, 0x10000e00 },
124 { 0xa94c, 0x02000004 },
125 { 0xa950, 0x00000001 },
126 { 0xa954, 0x00000004 },
127 { 0xa960, 0x00060000 },
128 { 0xaa3c, 0x00001c00 },
129 { 0xaa54, 0x00000004 },
130 { 0xaa60, 0x00060000 },
131 { 0 }
132};
133
2c943804
SG		 134static const struct gt_powermeter ivb_pm_gt2_17w[] = {
135 { 0xa800, 0x20000000 },
136 { 0xa804, 0x000e3800 },
137 { 0xa808, 0x00000806 },
138 { 0xa80c, 0x0c002f00 },
139 { 0xa810, 0x0c000800 },
140 { 0xa814, 0x00000000 },
141 { 0xa818, 0x00d20d00 },
142 { 0xa81c, 0x000000ff },
143 { 0xa820, 0x03004b02 },
144 { 0xa824, 0x00000600 },
145 { 0xa828, 0x07000773 },
146 { 0xa82c, 0x00000000 },
147 { 0xa830, 0x00020032 },
148 { 0xa834, 0x1520040d },
149 { 0xa838, 0x00020105 },
150 { 0xa83c, 0x00083700 },
151 { 0xa840, 0x000016ff },
152 { 0xa844, 0x00000000 },
153 { 0xa848, 0xff000000 },
154 { 0xa84c, 0x0a000010 },
155 { 0xa850, 0x00000002 },
156 { 0xa854, 0x00000008 },
157 { 0xa858, 0x0000000f },
158 { 0xa85c, 0x00000000 },
159 { 0xa860, 0x00020000 },
160 { 0xa248, 0x0000221e },
161 { 0xa900, 0x00000000 },
162 { 0xa904, 0x00003800 },
163 { 0xa908, 0x00000000 },
164 { 0xa90c, 0x0c000000 },
165 { 0xa910, 0x12000800 },
166 { 0xa914, 0x00000000 },
167 { 0xa918, 0x00b20000 },
168 { 0xa91c, 0x00000000 },
169 { 0xa920, 0x08004b02 },
170 { 0xa924, 0x00000300 },
171 { 0xa928, 0x01000820 },
172 { 0xa92c, 0x00000000 },
173 { 0xa930, 0x00030000 },
174 { 0xa934, 0x15150406 },
175 { 0xa938, 0x00020300 },
176 { 0xa93c, 0x00903900 },
177 { 0xa940, 0x00000000 },
178 { 0xa944, 0x00000000 },
179 { 0xa948, 0x20001b00 },
180 { 0xa94c, 0x0a000010 },
181 { 0xa950, 0x00000000 },
182 { 0xa954, 0x00000008 },
183 { 0xa960, 0x00110000 },
184 { 0xaa3c, 0x00003900 },
185 { 0xaa54, 0x00000008 },
186 { 0xaa60, 0x00110000 },
187 { 0 }
188};
189
190static const struct gt_powermeter ivb_pm_gt2_35w[] = {
191 { 0xa800, 0x00000000 },
192 { 0xa804, 0x00030400 },
193 { 0xa808, 0x00000806 },
194 { 0xa80c, 0x0c002f00 },
195 { 0xa810, 0x0c000300 },
196 { 0xa814, 0x00000000 },
197 { 0xa818, 0x00d20d00 },
198 { 0xa81c, 0x000000ff },
199 { 0xa820, 0x03004b02 },
200 { 0xa824, 0x00000600 },
201 { 0xa828, 0x07000773 },
202 { 0xa82c, 0x00000000 },
203 { 0xa830, 0x00020032 },
204 { 0xa834, 0x1520040d },
205 { 0xa838, 0x00020105 },
206 { 0xa83c, 0x00083700 },
207 { 0xa840, 0x000016ff },
208 { 0xa844, 0x00000000 },
209 { 0xa848, 0xff000000 },
210 { 0xa84c, 0x0a000010 },
211 { 0xa850, 0x00000001 },
212 { 0xa854, 0x00000008 },
213 { 0xa858, 0x00000008 },
214 { 0xa85c, 0x00000000 },
215 { 0xa860, 0x00020000 },
216 { 0xa248, 0x0000221e },
217 { 0xa900, 0x00000000 },
218 { 0xa904, 0x00003800 },
219 { 0xa908, 0x00000000 },
220 { 0xa90c, 0x0c000000 },
221 { 0xa910, 0x12000800 },
222 { 0xa914, 0x00000000 },
223 { 0xa918, 0x00b20000 },
224 { 0xa91c, 0x00000000 },
225 { 0xa920, 0x08004b02 },
226 { 0xa924, 0x00000300 },
227 { 0xa928, 0x01000820 },
228 { 0xa92c, 0x00000000 },
229 { 0xa930, 0x00030000 },
230 { 0xa934, 0x15150406 },
231 { 0xa938, 0x00020300 },
232 { 0xa93c, 0x00903900 },
233 { 0xa940, 0x00000000 },
234 { 0xa944, 0x00000000 },
235 { 0xa948, 0x20001b00 },
236 { 0xa94c, 0x0a000010 },
237 { 0xa950, 0x00000000 },
238 { 0xa954, 0x00000008 },
239 { 0xa960, 0x00110000 },
240 { 0xaa3c, 0x00003900 },
241 { 0xaa54, 0x00000008 },
242 { 0xaa60, 0x00110000 },
243 { 0 }
244};
245
246static inline u32 gtt_read(void *bar, u32 reg)
247{
248 return readl(bar + reg);
249}
250
251static inline void gtt_write(void *bar, u32 reg, u32 data)
252{
253 writel(data, bar + reg);
254}
255
256static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
257{
258 for (; pm && pm->reg; pm++)
259 gtt_write(bar, pm->reg, pm->value);
260}
261
262#define GTT_RETRY 1000
263static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
264{
265 unsigned try = GTT_RETRY;
266 u32 data;
267
268 while (try--) {
269 data = gtt_read(bar, reg);
270 if ((data & mask) == value)
271 return 1;
272 udelay(10);
273 }
274
275 printf("GT init timeout\n");
276 return 0;
277}
278
279static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
280{
281 u32 reg32;
282
283 debug("GT Power Management Init, silicon = %#x\n", rev);
284
285 if (rev < IVB_STEP_C0) {
286 /* 1: Enable force wake */
287 gtt_write(gtt_bar, 0xa18c, 0x00000001);
288 gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
289 } else {
290 gtt_write(gtt_bar, 0xa180, 1 << 5);
291 gtt_write(gtt_bar, 0xa188, 0xffff0001);
292 gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
293 }
294
295 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
296 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
297 reg32 = gtt_read(gtt_bar, 0x42004);
298 reg32 |= (1 << 14) | (1 << 15);
299 gtt_write(gtt_bar, 0x42004, reg32);
300 }
301
302 if (rev >= IVB_STEP_A0) {
303 /* Display Reset Acknowledge Settings */
304 reg32 = gtt_read(gtt_bar, 0x45010);
305 reg32 |= (1 << 1) | (1 << 0);
306 gtt_write(gtt_bar, 0x45010, reg32);
307 }
308
309 /* 2: Get GT SKU from GTT+0x911c[13] */
310 reg32 = gtt_read(gtt_bar, 0x911c);
311 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
312 if (reg32 & (1 << 13)) {
313 debug("SNB GT1 Power Meter Weights\n");
314 gtt_write_powermeter(gtt_bar, snb_pm_gt1);
315 } else {
316 debug("SNB GT2 Power Meter Weights\n");
317 gtt_write_powermeter(gtt_bar, snb_pm_gt2);
318 }
319 } else {
320 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
321
322 if (reg32 & (1 << 13)) {
323 /* GT1 SKU */
324 debug("IVB GT1 Power Meter Weights\n");
325 gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
326 } else {
327 /* GT2 SKU */
328 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
329 tdp /= (1 << unit);
330
331 if (tdp <= 17) {
332 /* <=17W ULV */
333 debug("IVB GT2 17W Power Meter Weights\n");
334 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
335 } else if ((tdp >= 25) && (tdp <= 35)) {
336 /* 25W-35W */
337 debug("IVB GT2 25W-35W Power Meter Weights\n");
338 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
339 } else {
340 /* All others */
341 debug("IVB GT2 35W Power Meter Weights\n");
342 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
343 }
344 }
345 }
346
347 /* 3: Gear ratio map */
348 gtt_write(gtt_bar, 0xa004, 0x00000010);
349
350 /* 4: GFXPAUSE */
351 gtt_write(gtt_bar, 0xa000, 0x00070020);
352
353 /* 5: Dynamic EU trip control */
354 gtt_write(gtt_bar, 0xa080, 0x00000004);
355
356 /* 6: ECO bits */
357 reg32 = gtt_read(gtt_bar, 0xa180);
358 reg32 |= (1 << 26) | (1 << 31);
359 /* (bit 20=1 for SNB step D1+ / IVB A0+) */
360 if (rev >= SNB_STEP_D1)
361 reg32 |= (1 << 20);
362 gtt_write(gtt_bar, 0xa180, reg32);
363
364 /* 6a: for SnB step D2+ only */
365 if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
366 (rev >= SNB_STEP_D2)) {
367 reg32 = gtt_read(gtt_bar, 0x9400);
368 reg32 |= (1 << 7);
369 gtt_write(gtt_bar, 0x9400, reg32);
370
371 reg32 = gtt_read(gtt_bar, 0x941c);
372 reg32 &= 0xf;
373 reg32 |= (1 << 1);
374 gtt_write(gtt_bar, 0x941c, reg32);
375 gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
376 }
377
378 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
379 reg32 = gtt_read(gtt_bar, 0x907c);
380 reg32 |= (1 << 16);
381 gtt_write(gtt_bar, 0x907c, reg32);
382
383 /* 6b: Clocking reset controls */
384 gtt_write(gtt_bar, 0x9424, 0x00000001);
385 } else {
386 /* 6b: Clocking reset controls */
387 gtt_write(gtt_bar, 0x9424, 0x00000000);
388 }
389
390 /* 7 */
391 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
392 gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
393 /* Mailbox Cmd for RC6 VID */
394 gtt_write(gtt_bar, 0x138124, 0x80000004);
395 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
396 gtt_write(gtt_bar, 0x138124, 0x8000000a);
397 gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
398 }
399
400 /* 8 */
401 gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
402 gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
403 gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
404 gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
405 gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
406 gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
407
408 /* 9 */
409 gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
410 gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
411 gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
412
413 /* 10 */
414 gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
415 gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
416 gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
417 gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
418 gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
419
420 /* 11 */
421 gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
422 gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
423 gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
424 gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
425 gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
426 gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
427 gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
428
429 /* 11a: Enable Render Standby (RC6) */
430 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
431 /*
432 * IvyBridge should also support DeepRenderStandby.
433 *
434 * Unfortunately it does not work reliably on all SKUs so
435 * disable it here and it can be enabled by the kernel.
436 */
437 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
438 } else {
439 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
440 }
441
442 /* 12: Normal Frequency Request */
443 /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
444 reg32 = readl(MCHBAR_REG(0x5998));
445 reg32 >>= 16;
446 reg32 &= 0xef;
447 reg32 <<= 25;
448 gtt_write(gtt_bar, 0xa008, reg32);
449
450 /* 13: RP Control */
451 gtt_write(gtt_bar, 0xa024, 0x00000592);
452
453 /* 14: Enable PM Interrupts */
454 gtt_write(gtt_bar, 0x4402c, 0x03000076);
455
456 /* Clear 0x6c024 [8:6] */
457 reg32 = gtt_read(gtt_bar, 0x6c024);
458 reg32 &= ~0x000001c0;
459 gtt_write(gtt_bar, 0x6c024, reg32);
460
461 return 0;
462}
463
464static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
465{
466 const void *blob = gd->fdt_blob;
e160f7d4 467 int node = dev_of_offset(dev);
2c943804
SG		 468 u32 reg32, cycle_delay;
469
470 debug("GT Power Management Init (post VBIOS)\n");
471
472 /* 15: Deassert Force Wake */
473 if (rev < IVB_STEP_C0) {
474 gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
475 gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
476 } else {
477 gtt_write(gtt_bar, 0xa188, 0x1fffe);
478 if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
479 gtt_write(gtt_bar, 0xa188,
480 gtt_read(gtt_bar, 0xa188) | 1);
481 }
482 }
483
484 /* 16: SW RC Control */
485 gtt_write(gtt_bar, 0xa094, 0x00060000);
486
487 /* Setup Digital Port Hotplug */
488 reg32 = gtt_read(gtt_bar, 0xc4030);
489 if (!reg32) {
490 u32 dp_hotplug[3];
491
492 if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
493 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
494 return -EINVAL;
495
496 reg32 = (dp_hotplug[0] & 0x7) << 2;
497 reg32 |= (dp_hotplug[0] & 0x7) << 10;
498 reg32 |= (dp_hotplug[0] & 0x7) << 18;
499 gtt_write(gtt_bar, 0xc4030, reg32);
500 }
501
502 /* Setup Panel Power On Delays */
503 reg32 = gtt_read(gtt_bar, 0xc7208);
504 if (!reg32) {
505 reg32 = (unsigned)fdtdec_get_int(blob, node,
506 "panel-port-select", 0) << 30;
507 reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
508 << 16;
509 reg32 |= fdtdec_get_int(blob, node,
510 "panel-power-backlight-on-delay", 0);
511 gtt_write(gtt_bar, 0xc7208, reg32);
512 }
513
514 /* Setup Panel Power Off Delays */
515 reg32 = gtt_read(gtt_bar, 0xc720c);
516 if (!reg32) {
517 reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
518 << 16;
519 reg32 |= fdtdec_get_int(blob, node,
520 "panel-power-backlight-off-delay", 0);
521 gtt_write(gtt_bar, 0xc720c, reg32);
522 }
523
524 /* Setup Panel Power Cycle Delay */
525 cycle_delay = fdtdec_get_int(blob, node,
526 "intel,panel-power-cycle-delay", 0);
527 if (cycle_delay) {
528 reg32 = gtt_read(gtt_bar, 0xc7210);
529 reg32 &= ~0xff;
530 reg32 |= cycle_delay;
531 gtt_write(gtt_bar, 0xc7210, reg32);
532 }
533
534 /* Enable Backlight if needed */
535 reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
536 if (reg32) {
537 gtt_write(gtt_bar, 0x48250, (1 << 31));
538 gtt_write(gtt_bar, 0x48254, reg32);
539 }
540 reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
541 if (reg32) {
542 gtt_write(gtt_bar, 0xc8250, (1 << 31));
543 gtt_write(gtt_bar, 0xc8254, reg32);
544 }
545
546 return 0;
547}
548
549/*
550 * Some vga option roms are used for several chipsets but they only have one
551 * PCI ID in their header. If we encounter such an option rom, we need to do
552 * the mapping ourselves.
553 */
554
555uint32_t board_map_oprom_vendev(uint32_t vendev)
556{
557 switch (vendev) {
558 case 0x80860102: /* GT1 Desktop */
559 case 0x8086010a: /* GT1 Server */
560 case 0x80860112: /* GT2 Desktop */
561 case 0x80860116: /* GT2 Mobile */
562 case 0x80860122: /* GT2 Desktop >=1.3GHz */
563 case 0x80860126: /* GT2 Mobile >=1.3GHz */
564 case 0x80860156: /* IVB */
565 case 0x80860166: /* IVB */
566 return 0x80860106; /* GT1 Mobile */
567 }
568
569 return vendev;
570}
571
572static int int15_handler(void)
573{
574 int res = 0;
575
576 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
577
578 switch (M.x86.R_AX) {
579 case 0x5f34:
580 /*
581 * Set Panel Fitting Hook:
582 * bit 2 = Graphics Stretching
583 * bit 1 = Text Stretching
584 * bit 0 = Centering (do not set with bit1 or bit2)
585 * 0 = video bios default
586 */
587 M.x86.R_AX = 0x005f;
588 M.x86.R_CL = 0x00; /* Use video bios default */
589 res = 1;
590 break;
591 case 0x5f35:
592 /*
593 * Boot Display Device Hook:
594 * bit 0 = CRT
595 * bit 1 = TV (eDP)
596 * bit 2 = EFP
597 * bit 3 = LFP
598 * bit 4 = CRT2
599 * bit 5 = TV2 (eDP)
600 * bit 6 = EFP2
601 * bit 7 = LFP2
602 */
603 M.x86.R_AX = 0x005f;
604 M.x86.R_CX = 0x0000; /* Use video bios default */
605 res = 1;
606 break;
607 case 0x5f51:
608 /*
609 * Hook to select active LFP configuration:
610 * 00h = No LVDS, VBIOS does not enable LVDS
611 * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
612 * 02h = SVDO-LVDS, LFP driven by SVDO decoder
613 * 03h = eDP, LFP Driven by Int-DisplayPort encoder
614 */
615 M.x86.R_AX = 0x005f;
616 M.x86.R_CX = 0x0003; /* eDP */
617 res = 1;
618 break;
619 case 0x5f70:
620 switch (M.x86.R_CH) {
621 case 0:
622 /* Get Mux */
623 M.x86.R_AX = 0x005f;
624 M.x86.R_CX = 0x0000;
625 res = 1;
626 break;
627 case 1:
628 /* Set Mux */
629 M.x86.R_AX = 0x005f;
630 M.x86.R_CX = 0x0000;
631 res = 1;
632 break;
633 case 2:
634 /* Get SG/Non-SG mode */
635 M.x86.R_AX = 0x005f;
636 M.x86.R_CX = 0x0000;
637 res = 1;
638 break;
639 default:
640 /* Interrupt was not handled */
641 debug("Unknown INT15 5f70 function: 0x%02x\n",
642 M.x86.R_CH);
643 break;
644 }
645 break;
646 case 0x5fac:
647 res = 1;
648 break;
649 default:
650 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
651 break;
652 }
653 return res;
654}
655
656static void sandybridge_setup_graphics(struct udevice *dev,
657 struct udevice *video_dev)
658{
659 u32 reg32;
660 u16 reg16;
661 u8 reg8;
662
663 dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16);
664 switch (reg16) {
665 case 0x0102: /* GT1 Desktop */
666 case 0x0106: /* GT1 Mobile */
667 case 0x010a: /* GT1 Server */
668 case 0x0112: /* GT2 Desktop */
669 case 0x0116: /* GT2 Mobile */
670 case 0x0122: /* GT2 Desktop >=1.3GHz */
671 case 0x0126: /* GT2 Mobile >=1.3GHz */
672 case 0x0156: /* IvyBridge */
673 case 0x0166: /* IvyBridge */
674 break;
675 default:
676 debug("Graphics not supported by this CPU/chipset\n");
677 return;
678 }
679
680 debug("Initialising Graphics\n");
681
682 /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
683 dm_pci_read_config16(dev, GGC, &reg16);
684 reg16 &= ~0x00f8;
685 reg16 |= 1 << 3;
686 /* Program GTT memory by setting GGC[9:8] = 2MB */
687 reg16 &= ~0x0300;
688 reg16 |= 2 << 8;
689 /* Enable VGA decode */
690 reg16 &= ~0x0002;
691 dm_pci_write_config16(dev, GGC, reg16);
692
693 /* Enable 256MB aperture */
694 dm_pci_read_config8(video_dev, MSAC, &reg8);
695 reg8 &= ~0x06;
696 reg8 |= 0x02;
697 dm_pci_write_config8(video_dev, MSAC, reg8);
698
699 /* Erratum workarounds */
700 reg32 = readl(MCHBAR_REG(0x5f00));
701 reg32 |= (1 << 9) | (1 << 10);
702 writel(reg32, MCHBAR_REG(0x5f00));
703
704 /* Enable SA Clock Gating */
705 reg32 = readl(MCHBAR_REG(0x5f00));
706 writel(reg32 | 1, MCHBAR_REG(0x5f00));
707
708 /* GPU RC6 workaround for sighting 366252 */
709 reg32 = readl(MCHBAR_REG(0x5d14));
710 reg32 |= (1 << 31);
711 writel(reg32, MCHBAR_REG(0x5d14));
712
713 /* VLW */
714 reg32 = readl(MCHBAR_REG(0x6120));
715 reg32 &= ~(1 << 0);
716 writel(reg32, MCHBAR_REG(0x6120));
717
718 reg32 = readl(MCHBAR_REG(0x5418));
719 reg32 |= (1 << 4) | (1 << 5);
720 writel(reg32, MCHBAR_REG(0x5418));
721}
722
723static int gma_func0_init(struct udevice *dev)
724{
725 struct udevice *nbridge;
726 void *gtt_bar;
2c943804
SG		 727 u32 reg32;
728 int ret;
729 int rev;
730
731 /* Enable PCH Display Port */
732 writew(0x0010, RCB_REG(DISPBDF));
733 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
734
735 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
736 if (ret)
737 return ret;
738 rev = bridge_silicon_revision(nbridge);
739 sandybridge_setup_graphics(nbridge, dev);
740
741 /* IGD needs to be Bus Master */
742 dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
743 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
744 dm_pci_write_config32(dev, PCI_COMMAND, reg32);
745
c7ccb2c0 746 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
2c943804
SG		 747 debug("GT bar %p\n", gtt_bar);
748 ret = gma_pm_init_pre_vbios(gtt_bar, rev);
749 if (ret)
750 return ret;
751
752 return rev;
753}
754
755static int bd82x6x_video_probe(struct udevice *dev)
756{
8a8d24bd 757 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
a67b0db2 758 ulong fbbase;
2c943804
SG		 759 void *gtt_bar;
760 int ret, rev;
761
762 rev = gma_func0_init(dev);
763 if (rev < 0)
764 return rev;
da62e1e8 765 ret = vesa_setup_video(dev, int15_handler);
2c943804
SG		 766 if (ret)
767 return ret;
768
769 /* Post VBIOS init */
c7ccb2c0 770 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
2c943804
SG		 771 ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
772 if (ret)
773 return ret;
774
a67b0db2
SG		 775 /* Use write-combining for the graphics memory, 256MB */
776 fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
0f497b2b 777 mtrr_set_next_var(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
a67b0db2
SG		 778
779 return 0;
780}
781
782static int bd82x6x_video_bind(struct udevice *dev)
783{
8a8d24bd 784 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
a67b0db2
SG		 785
786 /* Set the maximum supported resolution */
787 uc_plat->size = 2560 * 1600 * 4;
788 log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
789
2c943804
SG		 790 return 0;
791}
792
793static const struct udevice_id bd82x6x_video_ids[] = {
794 { .compatible = "intel,gma" },
795 { }
796};
797
798U_BOOT_DRIVER(bd82x6x_video) = {
799 .name = "bd82x6x_video",
800 .id = UCLASS_VIDEO,
801 .of_match = bd82x6x_video_ids,
a67b0db2 802 .bind = bd82x6x_video_bind,
2c943804
SG		 803 .probe = bd82x6x_video_probe,
804};
"Das U-Boot" Source Tree