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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c2539483 | 2 | /* |
147fd3ac | 3 | * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH |
c2539483 SG |
4 | * Copyright (c) 2015 Google, Inc |
5 | * Copyright 2014 Rockchip Inc. | |
c2539483 SG |
6 | */ |
7 | ||
d678a59d | 8 | #include <common.h> |
c2539483 SG |
9 | #include <clk.h> |
10 | #include <display.h> | |
11 | #include <dm.h> | |
cc232a9d | 12 | #include <dw_hdmi.h> |
c2539483 | 13 | #include <edid.h> |
f7ae49fc | 14 | #include <log.h> |
c2539483 SG |
15 | #include <regmap.h> |
16 | #include <syscon.h> | |
17 | #include <asm/gpio.h> | |
15f09a1a KY |
18 | #include <asm/arch-rockchip/clock.h> |
19 | #include <asm/arch-rockchip/hardware.h> | |
147fd3ac PT |
20 | #include "rk_hdmi.h" |
21 | #include "rk_vop.h" /* for rk_vop_probe_regulators */ | |
c2539483 | 22 | |
c2539483 SG |
23 | static const struct hdmi_phy_config rockchip_phy_config[] = { |
24 | { | |
0fc41e55 | 25 | .mpixelclock = 74250000, |
c2539483 SG |
26 | .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272, |
27 | }, { | |
0fc41e55 | 28 | .mpixelclock = 148500000, |
c2539483 SG |
29 | .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d, |
30 | }, { | |
0fc41e55 | 31 | .mpixelclock = 297000000, |
c2539483 | 32 | .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, |
f210e557 PT |
33 | }, { |
34 | .mpixelclock = 584000000, | |
35 | .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d, | |
c2539483 SG |
36 | }, { |
37 | .mpixelclock = ~0ul, | |
38 | .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000, | |
39 | } | |
40 | }; | |
41 | ||
42 | static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { | |
43 | { | |
0fc41e55 | 44 | .mpixelclock = 40000000, |
c2539483 SG |
45 | .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018, |
46 | }, { | |
0fc41e55 | 47 | .mpixelclock = 65000000, |
c2539483 SG |
48 | .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, |
49 | }, { | |
0fc41e55 | 50 | .mpixelclock = 66000000, |
c2539483 SG |
51 | .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038, |
52 | }, { | |
94412745 | 53 | .mpixelclock = 83500000, |
c2539483 SG |
54 | .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, |
55 | }, { | |
0fc41e55 | 56 | .mpixelclock = 146250000, |
c2539483 SG |
57 | .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038, |
58 | }, { | |
0fc41e55 | 59 | .mpixelclock = 148500000, |
c2539483 | 60 | .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, |
f210e557 PT |
61 | }, { |
62 | .mpixelclock = 272000000, | |
63 | .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000, | |
64 | }, { | |
65 | .mpixelclock = 340000000, | |
66 | .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000, | |
c2539483 SG |
67 | }, { |
68 | .mpixelclock = ~0ul, | |
69 | .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, | |
70 | } | |
71 | }; | |
72 | ||
147fd3ac | 73 | int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) |
c2539483 SG |
74 | { |
75 | struct rk_hdmi_priv *priv = dev_get_priv(dev); | |
c2539483 | 76 | |
cc232a9d | 77 | return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); |
c2539483 SG |
78 | } |
79 | ||
d1998a9f | 80 | int rk_hdmi_of_to_plat(struct udevice *dev) |
c2539483 SG |
81 | { |
82 | struct rk_hdmi_priv *priv = dev_get_priv(dev); | |
cc232a9d JS |
83 | struct dw_hdmi *hdmi = &priv->hdmi; |
84 | ||
18e48776 | 85 | hdmi->ioaddr = (ulong)dev_read_addr(dev); |
cc232a9d JS |
86 | hdmi->mpll_cfg = rockchip_mpll_cfg; |
87 | hdmi->phy_cfg = rockchip_phy_config; | |
147fd3ac PT |
88 | |
89 | /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */ | |
90 | ||
cc232a9d | 91 | hdmi->reg_io_width = 4; |
c2539483 | 92 | |
c2539483 SG |
93 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
94 | ||
60a62acf NS |
95 | uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", |
96 | &hdmi->ddc_bus); | |
97 | ||
c2539483 SG |
98 | return 0; |
99 | } | |
100 | ||
147fd3ac PT |
101 | void rk_hdmi_probe_regulators(struct udevice *dev, |
102 | const char * const *names, int cnt) | |
103 | { | |
104 | rk_vop_probe_regulators(dev, names, cnt); | |
105 | } | |
106 | ||
107 | int rk_hdmi_probe(struct udevice *dev) | |
c2539483 | 108 | { |
c2539483 | 109 | struct rk_hdmi_priv *priv = dev_get_priv(dev); |
cc232a9d | 110 | struct dw_hdmi *hdmi = &priv->hdmi; |
c2539483 | 111 | int ret; |
c2539483 | 112 | |
41524d7f JT |
113 | dw_hdmi_init(hdmi); |
114 | dw_hdmi_phy_init(hdmi); | |
115 | ||
5eacb920 JT |
116 | ret = dw_hdmi_detect_hpd(hdmi); |
117 | if (ret < 0) | |
118 | return ret; | |
c2539483 | 119 | |
c2539483 SG |
120 | return 0; |
121 | } |