[thirdparty/u-boot.git] / drivers / video / rockchip / rk_vop.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 Google, Inc
 * Copyright 2014 Rockchip Inc.
 */

#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <edid.h>
#include <log.h>
#include <regmap.h>
#include <reset.h>
#include <syscon.h>
#include <video.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/edp_rk3288.h>
#include <asm/arch-rockchip/vop_rk3288.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <efi.h>
#include <efi_loader.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <power/regulator.h>
#include "rk_vop.h"

DECLARE_GLOBAL_DATA_PTR;

enum vop_pol {
	HSYNC_POSITIVE = 0,
	VSYNC_POSITIVE = 1,
	DEN_NEGATIVE   = 2,
	DCLK_INVERT    = 3
};

static void rkvop_enable(struct udevice *dev, ulong fbbase,
			 int fb_bits_per_pixel,
			 const struct display_timing *edid,
			 struct reset_ctl *dclk_rst)
{
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rk3288_vop *regs = priv->regs;
	struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
	u32 lb_mode;
	u32 rgb_mode;
	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;
	int ret;

	writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
	       &win_regs->win0_act_info);

	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
	       V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	       &win_regs->win0_dsp_st);

	writel(V_DSP_WIDTH(hactive - 1) |
		V_DSP_HEIGHT(vactive - 1),
		&win_regs->win0_dsp_info);

	clrsetbits_le32(&win_regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
			V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));

	switch (fb_bits_per_pixel) {
	case 16:
		rgb_mode = RGB565;
		writel(V_RGB565_VIRWIDTH(hactive), &win_regs->win0_vir);
		break;
	case 24:
		rgb_mode = RGB888;
		writel(V_RGB888_VIRWIDTH(hactive), &win_regs->win0_vir);
		break;
	case 32:
	default:
		rgb_mode = ARGB8888;
		writel(V_ARGB888_VIRWIDTH(hactive), &win_regs->win0_vir);
		break;
	}

	if (hactive > 2560)
		lb_mode = LB_RGB_3840X2;
	else if (hactive > 1920)
		lb_mode = LB_RGB_2560X4;
	else if (hactive > 1280)
		lb_mode = LB_RGB_1920X5;
	else
		lb_mode = LB_RGB_1280X8;

	clrsetbits_le32(&win_regs->win0_ctrl0,
			M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
			V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
			V_WIN0_EN(1));

	writel(fbbase, &win_regs->win0_yrgb_mst);
	writel(0x01, &regs->reg_cfg_done); /* enable reg config */

	ret = reset_assert(dclk_rst);
	if (ret) {
		dev_warn(dev, "failed to assert dclk reset (ret=%d)\n", ret);
		return;
	}
	udelay(20);

	ret = reset_deassert(dclk_rst);
	if (ret)
		dev_warn(dev, "failed to deassert dclk reset (ret=%d)\n", ret);

}

static void rkvop_set_pin_polarity(struct udevice *dev,
				   enum vop_modes mode, u32 polarity)
{
	struct rkvop_driverdata *ops =
		(struct rkvop_driverdata *)dev_get_driver_data(dev);

	if (ops->set_pin_polarity)
		ops->set_pin_polarity(dev, mode, polarity);
}

static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
{
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rk3288_vop *regs = priv->regs;

	/* remove from standby */
	clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));

	switch (mode) {
	case VOP_MODE_HDMI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_HDMI_OUT_EN(1));
		break;

	case VOP_MODE_EDP:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_EDP_OUT_EN(1));
		break;

#if defined(CONFIG_ROCKCHIP_RK3288)
	case VOP_MODE_LVDS:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_RGB_OUT_EN(1));
		break;
#endif

	case VOP_MODE_MIPI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_MIPI_OUT_EN(1));
		break;

	default:
		debug("%s: unsupported output mode %x\n", __func__, mode);
	}
}

static void rkvop_mode_set(struct udevice *dev,
			   const struct display_timing *edid,
			   enum vop_modes mode)
{
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rk3288_vop *regs = priv->regs;
	struct rk3288_vop *dsp_regs = priv->regs + priv->dsp_offset;
	struct rkvop_driverdata *data =
		(struct rkvop_driverdata *)dev_get_driver_data(dev);

	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;
	u32 hsync_len = edid->hsync_len.typ;
	u32 hback_porch = edid->hback_porch.typ;
	u32 vsync_len = edid->vsync_len.typ;
	u32 vback_porch = edid->vback_porch.typ;
	u32 hfront_porch = edid->hfront_porch.typ;
	u32 vfront_porch = edid->vfront_porch.typ;
	int mode_flags;
	u32 pin_polarity;

	pin_polarity = BIT(DCLK_INVERT);
	if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
		pin_polarity |= BIT(HSYNC_POSITIVE);
	if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
		pin_polarity |= BIT(VSYNC_POSITIVE);

	rkvop_set_pin_polarity(dev, mode, pin_polarity);
	rkvop_enable_output(dev, mode);

	mode_flags = 0;  /* RGB888 */
	if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
	    (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
		mode_flags = 15;  /* RGBaaa */

	clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
			V_DSP_OUT_MODE(mode_flags));

	writel(V_HSYNC(hsync_len) |
	       V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
			&dsp_regs->dsp_htotal_hs_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &dsp_regs->dsp_hact_st_end);

	writel(V_VSYNC(vsync_len) |
	       V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	       &dsp_regs->dsp_vtotal_vs_end);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &dsp_regs->dsp_vact_st_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &dsp_regs->post_dsp_hact_info);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &dsp_regs->post_dsp_vact_info);

	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

/**
 * rk_display_init() - Try to enable the given display device
 *
 * This function performs many steps:
 * - Finds the display device being referenced by @ep_node
 * - Puts the VOP's ID into its uclass platform data
 * - Probes the device to set it up
 * - Reads the EDID timing information
 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
 * - Enables the display (the display device handles this and will do different
 *     things depending on the display type)
 * - Tells the uclass about the display resolution so that the console will
 *     appear correctly
 *
 * @dev:	VOP device that we want to connect to the display
 * @fbbase:	Frame buffer address
 * @ep_node:	Device tree node to process - this is the offset of an endpoint
 *		node within the VOP's 'port' list.
 * Return: 0 if OK, -ve if something went wrong
 */
static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
{
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	int vop_id, remote_vop_id;
	struct display_timing timing;
	struct udevice *disp;
	int ret;
	u32 remote_phandle;
	struct display_plat *disp_uc_plat;
	struct clk clk;
	enum video_log2_bpp l2bpp;
	ofnode remote;
	const char *compat;
	struct reset_ctl dclk_rst;

	debug("%s(%s, 0x%lx, %s)\n", __func__,
	      dev_read_name(dev), fbbase, ofnode_get_name(ep_node));

	ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
	if (ret)
		return ret;

	remote = ofnode_get_by_phandle(remote_phandle);
	if (!ofnode_valid(remote))
		return -EINVAL;
	remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
	debug("remote vop_id=%d\n", remote_vop_id);

	/*
	 * The remote-endpoint references into a subnode of the encoder
	 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
	 * the following (assume 'hdmi_in_vopl' to be referenced):
	 *
	 * hdmi: hdmi@ff940000 {
	 *   ports {
	 *     hdmi_in: port {
	 *       hdmi_in_vopb: endpoint@0 { ... };
	 *       hdmi_in_vopl: endpoint@1 { ... };
	 *     }
	 *   }
	 * }
	 *
	 * The original code had 3 steps of "walking the parent", but
	 * a much better (as in: less likely to break if the DTS
	 * changes) way of doing this is to "find the enclosing device
	 * of UCLASS_DISPLAY".
	 */
	while (ofnode_valid(remote)) {
		remote = ofnode_get_parent(remote);
		if (!ofnode_valid(remote)) {
			debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
			      __func__, dev_read_name(dev));
			return -EINVAL;
		}

		uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
		if (disp)
			break;
	};
	compat = ofnode_get_property(remote, "compatible", NULL);
	if (!compat) {
		debug("%s(%s): Failed to find compatible property\n",
		      __func__, dev_read_name(dev));
		return -EINVAL;
	}
	if (strstr(compat, "edp") ||
	    strstr(compat, "rk3288-dp")) {
		vop_id = VOP_MODE_EDP;
	} else if (strstr(compat, "mipi")) {
		vop_id = VOP_MODE_MIPI;
	} else if (strstr(compat, "hdmi")) {
		vop_id = VOP_MODE_HDMI;
	} else if (strstr(compat, "cdn-dp")) {
		vop_id = VOP_MODE_DP;
	} else if (strstr(compat, "lvds")) {
		vop_id = VOP_MODE_LVDS;
	} else {
		debug("%s(%s): Failed to find vop mode for %s\n",
		      __func__, dev_read_name(dev), compat);
		return -EINVAL;
	}
	debug("vop_id=%d\n", vop_id);

	disp_uc_plat = dev_get_uclass_plat(disp);
	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
	if (display_in_use(disp)) {
		debug("   - device in use\n");
		return -EBUSY;
	}

	disp_uc_plat->source_id = remote_vop_id;
	disp_uc_plat->src_dev = dev;

	ret = device_probe(disp);
	if (ret) {
		debug("%s: device '%s' display won't probe (ret=%d)\n",
		      __func__, dev->name, ret);
		return ret;
	}

	ret = display_read_timing(disp, &timing);
	if (ret) {
		debug("%s: Failed to read timings\n", __func__);
		return ret;
	}

	ret = clk_get_by_index(dev, 1, &clk);
	if (!ret)
		ret = clk_set_rate(&clk, timing.pixelclock.typ);
	if (IS_ERR_VALUE(ret)) {
		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
		return ret;
	}

	/* Set bitwidth for vop display according to vop mode */
	switch (vop_id) {
	case VOP_MODE_EDP:
#if defined(CONFIG_ROCKCHIP_RK3288)
	case VOP_MODE_LVDS:
#endif
		l2bpp = VIDEO_BPP16;
		break;
	case VOP_MODE_HDMI:
	case VOP_MODE_MIPI:
		l2bpp = VIDEO_BPP32;
		break;
	default:
		l2bpp = VIDEO_BPP16;
	}

	rkvop_mode_set(dev, &timing, vop_id);

	ret = reset_get_by_name(dev, "dclk", &dclk_rst);
	if (ret) {
		dev_err(dev, "failed to get dclk reset (ret=%d)\n", ret);
		return ret;
	}

	rkvop_enable(dev, fbbase, 1 << l2bpp, &timing, &dclk_rst);

	ret = display_enable(disp, 1 << l2bpp, &timing);
	if (ret)
		return ret;

	uc_priv->xsize = timing.hactive.typ;
	uc_priv->ysize = timing.vactive.typ;
	uc_priv->bpix = l2bpp;
	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);

	return 0;
}

void rk_vop_probe_regulators(struct udevice *dev,
			     const char * const *names, int cnt)
{
	int i, ret;
	const char *name;
	struct udevice *reg;

	for (i = 0; i < cnt; ++i) {
		name = names[i];
		debug("%s: probing regulator '%s'\n", dev->name, name);

		ret = regulator_autoset_by_name(name, &reg);
		if (!ret)
			ret = regulator_set_enable(reg, true);
	}
}

int rk_vop_probe(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rkvop_driverdata *ops =
		(struct rkvop_driverdata *)dev_get_driver_data(dev);
	int ret = 0;
	ofnode port, node;
	struct reset_ctl ahb_rst;

	/* Before relocation we don't need to do anything */
	if (!(gd->flags & GD_FLG_RELOC))
		return 0;

	ret = reset_get_by_name(dev, "ahb", &ahb_rst);
	if (ret) {
		dev_err(dev, "failed to get ahb reset (ret=%d)\n", ret);
		return ret;
	}

	ret = reset_assert(&ahb_rst);
	if (ret) {
		dev_err(dev, "failed to assert ahb reset (ret=%d)\n", ret);
		return ret;
	}
	udelay(20);

	ret = reset_deassert(&ahb_rst);
	if (ret) {
		dev_err(dev, "failed to deassert ahb reset (ret=%d)\n", ret);
		return ret;
	}

#if defined(CONFIG_EFI_LOADER)
	debug("Adding to EFI map %d @ %lx\n", plat->size, plat->base);
	efi_add_memory_map(plat->base, plat->size, EFI_RESERVED_MEMORY_TYPE);
#endif

	priv->regs = dev_read_addr_ptr(dev);
	priv->win_offset = ops->win_offset;
	priv->dsp_offset = ops->dsp_offset;

	/*
	 * Try all the ports until we find one that works. In practice this
	 * tries EDP first if available, then HDMI.
	 *
	 * Note that rockchip_vop_set_clk() always uses NPLL as the source
	 * clock so it is currently not possible to use more than one display
	 * device simultaneously.
	 */
	port = dev_read_subnode(dev, "port");
	if (!ofnode_valid(port)) {
		debug("%s(%s): 'port' subnode not found\n",
		      __func__, dev_read_name(dev));
		return -EINVAL;
	}

	for (node = ofnode_first_subnode(port);
	     ofnode_valid(node);
	     node = dev_read_next_subnode(node)) {
		ret = rk_display_init(dev, plat->base, node);
		if (ret)
			debug("Device failed: ret=%d\n", ret);
		if (!ret)
			break;
	}
	video_set_flush_dcache(dev, 1);

	return ret;
}

int rk_vop_bind(struct udevice *dev)
{
	struct video_uc_plat *plat = dev_get_uclass_plat(dev);

	plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
			  CONFIG_VIDEO_ROCKCHIP_MAX_YRES);

	return 0;
}
Commit	Line	Data
a355ece8	1	// SPDX-License-Identifier: GPL-2.0
7b7ad5c3 SG	2	/*
	3	* Copyright (c) 2015 Google, Inc
	4	* Copyright 2014 Rockchip Inc.
7b7ad5c3 SG	5	*/
7b7ad5c3 SG	6
d678a59d	7	#include <common.h>
7b7ad5c3 SG	8	#include <clk.h>
	9	#include <display.h>
	10	#include <dm.h>
9749d2ea	11	#include <dm/device_compat.h>
7b7ad5c3	12	#include <edid.h>
f7ae49fc	13	#include <log.h>
7b7ad5c3	14	#include <regmap.h>
9749d2ea	15	#include <reset.h>
7b7ad5c3 SG	16	#include <syscon.h>
7b7ad5c3 SG	17	#include <video.h>
401d1c4f	18	#include <asm/global_data.h>
7b7ad5c3	19	#include <asm/gpio.h>
7b7ad5c3	20	#include <asm/io.h>
15f09a1a KY	21	#include <asm/arch-rockchip/clock.h>
	22	#include <asm/arch-rockchip/edp_rk3288.h>
	23	#include <asm/arch-rockchip/vop_rk3288.h>
7b7ad5c3 SG	24	#include <dm/device-internal.h>
7b7ad5c3 SG	25	#include <dm/uclass-internal.h>
decbc18e APR	26	#include <efi.h>
decbc18e APR	27	#include <efi_loader.h>
cd93d625	28	#include <linux/bitops.h>
61b29b82	29	#include <linux/err.h>
7b7ad5c3	30	#include <power/regulator.h>
d46d4047	31	#include "rk_vop.h"
7b7ad5c3 SG	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
d46d4047 PT	35	enum vop_pol {
	36	HSYNC_POSITIVE = 0,
	37	VSYNC_POSITIVE = 1,
	38	DEN_NEGATIVE = 2,
	39	DCLK_INVERT = 3
7b7ad5c3 SG	40	};
7b7ad5c3 SG	41
3c0f45c6	42	static void rkvop_enable(struct udevice *dev, ulong fbbase,
d46d4047	43	int fb_bits_per_pixel,
9749d2ea APR	44	const struct display_timing *edid,
9749d2ea APR	45	struct reset_ctl *dclk_rst)
7b7ad5c3	46	{
3c0f45c6 JT	47	struct rk_vop_priv *priv = dev_get_priv(dev);
3c0f45c6 JT	48	struct rk3288_vop *regs = priv->regs;
41b612ee	49	struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
7b7ad5c3 SG	50	u32 lb_mode;
	51	u32 rgb_mode;
	52	u32 hactive = edid->hactive.typ;
	53	u32 vactive = edid->vactive.typ;
9749d2ea	54	int ret;
7b7ad5c3 SG	55
7b7ad5c3 SG	56	writel(V_ACT_WIDTH(hactive - 1) \| V_ACT_HEIGHT(vactive - 1),
41b612ee	57	&win_regs->win0_act_info);
7b7ad5c3 SG	58
	59	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) \|
	60	V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
41b612ee	61	&win_regs->win0_dsp_st);
7b7ad5c3 SG	62
	63	writel(V_DSP_WIDTH(hactive - 1) \|
	64	V_DSP_HEIGHT(vactive - 1),
41b612ee	65	&win_regs->win0_dsp_info);
7b7ad5c3	66
41b612ee	67	clrsetbits_le32(&win_regs->win0_color_key, M_WIN0_KEY_EN \| M_WIN0_KEY_COLOR,
7b7ad5c3 SG	68	V_WIN0_KEY_EN(0) \| V_WIN0_KEY_COLOR(0));
	69
	70	switch (fb_bits_per_pixel) {
	71	case 16:
	72	rgb_mode = RGB565;
41b612ee	73	writel(V_RGB565_VIRWIDTH(hactive), &win_regs->win0_vir);
7b7ad5c3 SG	74	break;
	75	case 24:
	76	rgb_mode = RGB888;
41b612ee	77	writel(V_RGB888_VIRWIDTH(hactive), &win_regs->win0_vir);
7b7ad5c3 SG	78	break;
	79	case 32:
	80	default:
	81	rgb_mode = ARGB8888;
41b612ee	82	writel(V_ARGB888_VIRWIDTH(hactive), &win_regs->win0_vir);
7b7ad5c3 SG	83	break;
	84	}
	85
	86	if (hactive > 2560)
	87	lb_mode = LB_RGB_3840X2;
	88	else if (hactive > 1920)
	89	lb_mode = LB_RGB_2560X4;
	90	else if (hactive > 1280)
	91	lb_mode = LB_RGB_1920X5;
	92	else
	93	lb_mode = LB_RGB_1280X8;
	94
41b612ee	95	clrsetbits_le32(&win_regs->win0_ctrl0,
7b7ad5c3 SG	96	M_WIN0_LB_MODE \| M_WIN0_DATA_FMT \| M_WIN0_EN,
	97	V_WIN0_LB_MODE(lb_mode) \| V_WIN0_DATA_FMT(rgb_mode) \|
	98	V_WIN0_EN(1));
	99
41b612ee	100	writel(fbbase, &win_regs->win0_yrgb_mst);
7b7ad5c3	101	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
9749d2ea APR	102
	103	ret = reset_assert(dclk_rst);
	104	if (ret) {
	105	dev_warn(dev, "failed to assert dclk reset (ret=%d)\n", ret);
	106	return;
	107	}
	108	udelay(20);
	109
	110	ret = reset_deassert(dclk_rst);
	111	if (ret)
	112	dev_warn(dev, "failed to deassert dclk reset (ret=%d)\n", ret);
	113
7b7ad5c3 SG	114	}
7b7ad5c3 SG	115
d46d4047 PT	116	static void rkvop_set_pin_polarity(struct udevice *dev,
d46d4047 PT	117	enum vop_modes mode, u32 polarity)
7b7ad5c3	118	{
d46d4047 PT	119	struct rkvop_driverdata *ops =
	120	(struct rkvop_driverdata *)dev_get_driver_data(dev);
	121
	122	if (ops->set_pin_polarity)
	123	ops->set_pin_polarity(dev, mode, polarity);
	124	}
	125
	126	static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
	127	{
	128	struct rk_vop_priv *priv = dev_get_priv(dev);
	129	struct rk3288_vop *regs = priv->regs;
7b7ad5c3	130
6b5a09aa SG	131	/* remove from standby */
	132	clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));
	133
7b7ad5c3 SG	134	switch (mode) {
	135	case VOP_MODE_HDMI:
	136	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	137	V_HDMI_OUT_EN(1));
	138	break;
d46d4047	139
7b7ad5c3	140	case VOP_MODE_EDP:
7b7ad5c3 SG	141	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	142	V_EDP_OUT_EN(1));
	143	break;
d46d4047	144
e67243f1	145	#if defined(CONFIG_ROCKCHIP_RK3288)
85307835 JC	146	case VOP_MODE_LVDS:
	147	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	148	V_RGB_OUT_EN(1));
	149	break;
e67243f1	150	#endif
d46d4047	151
9f819931 EG	152	case VOP_MODE_MIPI:
	153	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	154	V_MIPI_OUT_EN(1));
d46d4047 PT	155	break;
	156
	157	default:
	158	debug("%s: unsupported output mode %x\n", __func__, mode);
7b7ad5c3	159	}
d46d4047	160	}
7b7ad5c3	161
d46d4047 PT	162	static void rkvop_mode_set(struct udevice *dev,
	163	const struct display_timing *edid,
	164	enum vop_modes mode)
	165	{
	166	struct rk_vop_priv *priv = dev_get_priv(dev);
	167	struct rk3288_vop *regs = priv->regs;
7cebb300	168	struct rk3288_vop *dsp_regs = priv->regs + priv->dsp_offset;
d46d4047 PT	169	struct rkvop_driverdata *data =
d46d4047 PT	170	(struct rkvop_driverdata *)dev_get_driver_data(dev);
85307835	171
d46d4047 PT	172	u32 hactive = edid->hactive.typ;
	173	u32 vactive = edid->vactive.typ;
	174	u32 hsync_len = edid->hsync_len.typ;
	175	u32 hback_porch = edid->hback_porch.typ;
	176	u32 vsync_len = edid->vsync_len.typ;
	177	u32 vback_porch = edid->vback_porch.typ;
	178	u32 hfront_porch = edid->hfront_porch.typ;
	179	u32 vfront_porch = edid->vfront_porch.typ;
	180	int mode_flags;
	181	u32 pin_polarity;
	182
	183	pin_polarity = BIT(DCLK_INVERT);
	184	if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
	185	pin_polarity \|= BIT(HSYNC_POSITIVE);
	186	if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
	187	pin_polarity \|= BIT(VSYNC_POSITIVE);
	188
	189	rkvop_set_pin_polarity(dev, mode, pin_polarity);
	190	rkvop_enable_output(dev, mode);
7b7ad5c3	191
d46d4047 PT	192	mode_flags = 0; /* RGB888 */
	193	if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
	194	(mode == VOP_MODE_HDMI \|\| mode == VOP_MODE_EDP))
	195	mode_flags = 15; /* RGBaaa */
	196
	197	clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
	198	V_DSP_OUT_MODE(mode_flags));
7b7ad5c3 SG	199
	200	writel(V_HSYNC(hsync_len) \|
	201	V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
7cebb300	202	&dsp_regs->dsp_htotal_hs_end);
7b7ad5c3 SG	203
	204	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	205	V_HASP(hsync_len + hback_porch),
7cebb300	206	&dsp_regs->dsp_hact_st_end);
7b7ad5c3 SG	207
	208	writel(V_VSYNC(vsync_len) \|
	209	V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
7cebb300	210	&dsp_regs->dsp_vtotal_vs_end);
7b7ad5c3 SG	211
	212	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	213	V_VASP(vsync_len + vback_porch),
7cebb300	214	&dsp_regs->dsp_vact_st_end);
7b7ad5c3 SG	215
	216	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	217	V_HASP(hsync_len + hback_porch),
7cebb300	218	&dsp_regs->post_dsp_hact_info);
7b7ad5c3 SG	219
	220	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	221	V_VASP(vsync_len + vback_porch),
7cebb300	222	&dsp_regs->post_dsp_vact_info);
7b7ad5c3 SG	223
	224	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
	225	}
	226
	227	/**
	228	* rk_display_init() - Try to enable the given display device
	229	*
	230	* This function performs many steps:
	231	* - Finds the display device being referenced by @ep_node
	232	* - Puts the VOP's ID into its uclass platform data
	233	* - Probes the device to set it up
	234	* - Reads the EDID timing information
	235	* - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
	236	* - Enables the display (the display device handles this and will do different
	237	* things depending on the display type)
	238	* - Tells the uclass about the display resolution so that the console will
	239	* appear correctly
	240	*
	241	* @dev: VOP device that we want to connect to the display
	242	* @fbbase: Frame buffer address
7b7ad5c3 SG	243	* @ep_node: Device tree node to process - this is the offset of an endpoint
7b7ad5c3 SG	244	* node within the VOP's 'port' list.
185f812c	245	* Return: 0 if OK, -ve if something went wrong
7b7ad5c3	246	*/
5de0b5a3	247	static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
7b7ad5c3 SG	248	{
7b7ad5c3 SG	249	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
7b7ad5c3	250	int vop_id, remote_vop_id;
7b7ad5c3 SG	251	struct display_timing timing;
7b7ad5c3 SG	252	struct udevice *disp;
5de0b5a3 PT	253	int ret;
5de0b5a3 PT	254	u32 remote_phandle;
7b7ad5c3	255	struct display_plat *disp_uc_plat;
135aa950	256	struct clk clk;
8aed0d77	257	enum video_log2_bpp l2bpp;
5de0b5a3	258	ofnode remote;
7fe2ebf3	259	const char *compat;
9749d2ea	260	struct reset_ctl dclk_rst;
7b7ad5c3	261
3fd64112	262	debug("%s(%s, 0x%lx, %s)\n", __func__,
5de0b5a3 PT	263	dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
5de0b5a3 PT	264
5de0b5a3 PT	265	ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
	266	if (ret)
	267	return ret;
7b7ad5c3	268
5de0b5a3 PT	269	remote = ofnode_get_by_phandle(remote_phandle);
5de0b5a3 PT	270	if (!ofnode_valid(remote))
7b7ad5c3	271	return -EINVAL;
5de0b5a3 PT	272	remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
5de0b5a3 PT	273	debug("remote vop_id=%d\n", remote_vop_id);
7b7ad5c3	274
5de0b5a3 PT	275	/*
	276	* The remote-endpoint references into a subnode of the encoder
	277	* (i.e. HDMI, MIPI, etc.) with the DTS looking something like
	278	* the following (assume 'hdmi_in_vopl' to be referenced):
	279	*
	280	* hdmi: hdmi@ff940000 {
	281	* ports {
	282	* hdmi_in: port {
	283	* hdmi_in_vopb: endpoint@0 { ... };
	284	* hdmi_in_vopl: endpoint@1 { ... };
	285	* }
	286	* }
	287	* }
	288	*
	289	* The original code had 3 steps of "walking the parent", but
	290	* a much better (as in: less likely to break if the DTS
	291	* changes) way of doing this is to "find the enclosing device
	292	* of UCLASS_DISPLAY".
	293	*/
	294	while (ofnode_valid(remote)) {
	295	remote = ofnode_get_parent(remote);
	296	if (!ofnode_valid(remote)) {
	297	debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
	298	__func__, dev_read_name(dev));
	299	return -EINVAL;
	300	}
	301
	302	uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
	303	if (disp)
	304	break;
	305	};
7fe2ebf3 APR	306	compat = ofnode_get_property(remote, "compatible", NULL);
	307	if (!compat) {
	308	debug("%s(%s): Failed to find compatible property\n",
	309	__func__, dev_read_name(dev));
	310	return -EINVAL;
	311	}
e2b57ffb JJ	312	if (strstr(compat, "edp") \|\|
e2b57ffb JJ	313	strstr(compat, "rk3288-dp")) {
7fe2ebf3 APR	314	vop_id = VOP_MODE_EDP;
	315	} else if (strstr(compat, "mipi")) {
	316	vop_id = VOP_MODE_MIPI;
	317	} else if (strstr(compat, "hdmi")) {
	318	vop_id = VOP_MODE_HDMI;
	319	} else if (strstr(compat, "cdn-dp")) {
	320	vop_id = VOP_MODE_DP;
	321	} else if (strstr(compat, "lvds")) {
	322	vop_id = VOP_MODE_LVDS;
	323	} else {
	324	debug("%s(%s): Failed to find vop mode for %s\n",
	325	__func__, dev_read_name(dev), compat);
	326	return -EINVAL;
	327	}
	328	debug("vop_id=%d\n", vop_id);
7b7ad5c3	329
caa4daa2	330	disp_uc_plat = dev_get_uclass_plat(disp);
7b7ad5c3	331	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
987a404a SG	332	if (display_in_use(disp)) {
	333	debug(" - device in use\n");
	334	return -EBUSY;
	335	}
	336
7b7ad5c3 SG	337	disp_uc_plat->source_id = remote_vop_id;
	338	disp_uc_plat->src_dev = dev;
	339
	340	ret = device_probe(disp);
	341	if (ret) {
	342	debug("%s: device '%s' display won't probe (ret=%d)\n",
	343	__func__, dev->name, ret);
	344	return ret;
	345	}
	346
	347	ret = display_read_timing(disp, &timing);
	348	if (ret) {
	349	debug("%s: Failed to read timings\n", __func__);
	350	return ret;
	351	}
	352
9ed68260	353	ret = clk_get_by_index(dev, 1, &clk);
135aa950 SW	354	if (!ret)
135aa950 SW	355	ret = clk_set_rate(&clk, timing.pixelclock.typ);
e07e5bde	356	if (IS_ERR_VALUE(ret)) {
7b7ad5c3 SG	357	debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
	358	return ret;
	359	}
	360
8aed0d77 EG	361	/* Set bitwidth for vop display according to vop mode */
	362	switch (vop_id) {
	363	case VOP_MODE_EDP:
e67243f1	364	#if defined(CONFIG_ROCKCHIP_RK3288)
8aed0d77	365	case VOP_MODE_LVDS:
e67243f1	366	#endif
8aed0d77 EG	367	l2bpp = VIDEO_BPP16;
8aed0d77 EG	368	break;
d46d4047	369	case VOP_MODE_HDMI:
8aed0d77 EG	370	case VOP_MODE_MIPI:
	371	l2bpp = VIDEO_BPP32;
	372	break;
	373	default:
	374	l2bpp = VIDEO_BPP16;
	375	}
7b7ad5c3	376
d46d4047	377	rkvop_mode_set(dev, &timing, vop_id);
9749d2ea APR	378
	379	ret = reset_get_by_name(dev, "dclk", &dclk_rst);
	380	if (ret) {
	381	dev_err(dev, "failed to get dclk reset (ret=%d)\n", ret);
	382	return ret;
	383	}
	384
3c0f45c6	385	rkvop_enable(dev, fbbase, 1 << l2bpp, &timing, &dclk_rst);
7b7ad5c3 SG	386
	387	ret = display_enable(disp, 1 << l2bpp, &timing);
	388	if (ret)
	389	return ret;
	390
	391	uc_priv->xsize = timing.hactive.typ;
	392	uc_priv->ysize = timing.vactive.typ;
	393	uc_priv->bpix = l2bpp;
	394	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
	395
	396	return 0;
	397	}
	398
d46d4047 PT	399	void rk_vop_probe_regulators(struct udevice *dev,
	400	const char * const *names, int cnt)
	401	{
	402	int i, ret;
	403	const char *name;
	404	struct udevice *reg;
	405
	406	for (i = 0; i < cnt; ++i) {
	407	name = names[i];
	408	debug("%s: probing regulator '%s'\n", dev->name, name);
	409
	410	ret = regulator_autoset_by_name(name, &reg);
	411	if (!ret)
	412	ret = regulator_set_enable(reg, true);
	413	}
	414	}
	415
	416	int rk_vop_probe(struct udevice *dev)
7b7ad5c3	417	{
8a8d24bd	418	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
7b7ad5c3	419	struct rk_vop_priv *priv = dev_get_priv(dev);
41b612ee JT	420	struct rkvop_driverdata *ops =
41b612ee JT	421	(struct rkvop_driverdata *)dev_get_driver_data(dev);
d46d4047	422	int ret = 0;
5de0b5a3	423	ofnode port, node;
9749d2ea	424	struct reset_ctl ahb_rst;
7b7ad5c3 SG	425
	426	/* Before relocation we don't need to do anything */
	427	if (!(gd->flags & GD_FLG_RELOC))
	428	return 0;
	429
9749d2ea APR	430	ret = reset_get_by_name(dev, "ahb", &ahb_rst);
	431	if (ret) {
	432	dev_err(dev, "failed to get ahb reset (ret=%d)\n", ret);
	433	return ret;
	434	}
	435
	436	ret = reset_assert(&ahb_rst);
	437	if (ret) {
	438	dev_err(dev, "failed to assert ahb reset (ret=%d)\n", ret);
f4c7efe0	439	return ret;
9749d2ea APR	440	}
	441	udelay(20);
	442
	443	ret = reset_deassert(&ahb_rst);
	444	if (ret) {
	445	dev_err(dev, "failed to deassert ahb reset (ret=%d)\n", ret);
	446	return ret;
	447	}
	448
decbc18e APR	449	#if defined(CONFIG_EFI_LOADER)
	450	debug("Adding to EFI map %d @ %lx\n", plat->size, plat->base);
	451	efi_add_memory_map(plat->base, plat->size, EFI_RESERVED_MEMORY_TYPE);
	452	#endif
	453
a12a73b6	454	priv->regs = dev_read_addr_ptr(dev);
41b612ee	455	priv->win_offset = ops->win_offset;
7cebb300	456	priv->dsp_offset = ops->dsp_offset;
7b7ad5c3	457
7b7ad5c3 SG	458	/*
	459	* Try all the ports until we find one that works. In practice this
	460	* tries EDP first if available, then HDMI.
987a404a SG	461	*
	462	* Note that rockchip_vop_set_clk() always uses NPLL as the source
	463	* clock so it is currently not possible to use more than one display
	464	* device simultaneously.
7b7ad5c3	465	*/
5de0b5a3 PT	466	port = dev_read_subnode(dev, "port");
	467	if (!ofnode_valid(port)) {
	468	debug("%s(%s): 'port' subnode not found\n",
	469	__func__, dev_read_name(dev));
7b7ad5c3	470	return -EINVAL;
5de0b5a3 PT	471	}
	472
	473	for (node = ofnode_first_subnode(port);
	474	ofnode_valid(node);
	475	node = dev_read_next_subnode(node)) {
8aed0d77	476	ret = rk_display_init(dev, plat->base, node);
7b7ad5c3 SG	477	if (ret)
	478	debug("Device failed: ret=%d\n", ret);
	479	if (!ret)
	480	break;
	481	}
b55e04a0	482	video_set_flush_dcache(dev, 1);
7b7ad5c3 SG	483
	484	return ret;
	485	}
	486
d46d4047	487	int rk_vop_bind(struct udevice *dev)
7b7ad5c3	488	{
8a8d24bd	489	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
7b7ad5c3	490
89b2b618 PT	491	plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
89b2b618 PT	492	CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
7b7ad5c3 SG	493
	494	return 0;
	495	}