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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / video / stm32 / stm32_ltdc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
72719d2f 2/*
c4c33e9d 3 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
4 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
5 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
72719d2f
PC		 6 */
7
8d2257e5
PD		 8#define LOG_CATEGORY UCLASS_VIDEO
9
d678a59d 10#include <common.h>
72719d2f 11#include <clk.h>
aeaf3306 12#include <display.h>
72719d2f 13#include <dm.h>
f7ae49fc 14#include <log.h>
72719d2f 15#include <panel.h>
c0fb2fc0 16#include <reset.h>
72719d2f 17#include <video.h>
aeaf3306 18#include <video_bridge.h>
72719d2f 19#include <asm/io.h>
72719d2f 20#include <dm/device-internal.h>
336d4615 21#include <dm/device_compat.h>
cd93d625 22#include <linux/bitops.h>
1e94b46f 23#include <linux/printk.h>
72719d2f 24
72719d2f
PC		 25struct stm32_ltdc_priv {
26 void __iomem *regs;
72719d2f
PC		 27 enum video_log2_bpp l2bpp;
28 u32 bg_col_argb;
13dc7562
YF		 29 const u32 *layer_regs;
30 const u32 *pix_fmt_hw;
72719d2f
PC		 31 u32 crop_x, crop_y, crop_w, crop_h;
32 u32 alpha;
13dc7562
YF		 33 u32 hw_version;
34};
35
36/* Layer register offsets */
37static const u32 layer_regs_a0[] = {
38 0x80, /* L1 configuration 0 */
39 0x00, /* not available */
40 0x00, /* not available */
41 0x84, /* L1 control register */
42 0x88, /* L1 window horizontal position configuration */
43 0x8c, /* L1 window vertical position configuration */
44 0x90, /* L1 color keying configuration */
45 0x94, /* L1 pixel format configuration */
46 0x98, /* L1 constant alpha configuration */
47 0x9c, /* L1 default color configuration */
48 0xa0, /* L1 blending factors configuration */
49 0x00, /* not available */
50 0x00, /* not available */
51 0xac, /* L1 color frame buffer address */
52 0xb0, /* L1 color frame buffer length */
53 0xb4, /* L1 color frame buffer line number */
54 0x00, /* not available */
55 0x00, /* not available */
56 0x00, /* not available */
57 0x00, /* not available */
58 0xc4, /* L1 CLUT write */
59 0x00, /* not available */
60 0x00, /* not available */
61 0x00, /* not available */
62 0x00, /* not available */
63 0x00, /* not available */
64 0x00, /* not available */
65 0x00, /* not available */
66 0x00, /* not available */
67 0x00, /* not available */
68 0x00 /* not available */
69};
70
71static const u32 layer_regs_a1[] = {
72 0x80, /* L1 configuration 0 */
73 0x84, /* L1 configuration 1 */
74 0x00, /* L1 reload control */
75 0x88, /* L1 control register */
76 0x8c, /* L1 window horizontal position configuration */
77 0x90, /* L1 window vertical position configuration */
78 0x94, /* L1 color keying configuration */
79 0x98, /* L1 pixel format configuration */
80 0x9c, /* L1 constant alpha configuration */
81 0xa0, /* L1 default color configuration */
82 0xa4, /* L1 blending factors configuration */
83 0xa8, /* L1 burst length configuration */
84 0x00, /* not available */
85 0xac, /* L1 color frame buffer address */
86 0xb0, /* L1 color frame buffer length */
87 0xb4, /* L1 color frame buffer line number */
88 0xb8, /* L1 auxiliary frame buffer address 0 */
89 0xbc, /* L1 auxiliary frame buffer address 1 */
90 0xc0, /* L1 auxiliary frame buffer length */
91 0xc4, /* L1 auxiliary frame buffer line number */
92 0xc8, /* L1 CLUT write */
93 0x00, /* not available */
94 0x00, /* not available */
95 0x00, /* not available */
96 0x00, /* not available */
97 0x00, /* not available */
98 0x00, /* not available */
99 0x00, /* not available */
100 0x00, /* not available */
101 0x00, /* not available */
102 0x00 /* not available */
103};
104
105static const u32 layer_regs_a2[] = {
106 0x100, /* L1 configuration 0 */
107 0x104, /* L1 configuration 1 */
108 0x108, /* L1 reload control */
109 0x10c, /* L1 control register */
110 0x110, /* L1 window horizontal position configuration */
111 0x114, /* L1 window vertical position configuration */
112 0x118, /* L1 color keying configuration */
113 0x11c, /* L1 pixel format configuration */
114 0x120, /* L1 constant alpha configuration */
115 0x124, /* L1 default color configuration */
116 0x128, /* L1 blending factors configuration */
117 0x12c, /* L1 burst length configuration */
118 0x130, /* L1 planar configuration */
119 0x134, /* L1 color frame buffer address */
120 0x138, /* L1 color frame buffer length */
121 0x13c, /* L1 color frame buffer line number */
122 0x140, /* L1 auxiliary frame buffer address 0 */
123 0x144, /* L1 auxiliary frame buffer address 1 */
124 0x148, /* L1 auxiliary frame buffer length */
125 0x14c, /* L1 auxiliary frame buffer line number */
126 0x150, /* L1 CLUT write */
127 0x154, /* not available */
128 0x158, /* not available */
129 0x15c, /* not available */
130 0x160, /* not available */
131 0x164, /* not available */
132 0x168, /* not available */
133 0x16c, /* L1 Conversion YCbCr RGB 0 */
134 0x170, /* L1 Conversion YCbCr RGB 1 */
135 0x174, /* L1 Flexible Pixel Format 0 */
136 0x178 /* L1 Flexible Pixel Format 1 */
72719d2f
PC		 137};
138
139/* LTDC main registers */
140#define LTDC_IDR 0x00 /* IDentification */
141#define LTDC_LCR 0x04 /* Layer Count */
142#define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
143#define LTDC_BPCR 0x0C /* Back Porch Configuration */
144#define LTDC_AWCR 0x10 /* Active Width Configuration */
145#define LTDC_TWCR 0x14 /* Total Width Configuration */
146#define LTDC_GCR 0x18 /* Global Control */
147#define LTDC_GC1R 0x1C /* Global Configuration 1 */
148#define LTDC_GC2R 0x20 /* Global Configuration 2 */
149#define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
150#define LTDC_GACR 0x28 /* GAmma Correction */
151#define LTDC_BCCR 0x2C /* Background Color Configuration */
152#define LTDC_IER 0x34 /* Interrupt Enable */
153#define LTDC_ISR 0x38 /* Interrupt Status */
154#define LTDC_ICR 0x3C /* Interrupt Clear */
155#define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
156#define LTDC_CPSR 0x44 /* Current Position Status */
157#define LTDC_CDSR 0x48 /* Current Display Status */
158
13dc7562
YF		 159/* Layer register offsets */
160#define LTDC_L1C0R (priv->layer_regs[0]) /* L1 configuration 0 */
161#define LTDC_L1C1R (priv->layer_regs[1]) /* L1 configuration 1 */
162#define LTDC_L1RCR (priv->layer_regs[2]) /* L1 reload control */
163#define LTDC_L1CR (priv->layer_regs[3]) /* L1 control register */
164#define LTDC_L1WHPCR (priv->layer_regs[4]) /* L1 window horizontal position configuration */
165#define LTDC_L1WVPCR (priv->layer_regs[5]) /* L1 window vertical position configuration */
166#define LTDC_L1CKCR (priv->layer_regs[6]) /* L1 color keying configuration */
167#define LTDC_L1PFCR (priv->layer_regs[7]) /* L1 pixel format configuration */
168#define LTDC_L1CACR (priv->layer_regs[8]) /* L1 constant alpha configuration */
169#define LTDC_L1DCCR (priv->layer_regs[9]) /* L1 default color configuration */
170#define LTDC_L1BFCR (priv->layer_regs[10]) /* L1 blending factors configuration */
171#define LTDC_L1BLCR (priv->layer_regs[11]) /* L1 burst length configuration */
172#define LTDC_L1PCR (priv->layer_regs[12]) /* L1 planar configuration */
173#define LTDC_L1CFBAR (priv->layer_regs[13]) /* L1 color frame buffer address */
174#define LTDC_L1CFBLR (priv->layer_regs[14]) /* L1 color frame buffer length */
175#define LTDC_L1CFBLNR (priv->layer_regs[15]) /* L1 color frame buffer line number */
176#define LTDC_L1AFBA0R (priv->layer_regs[16]) /* L1 auxiliary frame buffer address 0 */
177#define LTDC_L1AFBA1R (priv->layer_regs[17]) /* L1 auxiliary frame buffer address 1 */
178#define LTDC_L1AFBLR (priv->layer_regs[18]) /* L1 auxiliary frame buffer length */
179#define LTDC_L1AFBLNR (priv->layer_regs[19]) /* L1 auxiliary frame buffer line number */
180#define LTDC_L1CLUTWR (priv->layer_regs[20]) /* L1 CLUT write */
181#define LTDC_L1CYR0R (priv->layer_regs[27]) /* L1 Conversion YCbCr RGB 0 */
182#define LTDC_L1CYR1R (priv->layer_regs[28]) /* L1 Conversion YCbCr RGB 1 */
183#define LTDC_L1FPF0R (priv->layer_regs[29]) /* L1 Flexible Pixel Format 0 */
184#define LTDC_L1FPF1R (priv->layer_regs[30]) /* L1 Flexible Pixel Format 1 */
72719d2f
PC		 185
186/* Bit definitions */
187#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
188#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
189
190#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
191#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
192
193#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
194#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
195
196#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
197#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
198
199#define GCR_LTDCEN BIT(0) /* LTDC ENable */
200#define GCR_DEN BIT(16) /* Dither ENable */
201#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
202#define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
203#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
204#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
205
206#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
207#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
208#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
209#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
210#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
211#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
212#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
213#define GC1R_BCP BIT(22) /* Background Colour Programmable */
214#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
215#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
216#define GC1R_TP BIT(25) /* Timing Programmable */
217#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
218#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
219#define GC1R_DWP BIT(28) /* Dither Width Programmable */
220#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
221#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
222
223#define GC2R_EDCA BIT(0) /* External Display Control Ability */
224#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
225#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
226#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
227#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
228#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
229
230#define SRCR_IMR BIT(0) /* IMmediate Reload */
231#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
232
233#define LXCR_LEN BIT(0) /* Layer ENable */
234#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
235#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
236
237#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
238#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
239
240#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
241#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
242
243#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
244
245#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
246
247#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
248#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
249
250#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
251#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
252
253#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
254
255#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
e6194ce6 256#define BF1_CA 0x400 /* Constant Alpha */
72719d2f 257#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
e6194ce6 258#define BF2_1CA 0x005 /* 1 - Constant Alpha */
72719d2f 259
13dc7562
YF		 260#define NB_PF 8 /* Max nb of HW pixel format */
261
262#define HWVER_10200 0x010200
263#define HWVER_10300 0x010300
264#define HWVER_20101 0x020101
265#define HWVER_40100 0x040100
266
72719d2f 267enum stm32_ltdc_pix_fmt {
13dc7562
YF		 268 PF_ARGB8888 = 0, /* ARGB [32 bits] */
269 PF_ABGR8888, /* ABGR [32 bits] */
270 PF_BGRA8888, /* BGRA [32 bits] */
271 PF_RGBA8888, /* RGBA [32 bits] */
272 PF_RGB888, /* RGB [24 bits] */
273 PF_BGR565, /* RGB [16 bits] */
274 PF_RGB565, /* RGB [16 bits] */
275 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
276 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
277 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
278 PF_AL88, /* Alpha:8 bits + indexed 8 bits [16 bits] */
279 PF_L8, /* Indexed 8 bits [8 bits] */
280 PF_NONE
281};
282
283static const enum stm32_ltdc_pix_fmt pix_fmt_a0[NB_PF] = {
284 PF_ARGB8888, /* 0x00 */
285 PF_RGB888, /* 0x01 */
286 PF_RGB565, /* 0x02 */
287 PF_ARGB1555, /* 0x03 */
288 PF_ARGB4444, /* 0x04 */
289 PF_L8, /* 0x05 */
290 PF_AL44, /* 0x06 */
291 PF_AL88 /* 0x07 */
292};
293
294static const enum stm32_ltdc_pix_fmt pix_fmt_a1[NB_PF] = {
295 PF_ARGB8888, /* 0x00 */
296 PF_RGB888, /* 0x01 */
297 PF_RGB565, /* 0x02 */
298 PF_RGBA8888, /* 0x03 */
299 PF_AL44, /* 0x04 */
300 PF_L8, /* 0x05 */
301 PF_ARGB1555, /* 0x06 */
302 PF_ARGB4444 /* 0x07 */
303};
304
305static const enum stm32_ltdc_pix_fmt pix_fmt_a2[NB_PF] = {
306 PF_ARGB8888, /* 0x00 */
307 PF_ABGR8888, /* 0x01 */
308 PF_RGBA8888, /* 0x02 */
309 PF_BGRA8888, /* 0x03 */
310 PF_RGB565, /* 0x04 */
311 PF_BGR565, /* 0x05 */
312 PF_RGB888, /* 0x06 */
313 PF_NONE /* 0x07 (flexible pixel format) */
72719d2f
PC		 314};
315
316/* TODO add more color format support */
317static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
318{
319 enum stm32_ltdc_pix_fmt pf;
320
321 switch (l2bpp) {
322 case VIDEO_BPP16:
323 pf = PF_RGB565;
324 break;
325
e6194ce6 326 case VIDEO_BPP32:
327 pf = PF_ARGB8888;
328 break;
329
330 case VIDEO_BPP8:
331 pf = PF_L8;
332 break;
333
72719d2f
PC		 334 case VIDEO_BPP1:
335 case VIDEO_BPP2:
336 case VIDEO_BPP4:
72719d2f 337 default:
8d2257e5
PD		 338 log_warning("warning %dbpp not supported yet, %dbpp instead\n",
339 VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
72719d2f
PC		 340 pf = PF_RGB565;
341 break;
342 }
343
8d2257e5 344 log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
72719d2f
PC		 345
346 return (u32)pf;
347}
348
e6194ce6 349static bool has_alpha(u32 fmt)
350{
351 switch (fmt) {
352 case PF_ARGB8888:
353 case PF_ARGB1555:
354 case PF_ARGB4444:
355 case PF_AL44:
356 case PF_AL88:
357 return true;
358 case PF_RGB888:
359 case PF_RGB565:
360 case PF_L8:
361 default:
362 return false;
363 }
364}
365
72719d2f
PC		 366static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
367{
368 /* Reload configuration immediately & enable LTDC */
369 setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
370 setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
371}
372
aeaf3306
YF		 373static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
374 struct display_timing *timings)
72719d2f
PC		 375{
376 void __iomem *regs = priv->regs;
72719d2f
PC		 377 u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
378 u32 total_w, total_h;
379 u32 val;
380
381 /* Convert video timings to ltdc timings */
aeaf3306
YF		 382 hsync = timings->hsync_len.typ - 1;
383 vsync = timings->vsync_len.typ - 1;
384 acc_hbp = hsync + timings->hback_porch.typ;
385 acc_vbp = vsync + timings->vback_porch.typ;
386 acc_act_w = acc_hbp + timings->hactive.typ;
387 acc_act_h = acc_vbp + timings->vactive.typ;
388 total_w = acc_act_w + timings->hfront_porch.typ;
389 total_h = acc_act_h + timings->vfront_porch.typ;
72719d2f
PC		 390
391 /* Synchronization sizes */
392 val = (hsync << 16) | vsync;
393 clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
394
395 /* Accumulated back porch */
396 val = (acc_hbp << 16) | acc_vbp;
397 clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
398
399 /* Accumulated active width */
400 val = (acc_act_w << 16) | acc_act_h;
401 clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
402
403 /* Total width & height */
404 val = (total_w << 16) | total_h;
405 clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
406
75fa711a 407 setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
408
72719d2f
PC		 409 /* Signal polarities */
410 val = 0;
8d2257e5 411 log_debug("timing->flags 0x%08x\n", timings->flags);
aeaf3306 412 if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
72719d2f 413 val |= GCR_HSPOL;
aeaf3306 414 if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
72719d2f 415 val |= GCR_VSPOL;
ef4ce6df 416 if (timings->flags & DISPLAY_FLAGS_DE_LOW)
72719d2f 417 val |= GCR_DEPOL;
aeaf3306 418 if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
72719d2f
PC		 419 val |= GCR_PCPOL;
420 clrsetbits_le32(regs + LTDC_GCR,
421 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
422
423 /* Overall background color */
424 writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
425}
426
427static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
428{
429 void __iomem *regs = priv->regs;
430 u32 x0, x1, y0, y1;
431 u32 pitch_in_bytes;
432 u32 line_length;
433 u32 bus_width;
434 u32 val, tmp, bpp;
e6194ce6 435 u32 format;
72719d2f
PC		 436
437 x0 = priv->crop_x;
438 x1 = priv->crop_x + priv->crop_w - 1;
439 y0 = priv->crop_y;
440 y1 = priv->crop_y + priv->crop_h - 1;
441
442 /* Horizontal start and stop position */
443 tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
444 val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
445 clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
446 val);
447
448 /* Vertical start & stop position */
449 tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
450 val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
451 clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
452 val);
453
454 /* Layer background color */
455 writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
456
457 /* Color frame buffer pitch in bytes & line length */
458 bpp = VNBITS(priv->l2bpp);
459 pitch_in_bytes = priv->crop_w * (bpp >> 3);
460 bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
461 line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
462 val = (pitch_in_bytes << 16) | line_length;
463 clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
464
465 /* Pixel format */
e6194ce6 466 format = stm32_ltdc_get_pixel_format(priv->l2bpp);
13dc7562
YF		 467 for (val = 0; val < NB_PF; val++)
468 if (priv->pix_fmt_hw[val] == format)
469 break;
470
471 if (val >= NB_PF) {
472 log_err("invalid pixel format\n");
473 return;
474 }
475
476 clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
72719d2f
PC		 477
478 /* Constant alpha value */
479 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
480
e6194ce6 481 /* Specifies the blending factors : with or without pixel alpha */
482 /* Manage hw-specific capabilities */
483 val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
484
72719d2f 485 /* Blending factors */
e6194ce6 486 clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
72719d2f
PC		 487
488 /* Frame buffer line number */
489 clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
490
491 /* Frame buffer address */
492 writel(fb_addr, regs + LTDC_L1CFBAR);
493
494 /* Enable layer 1 */
495 setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
496}
497
47256b04
DB		 498#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY)
499static int stm32_ltdc_alloc_fb(struct udevice *dev)
500{
501 u32 sdram_size = gd->ram_size;
502 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
503 phys_addr_t cpu;
504 dma_addr_t bus;
505 u64 dma_size;
506 int ret;
507
508 ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size);
509 if (ret) {
510 dev_err(dev, "failed to get dma address\n");
511 return ret;
512 }
513
514 uc_plat->base = bus + sdram_size - ALIGN(uc_plat->size, uc_plat->align);
515 return 0;
516}
517#else
518static inline int stm32_ltdc_alloc_fb(struct udevice *dev)
519{
520 /* Delegate framebuffer allocation to video-uclass */
521 return 0;
522}
523#endif
524
72719d2f
PC		 525static int stm32_ltdc_probe(struct udevice *dev)
526{
8a8d24bd 527 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
72719d2f
PC		 528 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
529 struct stm32_ltdc_priv *priv = dev_get_priv(dev);
aeaf3306
YF		 530 struct udevice *bridge = NULL;
531 struct udevice *panel = NULL;
532 struct display_timing timings;
2a0e8784 533 struct clk pclk;
c0fb2fc0 534 struct reset_ctl rst;
310ef930 535 ulong rate;
aeaf3306 536 int ret;
72719d2f 537
a12a73b6
JJ		 538 priv->regs = dev_read_addr_ptr(dev);
539 if (!priv->regs) {
aeaf3306 540 dev_err(dev, "ltdc dt register address error\n");
72719d2f
PC		 541 return -EINVAL;
542 }
543
2a0e8784 544 ret = clk_get_by_index(dev, 0, &pclk);
72719d2f 545 if (ret) {
aeaf3306 546 dev_err(dev, "peripheral clock get error %d\n", ret);
2a0e8784 547 return ret;
548 }
549
550 ret = clk_enable(&pclk);
551 if (ret) {
aeaf3306 552 dev_err(dev, "peripheral clock enable error %d\n", ret);
72719d2f
PC		 553 return ret;
554 }
555
13dc7562
YF		 556 priv->hw_version = readl(priv->regs + LTDC_IDR);
557 debug("%s: LTDC hardware 0x%x\n", __func__, priv->hw_version);
558
559 switch (priv->hw_version) {
560 case HWVER_10200:
561 case HWVER_10300:
562 priv->layer_regs = layer_regs_a0;
563 priv->pix_fmt_hw = pix_fmt_a0;
564 break;
565 case HWVER_20101:
566 priv->layer_regs = layer_regs_a1;
567 priv->pix_fmt_hw = pix_fmt_a1;
568 break;
569 case HWVER_40100:
570 priv->layer_regs = layer_regs_a2;
571 priv->pix_fmt_hw = pix_fmt_a2;
572 break;
573 default:
574 return -ENODEV;
575 }
576
aeaf3306 577 ret = uclass_first_device_err(UCLASS_PANEL, &panel);
c0fb2fc0 578 if (ret) {
aeaf3306
YF		 579 if (ret != -ENODEV)
580 dev_err(dev, "panel device error %d\n", ret);
581 return ret;
c0fb2fc0 582 }
583
aeaf3306 584 ret = panel_get_display_timing(panel, &timings);
2a0e8784 585 if (ret) {
28c6ba86 586 ret = ofnode_decode_display_timing(dev_ofnode(panel),
aeaf3306
YF		 587 0, &timings);
588 if (ret) {
589 dev_err(dev, "decode display timing error %d\n", ret);
590 return ret;
591 }
2a0e8784 592 }
593
310ef930
GF		 594 rate = clk_set_rate(&pclk, timings.pixelclock.typ);
595 if (IS_ERR_VALUE(rate))
596 dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
597 timings.pixelclock.typ, rate);
aeaf3306 598
8d2257e5 599 dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
310ef930 600 timings.pixelclock.typ, rate);
aeaf3306
YF		 601
602 ret = reset_get_by_index(dev, 0, &rst);
72719d2f 603 if (ret) {
aeaf3306 604 dev_err(dev, "missing ltdc hardware reset\n");
72719d2f
PC		 605 return ret;
606 }
607
aeaf3306
YF		 608 /* Reset */
609 reset_deassert(&rst);
72719d2f 610
aeaf3306
YF		 611 if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
612 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
613 if (ret)
8d2257e5
PD		 614 dev_dbg(dev,
615 "No video bridge, or no backlight on bridge\n");
aeaf3306
YF		 616
617 if (bridge) {
618 ret = video_bridge_attach(bridge);
619 if (ret) {
8d2257e5 620 dev_err(bridge, "fail to attach bridge\n");
aeaf3306
YF		 621 return ret;
622 }
623 }
72719d2f
PC		 624 }
625
72719d2f
PC		 626 /* TODO Below parameters are hard-coded for the moment... */
627 priv->l2bpp = VIDEO_BPP16;
628 priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
629 priv->crop_x = 0;
630 priv->crop_y = 0;
aeaf3306
YF		 631 priv->crop_w = timings.hactive.typ;
632 priv->crop_h = timings.vactive.typ;
72719d2f
PC		 633 priv->alpha = 0xFF;
634
47256b04
DB		 635 ret = stm32_ltdc_alloc_fb(dev);
636 if (ret)
637 return ret;
638
8d2257e5
PD		 639 dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
640 timings.hactive.typ, timings.vactive.typ,
641 VNBITS(priv->l2bpp), uc_plat->base);
642 dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
643 priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
644 priv->bg_col_argb, priv->alpha);
72719d2f
PC		 645
646 /* Configure & start LTDC */
aeaf3306 647 stm32_ltdc_set_mode(priv, &timings);
72719d2f
PC		 648 stm32_ltdc_set_layer1(priv, uc_plat->base);
649 stm32_ltdc_enable(priv);
650
aeaf3306
YF		 651 uc_priv->xsize = timings.hactive.typ;
652 uc_priv->ysize = timings.vactive.typ;
72719d2f
PC		 653 uc_priv->bpix = priv->l2bpp;
654
aeaf3306
YF		 655 if (!bridge) {
656 ret = panel_enable_backlight(panel);
657 if (ret) {
658 dev_err(dev, "panel %s enable backlight error %d\n",
659 panel->name, ret);
660 return ret;
661 }
662 } else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
663 ret = video_bridge_set_backlight(bridge, 80);
664 if (ret) {
665 dev_err(dev, "fail to set backlight\n");
666 return ret;
667 }
668 }
669
72719d2f
PC		 670 video_set_flush_dcache(dev, true);
671
672 return 0;
673}
674
675static int stm32_ltdc_bind(struct udevice *dev)
676{
8a8d24bd 677 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
72719d2f
PC		 678
679 uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
680 CONFIG_VIDEO_STM32_MAX_YRES *
681 (CONFIG_VIDEO_STM32_MAX_BPP >> 3);
6cdeb323
PD		 682 /* align framebuffer on kernel MMU_SECTION_SIZE = max 2MB for LPAE */
683 uc_plat->align = SZ_2M;
684 dev_dbg(dev, "frame buffer max size %d bytes align %x\n",
685 uc_plat->size, uc_plat->align);
72719d2f
PC		 686
687 return 0;
688}
689
690static const struct udevice_id stm32_ltdc_ids[] = {
691 { .compatible = "st,stm32-ltdc" },
692 { }
693};
694
695U_BOOT_DRIVER(stm32_ltdc) = {
c4c33e9d 696 .name = "stm32_display",
697 .id = UCLASS_VIDEO,
698 .of_match = stm32_ltdc_ids,
699 .probe = stm32_ltdc_probe,
700 .bind = stm32_ltdc_bind,
41575d8e 701 .priv_auto = sizeof(struct stm32_ltdc_priv),
72719d2f 702};
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