[thirdparty/u-boot.git] / drivers / video / sunxi / lcdc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Timing controller driver for Allwinner SoCs.
 *
 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
 */

#include <common.h>
#include <log.h>
#include <linux/delay.h>

#include <asm/arch/clock.h>
#include <asm/arch/lcdc.h>
#include <asm/io.h>

static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon)
{
	int delay;

	delay = mode->vfront_porch.typ + mode->vsync_len.typ +
		mode->vback_porch.typ;
	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
		delay /= 2;
	if (tcon == 1)
		delay -= 2;

	return (delay > 30) ? 30 : delay;
}

void lcdc_init(struct sunxi_lcdc_reg * const lcdc)
{
	/* Init lcdc */
	writel(0, &lcdc->ctrl); /* Disable tcon */
	writel(0, &lcdc->int0); /* Disable all interrupts */

	/* Disable tcon0 dot clock */
	clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);

	/* Set all io lines to tristate */
	writel(0xffffffff, &lcdc->tcon0_io_tristate);
	writel(0xffffffff, &lcdc->tcon1_io_tristate);
}

void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)
{
	setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
	setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
#ifdef CONFIG_SUNXI_GEN_SUN6I
	udelay(2); /* delay at least 1200 ns */
	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
	udelay(2); /* delay at least 1200 ns */
	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
	if (depth == 18)
		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
	else
		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
#else
	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
	udelay(2); /* delay at least 1200 ns */
	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
	udelay(1); /* delay at least 120 ns */
	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
#endif
#endif
}

void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
			 const struct display_timing *mode,
			 int clk_div, bool for_ext_vga_dac,
			 int depth, int dclk_phase)
{
	int bp, clk_delay, total, val;

#ifndef CONFIG_SUNXI_DE2
	/* Use tcon0 */
	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
			SUNXI_LCDC_CTRL_IO_MAP_TCON0);
#endif

	clk_delay = lcdc_get_clk_delay(mode, 0);
	writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
	       SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);

	writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
	       SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);

	writel(SUNXI_LCDC_X(mode->hactive.typ) |
	       SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active);

	bp = mode->hsync_len.typ + mode->hback_porch.typ;
	total = mode->hactive.typ + mode->hfront_porch.typ + bp;
	writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
	       SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);

	bp = mode->vsync_len.typ + mode->vback_porch.typ;
	total = mode->vactive.typ + mode->vfront_porch.typ + bp;
	writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
	       SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);

#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_VIDEO_DE2)
	writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
	       SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);

	writel(0, &lcdc->tcon0_hv_intf);
	writel(0, &lcdc->tcon0_cpu_intf);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
	val = (depth == 18) ? 1 : 0;
	writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
	       SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
#endif

	if (depth == 18 || depth == 16) {
		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
		writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
		writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
		writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
		writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
		writel(((depth == 18) ?
			SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
			SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
		       &lcdc->tcon0_frm_ctrl);
	}

	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
	if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
		val |= SUNXI_LCDC_TCON_HSYNC_MASK;
	if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
		val |= SUNXI_LCDC_TCON_VSYNC_MASK;

#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
	if (for_ext_vga_dac)
		val = 0;
#endif
	writel(val, &lcdc->tcon0_io_polarity);

	writel(0, &lcdc->tcon0_io_tristate);
}

void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
			 const struct display_timing *mode,
			 bool ext_hvsync, bool is_composite)
{
	int bp, clk_delay, total, val, yres;

#ifndef CONFIG_SUNXI_DE2
	/* Use tcon1 */
	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
			SUNXI_LCDC_CTRL_IO_MAP_TCON1);
#endif

	clk_delay = lcdc_get_clk_delay(mode, 1);
	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
	       ((mode->flags & DISPLAY_FLAGS_INTERLACED) ?
			SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
	       SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);

	yres = mode->vactive.typ;
	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
		yres /= 2;
	writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
	       &lcdc->tcon1_timing_source);
	writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
	       &lcdc->tcon1_timing_scale);
	writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
	       &lcdc->tcon1_timing_out);

	bp = mode->hsync_len.typ + mode->hback_porch.typ;
	total = mode->hactive.typ + mode->hfront_porch.typ + bp;
	writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
	       SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);

	bp = mode->vsync_len.typ + mode->vback_porch.typ;
	total = mode->vactive.typ + mode->vfront_porch.typ + bp;
	if (!(mode->flags & DISPLAY_FLAGS_INTERLACED))
		total *= 2;
	writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
	       SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);

	writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
	       SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync);

	if (ext_hvsync) {
		val = 0;
		if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
			val |= SUNXI_LCDC_TCON_HSYNC_MASK;
		if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
			val |= SUNXI_LCDC_TCON_VSYNC_MASK;
		writel(val, &lcdc->tcon1_io_polarity);

		clrbits_le32(&lcdc->tcon1_io_tristate,
			     SUNXI_LCDC_TCON_VSYNC_MASK |
			     SUNXI_LCDC_TCON_HSYNC_MASK);
	}

#ifdef CONFIG_MACH_SUN5I
	if (is_composite)
		clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
				SUNXI_LCDC_MUX_CTRL_SRC0(1));
#endif
}

void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
		  int *clk_div, int *clk_double, bool is_composite)
{
	int value, n, m, min_m, max_m, diff, step;
	int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
	int best_double = 0;
	bool use_mipi_pll = false;

#ifdef CONFIG_SUNXI_DE2
	step = 6000;
#else
	step = 3000;
#endif

	if (tcon == 0) {
#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
		min_m = 6;
		max_m = 127;
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
		min_m = 7;
		max_m = 7;
#endif
	} else {
		min_m = 1;
		max_m = 15;
	}

	/*
	 * Find the lowest divider resulting in a matching clock, if there
	 * is no match, pick the closest lower clock, as monitors tend to
	 * not sync to higher frequencies.
	 */
	for (m = min_m; m <= max_m; m++) {
#ifndef CONFIG_SUNXI_DE2
		n = (m * dotclock) / step;

		if ((n >= 9) && (n <= 127)) {
			value = (step * n) / m;
			diff = dotclock - value;
			if (diff < best_diff) {
				best_diff = diff;
				best_m = m;
				best_n = n;
				best_double = 0;
			}
		}

		/* These are just duplicates */
		if (!(m & 1))
			continue;
#endif

		/* No double clock on DE2 */
		n = (m * dotclock) / (step * 2);
		if ((n >= 9) && (n <= 127)) {
			value = (step * 2 * n) / m;
			diff = dotclock - value;
			if (diff < best_diff) {
				best_diff = diff;
				best_m = m;
				best_n = n;
				best_double = 1;
			}
		}
	}

#ifdef CONFIG_MACH_SUN6I
	/*
	 * Use the MIPI pll if we've been unable to find any matching setting
	 * for PLL3, this happens with high dotclocks because of min_m = 6.
	 */
	if (tcon == 0 && best_n == 0) {
		use_mipi_pll = true;
		best_m = 6;  /* Minimum m for tcon0 */
	}

	if (use_mipi_pll) {
		clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */
		clock_set_mipi_pll(best_m * dotclock * 1000);
		debug("dotclock: %dkHz = %dkHz via mipi pll\n",
		      dotclock, clock_get_mipi_pll() / best_m / 1000);
	} else
#endif
	{
		clock_set_pll3(best_n * step * 1000);
		debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
		      dotclock,
		      (best_double + 1) * clock_get_pll3() / best_m / 1000,
		      best_double + 1, step, best_n, best_m);
	}

	if (tcon == 0) {
		u32 pll;

		if (use_mipi_pll)
			pll = CCM_LCD_CH0_CTRL_MIPI_PLL;
		else if (best_double)
			pll = CCM_LCD_CH0_CTRL_PLL3_2X;
		else
			pll = CCM_LCD_CH0_CTRL_PLL3;
#ifndef CONFIG_SUNXI_DE2
		writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
		       &ccm->lcd0_ch0_clk_cfg);
#else
		writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
		       &ccm->lcd0_clk_cfg);
#endif
	}
#ifndef CONFIG_SUNXI_DE2
	else {
		writel(CCM_LCD_CH1_CTRL_GATE |
		       (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
				      CCM_LCD_CH1_CTRL_PLL3) |
		       CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
		if (is_composite)
			setbits_le32(&ccm->lcd0_ch1_clk_cfg,
				     CCM_LCD_CH1_CTRL_HALF_SCLK1);
	}
#endif

	*clk_div = best_m;
	*clk_double = best_double;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5e023e7e JS	2	/*
	3	* Timing controller driver for Allwinner SoCs.
	4	*
	5	* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
	6	* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
	7	* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
5e023e7e JS	8	*/
5e023e7e JS	9
d678a59d	10	#include <common.h>
f7ae49fc	11	#include <log.h>
c05ed00a	12	#include <linux/delay.h>
5e023e7e	13
79f285dd	14	#include <asm/arch/clock.h>
5e023e7e JS	15	#include <asm/arch/lcdc.h>
	16	#include <asm/io.h>
	17
30ca2023	18	static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon)
5e023e7e JS	19	{
	20	int delay;
	21
30ca2023 JS	22	delay = mode->vfront_porch.typ + mode->vsync_len.typ +
	23	mode->vback_porch.typ;
	24	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
5e023e7e JS	25	delay /= 2;
	26	if (tcon == 1)
	27	delay -= 2;
	28
	29	return (delay > 30) ? 30 : delay;
	30	}
	31
	32	void lcdc_init(struct sunxi_lcdc_reg * const lcdc)
	33	{
	34	/* Init lcdc */
	35	writel(0, &lcdc->ctrl); /* Disable tcon */
	36	writel(0, &lcdc->int0); /* Disable all interrupts */
	37
	38	/* Disable tcon0 dot clock */
	39	clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
	40
	41	/* Set all io lines to tristate */
	42	writel(0xffffffff, &lcdc->tcon0_io_tristate);
	43	writel(0xffffffff, &lcdc->tcon1_io_tristate);
	44	}
	45
	46	void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)
	47	{
	48	setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
	49	#ifdef CONFIG_VIDEO_LCD_IF_LVDS
	50	setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
	51	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
	52	#ifdef CONFIG_SUNXI_GEN_SUN6I
	53	udelay(2); /* delay at least 1200 ns */
	54	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
	55	udelay(2); /* delay at least 1200 ns */
	56	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
	57	if (depth == 18)
	58	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
	59	else
	60	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
	61	#else
	62	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
	63	udelay(2); /* delay at least 1200 ns */
	64	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
	65	udelay(1); /* delay at least 120 ns */
	66	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
	67	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
	68	#endif
	69	#endif
	70	}
	71
	72	void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
30ca2023	73	const struct display_timing *mode,
5e023e7e JS	74	int clk_div, bool for_ext_vga_dac,
	75	int depth, int dclk_phase)
	76	{
	77	int bp, clk_delay, total, val;
	78
1ae5def6	79	#ifndef CONFIG_SUNXI_DE2
5e023e7e JS	80	/* Use tcon0 */
	81	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
	82	SUNXI_LCDC_CTRL_IO_MAP_TCON0);
1ae5def6	83	#endif
5e023e7e JS	84
	85	clk_delay = lcdc_get_clk_delay(mode, 0);
	86	writel(SUNXI_LCDC_TCON0_CTRL_ENABLE \|
	87	SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
	88
	89	writel(SUNXI_LCDC_TCON0_DCLK_ENABLE \|
	90	SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
	91
30ca2023 JS	92	writel(SUNXI_LCDC_X(mode->hactive.typ) \|
30ca2023 JS	93	SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active);
5e023e7e	94
30ca2023 JS	95	bp = mode->hsync_len.typ + mode->hback_porch.typ;
30ca2023 JS	96	total = mode->hactive.typ + mode->hfront_porch.typ + bp;
5e023e7e JS	97	writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) \|
	98	SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
	99
30ca2023 JS	100	bp = mode->vsync_len.typ + mode->vback_porch.typ;
30ca2023 JS	101	total = mode->vactive.typ + mode->vfront_porch.typ + bp;
5e023e7e JS	102	writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) \|
	103	SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
	104
79f285dd	105	#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) \|\| defined(CONFIG_VIDEO_DE2)
30ca2023 JS	106	writel(SUNXI_LCDC_X(mode->hsync_len.typ) \|
30ca2023 JS	107	SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);
5e023e7e JS	108
	109	writel(0, &lcdc->tcon0_hv_intf);
	110	writel(0, &lcdc->tcon0_cpu_intf);
	111	#endif
	112	#ifdef CONFIG_VIDEO_LCD_IF_LVDS
	113	val = (depth == 18) ? 1 : 0;
	114	writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) \|
	115	SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
	116	#endif
	117
	118	if (depth == 18 \|\| depth == 16) {
	119	writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
	120	writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
	121	writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
	122	writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
	123	writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
	124	writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
	125	writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
	126	writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
	127	writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
	128	writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
	129	writel(((depth == 18) ?
	130	SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
	131	SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
	132	&lcdc->tcon0_frm_ctrl);
	133	}
	134
	135	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
30ca2023	136	if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
5e023e7e	137	val \|= SUNXI_LCDC_TCON_HSYNC_MASK;
30ca2023	138	if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
5e023e7e JS	139	val \|= SUNXI_LCDC_TCON_VSYNC_MASK;
	140
	141	#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
	142	if (for_ext_vga_dac)
	143	val = 0;
	144	#endif
	145	writel(val, &lcdc->tcon0_io_polarity);
	146
	147	writel(0, &lcdc->tcon0_io_tristate);
	148	}
	149
	150	void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
30ca2023	151	const struct display_timing *mode,
5e023e7e JS	152	bool ext_hvsync, bool is_composite)
	153	{
	154	int bp, clk_delay, total, val, yres;
	155
1ae5def6	156	#ifndef CONFIG_SUNXI_DE2
5e023e7e JS	157	/* Use tcon1 */
	158	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
	159	SUNXI_LCDC_CTRL_IO_MAP_TCON1);
1ae5def6	160	#endif
5e023e7e JS	161
	162	clk_delay = lcdc_get_clk_delay(mode, 1);
	163	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE \|
30ca2023	164	((mode->flags & DISPLAY_FLAGS_INTERLACED) ?
5e023e7e JS	165	SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) \|
	166	SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
	167
30ca2023 JS	168	yres = mode->vactive.typ;
30ca2023 JS	169	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
5e023e7e	170	yres /= 2;
30ca2023	171	writel(SUNXI_LCDC_X(mode->hactive.typ) \| SUNXI_LCDC_Y(yres),
5e023e7e	172	&lcdc->tcon1_timing_source);
30ca2023	173	writel(SUNXI_LCDC_X(mode->hactive.typ) \| SUNXI_LCDC_Y(yres),
5e023e7e	174	&lcdc->tcon1_timing_scale);
30ca2023	175	writel(SUNXI_LCDC_X(mode->hactive.typ) \| SUNXI_LCDC_Y(yres),
5e023e7e JS	176	&lcdc->tcon1_timing_out);
5e023e7e JS	177
30ca2023 JS	178	bp = mode->hsync_len.typ + mode->hback_porch.typ;
30ca2023 JS	179	total = mode->hactive.typ + mode->hfront_porch.typ + bp;
5e023e7e JS	180	writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) \|
	181	SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
	182
30ca2023 JS	183	bp = mode->vsync_len.typ + mode->vback_porch.typ;
	184	total = mode->vactive.typ + mode->vfront_porch.typ + bp;
	185	if (!(mode->flags & DISPLAY_FLAGS_INTERLACED))
5e023e7e JS	186	total *= 2;
	187	writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) \|
	188	SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
	189
30ca2023 JS	190	writel(SUNXI_LCDC_X(mode->hsync_len.typ) \|
30ca2023 JS	191	SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync);
5e023e7e JS	192
	193	if (ext_hvsync) {
	194	val = 0;
30ca2023	195	if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
5e023e7e	196	val \|= SUNXI_LCDC_TCON_HSYNC_MASK;
30ca2023	197	if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
5e023e7e JS	198	val \|= SUNXI_LCDC_TCON_VSYNC_MASK;
	199	writel(val, &lcdc->tcon1_io_polarity);
	200
	201	clrbits_le32(&lcdc->tcon1_io_tristate,
	202	SUNXI_LCDC_TCON_VSYNC_MASK \|
	203	SUNXI_LCDC_TCON_HSYNC_MASK);
	204	}
	205
	206	#ifdef CONFIG_MACH_SUN5I
	207	if (is_composite)
	208	clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
	209	SUNXI_LCDC_MUX_CTRL_SRC0(1));
	210	#endif
	211	}
79f285dd VK	212
	213	void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
	214	int clk_div, int clk_double, bool is_composite)
	215	{
7d121a8e	216	int value, n, m, min_m, max_m, diff, step;
79f285dd VK	217	int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
	218	int best_double = 0;
	219	bool use_mipi_pll = false;
	220
7d121a8e IZ	221	#ifdef CONFIG_SUNXI_DE2
	222	step = 6000;
	223	#else
	224	step = 3000;
	225	#endif
	226
79f285dd VK	227	if (tcon == 0) {
	228	#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) \|\| defined(CONFIG_SUNXI_DE2)
	229	min_m = 6;
	230	max_m = 127;
	231	#endif
	232	#ifdef CONFIG_VIDEO_LCD_IF_LVDS
	233	min_m = 7;
	234	max_m = 7;
	235	#endif
	236	} else {
	237	min_m = 1;
	238	max_m = 15;
	239	}
	240
	241	/*
	242	* Find the lowest divider resulting in a matching clock, if there
	243	* is no match, pick the closest lower clock, as monitors tend to
	244	* not sync to higher frequencies.
	245	*/
	246	for (m = min_m; m <= max_m; m++) {
	247	#ifndef CONFIG_SUNXI_DE2
7d121a8e	248	n = (m * dotclock) / step;
79f285dd VK	249
79f285dd VK	250	if ((n >= 9) && (n <= 127)) {
7d121a8e	251	value = (step * n) / m;
79f285dd VK	252	diff = dotclock - value;
	253	if (diff < best_diff) {
	254	best_diff = diff;
	255	best_m = m;
	256	best_n = n;
	257	best_double = 0;
	258	}
	259	}
	260
	261	/* These are just duplicates */
	262	if (!(m & 1))
	263	continue;
	264	#endif
	265
	266	/* No double clock on DE2 */
7d121a8e	267	n = (m * dotclock) / (step * 2);
79f285dd	268	if ((n >= 9) && (n <= 127)) {
7d121a8e	269	value = (step * 2 * n) / m;
79f285dd VK	270	diff = dotclock - value;
	271	if (diff < best_diff) {
	272	best_diff = diff;
	273	best_m = m;
	274	best_n = n;
	275	best_double = 1;
	276	}
	277	}
	278	}
	279
	280	#ifdef CONFIG_MACH_SUN6I
	281	/*
	282	* Use the MIPI pll if we've been unable to find any matching setting
	283	* for PLL3, this happens with high dotclocks because of min_m = 6.
	284	*/
	285	if (tcon == 0 && best_n == 0) {
	286	use_mipi_pll = true;
	287	best_m = 6; /* Minimum m for tcon0 */
	288	}
	289
	290	if (use_mipi_pll) {
	291	clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */
	292	clock_set_mipi_pll(best_m * dotclock * 1000);
	293	debug("dotclock: %dkHz = %dkHz via mipi pll\n",
	294	dotclock, clock_get_mipi_pll() / best_m / 1000);
	295	} else
	296	#endif
	297	{
7d121a8e IZ	298	clock_set_pll3(best_n * step * 1000);
7d121a8e IZ	299	debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
79f285dd VK	300	dotclock,
79f285dd VK	301	(best_double + 1) * clock_get_pll3() / best_m / 1000,
7d121a8e	302	best_double + 1, step, best_n, best_m);
79f285dd VK	303	}
	304
	305	if (tcon == 0) {
	306	u32 pll;
	307
	308	if (use_mipi_pll)
	309	pll = CCM_LCD_CH0_CTRL_MIPI_PLL;
	310	else if (best_double)
	311	pll = CCM_LCD_CH0_CTRL_PLL3_2X;
	312	else
	313	pll = CCM_LCD_CH0_CTRL_PLL3;
	314	#ifndef CONFIG_SUNXI_DE2
	315	writel(CCM_LCD_CH0_CTRL_GATE \| CCM_LCD_CH0_CTRL_RST \| pll,
	316	&ccm->lcd0_ch0_clk_cfg);
	317	#else
	318	writel(CCM_LCD_CH0_CTRL_GATE \| CCM_LCD_CH0_CTRL_RST \| pll,
	319	&ccm->lcd0_clk_cfg);
	320	#endif
	321	}
	322	#ifndef CONFIG_SUNXI_DE2
	323	else {
	324	writel(CCM_LCD_CH1_CTRL_GATE \|
	325	(best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
	326	CCM_LCD_CH1_CTRL_PLL3) \|
	327	CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
	328	if (is_composite)
	329	setbits_le32(&ccm->lcd0_ch1_clk_cfg,
	330	CCM_LCD_CH1_CTRL_HALF_SCLK1);
	331	}
	332	#endif
	333
	334	*clk_div = best_m;
	335	*clk_double = best_double;
	336	}