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[thirdparty/binutils-gdb.git] / gas / ChangeLog
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12013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * config/tc-mips.c (mips_check_isa_supports_ase, reg_lookup)
4 (mips_parse_argument_token, validate_micromips_insn, md_begin)
5 (check_regno, match_float_constant, check_completed_insn, append_insn)
6 (match_insn, match_mips16_insn, match_insns, macro_start)
7 (macro_build_ldst_constoffset, load_register, macro, mips_ip)
8 (mips16_ip, mips_set_option_string, md_parse_option)
9 (mips_after_parse_args, mips_after_parse_args, md_pcrel_from)
10 (md_apply_fix, s_align, s_option, s_mipsset, s_tls_rel_directive)
11 (s_gpword, s_gpdword, s_ehword, s_nan, tc_gen_reloc, md_convert_frag)
12 (s_mips_end, s_mips_ent, s_mips_frame, s_mips_mask, mips_parse_cpu):
13 Start error messages with a lower-case letter. Do not end error
14 messages with a period. Wrap long messages to 80 character-lines.
15 Use "cannot" instead of "can't" and "can not".
16
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172013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
18
19 * config/tc-mips.c (imm_expr): Expand comment.
20 (set_at, macro, mips16_macro): Expect imm_expr to be O_constant
21 when populated.
22
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232013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
24
25 * config/tc-mips.c (imm2_expr): Delete.
26 (md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly.
27
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282013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
29
30 * config/tc-mips.c (report_bad_range, report_bad_field): Delete.
31 (macro): Remove M_DEXT and M_DINS handling.
32
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332013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
34
35 * config/tc-mips.c (mips_arg_info): Replace allow_nonconst and
36 lax_max with lax_match.
37 (match_int_operand): Update accordingly. Don't report an error
38 for !lax_match-only cases.
39 (match_insn): Replace more_alts with lax_match and use it to
40 initialize the mips_arg_info field. Add a complete_p parameter.
41 Handle implicit VU0 suffixes here.
42 (match_invalid_for_isa, match_insns, match_mips16_insns): New
43 functions.
44 (mips_ip, mips16_ip): Use them.
45
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462013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
47
48 * config/tc-mips.c (match_expression): Report uses of registers here.
49 Add a "must be an immediate expression" error. Handle elided offsets
50 here rather than...
51 (match_int_operand): ...here.
52
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532013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
54
55 * config/tc-mips.c (mips_arg_info): Remove soft_match.
56 (match_out_of_range, match_not_constant): New functions.
57 (match_const_int): Remove fallback parameter and check for soft_match.
58 Use match_not_constant.
59 (match_mapped_int_operand, match_addiusp_operand)
60 (match_perf_reg_operand, match_save_restore_list_operand)
61 (match_mdmx_imm_reg_operand): Update accordingly. Use
62 match_out_of_range and set_insn_error* instead of as_bad.
63 (match_int_operand): Likewise. Use match_not_constant in the
64 !allows_nonconst case.
65 (match_float_constant): Report invalid float constants.
66 (match_insn, match_mips16_insn): Remove soft_match code. Rely on
67 match_float_constant to check for invalid constants. Fail the
68 match if match_const_int or match_float_constant return false.
69 (mips_ip): Update accordingly.
70 (mips16_ip): Likewise. Undo null termination of instruction name
71 once lookup is complete.
72
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732013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
74
75 * config/tc-mips.c (mips_insn_error_format): New enum.
76 (mips_insn_error): New struct.
77 (insn_error): Change to a mips_insn_error.
78 (clear_insn_error, set_insn_error_format, set_insn_error)
79 (set_insn_error_i, set_insn_error_ss, report_insn_error): New
80 functions.
81 (mips_parse_argument_token, md_assemble, match_insn)
82 (match_mips16_insn): Use them instead of manipulating insn_error
83 directly.
84 (mips_ip, mips16_ip): Likewise. Simplify control flow.
85
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862013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
87
88 * config/tc-mips.c (normalize_constant_expr): Move further up file.
89 (normalize_address_expr): Likewise.
90 (match_insn, match_mips16_insn): New functions, split out from...
91 (mips_ip, mips16_ip): ...here.
92
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932013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
94
95 * config/tc-mips.c (operand_reg_mask, match_operand): Handle
96 OP_OPTIONAL_REG.
97 (mips_ip, mips16_ip): Use mips_optional_operand_p to check
98 for optional operands.
99
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1002013-08-16 Alan Modra <amodra@gmail.com>
101
102 * config/tc-ppc.c (ppc_elf_cons): Allow @l and other reloc
103 modifiers generally.
104
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1052013-08-16 Alan Modra <amodra@gmail.com>
106
107 * config/tc-ppc.c (ppc_elf_lcomm): Use subsection 1.
108
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1092013-08-14 David Edelsohn <dje.gcc@gmail.com>
110
111 * config/tc-ppc.c (ppc_comm): Accept optional fourth .lcomm
112 argument as alignment.
113
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1142013-08-09 Nick Clifton <nickc@redhat.com>
115
116 * config/tc-rl78.c (elf_flags): New variable.
117 (enum options): Add OPTION_G10.
118 (md_longopts): Add mg10.
119 (md_parse_option): Parse -mg10.
120 (rl78_elf_final_processing): New function.
121 * config/tc-rl78.c (tc_final_processing): Define.
122 * doc/c-rl78.texi: Document -mg10 option.
123
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1242013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
125
126 * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
127 suffixes to be elided too.
128 (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
129 (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N
130 to be omitted too.
131
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1322013-08-05 John Tytgat <john@bass-software.com>
133
134 * po/POTFILES.in: Regenerate.
135
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1362013-08-05 Eric Botcazou <ebotcazou@adacore.com>
137 Konrad Eisele <konrad@gaisler.com>
138
139 * config/tc-sparc.c (sparc_arch_types): Add leon.
140 (sparc_arch): Move sparc4 around and add leon.
141 (sparc_target_format): Document -Aleon.
142 * doc/c-sparc.texi: Likewise.
143
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1442013-08-05 Richard Sandiford <rdsandiford@googlemail.com>
145
146 * config/tc-mips.c (mips_lookup_insn): Make length and opend signed.
147
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1482013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
149 Richard Sandiford <rdsandiford@googlemail.com>
150
151 * config/tc-mips.c (MAX_OPERANDS): Bump to 6.
152 (RWARN): Bump to 0x8000000.
153 (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
154 (RTYPE_R5900_ACC): New register types.
155 (RTYPE_MASK): Include them.
156 (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
157 macros.
158 (reg_names): Include them.
159 (mips_parse_register_1): New function, split out from...
160 (mips_parse_register): ...here. Add a channels_ptr parameter.
161 Look for VU0 channel suffixes when nonnull.
162 (reg_lookup): Update the call to mips_parse_register.
163 (mips_parse_vu0_channels): New function.
164 (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
165 (mips_operand_token): Add a "channels" field to the union.
166 Extend the comment above "ch" to OT_DOUBLE_CHAR.
167 (mips_parse_base_start): Match -- and ++. Handle channel suffixes.
168 (mips_parse_argument_token): Handle channel suffixes here too.
169 (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
170 Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
171 Handle '#' formats.
172 (md_begin): Register $vfN and $vfI registers.
173 (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
174 (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
175 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
176 (match_vu0_suffix_operand): New function.
177 (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
178 (macro): Use "+7" rather than "E" for LDQ2 and STQ2.
179 (mips_lookup_insn): New function.
180 (mips_ip): Use it. Allow "+K" operands to be elided at the end
181 of an instruction. Handle '#' sequences.
182
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1832013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
184
185 * config/tc-mips.c (macro, mips16_macro): Create an array of operand
186 values and use it instead of sreg, treg, xreg, etc.
187
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1882013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
189
190 * config/tc-mips.c (match_int_operand): Use mips_int_operand_min
191 and mips_int_operand_max.
192 (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
193 Delete.
194 (mips16_immed_operand, mips16_immed_in_range_p): New functions.
195 (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
196 instead of mips16_immed_operand.
197
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1982013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
199
200 * config/tc-mips.c (mips16_macro): Don't use move_register.
201 (mips16_ip): Allow macros to use 'p'.
202
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2032013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
204
205 * config/tc-mips.c (MAX_OPERANDS): New macro.
206 (mips_operand_array): New structure.
207 (mips_operands, mips16_operands, micromips_operands): New arrays.
208 (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
209 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
210 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
211 (micromips_to_32_reg_q_map): Delete.
212 (insn_operands, insn_opno, insn_extract_operand): New functions.
213 (validate_mips_insn): Take a mips_operand_array as argument and
214 use it to build up a list of operands. Extend to handle INSN_MACRO
215 and MIPS16.
216 (validate_mips16_insn): New function.
217 (validate_micromips_insn): Take a mips_operand_array as argument.
218 Handle INSN_MACRO.
219 (md_begin): Initialize mips_operands, mips16_operands and
220 micromips_operands. Call validate_mips_insn and
221 validate_micromips_insn for macro instructions too.
222 Call validate_mips16_insn for MIPS16 instructions.
223 (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
224 New functions.
225 (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
226 them. Handle INSN_UDI.
227 (get_append_method): Use gpr_read_mask.
228
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2292013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
230
231 * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
232 flags for MIPS16 and non-MIPS16 instructions.
233 (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
234 (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
235 (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
236 (can_swap_branch_p, get_append_method): Use the same flags for MIPS16
237 and non-MIPS16 instructions. Fix formatting.
238
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2392013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
240
241 * config/tc-mips.c (reg_needs_delay): Move later in file.
242 Use gpr_write_mask.
243 (insns_between): Use gpr_read_mask instead of EXTRACT_OPERAND.
244
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2452013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
246 Alexander Ivchenko <alexander.ivchenko@intel.com>
247 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
248 Sergey Lega <sergey.s.lega@intel.com>
249 Anna Tikhonova <anna.tikhonova@intel.com>
250 Ilya Tocar <ilya.tocar@intel.com>
251 Andrey Turetskiy <andrey.turetskiy@intel.com>
252 Ilya Verbin <ilya.verbin@intel.com>
253 Kirill Yukhin <kirill.yukhin@intel.com>
254 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
255
256 * config/tc-i386-intel.c (O_zmmword_ptr): New.
257 (i386_types): Add zmmword.
258 (i386_intel_simplify_register): Allow regzmm.
259 (i386_intel_simplify): Handle zmmwords.
260 (i386_intel_operand): Handle RC/SAE, vector operations and
261 zmmwords.
262 * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
263 (struct RC_Operation): New.
264 (struct Mask_Operation): New.
265 (struct Broadcast_Operation): New.
266 (vex_prefix): Size of bytes increased to 4 to support EVEX
267 encoding.
268 (enum i386_error): Add new error codes: unsupported_broadcast,
269 broadcast_not_on_src_operand, broadcast_needed,
270 unsupported_masking, mask_not_on_destination, no_default_mask,
271 unsupported_rc_sae, rc_sae_operand_not_last_imm,
272 invalid_register_operand, try_vector_disp8.
273 (struct _i386_insn): Add new fields vrex, need_vrex, mask,
274 rounding, broadcast, memshift.
275 (struct RC_name): New.
276 (RC_NamesTable): New.
277 (evexlig): New.
278 (evexwig): New.
279 (extra_symbol_chars): Add '{'.
280 (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
281 (i386_operand_type): Add regzmm, regmask and vec_disp8.
282 (match_mem_size): Handle zmmwords.
283 (operand_type_match): Handle zmm-registers.
284 (mode_from_disp_size): Handle vec_disp8.
285 (fits_in_vec_disp8): New.
286 (md_begin): Handle {} properly.
287 (type_names): Add "rZMM", "Mask reg" and "Vector d8".
288 (build_vex_prefix): Handle vrex.
289 (build_evex_prefix): New.
290 (process_immext): Adjust to properly handle EVEX.
291 (md_assemble): Add EVEX encoding support.
292 (swap_2_operands): Correctly handle operands with masking,
293 broadcasting or RC/SAE.
294 (check_VecOperands): Support EVEX features.
295 (VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
296 (match_template): Support regzmm and handle new error codes.
297 (process_suffix): Handle zmmwords and zmm-registers.
298 (check_byte_reg): Extend to zmm-registers.
299 (process_operands): Extend to zmm-registers.
300 (build_modrm_byte): Handle EVEX.
301 (output_insn): Adjust to properly handle EVEX case.
302 (disp_size): Handle vec_disp8.
303 (output_disp): Support compressed disp8*N evex feature.
304 (output_imm): Handle RC/SAE immediates properly.
305 (check_VecOperations): New.
306 (i386_immediate): Handle EVEX features.
307 (i386_index_check): Handle zmmwords and zmm-registers.
308 (RC_SAE_immediate): New.
309 (i386_att_operand): Handle EVEX features.
310 (parse_real_register): Add a check for ZMM/Mask registers.
311 (OPTION_MEVEXLIG): New.
312 (OPTION_MEVEXWIG): New.
313 (md_longopts): Add mevexlig and mevexwig.
314 (md_parse_option): Handle mevexlig and mevexwig options.
315 (md_show_usage): Add description for mevexlig and mevexwig.
316 * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
317 avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
318
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3192013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
320
321 * config/tc-i386.c (cpu_arch): Add .sha.
322 * doc/c-i386.texi: Document sha/.sha.
323
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3242013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
325 Kirill Yukhin <kirill.yukhin@intel.com>
326 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
327
328 * config/tc-i386.c (BND_PREFIX): New.
329 (struct _i386_insn): Add new field bnd_prefix.
330 (add_bnd_prefix): New.
331 (cpu_arch): Add MPX.
332 (i386_operand_type): Add regbnd.
333 (md_assemble): Handle BND prefixes.
334 (parse_insn): Likewise.
335 (output_branch): Likewise.
336 (output_jump): Likewise.
337 (build_modrm_byte): Handle regbnd.
338 (OPTION_MADD_BND_PREFIX): New.
339 (md_longopts): Add entry for 'madd-bnd-prefix'.
340 (md_parse_option): Handle madd-bnd-prefix option.
341 (md_show_usage): Add description for madd-bnd-prefix
342 option.
343 * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.
344
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3452013-07-24 Tristan Gingold <gingold@adacore.com>
346
347 * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on
348 xcoff targets.
349
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3502013-07-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
351
352 * config/tc-s390.c (s390_machine): Don't force the .machine
353 argument to lower case.
354
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3552013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
356
357 * config/tc-arm.c (s_arm_arch_extension): Improve error message
358 for invalid extension.
359
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3602013-07-19 Yufeng Zhang <yufeng.zhang@arm.com>
361
362 * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
363 (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
364 (aarch64_abi): New variable.
365 (ilp32_p): Change to be a macro.
366 (aarch64_opts): Remove the support for option -milp32 and -mlp64.
367 (struct aarch64_option_abi_value_table): New struct.
368 (aarch64_abis): New table.
369 (aarch64_parse_abi): New function.
370 (aarch64_long_opts): Add entry for -mabi=.
371 * doc/as.texinfo (Target AArch64 options): Document -mabi.
372 * doc/c-aarch64.texi: Likewise.
373
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3742013-07-18 Jim Thomas <thomas@cfht.hawaii.edu>
375
376 * config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs
377 unsigned comparison.
378
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3792013-07-18 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
380
cbe02d4f 381 * config/rx-defs.h: Add macros for RX100, RX200, RX600, and
f0c00282 382 RX610.
cbe02d4f 383 * config/rx-parse.y: (rx_check_float_support): Add function to
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384 check floating point operation support for target RX100 and
385 RX200.
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386 * config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610.
387 * doc/c-rx.texi: Add -mcpu option to recognize macros for RX100,
388 RX200, RX600, and RX610
f0c00282 389
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3902013-07-18 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
391
392 * config/tc-avr.c (md_show_usage): Add avrxmega2 to help text
393
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3942013-07-18 Vishnu K.S <vishnu.k_s@atmel.com>
395
396 * config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4.
397 * doc/c-avr.texi: Likewise.
398
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3992013-07-15 Richard Sandiford <rdsandiford@googlemail.com>
400
401 * config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat
402 error with older GCCs.
403 (mips16_macro_build): Dereference args.
404
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4052013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
406
407 * config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
408 New functions, split out from...
409 (reg_lookup): ...here. Remove itbl support.
410 (reglist_lookup): Delete.
411 (mips_operand_token_type): New enum.
412 (mips_operand_token): New structure.
413 (mips_operand_tokens): New variable.
414 (mips_add_token, mips_parse_base_start, mips_parse_argument_token)
415 (mips_parse_arguments): New functions.
416 (md_begin): Initialize mips_operand_tokens.
417 (mips_arg_info): Add a token field. Remove optional_reg field.
418 (match_char, match_expression): New functions.
419 (match_const_int): Use match_expression. Remove "s" argument
420 and return a boolean result. Remove O_register handling.
421 (match_regno, match_reg, match_reg_range): New functions.
422 (match_int_operand, match_mapped_int_operand, match_msb_operand)
423 (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
424 (match_addiusp_operand, match_clo_clz_dest_operand)
425 (match_lwm_swm_list_operand, match_entry_exit_operand)
426 (match_save_restore_list_operand, match_mdmx_imm_reg_operand)
427 (match_tied_reg_operand): Remove "s" argument and return a boolean
428 result. Match tokens rather than text. Update calls to
429 match_const_int. Rely on match_regno to call check_regno.
430 (match_pcrel_operand, match_pc_operand): Replace "s" argument with
431 "arg" argument. Return a boolean result.
432 (parse_float_constant): Replace with...
433 (match_float_constant): ...this new function.
434 (match_operand): Remove "s" argument and return a boolean result.
435 Update calls to subfunctions.
436 (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
437 rather than string-parsing routines. Update handling of optional
438 registers for token scheme.
439
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4402013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
441
442 * config/tc-mips.c (parse_float_constant): Split out from...
443 (mips_ip): ...here.
444
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4452013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
446
447 * config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND):
448 Delete.
449
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4502013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
451
452 * config/tc-mips.c (mips32_to_16_reg_map): Delete.
453 (match_entry_exit_operand): New function.
454 (match_save_restore_list_operand): Likewise.
455 (match_operand): Use them.
456 (check_absolute_expr): Delete.
457 (mips16_ip): Rewrite main parsing loop to use mips_operands.
458
9e12b7a2
RS
4592013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
460
461 * config/tc-mips.c: Enable functions commented out in previous patch.
462 (SKIP_SPACE_TABS): Move further up file.
463 (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map)
464 (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map)
465 (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map)
466 (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map)
467 (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map)
468 (micromips_imm_b_map, micromips_imm_c_map): Delete.
469 (mips_lookup_reg_pair): Delete.
470 (macro): Use report_bad_range and report_bad_field.
471 (mips_immed, expr_const_in_range): Delete.
472 (mips_ip): Rewrite main parsing loop to use new functions.
473
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RS
4742013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
475
476 * config/tc-mips.c (mips_oddfpreg_ok): Move further up file.
477 Change return type to bfd_boolean.
478 (report_bad_range, report_bad_field): New functions.
479 (mips_arg_info): New structure.
480 (match_const_int, convert_reg_type, check_regno, match_int_operand)
481 (match_mapped_int_operand, match_msb_operand, match_reg_operand)
482 (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand)
483 (match_addiusp_operand, match_clo_clz_dest_operand)
484 (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand)
485 (match_pc_operand, match_tied_reg_operand, match_operand)
486 (check_completed_insn): New functions, commented out for now.
487
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RS
4882013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
489
490 * config/tc-mips.c (insn_insert_operand): New function.
491 (macro_build, mips16_macro_build): Put null character check
492 in the for loop and convert continues to breaks. Use operand
493 structures to handle constant operands.
494
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RS
4952013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
496
497 * config/tc-mips.c (validate_mips_insn): Move further up file.
498 Add insn_bits and decode_operand arguments. Use the mips_operand
499 fields to work out which bits an operand occupies. Detect double
500 definitions.
501 (validate_micromips_insn): Move further up file. Call into
502 validate_mips_insn.
503
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RS
5042013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
505
506 * config/tc-mips.c (mips16_macro_build): Remove 'Y' case.
507
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RS
5082013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
509
510 * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\"
511 and "~".
512 (macro): Update accordingly.
513
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RS
5142013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
515
516 * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary.
517 (imm_reloc): Delete.
518 (md_assemble): Remove imm_reloc handling.
519 (mips_ip): Update commentary. Use offset_expr and offset_reloc
520 rather than imm_expr and imm_reloc for 'i', 'j' and 'u'.
521 Use a temporary array rather than imm_reloc when parsing
522 constant expressions. Remove imm_reloc initialization.
523 (mips16_ip): Update commentary. Use offset_expr and offset_reloc
524 for the relaxable field. Use a relax_char variable to track the
525 type of this field. Remove imm_reloc initialization.
526
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RS
5272013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
528
529 * config/tc-mips.c (mips16_ip): Handle "I".
530
ba92f887
MR
5312013-07-12 Maciej W. Rozycki <macro@codesourcery.com>
532
533 * config/tc-mips.c (mips_flag_nan2008): New variable.
534 (options): Add OPTION_NAN enum value.
535 (md_longopts): Handle it.
536 (md_parse_option): Likewise.
537 (s_nan): New function.
538 (mips_elf_final_processing): Handle EF_MIPS_NAN2008.
539 (md_show_usage): Add -mnan.
540
541 * doc/as.texinfo (Overview): Add -mnan.
542 * doc/c-mips.texi (MIPS Opts): Document -mnan.
543 (MIPS NaN Encodings): New node. Document .nan directive.
544 (MIPS-Dependent): List the new node.
545
c1094734
TG
5462013-07-09 Tristan Gingold <gingold@adacore.com>
547
548 * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
549
0cbbe1b8
RS
5502013-07-08 Richard Sandiford <rdsandiford@googlemail.com>
551
552 * config/tc-mips.c (mips_ip): Unconditionally parse an expression
553 for 'A' and assume that the constant has been elided if the result
554 is an O_register.
555
f2ae14a1
RS
5562013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
557
558 * config/tc-mips.c (gprel16_reloc_p): New function.
559 (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
560 BFD_RELOC_UNUSED.
561 (offset_high_part, small_offset_p): New functions.
562 (nacro): Use them. Remove *_OB and *_DOB cases. For single-
563 register load and store macros, handle the 16-bit offset case first.
564 If a 16-bit offset is not suitable for the instruction we're
565 generating, load it into the temporary register using
566 ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
567 M_L_DAB code once the address has been constructed. For double load
568 and store macros, again handle the 16-bit offset case first.
569 If the second register cannot be accessed from the same high
570 part as the first, load it into AT using ADDRESS_ADDI_INSN.
571 Fix the handling of LD in cases where the first register is the
572 same as the base. Also handle the case where the offset is
573 not 16 bits and the second register cannot be accessed from the
574 same high part as the first. For unaligned loads and stores,
575 fuse the offbits == 12 and old "ab" handling. Apply this handling
576 whenever the second offset needs a different high part from the first.
577 Construct the offset using ADDRESS_ADDI_INSN where possible,
578 for offbits == 16 as well as offbits == 12. Use offset_reloc
579 when constructing the individual loads and stores.
580 (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
581 and offset_reloc before matching against a particular opcode.
582 Handle elided 'A' constants. Allow 'A' constants to use
583 relocation operators.
584
5c324c16
RS
5852013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
586
587 * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
588 (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
589 Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
590
23e69e47
RS
5912013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
592
593 * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
594 Require the msb to be <= 31 for "+s". Check that the size is <= 31
595 for both "+s" and "+S".
596
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RS
5972013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
598
599 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
600 (mips_ip, mips16_ip): Handle "+i".
601
e76ff5ab
RS
6022013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
603
604 * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
605 (micromips_to_32_reg_h_map): Rename to...
606 (micromips_to_32_reg_h_map1): ...this.
607 (micromips_to_32_reg_i_map): Rename to...
608 (micromips_to_32_reg_h_map2): ...this.
609 (mips_lookup_reg_pair): New function.
610 (gpr_write_mask, macro): Adjust after above renaming.
611 (validate_micromips_insn): Remove "mi" handling.
612 (mips_ip): Likewise. Parse both registers in a pair for "mh".
613
fa7616a4
RS
6142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
615
616 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
617 (mips_ip): Remove "+D" and "+T" handling.
618
fb798c50
AK
6192013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
620
621 * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
622 relocs.
623
2c0a3565
MS
6242013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
625
4aa2c5e2
MS
626 * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
627
6282013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
629
2c0a3565
MS
630 * config/tc-aarch64.c (md_apply_fix): Reorder case values.
631 (aarch64_force_relocation): Likewise.
632
f40da81b
AM
6332013-07-02 Alan Modra <amodra@gmail.com>
634
635 * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
636
81566a9b
MR
6372013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
638
639 * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
640 * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
641 Replace @sc{mips16} with literal `MIPS16'.
642 (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
643
a6bb11b2
YZ
6442013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
645
646 * config/tc-aarch64.c (reloc_table): Replace
647 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
648 BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
649 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
650 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
651 (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
652 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
653 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
654 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
655 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
656 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
657 (aarch64_force_relocation): Likewise.
658
cec5225b
YZ
6592013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
660
661 * config/tc-aarch64.c (ilp32_p): New static variable.
662 (elf64_aarch64_target_format): Return the target according to the
663 value of 'ilp32_p'.
664 (md_begin): Determine 'mach' according to the value of 'ilp32_p'.
665 (aarch64_opts): Add support for options '-milp32' and '-mlp64'.
666 (aarch64_dwarf2_addr_size): New function.
667 * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
668 (DWARF2_ADDR_SIZE): New define.
669
e335d9cb
RS
6702013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
671
672 * doc/c-mips.texi: Use ISA instead of @sc{isa}.
673
18870af7
RS
6742013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
675
676 * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
677
833794fc
MR
6782013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
679
680 * config/tc-mips.c (mips_set_options): Add insn32 member.
681 (mips_opts): Initialize it.
682 (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
683 (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
684 (md_longopts): Add "minsn32" and "mno-insn32" options.
685 (is_size_valid): Handle insn32 mode.
686 (md_assemble): Pass instruction string down to macro.
687 (brk_fmt): Add second dimension and insn32 mode initializers.
688 (mfhl_fmt): Likewise.
689 (BRK_FMT, MFHL_FMT): Handle insn32 mode.
690 (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
691 (macro_build_jalr, move_register): Handle insn32 mode.
692 (macro_build_branch_rs): Likewise.
693 (macro): Handle insn32 mode.
694 <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
695 (mips_ip): Handle insn32 mode.
696 (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
697 (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
698 (mips_handle_align): Handle insn32 mode.
699 (md_show_usage): Add -minsn32 and -mno-insn32.
700
701 * doc/as.texinfo (Target MIPS options): Add -minsn32 and
702 -mno-insn32 options.
703 (-minsn32, -mno-insn32): New options.
704 * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
705 options.
706 (MIPS assembly options): New node. Document .set insn32 and
707 .set noinsn32.
708 (MIPS-Dependent): List the new node.
709
d1706f38
NC
7102013-06-25 Nick Clifton <nickc@redhat.com>
711
712 * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
713 the PC in indirect addressing on 430xv2 parts.
714 (msp430_operands): Add version test to hardware bug encoding
715 restrictions.
716
477330fc
RM
7172013-06-24 Roland McGrath <mcgrathr@google.com>
718
d996d970
RM
719 * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
720 so it skips whitespace before it.
721 (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
722
477330fc
RM
723 * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
724 (arm_reg_parse_multi): Skip whitespace first.
725 (parse_reg_list): Likewise.
726 (parse_vfp_reg_list): Likewise.
727 (s_arm_unwind_save_mmxwcg): Likewise.
728
24382199
NC
7292013-06-24 Nick Clifton <nickc@redhat.com>
730
731 PR gas/15623
732 * config/tc-arm.c (do_t_smc): Mark as ending an IT block.
733
c3678916
RS
7342013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
735
736 * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
737
42429eac
RS
7382013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
739
740 * config/tc-mips.c: Assert that offsetT and valueT are at least
741 8 bytes in size.
742 (GPR_SMIN, GPR_SMAX): New macros.
743 (macro, mips_ip): Remove code for 4-byte valueT and offsetT.
744
f3ded42a
RS
7452013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
746
747 * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
748 conditions. Remove any code deselected by them.
749 (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
750
e8044f35
RS
7512013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
752
753 * NEWS: Note removal of ECOFF support.
754 * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
755 * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
756 (MULTI_CFILES): Remove config/e-mipsecoff.c.
757 * Makefile.in: Regenerate.
758 * configure.in: Remove MIPS ECOFF references.
759 (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
760 Delete cases.
761 (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
762 (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
763 (mips-*-*): ...this single case.
764 (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
765 MIPS emulations to be e-mipself*.
766 * configure: Regenerate.
767 * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
768 (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
769 (mips-*-sysv*): Remove coff and ecoff cases.
770 * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
771 * ecoff.c: Remove reference to MIPS ECOFF.
772 * config/e-mipsecoff.c, config/te-lnews.h: Delete files.
773 * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
774 (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
775 (mips_hi_fixup): Tweak comment.
776 (append_insn): Require a howto.
777 (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
778
98508b2a
RS
7792013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
780
781 * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
782 Use "CPU" instead of "cpu".
783 * doc/c-mips.texi: Likewise.
784 (MIPS Opts): Rename to MIPS Options.
785 (MIPS option stack): Rename to MIPS Option Stack.
786 (MIPS ASE instruction generation overrides): Rename to
787 MIPS ASE Instruction Generation Overrides (for now).
788 (MIPS floating-point): Rename to MIPS Floating-Point.
789
fc16f8cc
RS
7902013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
791
792 * doc/c-mips.texi (MIPS Macros): New section.
793 (MIPS Object): Replace with...
794 (MIPS Small Data): ...this new section.
795
5a7560b5
RS
7962013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
797
798 * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
799 Capitalize name. Use @kindex instead of @cindex for .set entries.
800
a1b86ab7
RS
8012013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
802
803 * doc/c-mips.texi (MIPS Stabs): Remove section.
804
c6278170
RS
8052013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
806
807 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
808 (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
809 (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
810 (ISA_SUPPORTS_VIRT64_ASE): Delete.
811 (mips_ase): New structure.
812 (mips_ases): New table.
813 (FP64_ASES): New macro.
814 (mips_ase_groups): New array.
815 (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
816 (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
817 functions.
818 (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
819 (md_parse_option): Use mips_ases and mips_set_ase instead of
820 separate case statements for each ASE option.
821 (mips_after_parse_args): Use FP64_ASES. Use
822 mips_check_isa_supports_ases to check the ASEs against
823 other options.
824 (s_mipsset): Use mips_ases and mips_set_ase instead of
825 separate if statements for each ASE option. Use
826 mips_check_isa_supports_ases, even when a non-ASE option
827 is specified.
828
63a4bc21
KT
8292013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
830
831 * config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
832
c31f3936
RS
8332013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
834
835 * config/tc-mips.c (md_shortopts, options, md_longopts)
836 (md_longopts_size): Move earlier in file.
837
846ef2d0
RS
8382013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
839
840 * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
841 with a single "ase" bitmask.
842 (mips_opts): Update accordingly.
843 (file_ase, file_ase_explicit): New variables.
844 (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
845 (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
846 (ISA_HAS_ROR): Adjust for mips_set_options change.
847 (is_opcode_valid): Take the base ase mask directly from mips_opts.
848 (mips_ip): Adjust for mips_set_options change.
849 (md_parse_option): Likewise. Update file_ase_explicit.
850 (mips_after_parse_args): Adjust for mips_set_options change.
851 Use bitmask operations to select the default ASEs. Set file_ase
852 rather than individual per-ASE variables.
853 (s_mipsset): Adjust for mips_set_options change.
854 (mips_elf_final_processing): Test file_ase rather than
855 file_ase_mdmx. Remove commented-out code.
856
d16afab6
RS
8572013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
858
859 * config/tc-mips.c (mips_cpu_info): Add an "ase" field.
860 (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
861 (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
862 (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
863 (mips_after_parse_args): Use the new "ase" field to choose
864 the default ASEs.
865 (mips_cpu_info_table): Move ASEs from the "flags" field to the
866 "ase" field.
867
e83a675f
RE
8682013-06-18 Richard Earnshaw <rearnsha@arm.com>
869
870 * config/tc-arm.c (symbol_preemptible): New function.
871 (relax_branch): Use it.
872
7f3c4072
CM
8732013-06-17 Catherine Moore <clm@codesourcery.com>
874 Maciej W. Rozycki <macro@codesourcery.com>
875 Chao-Ying Fu <fu@mips.com>
876
877 * config/tc-mips.c (mips_set_options): Add ase_eva.
878 (mips_set_options mips_opts): Add ase_eva.
879 (file_ase_eva): Declare.
880 (ISA_SUPPORTS_EVA_ASE): Define.
881 (IS_SEXT_9BIT_NUM): Define.
882 (MIPS_CPU_ASE_EVA): Define.
883 (is_opcode_valid): Add support for ase_eva.
884 (macro_build): Likewise.
885 (macro): Likewise.
886 (validate_mips_insn): Likewise.
887 (validate_micromips_insn): Likewise.
888 (mips_ip): Likewise.
889 (options): Add OPTION_EVA and OPTION_NO_EVA.
890 (md_longopts): Add -meva and -mno-eva.
891 (md_parse_option): Process new options.
892 (mips_after_parse_args): Check for valid EVA combinations.
893 (s_mipsset): Likewise.
894
e410add4
RS
8952013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
896
897 * dwarf2dbg.h (dwarf2_move_insn): Declare.
898 * dwarf2dbg.c (line_subseg): Add pmove_tail.
899 (get_line_subseg): Add create_p argument. Initialize pmove_tail.
900 (dwarf2_gen_line_info_1): Update call accordingly.
901 (dwarf2_move_insn): New function.
902 * config/tc-mips.c (append_insn): Use dwarf2_move_insn.
903
6a50d470
RS
9042013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
905
906 Revert:
907
908 2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
909
910 PR gas/13024
911 * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
912 (dwarf2_gen_line_info_1): Delete.
913 (dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
914 (dwarf2_gen_line_info, dwarf2_emit_label): Use them.
915 (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
916 (dwarf2_directive_loc): Push previous .locs instead of generating
917 them immediately.
918
f122319e
CF
9192013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
920
921 * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
922 (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
923
909c7f9c
NC
9242013-06-13 Nick Clifton <nickc@redhat.com>
925
926 PR gas/15602
927 * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
928 * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
929 function. Generates an error if the adjusted offset is out of a
930 16-bit range.
931
5d5755a7
SL
9322013-06-12 Sandra Loosemore <sandra@codesourcery.com>
933
934 * config/tc-nios2.c (md_apply_fix): Mask constant
935 BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
936
3bf0dbfb
MR
9372013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
938
939 * config/tc-mips.c (append_insn): Don't do branch relaxation for
940 MIPS-3D instructions either.
941 (md_convert_frag): Update the COPx branch mask accordingly.
942
943 * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
944 option.
945 * doc/as.texinfo (Overview): Add --relax-branch and
946 --no-relax-branch.
947 * doc/c-mips.texi (MIPS Opts): Document --relax-branch and
948 --no-relax-branch.
949
9daf7bab
SL
9502013-06-09 Sandra Loosemore <sandra@codesourcery.com>
951
952 * config/tc-nios2.c (nios2_parse_args): Allow trap argument to
953 omitted.
954
d301a56b
RS
9552013-06-08 Catherine Moore <clm@codesourcery.com>
956
957 * config/tc-mips.c (is_opcode_valid): Build ASE mask.
958 (is_opcode_valid_16): Pass ase value to opcode_is_member.
959 (append_insn): Change INSN_xxxx to ASE_xxxx.
960
7bab7634
DC
9612013-06-01 George Thomas <george.thomas@atmel.com>
962
cbe02d4f 963 * gas/config/tc-avr.c: Change ISA for devices with USB support to
7bab7634
DC
964 AVR_ISA_XMEGAU
965
f60cf82f
L
9662013-05-31 H.J. Lu <hongjiu.lu@intel.com>
967
968 * config/tc-i386.c (md_begin): Don't align text/data/bss sections
969 for ELF.
970
a3f278e2
CM
9712013-05-31 Paul Brook <paul@codesourcery.com>
972
a3f278e2
CM
973 * config/tc-mips.c (s_ehword): New.
974
067ec077
CM
9752013-05-30 Paul Brook <paul@codesourcery.com>
976
977 * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH.
978
d6101ac2
MR
9792013-05-29 Maciej W. Rozycki <macro@codesourcery.com>
980
981 * write.c (resolve_reloc_expr_symbols): On REL targets don't
982 convert relocs who have no relocatable field either. Rephrase
983 the conditional so that the PC-relative check is only applied
984 for REL targets.
985
f19ccbda
MR
9862013-05-28 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
987
988 * config/tc-mips.c (macro) <ld>: Don't use $zero for address
989 calculation.
990
418009c2
YZ
9912013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
992
993 * config/tc-aarch64.c (reloc_table): Update to use
477330fc 994 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
418009c2
YZ
995 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
996 (md_apply_fix): Likewise.
997 (aarch64_force_relocation): Likewise.
998
0a8897c7
KT
9992013-05-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1000
1001 * config/tc-arm.c (it_fsm_post_encode): Improve
1002 warning messages about deprecated IT block formats.
1003
89d2a2a3
MS
10042013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
1005
1006 * config/tc-aarch64.c (md_apply_fix): Move value range checking
1007 inside fx_done condition.
1008
c77c0862
RS
10092013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
1010
1011 * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
1012
c0637f3a
PB
10132013-05-20 Peter Bergner <bergner@vnet.ibm.com>
1014
1015 * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
1016 and clean up warning when using PRINT_OPCODE_TABLE.
1017
5656a981
AM
10182013-05-20 Alan Modra <amodra@gmail.com>
1019
1020 * config/tc-ppc.c (md_apply_fix): Hoist code common to insn
1021 and data fixups performing shift/high adjust/sign extension on
1022 fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
1023 when writing data fixups rather than recalculating size.
1024
997b26e8
JBG
10252013-05-16 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1026
1027 * doc/c-msp430.texi: Fix typo.
1028
9f6e76f4
TG
10292013-05-16 Tristan Gingold <gingold@adacore.com>
1030
1031 * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC
1032 are also TOC symbols.
1033
638d3803
NC
10342013-05-16 Nick Clifton <nickc@redhat.com>
1035
1036 * config/tc-msp430.c: Make -mmcu recognise more part numbers.
1037 Add -mcpu command to specify core type.
997b26e8 1038 * doc/c-msp430.texi: Update documentation.
638d3803 1039
b015e599
AP
10402013-05-09 Andrew Pinski <apinski@cavium.com>
1041
1042 * config/tc-mips.c (struct mips_set_options): New ase_virt field.
1043 (mips_opts): Update for the new field.
1044 (file_ase_virt): New variable.
1045 (ISA_SUPPORTS_VIRT_ASE): New macro.
1046 (ISA_SUPPORTS_VIRT64_ASE): New macro.
1047 (MIPS_CPU_ASE_VIRT): New define.
1048 (is_opcode_valid): Handle ase_virt.
1049 (macro_build): Handle "+J".
1050 (validate_mips_insn): Likewise.
1051 (mips_ip): Likewise.
1052 (enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
1053 (md_longopts): Add mvirt and mnovirt
1054 (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
1055 (mips_after_parse_args): Handle ase_virt field.
1056 (s_mipsset): Handle "virt" and "novirt".
1057 (mips_elf_final_processing): Add a comment about virt ASE might need
1058 a new flag.
1059 (md_show_usage): Print out the usage of -mvirt and mno-virt options.
1060 * doc/c-mips.texi: Document -mvirt and -mno-virt.
1061 Document ".set virt" and ".set novirt".
1062
da8094d7
AM
10632013-05-09 Alan Modra <amodra@gmail.com>
1064
1065 * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under
1066 control of operand flag bits.
1067
c5f8c205
AM
10682013-05-07 Alan Modra <amodra@gmail.com>
1069
1070 * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro.
1071 (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
1072 (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
1073 (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
1074 (md_apply_fix): Set fx_no_overflow for assorted relocations.
1075 Shift and sign-extend fieldval for use by some VLE reloc
1076 operand->insert functions.
1077
b47468a6
CM
10782013-05-06 Paul Brook <paul@codesourcery.com>
1079 Catherine Moore <clm@codesourcery.com>
1080
c5f8c205
AM
1081 * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL.
1082 (limited_pcrel_reloc_p): Likewise.
b47468a6
CM
1083 (md_apply_fix): Likewise.
1084 (tc_gen_reloc): Likewise.
1085
2de39019
CM
10862013-05-06 Richard Sandiford <rdsandiford@googlemail.com>
1087
1088 * config/tc-mips.c (limited_pcrel_reloc_p): New function.
1089 (mips_fix_adjustable): Adjust pc-relative check to use
1090 limited_pc_reloc_p.
1091
754e2bb9
RS
10922013-05-02 Richard Sandiford <rdsandiford@googlemail.com>
1093
1094 * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
1095 (s_mips_stab): Do not restrict to stabn only.
1096
13761a11
NC
10972013-05-02 Nick Clifton <nickc@redhat.com>
1098
1099 * config/tc-msp430.c: Add support for the MSP430X architecture.
1100 Add code to insert a NOP instruction after any instruction that
1101 might change the interrupt state.
1102 Add support for the LARGE memory model.
1103 Add code to initialise the .MSP430.attributes section.
1104 * config/tc-msp430.h: Add support for the MSP430X architecture.
1105 * doc/c-msp430.texi: Document the new -mL and -mN command line
1106 options.
1107 * NEWS: Mention support for the MSP430X architecture.
1108
df26367c
MR
11092013-05-01 Maciej W. Rozycki <macro@codesourcery.com>
1110
1111 * configure.tgt: Replace alpha*-*-linuxecoff* pattern with
1112 alpha*-*-linux*ecoff*.
1113
f02d8318
CF
11142013-04-30 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
1115
1116 * config/tc-mips.c (mips_ip): Add sizelo.
1117 For "+C", "+G", and "+H", set sizelo and compare against it.
1118
b40bf0a2
NC
11192013-04-29 Nick Clifton <nickc@redhat.com>
1120
1121 * as.c (Options): Add -gdwarf-sections.
1122 (parse_args): Likewise.
1123 * as.h (flag_dwarf_sections): Declare.
1124 * dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes.
1125 (process_entries): When -gdwarf-sections is enabled generate
1126 fragmentary .debug_line sections.
1127 (out_debug_line): Set the section for the .debug_line section end
1128 symbol.
1129 * doc/as.texinfo: Document -gdwarf-sections.
1130 * NEWS: Mention -gdwarf-sections.
1131
8eeccb77 11322013-04-26 Christian Groessler <chris@groessler.org>
00a3147e
CG
1133
1134 * config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline
1135 according to the target parameter. Don't call s_segm since s_segm
1136 calls bfd_set_arch_mach using stdoutput, but stdoutput isn't
1137 initialized yet.
1138 (md_begin): Call s_segm according to target parameter from command
1139 line.
1140
49926cd0
AM
11412013-04-25 Alan Modra <amodra@gmail.com>
1142
1143 * configure.in: Allow little-endian linux.
1144 * configure: Regenerate.
1145
e3031850
SL
11462013-04-24 Sandra Loosemore <sandra@codesourcery.com>
1147
1148 * config/tc-nios2.c (nios2_control_register_arg_p): Rename
1149 "fstatus" control register to "eccinj".
1150
cb948fc0
KT
11512013-04-19 Kai Tietz <ktietz@redhat.com>
1152
1153 * configure.tgt (i386-*-cygwin): Handle x86_64 cygwin.
1154
4455e9ad
JB
11552013-04-15 Julian Brown <julian@codesourcery.com>
1156
1157 * expr.c (add_to_result, subtract_from_result): Make global.
1158 * expr.h (add_to_result, subtract_from_result): Add prototypes.
1159 * config/tc-sh.c (sh_optimize_expr): Use add_to_result,
1160 subtract_from_result to handle extra bit of precision for .sleb128
1161 directive operands.
1162
956a6ba3
JB
11632013-04-10 Julian Brown <julian@codesourcery.com>
1164
1165 * read.c (convert_to_bignum): Add sign parameter. Use it
1166 instead of X_unsigned to determine sign of resulting bignum.
1167 (emit_expr): Pass extra argument to convert_to_bignum.
1168 (emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass
1169 X_extrabit to convert_to_bignum.
1170 (parse_bitfield_cons): Set X_extrabit.
1171 * expr.c (make_expr_symbol, expr_build_uconstant, operand):
1172 Initialise X_extrabit field as appropriate.
1173 (add_to_result): New.
1174 (subtract_from_result): New.
1175 (expr): Use above.
1176 * expr.h (expressionS): Add X_extrabit field.
1177
eb9f3f00
JB
11782013-04-10 Jan Beulich <jbeulich@suse.com>
1179
1180 * gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
1181 register being PC when is_t or writeback, and use distinct
1182 diagnostic for the latter case.
1183
ccb84d65
JB
11842013-04-10 Jan Beulich <jbeulich@suse.com>
1185
1186 * gas/config/tc-arm.c (parse_operands): Re-write
1187 po_barrier_or_imm().
1188 (do_barrier): Remove bogus constraint().
1189 (do_t_barrier): Remove.
1190
4d13caa0
NC
11912013-04-09 Joerg Wunsch <joerg.wunsch@atmel.com>
1192
1193 * gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2,
1194 ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2,
1195 ATmega2564RFR2
1196 * gas/doc/c-avr.texi (-mmcu documentation): Likewise.
1197
16d02dc9
JB
11982013-04-09 Jan Beulich <jbeulich@suse.com>
1199
1200 * gas/config/tc-arm.c (do_vmrs): Accept all control registers.
1201 Use local variable Rt in more places.
1202 (do_vmsr): Accept all control registers.
1203
05ac0ffb
JB
12042013-04-09 Jan Beulich <jbeulich@suse.com>
1205
1206 * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
1207 if there was none specified for moves between scalar and core
1208 register.
1209
2d51fb74
JB
12102013-04-09 Jan Beulich <jbeulich@suse.com>
1211
1212 * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
1213 NEON_ALL_LANES case.
1214
94dcf8bf
JB
12152013-04-08 Jan Beulich <jbeulich@suse.com>
1216
1217 * gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for
1218 PC-relative VSTR.
1219
1472d06f
JB
12202013-04-08 Jan Beulich <jbeulich@suse.com>
1221
1222 * gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq
1223 entry to sp_fiq.
1224
0c76cae8
AM
12252013-04-03 Alan Modra <amodra@gmail.com>
1226
1227 * doc/as.texinfo: Add support to generate man options for h8300.
1228 * doc/c-h8300.texi: Likewise.
1229
92eb40d9
RR
12302013-03-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1231
1232 * config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and
1233 Cortex-A57.
1234
51dcdd4d
NC
12352013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1236
1237 PR binutils/15068
1238 * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
1239
c5d685bf
NC
12402013-03-26 Nick Clifton <nickc@redhat.com>
1241
9b978282
NC
1242 PR gas/15295
1243 * listing.c (rebuffer_line): Rewrite to avoid seeking back to the
1244 start of the file each time.
1245
c5d685bf
NC
1246 PR gas/15178
1247 * config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for
1248 FreeBSD targets.
1249
9699c833
TG
12502013-03-26 Douglas B Rupp <rupp@gnat.com>
1251
1252 * config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
1253 after fixup.
1254
4755303e
WN
12552013-03-21 Will Newton <will.newton@linaro.org>
1256
1257 * config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
1258 pc-relative str instructions in Thumb mode.
1259
81f5558e
NC
12602013-03-21 Michael Schewe <michael.schewe@gmx.net>
1261
1262 * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov
1263 @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc
1264 R_H8_DISP32A16.
1265 * config/tc-h8300.h: Remove duplicated defines.
1266
71863e73
NC
12672013-03-21 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
1268
1269 PR gas/15282
1270 * tc-avr.c (mcu_has_3_byte_pc): New function.
1271 (tc_cfi_frame_initial_instructions): Call it to find return
1272 address size.
1273
795b8e6b
NC
12742013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1275
1276 PR gas/15095
1277 * config/tc-tic6x.c (tic6x_try_encode): Handle
1278 tic6x_coding_dreg_(msb|lsb) field coding types and use it to
1279 encode register pair numbers when required.
1280
ba86b375
WN
12812013-03-15 Will Newton <will.newton@linaro.org>
1282
1283 * config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register
1284 in vstr in Thumb mode for pre-ARMv7 cores.
1285
9e6f3811
AS
12862013-03-14 Andreas Schwab <schwab@suse.de>
1287
1288 * doc/c-arc.texi (ARC Directives): Revert last change and use
1289 @itemize instead of @table.
1290 * doc/c-arm.texi (ARM-Instruction-Set): Likewise.
1291
b10bf8c5
NC
12922013-03-14 Nick Clifton <nickc@redhat.com>
1293
1294 PR gas/15273
1295 * config/tc-arm.c (do_co_reg): Do not call check_obsolete with a
1296 NULL message, instead just check ARM_CPU_IS_ANY directly.
1297
ba724cfc
NC
12982013-03-14 Nick Clifton <nickc@redhat.com>
1299
1300 PR gas/15212
9e6f3811 1301 * doc/c-arc.texi (ARC Directives): Use @code instead of @bullet
ba724cfc
NC
1302 for table format.
1303 * doc/c-arm.texi (ARM-Instruction-Set): Likewise. Also add text
1304 to the @item directives.
1305 (ARM-Neon-Alignment): Move to correct place in the document.
1306 * doc/c-cr16.texi (CR16 Operand Qualifiers): Fix up table
1307 formatting.
1308 * doc/c-tic54x.texi (TIC54X-Subsyms): Correct use of
1309 @smallexample.
1310
531a94fd
SL
13112013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de>
1312
1313 * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o'
1314 case. Add default BAD_CASE to switch.
1315
dad60f8e
SL
13162013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1317
1318 * config/tc-nios2.c (nios2_assemble_args_ds): New function.
1319 (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries.
1320
dd5181d5
KT
13212013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1322
1323 * config/tc-arm.c (crc_ext_armv8): New feature set.
1324 (UNPRED_REG): New macro.
1325 (do_crc32_1): New function.
1326 (do_crc32b, do_crc32h, do_crc32w, do_crc32cb,
1327 do_crc32ch, do_crc32cw): Likewise.
1328 (TUEc): New macro.
1329 (insns): Add entries for crc32 mnemonics.
1330 (arm_extensions): Add entry for crc.
1331
8e723a10
CLT
13322013-03-08 Chung-Lin Tang <cltang@codesourcery.com>
1333
1334 * write.h (struct fix): Add fx_dot_frag field.
1335 (dot_frag): Declare.
1336 * write.c (dot_frag): New variable.
1337 (fix_new_internal): Set fx_dot_frag field with dot_frag.
1338 (fixup_segment): Base calculation of fx_offset with fx_dot_frag.
1339 * expr.c (expr): Save value of frag_now in dot_frag when setting
1340 dot_value.
1341 * read.c (emit_expr): Likewise. Delete comments.
1342
be05d201
L
13432013-03-07 H.J. Lu <hongjiu.lu@intel.com>
1344
1345 * config/tc-i386.c (flag_code_names): Removed.
1346 (i386_index_check): Rewrote.
1347
62b0d0d5
YZ
13482013-03-05 Yufeng Zhang <yufeng.zhang@arm.com>
1349
1350 * config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern';
1351 add comment.
1352 (aarch64_double_precision_fmovable): New function.
1353 (parse_aarch64_imm_float): Add parameter 'dp_p'; call the new
1354 function; handle hexadecimal representation of IEEE754 encoding.
1355 (parse_operands): Update the call to parse_aarch64_imm_float.
1356
165de32a
L
13572013-02-28 H.J. Lu <hongjiu.lu@intel.com>
1358
1359 * config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix.
1360 (check_hle): Updated.
1361 (md_assemble): Likewise.
1362 (parse_insn): Likewise.
1363
d5de92cf
L
13642013-02-28 H.J. Lu <hongjiu.lu@intel.com>
1365
1366 * config/tc-i386.c (_i386_insn): Add rep_prefix.
9e6f3811 1367 (md_assemble): Check if REP prefix is OK.
d5de92cf
L
1368 (parse_insn): Remove expecting_string_instruction. Set
1369 i.rep_prefix.
1370
e60bb1dd
YZ
13712013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1372
1373 * config/tc-aarch64.c (aarch64_features): Add the 'crc' option.
1374
aeebdd9b
YZ
13752013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1376
1377 * config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
1378 for system registers.
1379
4107ae22
DD
13802013-02-27 DJ Delorie <dj@redhat.com>
1381
1382 * config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE.
1383 (rl78_op): Handle %code().
1384 (rl78_cons_fix_new): Likewise, but ignore for 20-bit operands.
1385 (tc_gen_reloc): Likwise; convert to a computed reloc.
1386 (md_apply_fix): Likewise.
1387
151fa98f
NC
13882013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1389
1390 * config/rl78-parse.y: Fix encoding of DIVWU insn.
1391
70a8bc5b 13922013-02-25 Terry Guo <terry.guo@arm.com>
1393
1394 * config/tc-arm.c (arm_cpus): Add cortex-r7 entry.
1395 * doc/c-arm.texi: Add cortex-r7 and missing cortex-r5 to
1396 list of accepted CPUs.
1397
5c111e37
L
13982013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1399
1400 PR gas/15159
1401 * config/tc-i386.c (cpu_arch): Add ".smap".
1402
1403 * doc/c-i386.texi: Document smap.
1404
8a75745d
MR
14052013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
1406
1407 * config/tc-mips.c (s_cpload): Call mips_mark_labels and set
1408 mips_assembling_insn appropriately.
1409 (s_cpsetup, s_cprestore, s_cpreturn, s_cpadd): Likewise.
1410
79850f26
MR
14112013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
1412
cf29fc61 1413 * config/tc-mips.c (append_insn): Correct indentation, remove
79850f26
MR
1414 extraneous braces.
1415
4c261dff
NC
14162013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1417
5c111e37 1418 * config/tc-arm.c (do_neon_mov): Break on NS_NULL.
4c261dff 1419
ea33f281
NC
14202013-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
1421
1422 * configure.tgt: Add nios2-*-rtems*.
1423
a1ccaec9
YZ
14242013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1425
1426 * config/tc-aarch64.c (md_begin): Change to check if 'name' is
1427 NULL.
1428
0aa27725
RS
14292013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1430
1431 * config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
1432 (macro): Use it. Assert that trunc.w.s is not used for r5900.
1433
da4339ed
NC
14342013-02-08 Yi-Hsiu, Hsu <ahsu@marvell.com>
1435
1436 * gas/config/tc-arm.c (arm_cpus): Add support for mcpu=marvell-pj4
1437 core.
1438
36591ba1 14392013-02-06 Sandra Loosemore <sandra@codesourcery.com>
5c111e37 1440 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL
1441
1442 Based on patches from Altera Corporation.
1443
1444 * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c.
1445 (TARGET_CPU_HFILES): Add config/tc-nios2.h.
1446 * Makefile.in: Regenerated.
1447 * configure.tgt: Add case for nios2*-linux*.
1448 * config/obj-elf.c: Conditionally include elf/nios2.h.
1449 * config/tc-nios2.c: New file.
1450 * config/tc-nios2.h: New file.
1451 * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi.
1452 * doc/Makefile.in: Regenerated.
1453 * doc/all.texi: Set NIOSII.
1454 * doc/as.texinfo (Overview): Add Nios II options.
1455 (Machine Dependencies): Include c-nios2.texi.
1456 * doc/c-nios2.texi: New file.
1457 * NEWS: Note Altera Nios II support.
1458
94d4433a
AM
14592013-02-06 Alan Modra <amodra@gmail.com>
1460
1461 PR gas/14255
1462 * config/tc-avr.h (TC_VALIDATE_FIX): Mark symbol used by reloc.
1463 Don't skip fixups with fx_subsy non-NULL.
1464 * config/tc-avr.c (tc_gen_reloc): Don't specially handle fixups
1465 with fx_subsy non-NULL.
1466
ace9af6f
L
14672013-02-04 H.J. Lu <hongjiu.lu@intel.com>
1468
1469 * doc/c-metag.texi: Add "@c man" markers.
1470
89d67ed9
AM
14712013-02-04 Alan Modra <amodra@gmail.com>
1472
1473 * write.c (fixup_segment): Return void. Delete seg_reloc_count
1474 related code.
1475 (TC_ADJUST_RELOC_COUNT): Delete.
1476 * config/tc-i960.h (TC_ADJUST_RELOC_COUNT): Delete.
1477
89072bd6
AM
14782013-02-04 Alan Modra <amodra@gmail.com>
1479
1480 * po/POTFILES.in: Regenerate.
1481
f9b2d544
NC
14822013-01-30 Markos Chandras <markos.chandras@imgtec.com>
1483
1484 * config/tc-metag.c: Make SWAP instruction less permissive with
1485 its operands.
1486
392ca752
DD
14872013-01-29 DJ Delorie <dj@redhat.com>
1488
1489 * config/tc-rl78.c (rl78_cons_fix_new): Handle user-specified
1490 relocs in .word/.etc statements.
1491
427d0db6
RM
14922013-01-29 Roland McGrath <mcgrathr@google.com>
1493
1494 * config/tc-arm.c (md_apply_fix): Use as_bad_where for "bad
1495 immediate value for 8-bit offset" error so it shows line info.
1496
4faf939a
JM
14972013-01-24 Joseph Myers <joseph@codesourcery.com>
1498
1499 * config/tc-ppc.c (md_assemble): Do not generate APUinfo sections
1500 for 64-bit output.
1501
78c8d46c
NC
15022013-01-24 Nick Clifton <nickc@redhat.com>
1503
1504 * config/tc-v850.c: Add support for e3v5 architecture.
1505 * doc/c-v850.texi: Mention new support.
1506
fb5b7503
NC
15072013-01-23 Nick Clifton <nickc@redhat.com>
1508
1509 PR gas/15039
1510 * config/tc-avr.c: Include dwarf2dbg.h.
1511
8ce3d284
L
15122013-01-18 H.J. Lu <hongjiu.lu@intel.com>
1513
1514 * config/tc-i386.c (reloc): Support size relocation only for ELF.
1515 (tc_i386_fix_adjustable): Likewise.
1516 (lex_got): Likewise.
1517 (tc_gen_reloc): Likewise.
1518
f5555712
YZ
15192013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1520
1521 * config/tc-aarch64.c (output_operand_error_record): Change to output
1522 the out-of-range error message as value-expected message if there is
1523 only one single value in the expected range.
1524 (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
1525 LSL #0 as a programmer-friendly feature.
1526
8fd4256d
L
15272013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1528
1529 * config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32.
1530 (tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and
1531 BFD_RELOC_64_SIZE relocations.
1532 (lex_got): Support "symbol@SIZE" and don't create GOT symbol
1533 for it.
1534 (tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64
1535 relocations against local symbols.
1536
a5840dce
AM
15372013-01-16 Alan Modra <amodra@gmail.com>
1538
1539 * config/tc-ppc.c (md_assemble <TE_PE>): Ignore line after
1540 finding some sort of toc syntax error, and break to avoid
1541 compiler uninit warning.
1542
af89796a
L
15432013-01-15 H.J. Lu <hongjiu.lu@intel.com>
1544
1545 PR gas/15019
1546 * config/tc-i386.c (lex_got): Increment length by 1 if the
1547 relocation token is removed.
1548
dd42f060
NC
15492013-01-15 Nick Clifton <nickc@redhat.com>
1550
1551 * config/tc-v850.c (md_assemble): Allow signed values for
1552 V850E_IMMEDIATE.
1553
464e3686
SK
15542013-01-11 Sean Keys <skeys@ipdatasys.com>
1555
1556 * config/tc-xgate.c (md_begin): Fix mistake made when going from
af89796a 1557 git to cvs.
464e3686 1558
5817ffd1
PB
15592013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1560
1561 * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
1562 * doc/c-ppc.texi (PowerPC-Opts): Likewise.
1563 * config/tc-ppc.c (md_show_usage): Likewise.
1564 (ppc_handle_align): Handle power8's group ending nop.
1565
f4b1f6a9
SK
15662013-01-10 Sean Keys <skeys@ipdatasys.com>
1567
1568 * config/tc-xgate.c (md_begin): Fix the printing of opcodes so
af89796a 1569 that the assember exits after the opcodes have been printed.
f4b1f6a9 1570
34bca508
L
15712013-01-10 H.J. Lu <hongjiu.lu@intel.com>
1572
1573 * app.c: Remove trailing white spaces.
1574 * as.c: Likewise.
1575 * as.h: Likewise.
1576 * cond.c: Likewise.
1577 * dw2gencfi.c: Likewise.
1578 * dwarf2dbg.h: Likewise.
1579 * ecoff.c: Likewise.
1580 * input-file.c: Likewise.
1581 * itbl-lex.h: Likewise.
1582 * output-file.c: Likewise.
1583 * read.c: Likewise.
1584 * sb.c: Likewise.
1585 * subsegs.c: Likewise.
1586 * symbols.c: Likewise.
1587 * write.c: Likewise.
1588 * config/tc-i386.c: Likewise.
1589 * doc/Makefile.am: Likewise.
1590 * doc/Makefile.in: Likewise.
1591 * doc/c-aarch64.texi: Likewise.
1592 * doc/c-alpha.texi: Likewise.
1593 * doc/c-arc.texi: Likewise.
1594 * doc/c-arm.texi: Likewise.
1595 * doc/c-avr.texi: Likewise.
1596 * doc/c-bfin.texi: Likewise.
1597 * doc/c-cr16.texi: Likewise.
1598 * doc/c-d10v.texi: Likewise.
1599 * doc/c-d30v.texi: Likewise.
1600 * doc/c-h8300.texi: Likewise.
1601 * doc/c-hppa.texi: Likewise.
1602 * doc/c-i370.texi: Likewise.
1603 * doc/c-i386.texi: Likewise.
1604 * doc/c-i860.texi: Likewise.
1605 * doc/c-m32c.texi: Likewise.
1606 * doc/c-m32r.texi: Likewise.
1607 * doc/c-m68hc11.texi: Likewise.
1608 * doc/c-m68k.texi: Likewise.
1609 * doc/c-microblaze.texi: Likewise.
1610 * doc/c-mips.texi: Likewise.
1611 * doc/c-msp430.texi: Likewise.
1612 * doc/c-mt.texi: Likewise.
1613 * doc/c-s390.texi: Likewise.
1614 * doc/c-score.texi: Likewise.
1615 * doc/c-sh.texi: Likewise.
1616 * doc/c-sh64.texi: Likewise.
1617 * doc/c-tic54x.texi: Likewise.
1618 * doc/c-tic6x.texi: Likewise.
1619 * doc/c-v850.texi: Likewise.
1620 * doc/c-xc16x.texi: Likewise.
1621 * doc/c-xgate.texi: Likewise.
1622 * doc/c-xtensa.texi: Likewise.
1623 * doc/c-z80.texi: Likewise.
1624 * doc/internals.texi: Likewise.
1625
4c665b71
RM
16262013-01-10 Roland McGrath <mcgrathr@google.com>
1627
1628 * hash.c (hash_new_sized): Make it global.
1629 * hash.h: Declare it.
1630 * macro.c (define_macro): Use hash_new_sized instead of hash_new,
1631 pass a small size.
1632
a3c62988
NC
16332013-01-10 Will Newton <will.newton@imgtec.com>
1634
1635 * Makefile.am: Add Meta.
1636 * Makefile.in: Regenerate.
1637 * config/tc-metag.c: New file.
1638 * config/tc-metag.h: New file.
1639 * configure.tgt: Add Meta.
1640 * doc/Makefile.am: Add Meta.
1641 * doc/Makefile.in: Regenerate.
1642 * doc/all.texi: Add Meta.
1643 * doc/as.texiinfo: Document Meta options.
1644 * doc/c-metag.texi: New file.
1645
b37df7c4
SE
16462013-01-09 Steve Ellcey <sellcey@mips.com>
1647
1648 * config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal
1649 calls.
1650 * config/tc-mips.c (internalError): Remove, replace with abort.
1651
a3251895
YZ
16522013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
1653
1654 * config/tc-aarch64.c (parse_operands): Change to compare the result
1655 of function call 'parse_sys_reg' with 'PARSE_FAIL' instead of 'FALSE'.
1656
8ab8155f
NC
16572013-01-07 Nick Clifton <nickc@redhat.com>
1658
1659 PR gas/14887
1660 * config/tc-arm.c (skip_past_char): Skip whitespace before the
1661 anticipated character.
1662 * config/tc-arm.c (parse_address_main): Delete skip of whitespace
1663 here as it is no longer needed.
1664
a4ac1c42
AS
16652013-01-06 Andreas Schwab <schwab@linux-m68k.org>
1666
1667 * doc/c-mips.texi (MIPS Opts): Fix use of @itemx.
1668 * doc/c-score.texi (SCORE-Opts): Likewise.
1669 * doc/c-tic54x.texi (TIC54X-Directives): Likewise.
1670
e407c74b
NC
16712013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1672
1673 * config/tc-mips.c: Add support for MIPS r5900.
1674 Add M_LQ_AB and M_SQ_AB to support large values for instructions
1675 lq and sq.
1676 (can_swap_branch_p, get_append_method): Detect some conditional
1677 short loops to fix a bug on the r5900 by NOP in the branch delay
1678 slot.
1679 (M_MUL): Support 3 operands in multu on r5900.
1680 (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
1681 (s_mipsset): Force 32 bit floating point on r5900.
1682 (mips_ip): Check parameter range of instructions mfps and mtps on
1683 r5900.
1684 * configure.in: Detect CPU type when target string contains r5900
1685 (e.g. mips64r5900el-linux-gnu).
1686
62658407
L
16872013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1688
1689 * as.c (parse_args): Update copyright year to 2013.
1690
95830fd1
YZ
16912013-01-02 Yufeng Zhang <yufeng.zhang@arm.com>
1692
1693 * config/tc-aarch64.c (aarch64_cpus): Add entries for "cortex-a53"
1694 and "cortex57".
1695
517bb291 16962013-01-02 Nick Clifton <nickc@redhat.com>
d709e4e6 1697
517bb291
NC
1698 PR gas/14987
1699 * config/tc-arm.c (parse_address_main): Skip whitespace before a
1700 closing bracket.
d709e4e6 1701
517bb291 1702For older changes see ChangeLog-2012
08d56133 1703\f
517bb291 1704Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC
1705
1706Copying and distribution of this file, with or without modification,
1707are permitted in any medium without royalty provided the copyright
1708notice and this notice are preserved.
1709
08d56133
NC
1710Local Variables:
1711mode: change-log
1712left-margin: 8
1713fill-column: 74
1714version-control: never
1715End: