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12013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * config/tc-mips.c (imm_expr): Expand comment.
4 (set_at, macro, mips16_macro): Expect imm_expr to be O_constant
5 when populated.
6
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72013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
8
9 * config/tc-mips.c (imm2_expr): Delete.
10 (md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly.
11
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122013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
13
14 * config/tc-mips.c (report_bad_range, report_bad_field): Delete.
15 (macro): Remove M_DEXT and M_DINS handling.
16
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172013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
18
19 * config/tc-mips.c (mips_arg_info): Replace allow_nonconst and
20 lax_max with lax_match.
21 (match_int_operand): Update accordingly. Don't report an error
22 for !lax_match-only cases.
23 (match_insn): Replace more_alts with lax_match and use it to
24 initialize the mips_arg_info field. Add a complete_p parameter.
25 Handle implicit VU0 suffixes here.
26 (match_invalid_for_isa, match_insns, match_mips16_insns): New
27 functions.
28 (mips_ip, mips16_ip): Use them.
29
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302013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
31
32 * config/tc-mips.c (match_expression): Report uses of registers here.
33 Add a "must be an immediate expression" error. Handle elided offsets
34 here rather than...
35 (match_int_operand): ...here.
36
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372013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
38
39 * config/tc-mips.c (mips_arg_info): Remove soft_match.
40 (match_out_of_range, match_not_constant): New functions.
41 (match_const_int): Remove fallback parameter and check for soft_match.
42 Use match_not_constant.
43 (match_mapped_int_operand, match_addiusp_operand)
44 (match_perf_reg_operand, match_save_restore_list_operand)
45 (match_mdmx_imm_reg_operand): Update accordingly. Use
46 match_out_of_range and set_insn_error* instead of as_bad.
47 (match_int_operand): Likewise. Use match_not_constant in the
48 !allows_nonconst case.
49 (match_float_constant): Report invalid float constants.
50 (match_insn, match_mips16_insn): Remove soft_match code. Rely on
51 match_float_constant to check for invalid constants. Fail the
52 match if match_const_int or match_float_constant return false.
53 (mips_ip): Update accordingly.
54 (mips16_ip): Likewise. Undo null termination of instruction name
55 once lookup is complete.
56
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572013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
58
59 * config/tc-mips.c (mips_insn_error_format): New enum.
60 (mips_insn_error): New struct.
61 (insn_error): Change to a mips_insn_error.
62 (clear_insn_error, set_insn_error_format, set_insn_error)
63 (set_insn_error_i, set_insn_error_ss, report_insn_error): New
64 functions.
65 (mips_parse_argument_token, md_assemble, match_insn)
66 (match_mips16_insn): Use them instead of manipulating insn_error
67 directly.
68 (mips_ip, mips16_ip): Likewise. Simplify control flow.
69
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702013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
71
72 * config/tc-mips.c (normalize_constant_expr): Move further up file.
73 (normalize_address_expr): Likewise.
74 (match_insn, match_mips16_insn): New functions, split out from...
75 (mips_ip, mips16_ip): ...here.
76
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772013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
78
79 * config/tc-mips.c (operand_reg_mask, match_operand): Handle
80 OP_OPTIONAL_REG.
81 (mips_ip, mips16_ip): Use mips_optional_operand_p to check
82 for optional operands.
83
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842013-08-16 Alan Modra <amodra@gmail.com>
85
86 * config/tc-ppc.c (ppc_elf_cons): Allow @l and other reloc
87 modifiers generally.
88
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892013-08-16 Alan Modra <amodra@gmail.com>
90
91 * config/tc-ppc.c (ppc_elf_lcomm): Use subsection 1.
92
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932013-08-14 David Edelsohn <dje.gcc@gmail.com>
94
95 * config/tc-ppc.c (ppc_comm): Accept optional fourth .lcomm
96 argument as alignment.
97
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982013-08-09 Nick Clifton <nickc@redhat.com>
99
100 * config/tc-rl78.c (elf_flags): New variable.
101 (enum options): Add OPTION_G10.
102 (md_longopts): Add mg10.
103 (md_parse_option): Parse -mg10.
104 (rl78_elf_final_processing): New function.
105 * config/tc-rl78.c (tc_final_processing): Define.
106 * doc/c-rl78.texi: Document -mg10 option.
107
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1082013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
109
110 * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
111 suffixes to be elided too.
112 (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
113 (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N
114 to be omitted too.
115
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1162013-08-05 John Tytgat <john@bass-software.com>
117
118 * po/POTFILES.in: Regenerate.
119
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1202013-08-05 Eric Botcazou <ebotcazou@adacore.com>
121 Konrad Eisele <konrad@gaisler.com>
122
123 * config/tc-sparc.c (sparc_arch_types): Add leon.
124 (sparc_arch): Move sparc4 around and add leon.
125 (sparc_target_format): Document -Aleon.
126 * doc/c-sparc.texi: Likewise.
127
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1282013-08-05 Richard Sandiford <rdsandiford@googlemail.com>
129
130 * config/tc-mips.c (mips_lookup_insn): Make length and opend signed.
131
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1322013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
133 Richard Sandiford <rdsandiford@googlemail.com>
134
135 * config/tc-mips.c (MAX_OPERANDS): Bump to 6.
136 (RWARN): Bump to 0x8000000.
137 (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
138 (RTYPE_R5900_ACC): New register types.
139 (RTYPE_MASK): Include them.
140 (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
141 macros.
142 (reg_names): Include them.
143 (mips_parse_register_1): New function, split out from...
144 (mips_parse_register): ...here. Add a channels_ptr parameter.
145 Look for VU0 channel suffixes when nonnull.
146 (reg_lookup): Update the call to mips_parse_register.
147 (mips_parse_vu0_channels): New function.
148 (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
149 (mips_operand_token): Add a "channels" field to the union.
150 Extend the comment above "ch" to OT_DOUBLE_CHAR.
151 (mips_parse_base_start): Match -- and ++. Handle channel suffixes.
152 (mips_parse_argument_token): Handle channel suffixes here too.
153 (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
154 Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
155 Handle '#' formats.
156 (md_begin): Register $vfN and $vfI registers.
157 (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
158 (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
159 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
160 (match_vu0_suffix_operand): New function.
161 (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
162 (macro): Use "+7" rather than "E" for LDQ2 and STQ2.
163 (mips_lookup_insn): New function.
164 (mips_ip): Use it. Allow "+K" operands to be elided at the end
165 of an instruction. Handle '#' sequences.
166
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1672013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
168
169 * config/tc-mips.c (macro, mips16_macro): Create an array of operand
170 values and use it instead of sreg, treg, xreg, etc.
171
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1722013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
173
174 * config/tc-mips.c (match_int_operand): Use mips_int_operand_min
175 and mips_int_operand_max.
176 (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
177 Delete.
178 (mips16_immed_operand, mips16_immed_in_range_p): New functions.
179 (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
180 instead of mips16_immed_operand.
181
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1822013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
183
184 * config/tc-mips.c (mips16_macro): Don't use move_register.
185 (mips16_ip): Allow macros to use 'p'.
186
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1872013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
188
189 * config/tc-mips.c (MAX_OPERANDS): New macro.
190 (mips_operand_array): New structure.
191 (mips_operands, mips16_operands, micromips_operands): New arrays.
192 (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
193 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
194 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
195 (micromips_to_32_reg_q_map): Delete.
196 (insn_operands, insn_opno, insn_extract_operand): New functions.
197 (validate_mips_insn): Take a mips_operand_array as argument and
198 use it to build up a list of operands. Extend to handle INSN_MACRO
199 and MIPS16.
200 (validate_mips16_insn): New function.
201 (validate_micromips_insn): Take a mips_operand_array as argument.
202 Handle INSN_MACRO.
203 (md_begin): Initialize mips_operands, mips16_operands and
204 micromips_operands. Call validate_mips_insn and
205 validate_micromips_insn for macro instructions too.
206 Call validate_mips16_insn for MIPS16 instructions.
207 (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
208 New functions.
209 (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
210 them. Handle INSN_UDI.
211 (get_append_method): Use gpr_read_mask.
212
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2132013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
214
215 * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
216 flags for MIPS16 and non-MIPS16 instructions.
217 (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
218 (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
219 (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
220 (can_swap_branch_p, get_append_method): Use the same flags for MIPS16
221 and non-MIPS16 instructions. Fix formatting.
222
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2232013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
224
225 * config/tc-mips.c (reg_needs_delay): Move later in file.
226 Use gpr_write_mask.
227 (insns_between): Use gpr_read_mask instead of EXTRACT_OPERAND.
228
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2292013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
230 Alexander Ivchenko <alexander.ivchenko@intel.com>
231 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
232 Sergey Lega <sergey.s.lega@intel.com>
233 Anna Tikhonova <anna.tikhonova@intel.com>
234 Ilya Tocar <ilya.tocar@intel.com>
235 Andrey Turetskiy <andrey.turetskiy@intel.com>
236 Ilya Verbin <ilya.verbin@intel.com>
237 Kirill Yukhin <kirill.yukhin@intel.com>
238 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
239
240 * config/tc-i386-intel.c (O_zmmword_ptr): New.
241 (i386_types): Add zmmword.
242 (i386_intel_simplify_register): Allow regzmm.
243 (i386_intel_simplify): Handle zmmwords.
244 (i386_intel_operand): Handle RC/SAE, vector operations and
245 zmmwords.
246 * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
247 (struct RC_Operation): New.
248 (struct Mask_Operation): New.
249 (struct Broadcast_Operation): New.
250 (vex_prefix): Size of bytes increased to 4 to support EVEX
251 encoding.
252 (enum i386_error): Add new error codes: unsupported_broadcast,
253 broadcast_not_on_src_operand, broadcast_needed,
254 unsupported_masking, mask_not_on_destination, no_default_mask,
255 unsupported_rc_sae, rc_sae_operand_not_last_imm,
256 invalid_register_operand, try_vector_disp8.
257 (struct _i386_insn): Add new fields vrex, need_vrex, mask,
258 rounding, broadcast, memshift.
259 (struct RC_name): New.
260 (RC_NamesTable): New.
261 (evexlig): New.
262 (evexwig): New.
263 (extra_symbol_chars): Add '{'.
264 (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
265 (i386_operand_type): Add regzmm, regmask and vec_disp8.
266 (match_mem_size): Handle zmmwords.
267 (operand_type_match): Handle zmm-registers.
268 (mode_from_disp_size): Handle vec_disp8.
269 (fits_in_vec_disp8): New.
270 (md_begin): Handle {} properly.
271 (type_names): Add "rZMM", "Mask reg" and "Vector d8".
272 (build_vex_prefix): Handle vrex.
273 (build_evex_prefix): New.
274 (process_immext): Adjust to properly handle EVEX.
275 (md_assemble): Add EVEX encoding support.
276 (swap_2_operands): Correctly handle operands with masking,
277 broadcasting or RC/SAE.
278 (check_VecOperands): Support EVEX features.
279 (VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
280 (match_template): Support regzmm and handle new error codes.
281 (process_suffix): Handle zmmwords and zmm-registers.
282 (check_byte_reg): Extend to zmm-registers.
283 (process_operands): Extend to zmm-registers.
284 (build_modrm_byte): Handle EVEX.
285 (output_insn): Adjust to properly handle EVEX case.
286 (disp_size): Handle vec_disp8.
287 (output_disp): Support compressed disp8*N evex feature.
288 (output_imm): Handle RC/SAE immediates properly.
289 (check_VecOperations): New.
290 (i386_immediate): Handle EVEX features.
291 (i386_index_check): Handle zmmwords and zmm-registers.
292 (RC_SAE_immediate): New.
293 (i386_att_operand): Handle EVEX features.
294 (parse_real_register): Add a check for ZMM/Mask registers.
295 (OPTION_MEVEXLIG): New.
296 (OPTION_MEVEXWIG): New.
297 (md_longopts): Add mevexlig and mevexwig.
298 (md_parse_option): Handle mevexlig and mevexwig options.
299 (md_show_usage): Add description for mevexlig and mevexwig.
300 * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
301 avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
302
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3032013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
304
305 * config/tc-i386.c (cpu_arch): Add .sha.
306 * doc/c-i386.texi: Document sha/.sha.
307
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3082013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
309 Kirill Yukhin <kirill.yukhin@intel.com>
310 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
311
312 * config/tc-i386.c (BND_PREFIX): New.
313 (struct _i386_insn): Add new field bnd_prefix.
314 (add_bnd_prefix): New.
315 (cpu_arch): Add MPX.
316 (i386_operand_type): Add regbnd.
317 (md_assemble): Handle BND prefixes.
318 (parse_insn): Likewise.
319 (output_branch): Likewise.
320 (output_jump): Likewise.
321 (build_modrm_byte): Handle regbnd.
322 (OPTION_MADD_BND_PREFIX): New.
323 (md_longopts): Add entry for 'madd-bnd-prefix'.
324 (md_parse_option): Handle madd-bnd-prefix option.
325 (md_show_usage): Add description for madd-bnd-prefix
326 option.
327 * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.
328
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3292013-07-24 Tristan Gingold <gingold@adacore.com>
330
331 * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on
332 xcoff targets.
333
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3342013-07-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
335
336 * config/tc-s390.c (s390_machine): Don't force the .machine
337 argument to lower case.
338
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3392013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
340
341 * config/tc-arm.c (s_arm_arch_extension): Improve error message
342 for invalid extension.
343
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3442013-07-19 Yufeng Zhang <yufeng.zhang@arm.com>
345
346 * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
347 (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
348 (aarch64_abi): New variable.
349 (ilp32_p): Change to be a macro.
350 (aarch64_opts): Remove the support for option -milp32 and -mlp64.
351 (struct aarch64_option_abi_value_table): New struct.
352 (aarch64_abis): New table.
353 (aarch64_parse_abi): New function.
354 (aarch64_long_opts): Add entry for -mabi=.
355 * doc/as.texinfo (Target AArch64 options): Document -mabi.
356 * doc/c-aarch64.texi: Likewise.
357
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3582013-07-18 Jim Thomas <thomas@cfht.hawaii.edu>
359
360 * config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs
361 unsigned comparison.
362
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3632013-07-18 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
364
cbe02d4f 365 * config/rx-defs.h: Add macros for RX100, RX200, RX600, and
f0c00282 366 RX610.
cbe02d4f 367 * config/rx-parse.y: (rx_check_float_support): Add function to
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368 check floating point operation support for target RX100 and
369 RX200.
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370 * config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610.
371 * doc/c-rx.texi: Add -mcpu option to recognize macros for RX100,
372 RX200, RX600, and RX610
f0c00282 373
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3742013-07-18 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
375
376 * config/tc-avr.c (md_show_usage): Add avrxmega2 to help text
377
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3782013-07-18 Vishnu K.S <vishnu.k_s@atmel.com>
379
380 * config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4.
381 * doc/c-avr.texi: Likewise.
382
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3832013-07-15 Richard Sandiford <rdsandiford@googlemail.com>
384
385 * config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat
386 error with older GCCs.
387 (mips16_macro_build): Dereference args.
388
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3892013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
390
391 * config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
392 New functions, split out from...
393 (reg_lookup): ...here. Remove itbl support.
394 (reglist_lookup): Delete.
395 (mips_operand_token_type): New enum.
396 (mips_operand_token): New structure.
397 (mips_operand_tokens): New variable.
398 (mips_add_token, mips_parse_base_start, mips_parse_argument_token)
399 (mips_parse_arguments): New functions.
400 (md_begin): Initialize mips_operand_tokens.
401 (mips_arg_info): Add a token field. Remove optional_reg field.
402 (match_char, match_expression): New functions.
403 (match_const_int): Use match_expression. Remove "s" argument
404 and return a boolean result. Remove O_register handling.
405 (match_regno, match_reg, match_reg_range): New functions.
406 (match_int_operand, match_mapped_int_operand, match_msb_operand)
407 (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
408 (match_addiusp_operand, match_clo_clz_dest_operand)
409 (match_lwm_swm_list_operand, match_entry_exit_operand)
410 (match_save_restore_list_operand, match_mdmx_imm_reg_operand)
411 (match_tied_reg_operand): Remove "s" argument and return a boolean
412 result. Match tokens rather than text. Update calls to
413 match_const_int. Rely on match_regno to call check_regno.
414 (match_pcrel_operand, match_pc_operand): Replace "s" argument with
415 "arg" argument. Return a boolean result.
416 (parse_float_constant): Replace with...
417 (match_float_constant): ...this new function.
418 (match_operand): Remove "s" argument and return a boolean result.
419 Update calls to subfunctions.
420 (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
421 rather than string-parsing routines. Update handling of optional
422 registers for token scheme.
423
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4242013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
425
426 * config/tc-mips.c (parse_float_constant): Split out from...
427 (mips_ip): ...here.
428
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4292013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
430
431 * config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND):
432 Delete.
433
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4342013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
435
436 * config/tc-mips.c (mips32_to_16_reg_map): Delete.
437 (match_entry_exit_operand): New function.
438 (match_save_restore_list_operand): Likewise.
439 (match_operand): Use them.
440 (check_absolute_expr): Delete.
441 (mips16_ip): Rewrite main parsing loop to use mips_operands.
442
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4432013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
444
445 * config/tc-mips.c: Enable functions commented out in previous patch.
446 (SKIP_SPACE_TABS): Move further up file.
447 (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map)
448 (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map)
449 (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map)
450 (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map)
451 (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map)
452 (micromips_imm_b_map, micromips_imm_c_map): Delete.
453 (mips_lookup_reg_pair): Delete.
454 (macro): Use report_bad_range and report_bad_field.
455 (mips_immed, expr_const_in_range): Delete.
456 (mips_ip): Rewrite main parsing loop to use new functions.
457
a1d78564
RS
4582013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
459
460 * config/tc-mips.c (mips_oddfpreg_ok): Move further up file.
461 Change return type to bfd_boolean.
462 (report_bad_range, report_bad_field): New functions.
463 (mips_arg_info): New structure.
464 (match_const_int, convert_reg_type, check_regno, match_int_operand)
465 (match_mapped_int_operand, match_msb_operand, match_reg_operand)
466 (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand)
467 (match_addiusp_operand, match_clo_clz_dest_operand)
468 (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand)
469 (match_pc_operand, match_tied_reg_operand, match_operand)
470 (check_completed_insn): New functions, commented out for now.
471
e077a1c8
RS
4722013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
473
474 * config/tc-mips.c (insn_insert_operand): New function.
475 (macro_build, mips16_macro_build): Put null character check
476 in the for loop and convert continues to breaks. Use operand
477 structures to handle constant operands.
478
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RS
4792013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
480
481 * config/tc-mips.c (validate_mips_insn): Move further up file.
482 Add insn_bits and decode_operand arguments. Use the mips_operand
483 fields to work out which bits an operand occupies. Detect double
484 definitions.
485 (validate_micromips_insn): Move further up file. Call into
486 validate_mips_insn.
487
2f8b73cc
RS
4882013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
489
490 * config/tc-mips.c (mips16_macro_build): Remove 'Y' case.
491
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RS
4922013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
493
494 * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\"
495 and "~".
496 (macro): Update accordingly.
497
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RS
4982013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
499
500 * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary.
501 (imm_reloc): Delete.
502 (md_assemble): Remove imm_reloc handling.
503 (mips_ip): Update commentary. Use offset_expr and offset_reloc
504 rather than imm_expr and imm_reloc for 'i', 'j' and 'u'.
505 Use a temporary array rather than imm_reloc when parsing
506 constant expressions. Remove imm_reloc initialization.
507 (mips16_ip): Update commentary. Use offset_expr and offset_reloc
508 for the relaxable field. Use a relax_char variable to track the
509 type of this field. Remove imm_reloc initialization.
510
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RS
5112013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
512
513 * config/tc-mips.c (mips16_ip): Handle "I".
514
ba92f887
MR
5152013-07-12 Maciej W. Rozycki <macro@codesourcery.com>
516
517 * config/tc-mips.c (mips_flag_nan2008): New variable.
518 (options): Add OPTION_NAN enum value.
519 (md_longopts): Handle it.
520 (md_parse_option): Likewise.
521 (s_nan): New function.
522 (mips_elf_final_processing): Handle EF_MIPS_NAN2008.
523 (md_show_usage): Add -mnan.
524
525 * doc/as.texinfo (Overview): Add -mnan.
526 * doc/c-mips.texi (MIPS Opts): Document -mnan.
527 (MIPS NaN Encodings): New node. Document .nan directive.
528 (MIPS-Dependent): List the new node.
529
c1094734
TG
5302013-07-09 Tristan Gingold <gingold@adacore.com>
531
532 * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
533
0cbbe1b8
RS
5342013-07-08 Richard Sandiford <rdsandiford@googlemail.com>
535
536 * config/tc-mips.c (mips_ip): Unconditionally parse an expression
537 for 'A' and assume that the constant has been elided if the result
538 is an O_register.
539
f2ae14a1
RS
5402013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
541
542 * config/tc-mips.c (gprel16_reloc_p): New function.
543 (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
544 BFD_RELOC_UNUSED.
545 (offset_high_part, small_offset_p): New functions.
546 (nacro): Use them. Remove *_OB and *_DOB cases. For single-
547 register load and store macros, handle the 16-bit offset case first.
548 If a 16-bit offset is not suitable for the instruction we're
549 generating, load it into the temporary register using
550 ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
551 M_L_DAB code once the address has been constructed. For double load
552 and store macros, again handle the 16-bit offset case first.
553 If the second register cannot be accessed from the same high
554 part as the first, load it into AT using ADDRESS_ADDI_INSN.
555 Fix the handling of LD in cases where the first register is the
556 same as the base. Also handle the case where the offset is
557 not 16 bits and the second register cannot be accessed from the
558 same high part as the first. For unaligned loads and stores,
559 fuse the offbits == 12 and old "ab" handling. Apply this handling
560 whenever the second offset needs a different high part from the first.
561 Construct the offset using ADDRESS_ADDI_INSN where possible,
562 for offbits == 16 as well as offbits == 12. Use offset_reloc
563 when constructing the individual loads and stores.
564 (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
565 and offset_reloc before matching against a particular opcode.
566 Handle elided 'A' constants. Allow 'A' constants to use
567 relocation operators.
568
5c324c16
RS
5692013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
570
571 * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
572 (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
573 Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
574
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RS
5752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
576
577 * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
578 Require the msb to be <= 31 for "+s". Check that the size is <= 31
579 for both "+s" and "+S".
580
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RS
5812013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
582
583 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
584 (mips_ip, mips16_ip): Handle "+i".
585
e76ff5ab
RS
5862013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
587
588 * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
589 (micromips_to_32_reg_h_map): Rename to...
590 (micromips_to_32_reg_h_map1): ...this.
591 (micromips_to_32_reg_i_map): Rename to...
592 (micromips_to_32_reg_h_map2): ...this.
593 (mips_lookup_reg_pair): New function.
594 (gpr_write_mask, macro): Adjust after above renaming.
595 (validate_micromips_insn): Remove "mi" handling.
596 (mips_ip): Likewise. Parse both registers in a pair for "mh".
597
fa7616a4
RS
5982013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
599
600 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
601 (mips_ip): Remove "+D" and "+T" handling.
602
fb798c50
AK
6032013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
604
605 * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
606 relocs.
607
2c0a3565
MS
6082013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
609
4aa2c5e2
MS
610 * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
611
6122013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
613
2c0a3565
MS
614 * config/tc-aarch64.c (md_apply_fix): Reorder case values.
615 (aarch64_force_relocation): Likewise.
616
f40da81b
AM
6172013-07-02 Alan Modra <amodra@gmail.com>
618
619 * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
620
81566a9b
MR
6212013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
622
623 * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
624 * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
625 Replace @sc{mips16} with literal `MIPS16'.
626 (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
627
a6bb11b2
YZ
6282013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
629
630 * config/tc-aarch64.c (reloc_table): Replace
631 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
632 BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
633 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
634 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
635 (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
636 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
637 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
638 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
639 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
640 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
641 (aarch64_force_relocation): Likewise.
642
cec5225b
YZ
6432013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
644
645 * config/tc-aarch64.c (ilp32_p): New static variable.
646 (elf64_aarch64_target_format): Return the target according to the
647 value of 'ilp32_p'.
648 (md_begin): Determine 'mach' according to the value of 'ilp32_p'.
649 (aarch64_opts): Add support for options '-milp32' and '-mlp64'.
650 (aarch64_dwarf2_addr_size): New function.
651 * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
652 (DWARF2_ADDR_SIZE): New define.
653
e335d9cb
RS
6542013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
655
656 * doc/c-mips.texi: Use ISA instead of @sc{isa}.
657
18870af7
RS
6582013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
659
660 * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
661
833794fc
MR
6622013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
663
664 * config/tc-mips.c (mips_set_options): Add insn32 member.
665 (mips_opts): Initialize it.
666 (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
667 (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
668 (md_longopts): Add "minsn32" and "mno-insn32" options.
669 (is_size_valid): Handle insn32 mode.
670 (md_assemble): Pass instruction string down to macro.
671 (brk_fmt): Add second dimension and insn32 mode initializers.
672 (mfhl_fmt): Likewise.
673 (BRK_FMT, MFHL_FMT): Handle insn32 mode.
674 (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
675 (macro_build_jalr, move_register): Handle insn32 mode.
676 (macro_build_branch_rs): Likewise.
677 (macro): Handle insn32 mode.
678 <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
679 (mips_ip): Handle insn32 mode.
680 (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
681 (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
682 (mips_handle_align): Handle insn32 mode.
683 (md_show_usage): Add -minsn32 and -mno-insn32.
684
685 * doc/as.texinfo (Target MIPS options): Add -minsn32 and
686 -mno-insn32 options.
687 (-minsn32, -mno-insn32): New options.
688 * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
689 options.
690 (MIPS assembly options): New node. Document .set insn32 and
691 .set noinsn32.
692 (MIPS-Dependent): List the new node.
693
d1706f38
NC
6942013-06-25 Nick Clifton <nickc@redhat.com>
695
696 * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
697 the PC in indirect addressing on 430xv2 parts.
698 (msp430_operands): Add version test to hardware bug encoding
699 restrictions.
700
477330fc
RM
7012013-06-24 Roland McGrath <mcgrathr@google.com>
702
d996d970
RM
703 * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
704 so it skips whitespace before it.
705 (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
706
477330fc
RM
707 * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
708 (arm_reg_parse_multi): Skip whitespace first.
709 (parse_reg_list): Likewise.
710 (parse_vfp_reg_list): Likewise.
711 (s_arm_unwind_save_mmxwcg): Likewise.
712
24382199
NC
7132013-06-24 Nick Clifton <nickc@redhat.com>
714
715 PR gas/15623
716 * config/tc-arm.c (do_t_smc): Mark as ending an IT block.
717
c3678916
RS
7182013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
719
720 * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
721
42429eac
RS
7222013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
723
724 * config/tc-mips.c: Assert that offsetT and valueT are at least
725 8 bytes in size.
726 (GPR_SMIN, GPR_SMAX): New macros.
727 (macro, mips_ip): Remove code for 4-byte valueT and offsetT.
728
f3ded42a
RS
7292013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
730
731 * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
732 conditions. Remove any code deselected by them.
733 (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
734
e8044f35
RS
7352013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
736
737 * NEWS: Note removal of ECOFF support.
738 * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
739 * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
740 (MULTI_CFILES): Remove config/e-mipsecoff.c.
741 * Makefile.in: Regenerate.
742 * configure.in: Remove MIPS ECOFF references.
743 (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
744 Delete cases.
745 (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
746 (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
747 (mips-*-*): ...this single case.
748 (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
749 MIPS emulations to be e-mipself*.
750 * configure: Regenerate.
751 * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
752 (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
753 (mips-*-sysv*): Remove coff and ecoff cases.
754 * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
755 * ecoff.c: Remove reference to MIPS ECOFF.
756 * config/e-mipsecoff.c, config/te-lnews.h: Delete files.
757 * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
758 (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
759 (mips_hi_fixup): Tweak comment.
760 (append_insn): Require a howto.
761 (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
762
98508b2a
RS
7632013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
764
765 * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
766 Use "CPU" instead of "cpu".
767 * doc/c-mips.texi: Likewise.
768 (MIPS Opts): Rename to MIPS Options.
769 (MIPS option stack): Rename to MIPS Option Stack.
770 (MIPS ASE instruction generation overrides): Rename to
771 MIPS ASE Instruction Generation Overrides (for now).
772 (MIPS floating-point): Rename to MIPS Floating-Point.
773
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RS
7742013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
775
776 * doc/c-mips.texi (MIPS Macros): New section.
777 (MIPS Object): Replace with...
778 (MIPS Small Data): ...this new section.
779
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RS
7802013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
781
782 * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
783 Capitalize name. Use @kindex instead of @cindex for .set entries.
784
a1b86ab7
RS
7852013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
786
787 * doc/c-mips.texi (MIPS Stabs): Remove section.
788
c6278170
RS
7892013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
790
791 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
792 (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
793 (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
794 (ISA_SUPPORTS_VIRT64_ASE): Delete.
795 (mips_ase): New structure.
796 (mips_ases): New table.
797 (FP64_ASES): New macro.
798 (mips_ase_groups): New array.
799 (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
800 (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
801 functions.
802 (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
803 (md_parse_option): Use mips_ases and mips_set_ase instead of
804 separate case statements for each ASE option.
805 (mips_after_parse_args): Use FP64_ASES. Use
806 mips_check_isa_supports_ases to check the ASEs against
807 other options.
808 (s_mipsset): Use mips_ases and mips_set_ase instead of
809 separate if statements for each ASE option. Use
810 mips_check_isa_supports_ases, even when a non-ASE option
811 is specified.
812
63a4bc21
KT
8132013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
814
815 * config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
816
c31f3936
RS
8172013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
818
819 * config/tc-mips.c (md_shortopts, options, md_longopts)
820 (md_longopts_size): Move earlier in file.
821
846ef2d0
RS
8222013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
823
824 * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
825 with a single "ase" bitmask.
826 (mips_opts): Update accordingly.
827 (file_ase, file_ase_explicit): New variables.
828 (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
829 (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
830 (ISA_HAS_ROR): Adjust for mips_set_options change.
831 (is_opcode_valid): Take the base ase mask directly from mips_opts.
832 (mips_ip): Adjust for mips_set_options change.
833 (md_parse_option): Likewise. Update file_ase_explicit.
834 (mips_after_parse_args): Adjust for mips_set_options change.
835 Use bitmask operations to select the default ASEs. Set file_ase
836 rather than individual per-ASE variables.
837 (s_mipsset): Adjust for mips_set_options change.
838 (mips_elf_final_processing): Test file_ase rather than
839 file_ase_mdmx. Remove commented-out code.
840
d16afab6
RS
8412013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
842
843 * config/tc-mips.c (mips_cpu_info): Add an "ase" field.
844 (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
845 (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
846 (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
847 (mips_after_parse_args): Use the new "ase" field to choose
848 the default ASEs.
849 (mips_cpu_info_table): Move ASEs from the "flags" field to the
850 "ase" field.
851
e83a675f
RE
8522013-06-18 Richard Earnshaw <rearnsha@arm.com>
853
854 * config/tc-arm.c (symbol_preemptible): New function.
855 (relax_branch): Use it.
856
7f3c4072
CM
8572013-06-17 Catherine Moore <clm@codesourcery.com>
858 Maciej W. Rozycki <macro@codesourcery.com>
859 Chao-Ying Fu <fu@mips.com>
860
861 * config/tc-mips.c (mips_set_options): Add ase_eva.
862 (mips_set_options mips_opts): Add ase_eva.
863 (file_ase_eva): Declare.
864 (ISA_SUPPORTS_EVA_ASE): Define.
865 (IS_SEXT_9BIT_NUM): Define.
866 (MIPS_CPU_ASE_EVA): Define.
867 (is_opcode_valid): Add support for ase_eva.
868 (macro_build): Likewise.
869 (macro): Likewise.
870 (validate_mips_insn): Likewise.
871 (validate_micromips_insn): Likewise.
872 (mips_ip): Likewise.
873 (options): Add OPTION_EVA and OPTION_NO_EVA.
874 (md_longopts): Add -meva and -mno-eva.
875 (md_parse_option): Process new options.
876 (mips_after_parse_args): Check for valid EVA combinations.
877 (s_mipsset): Likewise.
878
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RS
8792013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
880
881 * dwarf2dbg.h (dwarf2_move_insn): Declare.
882 * dwarf2dbg.c (line_subseg): Add pmove_tail.
883 (get_line_subseg): Add create_p argument. Initialize pmove_tail.
884 (dwarf2_gen_line_info_1): Update call accordingly.
885 (dwarf2_move_insn): New function.
886 * config/tc-mips.c (append_insn): Use dwarf2_move_insn.
887
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RS
8882013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
889
890 Revert:
891
892 2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
893
894 PR gas/13024
895 * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
896 (dwarf2_gen_line_info_1): Delete.
897 (dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
898 (dwarf2_gen_line_info, dwarf2_emit_label): Use them.
899 (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
900 (dwarf2_directive_loc): Push previous .locs instead of generating
901 them immediately.
902
f122319e
CF
9032013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
904
905 * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
906 (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
907
909c7f9c
NC
9082013-06-13 Nick Clifton <nickc@redhat.com>
909
910 PR gas/15602
911 * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
912 * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
913 function. Generates an error if the adjusted offset is out of a
914 16-bit range.
915
5d5755a7
SL
9162013-06-12 Sandra Loosemore <sandra@codesourcery.com>
917
918 * config/tc-nios2.c (md_apply_fix): Mask constant
919 BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
920
3bf0dbfb
MR
9212013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
922
923 * config/tc-mips.c (append_insn): Don't do branch relaxation for
924 MIPS-3D instructions either.
925 (md_convert_frag): Update the COPx branch mask accordingly.
926
927 * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
928 option.
929 * doc/as.texinfo (Overview): Add --relax-branch and
930 --no-relax-branch.
931 * doc/c-mips.texi (MIPS Opts): Document --relax-branch and
932 --no-relax-branch.
933
9daf7bab
SL
9342013-06-09 Sandra Loosemore <sandra@codesourcery.com>
935
936 * config/tc-nios2.c (nios2_parse_args): Allow trap argument to
937 omitted.
938
d301a56b
RS
9392013-06-08 Catherine Moore <clm@codesourcery.com>
940
941 * config/tc-mips.c (is_opcode_valid): Build ASE mask.
942 (is_opcode_valid_16): Pass ase value to opcode_is_member.
943 (append_insn): Change INSN_xxxx to ASE_xxxx.
944
7bab7634
DC
9452013-06-01 George Thomas <george.thomas@atmel.com>
946
cbe02d4f 947 * gas/config/tc-avr.c: Change ISA for devices with USB support to
7bab7634
DC
948 AVR_ISA_XMEGAU
949
f60cf82f
L
9502013-05-31 H.J. Lu <hongjiu.lu@intel.com>
951
952 * config/tc-i386.c (md_begin): Don't align text/data/bss sections
953 for ELF.
954
a3f278e2
CM
9552013-05-31 Paul Brook <paul@codesourcery.com>
956
a3f278e2
CM
957 * config/tc-mips.c (s_ehword): New.
958
067ec077
CM
9592013-05-30 Paul Brook <paul@codesourcery.com>
960
961 * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH.
962
d6101ac2
MR
9632013-05-29 Maciej W. Rozycki <macro@codesourcery.com>
964
965 * write.c (resolve_reloc_expr_symbols): On REL targets don't
966 convert relocs who have no relocatable field either. Rephrase
967 the conditional so that the PC-relative check is only applied
968 for REL targets.
969
f19ccbda
MR
9702013-05-28 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
971
972 * config/tc-mips.c (macro) <ld>: Don't use $zero for address
973 calculation.
974
418009c2
YZ
9752013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
976
977 * config/tc-aarch64.c (reloc_table): Update to use
477330fc 978 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
418009c2
YZ
979 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
980 (md_apply_fix): Likewise.
981 (aarch64_force_relocation): Likewise.
982
0a8897c7
KT
9832013-05-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
984
985 * config/tc-arm.c (it_fsm_post_encode): Improve
986 warning messages about deprecated IT block formats.
987
89d2a2a3
MS
9882013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
989
990 * config/tc-aarch64.c (md_apply_fix): Move value range checking
991 inside fx_done condition.
992
c77c0862
RS
9932013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
994
995 * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
996
c0637f3a
PB
9972013-05-20 Peter Bergner <bergner@vnet.ibm.com>
998
999 * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
1000 and clean up warning when using PRINT_OPCODE_TABLE.
1001
5656a981
AM
10022013-05-20 Alan Modra <amodra@gmail.com>
1003
1004 * config/tc-ppc.c (md_apply_fix): Hoist code common to insn
1005 and data fixups performing shift/high adjust/sign extension on
1006 fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
1007 when writing data fixups rather than recalculating size.
1008
997b26e8
JBG
10092013-05-16 Jan-Benedict Glaw <jbglaw@lug-owl.de>
1010
1011 * doc/c-msp430.texi: Fix typo.
1012
9f6e76f4
TG
10132013-05-16 Tristan Gingold <gingold@adacore.com>
1014
1015 * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC
1016 are also TOC symbols.
1017
638d3803
NC
10182013-05-16 Nick Clifton <nickc@redhat.com>
1019
1020 * config/tc-msp430.c: Make -mmcu recognise more part numbers.
1021 Add -mcpu command to specify core type.
997b26e8 1022 * doc/c-msp430.texi: Update documentation.
638d3803 1023
b015e599
AP
10242013-05-09 Andrew Pinski <apinski@cavium.com>
1025
1026 * config/tc-mips.c (struct mips_set_options): New ase_virt field.
1027 (mips_opts): Update for the new field.
1028 (file_ase_virt): New variable.
1029 (ISA_SUPPORTS_VIRT_ASE): New macro.
1030 (ISA_SUPPORTS_VIRT64_ASE): New macro.
1031 (MIPS_CPU_ASE_VIRT): New define.
1032 (is_opcode_valid): Handle ase_virt.
1033 (macro_build): Handle "+J".
1034 (validate_mips_insn): Likewise.
1035 (mips_ip): Likewise.
1036 (enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
1037 (md_longopts): Add mvirt and mnovirt
1038 (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
1039 (mips_after_parse_args): Handle ase_virt field.
1040 (s_mipsset): Handle "virt" and "novirt".
1041 (mips_elf_final_processing): Add a comment about virt ASE might need
1042 a new flag.
1043 (md_show_usage): Print out the usage of -mvirt and mno-virt options.
1044 * doc/c-mips.texi: Document -mvirt and -mno-virt.
1045 Document ".set virt" and ".set novirt".
1046
da8094d7
AM
10472013-05-09 Alan Modra <amodra@gmail.com>
1048
1049 * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under
1050 control of operand flag bits.
1051
c5f8c205
AM
10522013-05-07 Alan Modra <amodra@gmail.com>
1053
1054 * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro.
1055 (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
1056 (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
1057 (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
1058 (md_apply_fix): Set fx_no_overflow for assorted relocations.
1059 Shift and sign-extend fieldval for use by some VLE reloc
1060 operand->insert functions.
1061
b47468a6
CM
10622013-05-06 Paul Brook <paul@codesourcery.com>
1063 Catherine Moore <clm@codesourcery.com>
1064
c5f8c205
AM
1065 * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL.
1066 (limited_pcrel_reloc_p): Likewise.
b47468a6
CM
1067 (md_apply_fix): Likewise.
1068 (tc_gen_reloc): Likewise.
1069
2de39019
CM
10702013-05-06 Richard Sandiford <rdsandiford@googlemail.com>
1071
1072 * config/tc-mips.c (limited_pcrel_reloc_p): New function.
1073 (mips_fix_adjustable): Adjust pc-relative check to use
1074 limited_pc_reloc_p.
1075
754e2bb9
RS
10762013-05-02 Richard Sandiford <rdsandiford@googlemail.com>
1077
1078 * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
1079 (s_mips_stab): Do not restrict to stabn only.
1080
13761a11
NC
10812013-05-02 Nick Clifton <nickc@redhat.com>
1082
1083 * config/tc-msp430.c: Add support for the MSP430X architecture.
1084 Add code to insert a NOP instruction after any instruction that
1085 might change the interrupt state.
1086 Add support for the LARGE memory model.
1087 Add code to initialise the .MSP430.attributes section.
1088 * config/tc-msp430.h: Add support for the MSP430X architecture.
1089 * doc/c-msp430.texi: Document the new -mL and -mN command line
1090 options.
1091 * NEWS: Mention support for the MSP430X architecture.
1092
df26367c
MR
10932013-05-01 Maciej W. Rozycki <macro@codesourcery.com>
1094
1095 * configure.tgt: Replace alpha*-*-linuxecoff* pattern with
1096 alpha*-*-linux*ecoff*.
1097
f02d8318
CF
10982013-04-30 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
1099
1100 * config/tc-mips.c (mips_ip): Add sizelo.
1101 For "+C", "+G", and "+H", set sizelo and compare against it.
1102
b40bf0a2
NC
11032013-04-29 Nick Clifton <nickc@redhat.com>
1104
1105 * as.c (Options): Add -gdwarf-sections.
1106 (parse_args): Likewise.
1107 * as.h (flag_dwarf_sections): Declare.
1108 * dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes.
1109 (process_entries): When -gdwarf-sections is enabled generate
1110 fragmentary .debug_line sections.
1111 (out_debug_line): Set the section for the .debug_line section end
1112 symbol.
1113 * doc/as.texinfo: Document -gdwarf-sections.
1114 * NEWS: Mention -gdwarf-sections.
1115
8eeccb77 11162013-04-26 Christian Groessler <chris@groessler.org>
00a3147e
CG
1117
1118 * config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline
1119 according to the target parameter. Don't call s_segm since s_segm
1120 calls bfd_set_arch_mach using stdoutput, but stdoutput isn't
1121 initialized yet.
1122 (md_begin): Call s_segm according to target parameter from command
1123 line.
1124
49926cd0
AM
11252013-04-25 Alan Modra <amodra@gmail.com>
1126
1127 * configure.in: Allow little-endian linux.
1128 * configure: Regenerate.
1129
e3031850
SL
11302013-04-24 Sandra Loosemore <sandra@codesourcery.com>
1131
1132 * config/tc-nios2.c (nios2_control_register_arg_p): Rename
1133 "fstatus" control register to "eccinj".
1134
cb948fc0
KT
11352013-04-19 Kai Tietz <ktietz@redhat.com>
1136
1137 * configure.tgt (i386-*-cygwin): Handle x86_64 cygwin.
1138
4455e9ad
JB
11392013-04-15 Julian Brown <julian@codesourcery.com>
1140
1141 * expr.c (add_to_result, subtract_from_result): Make global.
1142 * expr.h (add_to_result, subtract_from_result): Add prototypes.
1143 * config/tc-sh.c (sh_optimize_expr): Use add_to_result,
1144 subtract_from_result to handle extra bit of precision for .sleb128
1145 directive operands.
1146
956a6ba3
JB
11472013-04-10 Julian Brown <julian@codesourcery.com>
1148
1149 * read.c (convert_to_bignum): Add sign parameter. Use it
1150 instead of X_unsigned to determine sign of resulting bignum.
1151 (emit_expr): Pass extra argument to convert_to_bignum.
1152 (emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass
1153 X_extrabit to convert_to_bignum.
1154 (parse_bitfield_cons): Set X_extrabit.
1155 * expr.c (make_expr_symbol, expr_build_uconstant, operand):
1156 Initialise X_extrabit field as appropriate.
1157 (add_to_result): New.
1158 (subtract_from_result): New.
1159 (expr): Use above.
1160 * expr.h (expressionS): Add X_extrabit field.
1161
eb9f3f00
JB
11622013-04-10 Jan Beulich <jbeulich@suse.com>
1163
1164 * gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
1165 register being PC when is_t or writeback, and use distinct
1166 diagnostic for the latter case.
1167
ccb84d65
JB
11682013-04-10 Jan Beulich <jbeulich@suse.com>
1169
1170 * gas/config/tc-arm.c (parse_operands): Re-write
1171 po_barrier_or_imm().
1172 (do_barrier): Remove bogus constraint().
1173 (do_t_barrier): Remove.
1174
4d13caa0
NC
11752013-04-09 Joerg Wunsch <joerg.wunsch@atmel.com>
1176
1177 * gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2,
1178 ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2,
1179 ATmega2564RFR2
1180 * gas/doc/c-avr.texi (-mmcu documentation): Likewise.
1181
16d02dc9
JB
11822013-04-09 Jan Beulich <jbeulich@suse.com>
1183
1184 * gas/config/tc-arm.c (do_vmrs): Accept all control registers.
1185 Use local variable Rt in more places.
1186 (do_vmsr): Accept all control registers.
1187
05ac0ffb
JB
11882013-04-09 Jan Beulich <jbeulich@suse.com>
1189
1190 * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
1191 if there was none specified for moves between scalar and core
1192 register.
1193
2d51fb74
JB
11942013-04-09 Jan Beulich <jbeulich@suse.com>
1195
1196 * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
1197 NEON_ALL_LANES case.
1198
94dcf8bf
JB
11992013-04-08 Jan Beulich <jbeulich@suse.com>
1200
1201 * gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for
1202 PC-relative VSTR.
1203
1472d06f
JB
12042013-04-08 Jan Beulich <jbeulich@suse.com>
1205
1206 * gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq
1207 entry to sp_fiq.
1208
0c76cae8
AM
12092013-04-03 Alan Modra <amodra@gmail.com>
1210
1211 * doc/as.texinfo: Add support to generate man options for h8300.
1212 * doc/c-h8300.texi: Likewise.
1213
92eb40d9
RR
12142013-03-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1215
1216 * config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and
1217 Cortex-A57.
1218
51dcdd4d
NC
12192013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1220
1221 PR binutils/15068
1222 * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
1223
c5d685bf
NC
12242013-03-26 Nick Clifton <nickc@redhat.com>
1225
9b978282
NC
1226 PR gas/15295
1227 * listing.c (rebuffer_line): Rewrite to avoid seeking back to the
1228 start of the file each time.
1229
c5d685bf
NC
1230 PR gas/15178
1231 * config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for
1232 FreeBSD targets.
1233
9699c833
TG
12342013-03-26 Douglas B Rupp <rupp@gnat.com>
1235
1236 * config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
1237 after fixup.
1238
4755303e
WN
12392013-03-21 Will Newton <will.newton@linaro.org>
1240
1241 * config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
1242 pc-relative str instructions in Thumb mode.
1243
81f5558e
NC
12442013-03-21 Michael Schewe <michael.schewe@gmx.net>
1245
1246 * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov
1247 @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc
1248 R_H8_DISP32A16.
1249 * config/tc-h8300.h: Remove duplicated defines.
1250
71863e73
NC
12512013-03-21 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
1252
1253 PR gas/15282
1254 * tc-avr.c (mcu_has_3_byte_pc): New function.
1255 (tc_cfi_frame_initial_instructions): Call it to find return
1256 address size.
1257
795b8e6b
NC
12582013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1259
1260 PR gas/15095
1261 * config/tc-tic6x.c (tic6x_try_encode): Handle
1262 tic6x_coding_dreg_(msb|lsb) field coding types and use it to
1263 encode register pair numbers when required.
1264
ba86b375
WN
12652013-03-15 Will Newton <will.newton@linaro.org>
1266
1267 * config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register
1268 in vstr in Thumb mode for pre-ARMv7 cores.
1269
9e6f3811
AS
12702013-03-14 Andreas Schwab <schwab@suse.de>
1271
1272 * doc/c-arc.texi (ARC Directives): Revert last change and use
1273 @itemize instead of @table.
1274 * doc/c-arm.texi (ARM-Instruction-Set): Likewise.
1275
b10bf8c5
NC
12762013-03-14 Nick Clifton <nickc@redhat.com>
1277
1278 PR gas/15273
1279 * config/tc-arm.c (do_co_reg): Do not call check_obsolete with a
1280 NULL message, instead just check ARM_CPU_IS_ANY directly.
1281
ba724cfc
NC
12822013-03-14 Nick Clifton <nickc@redhat.com>
1283
1284 PR gas/15212
9e6f3811 1285 * doc/c-arc.texi (ARC Directives): Use @code instead of @bullet
ba724cfc
NC
1286 for table format.
1287 * doc/c-arm.texi (ARM-Instruction-Set): Likewise. Also add text
1288 to the @item directives.
1289 (ARM-Neon-Alignment): Move to correct place in the document.
1290 * doc/c-cr16.texi (CR16 Operand Qualifiers): Fix up table
1291 formatting.
1292 * doc/c-tic54x.texi (TIC54X-Subsyms): Correct use of
1293 @smallexample.
1294
531a94fd
SL
12952013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de>
1296
1297 * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o'
1298 case. Add default BAD_CASE to switch.
1299
dad60f8e
SL
13002013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1301
1302 * config/tc-nios2.c (nios2_assemble_args_ds): New function.
1303 (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries.
1304
dd5181d5
KT
13052013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1306
1307 * config/tc-arm.c (crc_ext_armv8): New feature set.
1308 (UNPRED_REG): New macro.
1309 (do_crc32_1): New function.
1310 (do_crc32b, do_crc32h, do_crc32w, do_crc32cb,
1311 do_crc32ch, do_crc32cw): Likewise.
1312 (TUEc): New macro.
1313 (insns): Add entries for crc32 mnemonics.
1314 (arm_extensions): Add entry for crc.
1315
8e723a10
CLT
13162013-03-08 Chung-Lin Tang <cltang@codesourcery.com>
1317
1318 * write.h (struct fix): Add fx_dot_frag field.
1319 (dot_frag): Declare.
1320 * write.c (dot_frag): New variable.
1321 (fix_new_internal): Set fx_dot_frag field with dot_frag.
1322 (fixup_segment): Base calculation of fx_offset with fx_dot_frag.
1323 * expr.c (expr): Save value of frag_now in dot_frag when setting
1324 dot_value.
1325 * read.c (emit_expr): Likewise. Delete comments.
1326
be05d201
L
13272013-03-07 H.J. Lu <hongjiu.lu@intel.com>
1328
1329 * config/tc-i386.c (flag_code_names): Removed.
1330 (i386_index_check): Rewrote.
1331
62b0d0d5
YZ
13322013-03-05 Yufeng Zhang <yufeng.zhang@arm.com>
1333
1334 * config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern';
1335 add comment.
1336 (aarch64_double_precision_fmovable): New function.
1337 (parse_aarch64_imm_float): Add parameter 'dp_p'; call the new
1338 function; handle hexadecimal representation of IEEE754 encoding.
1339 (parse_operands): Update the call to parse_aarch64_imm_float.
1340
165de32a
L
13412013-02-28 H.J. Lu <hongjiu.lu@intel.com>
1342
1343 * config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix.
1344 (check_hle): Updated.
1345 (md_assemble): Likewise.
1346 (parse_insn): Likewise.
1347
d5de92cf
L
13482013-02-28 H.J. Lu <hongjiu.lu@intel.com>
1349
1350 * config/tc-i386.c (_i386_insn): Add rep_prefix.
9e6f3811 1351 (md_assemble): Check if REP prefix is OK.
d5de92cf
L
1352 (parse_insn): Remove expecting_string_instruction. Set
1353 i.rep_prefix.
1354
e60bb1dd
YZ
13552013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1356
1357 * config/tc-aarch64.c (aarch64_features): Add the 'crc' option.
1358
aeebdd9b
YZ
13592013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1360
1361 * config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
1362 for system registers.
1363
4107ae22
DD
13642013-02-27 DJ Delorie <dj@redhat.com>
1365
1366 * config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE.
1367 (rl78_op): Handle %code().
1368 (rl78_cons_fix_new): Likewise, but ignore for 20-bit operands.
1369 (tc_gen_reloc): Likwise; convert to a computed reloc.
1370 (md_apply_fix): Likewise.
1371
151fa98f
NC
13722013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1373
1374 * config/rl78-parse.y: Fix encoding of DIVWU insn.
1375
70a8bc5b 13762013-02-25 Terry Guo <terry.guo@arm.com>
1377
1378 * config/tc-arm.c (arm_cpus): Add cortex-r7 entry.
1379 * doc/c-arm.texi: Add cortex-r7 and missing cortex-r5 to
1380 list of accepted CPUs.
1381
5c111e37
L
13822013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1383
1384 PR gas/15159
1385 * config/tc-i386.c (cpu_arch): Add ".smap".
1386
1387 * doc/c-i386.texi: Document smap.
1388
8a75745d
MR
13892013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
1390
1391 * config/tc-mips.c (s_cpload): Call mips_mark_labels and set
1392 mips_assembling_insn appropriately.
1393 (s_cpsetup, s_cprestore, s_cpreturn, s_cpadd): Likewise.
1394
79850f26
MR
13952013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
1396
cf29fc61 1397 * config/tc-mips.c (append_insn): Correct indentation, remove
79850f26
MR
1398 extraneous braces.
1399
4c261dff
NC
14002013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1401
5c111e37 1402 * config/tc-arm.c (do_neon_mov): Break on NS_NULL.
4c261dff 1403
ea33f281
NC
14042013-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
1405
1406 * configure.tgt: Add nios2-*-rtems*.
1407
a1ccaec9
YZ
14082013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1409
1410 * config/tc-aarch64.c (md_begin): Change to check if 'name' is
1411 NULL.
1412
0aa27725
RS
14132013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1414
1415 * config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
1416 (macro): Use it. Assert that trunc.w.s is not used for r5900.
1417
da4339ed
NC
14182013-02-08 Yi-Hsiu, Hsu <ahsu@marvell.com>
1419
1420 * gas/config/tc-arm.c (arm_cpus): Add support for mcpu=marvell-pj4
1421 core.
1422
36591ba1 14232013-02-06 Sandra Loosemore <sandra@codesourcery.com>
5c111e37 1424 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL
1425
1426 Based on patches from Altera Corporation.
1427
1428 * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c.
1429 (TARGET_CPU_HFILES): Add config/tc-nios2.h.
1430 * Makefile.in: Regenerated.
1431 * configure.tgt: Add case for nios2*-linux*.
1432 * config/obj-elf.c: Conditionally include elf/nios2.h.
1433 * config/tc-nios2.c: New file.
1434 * config/tc-nios2.h: New file.
1435 * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi.
1436 * doc/Makefile.in: Regenerated.
1437 * doc/all.texi: Set NIOSII.
1438 * doc/as.texinfo (Overview): Add Nios II options.
1439 (Machine Dependencies): Include c-nios2.texi.
1440 * doc/c-nios2.texi: New file.
1441 * NEWS: Note Altera Nios II support.
1442
94d4433a
AM
14432013-02-06 Alan Modra <amodra@gmail.com>
1444
1445 PR gas/14255
1446 * config/tc-avr.h (TC_VALIDATE_FIX): Mark symbol used by reloc.
1447 Don't skip fixups with fx_subsy non-NULL.
1448 * config/tc-avr.c (tc_gen_reloc): Don't specially handle fixups
1449 with fx_subsy non-NULL.
1450
ace9af6f
L
14512013-02-04 H.J. Lu <hongjiu.lu@intel.com>
1452
1453 * doc/c-metag.texi: Add "@c man" markers.
1454
89d67ed9
AM
14552013-02-04 Alan Modra <amodra@gmail.com>
1456
1457 * write.c (fixup_segment): Return void. Delete seg_reloc_count
1458 related code.
1459 (TC_ADJUST_RELOC_COUNT): Delete.
1460 * config/tc-i960.h (TC_ADJUST_RELOC_COUNT): Delete.
1461
89072bd6
AM
14622013-02-04 Alan Modra <amodra@gmail.com>
1463
1464 * po/POTFILES.in: Regenerate.
1465
f9b2d544
NC
14662013-01-30 Markos Chandras <markos.chandras@imgtec.com>
1467
1468 * config/tc-metag.c: Make SWAP instruction less permissive with
1469 its operands.
1470
392ca752
DD
14712013-01-29 DJ Delorie <dj@redhat.com>
1472
1473 * config/tc-rl78.c (rl78_cons_fix_new): Handle user-specified
1474 relocs in .word/.etc statements.
1475
427d0db6
RM
14762013-01-29 Roland McGrath <mcgrathr@google.com>
1477
1478 * config/tc-arm.c (md_apply_fix): Use as_bad_where for "bad
1479 immediate value for 8-bit offset" error so it shows line info.
1480
4faf939a
JM
14812013-01-24 Joseph Myers <joseph@codesourcery.com>
1482
1483 * config/tc-ppc.c (md_assemble): Do not generate APUinfo sections
1484 for 64-bit output.
1485
78c8d46c
NC
14862013-01-24 Nick Clifton <nickc@redhat.com>
1487
1488 * config/tc-v850.c: Add support for e3v5 architecture.
1489 * doc/c-v850.texi: Mention new support.
1490
fb5b7503
NC
14912013-01-23 Nick Clifton <nickc@redhat.com>
1492
1493 PR gas/15039
1494 * config/tc-avr.c: Include dwarf2dbg.h.
1495
8ce3d284
L
14962013-01-18 H.J. Lu <hongjiu.lu@intel.com>
1497
1498 * config/tc-i386.c (reloc): Support size relocation only for ELF.
1499 (tc_i386_fix_adjustable): Likewise.
1500 (lex_got): Likewise.
1501 (tc_gen_reloc): Likewise.
1502
f5555712
YZ
15032013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1504
1505 * config/tc-aarch64.c (output_operand_error_record): Change to output
1506 the out-of-range error message as value-expected message if there is
1507 only one single value in the expected range.
1508 (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
1509 LSL #0 as a programmer-friendly feature.
1510
8fd4256d
L
15112013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1512
1513 * config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32.
1514 (tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and
1515 BFD_RELOC_64_SIZE relocations.
1516 (lex_got): Support "symbol@SIZE" and don't create GOT symbol
1517 for it.
1518 (tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64
1519 relocations against local symbols.
1520
a5840dce
AM
15212013-01-16 Alan Modra <amodra@gmail.com>
1522
1523 * config/tc-ppc.c (md_assemble <TE_PE>): Ignore line after
1524 finding some sort of toc syntax error, and break to avoid
1525 compiler uninit warning.
1526
af89796a
L
15272013-01-15 H.J. Lu <hongjiu.lu@intel.com>
1528
1529 PR gas/15019
1530 * config/tc-i386.c (lex_got): Increment length by 1 if the
1531 relocation token is removed.
1532
dd42f060
NC
15332013-01-15 Nick Clifton <nickc@redhat.com>
1534
1535 * config/tc-v850.c (md_assemble): Allow signed values for
1536 V850E_IMMEDIATE.
1537
464e3686
SK
15382013-01-11 Sean Keys <skeys@ipdatasys.com>
1539
1540 * config/tc-xgate.c (md_begin): Fix mistake made when going from
af89796a 1541 git to cvs.
464e3686 1542
5817ffd1
PB
15432013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1544
1545 * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
1546 * doc/c-ppc.texi (PowerPC-Opts): Likewise.
1547 * config/tc-ppc.c (md_show_usage): Likewise.
1548 (ppc_handle_align): Handle power8's group ending nop.
1549
f4b1f6a9
SK
15502013-01-10 Sean Keys <skeys@ipdatasys.com>
1551
1552 * config/tc-xgate.c (md_begin): Fix the printing of opcodes so
af89796a 1553 that the assember exits after the opcodes have been printed.
f4b1f6a9 1554
34bca508
L
15552013-01-10 H.J. Lu <hongjiu.lu@intel.com>
1556
1557 * app.c: Remove trailing white spaces.
1558 * as.c: Likewise.
1559 * as.h: Likewise.
1560 * cond.c: Likewise.
1561 * dw2gencfi.c: Likewise.
1562 * dwarf2dbg.h: Likewise.
1563 * ecoff.c: Likewise.
1564 * input-file.c: Likewise.
1565 * itbl-lex.h: Likewise.
1566 * output-file.c: Likewise.
1567 * read.c: Likewise.
1568 * sb.c: Likewise.
1569 * subsegs.c: Likewise.
1570 * symbols.c: Likewise.
1571 * write.c: Likewise.
1572 * config/tc-i386.c: Likewise.
1573 * doc/Makefile.am: Likewise.
1574 * doc/Makefile.in: Likewise.
1575 * doc/c-aarch64.texi: Likewise.
1576 * doc/c-alpha.texi: Likewise.
1577 * doc/c-arc.texi: Likewise.
1578 * doc/c-arm.texi: Likewise.
1579 * doc/c-avr.texi: Likewise.
1580 * doc/c-bfin.texi: Likewise.
1581 * doc/c-cr16.texi: Likewise.
1582 * doc/c-d10v.texi: Likewise.
1583 * doc/c-d30v.texi: Likewise.
1584 * doc/c-h8300.texi: Likewise.
1585 * doc/c-hppa.texi: Likewise.
1586 * doc/c-i370.texi: Likewise.
1587 * doc/c-i386.texi: Likewise.
1588 * doc/c-i860.texi: Likewise.
1589 * doc/c-m32c.texi: Likewise.
1590 * doc/c-m32r.texi: Likewise.
1591 * doc/c-m68hc11.texi: Likewise.
1592 * doc/c-m68k.texi: Likewise.
1593 * doc/c-microblaze.texi: Likewise.
1594 * doc/c-mips.texi: Likewise.
1595 * doc/c-msp430.texi: Likewise.
1596 * doc/c-mt.texi: Likewise.
1597 * doc/c-s390.texi: Likewise.
1598 * doc/c-score.texi: Likewise.
1599 * doc/c-sh.texi: Likewise.
1600 * doc/c-sh64.texi: Likewise.
1601 * doc/c-tic54x.texi: Likewise.
1602 * doc/c-tic6x.texi: Likewise.
1603 * doc/c-v850.texi: Likewise.
1604 * doc/c-xc16x.texi: Likewise.
1605 * doc/c-xgate.texi: Likewise.
1606 * doc/c-xtensa.texi: Likewise.
1607 * doc/c-z80.texi: Likewise.
1608 * doc/internals.texi: Likewise.
1609
4c665b71
RM
16102013-01-10 Roland McGrath <mcgrathr@google.com>
1611
1612 * hash.c (hash_new_sized): Make it global.
1613 * hash.h: Declare it.
1614 * macro.c (define_macro): Use hash_new_sized instead of hash_new,
1615 pass a small size.
1616
a3c62988
NC
16172013-01-10 Will Newton <will.newton@imgtec.com>
1618
1619 * Makefile.am: Add Meta.
1620 * Makefile.in: Regenerate.
1621 * config/tc-metag.c: New file.
1622 * config/tc-metag.h: New file.
1623 * configure.tgt: Add Meta.
1624 * doc/Makefile.am: Add Meta.
1625 * doc/Makefile.in: Regenerate.
1626 * doc/all.texi: Add Meta.
1627 * doc/as.texiinfo: Document Meta options.
1628 * doc/c-metag.texi: New file.
1629
b37df7c4
SE
16302013-01-09 Steve Ellcey <sellcey@mips.com>
1631
1632 * config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal
1633 calls.
1634 * config/tc-mips.c (internalError): Remove, replace with abort.
1635
a3251895
YZ
16362013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
1637
1638 * config/tc-aarch64.c (parse_operands): Change to compare the result
1639 of function call 'parse_sys_reg' with 'PARSE_FAIL' instead of 'FALSE'.
1640
8ab8155f
NC
16412013-01-07 Nick Clifton <nickc@redhat.com>
1642
1643 PR gas/14887
1644 * config/tc-arm.c (skip_past_char): Skip whitespace before the
1645 anticipated character.
1646 * config/tc-arm.c (parse_address_main): Delete skip of whitespace
1647 here as it is no longer needed.
1648
a4ac1c42
AS
16492013-01-06 Andreas Schwab <schwab@linux-m68k.org>
1650
1651 * doc/c-mips.texi (MIPS Opts): Fix use of @itemx.
1652 * doc/c-score.texi (SCORE-Opts): Likewise.
1653 * doc/c-tic54x.texi (TIC54X-Directives): Likewise.
1654
e407c74b
NC
16552013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1656
1657 * config/tc-mips.c: Add support for MIPS r5900.
1658 Add M_LQ_AB and M_SQ_AB to support large values for instructions
1659 lq and sq.
1660 (can_swap_branch_p, get_append_method): Detect some conditional
1661 short loops to fix a bug on the r5900 by NOP in the branch delay
1662 slot.
1663 (M_MUL): Support 3 operands in multu on r5900.
1664 (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
1665 (s_mipsset): Force 32 bit floating point on r5900.
1666 (mips_ip): Check parameter range of instructions mfps and mtps on
1667 r5900.
1668 * configure.in: Detect CPU type when target string contains r5900
1669 (e.g. mips64r5900el-linux-gnu).
1670
62658407
L
16712013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1672
1673 * as.c (parse_args): Update copyright year to 2013.
1674
95830fd1
YZ
16752013-01-02 Yufeng Zhang <yufeng.zhang@arm.com>
1676
1677 * config/tc-aarch64.c (aarch64_cpus): Add entries for "cortex-a53"
1678 and "cortex57".
1679
517bb291 16802013-01-02 Nick Clifton <nickc@redhat.com>
d709e4e6 1681
517bb291
NC
1682 PR gas/14987
1683 * config/tc-arm.c (parse_address_main): Skip whitespace before a
1684 closing bracket.
d709e4e6 1685
517bb291 1686For older changes see ChangeLog-2012
08d56133 1687\f
517bb291 1688Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC
1689
1690Copying and distribution of this file, with or without modification,
1691are permitted in any medium without royalty provided the copyright
1692notice and this notice are preserved.
1693
08d56133
NC
1694Local Variables:
1695mode: change-log
1696left-margin: 8
1697fill-column: 74
1698version-control: never
1699End: