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cc537e56
RS		 12013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * config/tc-mips.c (mips16_ip): Handle "I".
4
ba92f887
MR		 52013-07-12 Maciej W. Rozycki <macro@codesourcery.com>
6
7 * config/tc-mips.c (mips_flag_nan2008): New variable.
8 (options): Add OPTION_NAN enum value.
9 (md_longopts): Handle it.
10 (md_parse_option): Likewise.
11 (s_nan): New function.
12 (mips_elf_final_processing): Handle EF_MIPS_NAN2008.
13 (md_show_usage): Add -mnan.
14
15 * doc/as.texinfo (Overview): Add -mnan.
16 * doc/c-mips.texi (MIPS Opts): Document -mnan.
17 (MIPS NaN Encodings): New node. Document .nan directive.
18 (MIPS-Dependent): List the new node.
19
c1094734
TG		 202013-07-09 Tristan Gingold <gingold@adacore.com>
21
22 * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
23
0cbbe1b8
RS		 242013-07-08 Richard Sandiford <rdsandiford@googlemail.com>
25
26 * config/tc-mips.c (mips_ip): Unconditionally parse an expression
27 for 'A' and assume that the constant has been elided if the result
28 is an O_register.
29
f2ae14a1
RS		 302013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
31
32 * config/tc-mips.c (gprel16_reloc_p): New function.
33 (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
34 BFD_RELOC_UNUSED.
35 (offset_high_part, small_offset_p): New functions.
36 (nacro): Use them. Remove *_OB and *_DOB cases. For single-
37 register load and store macros, handle the 16-bit offset case first.
38 If a 16-bit offset is not suitable for the instruction we're
39 generating, load it into the temporary register using
40 ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
41 M_L_DAB code once the address has been constructed. For double load
42 and store macros, again handle the 16-bit offset case first.
43 If the second register cannot be accessed from the same high
44 part as the first, load it into AT using ADDRESS_ADDI_INSN.
45 Fix the handling of LD in cases where the first register is the
46 same as the base. Also handle the case where the offset is
47 not 16 bits and the second register cannot be accessed from the
48 same high part as the first. For unaligned loads and stores,
49 fuse the offbits == 12 and old "ab" handling. Apply this handling
50 whenever the second offset needs a different high part from the first.
51 Construct the offset using ADDRESS_ADDI_INSN where possible,
52 for offbits == 16 as well as offbits == 12. Use offset_reloc
53 when constructing the individual loads and stores.
54 (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
55 and offset_reloc before matching against a particular opcode.
56 Handle elided 'A' constants. Allow 'A' constants to use
57 relocation operators.
58
5c324c16
RS		 592013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
60
61 * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
62 (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
63 Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
64
23e69e47
RS		 652013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
66
67 * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
68 Require the msb to be <= 31 for "+s". Check that the size is <= 31
69 for both "+s" and "+S".
70
27c5c572
RS		 712013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
72
73 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
74 (mips_ip, mips16_ip): Handle "+i".
75
e76ff5ab
RS		 762013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
77
78 * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
79 (micromips_to_32_reg_h_map): Rename to...
80 (micromips_to_32_reg_h_map1): ...this.
81 (micromips_to_32_reg_i_map): Rename to...
82 (micromips_to_32_reg_h_map2): ...this.
83 (mips_lookup_reg_pair): New function.
84 (gpr_write_mask, macro): Adjust after above renaming.
85 (validate_micromips_insn): Remove "mi" handling.
86 (mips_ip): Likewise. Parse both registers in a pair for "mh".
87
fa7616a4
RS		 882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
89
90 * config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
91 (mips_ip): Remove "+D" and "+T" handling.
92
fb798c50
AK		 932013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
94
95 * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
96 relocs.
97
2c0a3565
MS		 982013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
99
4aa2c5e2
MS		 100 * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
101
1022013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
103
2c0a3565
MS		 104 * config/tc-aarch64.c (md_apply_fix): Reorder case values.
105 (aarch64_force_relocation): Likewise.
106
f40da81b
AM		 1072013-07-02 Alan Modra <amodra@gmail.com>
108
109 * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
110
81566a9b
MR		 1112013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
112
113 * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
114 * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
115 Replace @sc{mips16} with literal `MIPS16'.
116 (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
117
a6bb11b2
YZ		 1182013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
119
120 * config/tc-aarch64.c (reloc_table): Replace
121 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
122 BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
123 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
124 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
125 (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
126 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
127 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
128 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
129 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
130 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
131 (aarch64_force_relocation): Likewise.
132
cec5225b
YZ		 1332013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
134
135 * config/tc-aarch64.c (ilp32_p): New static variable.
136 (elf64_aarch64_target_format): Return the target according to the
137 value of 'ilp32_p'.
138 (md_begin): Determine 'mach' according to the value of 'ilp32_p'.
139 (aarch64_opts): Add support for options '-milp32' and '-mlp64'.
140 (aarch64_dwarf2_addr_size): New function.
141 * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
142 (DWARF2_ADDR_SIZE): New define.
143
e335d9cb
RS		 1442013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
145
146 * doc/c-mips.texi: Use ISA instead of @sc{isa}.
147
18870af7
RS		 1482013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
149
150 * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
151
833794fc
MR		 1522013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
153
154 * config/tc-mips.c (mips_set_options): Add insn32 member.
155 (mips_opts): Initialize it.
156 (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
157 (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
158 (md_longopts): Add "minsn32" and "mno-insn32" options.
159 (is_size_valid): Handle insn32 mode.
160 (md_assemble): Pass instruction string down to macro.
161 (brk_fmt): Add second dimension and insn32 mode initializers.
162 (mfhl_fmt): Likewise.
163 (BRK_FMT, MFHL_FMT): Handle insn32 mode.
164 (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
165 (macro_build_jalr, move_register): Handle insn32 mode.
166 (macro_build_branch_rs): Likewise.
167 (macro): Handle insn32 mode.
168 <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
169 (mips_ip): Handle insn32 mode.
170 (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
171 (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
172 (mips_handle_align): Handle insn32 mode.
173 (md_show_usage): Add -minsn32 and -mno-insn32.
174
175 * doc/as.texinfo (Target MIPS options): Add -minsn32 and
176 -mno-insn32 options.
177 (-minsn32, -mno-insn32): New options.
178 * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
179 options.
180 (MIPS assembly options): New node. Document .set insn32 and
181 .set noinsn32.
182 (MIPS-Dependent): List the new node.
183
d1706f38
NC		 1842013-06-25 Nick Clifton <nickc@redhat.com>
185
186 * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
187 the PC in indirect addressing on 430xv2 parts.
188 (msp430_operands): Add version test to hardware bug encoding
189 restrictions.
190
477330fc
RM		 1912013-06-24 Roland McGrath <mcgrathr@google.com>
192
d996d970
RM		 193 * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
194 so it skips whitespace before it.
195 (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
196
477330fc
RM		 197 * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
198 (arm_reg_parse_multi): Skip whitespace first.
199 (parse_reg_list): Likewise.
200 (parse_vfp_reg_list): Likewise.
201 (s_arm_unwind_save_mmxwcg): Likewise.
202
24382199
NC		 2032013-06-24 Nick Clifton <nickc@redhat.com>
204
205 PR gas/15623
206 * config/tc-arm.c (do_t_smc): Mark as ending an IT block.
207
c3678916
RS		 2082013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
209
210 * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
211
42429eac
RS		 2122013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
213
214 * config/tc-mips.c: Assert that offsetT and valueT are at least
215 8 bytes in size.
216 (GPR_SMIN, GPR_SMAX): New macros.
217 (macro, mips_ip): Remove code for 4-byte valueT and offsetT.
218
f3ded42a
RS		 2192013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
220
221 * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
222 conditions. Remove any code deselected by them.
223 (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
224
e8044f35
RS		 2252013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
226
227 * NEWS: Note removal of ECOFF support.
228 * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
229 * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
230 (MULTI_CFILES): Remove config/e-mipsecoff.c.
231 * Makefile.in: Regenerate.
232 * configure.in: Remove MIPS ECOFF references.
233 (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
234 Delete cases.
235 (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
236 (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
237 (mips-*-*): ...this single case.
238 (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
239 MIPS emulations to be e-mipself*.
240 * configure: Regenerate.
241 * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
242 (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
243 (mips-*-sysv*): Remove coff and ecoff cases.
244 * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
245 * ecoff.c: Remove reference to MIPS ECOFF.
246 * config/e-mipsecoff.c, config/te-lnews.h: Delete files.
247 * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
248 (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
249 (mips_hi_fixup): Tweak comment.
250 (append_insn): Require a howto.
251 (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
252
98508b2a
RS		 2532013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
254
255 * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
256 Use "CPU" instead of "cpu".
257 * doc/c-mips.texi: Likewise.
258 (MIPS Opts): Rename to MIPS Options.
259 (MIPS option stack): Rename to MIPS Option Stack.
260 (MIPS ASE instruction generation overrides): Rename to
261 MIPS ASE Instruction Generation Overrides (for now).
262 (MIPS floating-point): Rename to MIPS Floating-Point.
263
fc16f8cc
RS		 2642013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
265
266 * doc/c-mips.texi (MIPS Macros): New section.
267 (MIPS Object): Replace with...
268 (MIPS Small Data): ...this new section.
269
5a7560b5
RS		 2702013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
271
272 * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
273 Capitalize name. Use @kindex instead of @cindex for .set entries.
274
a1b86ab7
RS		 2752013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
276
277 * doc/c-mips.texi (MIPS Stabs): Remove section.
278
c6278170
RS		 2792013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
280
281 * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
282 (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
283 (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
284 (ISA_SUPPORTS_VIRT64_ASE): Delete.
285 (mips_ase): New structure.
286 (mips_ases): New table.
287 (FP64_ASES): New macro.
288 (mips_ase_groups): New array.
289 (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
290 (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
291 functions.
292 (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
293 (md_parse_option): Use mips_ases and mips_set_ase instead of
294 separate case statements for each ASE option.
295 (mips_after_parse_args): Use FP64_ASES. Use
296 mips_check_isa_supports_ases to check the ASEs against
297 other options.
298 (s_mipsset): Use mips_ases and mips_set_ase instead of
299 separate if statements for each ASE option. Use
300 mips_check_isa_supports_ases, even when a non-ASE option
301 is specified.
302
63a4bc21
KT		 3032013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
304
305 * config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
306
c31f3936
RS		 3072013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
308
309 * config/tc-mips.c (md_shortopts, options, md_longopts)
310 (md_longopts_size): Move earlier in file.
311
846ef2d0
RS		 3122013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
313
314 * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
315 with a single "ase" bitmask.
316 (mips_opts): Update accordingly.
317 (file_ase, file_ase_explicit): New variables.
318 (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
319 (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
320 (ISA_HAS_ROR): Adjust for mips_set_options change.
321 (is_opcode_valid): Take the base ase mask directly from mips_opts.
322 (mips_ip): Adjust for mips_set_options change.
323 (md_parse_option): Likewise. Update file_ase_explicit.
324 (mips_after_parse_args): Adjust for mips_set_options change.
325 Use bitmask operations to select the default ASEs. Set file_ase
326 rather than individual per-ASE variables.
327 (s_mipsset): Adjust for mips_set_options change.
328 (mips_elf_final_processing): Test file_ase rather than
329 file_ase_mdmx. Remove commented-out code.
330
d16afab6
RS		 3312013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
332
333 * config/tc-mips.c (mips_cpu_info): Add an "ase" field.
334 (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
335 (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
336 (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
337 (mips_after_parse_args): Use the new "ase" field to choose
338 the default ASEs.
339 (mips_cpu_info_table): Move ASEs from the "flags" field to the
340 "ase" field.
341
e83a675f
RE		 3422013-06-18 Richard Earnshaw <rearnsha@arm.com>
343
344 * config/tc-arm.c (symbol_preemptible): New function.
345 (relax_branch): Use it.
346
7f3c4072
CM		 3472013-06-17 Catherine Moore <clm@codesourcery.com>
348 Maciej W. Rozycki <macro@codesourcery.com>
349 Chao-Ying Fu <fu@mips.com>
350
351 * config/tc-mips.c (mips_set_options): Add ase_eva.
352 (mips_set_options mips_opts): Add ase_eva.
353 (file_ase_eva): Declare.
354 (ISA_SUPPORTS_EVA_ASE): Define.
355 (IS_SEXT_9BIT_NUM): Define.
356 (MIPS_CPU_ASE_EVA): Define.
357 (is_opcode_valid): Add support for ase_eva.
358 (macro_build): Likewise.
359 (macro): Likewise.
360 (validate_mips_insn): Likewise.
361 (validate_micromips_insn): Likewise.
362 (mips_ip): Likewise.
363 (options): Add OPTION_EVA and OPTION_NO_EVA.
364 (md_longopts): Add -meva and -mno-eva.
365 (md_parse_option): Process new options.
366 (mips_after_parse_args): Check for valid EVA combinations.
367 (s_mipsset): Likewise.
368
e410add4
RS		 3692013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
370
371 * dwarf2dbg.h (dwarf2_move_insn): Declare.
372 * dwarf2dbg.c (line_subseg): Add pmove_tail.
373 (get_line_subseg): Add create_p argument. Initialize pmove_tail.
374 (dwarf2_gen_line_info_1): Update call accordingly.
375 (dwarf2_move_insn): New function.
376 * config/tc-mips.c (append_insn): Use dwarf2_move_insn.
377
6a50d470
RS		 3782013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
379
380 Revert:
381
382 2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
383
384 PR gas/13024
385 * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
386 (dwarf2_gen_line_info_1): Delete.
387 (dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
388 (dwarf2_gen_line_info, dwarf2_emit_label): Use them.
389 (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
390 (dwarf2_directive_loc): Push previous .locs instead of generating
391 them immediately.
392
f122319e
CF		 3932013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
394
395 * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
396 (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
397
909c7f9c
NC		 3982013-06-13 Nick Clifton <nickc@redhat.com>
399
400 PR gas/15602
401 * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
402 * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
403 function. Generates an error if the adjusted offset is out of a
404 16-bit range.
405
5d5755a7
SL		 4062013-06-12 Sandra Loosemore <sandra@codesourcery.com>
407
408 * config/tc-nios2.c (md_apply_fix): Mask constant
409 BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
410
3bf0dbfb
MR		 4112013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
412
413 * config/tc-mips.c (append_insn): Don't do branch relaxation for
414 MIPS-3D instructions either.
415 (md_convert_frag): Update the COPx branch mask accordingly.
416
417 * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
418 option.
419 * doc/as.texinfo (Overview): Add --relax-branch and
420 --no-relax-branch.
421 * doc/c-mips.texi (MIPS Opts): Document --relax-branch and
422 --no-relax-branch.
423
9daf7bab
SL		 4242013-06-09 Sandra Loosemore <sandra@codesourcery.com>
425
426 * config/tc-nios2.c (nios2_parse_args): Allow trap argument to
427 omitted.
428
d301a56b
RS		 4292013-06-08 Catherine Moore <clm@codesourcery.com>
430
431 * config/tc-mips.c (is_opcode_valid): Build ASE mask.
432 (is_opcode_valid_16): Pass ase value to opcode_is_member.
433 (append_insn): Change INSN_xxxx to ASE_xxxx.
434
7bab7634
DC		 4352013-06-01 George Thomas <george.thomas@atmel.com>
436
437 * gas/config/tc-avr.c: Change ISA for devices with USB support to
438 AVR_ISA_XMEGAU
439
f60cf82f
L		 4402013-05-31 H.J. Lu <hongjiu.lu@intel.com>
441
442 * config/tc-i386.c (md_begin): Don't align text/data/bss sections
443 for ELF.
444
a3f278e2
CM		 4452013-05-31 Paul Brook <paul@codesourcery.com>
446
447 gas/
448 * config/tc-mips.c (s_ehword): New.
449
067ec077
CM		 4502013-05-30 Paul Brook <paul@codesourcery.com>
451
452 * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH.
453
d6101ac2
MR		 4542013-05-29 Maciej W. Rozycki <macro@codesourcery.com>
455
456 * write.c (resolve_reloc_expr_symbols): On REL targets don't
457 convert relocs who have no relocatable field either. Rephrase
458 the conditional so that the PC-relative check is only applied
459 for REL targets.
460
f19ccbda
MR		 4612013-05-28 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
462
463 * config/tc-mips.c (macro) <ld>: Don't use $zero for address
464 calculation.
465
418009c2
YZ		 4662013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
467
468 * config/tc-aarch64.c (reloc_table): Update to use
477330fc 469 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
418009c2
YZ		 470 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
471 (md_apply_fix): Likewise.
472 (aarch64_force_relocation): Likewise.
473
0a8897c7
KT		 4742013-05-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
475
476 * config/tc-arm.c (it_fsm_post_encode): Improve
477 warning messages about deprecated IT block formats.
478
89d2a2a3
MS		 4792013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
480
481 * config/tc-aarch64.c (md_apply_fix): Move value range checking
482 inside fx_done condition.
483
c77c0862
RS		 4842013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
485
486 * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
487
c0637f3a
PB		 4882013-05-20 Peter Bergner <bergner@vnet.ibm.com>
489
490 * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
491 and clean up warning when using PRINT_OPCODE_TABLE.
492
5656a981
AM		 4932013-05-20 Alan Modra <amodra@gmail.com>
494
495 * config/tc-ppc.c (md_apply_fix): Hoist code common to insn
496 and data fixups performing shift/high adjust/sign extension on
497 fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
498 when writing data fixups rather than recalculating size.
499
997b26e8
JBG		 5002013-05-16 Jan-Benedict Glaw <jbglaw@lug-owl.de>
501
502 * doc/c-msp430.texi: Fix typo.
503
9f6e76f4
TG		 5042013-05-16 Tristan Gingold <gingold@adacore.com>
505
506 * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC
507 are also TOC symbols.
508
638d3803
NC		 5092013-05-16 Nick Clifton <nickc@redhat.com>
510
511 * config/tc-msp430.c: Make -mmcu recognise more part numbers.
512 Add -mcpu command to specify core type.
997b26e8 513 * doc/c-msp430.texi: Update documentation.
638d3803 514
b015e599
AP		 5152013-05-09 Andrew Pinski <apinski@cavium.com>
516
517 * config/tc-mips.c (struct mips_set_options): New ase_virt field.
518 (mips_opts): Update for the new field.
519 (file_ase_virt): New variable.
520 (ISA_SUPPORTS_VIRT_ASE): New macro.
521 (ISA_SUPPORTS_VIRT64_ASE): New macro.
522 (MIPS_CPU_ASE_VIRT): New define.
523 (is_opcode_valid): Handle ase_virt.
524 (macro_build): Handle "+J".
525 (validate_mips_insn): Likewise.
526 (mips_ip): Likewise.
527 (enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
528 (md_longopts): Add mvirt and mnovirt
529 (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
530 (mips_after_parse_args): Handle ase_virt field.
531 (s_mipsset): Handle "virt" and "novirt".
532 (mips_elf_final_processing): Add a comment about virt ASE might need
533 a new flag.
534 (md_show_usage): Print out the usage of -mvirt and mno-virt options.
535 * doc/c-mips.texi: Document -mvirt and -mno-virt.
536 Document ".set virt" and ".set novirt".
537
da8094d7
AM		 5382013-05-09 Alan Modra <amodra@gmail.com>
539
540 * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under
541 control of operand flag bits.
542
c5f8c205
AM		 5432013-05-07 Alan Modra <amodra@gmail.com>
544
545 * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro.
546 (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
547 (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
548 (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
549 (md_apply_fix): Set fx_no_overflow for assorted relocations.
550 Shift and sign-extend fieldval for use by some VLE reloc
551 operand->insert functions.
552
b47468a6
CM		 5532013-05-06 Paul Brook <paul@codesourcery.com>
554 Catherine Moore <clm@codesourcery.com>
555
c5f8c205
AM		 556 * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL.
557 (limited_pcrel_reloc_p): Likewise.
b47468a6
CM		 558 (md_apply_fix): Likewise.
559 (tc_gen_reloc): Likewise.
560
2de39019
CM		 5612013-05-06 Richard Sandiford <rdsandiford@googlemail.com>
562
563 * config/tc-mips.c (limited_pcrel_reloc_p): New function.
564 (mips_fix_adjustable): Adjust pc-relative check to use
565 limited_pc_reloc_p.
566
754e2bb9
RS		 5672013-05-02 Richard Sandiford <rdsandiford@googlemail.com>
568
569 * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
570 (s_mips_stab): Do not restrict to stabn only.
571
13761a11
NC		 5722013-05-02 Nick Clifton <nickc@redhat.com>
573
574 * config/tc-msp430.c: Add support for the MSP430X architecture.
575 Add code to insert a NOP instruction after any instruction that
576 might change the interrupt state.
577 Add support for the LARGE memory model.
578 Add code to initialise the .MSP430.attributes section.
579 * config/tc-msp430.h: Add support for the MSP430X architecture.
580 * doc/c-msp430.texi: Document the new -mL and -mN command line
581 options.
582 * NEWS: Mention support for the MSP430X architecture.
583
df26367c
MR		 5842013-05-01 Maciej W. Rozycki <macro@codesourcery.com>
585
586 * configure.tgt: Replace alpha*-*-linuxecoff* pattern with
587 alpha*-*-linux*ecoff*.
588
f02d8318
CF		 5892013-04-30 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
590
591 * config/tc-mips.c (mips_ip): Add sizelo.
592 For "+C", "+G", and "+H", set sizelo and compare against it.
593
b40bf0a2
NC		 5942013-04-29 Nick Clifton <nickc@redhat.com>
595
596 * as.c (Options): Add -gdwarf-sections.
597 (parse_args): Likewise.
598 * as.h (flag_dwarf_sections): Declare.
599 * dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes.
600 (process_entries): When -gdwarf-sections is enabled generate
601 fragmentary .debug_line sections.
602 (out_debug_line): Set the section for the .debug_line section end
603 symbol.
604 * doc/as.texinfo: Document -gdwarf-sections.
605 * NEWS: Mention -gdwarf-sections.
606
8eeccb77 6072013-04-26 Christian Groessler <chris@groessler.org>
00a3147e
CG		 608
609 * config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline
610 according to the target parameter. Don't call s_segm since s_segm
611 calls bfd_set_arch_mach using stdoutput, but stdoutput isn't
612 initialized yet.
613 (md_begin): Call s_segm according to target parameter from command
614 line.
615
49926cd0
AM		 6162013-04-25 Alan Modra <amodra@gmail.com>
617
618 * configure.in: Allow little-endian linux.
619 * configure: Regenerate.
620
e3031850
SL		 6212013-04-24 Sandra Loosemore <sandra@codesourcery.com>
622
623 * config/tc-nios2.c (nios2_control_register_arg_p): Rename
624 "fstatus" control register to "eccinj".
625
cb948fc0
KT		 6262013-04-19 Kai Tietz <ktietz@redhat.com>
627
628 * configure.tgt (i386-*-cygwin): Handle x86_64 cygwin.
629
4455e9ad
JB		 6302013-04-15 Julian Brown <julian@codesourcery.com>
631
632 * expr.c (add_to_result, subtract_from_result): Make global.
633 * expr.h (add_to_result, subtract_from_result): Add prototypes.
634 * config/tc-sh.c (sh_optimize_expr): Use add_to_result,
635 subtract_from_result to handle extra bit of precision for .sleb128
636 directive operands.
637
956a6ba3
JB		 6382013-04-10 Julian Brown <julian@codesourcery.com>
639
640 * read.c (convert_to_bignum): Add sign parameter. Use it
641 instead of X_unsigned to determine sign of resulting bignum.
642 (emit_expr): Pass extra argument to convert_to_bignum.
643 (emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass
644 X_extrabit to convert_to_bignum.
645 (parse_bitfield_cons): Set X_extrabit.
646 * expr.c (make_expr_symbol, expr_build_uconstant, operand):
647 Initialise X_extrabit field as appropriate.
648 (add_to_result): New.
649 (subtract_from_result): New.
650 (expr): Use above.
651 * expr.h (expressionS): Add X_extrabit field.
652
eb9f3f00
JB		 6532013-04-10 Jan Beulich <jbeulich@suse.com>
654
655 * gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
656 register being PC when is_t or writeback, and use distinct
657 diagnostic for the latter case.
658
ccb84d65
JB		 6592013-04-10 Jan Beulich <jbeulich@suse.com>
660
661 * gas/config/tc-arm.c (parse_operands): Re-write
662 po_barrier_or_imm().
663 (do_barrier): Remove bogus constraint().
664 (do_t_barrier): Remove.
665
4d13caa0
NC		 6662013-04-09 Joerg Wunsch <joerg.wunsch@atmel.com>
667
668 * gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2,
669 ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2,
670 ATmega2564RFR2
671 * gas/doc/c-avr.texi (-mmcu documentation): Likewise.
672
16d02dc9
JB		 6732013-04-09 Jan Beulich <jbeulich@suse.com>
674
675 * gas/config/tc-arm.c (do_vmrs): Accept all control registers.
676 Use local variable Rt in more places.
677 (do_vmsr): Accept all control registers.
678
05ac0ffb
JB		 6792013-04-09 Jan Beulich <jbeulich@suse.com>
680
681 * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
682 if there was none specified for moves between scalar and core
683 register.
684
2d51fb74
JB		 6852013-04-09 Jan Beulich <jbeulich@suse.com>
686
687 * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
688 NEON_ALL_LANES case.
689
94dcf8bf
JB		 6902013-04-08 Jan Beulich <jbeulich@suse.com>
691
692 * gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for
693 PC-relative VSTR.
694
1472d06f
JB		 6952013-04-08 Jan Beulich <jbeulich@suse.com>
696
697 * gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq
698 entry to sp_fiq.
699
0c76cae8
AM		 7002013-04-03 Alan Modra <amodra@gmail.com>
701
702 * doc/as.texinfo: Add support to generate man options for h8300.
703 * doc/c-h8300.texi: Likewise.
704
92eb40d9
RR		 7052013-03-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
706
707 * config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and
708 Cortex-A57.
709
51dcdd4d
NC		 7102013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
711
712 PR binutils/15068
713 * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
714
c5d685bf
NC		 7152013-03-26 Nick Clifton <nickc@redhat.com>
716
9b978282
NC		 717 PR gas/15295
718 * listing.c (rebuffer_line): Rewrite to avoid seeking back to the
719 start of the file each time.
720
c5d685bf
NC		 721 PR gas/15178
722 * config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for
723 FreeBSD targets.
724
9699c833
TG		 7252013-03-26 Douglas B Rupp <rupp@gnat.com>
726
727 * config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
728 after fixup.
729
4755303e
WN		 7302013-03-21 Will Newton <will.newton@linaro.org>
731
732 * config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
733 pc-relative str instructions in Thumb mode.
734
81f5558e
NC		 7352013-03-21 Michael Schewe <michael.schewe@gmx.net>
736
737 * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov
738 @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc
739 R_H8_DISP32A16.
740 * config/tc-h8300.h: Remove duplicated defines.
741
71863e73
NC		 7422013-03-21 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
743
744 PR gas/15282
745 * tc-avr.c (mcu_has_3_byte_pc): New function.
746 (tc_cfi_frame_initial_instructions): Call it to find return
747 address size.
748
795b8e6b
NC		 7492013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
750
751 PR gas/15095
752 * config/tc-tic6x.c (tic6x_try_encode): Handle
753 tic6x_coding_dreg_(msb|lsb) field coding types and use it to
754 encode register pair numbers when required.
755
ba86b375
WN		 7562013-03-15 Will Newton <will.newton@linaro.org>
757
758 * config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register
759 in vstr in Thumb mode for pre-ARMv7 cores.
760
9e6f3811
AS		 7612013-03-14 Andreas Schwab <schwab@suse.de>
762
763 * doc/c-arc.texi (ARC Directives): Revert last change and use
764 @itemize instead of @table.
765 * doc/c-arm.texi (ARM-Instruction-Set): Likewise.
766
b10bf8c5
NC		 7672013-03-14 Nick Clifton <nickc@redhat.com>
768
769 PR gas/15273
770 * config/tc-arm.c (do_co_reg): Do not call check_obsolete with a
771 NULL message, instead just check ARM_CPU_IS_ANY directly.
772
ba724cfc
NC		 7732013-03-14 Nick Clifton <nickc@redhat.com>
774
775 PR gas/15212
9e6f3811 776 * doc/c-arc.texi (ARC Directives): Use @code instead of @bullet
ba724cfc
NC		 777 for table format.
778 * doc/c-arm.texi (ARM-Instruction-Set): Likewise. Also add text
779 to the @item directives.
780 (ARM-Neon-Alignment): Move to correct place in the document.
781 * doc/c-cr16.texi (CR16 Operand Qualifiers): Fix up table
782 formatting.
783 * doc/c-tic54x.texi (TIC54X-Subsyms): Correct use of
784 @smallexample.
785
531a94fd
SL		 7862013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de>
787
788 * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o'
789 case. Add default BAD_CASE to switch.
790
dad60f8e
SL		 7912013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
792
793 * config/tc-nios2.c (nios2_assemble_args_ds): New function.
794 (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries.
795
dd5181d5
KT		 7962013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
797
798 * config/tc-arm.c (crc_ext_armv8): New feature set.
799 (UNPRED_REG): New macro.
800 (do_crc32_1): New function.
801 (do_crc32b, do_crc32h, do_crc32w, do_crc32cb,
802 do_crc32ch, do_crc32cw): Likewise.
803 (TUEc): New macro.
804 (insns): Add entries for crc32 mnemonics.
805 (arm_extensions): Add entry for crc.
806
8e723a10
CLT		 8072013-03-08 Chung-Lin Tang <cltang@codesourcery.com>
808
809 * write.h (struct fix): Add fx_dot_frag field.
810 (dot_frag): Declare.
811 * write.c (dot_frag): New variable.
812 (fix_new_internal): Set fx_dot_frag field with dot_frag.
813 (fixup_segment): Base calculation of fx_offset with fx_dot_frag.
814 * expr.c (expr): Save value of frag_now in dot_frag when setting
815 dot_value.
816 * read.c (emit_expr): Likewise. Delete comments.
817
be05d201
L		 8182013-03-07 H.J. Lu <hongjiu.lu@intel.com>
819
820 * config/tc-i386.c (flag_code_names): Removed.
821 (i386_index_check): Rewrote.
822
62b0d0d5
YZ		 8232013-03-05 Yufeng Zhang <yufeng.zhang@arm.com>
824
825 * config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern';
826 add comment.
827 (aarch64_double_precision_fmovable): New function.
828 (parse_aarch64_imm_float): Add parameter 'dp_p'; call the new
829 function; handle hexadecimal representation of IEEE754 encoding.
830 (parse_operands): Update the call to parse_aarch64_imm_float.
831
165de32a
L		 8322013-02-28 H.J. Lu <hongjiu.lu@intel.com>
833
834 * config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix.
835 (check_hle): Updated.
836 (md_assemble): Likewise.
837 (parse_insn): Likewise.
838
d5de92cf
L		 8392013-02-28 H.J. Lu <hongjiu.lu@intel.com>
840
841 * config/tc-i386.c (_i386_insn): Add rep_prefix.
9e6f3811 842 (md_assemble): Check if REP prefix is OK.
d5de92cf
L		 843 (parse_insn): Remove expecting_string_instruction. Set
844 i.rep_prefix.
845
e60bb1dd
YZ		 8462013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
847
848 * config/tc-aarch64.c (aarch64_features): Add the 'crc' option.
849
aeebdd9b
YZ		 8502013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
851
852 * config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
853 for system registers.
854
4107ae22
DD		 8552013-02-27 DJ Delorie <dj@redhat.com>
856
857 * config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE.
858 (rl78_op): Handle %code().
859 (rl78_cons_fix_new): Likewise, but ignore for 20-bit operands.
860 (tc_gen_reloc): Likwise; convert to a computed reloc.
861 (md_apply_fix): Likewise.
862
151fa98f
NC		 8632013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
864
865 * config/rl78-parse.y: Fix encoding of DIVWU insn.
866
70a8bc5b 8672013-02-25 Terry Guo <terry.guo@arm.com>
868
869 * config/tc-arm.c (arm_cpus): Add cortex-r7 entry.
870 * doc/c-arm.texi: Add cortex-r7 and missing cortex-r5 to
871 list of accepted CPUs.
872
5c111e37
L		 8732013-02-19 H.J. Lu <hongjiu.lu@intel.com>
874
875 PR gas/15159
876 * config/tc-i386.c (cpu_arch): Add ".smap".
877
878 * doc/c-i386.texi: Document smap.
879
8a75745d
MR		 8802013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
881
882 * config/tc-mips.c (s_cpload): Call mips_mark_labels and set
883 mips_assembling_insn appropriately.
884 (s_cpsetup, s_cprestore, s_cpreturn, s_cpadd): Likewise.
885
79850f26
MR		 8862013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
887
cf29fc61 888 * config/tc-mips.c (append_insn): Correct indentation, remove
79850f26
MR		 889 extraneous braces.
890
4c261dff
NC		 8912013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
892
5c111e37 893 * config/tc-arm.c (do_neon_mov): Break on NS_NULL.
4c261dff 894
ea33f281
NC		 8952013-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
896
897 * configure.tgt: Add nios2-*-rtems*.
898
a1ccaec9
YZ		 8992013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
900
901 * config/tc-aarch64.c (md_begin): Change to check if 'name' is
902 NULL.
903
0aa27725
RS		 9042013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
905
906 * config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
907 (macro): Use it. Assert that trunc.w.s is not used for r5900.
908
da4339ed
NC		 9092013-02-08 Yi-Hsiu, Hsu <ahsu@marvell.com>
910
911 * gas/config/tc-arm.c (arm_cpus): Add support for mcpu=marvell-pj4
912 core.
913
36591ba1 9142013-02-06 Sandra Loosemore <sandra@codesourcery.com>
5c111e37 915 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 916
917 Based on patches from Altera Corporation.
918
919 * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c.
920 (TARGET_CPU_HFILES): Add config/tc-nios2.h.
921 * Makefile.in: Regenerated.
922 * configure.tgt: Add case for nios2*-linux*.
923 * config/obj-elf.c: Conditionally include elf/nios2.h.
924 * config/tc-nios2.c: New file.
925 * config/tc-nios2.h: New file.
926 * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi.
927 * doc/Makefile.in: Regenerated.
928 * doc/all.texi: Set NIOSII.
929 * doc/as.texinfo (Overview): Add Nios II options.
930 (Machine Dependencies): Include c-nios2.texi.
931 * doc/c-nios2.texi: New file.
932 * NEWS: Note Altera Nios II support.
933
94d4433a
AM		 9342013-02-06 Alan Modra <amodra@gmail.com>
935
936 PR gas/14255
937 * config/tc-avr.h (TC_VALIDATE_FIX): Mark symbol used by reloc.
938 Don't skip fixups with fx_subsy non-NULL.
939 * config/tc-avr.c (tc_gen_reloc): Don't specially handle fixups
940 with fx_subsy non-NULL.
941
ace9af6f
L		 9422013-02-04 H.J. Lu <hongjiu.lu@intel.com>
943
944 * doc/c-metag.texi: Add "@c man" markers.
945
89d67ed9
AM		 9462013-02-04 Alan Modra <amodra@gmail.com>
947
948 * write.c (fixup_segment): Return void. Delete seg_reloc_count
949 related code.
950 (TC_ADJUST_RELOC_COUNT): Delete.
951 * config/tc-i960.h (TC_ADJUST_RELOC_COUNT): Delete.
952
89072bd6
AM		 9532013-02-04 Alan Modra <amodra@gmail.com>
954
955 * po/POTFILES.in: Regenerate.
956
f9b2d544
NC		 9572013-01-30 Markos Chandras <markos.chandras@imgtec.com>
958
959 * config/tc-metag.c: Make SWAP instruction less permissive with
960 its operands.
961
392ca752
DD		 9622013-01-29 DJ Delorie <dj@redhat.com>
963
964 * config/tc-rl78.c (rl78_cons_fix_new): Handle user-specified
965 relocs in .word/.etc statements.
966
427d0db6
RM		 9672013-01-29 Roland McGrath <mcgrathr@google.com>
968
969 * config/tc-arm.c (md_apply_fix): Use as_bad_where for "bad
970 immediate value for 8-bit offset" error so it shows line info.
971
4faf939a
JM		 9722013-01-24 Joseph Myers <joseph@codesourcery.com>
973
974 * config/tc-ppc.c (md_assemble): Do not generate APUinfo sections
975 for 64-bit output.
976
78c8d46c
NC		 9772013-01-24 Nick Clifton <nickc@redhat.com>
978
979 * config/tc-v850.c: Add support for e3v5 architecture.
980 * doc/c-v850.texi: Mention new support.
981
fb5b7503
NC		 9822013-01-23 Nick Clifton <nickc@redhat.com>
983
984 PR gas/15039
985 * config/tc-avr.c: Include dwarf2dbg.h.
986
8ce3d284
L		 9872013-01-18 H.J. Lu <hongjiu.lu@intel.com>
988
989 * config/tc-i386.c (reloc): Support size relocation only for ELF.
990 (tc_i386_fix_adjustable): Likewise.
991 (lex_got): Likewise.
992 (tc_gen_reloc): Likewise.
993
f5555712
YZ		 9942013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
995
996 * config/tc-aarch64.c (output_operand_error_record): Change to output
997 the out-of-range error message as value-expected message if there is
998 only one single value in the expected range.
999 (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
1000 LSL #0 as a programmer-friendly feature.
1001
8fd4256d
L		 10022013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1003
1004 * config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32.
1005 (tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and
1006 BFD_RELOC_64_SIZE relocations.
1007 (lex_got): Support "symbol@SIZE" and don't create GOT symbol
1008 for it.
1009 (tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64
1010 relocations against local symbols.
1011
a5840dce
AM		 10122013-01-16 Alan Modra <amodra@gmail.com>
1013
1014 * config/tc-ppc.c (md_assemble <TE_PE>): Ignore line after
1015 finding some sort of toc syntax error, and break to avoid
1016 compiler uninit warning.
1017
af89796a
L		 10182013-01-15 H.J. Lu <hongjiu.lu@intel.com>
1019
1020 PR gas/15019
1021 * config/tc-i386.c (lex_got): Increment length by 1 if the
1022 relocation token is removed.
1023
dd42f060
NC		 10242013-01-15 Nick Clifton <nickc@redhat.com>
1025
1026 * config/tc-v850.c (md_assemble): Allow signed values for
1027 V850E_IMMEDIATE.
1028
464e3686
SK		 10292013-01-11 Sean Keys <skeys@ipdatasys.com>
1030
1031 * config/tc-xgate.c (md_begin): Fix mistake made when going from
af89796a 1032 git to cvs.
464e3686 1033
5817ffd1
PB		 10342013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1035
1036 * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
1037 * doc/c-ppc.texi (PowerPC-Opts): Likewise.
1038 * config/tc-ppc.c (md_show_usage): Likewise.
1039 (ppc_handle_align): Handle power8's group ending nop.
1040
f4b1f6a9
SK		 10412013-01-10 Sean Keys <skeys@ipdatasys.com>
1042
1043 * config/tc-xgate.c (md_begin): Fix the printing of opcodes so
af89796a 1044 that the assember exits after the opcodes have been printed.
f4b1f6a9 1045
34bca508
L		 10462013-01-10 H.J. Lu <hongjiu.lu@intel.com>
1047
1048 * app.c: Remove trailing white spaces.
1049 * as.c: Likewise.
1050 * as.h: Likewise.
1051 * cond.c: Likewise.
1052 * dw2gencfi.c: Likewise.
1053 * dwarf2dbg.h: Likewise.
1054 * ecoff.c: Likewise.
1055 * input-file.c: Likewise.
1056 * itbl-lex.h: Likewise.
1057 * output-file.c: Likewise.
1058 * read.c: Likewise.
1059 * sb.c: Likewise.
1060 * subsegs.c: Likewise.
1061 * symbols.c: Likewise.
1062 * write.c: Likewise.
1063 * config/tc-i386.c: Likewise.
1064 * doc/Makefile.am: Likewise.
1065 * doc/Makefile.in: Likewise.
1066 * doc/c-aarch64.texi: Likewise.
1067 * doc/c-alpha.texi: Likewise.
1068 * doc/c-arc.texi: Likewise.
1069 * doc/c-arm.texi: Likewise.
1070 * doc/c-avr.texi: Likewise.
1071 * doc/c-bfin.texi: Likewise.
1072 * doc/c-cr16.texi: Likewise.
1073 * doc/c-d10v.texi: Likewise.
1074 * doc/c-d30v.texi: Likewise.
1075 * doc/c-h8300.texi: Likewise.
1076 * doc/c-hppa.texi: Likewise.
1077 * doc/c-i370.texi: Likewise.
1078 * doc/c-i386.texi: Likewise.
1079 * doc/c-i860.texi: Likewise.
1080 * doc/c-m32c.texi: Likewise.
1081 * doc/c-m32r.texi: Likewise.
1082 * doc/c-m68hc11.texi: Likewise.
1083 * doc/c-m68k.texi: Likewise.
1084 * doc/c-microblaze.texi: Likewise.
1085 * doc/c-mips.texi: Likewise.
1086 * doc/c-msp430.texi: Likewise.
1087 * doc/c-mt.texi: Likewise.
1088 * doc/c-s390.texi: Likewise.
1089 * doc/c-score.texi: Likewise.
1090 * doc/c-sh.texi: Likewise.
1091 * doc/c-sh64.texi: Likewise.
1092 * doc/c-tic54x.texi: Likewise.
1093 * doc/c-tic6x.texi: Likewise.
1094 * doc/c-v850.texi: Likewise.
1095 * doc/c-xc16x.texi: Likewise.
1096 * doc/c-xgate.texi: Likewise.
1097 * doc/c-xtensa.texi: Likewise.
1098 * doc/c-z80.texi: Likewise.
1099 * doc/internals.texi: Likewise.
1100
4c665b71
RM		 11012013-01-10 Roland McGrath <mcgrathr@google.com>
1102
1103 * hash.c (hash_new_sized): Make it global.
1104 * hash.h: Declare it.
1105 * macro.c (define_macro): Use hash_new_sized instead of hash_new,
1106 pass a small size.
1107
a3c62988
NC		 11082013-01-10 Will Newton <will.newton@imgtec.com>
1109
1110 * Makefile.am: Add Meta.
1111 * Makefile.in: Regenerate.
1112 * config/tc-metag.c: New file.
1113 * config/tc-metag.h: New file.
1114 * configure.tgt: Add Meta.
1115 * doc/Makefile.am: Add Meta.
1116 * doc/Makefile.in: Regenerate.
1117 * doc/all.texi: Add Meta.
1118 * doc/as.texiinfo: Document Meta options.
1119 * doc/c-metag.texi: New file.
1120
b37df7c4
SE		 11212013-01-09 Steve Ellcey <sellcey@mips.com>
1122
1123 * config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal
1124 calls.
1125 * config/tc-mips.c (internalError): Remove, replace with abort.
1126
a3251895
YZ		 11272013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
1128
1129 * config/tc-aarch64.c (parse_operands): Change to compare the result
1130 of function call 'parse_sys_reg' with 'PARSE_FAIL' instead of 'FALSE'.
1131
8ab8155f
NC		 11322013-01-07 Nick Clifton <nickc@redhat.com>
1133
1134 PR gas/14887
1135 * config/tc-arm.c (skip_past_char): Skip whitespace before the
1136 anticipated character.
1137 * config/tc-arm.c (parse_address_main): Delete skip of whitespace
1138 here as it is no longer needed.
1139
a4ac1c42
AS		 11402013-01-06 Andreas Schwab <schwab@linux-m68k.org>
1141
1142 * doc/c-mips.texi (MIPS Opts): Fix use of @itemx.
1143 * doc/c-score.texi (SCORE-Opts): Likewise.
1144 * doc/c-tic54x.texi (TIC54X-Directives): Likewise.
1145
e407c74b
NC		 11462013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1147
1148 * config/tc-mips.c: Add support for MIPS r5900.
1149 Add M_LQ_AB and M_SQ_AB to support large values for instructions
1150 lq and sq.
1151 (can_swap_branch_p, get_append_method): Detect some conditional
1152 short loops to fix a bug on the r5900 by NOP in the branch delay
1153 slot.
1154 (M_MUL): Support 3 operands in multu on r5900.
1155 (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
1156 (s_mipsset): Force 32 bit floating point on r5900.
1157 (mips_ip): Check parameter range of instructions mfps and mtps on
1158 r5900.
1159 * configure.in: Detect CPU type when target string contains r5900
1160 (e.g. mips64r5900el-linux-gnu).
1161
62658407
L		 11622013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1163
1164 * as.c (parse_args): Update copyright year to 2013.
1165
95830fd1
YZ		 11662013-01-02 Yufeng Zhang <yufeng.zhang@arm.com>
1167
1168 * config/tc-aarch64.c (aarch64_cpus): Add entries for "cortex-a53"
1169 and "cortex57".
1170
517bb291 11712013-01-02 Nick Clifton <nickc@redhat.com>
d709e4e6 1172
517bb291
NC		 1173 PR gas/14987
1174 * config/tc-arm.c (parse_address_main): Skip whitespace before a
1175 closing bracket.
d709e4e6 1176
517bb291 1177For older changes see ChangeLog-2012
08d56133 1178\f
517bb291 1179Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1180
1181Copying and distribution of this file, with or without modification,
1182are permitted in any medium without royalty provided the copyright
1183notice and this notice are preserved.
1184
08d56133
NC		 1185Local Variables:
1186mode: change-log
1187left-margin: 8
1188fill-column: 74
1189version-control: never
1190End:
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