[thirdparty/binutils-gdb.git] / gas / config / m68k-parse.h

/* m68k-parse.h -- header file for m68k assembler
   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
   2003, 2004, 2005 Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

#ifndef M68K_PARSE_H
#define M68K_PARSE_H

/* This header file defines things which are shared between the
   operand parser in m68k.y and the m68k assembler proper in
   tc-m68k.c.  */

/* The various m68k registers.  */

/* DATA and ADDR have to be contiguous, so that reg-DATA gives
   0-7==data reg, 8-15==addr reg for operands that take both types.

   We don't use forms like "ADDR0 = ADDR" here because this file is
   likely to be used on an Apollo, and the broken Apollo compiler
   gives an `undefined variable' error if we do that, according to
   troy@cbme.unsw.edu.au.  */

#define DATA DATA0
#define ADDR ADDR0
#define SP ADDR7
#define BAD BAD0
#define BAC BAC0

enum m68k_register
{
  DATA0 = 1,			/*   1- 8 == data registers 0-7 */
  DATA1,
  DATA2,
  DATA3,
  DATA4,
  DATA5,
  DATA6,
  DATA7,

  ADDR0,
  ADDR1,
  ADDR2,
  ADDR3,
  ADDR4,
  ADDR5,
  ADDR6,
  ADDR7,

  FP0,				/* Eight FP registers */
  FP1,
  FP2,
  FP3,
  FP4,
  FP5,
  FP6,
  FP7,

  COP0,				/* Co-processor #0-#7 */
  COP1,
  COP2,
  COP3,
  COP4,
  COP5,
  COP6,
  COP7,

  PC,				/* Program counter */
  ZPC,				/* Hack for Program space, but 0 addressing */
  SR,				/* Status Reg */
  CCR,				/* Condition code Reg */
  ACC,				/* Accumulator Reg0 (EMAC or ACC on MAC).  */
  ACC1,				/* Accumulator Reg 1 (EMAC).  */
  ACC2,				/* Accumulator Reg 2 (EMAC).  */
  ACC3,				/* Accumulator Reg 3 (EMAC).  */
  ACCEXT01,			/* Accumulator extension 0&1 (EMAC).  */
  ACCEXT23,			/* Accumulator extension 2&3 (EMAC).  */
  MACSR,			/* MAC Status Reg */
  MASK,				/* Modulus Reg */

  /* These have to be grouped together for the movec instruction to work.  */
  USP,				/*  User Stack Pointer */
  ISP,				/*  Interrupt stack pointer */
  SFC,
  DFC,
  CACR,
  VBR,
  CAAR,
  MSP,
  ITT0,
  ITT1,
  DTT0,
  DTT1,
  MMUSR,
  TC,
  SRP,
  URP,
  BUSCR,			/* 68060 added these.  */
  PCR,
  ROMBAR,			/* mcf5200 added these.  */
  RAMBAR0,
  RAMBAR1,
  MMUBAR,			/* mcfv4e added these.  */
  ROMBAR0,			/* mcfv4e added these.  */
  ROMBAR1,			/* mcfv4e added these.  */
  MPCR, EDRAMBAR, SECMBAR,	/* mcfv4e added these.  */
  PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
  PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
  PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
  MBAR0, MBAR1,			/* mcfv4e added these.  */
  ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
  FLASHBAR, RAMBAR,  		/* mcf528x added these.  */
  MBAR2,  		        /* mcf5249 added this.  */
  MBAR,
  ASID,				/* m5475.  */
  CAC,  		        /* fido added this.  */
  MBB,
#define last_movec_reg MBB
  /* End of movec ordering constraints.  */

  FPI,
  FPS,
  FPC,

  DRP,				/* 68851 or 68030 MMU regs */
  CRP,
  CAL,
  VAL,
  SCC,
  AC,
  BAD0,
  BAD1,
  BAD2,
  BAD3,
  BAD4,
  BAD5,
  BAD6,
  BAD7,
  BAC0,
  BAC1,
  BAC2,
  BAC3,
  BAC4,
  BAC5,
  BAC6,
  BAC7,
  PSR,				/* aka MMUSR on 68030 (but not MMUSR on 68040)
				   and ACUSR on 68ec030 */
  PCSR,

  IC,				/* instruction cache token */
  DC,				/* data cache token */
  NC,				/* no cache token */
  BC,				/* both caches token */

  TT0,				/* 68030 access control unit regs */
  TT1,

  ZDATA0,			/* suppressed data registers.  */
  ZDATA1,
  ZDATA2,
  ZDATA3,
  ZDATA4,
  ZDATA5,
  ZDATA6,
  ZDATA7,

  ZADDR0,			/* suppressed address registers.  */
  ZADDR1,
  ZADDR2,
  ZADDR3,
  ZADDR4,
  ZADDR5,
  ZADDR6,
  ZADDR7,

  /* Upper and lower half of data and address registers.  Order *must*
     be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
  DATA0L,			/* lower half of data registers */
  DATA1L,
  DATA2L,
  DATA3L,
  DATA4L,
  DATA5L,
  DATA6L,
  DATA7L,

  ADDR0L,			/* lower half of address registers */
  ADDR1L,
  ADDR2L,
  ADDR3L,
  ADDR4L,
  ADDR5L,
  ADDR6L,
  ADDR7L,

  DATA0U,			/* upper half of data registers */
  DATA1U,
  DATA2U,
  DATA3U,
  DATA4U,
  DATA5U,
  DATA6U,
  DATA7U,

  ADDR0U,			/* upper half of address registers */
  ADDR1U,
  ADDR2U,
  ADDR3U,
  ADDR4U,
  ADDR5U,
  ADDR6U,
  ADDR7U,
};

/* Size information.  */

enum m68k_size
{
  /* Unspecified.  */
  SIZE_UNSPEC,

  /* Byte.  */
  SIZE_BYTE,

  /* Word (2 bytes).  */
  SIZE_WORD,

  /* Longword (4 bytes).  */
  SIZE_LONG
};

/* The structure used to hold information about an index register.  */

struct m68k_indexreg
{
  /* The index register itself.  */
  enum m68k_register reg;

  /* The size to use.  */
  enum m68k_size size;

  /* The value to scale by.  */
  int scale;
};

#ifdef OBJ_ELF
/* The type of a PIC expression.  */

enum pic_relocation
{
  pic_none,			/* not pic */
  pic_plt_pcrel,		/* @PLTPC */
  pic_got_pcrel,		/* @GOTPC */
  pic_plt_off,			/* @PLT */
  pic_got_off			/* @GOT */
};
#endif

/* The structure used to hold information about an expression.  */

struct m68k_exp
{
  /* The size to use.  */
  enum m68k_size size;

#ifdef OBJ_ELF
  /* The type of pic relocation if any.  */
  enum pic_relocation pic_reloc;
#endif

  /* The expression itself.  */
  expressionS exp;
};

/* The operand modes.  */

enum m68k_operand_type
{
  IMMED = 1,
  ABSL,
  DREG,
  AREG,
  FPREG,
  CONTROL,
  AINDR,
  AINC,
  ADEC,
  DISP,
  BASE,
  POST,
  PRE,
  LSH,  /* MAC/EMAC scalefactor '<<'.  */
  RSH,  /* MAC/EMAC scalefactor '>>'.  */
  REGLST
};

/* The structure used to hold a parsed operand.  */

struct m68k_op
{
  /* The type of operand.  */
  enum m68k_operand_type mode;

  /* The main register.  */
  enum m68k_register reg;

  /* The register mask for mode REGLST.  */
  unsigned long mask;

  /* An error message.  */
  const char *error;

  /* The index register.  */
  struct m68k_indexreg index;

  /* The displacement.  */
  struct m68k_exp disp;

  /* The outer displacement.  */
  struct m68k_exp odisp;

  /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
  int trailing_ampersand;
};

#endif /* ! defined (M68K_PARSE_H) */

/* The parsing function.  */

extern int m68k_ip_op (char *, struct m68k_op *);

/* Whether register prefixes are optional.  */
extern int flag_reg_prefix_optional;
Commit	Line	Data
252b5132	1	/* m68k-parse.h -- header file for m68k assembler
3e602632	2	Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
8f738565	3	2003, 2004, 2005 Free Software Foundation, Inc.
252b5132 RH	4
	5	This file is part of GAS, the GNU Assembler.
	6
	7	GAS is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	GAS is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GAS; see the file COPYING. If not, write to the Free
4b4da160 NC	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
4b4da160 NC	20	02110-1301, USA. */
252b5132 RH	21
	22	#ifndef M68K_PARSE_H
	23	#define M68K_PARSE_H
	24
	25	/* This header file defines things which are shared between the
	26	operand parser in m68k.y and the m68k assembler proper in
	27	tc-m68k.c. */
	28
	29	/* The various m68k registers. */
	30
	31	/* DATA and ADDR have to be contiguous, so that reg-DATA gives
	32	0-7==data reg, 8-15==addr reg for operands that take both types.
	33
	34	We don't use forms like "ADDR0 = ADDR" here because this file is
	35	likely to be used on an Apollo, and the broken Apollo compiler
	36	gives an `undefined variable' error if we do that, according to
	37	troy@cbme.unsw.edu.au. */
	38
	39	#define DATA DATA0
	40	#define ADDR ADDR0
	41	#define SP ADDR7
	42	#define BAD BAD0
	43	#define BAC BAC0
	44
	45	enum m68k_register
	46	{
	47	DATA0 = 1, /* 1- 8 == data registers 0-7 */
	48	DATA1,
	49	DATA2,
	50	DATA3,
	51	DATA4,
	52	DATA5,
	53	DATA6,
	54	DATA7,
	55
	56	ADDR0,
	57	ADDR1,
	58	ADDR2,
	59	ADDR3,
	60	ADDR4,
	61	ADDR5,
	62	ADDR6,
	63	ADDR7,
	64
	65	FP0, /* Eight FP registers */
	66	FP1,
	67	FP2,
	68	FP3,
	69	FP4,
	70	FP5,
	71	FP6,
	72	FP7,
	73
	74	COP0, /* Co-processor #0-#7 */
	75	COP1,
	76	COP2,
	77	COP3,
	78	COP4,
	79	COP5,
	80	COP6,
	81	COP7,
	82
	83	PC, /* Program counter */
	84	ZPC, /* Hack for Program space, but 0 addressing */
85	SR, /* Status Reg */
86	CCR, /* Condition code Reg */
fd99574b NC	87	ACC, /* Accumulator Reg0 (EMAC or ACC on MAC). */
	88	ACC1, /* Accumulator Reg 1 (EMAC). */
	89	ACC2, /* Accumulator Reg 2 (EMAC). */
	90	ACC3, /* Accumulator Reg 3 (EMAC). */
	91	ACCEXT01, /* Accumulator extension 0&1 (EMAC). */
	92	ACCEXT23, /* Accumulator extension 2&3 (EMAC). */
6da466c7 ILT	93	MACSR, /* MAC Status Reg */
6da466c7 ILT	94	MASK, /* Modulus Reg */
252b5132	95
4a1805b1	96	/* These have to be grouped together for the movec instruction to work. */
252b5132 RH	97	USP, /* User Stack Pointer */
	98	ISP, /* Interrupt stack pointer */
	99	SFC,
	100	DFC,
	101	CACR,
	102	VBR,
	103	CAAR,
	104	MSP,
	105	ITT0,
	106	ITT1,
	107	DTT0,
	108	DTT1,
	109	MMUSR,
	110	TC,
	111	SRP,
	112	URP,
3e602632	113	BUSCR, /* 68060 added these. */
252b5132	114	PCR,
3e602632	115	ROMBAR, /* mcf5200 added these. */
252b5132 RH	116	RAMBAR0,
252b5132 RH	117	RAMBAR1,
3e602632	118	MMUBAR, /* mcfv4e added these. */
a8e24a56	119	ROMBAR0, /* mcfv4e added these. */
3e602632 NC	120	ROMBAR1, /* mcfv4e added these. */
	121	MPCR, EDRAMBAR, SECMBAR, /* mcfv4e added these. */
	122	PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these. */
	123	PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these. */
	124	PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these. */
	125	MBAR0, MBAR1, /* mcfv4e added these. */
	126	ACR0, ACR1, ACR2, ACR3, /* mcf5200 added these. */
	127	FLASHBAR, RAMBAR, /* mcf528x added these. */
e80e0390	128	MBAR2, /* mcf5249 added this. */
252b5132	129	MBAR,
a8e24a56	130	ASID, /* m5475. */
f7ec513b KH	131	CAC, /* fido added this. */
	132	MBB,
	133	#define last_movec_reg MBB
3e602632	134	/* End of movec ordering constraints. */
252b5132 RH	135
	136	FPI,
	137	FPS,
	138	FPC,
	139
	140	DRP, /* 68851 or 68030 MMU regs */
	141	CRP,
	142	CAL,
	143	VAL,
	144	SCC,
	145	AC,
	146	BAD0,
	147	BAD1,
	148	BAD2,
	149	BAD3,
	150	BAD4,
	151	BAD5,
	152	BAD6,
	153	BAD7,
	154	BAC0,
	155	BAC1,
	156	BAC2,
	157	BAC3,
	158	BAC4,
	159	BAC5,
	160	BAC6,
	161	BAC7,
	162	PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
	163	and ACUSR on 68ec030 */
	164	PCSR,
	165
	166	IC, /* instruction cache token */
	167	DC, /* data cache token */
	168	NC, /* no cache token */
	169	BC, /* both caches token */
	170
	171	TT0, /* 68030 access control unit regs */
	172	TT1,
	173
	174	ZDATA0, /* suppressed data registers. */
	175	ZDATA1,
	176	ZDATA2,
	177	ZDATA3,
	178	ZDATA4,
	179	ZDATA5,
	180	ZDATA6,
	181	ZDATA7,
	182
	183	ZADDR0, /* suppressed address registers. */
	184	ZADDR1,
	185	ZADDR2,
	186	ZADDR3,
	187	ZADDR4,
	188	ZADDR5,
	189	ZADDR6,
	190	ZADDR7,
6da466c7 ILT	191
6da466c7 ILT	192	/* Upper and lower half of data and address registers. Order must
4a1805b1	193	be DATAxL, ADDRxL, DATAxU, ADDRxU. */
6da466c7 ILT	194	DATA0L, /* lower half of data registers */
	195	DATA1L,
	196	DATA2L,
	197	DATA3L,
	198	DATA4L,
	199	DATA5L,
	200	DATA6L,
	201	DATA7L,
	202
	203	ADDR0L, /* lower half of address registers */
	204	ADDR1L,
	205	ADDR2L,
	206	ADDR3L,
	207	ADDR4L,
	208	ADDR5L,
	209	ADDR6L,
	210	ADDR7L,
	211
	212	DATA0U, /* upper half of data registers */
	213	DATA1U,
	214	DATA2U,
	215	DATA3U,
	216	DATA4U,
	217	DATA5U,
	218	DATA6U,
	219	DATA7U,
	220
	221	ADDR0U, /* upper half of address registers */
	222	ADDR1U,
	223	ADDR2U,
	224	ADDR3U,
	225	ADDR4U,
	226	ADDR5U,
	227	ADDR6U,
	228	ADDR7U,
252b5132 RH	229	};
	230
	231	/* Size information. */
	232
	233	enum m68k_size
	234	{
	235	/* Unspecified. */
	236	SIZE_UNSPEC,
	237
	238	/* Byte. */
	239	SIZE_BYTE,
	240
	241	/* Word (2 bytes). */
	242	SIZE_WORD,
	243
	244	/* Longword (4 bytes). */
	245	SIZE_LONG
	246	};
	247
	248	/* The structure used to hold information about an index register. */
	249
	250	struct m68k_indexreg
	251	{
	252	/* The index register itself. */
	253	enum m68k_register reg;
	254
	255	/* The size to use. */
	256	enum m68k_size size;
	257
	258	/* The value to scale by. */
	259	int scale;
	260	};
	261
	262	#ifdef OBJ_ELF
	263	/* The type of a PIC expression. */
	264
	265	enum pic_relocation
	266	{
	267	pic_none, /* not pic */
	268	pic_plt_pcrel, /* @PLTPC */
	269	pic_got_pcrel, /* @GOTPC */
	270	pic_plt_off, /* @PLT */
	271	pic_got_off /* @GOT */
	272	};
	273	#endif
	274
	275	/* The structure used to hold information about an expression. */
	276
	277	struct m68k_exp
	278	{
	279	/* The size to use. */
	280	enum m68k_size size;
	281
	282	#ifdef OBJ_ELF
	283	/* The type of pic relocation if any. */
	284	enum pic_relocation pic_reloc;
	285	#endif
	286
	287	/* The expression itself. */
	288	expressionS exp;
	289	};
	290
	291	/* The operand modes. */
	292
293	enum m68k_operand_type
294	{
295	IMMED = 1,
296	ABSL,
297	DREG,
298	AREG,
299	FPREG,
300	CONTROL,
301	AINDR,
302	AINC,
303	ADEC,
304	DISP,
305	BASE,
306	POST,
307	PRE,
fd99574b NC	308	LSH, /* MAC/EMAC scalefactor '<<'. */
fd99574b NC	309	RSH, /* MAC/EMAC scalefactor '>>'. */
252b5132 RH	310	REGLST
	311	};
	312
	313	/* The structure used to hold a parsed operand. */
	314
	315	struct m68k_op
	316	{
	317	/* The type of operand. */
	318	enum m68k_operand_type mode;
	319
	320	/* The main register. */
	321	enum m68k_register reg;
	322
	323	/* The register mask for mode REGLST. */
	324	unsigned long mask;
	325
	326	/* An error message. */
	327	const char *error;
	328
	329	/* The index register. */
	330	struct m68k_indexreg index;
	331
	332	/* The displacement. */
	333	struct m68k_exp disp;
	334
	335	/* The outer displacement. */
	336	struct m68k_exp odisp;
fd99574b NC	337
	338	/* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing). */
	339	int trailing_ampersand;
252b5132 RH	340	};
	341
	342	#endif /* ! defined (M68K_PARSE_H) */
	343
	344	/* The parsing function. */
	345
8f738565	346	extern int m68k_ip_op (char , struct m68k_op );
252b5132 RH	347
	348	/* Whether register prefixes are optional. */
	349	extern int flag_reg_prefix_optional;