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Re: Get rid of fprintf_vma and sprintf_vma
[thirdparty/binutils-gdb.git] / gas / config / tc-arc.c
CommitLineData
252b5132 1/* tc-arc.c -- Assembler for the ARC
a2c58332 2 Copyright (C) 1994-2022 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
886a2506 25#include "dwarf2dbg.h"
726c18e1 26#include "dw2gencfi.h"
3882b010 27#include "safe-ctype.h"
886a2506 28
252b5132 29#include "opcode/arc.h"
53a346d8 30#include "opcode/arc-attrs.h"
252b5132 31#include "elf/arc.h"
b99747ae 32#include "../opcodes/arc-ext.h"
252b5132 33
886a2506 34/* Defines section. */
0d2bcfaf 35
886a2506
NC		 36#define MAX_INSN_FIXUPS 2
37#define MAX_CONSTR_STR 20
4670103e 38#define FRAG_MAX_GROWTH 8
0d2bcfaf 39
886a2506
NC		 40#ifdef DEBUG
41# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42#else
43# define pr_debug(fmt, args...)
44#endif
45
46#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 48#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
886a2506 50
9004b6bd
AB		 51#ifndef TARGET_WITH_CPU
52#define TARGET_WITH_CPU "arc700"
53#endif /* TARGET_WITH_CPU */
54
53a346d8
CZ		 55#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57#define streq(a, b) (strcmp (a, b) == 0)
58
4670103e
CZ		 59/* Enum used to enumerate the relaxable ins operands. */
60enum rlx_operand_type
61{
62 EMPTY = 0,
63 REGISTER,
64 REGISTER_S, /* Register for short instruction(s). */
65 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
66 REGISTER_DUP, /* Duplication of previous operand of type register. */
67 IMMEDIATE,
68 BRACKET
69};
70
71enum arc_rlx_types
72{
73 ARC_RLX_NONE = 0,
74 ARC_RLX_BL_S,
75 ARC_RLX_BL,
76 ARC_RLX_B_S,
77 ARC_RLX_B,
78 ARC_RLX_ADD_U3,
79 ARC_RLX_ADD_U6,
80 ARC_RLX_ADD_LIMM,
81 ARC_RLX_LD_U7,
82 ARC_RLX_LD_S9,
83 ARC_RLX_LD_LIMM,
84 ARC_RLX_MOV_U8,
85 ARC_RLX_MOV_S12,
86 ARC_RLX_MOV_LIMM,
87 ARC_RLX_SUB_U3,
88 ARC_RLX_SUB_U6,
89 ARC_RLX_SUB_LIMM,
90 ARC_RLX_MPY_U6,
91 ARC_RLX_MPY_LIMM,
92 ARC_RLX_MOV_RU6,
93 ARC_RLX_MOV_RLIMM,
94 ARC_RLX_ADD_RRU6,
95 ARC_RLX_ADD_RRLIMM,
96};
97
886a2506
NC		 98/* Macros section. */
99
100#define regno(x) ((x) & 0x3F)
101#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 102#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103#define is_spfp_p(op) (((sc) == SPX))
104#define is_dpfp_p(op) (((sc) == DPX))
105#define is_fpuda_p(op) (((sc) == DPA))
cf9bdae9 106#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
117 ))
c810e0b8 118#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 119#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 120
886a2506
NC		 121/* Generic assembler global variables which must be defined by all
122 targets. */
0d2bcfaf 123
886a2506 124/* Characters which always start a comment. */
252b5132
RH		 125const char comment_chars[] = "#;";
126
886a2506 127/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 128const char line_comment_chars[] = "#";
129
886a2506
NC		 130/* Characters which may be used to separate multiple commands on a
131 single line. */
132const char line_separator_chars[] = "`";
252b5132 133
886a2506
NC		 134/* Characters which are used to indicate an exponent in a floating
135 point number. */
252b5132
RH		 136const char EXP_CHARS[] = "eE";
137
bcee8eb8
AM		 138/* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 140const char FLT_CHARS[] = "rRsSfFdD";
141
142/* Byte order. */
143extern int target_big_endian;
144const char *arc_target_format = DEFAULT_TARGET_FORMAT;
145static int byte_order = DEFAULT_BYTE_ORDER;
146
b99747ae
CZ		 147/* Arc extension section. */
148static segT arcext_section;
149
4670103e
CZ		 150/* By default relaxation is disabled. */
151static int relaxation_state = 0;
152
886a2506 153extern int arc_get_mach (char *);
0d2bcfaf 154
4670103e 155/* Forward declarations. */
886a2506
NC		 156static void arc_lcomm (int);
157static void arc_option (int);
158static void arc_extra_reloc (int);
b99747ae 159static void arc_extinsn (int);
f36e33da 160static void arc_extcorereg (int);
53a346d8 161static void arc_attribute (int);
4670103e 162
886a2506 163const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 164{
165 /* Make sure that .word is 32 bits. */
166 { "word", cons, 4 },
886a2506 167
6f4b1afc
CM		 168 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm, 0 },
170 { "lcommon", arc_lcomm, 0 },
171 { "cpu", arc_option, 0 },
252b5132 172
53a346d8 173 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 174 { "extinstruction", arc_extinsn, 0 },
175 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
176 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
177 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 178
6f4b1afc
CM		 179 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
180 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 181
6f4b1afc
CM		 182 { NULL, NULL, 0 }
183};
252b5132 184
252b5132 185const char *md_shortopts = "";
ea1562b3
NC		 186
187enum options
6f4b1afc
CM		 188{
189 OPTION_EB = OPTION_MD_BASE,
190 OPTION_EL,
191
192 OPTION_ARC600,
193 OPTION_ARC601,
194 OPTION_ARC700,
195 OPTION_ARCEM,
196 OPTION_ARCHS,
197
198 OPTION_MCPU,
199 OPTION_CD,
4670103e 200 OPTION_RELAX,
bdd582db 201 OPTION_NPS400,
6f4b1afc 202
ce440d63
GM		 203 OPTION_SPFP,
204 OPTION_DPFP,
205 OPTION_FPUDA,
206
6f4b1afc
CM		 207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
209 OPTION_USER_MODE,
210 OPTION_LD_EXT_MASK,
211 OPTION_SWAP,
212 OPTION_NORM,
213 OPTION_BARREL_SHIFT,
214 OPTION_MIN_MAX,
215 OPTION_NO_MPY,
216 OPTION_EA,
217 OPTION_MUL64,
218 OPTION_SIMD,
6f4b1afc
CM		 219 OPTION_XMAC_D16,
220 OPTION_XMAC_24,
221 OPTION_DSP_PACKA,
222 OPTION_CRC,
223 OPTION_DVBF,
224 OPTION_TELEPHONY,
225 OPTION_XYMEMORY,
226 OPTION_LOCK,
227 OPTION_SWAPE,
ce440d63 228 OPTION_RTSC
6f4b1afc 229};
ea1562b3
NC		 230
231struct option md_longopts[] =
6f4b1afc
CM		 232{
233 { "EB", no_argument, NULL, OPTION_EB },
234 { "EL", no_argument, NULL, OPTION_EL },
235 { "mcpu", required_argument, NULL, OPTION_MCPU },
236 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 237 { "mARC600", no_argument, NULL, OPTION_ARC600 },
238 { "mARC601", no_argument, NULL, OPTION_ARC601 },
239 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 240 { "mA7", no_argument, NULL, OPTION_ARC700 },
241 { "mEM", no_argument, NULL, OPTION_ARCEM },
242 { "mHS", no_argument, NULL, OPTION_ARCHS },
243 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 244 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 245 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 246
ce440d63
GM		 247 /* Floating point options */
248 { "mspfp", no_argument, NULL, OPTION_SPFP},
249 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
250 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
251 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
252 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
253 { "mdpfp", no_argument, NULL, OPTION_DPFP},
254 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
255 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
256 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
257 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
258 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
259
6f4b1afc
CM		 260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument, NULL, OPTION_ARCEM },
263 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
264 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
265 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
266 { "mswap", no_argument, NULL, OPTION_SWAP },
267 { "mnorm", no_argument, NULL, OPTION_NORM },
268 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
269 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
270 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
271 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
272 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
273 { "mea", no_argument, NULL, OPTION_EA },
274 { "mEA", no_argument, NULL, OPTION_EA },
275 { "mmul64", no_argument, NULL, OPTION_MUL64 },
276 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 277 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
278 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
279 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
280 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
281 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
282 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
283 { "mcrc", no_argument, NULL, OPTION_CRC},
284 { "mdvbf", no_argument, NULL, OPTION_DVBF},
285 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
286 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
287 { "mlock", no_argument, NULL, OPTION_LOCK},
288 { "mswape", no_argument, NULL, OPTION_SWAPE},
289 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 290
291 { NULL, no_argument, NULL, 0 }
292};
252b5132 293
886a2506 294size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 295
886a2506 296/* Local data and data types. */
252b5132 297
886a2506
NC		 298/* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300typedef int extended_bfd_reloc_code_real_type;
252b5132 301
886a2506 302struct arc_fixup
252b5132 303{
886a2506 304 expressionS exp;
252b5132 305
886a2506 306 extended_bfd_reloc_code_real_type reloc;
252b5132 307
886a2506
NC		 308 /* index into arc_operands. */
309 unsigned int opindex;
252b5132 310
886a2506
NC		 311 /* PC-relative, used by internals fixups. */
312 unsigned char pcrel;
252b5132 313
886a2506 314 /* TRUE if this fixup is for LIMM operand. */
5b7c81bd 315 bool islong;
886a2506 316};
252b5132 317
886a2506
NC		 318struct arc_insn
319{
bdfe53e3 320 unsigned long long int insn;
886a2506
NC		 321 int nfixups;
322 struct arc_fixup fixups[MAX_INSN_FIXUPS];
323 long limm;
5b7c81bd
AM		 324 unsigned int len; /* Length of instruction in bytes. */
325 bool has_limm; /* Boolean value: TRUE if limm field is valid. */
326 bool relax; /* Boolean value: TRUE if needs relaxation. */
886a2506 327};
ea1562b3 328
886a2506
NC		 329/* Structure to hold any last two instructions. */
330static struct arc_last_insn
252b5132 331{
886a2506
NC		 332 /* Saved instruction opcode. */
333 const struct arc_opcode *opcode;
252b5132 334
886a2506 335 /* Boolean value: TRUE if current insn is short. */
5b7c81bd 336 bool has_limm;
252b5132 337
886a2506 338 /* Boolean value: TRUE if current insn has delay slot. */
5b7c81bd 339 bool has_delay_slot;
886a2506 340} arc_last_insns[2];
252b5132 341
b99747ae
CZ		 342/* Extension instruction suffix classes. */
343typedef struct
344{
345 const char *name;
346 int len;
c810e0b8 347 int attr_class;
b99747ae
CZ		 348} attributes_t;
349
350static const attributes_t suffixclass[] =
351{
352 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
353 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
354 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
355};
356
357/* Extension instruction syntax classes. */
358static const attributes_t syntaxclass[] =
359{
360 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 361 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
362 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
363 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 364};
365
366/* Extension instruction syntax classes modifiers. */
367static const attributes_t syntaxclassmod[] =
368{
369 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
370 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
371};
372
f36e33da
CZ		 373/* Extension register type. */
374typedef struct
375{
376 char *name;
377 int number;
378 int imode;
379} extRegister_t;
380
381/* A structure to hold the additional conditional codes. */
382static struct
383{
384 struct arc_flag_operand *arc_ext_condcode;
385 int size;
386} ext_condcode = { NULL, 0 };
387
da5be039
AB		 388/* Structure to hold an entry in ARC_OPCODE_HASH. */
389struct arc_opcode_hash_entry
390{
391 /* The number of pointers in the OPCODE list. */
392 size_t count;
393
394 /* Points to a list of opcode pointers. */
395 const struct arc_opcode **opcode;
396};
397
1328504b
AB		 398/* Structure used for iterating through an arc_opcode_hash_entry. */
399struct arc_opcode_hash_entry_iterator
400{
401 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
402 size_t index;
403
404 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
405 returned by this iterator. */
406 const struct arc_opcode *opcode;
407};
408
4670103e
CZ		 409/* Forward declaration. */
410static void assemble_insn
411 (const struct arc_opcode *, const expressionS *, int,
412 const struct arc_flags *, int, struct arc_insn *);
413
bb65a718
AB		 414/* The selection of the machine type can come from different sources. This
415 enum is used to track how the selection was made in order to perform
416 error checks. */
417enum mach_selection_type
418 {
419 MACH_SELECTION_NONE,
420 MACH_SELECTION_FROM_DEFAULT,
421 MACH_SELECTION_FROM_CPU_DIRECTIVE,
422 MACH_SELECTION_FROM_COMMAND_LINE
423 };
424
425/* How the current machine type was selected. */
426static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 427
886a2506 428/* The hash table of instruction opcodes. */
629310ab 429static htab_t arc_opcode_hash;
0d2bcfaf 430
886a2506 431/* The hash table of register symbols. */
629310ab 432static htab_t arc_reg_hash;
252b5132 433
f36e33da 434/* The hash table of aux register symbols. */
629310ab 435static htab_t arc_aux_hash;
f36e33da 436
db18dbab 437/* The hash table of address types. */
629310ab 438static htab_t arc_addrtype_hash;
db18dbab 439
a9752fdf
CZ		 440#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
441 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
442 E_ARC_MACH_ARC600, EXTRA}
443#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
444 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
445 E_ARC_MACH_ARC700, EXTRA}
446#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
448 EF_ARC_CPU_ARCV2EM, EXTRA}
449#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
451 EF_ARC_CPU_ARCV2HS, EXTRA}
940171d0
AK		 452#define ARC_CPU_TYPE_NONE \
453 { 0, 0, 0, 0, 0 }
a9752fdf 454
886a2506
NC		 455/* A table of CPU names and opcode sets. */
456static const struct cpu_type
457{
458 const char *name;
459 unsigned flags;
460 int mach;
461 unsigned eflags;
462 unsigned features;
252b5132 463}
886a2506 464 cpu_types[] =
252b5132 465{
940171d0 466 #include "elf/arc-cpu.def"
886a2506 467};
252b5132 468
bb65a718 469/* Information about the cpu/variant we're assembling for. */
53a346d8 470static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 471
63741043 472/* TRUE if current assembly code uses RF16 only registers. */
5b7c81bd 473static bool rf16_only = true;
63741043 474
53a346d8
CZ		 475/* MPY option. */
476static unsigned mpy_option = 0;
477
478/* Use PIC. */
479static unsigned pic_option = 0;
480
481/* Use small data. */
482static unsigned sda_option = 0;
483
484/* Use TLS. */
485static unsigned tls_option = 0;
bb65a718 486
a9752fdf
CZ		 487/* Command line given features. */
488static unsigned cl_features = 0;
489
886a2506
NC		 490/* Used by the arc_reloc_op table. Order is important. */
491#define O_gotoff O_md1 /* @gotoff relocation. */
492#define O_gotpc O_md2 /* @gotpc relocation. */
493#define O_plt O_md3 /* @plt relocation. */
494#define O_sda O_md4 /* @sda relocation. */
495#define O_pcl O_md5 /* @pcl relocation. */
496#define O_tlsgd O_md6 /* @tlsgd relocation. */
497#define O_tlsie O_md7 /* @tlsie relocation. */
498#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
499#define O_tpoff O_md9 /* @tpoff relocation. */
500#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
501#define O_dtpoff O_md11 /* @dtpoff relocation. */
502#define O_last O_dtpoff
503
504/* Used to define a bracket as operand in tokens. */
505#define O_bracket O_md32
506
db18dbab
GM		 507/* Used to define a colon as an operand in tokens. */
508#define O_colon O_md31
509
510/* Used to define address types in nps400. */
511#define O_addrtype O_md30
512
886a2506
NC		 513/* Dummy relocation, to be sorted out. */
514#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
515
516#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
517
518/* A table to map the spelling of a relocation operand into an appropriate
519 bfd_reloc_code_real_type type. The table is assumed to be ordered such
520 that op-O_literal indexes into it. */
521#define ARC_RELOC_TABLE(op) \
522 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
523 ? (abort (), 0) \
524 : (int) (op) - (int) O_gotoff) ])
525
526#define DEF(NAME, RELOC, REQ) \
527 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
528
529static const struct arc_reloc_op_tag
530{
531 /* String to lookup. */
532 const char *name;
533 /* Size of the string. */
534 size_t length;
535 /* Which operator to use. */
536 operatorT op;
537 extended_bfd_reloc_code_real_type reloc;
538 /* Allows complex relocation expression like identifier@reloc +
539 const. */
540 unsigned int complex_expr : 1;
541}
542 arc_reloc_op[] =
6f4b1afc
CM		 543{
544 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
545 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
546 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
547 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
548 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
549 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
550 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
551 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 552 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 553 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 554 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 555};
252b5132 556
886a2506
NC		 557static const int arc_num_reloc_op
558= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
559
4670103e
CZ		 560/* Structure for relaxable instruction that have to be swapped with a
561 smaller alternative instruction. */
562struct arc_relaxable_ins
563{
564 /* Mnemonic that should be checked. */
565 const char *mnemonic_r;
566
567 /* Operands that should be checked.
568 Indexes of operands from operand array. */
569 enum rlx_operand_type operands[6];
570
571 /* Flags that should be checked. */
572 unsigned flag_classes[5];
573
574 /* Mnemonic (smaller) alternative to be used later for relaxation. */
575 const char *mnemonic_alt;
576
577 /* Index of operand that generic relaxation has to check. */
578 unsigned opcheckidx;
579
580 /* Base subtype index used. */
581 enum arc_rlx_types subtype;
582};
583
584#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
585 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
586 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
587 (SIZE), \
588 (NEXT) } \
589
590#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
591 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
592 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
593 (SIZE), \
594 (NEXT) } \
595
596
597/* ARC relaxation table. */
598const relax_typeS md_relax_table[] =
599{
600 /* Fake entry. */
601 {0, 0, 0, 0},
602
603 /* BL_S s13 ->
604 BL s25. */
db18dbab
GM		 605 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
606 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 607
608 /* B_S s10 ->
609 B s25. */
db18dbab
GM		 610 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
611 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 612
613 /* ADD_S c,b, u3 ->
614 ADD<.f> a,b,u6 ->
615 ADD<.f> a,b,limm. */
db18dbab
GM		 616 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
617 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
618 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 619
620 /* LD_S a, [b, u7] ->
621 LD<zz><.x><.aa><.di> a, [b, s9] ->
622 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 623 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
624 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
625 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 626
627 /* MOV_S b, u8 ->
628 MOV<.f> b, s12 ->
629 MOV<.f> b, limm. */
db18dbab
GM		 630 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
631 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
632 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 633
634 /* SUB_S c, b, u3 ->
635 SUB<.f> a, b, u6 ->
636 SUB<.f> a, b, limm. */
db18dbab
GM		 637 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
638 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
639 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 640
641 /* MPY<.f> a, b, u6 ->
642 MPY<.f> a, b, limm. */
db18dbab
GM		 643 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
644 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 645
646 /* MOV<.f><.cc> b, u6 ->
647 MOV<.f><.cc> b, limm. */
db18dbab
GM		 648 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
649 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 650
651 /* ADD<.f><.cc> b, b, u6 ->
652 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 653 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
654 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 655};
656
657/* Order of this table's entries matters! */
658const struct arc_relaxable_ins arc_relaxable_insns[] =
659{
660 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
661 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
662 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
663 2, ARC_RLX_ADD_RRU6},
664 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
665 ARC_RLX_ADD_U3 },
666 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
667 ARC_RLX_ADD_U6 },
668 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
669 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
670 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
671 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
672 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
673 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
674 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
675 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
676 ARC_RLX_SUB_U3 },
677 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
678 ARC_RLX_SUB_U6 },
679 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
680 ARC_RLX_MPY_U6 },
681};
682
683const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
684
886a2506
NC		 685/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
686symbolS * GOT_symbol = 0;
687
688/* Set to TRUE when we assemble instructions. */
5b7c81bd 689static bool assembling_insn = false;
886a2506 690
53a346d8 691/* List with attributes set explicitly. */
5b7c81bd 692static bool attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
53a346d8 693
886a2506
NC		 694/* Functions implementation. */
695
b9b47ab7
AB		 696/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
697 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
698 are no matching entries in ARC_OPCODE_HASH. */
da5be039 699
b9b47ab7 700static const struct arc_opcode_hash_entry *
da5be039
AB		 701arc_find_opcode (const char *name)
702{
703 const struct arc_opcode_hash_entry *entry;
da5be039 704
629310ab 705 entry = str_hash_find (arc_opcode_hash, name);
b9b47ab7 706 return entry;
da5be039
AB		 707}
708
1328504b
AB		 709/* Initialise the iterator ITER. */
710
711static void
712arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
713{
714 iter->index = 0;
715 iter->opcode = NULL;
716}
717
718/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
719 calls to this function. Return NULL when all ARC_OPCODE entries have
720 been returned. */
721
722static const struct arc_opcode *
723arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
724 struct arc_opcode_hash_entry_iterator *iter)
725{
726 if (iter->opcode == NULL && iter->index == 0)
727 {
728 gas_assert (entry->count > 0);
729 iter->opcode = entry->opcode[iter->index];
730 }
731 else if (iter->opcode != NULL)
732 {
733 const char *old_name = iter->opcode->name;
734
735 iter->opcode++;
fe779266
AB		 736 if (iter->opcode->name == NULL
737 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 738 {
739 iter->index++;
740 if (iter->index == entry->count)
741 iter->opcode = NULL;
742 else
743 iter->opcode = entry->opcode[iter->index];
744 }
745 }
746
747 return iter->opcode;
748}
749
b99747ae
CZ		 750/* Insert an opcode into opcode hash structure. */
751
752static void
753arc_insert_opcode (const struct arc_opcode *opcode)
754{
629310ab 755 const char *name;
b99747ae
CZ		 756 struct arc_opcode_hash_entry *entry;
757 name = opcode->name;
758
629310ab 759 entry = str_hash_find (arc_opcode_hash, name);
b99747ae
CZ		 760 if (entry == NULL)
761 {
add39d23 762 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 763 entry->count = 0;
764 entry->opcode = NULL;
765
fe0e921f
AM		 766 if (str_hash_insert (arc_opcode_hash, name, entry, 0) != NULL)
767 as_fatal (_("duplicate %s"), name);
b99747ae
CZ		 768 }
769
add39d23
TS		 770 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
771 entry->count + 1);
b99747ae 772
b99747ae
CZ		 773 entry->opcode[entry->count] = opcode;
774 entry->count++;
775}
776
a51628a9
AM		 777static void
778arc_opcode_free (void *elt)
779{
780 string_tuple_t *tuple = (string_tuple_t *) elt;
781 struct arc_opcode_hash_entry *entry = (void *) tuple->value;
782 free (entry->opcode);
783 free (entry);
784 free (tuple);
785}
b99747ae 786
bdfe53e3
AB		 787/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
788 value, is encoded as 'middle-endian' for a little-endian target. This
789 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 790
791static void
bdfe53e3 792md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 793{
bdfe53e3 794 switch (n)
886a2506 795 {
bdfe53e3
AB		 796 case 2:
797 md_number_to_chars (buf, val, n);
798 break;
799 case 6:
53b6d6f5 800 md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
bdfe53e3
AB		 801 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
802 break;
803 case 4:
886a2506
NC		 804 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
805 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 806 break;
807 case 8:
53b6d6f5 808 md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
bdfe53e3
AB		 809 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
810 break;
811 default:
812 abort ();
886a2506 813 }
252b5132
RH		 814}
815
bb050a69
CZ		 816/* Check if a feature is allowed for a specific CPU. */
817
818static void
819arc_check_feature (void)
820{
821 unsigned i;
822
823 if (!selected_cpu.features
824 || !selected_cpu.name)
825 return;
53a346d8
CZ		 826
827 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
828 if ((selected_cpu.features & feature_list[i].feature)
829 && !(selected_cpu.flags & feature_list[i].cpus))
830 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
831 selected_cpu.name);
832
833 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
834 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
835 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 836}
837
24740d83 838/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 839 the relevant static global variables. Parameter SEL describes where
840 this selection originated from. */
24740d83
AB		 841
842static void
bb65a718 843arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 844{
24740d83 845 int i;
5e4f7e05 846 static struct cpu_type old_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
24740d83 847
bb65a718
AB		 848 /* We should only set a default if we've not made a selection from some
849 other source. */
850 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
851 || mach_selection_mode == MACH_SELECTION_NONE);
852
bb050a69
CZ		 853 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
854 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
855 as_bad (_("Multiple .cpu directives found"));
856
bb65a718 857 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 858 for (i = 0; cpu_types[i].name; ++i)
859 {
860 if (!strcasecmp (cpu_types[i].name, arg))
861 {
bb65a718
AB		 862 /* If a previous selection was made on the command line, then we
863 allow later selections on the command line to override earlier
864 ones. However, a selection from a '.cpu NAME' directive must
865 match the command line selection, or we give a warning. */
866 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
867 {
868 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
869 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
870 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
871 && selected_cpu.mach != cpu_types[i].mach)
872 {
873 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 874 }
bb050a69 875 return;
bb65a718 876 }
bb050a69
CZ		 877 /* Initialise static global data about selected machine type. */
878 selected_cpu.flags = cpu_types[i].flags;
879 selected_cpu.name = cpu_types[i].name;
a9752fdf 880 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 881 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 882 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
883 | cpu_types[i].eflags);
24740d83
AB		 884 break;
885 }
886 }
887
888 if (!cpu_types[i].name)
889 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 890
891 /* Check if set features are compatible with the chosen CPU. */
892 arc_check_feature ();
53a346d8 893
5e4f7e05
CZ		 894 /* If we change the CPU, we need to re-init the bfd. */
895 if (mach_selection_mode != MACH_SELECTION_NONE
896 && (old_cpu.mach != selected_cpu.mach))
897 {
898 bfd_find_target (arc_target_format, stdoutput);
899 if (! bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
900 as_warn (_("Could not set architecture and machine"));
901 }
902
bb65a718 903 mach_selection_mode = sel;
5e4f7e05 904 old_cpu = selected_cpu;
24740d83
AB		 905}
906
886a2506
NC		 907/* Here ends all the ARCompact extension instruction assembling
908 stuff. */
252b5132 909
886a2506
NC		 910static void
911arc_extra_reloc (int r_type)
ea1562b3 912{
886a2506
NC		 913 char *sym_name, c;
914 symbolS *sym, *lab = NULL;
915
916 if (*input_line_pointer == '@')
917 input_line_pointer++;
918 c = get_symbol_name (&sym_name);
919 sym = symbol_find_or_make (sym_name);
920 restore_line_pointer (c);
921 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
922 {
923 ++input_line_pointer;
924 char *lab_name;
925 c = get_symbol_name (&lab_name);
926 lab = symbol_find_or_make (lab_name);
927 restore_line_pointer (c);
928 }
841fdfcd
CZ		 929
930 /* These relocations exist as a mechanism for the compiler to tell the
931 linker how to patch the code if the tls model is optimised. However,
932 the relocation itself does not require any space within the assembler
933 fragment, and so we pass a size of 0.
934
935 The lines that generate these relocations look like this:
936
937 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
938
939 The '.tls_gd_ld @.tdata' is processed first and generates the
940 additional relocation, while the 'bl __tls_get_addr@plt' is processed
941 second and generates the additional branch.
942
943 It is possible that the additional relocation generated by the
944 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
945 while the 'bl __tls_get_addr@plt' will be generated as the first thing
946 in the next fragment. This will be fine; both relocations will still
947 appear to be at the same address in the generated object file.
948 However, this only works as the additional relocation is generated
949 with size of 0 bytes. */
886a2506
NC		 950 fixS *fixP
951 = fix_new (frag_now, /* Which frag? */
952 frag_now_fix (), /* Where in that frag? */
841fdfcd 953 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 954 sym, /* X_add_symbol. */
955 0, /* X_add_number. */
5b7c81bd 956 false, /* TRUE if PC-relative relocation. */
886a2506
NC		 957 r_type /* Relocation type. */);
958 fixP->fx_subsy = lab;
959}
252b5132 960
886a2506
NC		 961static symbolS *
962arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
963 symbolS *symbolP, addressT size)
964{
965 addressT align = 0;
966 SKIP_WHITESPACE ();
252b5132 967
886a2506
NC		 968 if (*input_line_pointer == ',')
969 {
970 align = parse_align (1);
252b5132 971
886a2506
NC		 972 if (align == (addressT) -1)
973 return NULL;
974 }
975 else
976 {
977 if (size >= 8)
978 align = 3;
979 else if (size >= 4)
980 align = 2;
981 else if (size >= 2)
982 align = 1;
983 else
984 align = 0;
985 }
252b5132 986
886a2506
NC		 987 bss_alloc (symbolP, size, align);
988 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 989
886a2506
NC		 990 return symbolP;
991}
ea1562b3 992
886a2506
NC		 993static void
994arc_lcomm (int ignore)
995{
996 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 997
886a2506
NC		 998 if (symbolP)
999 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
1000}
ea1562b3 1001
886a2506 1002/* Select the cpu we're assembling for. */
ea1562b3 1003
886a2506
NC		 1004static void
1005arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 1006{
886a2506
NC		 1007 char c;
1008 char *cpu;
bb65a718 1009 const char *cpu_name;
252b5132 1010
886a2506 1011 c = get_symbol_name (&cpu);
252b5132 1012
a9752fdf 1013 cpu_name = cpu;
bb65a718
AB		 1014 if ((!strcmp ("ARC600", cpu))
1015 || (!strcmp ("ARC601", cpu))
1016 || (!strcmp ("A6", cpu)))
1017 cpu_name = "arc600";
1018 else if ((!strcmp ("ARC700", cpu))
1019 || (!strcmp ("A7", cpu)))
1020 cpu_name = "arc700";
1021 else if (!strcmp ("EM", cpu))
1022 cpu_name = "arcem";
1023 else if (!strcmp ("HS", cpu))
1024 cpu_name = "archs";
1025 else if (!strcmp ("NPS400", cpu))
1026 cpu_name = "nps400";
886a2506 1027
a9752fdf 1028 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1029
24b368f8 1030 restore_line_pointer (c);
886a2506 1031 demand_empty_rest_of_line ();
ea1562b3 1032}
252b5132 1033
886a2506
NC		 1034/* Smartly print an expression. */
1035
ea1562b3 1036static void
886a2506 1037debug_exp (expressionS *t)
ea1562b3 1038{
886a2506
NC		 1039 const char *name ATTRIBUTE_UNUSED;
1040 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1041
886a2506 1042 pr_debug ("debug_exp: ");
252b5132 1043
886a2506 1044 switch (t->X_op)
252b5132 1045 {
886a2506
NC		 1046 default: name = "unknown"; break;
1047 case O_illegal: name = "O_illegal"; break;
1048 case O_absent: name = "O_absent"; break;
1049 case O_constant: name = "O_constant"; break;
1050 case O_symbol: name = "O_symbol"; break;
1051 case O_symbol_rva: name = "O_symbol_rva"; break;
1052 case O_register: name = "O_register"; break;
1053 case O_big: name = "O_big"; break;
1054 case O_uminus: name = "O_uminus"; break;
1055 case O_bit_not: name = "O_bit_not"; break;
1056 case O_logical_not: name = "O_logical_not"; break;
1057 case O_multiply: name = "O_multiply"; break;
1058 case O_divide: name = "O_divide"; break;
1059 case O_modulus: name = "O_modulus"; break;
1060 case O_left_shift: name = "O_left_shift"; break;
1061 case O_right_shift: name = "O_right_shift"; break;
1062 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1063 case O_bit_or_not: name = "O_bit_or_not"; break;
1064 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1065 case O_bit_and: name = "O_bit_and"; break;
1066 case O_add: name = "O_add"; break;
1067 case O_subtract: name = "O_subtract"; break;
1068 case O_eq: name = "O_eq"; break;
1069 case O_ne: name = "O_ne"; break;
1070 case O_lt: name = "O_lt"; break;
1071 case O_le: name = "O_le"; break;
1072 case O_ge: name = "O_ge"; break;
1073 case O_gt: name = "O_gt"; break;
1074 case O_logical_and: name = "O_logical_and"; break;
1075 case O_logical_or: name = "O_logical_or"; break;
1076 case O_index: name = "O_index"; break;
1077 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1078 case O_colon: name = "O_colon"; break;
1079 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1080 }
252b5132 1081
886a2506 1082 switch (t->X_md)
ea1562b3 1083 {
886a2506
NC		 1084 default: namemd = "unknown"; break;
1085 case O_gotoff: namemd = "O_gotoff"; break;
1086 case O_gotpc: namemd = "O_gotpc"; break;
1087 case O_plt: namemd = "O_plt"; break;
1088 case O_sda: namemd = "O_sda"; break;
1089 case O_pcl: namemd = "O_pcl"; break;
1090 case O_tlsgd: namemd = "O_tlsgd"; break;
1091 case O_tlsie: namemd = "O_tlsie"; break;
1092 case O_tpoff9: namemd = "O_tpoff9"; break;
1093 case O_tpoff: namemd = "O_tpoff"; break;
1094 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1095 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1096 }
252b5132 1097
886a2506
NC		 1098 pr_debug ("%s (%s, %s, %d, %s)", name,
1099 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1100 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1101 (int) t->X_add_number,
1102 (t->X_md) ? namemd : "--");
1103 pr_debug ("\n");
1104 fflush (stderr);
1105}
252b5132 1106
2a1ebfb2
CZ		 1107/* Helper for parsing an argument, used for sorting out the relocation
1108 type. */
1109
1110static void
1111parse_reloc_symbol (expressionS *resultP)
1112{
1113 char *reloc_name, c, *sym_name;
1114 size_t len;
1115 int i;
1116 const struct arc_reloc_op_tag *r;
1117 expressionS right;
1118 symbolS *base;
1119
1120 /* A relocation operand has the following form
1121 @identifier@relocation_type. The identifier is already in
1122 tok! */
1123 if (resultP->X_op != O_symbol)
1124 {
1125 as_bad (_("No valid label relocation operand"));
1126 resultP->X_op = O_illegal;
1127 return;
1128 }
1129
1130 /* Parse @relocation_type. */
1131 input_line_pointer++;
1132 c = get_symbol_name (&reloc_name);
1133 len = input_line_pointer - reloc_name;
1134 if (len == 0)
1135 {
1136 as_bad (_("No relocation operand"));
1137 resultP->X_op = O_illegal;
1138 return;
1139 }
1140
1141 /* Go through known relocation and try to find a match. */
1142 r = &arc_reloc_op[0];
1143 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
1144 if (len == r->length
1145 && memcmp (reloc_name, r->name, len) == 0)
1146 break;
1147 if (i < 0)
1148 {
1149 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
1150 resultP->X_op = O_illegal;
1151 return;
1152 }
1153
1154 *input_line_pointer = c;
1155 SKIP_WHITESPACE_AFTER_NAME ();
1156 /* Extra check for TLS: base. */
1157 if (*input_line_pointer == '@')
1158 {
1159 if (resultP->X_op_symbol != NULL
1160 || resultP->X_op != O_symbol)
1161 {
1162 as_bad (_("Unable to parse TLS base: %s"),
1163 input_line_pointer);
1164 resultP->X_op = O_illegal;
1165 return;
1166 }
1167 input_line_pointer++;
1168 c = get_symbol_name (&sym_name);
1169 base = symbol_find_or_make (sym_name);
1170 resultP->X_op = O_subtract;
1171 resultP->X_op_symbol = base;
1172 restore_line_pointer (c);
1173 right.X_add_number = 0;
1174 }
1175
1176 if ((*input_line_pointer != '+')
1177 && (*input_line_pointer != '-'))
1178 right.X_add_number = 0;
1179 else
1180 {
1181 /* Parse the constant of a complex relocation expression
1182 like @identifier@reloc +/- const. */
1183 if (! r->complex_expr)
1184 {
1185 as_bad (_("@%s is not a complex relocation."), r->name);
1186 resultP->X_op = O_illegal;
1187 return;
1188 }
1189 expression (&right);
1190 if (right.X_op != O_constant)
1191 {
1192 as_bad (_("Bad expression: @%s + %s."),
1193 r->name, input_line_pointer);
1194 resultP->X_op = O_illegal;
1195 return;
1196 }
1197 }
1198
1199 resultP->X_md = r->op;
1200 resultP->X_add_number = right.X_add_number;
1201}
1202
886a2506
NC		 1203/* Parse the arguments to an opcode. */
1204
1205static int
1206tokenize_arguments (char *str,
1207 expressionS *tok,
1208 int ntok)
1209{
1210 char *old_input_line_pointer;
5b7c81bd
AM		 1211 bool saw_comma = false;
1212 bool saw_arg = false;
886a2506
NC		 1213 int brk_lvl = 0;
1214 int num_args = 0;
886a2506
NC		 1215
1216 memset (tok, 0, sizeof (*tok) * ntok);
1217
1218 /* Save and restore input_line_pointer around this function. */
1219 old_input_line_pointer = input_line_pointer;
1220 input_line_pointer = str;
ea1562b3 1221
886a2506 1222 while (*input_line_pointer)
ea1562b3
NC		 1223 {
1224 SKIP_WHITESPACE ();
886a2506 1225 switch (*input_line_pointer)
252b5132 1226 {
886a2506
NC		 1227 case '\0':
1228 goto fini;
1229
1230 case ',':
1231 input_line_pointer++;
1232 if (saw_comma || !saw_arg)
1233 goto err;
5b7c81bd 1234 saw_comma = true;
886a2506 1235 break;
252b5132 1236
886a2506
NC		 1237 case '}':
1238 case ']':
1239 ++input_line_pointer;
1240 --brk_lvl;
3b889a78 1241 if (!saw_arg || num_args == ntok)
886a2506
NC		 1242 goto err;
1243 tok->X_op = O_bracket;
1244 ++tok;
1245 ++num_args;
1246 break;
ea1562b3 1247
886a2506
NC		 1248 case '{':
1249 case '[':
1250 input_line_pointer++;
3b889a78 1251 if (brk_lvl || num_args == ntok)
886a2506
NC		 1252 goto err;
1253 ++brk_lvl;
1254 tok->X_op = O_bracket;
1255 ++tok;
1256 ++num_args;
1257 break;
1258
db18dbab
GM		 1259 case ':':
1260 input_line_pointer++;
1261 if (!saw_arg || num_args == ntok)
1262 goto err;
1263 tok->X_op = O_colon;
5b7c81bd 1264 saw_arg = false;
db18dbab
GM		 1265 ++tok;
1266 ++num_args;
1267 break;
1268
886a2506
NC		 1269 case '@':
1270 /* We have labels, function names and relocations, all
1271 starting with @ symbol. Sort them out. */
3b889a78 1272 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1273 goto err;
1274
1275 /* Parse @label. */
2a1ebfb2 1276 input_line_pointer++;
886a2506
NC		 1277 tok->X_op = O_symbol;
1278 tok->X_md = O_absent;
1279 expression (tok);
886a2506 1280
886a2506 1281 if (*input_line_pointer == '@')
2a1ebfb2 1282 parse_reloc_symbol (tok);
1e07b820 1283
886a2506 1284 debug_exp (tok);
ea1562b3 1285
2a1ebfb2
CZ		 1286 if (tok->X_op == O_illegal
1287 || tok->X_op == O_absent
1288 || num_args == ntok)
1289 goto err;
1290
5b7c81bd
AM		 1291 saw_comma = false;
1292 saw_arg = true;
886a2506
NC		 1293 tok++;
1294 num_args++;
1295 break;
252b5132 1296
886a2506
NC		 1297 case '%':
1298 /* Can be a register. */
1299 ++input_line_pointer;
1300 /* Fall through. */
1301 default:
252b5132 1302
3b889a78 1303 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1304 goto err;
252b5132 1305
886a2506 1306 tok->X_op = O_absent;
6f4b1afc 1307 tok->X_md = O_absent;
886a2506 1308 expression (tok);
252b5132 1309
6f4b1afc
CM		 1310 /* Legacy: There are cases when we have
1311 identifier@relocation_type, if it is the case parse the
1312 relocation type as well. */
1313 if (*input_line_pointer == '@')
2a1ebfb2 1314 parse_reloc_symbol (tok);
6f4b1afc 1315
886a2506 1316 debug_exp (tok);
252b5132 1317
3b889a78
AB		 1318 if (tok->X_op == O_illegal
1319 || tok->X_op == O_absent
1320 || num_args == ntok)
886a2506 1321 goto err;
252b5132 1322
5b7c81bd
AM		 1323 saw_comma = false;
1324 saw_arg = true;
886a2506
NC		 1325 tok++;
1326 num_args++;
1327 break;
1328 }
ea1562b3 1329 }
252b5132 1330
886a2506
NC		 1331 fini:
1332 if (saw_comma || brk_lvl)
1333 goto err;
1334 input_line_pointer = old_input_line_pointer;
252b5132 1335
886a2506 1336 return num_args;
252b5132 1337
886a2506
NC		 1338 err:
1339 if (brk_lvl)
1340 as_bad (_("Brackets in operand field incorrect"));
1341 else if (saw_comma)
1342 as_bad (_("extra comma"));
1343 else if (!saw_arg)
1344 as_bad (_("missing argument"));
1345 else
1346 as_bad (_("missing comma or colon"));
1347 input_line_pointer = old_input_line_pointer;
1348 return -1;
252b5132 1349}
ea1562b3 1350
886a2506
NC		 1351/* Parse the flags to a structure. */
1352
1353static int
1354tokenize_flags (const char *str,
1355 struct arc_flags flags[],
1356 int nflg)
252b5132 1357{
886a2506 1358 char *old_input_line_pointer;
5b7c81bd
AM		 1359 bool saw_flg = false;
1360 bool saw_dot = false;
886a2506
NC		 1361 int num_flags = 0;
1362 size_t flgnamelen;
252b5132 1363
886a2506 1364 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1365
886a2506
NC		 1366 /* Save and restore input_line_pointer around this function. */
1367 old_input_line_pointer = input_line_pointer;
1368 input_line_pointer = (char *) str;
0d2bcfaf 1369
886a2506
NC		 1370 while (*input_line_pointer)
1371 {
1372 switch (*input_line_pointer)
1373 {
1374 case ' ':
1375 case '\0':
1376 goto fini;
1377
1378 case '.':
1379 input_line_pointer++;
1380 if (saw_dot)
1381 goto err;
5b7c81bd
AM		 1382 saw_dot = true;
1383 saw_flg = false;
886a2506 1384 break;
ea1562b3 1385
886a2506
NC		 1386 default:
1387 if (saw_flg && !saw_dot)
1388 goto err;
0d2bcfaf 1389
886a2506
NC		 1390 if (num_flags >= nflg)
1391 goto err;
0d2bcfaf 1392
692166c2
AB		 1393 flgnamelen = strspn (input_line_pointer,
1394 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1395 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1396 goto err;
0d2bcfaf 1397
886a2506 1398 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1399
886a2506
NC		 1400 input_line_pointer += flgnamelen;
1401 flags++;
5b7c81bd
AM		 1402 saw_dot = false;
1403 saw_flg = true;
886a2506
NC		 1404 num_flags++;
1405 break;
1e07b820 1406 }
0d2bcfaf
NC		 1407 }
1408
886a2506
NC		 1409 fini:
1410 input_line_pointer = old_input_line_pointer;
1411 return num_flags;
0d2bcfaf 1412
886a2506
NC		 1413 err:
1414 if (saw_dot)
1415 as_bad (_("extra dot"));
1416 else if (!saw_flg)
1417 as_bad (_("unrecognized flag"));
1418 else
1419 as_bad (_("failed to parse flags"));
1420 input_line_pointer = old_input_line_pointer;
1421 return -1;
1422}
0d2bcfaf 1423
4670103e 1424/* Apply the fixups in order. */
0d2bcfaf 1425
4670103e
CZ		 1426static void
1427apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1428{
4670103e 1429 int i;
0d2bcfaf 1430
4670103e 1431 for (i = 0; i < insn->nfixups; i++)
252b5132 1432 {
4670103e
CZ		 1433 struct arc_fixup *fixup = &insn->fixups[i];
1434 int size, pcrel, offset = 0;
0d2bcfaf 1435
4670103e
CZ		 1436 /* FIXME! the reloc size is wrong in the BFD file.
1437 When it is fixed please delete me. */
91fdca6f 1438 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1439
4670103e 1440 if (fixup->islong)
91fdca6f 1441 offset = insn->len;
252b5132 1442
4670103e
CZ		 1443 /* Some fixups are only used internally, thus no howto. */
1444 if ((int) fixup->reloc == 0)
1445 as_fatal (_("Unhandled reloc type"));
886a2506 1446
4670103e
CZ		 1447 if ((int) fixup->reloc < 0)
1448 {
1449 /* FIXME! the reloc size is wrong in the BFD file.
1450 When it is fixed please enable me.
91fdca6f 1451 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1452 pcrel = fixup->pcrel;
1453 }
1454 else
1455 {
1456 reloc_howto_type *reloc_howto =
1457 bfd_reloc_type_lookup (stdoutput,
1458 (bfd_reloc_code_real_type) fixup->reloc);
1459 gas_assert (reloc_howto);
0d2bcfaf 1460
4670103e
CZ		 1461 /* FIXME! the reloc size is wrong in the BFD file.
1462 When it is fixed please enable me.
1463 size = bfd_get_reloc_size (reloc_howto); */
1464 pcrel = reloc_howto->pc_relative;
1465 }
0d2bcfaf 1466
4670103e
CZ		 1467 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1468offset %d + %d\n",
1469 fragP->fr_file, fragP->fr_line,
1470 (fixup->reloc < 0) ? "Internal" :
1471 bfd_get_reloc_code_name (fixup->reloc),
1472 pcrel ? "Y" : "N",
1473 size, fix, offset);
1474 fix_new_exp (fragP, fix + offset,
1475 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1476
4670103e
CZ		 1477 /* Check for ZOLs, and update symbol info if any. */
1478 if (LP_INSN (insn->insn))
886a2506 1479 {
4670103e
CZ		 1480 gas_assert (fixup->exp.X_add_symbol);
1481 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1482 }
1483 }
252b5132
RH		 1484}
1485
4670103e 1486/* Actually output an instruction with its fixup. */
886a2506 1487
4670103e 1488static void
5b7c81bd 1489emit_insn0 (struct arc_insn *insn, char *where, bool relax)
252b5132 1490{
4670103e 1491 char *f = where;
91fdca6f 1492 size_t total_len;
252b5132 1493
bdfe53e3 1494 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
777cd7ab 1495 pr_debug ("\tLength : %d\n", insn->len);
4670103e 1496 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1497
4670103e 1498 /* Write out the instruction. */
91fdca6f
GM		 1499 total_len = insn->len + (insn->has_limm ? 4 : 0);
1500 if (!relax)
1501 f = frag_more (total_len);
1502
1503 md_number_to_chars_midend(f, insn->insn, insn->len);
1504
1505 if (insn->has_limm)
1506 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1507 dwarf2_emit_insn (total_len);
252b5132 1508
4670103e
CZ		 1509 if (!relax)
1510 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1511}
252b5132 1512
4670103e
CZ		 1513static void
1514emit_insn1 (struct arc_insn *insn)
1515{
1516 /* How frag_var's args are currently configured:
1517 - rs_machine_dependent, to dictate it's a relaxation frag.
1518 - FRAG_MAX_GROWTH, maximum size of instruction
1519 - 0, variable size that might grow...unused by generic relaxation.
1520 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1521 - s, opand expression.
1522 - 0, offset but it's unused.
1523 - 0, opcode but it's unused. */
1524 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1525 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1526
1527 if (frag_room () < FRAG_MAX_GROWTH)
1528 {
1529 /* Handle differently when frag literal memory is exhausted.
1530 This is used because when there's not enough memory left in
1531 the current frag, a new frag is created and the information
1532 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1533
4670103e
CZ		 1534 struct arc_relax_type relax_info_copy;
1535 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1536
4670103e
CZ		 1537 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1538 sizeof (struct arc_relax_type));
0d2bcfaf 1539
4670103e
CZ		 1540 frag_wane (frag_now);
1541 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1542
4670103e
CZ		 1543 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1544 sizeof (struct arc_relax_type));
252b5132 1545
4670103e
CZ		 1546 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1547 subtype, s, 0, 0);
1548 }
1549 else
1550 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1551 frag_now->fr_subtype, s, 0, 0);
1552}
252b5132 1553
4670103e
CZ		 1554static void
1555emit_insn (struct arc_insn *insn)
252b5132 1556{
4670103e
CZ		 1557 if (insn->relax)
1558 emit_insn1 (insn);
252b5132 1559 else
5b7c81bd 1560 emit_insn0 (insn, NULL, false);
252b5132
RH		 1561}
1562
4670103e 1563/* Check whether a symbol involves a register. */
252b5132 1564
5b7c81bd 1565static bool
4670103e 1566contains_register (symbolS *sym)
252b5132 1567{
4670103e
CZ		 1568 if (sym)
1569 {
1570 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1571
4670103e
CZ		 1572 return ((O_register == ex->X_op)
1573 && !contains_register (ex->X_add_symbol)
1574 && !contains_register (ex->X_op_symbol));
1575 }
1576
5b7c81bd 1577 return false;
252b5132
RH		 1578}
1579
4670103e 1580/* Returns the register number within a symbol. */
252b5132 1581
4670103e
CZ		 1582static int
1583get_register (symbolS *sym)
252b5132 1584{
4670103e
CZ		 1585 if (!contains_register (sym))
1586 return -1;
0d2bcfaf 1587
4670103e
CZ		 1588 expressionS *ex = symbol_get_value_expression (sym);
1589 return regno (ex->X_add_number);
1590}
252b5132 1591
4670103e
CZ		 1592/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1593 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1594
5b7c81bd 1595static bool
4670103e
CZ		 1596generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1597{
1598 if (!reloc)
5b7c81bd 1599 return false;
886a2506 1600
4670103e
CZ		 1601 switch (reloc)
1602 {
1603 case BFD_RELOC_ARC_SDA_LDST:
1604 case BFD_RELOC_ARC_SDA_LDST1:
1605 case BFD_RELOC_ARC_SDA_LDST2:
1606 case BFD_RELOC_ARC_SDA16_LD:
1607 case BFD_RELOC_ARC_SDA16_LD1:
1608 case BFD_RELOC_ARC_SDA16_LD2:
1609 case BFD_RELOC_ARC_SDA16_ST2:
1610 case BFD_RELOC_ARC_SDA32_ME:
5b7c81bd 1611 return false;
4670103e 1612 default:
5b7c81bd 1613 return true;
f17c130b 1614 }
252b5132
RH		 1615}
1616
4670103e 1617/* Allocates a tok entry. */
252b5132 1618
4670103e
CZ		 1619static int
1620allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1621{
4670103e
CZ		 1622 if (ntok > MAX_INSN_ARGS - 2)
1623 return 0; /* No space left. */
252b5132 1624
4670103e 1625 if (cidx > ntok)
33eaf5de 1626 return 0; /* Incorrect args. */
252b5132 1627
4670103e 1628 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1629
4670103e
CZ		 1630 if (cidx == ntok)
1631 return 1; /* Success. */
1632 return allocate_tok (tok, ntok - 1, cidx);
1633}
886a2506 1634
8ddf6b2a
CZ		 1635/* Check if an particular ARC feature is enabled. */
1636
5b7c81bd 1637static bool
8ddf6b2a
CZ		 1638check_cpu_feature (insn_subclass_t sc)
1639{
53a346d8 1640 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
5b7c81bd 1641 return false;
8ddf6b2a 1642
53a346d8 1643 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
5b7c81bd 1644 return false;
8ddf6b2a 1645
53a346d8 1646 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
5b7c81bd 1647 return false;
8ddf6b2a 1648
53a346d8 1649 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
5b7c81bd 1650 return false;
bdd582db 1651
53a346d8 1652 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
5b7c81bd 1653 return false;
8ddf6b2a 1654
5b7c81bd 1655 return true;
8ddf6b2a
CZ		 1656}
1657
4eb6f892
AB		 1658/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1659 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1660 array and returns TRUE if the flag operands all match, otherwise,
1661 returns FALSE, in which case the FIRST_PFLAG array may have been
1662 modified. */
1663
5b7c81bd 1664static bool
4eb6f892
AB		 1665parse_opcode_flags (const struct arc_opcode *opcode,
1666 int nflgs,
1667 struct arc_flags *first_pflag)
1668{
1669 int lnflg, i;
1670 const unsigned char *flgidx;
1671
1672 lnflg = nflgs;
1673 for (i = 0; i < nflgs; i++)
1674 first_pflag[i].flgp = NULL;
1675
1676 /* Check the flags. Iterate over the valid flag classes. */
1677 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1678 {
1679 /* Get a valid flag class. */
1680 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1681 const unsigned *flgopridx;
1682 int cl_matches = 0;
1683 struct arc_flags *pflag = NULL;
1684
6ec7c1ae
CZ		 1685 /* Check if opcode has implicit flag classes. */
1686 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1687 continue;
1688
4eb6f892
AB		 1689 /* Check for extension conditional codes. */
1690 if (ext_condcode.arc_ext_condcode
1691 && cl_flags->flag_class & F_CLASS_EXTEND)
1692 {
1693 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1694 while (pf->name)
1695 {
1696 pflag = first_pflag;
1697 for (i = 0; i < nflgs; i++, pflag++)
1698 {
1699 if (!strcmp (pf->name, pflag->name))
1700 {
1701 if (pflag->flgp != NULL)
5b7c81bd 1702 return false;
4eb6f892
AB		 1703 /* Found it. */
1704 cl_matches++;
1705 pflag->flgp = pf;
1706 lnflg--;
1707 break;
1708 }
1709 }
1710 pf++;
1711 }
1712 }
1713
1714 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1715 {
1716 const struct arc_flag_operand *flg_operand;
1717
1718 pflag = first_pflag;
1719 flg_operand = &arc_flag_operands[*flgopridx];
1720 for (i = 0; i < nflgs; i++, pflag++)
1721 {
1722 /* Match against the parsed flags. */
1723 if (!strcmp (flg_operand->name, pflag->name))
1724 {
1725 if (pflag->flgp != NULL)
5b7c81bd 1726 return false;
4eb6f892
AB		 1727 cl_matches++;
1728 pflag->flgp = flg_operand;
1729 lnflg--;
1730 break; /* goto next flag class and parsed flag. */
1731 }
1732 }
1733 }
1734
1735 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
5b7c81bd 1736 return false;
4eb6f892 1737 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
5b7c81bd 1738 return false;
4eb6f892
AB		 1739 }
1740
1741 /* Did I check all the parsed flags? */
63b4cc53 1742 return lnflg == 0;
4eb6f892
AB		 1743}
1744
1745
4670103e
CZ		 1746/* Search forward through all variants of an opcode looking for a
1747 syntax match. */
886a2506 1748
4670103e 1749static const struct arc_opcode *
b9b47ab7 1750find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1751 expressionS *tok,
1752 int *pntok,
1753 struct arc_flags *first_pflag,
1754 int nflgs,
abe7c33b
CZ		 1755 int *pcpumatch,
1756 const char **errmsg)
4670103e 1757{
1328504b
AB		 1758 const struct arc_opcode *opcode;
1759 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1760 int ntok = *pntok;
1761 int got_cpu_match = 0;
1762 expressionS bktok[MAX_INSN_ARGS];
3128916d 1763 int bkntok, maxerridx = 0;
4670103e 1764 expressionS emptyE;
3128916d 1765 const char *tmpmsg = NULL;
886a2506 1766
1328504b 1767 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1768 memset (&emptyE, 0, sizeof (emptyE));
1769 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1770 bkntok = ntok;
a161fe53 1771
1328504b
AB		 1772 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1773 opcode != NULL;
1774 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1775 {
4670103e 1776 const unsigned char *opidx;
4eb6f892 1777 int tokidx = 0;
4670103e 1778 const expressionS *t = &emptyE;
252b5132 1779
bdfe53e3 1780 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1781 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1782
4670103e
CZ		 1783 /* Don't match opcodes that don't exist on this
1784 architecture. */
bb65a718 1785 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1786 goto match_failed;
886a2506 1787
8ddf6b2a 1788 if (!check_cpu_feature (opcode->subclass))
4670103e 1789 goto match_failed;
886a2506 1790
4670103e
CZ		 1791 got_cpu_match = 1;
1792 pr_debug ("cpu ");
886a2506 1793
4670103e
CZ		 1794 /* Check the operands. */
1795 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1796 {
4670103e 1797 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1798
4670103e 1799 /* Only take input from real operands. */
db18dbab 1800 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1801 continue;
252b5132 1802
4670103e
CZ		 1803 /* When we expect input, make sure we have it. */
1804 if (tokidx >= ntok)
1805 goto match_failed;
6f4b1afc 1806
4670103e
CZ		 1807 /* Match operand type with expression type. */
1808 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1809 {
db18dbab 1810 case ARC_OPERAND_ADDRTYPE:
b437d035 1811 {
3128916d 1812 tmpmsg = NULL;
b437d035
AB		 1813
1814 /* Check to be an address type. */
1815 if (tok[tokidx].X_op != O_addrtype)
1816 goto match_failed;
1817
1818 /* All address type operands need to have an insert
1819 method in order to check that we have the correct
1820 address type. */
1821 gas_assert (operand->insert != NULL);
1822 (*operand->insert) (0, tok[tokidx].X_add_number,
3128916d
CZ		 1823 &tmpmsg);
1824 if (tmpmsg != NULL)
b437d035
AB		 1825 goto match_failed;
1826 }
db18dbab
GM		 1827 break;
1828
4670103e
CZ		 1829 case ARC_OPERAND_IR:
1830 /* Check to be a register. */
1831 if ((tok[tokidx].X_op != O_register
1832 || !is_ir_num (tok[tokidx].X_add_number))
1833 && !(operand->flags & ARC_OPERAND_IGNORE))
1834 goto match_failed;
1835
1836 /* If expect duplicate, make sure it is duplicate. */
1837 if (operand->flags & ARC_OPERAND_DUPLICATE)
1838 {
1839 /* Check for duplicate. */
1840 if (t->X_op != O_register
1841 || !is_ir_num (t->X_add_number)
1842 || (regno (t->X_add_number) !=
1843 regno (tok[tokidx].X_add_number)))
1844 goto match_failed;
1845 }
1846
1847 /* Special handling? */
1848 if (operand->insert)
1849 {
3128916d 1850 tmpmsg = NULL;
4670103e
CZ		 1851 (*operand->insert)(0,
1852 regno (tok[tokidx].X_add_number),
3128916d
CZ		 1853 &tmpmsg);
1854 if (tmpmsg)
4670103e
CZ		 1855 {
1856 if (operand->flags & ARC_OPERAND_IGNORE)
1857 {
1858 /* Missing argument, create one. */
1859 if (!allocate_tok (tok, ntok - 1, tokidx))
1860 goto match_failed;
1861
1862 tok[tokidx].X_op = O_absent;
1863 ++ntok;
1864 }
1865 else
1866 goto match_failed;
1867 }
1868 }
1869
1870 t = &tok[tokidx];
1871 break;
1872
1873 case ARC_OPERAND_BRAKET:
1874 /* Check if bracket is also in opcode table as
1875 operand. */
1876 if (tok[tokidx].X_op != O_bracket)
1877 goto match_failed;
1878 break;
1879
db18dbab
GM		 1880 case ARC_OPERAND_COLON:
1881 /* Check if colon is also in opcode table as operand. */
1882 if (tok[tokidx].X_op != O_colon)
1883 goto match_failed;
1884 break;
1885
4670103e
CZ		 1886 case ARC_OPERAND_LIMM:
1887 case ARC_OPERAND_SIGNED:
1888 case ARC_OPERAND_UNSIGNED:
1889 switch (tok[tokidx].X_op)
1890 {
1891 case O_illegal:
1892 case O_absent:
1893 case O_register:
1894 goto match_failed;
1895
1896 case O_bracket:
1897 /* Got an (too) early bracket, check if it is an
1898 ignored operand. N.B. This procedure works only
1899 when bracket is the last operand! */
1900 if (!(operand->flags & ARC_OPERAND_IGNORE))
1901 goto match_failed;
1902 /* Insert the missing operand. */
1903 if (!allocate_tok (tok, ntok - 1, tokidx))
1904 goto match_failed;
1905
1906 tok[tokidx].X_op = O_absent;
1907 ++ntok;
1908 break;
1909
22b92fc4
AB		 1910 case O_symbol:
1911 {
1912 const char *p;
b6523c37 1913 char *tmpp, *pp;
22b92fc4 1914 const struct arc_aux_reg *auxr;
22b92fc4 1915
c810e0b8 1916 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1917 goto de_fault;
1918 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da 1919
b6523c37 1920 /* For compatibility reasons, an aux register can
1921 be spelled with upper or lower case
1922 letters. */
1923 tmpp = strdup (p);
1924 for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
1925
629310ab 1926 auxr = str_hash_find (arc_aux_hash, tmpp);
f36e33da
CZ		 1927 if (auxr)
1928 {
1929 /* We modify the token array here, safe in the
1930 knowledge, that if this was the wrong
1931 choice then the original contents will be
1932 restored from BKTOK. */
1933 tok[tokidx].X_op = O_constant;
1934 tok[tokidx].X_add_number = auxr->address;
1935 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1936 }
b6523c37 1937 free (tmpp);
22b92fc4
AB		 1938
1939 if (tok[tokidx].X_op != O_constant)
1940 goto de_fault;
1941 }
1a0670f3 1942 /* Fall through. */
4670103e
CZ		 1943 case O_constant:
1944 /* Check the range. */
1945 if (operand->bits != 32
1946 && !(operand->flags & ARC_OPERAND_NCHK))
1947 {
1948 offsetT min, max, val;
1949 val = tok[tokidx].X_add_number;
1950
1951 if (operand->flags & ARC_OPERAND_SIGNED)
1952 {
1953 max = (1 << (operand->bits - 1)) - 1;
1954 min = -(1 << (operand->bits - 1));
1955 }
1956 else
1957 {
1958 max = (1 << operand->bits) - 1;
1959 min = 0;
1960 }
1961
1962 if (val < min || val > max)
3128916d
CZ		 1963 {
1964 tmpmsg = _("immediate is out of bounds");
1965 goto match_failed;
1966 }
4670103e 1967
33eaf5de 1968 /* Check alignments. */
4670103e
CZ		 1969 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1970 && (val & 0x03))
3128916d
CZ		 1971 {
1972 tmpmsg = _("immediate is not 32bit aligned");
1973 goto match_failed;
1974 }
4670103e
CZ		 1975
1976 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1977 && (val & 0x01))
3128916d
CZ		 1978 {
1979 tmpmsg = _("immediate is not 16bit aligned");
1980 goto match_failed;
1981 }
4670103e
CZ		 1982 }
1983 else if (operand->flags & ARC_OPERAND_NCHK)
1984 {
1985 if (operand->insert)
1986 {
3128916d 1987 tmpmsg = NULL;
4670103e
CZ		 1988 (*operand->insert)(0,
1989 tok[tokidx].X_add_number,
3128916d
CZ		 1990 &tmpmsg);
1991 if (tmpmsg)
4670103e
CZ		 1992 goto match_failed;
1993 }
4eb6f892 1994 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1995 goto match_failed;
1996 }
1997 break;
1998
1999 case O_subtract:
2000 /* Check if it is register range. */
2001 if ((tok[tokidx].X_add_number == 0)
2002 && contains_register (tok[tokidx].X_add_symbol)
2003 && contains_register (tok[tokidx].X_op_symbol))
2004 {
2005 int regs;
2006
2007 regs = get_register (tok[tokidx].X_add_symbol);
2008 regs <<= 16;
2009 regs |= get_register (tok[tokidx].X_op_symbol);
2010 if (operand->insert)
2011 {
3128916d 2012 tmpmsg = NULL;
4670103e
CZ		 2013 (*operand->insert)(0,
2014 regs,
3128916d
CZ		 2015 &tmpmsg);
2016 if (tmpmsg)
4670103e
CZ		 2017 goto match_failed;
2018 }
2019 else
2020 goto match_failed;
2021 break;
2022 }
1a0670f3 2023 /* Fall through. */
4670103e 2024 default:
22b92fc4 2025 de_fault:
4670103e
CZ		 2026 if (operand->default_reloc == 0)
2027 goto match_failed; /* The operand needs relocation. */
2028
2029 /* Relocs requiring long immediate. FIXME! make it
2030 generic and move it to a function. */
2031 switch (tok[tokidx].X_md)
2032 {
2033 case O_gotoff:
2034 case O_gotpc:
2035 case O_pcl:
2036 case O_tpoff:
2037 case O_dtpoff:
2038 case O_tlsgd:
2039 case O_tlsie:
2040 if (!(operand->flags & ARC_OPERAND_LIMM))
2041 goto match_failed;
1a0670f3 2042 /* Fall through. */
4670103e
CZ		 2043 case O_absent:
2044 if (!generic_reloc_p (operand->default_reloc))
2045 goto match_failed;
2b804145 2046 break;
4670103e
CZ		 2047 default:
2048 break;
2049 }
2050 break;
2051 }
2052 /* If expect duplicate, make sure it is duplicate. */
2053 if (operand->flags & ARC_OPERAND_DUPLICATE)
2054 {
2055 if (t->X_op == O_illegal
2056 || t->X_op == O_absent
2057 || t->X_op == O_register
2058 || (t->X_add_number != tok[tokidx].X_add_number))
3128916d
CZ		 2059 {
2060 tmpmsg = _("operand is not duplicate of the "
2061 "previous one");
2062 goto match_failed;
2063 }
4670103e
CZ		 2064 }
2065 t = &tok[tokidx];
2066 break;
2067
2068 default:
2069 /* Everything else should have been fake. */
2070 abort ();
2071 }
2072
2073 ++tokidx;
2074 }
2075 pr_debug ("opr ");
2076
1ae8ab47 2077 /* Setup ready for flag parsing. */
4eb6f892 2078 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
3128916d
CZ		 2079 {
2080 tmpmsg = _("flag mismatch");
2081 goto match_failed;
2082 }
4670103e
CZ		 2083
2084 pr_debug ("flg");
2085 /* Possible match -- did we use all of our input? */
2086 if (tokidx == ntok)
2087 {
2088 *pntok = ntok;
2089 pr_debug ("\n");
2090 return opcode;
2091 }
3128916d 2092 tmpmsg = _("too many arguments");
4670103e
CZ		 2093
2094 match_failed:;
2095 pr_debug ("\n");
2096 /* Restore the original parameters. */
2097 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2098 ntok = bkntok;
3128916d
CZ		 2099 if (tokidx >= maxerridx
2100 && tmpmsg)
2101 {
2102 maxerridx = tokidx;
2103 *errmsg = tmpmsg;
2104 }
4670103e 2105 }
4670103e
CZ		 2106
2107 if (*pcpumatch)
2108 *pcpumatch = got_cpu_match;
2109
2110 return NULL;
2111}
2112
2113/* Swap operand tokens. */
2114
2115static void
2116swap_operand (expressionS *operand_array,
2117 unsigned source,
2118 unsigned destination)
2119{
2120 expressionS cpy_operand;
2121 expressionS *src_operand;
2122 expressionS *dst_operand;
2123 size_t size;
2124
2125 if (source == destination)
2126 return;
2127
2128 src_operand = &operand_array[source];
2129 dst_operand = &operand_array[destination];
2130 size = sizeof (expressionS);
2131
2132 /* Make copy of operand to swap with and swap. */
2133 memcpy (&cpy_operand, dst_operand, size);
2134 memcpy (dst_operand, src_operand, size);
2135 memcpy (src_operand, &cpy_operand, size);
2136}
2137
2138/* Check if *op matches *tok type.
2139 Returns FALSE if they don't match, TRUE if they match. */
2140
5b7c81bd 2141static bool
4670103e
CZ		 2142pseudo_operand_match (const expressionS *tok,
2143 const struct arc_operand_operation *op)
2144{
2145 offsetT min, max, val;
5b7c81bd 2146 bool ret;
4670103e
CZ		 2147 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2148
5b7c81bd 2149 ret = false;
4670103e
CZ		 2150 switch (tok->X_op)
2151 {
2152 case O_constant:
2153 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2154 ret = 1;
2155 else if (!(operand_real->flags & ARC_OPERAND_IR))
2156 {
2157 val = tok->X_add_number + op->count;
2158 if (operand_real->flags & ARC_OPERAND_SIGNED)
2159 {
2160 max = (1 << (operand_real->bits - 1)) - 1;
2161 min = -(1 << (operand_real->bits - 1));
2162 }
2163 else
2164 {
2165 max = (1 << operand_real->bits) - 1;
2166 min = 0;
2167 }
2168 if (min <= val && val <= max)
5b7c81bd 2169 ret = true;
4670103e 2170 }
6f4b1afc
CM		 2171 break;
2172
4670103e
CZ		 2173 case O_symbol:
2174 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2175 if (operand_real->flags & ARC_OPERAND_LIMM
2176 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2177 && operand_real->bits == 9))
5b7c81bd 2178 ret = true;
6f4b1afc
CM		 2179 break;
2180
4670103e
CZ		 2181 case O_register:
2182 if (operand_real->flags & ARC_OPERAND_IR)
5b7c81bd 2183 ret = true;
4670103e
CZ		 2184 break;
2185
2186 case O_bracket:
2187 if (operand_real->flags & ARC_OPERAND_BRAKET)
5b7c81bd 2188 ret = true;
6f4b1afc
CM		 2189 break;
2190
2191 default:
4670103e 2192 /* Unknown. */
6f4b1afc
CM		 2193 break;
2194 }
4670103e
CZ		 2195 return ret;
2196}
6f4b1afc 2197
4670103e
CZ		 2198/* Find pseudo instruction in array. */
2199
2200static const struct arc_pseudo_insn *
2201find_pseudo_insn (const char *opname,
2202 int ntok,
2203 const expressionS *tok)
2204{
2205 const struct arc_pseudo_insn *pseudo_insn = NULL;
2206 const struct arc_operand_operation *op;
2207 unsigned int i;
2208 int j;
2209
2210 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2211 {
4670103e
CZ		 2212 pseudo_insn = &arc_pseudo_insns[i];
2213 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2214 {
2215 op = pseudo_insn->operand;
2216 for (j = 0; j < ntok; ++j)
2217 if (!pseudo_operand_match (&tok[j], &op[j]))
2218 break;
2219
2220 /* Found the right instruction. */
2221 if (j == ntok)
2222 return pseudo_insn;
2223 }
6f4b1afc 2224 }
4670103e
CZ		 2225 return NULL;
2226}
252b5132 2227
4670103e 2228/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2229
b9b47ab7 2230static const struct arc_opcode_hash_entry *
4670103e
CZ		 2231find_special_case_pseudo (const char *opname,
2232 int *ntok,
2233 expressionS *tok,
2234 int *nflgs,
2235 struct arc_flags *pflags)
2236{
2237 const struct arc_pseudo_insn *pseudo_insn = NULL;
2238 const struct arc_operand_operation *operand_pseudo;
2239 const struct arc_operand *operand_real;
2240 unsigned i;
2241 char construct_operand[MAX_CONSTR_STR];
886a2506 2242
4670103e
CZ		 2243 /* Find whether opname is in pseudo instruction array. */
2244 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2245
2246 if (pseudo_insn == NULL)
2247 return NULL;
2248
2249 /* Handle flag, Limited to one flag at the moment. */
2250 if (pseudo_insn->flag_r != NULL)
2251 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2252 MAX_INSN_FLGS - *nflgs);
2253
2254 /* Handle operand operations. */
2255 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2256 {
4670103e
CZ		 2257 operand_pseudo = &pseudo_insn->operand[i];
2258 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2259
db18dbab
GM		 2260 if (operand_real->flags & ARC_OPERAND_BRAKET
2261 && !operand_pseudo->needs_insert)
4670103e 2262 continue;
b125bd17 2263
4670103e
CZ		 2264 /* Has to be inserted (i.e. this token does not exist yet). */
2265 if (operand_pseudo->needs_insert)
2266 {
2267 if (operand_real->flags & ARC_OPERAND_BRAKET)
2268 {
2269 tok[i].X_op = O_bracket;
2270 ++(*ntok);
2271 continue;
2272 }
b125bd17 2273
4670103e
CZ		 2274 /* Check if operand is a register or constant and handle it
2275 by type. */
2276 if (operand_real->flags & ARC_OPERAND_IR)
2277 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2278 operand_pseudo->count);
2279 else
2280 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2281 operand_pseudo->count);
886a2506 2282
4670103e
CZ		 2283 tokenize_arguments (construct_operand, &tok[i], 1);
2284 ++(*ntok);
2285 }
2286
2287 else if (operand_pseudo->count)
2288 {
2289 /* Operand number has to be adjusted accordingly (by operand
2290 type). */
2291 switch (tok[i].X_op)
2292 {
2293 case O_constant:
2294 tok[i].X_add_number += operand_pseudo->count;
2295 break;
2296
2297 case O_symbol:
2298 break;
2299
2300 default:
2301 /* Ignored. */
2302 break;
2303 }
2304 }
2305 }
2306
2307 /* Swap operands if necessary. Only supports one swap at the
2308 moment. */
2309 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2310 {
2311 operand_pseudo = &pseudo_insn->operand[i];
2312
2313 if (operand_pseudo->swap_operand_idx == i)
2314 continue;
2315
2316 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2317
2318 /* Prevent a swap back later by breaking out. */
2319 break;
2320 }
2321
da5be039 2322 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2323}
2324
b9b47ab7 2325static const struct arc_opcode_hash_entry *
4670103e
CZ		 2326find_special_case_flag (const char *opname,
2327 int *nflgs,
2328 struct arc_flags *pflags)
2329{
2330 unsigned int i;
2331 const char *flagnm;
2332 unsigned flag_idx, flag_arr_idx;
2333 size_t flaglen, oplen;
2334 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2335 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2336
2337 /* Search for special case instruction. */
2338 for (i = 0; i < arc_num_flag_special; i++)
2339 {
2340 arc_flag_special_opcode = &arc_flag_special_cases[i];
2341 oplen = strlen (arc_flag_special_opcode->name);
2342
2343 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2344 continue;
2345
2346 /* Found a potential special case instruction, now test for
2347 flags. */
2348 for (flag_arr_idx = 0;; ++flag_arr_idx)
2349 {
2350 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2351 if (flag_idx == 0)
2352 break; /* End of array, nothing found. */
886a2506 2353
4670103e
CZ		 2354 flagnm = arc_flag_operands[flag_idx].name;
2355 flaglen = strlen (flagnm);
2356 if (strcmp (opname + oplen, flagnm) == 0)
2357 {
b9b47ab7 2358 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2359
4670103e
CZ		 2360 if (*nflgs + 1 > MAX_INSN_FLGS)
2361 break;
2362 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2363 pflags[*nflgs].name[flaglen] = '\0';
2364 (*nflgs)++;
b9b47ab7 2365 return entry;
4670103e
CZ		 2366 }
2367 }
2368 }
2369 return NULL;
2370}
886a2506 2371
4670103e 2372/* Used to find special case opcode. */
886a2506 2373
b9b47ab7 2374static const struct arc_opcode_hash_entry *
4670103e
CZ		 2375find_special_case (const char *opname,
2376 int *nflgs,
2377 struct arc_flags *pflags,
2378 expressionS *tok,
2379 int *ntok)
2380{
b9b47ab7 2381 const struct arc_opcode_hash_entry *entry;
886a2506 2382
b9b47ab7 2383 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2384
b9b47ab7
AB		 2385 if (entry == NULL)
2386 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2387
b9b47ab7 2388 return entry;
4670103e 2389}
886a2506 2390
53a346d8
CZ		 2391/* Autodetect cpu attribute list. */
2392
2393static void
2394autodetect_attributes (const struct arc_opcode *opcode,
2395 const expressionS *tok,
2396 int ntok)
2397{
2398 unsigned i;
2399 struct mpy_type
2400 {
2401 unsigned feature;
2402 unsigned encoding;
2403 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2404 { MPY9E, 9 }};
2405
2406 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2407 if (opcode->subclass == feature_list[i].feature)
2408 selected_cpu.features |= feature_list[i].feature;
2409
2410 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2411 if (opcode->subclass == mpy_list[i].feature)
2412 mpy_option = mpy_list[i].encoding;
2413
2414 for (i = 0; i < (unsigned) ntok; i++)
2415 {
2416 switch (tok[i].X_md)
2417 {
2418 case O_gotoff:
2419 case O_gotpc:
2420 case O_plt:
2421 pic_option = 2;
2422 break;
2423 case O_sda:
2424 sda_option = 2;
2425 break;
2426 case O_tlsgd:
2427 case O_tlsie:
2428 case O_tpoff9:
2429 case O_tpoff:
2430 case O_dtpoff9:
2431 case O_dtpoff:
2432 tls_option = 1;
2433 break;
2434 default:
2435 break;
2436 }
63741043 2437
2438 switch (tok[i].X_op)
2439 {
2440 case O_register:
2441 if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
2442 || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
5b7c81bd 2443 rf16_only = false;
63741043 2444 break;
2445 default:
2446 break;
2447 }
53a346d8
CZ		 2448 }
2449}
2450
2451/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2452 opcode flags, take it all the way through emission. */
886a2506 2453
4670103e
CZ		 2454static void
2455assemble_tokens (const char *opname,
2456 expressionS *tok,
2457 int ntok,
2458 struct arc_flags *pflags,
2459 int nflgs)
2460{
5b7c81bd 2461 bool found_something = false;
b9b47ab7 2462 const struct arc_opcode_hash_entry *entry;
4670103e 2463 int cpumatch = 1;
abe7c33b 2464 const char *errmsg = NULL;
886a2506 2465
4670103e 2466 /* Search opcodes. */
b9b47ab7 2467 entry = arc_find_opcode (opname);
886a2506 2468
4670103e 2469 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2470 if (entry == NULL)
2471 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2472
b9b47ab7 2473 if (entry != NULL)
4670103e 2474 {
b9b47ab7
AB		 2475 const struct arc_opcode *opcode;
2476
1328504b
AB		 2477 pr_debug ("%s:%d: assemble_tokens: %s\n",
2478 frag_now->fr_file, frag_now->fr_line, opname);
5b7c81bd 2479 found_something = true;
b9b47ab7 2480 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2481 nflgs, &cpumatch, &errmsg);
b9b47ab7 2482 if (opcode != NULL)
4670103e
CZ		 2483 {
2484 struct arc_insn insn;
b9b47ab7 2485
53a346d8 2486 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2487 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2488 emit_insn (&insn);
2489 return;
2490 }
2491 }
886a2506 2492
4670103e
CZ		 2493 if (found_something)
2494 {
2495 if (cpumatch)
abe7c33b
CZ		 2496 if (errmsg)
2497 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2498 else
2499 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2500 else
2501 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2502 selected_cpu.name);
4670103e
CZ		 2503 }
2504 else
2505 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2506}
2507
4670103e 2508/* The public interface to the instruction assembler. */
886a2506 2509
4670103e
CZ		 2510void
2511md_assemble (char *str)
886a2506 2512{
4670103e
CZ		 2513 char *opname;
2514 expressionS tok[MAX_INSN_ARGS];
2515 int ntok, nflg;
2516 size_t opnamelen;
2517 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2518
4670103e 2519 /* Split off the opcode. */
51542162 2520 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123456789");
29a2809e 2521 opname = xmemdup0 (str, opnamelen);
886a2506 2522
33eaf5de 2523 /* Signalize we are assembling the instructions. */
5b7c81bd 2524 assembling_insn = true;
886a2506 2525
4670103e
CZ		 2526 /* Tokenize the flags. */
2527 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2528 {
2529 as_bad (_("syntax error"));
2530 return;
2531 }
886a2506 2532
4670103e
CZ		 2533 /* Scan up to the end of the mnemonic which must end in space or end
2534 of string. */
2535 str += opnamelen;
2536 for (; *str != '\0'; str++)
2537 if (*str == ' ')
2538 break;
886a2506 2539
4670103e
CZ		 2540 /* Tokenize the rest of the line. */
2541 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2542 {
4670103e
CZ		 2543 as_bad (_("syntax error"));
2544 return;
252b5132
RH		 2545 }
2546
4670103e
CZ		 2547 /* Finish it off. */
2548 assemble_tokens (opname, tok, ntok, flags, nflg);
5b7c81bd 2549 assembling_insn = false;
4670103e
CZ		 2550}
2551
2552/* Callback to insert a register into the hash table. */
2553
2554static void
f86f5863 2555declare_register (const char *name, int number)
4670103e 2556{
4670103e 2557 symbolS *regS = symbol_create (name, reg_section,
e01e1cee 2558 &zero_address_frag, number);
4670103e 2559
fe0e921f
AM		 2560 if (str_hash_insert (arc_reg_hash, S_GET_NAME (regS), regS, 0) != NULL)
2561 as_fatal (_("duplicate %s"), name);
4670103e 2562}
252b5132 2563
4670103e 2564/* Construct symbols for each of the general registers. */
252b5132 2565
4670103e
CZ		 2566static void
2567declare_register_set (void)
2568{
2569 int i;
2570 for (i = 0; i < 64; ++i)
886a2506 2571 {
ca159256 2572 char name[32];
4670103e
CZ		 2573
2574 sprintf (name, "r%d", i);
2575 declare_register (name, i);
2576 if ((i & 0x01) == 0)
886a2506 2577 {
4670103e
CZ		 2578 sprintf (name, "r%dr%d", i, i+1);
2579 declare_register (name, i);
886a2506
NC		 2580 }
2581 }
252b5132 2582}
ea1562b3 2583
db18dbab
GM		 2584/* Construct a symbol for an address type. */
2585
2586static void
2587declare_addrtype (const char *name, int number)
2588{
db18dbab 2589 symbolS *addrtypeS = symbol_create (name, undefined_section,
e01e1cee 2590 &zero_address_frag, number);
db18dbab 2591
fe0e921f
AM		 2592 if (str_hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS), addrtypeS, 0))
2593 as_fatal (_("duplicate %s"), name);
db18dbab
GM		 2594}
2595
4670103e
CZ		 2596/* Port-specific assembler initialization. This function is called
2597 once, at assembler startup time. */
ea1562b3
NC		 2598
2599void
4670103e 2600md_begin (void)
ea1562b3 2601{
b99747ae 2602 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2603
bb65a718
AB		 2604 if (mach_selection_mode == MACH_SELECTION_NONE)
2605 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2606
4670103e
CZ		 2607 /* The endianness can be chosen "at the factory". */
2608 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2609
bb65a718 2610 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2611 as_warn (_("could not set architecture and machine"));
2612
2613 /* Set elf header flags. */
bb65a718 2614 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2615
2616 /* Set up a hash table for the instructions. */
a51628a9
AM		 2617 arc_opcode_hash = htab_create_alloc (16, hash_string_tuple, eq_string_tuple,
2618 arc_opcode_free, xcalloc, free);
4670103e
CZ		 2619
2620 /* Initialize the hash table with the insns. */
b99747ae 2621 do
ea1562b3 2622 {
b99747ae 2623 const char *name = opcode->name;
da5be039 2624
b99747ae 2625 arc_insert_opcode (opcode);
4670103e 2626
b99747ae
CZ		 2627 while (++opcode && opcode->name
2628 && (opcode->name == name
2629 || !strcmp (opcode->name, name)))
4670103e 2630 continue;
b99747ae 2631 }while (opcode->name);
4670103e
CZ		 2632
2633 /* Register declaration. */
629310ab 2634 arc_reg_hash = str_htab_create ();
4670103e
CZ		 2635
2636 declare_register_set ();
2637 declare_register ("gp", 26);
2638 declare_register ("fp", 27);
2639 declare_register ("sp", 28);
2640 declare_register ("ilink", 29);
2641 declare_register ("ilink1", 29);
2642 declare_register ("ilink2", 30);
2643 declare_register ("blink", 31);
2644
87789e08
CZ		 2645 /* XY memory registers. */
2646 declare_register ("x0_u0", 32);
2647 declare_register ("x0_u1", 33);
2648 declare_register ("x1_u0", 34);
2649 declare_register ("x1_u1", 35);
2650 declare_register ("x2_u0", 36);
2651 declare_register ("x2_u1", 37);
2652 declare_register ("x3_u0", 38);
2653 declare_register ("x3_u1", 39);
2654 declare_register ("y0_u0", 40);
2655 declare_register ("y0_u1", 41);
2656 declare_register ("y1_u0", 42);
2657 declare_register ("y1_u1", 43);
2658 declare_register ("y2_u0", 44);
2659 declare_register ("y2_u1", 45);
2660 declare_register ("y3_u0", 46);
2661 declare_register ("y3_u1", 47);
2662 declare_register ("x0_nu", 48);
2663 declare_register ("x1_nu", 49);
2664 declare_register ("x2_nu", 50);
2665 declare_register ("x3_nu", 51);
2666 declare_register ("y0_nu", 52);
2667 declare_register ("y1_nu", 53);
2668 declare_register ("y2_nu", 54);
2669 declare_register ("y3_nu", 55);
2670
4670103e
CZ		 2671 declare_register ("mlo", 57);
2672 declare_register ("mmid", 58);
2673 declare_register ("mhi", 59);
2674
2675 declare_register ("acc1", 56);
2676 declare_register ("acc2", 57);
2677
2678 declare_register ("lp_count", 60);
2679 declare_register ("pcl", 63);
2680
2681 /* Initialize the last instructions. */
2682 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2683
2684 /* Aux register declaration. */
629310ab 2685 arc_aux_hash = str_htab_create ();
f36e33da
CZ		 2686
2687 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2688 unsigned int i;
2689 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2690 {
bb65a718 2691 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2692 continue;
2693
2694 if ((auxr->subclass != NONE)
2695 && !check_cpu_feature (auxr->subclass))
2696 continue;
2697
fe0e921f
AM		 2698 if (str_hash_insert (arc_aux_hash, auxr->name, auxr, 0) != 0)
2699 as_fatal (_("duplicate %s"), auxr->name);
f36e33da 2700 }
db18dbab
GM		 2701
2702 /* Address type declaration. */
629310ab 2703 arc_addrtype_hash = str_htab_create ();
db18dbab
GM		 2704
2705 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2706 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2707 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2708 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2709 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2710 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2711 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2712 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2713 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2714 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2715 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2716 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2717 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2718 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2719 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2720 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2721}
ea1562b3 2722
a51628a9
AM		 2723void
2724arc_md_end (void)
2725{
2726 htab_delete (arc_opcode_hash);
2727 htab_delete (arc_reg_hash);
2728 htab_delete (arc_aux_hash);
2729 htab_delete (arc_addrtype_hash);
2730}
2731
4670103e
CZ		 2732/* Write a value out to the object file, using the appropriate
2733 endianness. */
ea1562b3 2734
4670103e
CZ		 2735void
2736md_number_to_chars (char *buf,
2737 valueT val,
2738 int n)
886a2506 2739{
4670103e
CZ		 2740 if (target_big_endian)
2741 number_to_chars_bigendian (buf, val, n);
2742 else
2743 number_to_chars_littleendian (buf, val, n);
886a2506 2744}
ea1562b3 2745
4670103e 2746/* Round up a section size to the appropriate boundary. */
ea1562b3 2747
4670103e
CZ		 2748valueT
2749md_section_align (segT segment,
2750 valueT size)
886a2506 2751{
fd361982 2752 int align = bfd_section_alignment (segment);
4670103e
CZ		 2753
2754 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2755}
ea1562b3 2756
4670103e
CZ		 2757/* The location from which a PC relative jump should be calculated,
2758 given a PC relative reloc. */
ea1562b3 2759
4670103e
CZ		 2760long
2761md_pcrel_from_section (fixS *fixP,
2762 segT sec)
886a2506 2763{
4670103e 2764 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2765
4670103e 2766 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2767
4670103e
CZ		 2768 if (fixP->fx_addsy != (symbolS *) NULL
2769 && (!S_IS_DEFINED (fixP->fx_addsy)
2770 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2771 {
2772 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2773
4670103e
CZ		 2774 /* The symbol is undefined (or is defined but not in this section).
2775 Let the linker figure it out. */
2776 return 0;
2777 }
2778
2779 if ((int) fixP->fx_r_type < 0)
886a2506 2780 {
4670103e
CZ		 2781 /* These are the "internal" relocations. Align them to
2782 32 bit boundary (PCL), for the moment. */
2783 base &= ~3;
886a2506 2784 }
4670103e
CZ		 2785 else
2786 {
2787 switch (fixP->fx_r_type)
2788 {
2789 case BFD_RELOC_ARC_PC32:
2790 /* The hardware calculates relative to the start of the
2791 insn, but this relocation is relative to location of the
2792 LIMM, compensate. The base always needs to be
2b0f3761 2793 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2794 relocation for short instructions. */
2795 base -= 4;
2796 /* Fall through. */
2797 case BFD_RELOC_ARC_PLT32:
2798 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2799 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2800 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2801 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2802
2803 case BFD_RELOC_ARC_S21H_PCREL:
2804 case BFD_RELOC_ARC_S25H_PCREL:
2805 case BFD_RELOC_ARC_S13_PCREL:
2806 case BFD_RELOC_ARC_S21W_PCREL:
2807 case BFD_RELOC_ARC_S25W_PCREL:
2808 base &= ~3;
2809 break;
2810 default:
2811 as_bad_where (fixP->fx_file, fixP->fx_line,
2812 _("unhandled reloc %s in md_pcrel_from_section"),
2813 bfd_get_reloc_code_name (fixP->fx_r_type));
2814 break;
2815 }
2816 }
2817
9e32d9ae
AB		 2818 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2819 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2820 fixP->fx_frag->fr_address, fixP->fx_where, base,
2821 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2822 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2823
2824 return base;
886a2506 2825}
ea1562b3 2826
33eaf5de 2827/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2828
4670103e
CZ		 2829static const struct arc_operand *
2830find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2831{
2832 unsigned i;
ea1562b3 2833
4670103e
CZ		 2834 for (i = 0; i < arc_num_operands; i++)
2835 if (arc_operands[i].default_reloc == reloc)
2836 return &arc_operands[i];
2837 return NULL;
2838}
ea1562b3 2839
4670103e 2840/* Insert an operand value into an instruction. */
ea1562b3 2841
bdfe53e3
AB		 2842static unsigned long long
2843insert_operand (unsigned long long insn,
4670103e 2844 const struct arc_operand *operand,
bdfe53e3 2845 long long val,
3b4dbbbf 2846 const char *file,
4670103e 2847 unsigned line)
886a2506 2848{
4670103e 2849 offsetT min = 0, max = 0;
ea1562b3 2850
4670103e
CZ		 2851 if (operand->bits != 32
2852 && !(operand->flags & ARC_OPERAND_NCHK)
2853 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2854 {
4670103e
CZ		 2855 if (operand->flags & ARC_OPERAND_SIGNED)
2856 {
2857 max = (1 << (operand->bits - 1)) - 1;
2858 min = -(1 << (operand->bits - 1));
2859 }
2860 else
2861 {
2862 max = (1 << operand->bits) - 1;
2863 min = 0;
2864 }
886a2506 2865
4670103e
CZ		 2866 if (val < min || val > max)
2867 as_bad_value_out_of_range (_("operand"),
2868 val, min, max, file, line);
2869 }
ea1562b3 2870
cc07cda6 2871 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2872 min, val, max, insn);
ea1562b3 2873
4670103e
CZ		 2874 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2875 && (val & 0x03))
2876 as_bad_where (file, line,
2877 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2878
4670103e
CZ		 2879 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2880 && (val & 0x01))
2881 as_bad_where (file, line,
2882 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2883
4670103e
CZ		 2884 if (operand->insert)
2885 {
2886 const char *errmsg = NULL;
ea1562b3 2887
4670103e
CZ		 2888 insn = (*operand->insert) (insn, val, &errmsg);
2889 if (errmsg)
2890 as_warn_where (file, line, "%s", errmsg);
2891 }
2892 else
2893 {
2894 if (operand->flags & ARC_OPERAND_TRUNCATE)
2895 {
2896 if (operand->flags & ARC_OPERAND_ALIGNED32)
2897 val >>= 2;
2898 if (operand->flags & ARC_OPERAND_ALIGNED16)
2899 val >>= 1;
886a2506 2900 }
4670103e
CZ		 2901 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2902 }
2903 return insn;
2904}
ea1562b3 2905
4670103e
CZ		 2906/* Apply a fixup to the object code. At this point all symbol values
2907 should be fully resolved, and we attempt to completely resolve the
2908 reloc. If we can not do that, we determine the correct reloc code
2909 and put it back in the fixup. To indicate that a fixup has been
2910 eliminated, set fixP->fx_done. */
ea1562b3 2911
4670103e
CZ		 2912void
2913md_apply_fix (fixS *fixP,
2914 valueT *valP,
2915 segT seg)
2916{
2917 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2918 valueT value = *valP;
2919 unsigned insn = 0;
2920 symbolS *fx_addsy, *fx_subsy;
2921 offsetT fx_offset;
2922 segT add_symbol_segment = absolute_section;
2923 segT sub_symbol_segment = absolute_section;
2924 const struct arc_operand *operand = NULL;
2925 extended_bfd_reloc_code_real_type reloc;
886a2506 2926
4670103e
CZ		 2927 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2928 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2929 ((int) fixP->fx_r_type < 0) ? "Internal":
2930 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2931 fixP->fx_offset);
886a2506 2932
4670103e
CZ		 2933 fx_addsy = fixP->fx_addsy;
2934 fx_subsy = fixP->fx_subsy;
2935 fx_offset = 0;
886a2506 2936
4670103e
CZ		 2937 if (fx_addsy)
2938 {
2939 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2940 }
2941
4670103e
CZ		 2942 if (fx_subsy
2943 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2944 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2945 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2946 {
2947 resolve_symbol_value (fx_subsy);
2948 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2949
4670103e
CZ		 2950 if (sub_symbol_segment == absolute_section)
2951 {
2952 /* The symbol is really a constant. */
2953 fx_offset -= S_GET_VALUE (fx_subsy);
2954 fx_subsy = NULL;
2955 }
2956 else
2957 {
4bf09429 2958 as_bad_subtract (fixP);
4670103e
CZ		 2959 return;
2960 }
2961 }
886a2506 2962
4670103e
CZ		 2963 if (fx_addsy
2964 && !S_IS_WEAK (fx_addsy))
2965 {
2966 if (add_symbol_segment == seg
2967 && fixP->fx_pcrel)
2968 {
2969 value += S_GET_VALUE (fx_addsy);
2970 value -= md_pcrel_from_section (fixP, seg);
2971 fx_addsy = NULL;
5b7c81bd 2972 fixP->fx_pcrel = false;
4670103e
CZ		 2973 }
2974 else if (add_symbol_segment == absolute_section)
2975 {
2976 value = fixP->fx_offset;
2977 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2978 fx_addsy = NULL;
5b7c81bd 2979 fixP->fx_pcrel = false;
4670103e
CZ		 2980 }
2981 }
886a2506 2982
4670103e 2983 if (!fx_addsy)
5b7c81bd 2984 fixP->fx_done = true;
886a2506 2985
4670103e 2986 if (fixP->fx_pcrel)
886a2506 2987 {
4670103e
CZ		 2988 if (fx_addsy
2989 && ((S_IS_DEFINED (fx_addsy)
2990 && S_GET_SEGMENT (fx_addsy) != seg)
2991 || S_IS_WEAK (fx_addsy)))
2992 value += md_pcrel_from_section (fixP, seg);
886a2506 2993
4670103e
CZ		 2994 switch (fixP->fx_r_type)
2995 {
2996 case BFD_RELOC_ARC_32_ME:
2997 /* This is a pc-relative value in a LIMM. Adjust it to the
2998 address of the instruction not to the address of the
33eaf5de 2999 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 3000 the linker consider ARC_PC32 a fixup to entire 64 bit
3001 insn. */
3002 fixP->fx_offset += fixP->fx_frag->fr_address;
3003 /* Fall through. */
3004 case BFD_RELOC_32:
3005 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
3006 /* Fall through. */
3007 case BFD_RELOC_ARC_PC32:
3008 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 3009 break;
3010 default:
4670103e 3011 if ((int) fixP->fx_r_type < 0)
6e3f3473 3012 as_bad_where (fixP->fx_file, fixP->fx_line,
3013 _("PC relative relocation not allowed for (internal)"
3014 " type %d"),
3015 fixP->fx_r_type);
886a2506 3016 break;
ea1562b3
NC		 3017 }
3018 }
3019
4670103e
CZ		 3020 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
3021 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
3022 ((int) fixP->fx_r_type < 0) ? "Internal":
3023 bfd_get_reloc_code_name (fixP->fx_r_type), value,
3024 fixP->fx_offset);
886a2506 3025
886a2506 3026
4670103e
CZ		 3027 /* Now check for TLS relocations. */
3028 reloc = fixP->fx_r_type;
3029 switch (reloc)
886a2506 3030 {
4670103e
CZ		 3031 case BFD_RELOC_ARC_TLS_DTPOFF:
3032 case BFD_RELOC_ARC_TLS_LE_32:
3033 if (fixP->fx_done)
3034 break;
3035 /* Fall through. */
3036 case BFD_RELOC_ARC_TLS_GD_GOT:
3037 case BFD_RELOC_ARC_TLS_IE_GOT:
3038 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3039 break;
886a2506 3040
4670103e
CZ		 3041 case BFD_RELOC_ARC_TLS_GD_LD:
3042 gas_assert (!fixP->fx_offset);
3043 if (fixP->fx_subsy)
3044 fixP->fx_offset
3045 = (S_GET_VALUE (fixP->fx_subsy)
3046 - fixP->fx_frag->fr_address- fixP->fx_where);
3047 fixP->fx_subsy = NULL;
3048 /* Fall through. */
3049 case BFD_RELOC_ARC_TLS_GD_CALL:
3050 /* These two relocs are there just to allow ld to change the tls
3051 model for this symbol, by patching the code. The offset -
3052 and scale, if any - will be installed by the linker. */
3053 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3054 break;
886a2506 3055
4670103e
CZ		 3056 case BFD_RELOC_ARC_TLS_LE_S9:
3057 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3058 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3059 break;
3060
3061 default:
3062 break;
886a2506
NC		 3063 }
3064
4670103e 3065 if (!fixP->fx_done)
886a2506 3066 {
4670103e 3067 return;
886a2506 3068 }
886a2506 3069
33eaf5de 3070 /* Adjust the value if we have a constant. */
4670103e 3071 value += fx_offset;
886a2506 3072
4670103e
CZ		 3073 /* For hosts with longs bigger than 32-bits make sure that the top
3074 bits of a 32-bit negative value read in by the parser are set,
3075 so that the correct comparisons are made. */
3076 if (value & 0x80000000)
69c9e028 3077 value |= (-1UL << 31);
886a2506 3078
4670103e
CZ		 3079 reloc = fixP->fx_r_type;
3080 switch (reloc)
3081 {
3082 case BFD_RELOC_8:
3083 case BFD_RELOC_16:
3084 case BFD_RELOC_24:
3085 case BFD_RELOC_32:
3086 case BFD_RELOC_64:
3087 case BFD_RELOC_ARC_32_PCREL:
3088 md_number_to_chars (fixpos, value, fixP->fx_size);
3089 return;
886a2506 3090
4670103e
CZ		 3091 case BFD_RELOC_ARC_GOTPC32:
3092 /* I cannot fix an GOTPC relocation because I need to relax it
3093 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3094 as_bad (_("Unsupported operation on reloc"));
3095 return;
886a2506 3096
4670103e
CZ		 3097 case BFD_RELOC_ARC_TLS_DTPOFF:
3098 case BFD_RELOC_ARC_TLS_LE_32:
3099 gas_assert (!fixP->fx_addsy);
3100 gas_assert (!fixP->fx_subsy);
1a0670f3 3101 /* Fall through. */
886a2506 3102
4670103e
CZ		 3103 case BFD_RELOC_ARC_GOTOFF:
3104 case BFD_RELOC_ARC_32_ME:
3105 case BFD_RELOC_ARC_PC32:
3106 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3107 return;
886a2506 3108
4670103e
CZ		 3109 case BFD_RELOC_ARC_PLT32:
3110 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3111 return;
886a2506 3112
4670103e
CZ		 3113 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3114 reloc = BFD_RELOC_ARC_S25W_PCREL;
3115 goto solve_plt;
886a2506 3116
4670103e
CZ		 3117 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3118 reloc = BFD_RELOC_ARC_S21H_PCREL;
3119 goto solve_plt;
886a2506 3120
4670103e
CZ		 3121 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3122 reloc = BFD_RELOC_ARC_S25W_PCREL;
3123 goto solve_plt;
886a2506 3124
4670103e
CZ		 3125 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3126 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3127 /* Fall through. */
886a2506 3128
4670103e
CZ		 3129 case BFD_RELOC_ARC_S25W_PCREL:
3130 case BFD_RELOC_ARC_S21W_PCREL:
3131 case BFD_RELOC_ARC_S21H_PCREL:
3132 case BFD_RELOC_ARC_S25H_PCREL:
3133 case BFD_RELOC_ARC_S13_PCREL:
3134 solve_plt:
3135 operand = find_operand_for_reloc (reloc);
3136 gas_assert (operand);
886a2506
NC		 3137 break;
3138
3139 default:
4670103e
CZ		 3140 {
3141 if ((int) fixP->fx_r_type >= 0)
3142 as_fatal (_("unhandled relocation type %s"),
3143 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3144
4670103e
CZ		 3145 /* The rest of these fixups needs to be completely resolved as
3146 constants. */
3147 if (fixP->fx_addsy != 0
3148 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3149 as_bad_where (fixP->fx_file, fixP->fx_line,
3150 _("non-absolute expression in constant field"));
886a2506 3151
4670103e
CZ		 3152 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3153 operand = &arc_operands[-(int) fixP->fx_r_type];
3154 break;
3155 }
3156 }
886a2506 3157
4670103e 3158 if (target_big_endian)
886a2506 3159 {
4670103e 3160 switch (fixP->fx_size)
886a2506 3161 {
4670103e
CZ		 3162 case 4:
3163 insn = bfd_getb32 (fixpos);
3164 break;
3165 case 2:
3166 insn = bfd_getb16 (fixpos);
3167 break;
3168 default:
3169 as_bad_where (fixP->fx_file, fixP->fx_line,
3170 _("unknown fixup size"));
3171 }
3172 }
3173 else
3174 {
3175 insn = 0;
3176 switch (fixP->fx_size)
3177 {
3178 case 4:
3179 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3180 break;
3181 case 2:
3182 insn = bfd_getl16 (fixpos);
3183 break;
3184 default:
3185 as_bad_where (fixP->fx_file, fixP->fx_line,
3186 _("unknown fixup size"));
886a2506
NC		 3187 }
3188 }
886a2506 3189
4670103e
CZ		 3190 insn = insert_operand (insn, operand, (offsetT) value,
3191 fixP->fx_file, fixP->fx_line);
886a2506 3192
4670103e
CZ		 3193 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3194}
886a2506 3195
4670103e 3196/* Prepare machine-dependent frags for relaxation.
886a2506 3197
4670103e
CZ		 3198 Called just before relaxation starts. Any symbol that is now undefined
3199 will not become defined.
886a2506 3200
4670103e 3201 Return the correct fr_subtype in the frag.
886a2506 3202
4670103e
CZ		 3203 Return the initial "guess for fr_var" to caller. The guess for fr_var
3204 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3205 or fr_var contributes to our returned value.
886a2506 3206
4670103e
CZ		 3207 Although it may not be explicit in the frag, pretend
3208 fr_var starts with a value. */
886a2506 3209
4670103e
CZ		 3210int
3211md_estimate_size_before_relax (fragS *fragP,
3212 segT segment)
3213{
3214 int growth;
3215
3216 /* If the symbol is not located within the same section AND it's not
3217 an absolute section, use the maximum. OR if the symbol is a
3218 constant AND the insn is by nature not pc-rel, use the maximum.
3219 OR if the symbol is being equated against another symbol, use the
3220 maximum. OR if the symbol is weak use the maximum. */
3221 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3222 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3223 || (symbol_constant_p (fragP->fr_symbol)
3224 && !fragP->tc_frag_data.pcrel)
3225 || symbol_equated_p (fragP->fr_symbol)
3226 || S_IS_WEAK (fragP->fr_symbol))
3227 {
3228 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3229 ++fragP->fr_subtype;
3230 }
886a2506 3231
4670103e
CZ		 3232 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3233 fragP->fr_var = growth;
886a2506 3234
4670103e
CZ		 3235 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3236 fragP->fr_file, fragP->fr_line, growth);
886a2506 3237
4670103e
CZ		 3238 return growth;
3239}
886a2506 3240
4670103e
CZ		 3241/* Translate internal representation of relocation info to BFD target
3242 format. */
886a2506 3243
4670103e
CZ		 3244arelent *
3245tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3246 fixS *fixP)
3247{
3248 arelent *reloc;
3249 bfd_reloc_code_real_type code;
886a2506 3250
add39d23
TS		 3251 reloc = XNEW (arelent);
3252 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3253 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3254 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3255
4670103e
CZ		 3256 /* Make sure none of our internal relocations make it this far.
3257 They'd better have been fully resolved by this point. */
3258 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3259
4670103e 3260 code = fixP->fx_r_type;
886a2506 3261
4670103e
CZ		 3262 /* if we have something like add gp, pcl,
3263 _GLOBAL_OFFSET_TABLE_@gotpc. */
3264 if (code == BFD_RELOC_ARC_GOTPC32
3265 && GOT_symbol
3266 && fixP->fx_addsy == GOT_symbol)
3267 code = BFD_RELOC_ARC_GOTPC;
886a2506 3268
4670103e
CZ		 3269 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3270 if (reloc->howto == NULL)
886a2506 3271 {
4670103e
CZ		 3272 as_bad_where (fixP->fx_file, fixP->fx_line,
3273 _("cannot represent `%s' relocation in object file"),
3274 bfd_get_reloc_code_name (code));
3275 return NULL;
3276 }
886a2506 3277
4670103e
CZ		 3278 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3279 as_fatal (_("internal error? cannot generate `%s' relocation"),
3280 bfd_get_reloc_code_name (code));
886a2506 3281
4670103e 3282 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3283
05bbf016 3284 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3285
3286 return reloc;
886a2506
NC		 3287}
3288
4670103e
CZ		 3289/* Perform post-processing of machine-dependent frags after relaxation.
3290 Called after relaxation is finished.
3291 In: Address of frag.
3292 fr_type == rs_machine_dependent.
3293 fr_subtype is what the address relaxed to.
886a2506 3294
4670103e
CZ		 3295 Out: Any fixS:s and constants are set up. */
3296
3297void
3298md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3299 segT segment ATTRIBUTE_UNUSED,
3300 fragS *fragP)
886a2506 3301{
4670103e
CZ		 3302 const relax_typeS *table_entry;
3303 char *dest;
3304 const struct arc_opcode *opcode;
3305 struct arc_insn insn;
3306 int size, fix;
3307 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3308
871a6bd2 3309 fix = fragP->fr_fix;
4670103e
CZ		 3310 dest = fragP->fr_literal + fix;
3311 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3312
9e32d9ae
AB		 3313 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3314 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3315 fragP->fr_file, fragP->fr_line,
3316 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3317
4670103e
CZ		 3318 if (fragP->fr_subtype <= 0
3319 && fragP->fr_subtype >= arc_num_relax_opcodes)
3320 as_fatal (_("no relaxation found for this instruction."));
886a2506 3321
4670103e 3322 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3323
4670103e
CZ		 3324 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3325 relax_arg->nflg, &insn);
886a2506 3326
4670103e 3327 apply_fixups (&insn, fragP, fix);
886a2506 3328
91fdca6f 3329 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e 3330 gas_assert (table_entry->rlx_length == size);
5b7c81bd 3331 emit_insn0 (&insn, dest, true);
886a2506 3332
4670103e
CZ		 3333 fragP->fr_fix += table_entry->rlx_length;
3334 fragP->fr_var = 0;
886a2506
NC		 3335}
3336
4670103e
CZ		 3337/* We have no need to default values of symbols. We could catch
3338 register names here, but that is handled by inserting them all in
3339 the symbol table to begin with. */
886a2506 3340
4670103e
CZ		 3341symbolS *
3342md_undefined_symbol (char *name)
886a2506 3343{
4670103e
CZ		 3344 /* The arc abi demands that a GOT[0] should be referencible as
3345 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3346 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3347 if (((*name == '_')
3348 && (*(name+1) == 'G')
7ef0acc1 3349 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
886a2506 3350 {
4670103e
CZ		 3351 if (!GOT_symbol)
3352 {
3353 if (symbol_find (name))
3354 as_bad ("GOT already in symbol table");
3355
3356 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
e01e1cee 3357 &zero_address_frag, 0);
4670103e
CZ		 3358 };
3359 return GOT_symbol;
886a2506 3360 }
4670103e 3361 return NULL;
886a2506
NC		 3362}
3363
4670103e
CZ		 3364/* Turn a string in input_line_pointer into a floating point constant
3365 of type type, and store the appropriate bytes in *litP. The number
3366 of LITTLENUMS emitted is stored in *sizeP. An error message is
3367 returned, or NULL on OK. */
886a2506 3368
6d4af3c2 3369const char *
4670103e 3370md_atof (int type, char *litP, int *sizeP)
886a2506 3371{
4670103e
CZ		 3372 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3373}
886a2506 3374
4670103e
CZ		 3375/* Called for any expression that can not be recognized. When the
3376 function is called, `input_line_pointer' will point to the start of
2a1ebfb2
CZ		 3377 the expression. We use it when we have complex operations like
3378 @label1 - @label2. */
886a2506 3379
4670103e 3380void
2a1ebfb2 3381md_operand (expressionS *expressionP)
4670103e
CZ		 3382{
3383 char *p = input_line_pointer;
3384 if (*p == '@')
886a2506 3385 {
4670103e
CZ		 3386 input_line_pointer++;
3387 expressionP->X_op = O_symbol;
2a1ebfb2 3388 expressionP->X_md = O_absent;
4670103e
CZ		 3389 expression (expressionP);
3390 }
3391}
886a2506 3392
4670103e
CZ		 3393/* This function is called from the function 'expression', it attempts
3394 to parse special names (in our case register names). It fills in
3395 the expression with the identified register. It returns TRUE if
3396 it is a register and FALSE otherwise. */
886a2506 3397
5b7c81bd 3398bool
4670103e
CZ		 3399arc_parse_name (const char *name,
3400 struct expressionS *e)
3401{
3402 struct symbol *sym;
886a2506 3403
4670103e 3404 if (!assembling_insn)
5b7c81bd 3405 return false;
886a2506 3406
2a1ebfb2
CZ		 3407 if (e->X_op == O_symbol
3408 && e->X_md == O_absent)
5b7c81bd 3409 return false;
886a2506 3410
629310ab 3411 sym = str_hash_find (arc_reg_hash, name);
4670103e
CZ		 3412 if (sym)
3413 {
3414 e->X_op = O_register;
3415 e->X_add_number = S_GET_VALUE (sym);
5b7c81bd 3416 return true;
4670103e 3417 }
db18dbab 3418
629310ab 3419 sym = str_hash_find (arc_addrtype_hash, name);
db18dbab
GM		 3420 if (sym)
3421 {
3422 e->X_op = O_addrtype;
3423 e->X_add_number = S_GET_VALUE (sym);
5b7c81bd 3424 return true;
db18dbab
GM		 3425 }
3426
5b7c81bd 3427 return false;
4670103e 3428}
886a2506 3429
4670103e
CZ		 3430/* md_parse_option
3431 Invocation line includes a switch not recognized by the base assembler.
3432 See if it's a processor-specific option.
886a2506 3433
4670103e 3434 New options (supported) are:
886a2506 3435
4670103e
CZ		 3436 -mcpu=<cpu name> Assemble for selected processor
3437 -EB/-mbig-endian Big-endian
3438 -EL/-mlittle-endian Little-endian
3439 -mrelax Enable relaxation
886a2506 3440
4670103e 3441 The following CPU names are recognized:
ce440d63 3442 arc600, arc700, arcem, archs, nps400. */
886a2506 3443
4670103e 3444int
17b9d67d 3445md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3446{
4670103e
CZ		 3447 switch (c)
3448 {
3449 case OPTION_ARC600:
3450 case OPTION_ARC601:
3451 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3452
4670103e
CZ		 3453 case OPTION_ARC700:
3454 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3455
4670103e
CZ		 3456 case OPTION_ARCEM:
3457 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3458
4670103e
CZ		 3459 case OPTION_ARCHS:
3460 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3461
4670103e
CZ		 3462 case OPTION_MCPU:
3463 {
bb65a718 3464 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3465 break;
3466 }
886a2506 3467
4670103e
CZ		 3468 case OPTION_EB:
3469 arc_target_format = "elf32-bigarc";
3470 byte_order = BIG_ENDIAN;
3471 break;
886a2506 3472
4670103e
CZ		 3473 case OPTION_EL:
3474 arc_target_format = "elf32-littlearc";
3475 byte_order = LITTLE_ENDIAN;
3476 break;
886a2506 3477
4670103e 3478 case OPTION_CD:
53a346d8
CZ		 3479 selected_cpu.features |= CD;
3480 cl_features |= CD;
bb050a69 3481 arc_check_feature ();
4670103e 3482 break;
886a2506 3483
4670103e
CZ		 3484 case OPTION_RELAX:
3485 relaxation_state = 1;
3486 break;
886a2506 3487
bdd582db 3488 case OPTION_NPS400:
53a346d8
CZ		 3489 selected_cpu.features |= NPS400;
3490 cl_features |= NPS400;
bb050a69 3491 arc_check_feature ();
ce440d63 3492 break;
bdd582db 3493
ce440d63 3494 case OPTION_SPFP:
53a346d8
CZ		 3495 selected_cpu.features |= SPX;
3496 cl_features |= SPX;
bb050a69 3497 arc_check_feature ();
ce440d63
GM		 3498 break;
3499
3500 case OPTION_DPFP:
53a346d8
CZ		 3501 selected_cpu.features |= DPX;
3502 cl_features |= DPX;
bb050a69 3503 arc_check_feature ();
ce440d63
GM		 3504 break;
3505
3506 case OPTION_FPUDA:
53a346d8
CZ		 3507 selected_cpu.features |= DPA;
3508 cl_features |= DPA;
bb050a69 3509 arc_check_feature ();
ce440d63
GM		 3510 break;
3511
3512 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3513 case OPTION_USER_MODE:
3514 case OPTION_LD_EXT_MASK:
3515 case OPTION_SWAP:
3516 case OPTION_NORM:
3517 case OPTION_BARREL_SHIFT:
3518 case OPTION_MIN_MAX:
3519 case OPTION_NO_MPY:
3520 case OPTION_EA:
3521 case OPTION_MUL64:
3522 case OPTION_SIMD:
4670103e
CZ		 3523 case OPTION_XMAC_D16:
3524 case OPTION_XMAC_24:
3525 case OPTION_DSP_PACKA:
3526 case OPTION_CRC:
3527 case OPTION_DVBF:
3528 case OPTION_TELEPHONY:
3529 case OPTION_XYMEMORY:
3530 case OPTION_LOCK:
3531 case OPTION_SWAPE:
3532 case OPTION_RTSC:
8ddf6b2a
CZ		 3533 break;
3534
4670103e
CZ		 3535 default:
3536 return 0;
3537 }
886a2506 3538
4670103e
CZ		 3539 return 1;
3540}
886a2506 3541
a9752fdf
CZ		 3542/* Display the list of cpu names for use in the help text. */
3543
3544static void
3545arc_show_cpu_list (FILE *stream)
3546{
3547 int i, offset;
731f7c4e 3548 static const char *space_buf = " ";
a9752fdf 3549
731f7c4e
MR		 3550 fprintf (stream, "%s", space_buf);
3551 offset = strlen (space_buf);
a9752fdf
CZ		 3552 for (i = 0; cpu_types[i].name != NULL; ++i)
3553 {
5b7c81bd 3554 bool last = (cpu_types[i + 1].name == NULL);
a9752fdf
CZ		 3555
3556 /* If displaying the new cpu name string, and the ', ' (for all
3557 but the last one) will take us past a target width of 80
3558 characters, then it's time for a new line. */
3559 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3560 {
731f7c4e
MR		 3561 fprintf (stream, "\n%s", space_buf);
3562 offset = strlen (space_buf);
a9752fdf
CZ		 3563 }
3564
3565 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3566 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3567 }
3568}
3569
4670103e
CZ		 3570void
3571md_show_usage (FILE *stream)
3572{
3573 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3574
a9752fdf
CZ		 3575 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3576 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3577 arc_show_cpu_list (stream);
3578 fprintf (stream, "\n");
bdd582db
GM		 3579 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3580 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3581 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3582 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3583
3584 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3585 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3586 " instructions\n");
3587 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3588 " instructions\n");
bdd582db
GM		 3589 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3590 "point\n\t\t\t instructions for ARC EM\n");
3591
4670103e
CZ		 3592 fprintf (stream,
3593 " -mcode-density\t enable code density option for ARC EM\n");
3594
3595 fprintf (stream, _("\
3596 -EB assemble code for a big-endian cpu\n"));
3597 fprintf (stream, _("\
3598 -EL assemble code for a little-endian cpu\n"));
3599 fprintf (stream, _("\
bdd582db
GM		 3600 -mrelax enable relaxation\n"));
3601
3602 fprintf (stream, _("The following ARC-specific assembler options are "
3603 "deprecated and are accepted\nfor compatibility only:\n"));
3604
3605 fprintf (stream, _(" -mEA\n"
3606 " -mbarrel-shifter\n"
3607 " -mbarrel_shifter\n"
3608 " -mcrc\n"
3609 " -mdsp-packa\n"
3610 " -mdsp_packa\n"
3611 " -mdvbf\n"
3612 " -mld-extension-reg-mask\n"
3613 " -mlock\n"
3614 " -mmac-24\n"
3615 " -mmac-d16\n"
3616 " -mmac_24\n"
3617 " -mmac_d16\n"
3618 " -mmin-max\n"
3619 " -mmin_max\n"
3620 " -mmul64\n"
3621 " -mno-mpy\n"
3622 " -mnorm\n"
3623 " -mrtsc\n"
3624 " -msimd\n"
3625 " -mswap\n"
3626 " -mswape\n"
3627 " -mtelephony\n"
3628 " -muser-mode-only\n"
3629 " -mxy\n"));
886a2506
NC		 3630}
3631
3632/* Find the proper relocation for the given opcode. */
3633
3634static extended_bfd_reloc_code_real_type
3635find_reloc (const char *name,
3636 const char *opcodename,
3637 const struct arc_flags *pflags,
3638 int nflg,
3639 extended_bfd_reloc_code_real_type reloc)
3640{
3641 unsigned int i;
3642 int j;
5b7c81bd 3643 bool found_flag, tmp;
886a2506
NC		 3644 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3645
3646 for (i = 0; i < arc_num_equiv_tab; i++)
3647 {
3648 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3649
3650 /* Find the entry. */
3651 if (strcmp (name, r->name))
3652 continue;
3653 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3654 continue;
24b368f8 3655 if (r->flags[0])
886a2506
NC		 3656 {
3657 if (!nflg)
3658 continue;
5b7c81bd 3659 found_flag = false;
24b368f8
CZ		 3660 unsigned * psflg = (unsigned *)r->flags;
3661 do
3662 {
5b7c81bd 3663 tmp = false;
24b368f8
CZ		 3664 for (j = 0; j < nflg; j++)
3665 if (!strcmp (pflags[j].name,
3666 arc_flag_operands[*psflg].name))
3667 {
5b7c81bd 3668 tmp = true;
24b368f8
CZ		 3669 break;
3670 }
3671 if (!tmp)
3672 {
5b7c81bd 3673 found_flag = false;
24b368f8
CZ		 3674 break;
3675 }
3676 else
3677 {
5b7c81bd 3678 found_flag = true;
24b368f8
CZ		 3679 }
3680 ++ psflg;
3681 } while (*psflg);
3682
886a2506
NC		 3683 if (!found_flag)
3684 continue;
3685 }
3686
3687 if (reloc != r->oldreloc)
3688 continue;
3689 /* Found it. */
3690 ret = r->newreloc;
3691 break;
3692 }
3693
3694 if (ret == BFD_RELOC_UNUSED)
3695 as_bad (_("Unable to find %s relocation for instruction %s"),
3696 name, opcodename);
3697 return ret;
3698}
3699
4670103e
CZ		 3700/* All the symbol types that are allowed to be used for
3701 relaxation. */
3702
5b7c81bd 3703static bool
4670103e
CZ		 3704may_relax_expr (expressionS tok)
3705{
3706 /* Check if we have unrelaxable relocs. */
3707 switch (tok.X_md)
3708 {
3709 default:
3710 break;
3711 case O_plt:
5b7c81bd 3712 return false;
4670103e
CZ		 3713 }
3714
3715 switch (tok.X_op)
3716 {
3717 case O_symbol:
3718 case O_multiply:
3719 case O_divide:
3720 case O_modulus:
3721 case O_add:
3722 case O_subtract:
3723 break;
3724
3725 default:
5b7c81bd 3726 return false;
4670103e 3727 }
5b7c81bd 3728 return true;
4670103e
CZ		 3729}
3730
3731/* Checks if flags are in line with relaxable insn. */
3732
5b7c81bd 3733static bool
4670103e
CZ		 3734relaxable_flag (const struct arc_relaxable_ins *ins,
3735 const struct arc_flags *pflags,
3736 int nflgs)
3737{
3738 unsigned flag_class,
3739 flag,
3740 flag_class_idx = 0,
3741 flag_idx = 0;
3742
3743 const struct arc_flag_operand *flag_opand;
3744 int i, counttrue = 0;
3745
3746 /* Iterate through flags classes. */
3747 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3748 {
3749 /* Iterate through flags in flag class. */
3750 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3751 != 0)
3752 {
3753 flag_opand = &arc_flag_operands[flag];
3754 /* Iterate through flags in ins to compare. */
3755 for (i = 0; i < nflgs; ++i)
3756 {
3757 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3758 ++counttrue;
3759 }
3760
3761 ++flag_idx;
3762 }
3763
3764 ++flag_class_idx;
3765 flag_idx = 0;
3766 }
3767
3768 /* If counttrue == nflgs, then all flags have been found. */
63b4cc53 3769 return counttrue == nflgs;
4670103e
CZ		 3770}
3771
3772/* Checks if operands are in line with relaxable insn. */
3773
5b7c81bd 3774static bool
4670103e
CZ		 3775relaxable_operand (const struct arc_relaxable_ins *ins,
3776 const expressionS *tok,
3777 int ntok)
3778{
3779 const enum rlx_operand_type *operand = &ins->operands[0];
3780 int i = 0;
3781
3782 while (*operand != EMPTY)
3783 {
3784 const expressionS *epr = &tok[i];
3785
3786 if (i != 0 && i >= ntok)
5b7c81bd 3787 return false;
4670103e
CZ		 3788
3789 switch (*operand)
3790 {
3791 case IMMEDIATE:
3792 if (!(epr->X_op == O_multiply
3793 || epr->X_op == O_divide
3794 || epr->X_op == O_modulus
3795 || epr->X_op == O_add
3796 || epr->X_op == O_subtract
3797 || epr->X_op == O_symbol))
5b7c81bd 3798 return false;
4670103e
CZ		 3799 break;
3800
3801 case REGISTER_DUP:
3802 if ((i <= 0)
3803 || (epr->X_add_number != tok[i - 1].X_add_number))
5b7c81bd 3804 return false;
4670103e
CZ		 3805 /* Fall through. */
3806 case REGISTER:
3807 if (epr->X_op != O_register)
5b7c81bd 3808 return false;
4670103e
CZ		 3809 break;
3810
3811 case REGISTER_S:
3812 if (epr->X_op != O_register)
5b7c81bd 3813 return false;
4670103e
CZ		 3814
3815 switch (epr->X_add_number)
3816 {
3817 case 0: case 1: case 2: case 3:
3818 case 12: case 13: case 14: case 15:
3819 break;
3820 default:
5b7c81bd 3821 return false;
4670103e
CZ		 3822 }
3823 break;
3824
3825 case REGISTER_NO_GP:
3826 if ((epr->X_op != O_register)
3827 || (epr->X_add_number == 26)) /* 26 is the gp register. */
5b7c81bd 3828 return false;
4670103e
CZ		 3829 break;
3830
3831 case BRACKET:
3832 if (epr->X_op != O_bracket)
5b7c81bd 3833 return false;
4670103e
CZ		 3834 break;
3835
3836 default:
3837 /* Don't understand, bail out. */
5b7c81bd 3838 return false;
4670103e
CZ		 3839 break;
3840 }
3841
3842 ++i;
3843 operand = &ins->operands[i];
3844 }
3845
63b4cc53 3846 return i == ntok;
4670103e
CZ		 3847}
3848
3849/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3850
5b7c81bd 3851static bool
4670103e
CZ		 3852relax_insn_p (const struct arc_opcode *opcode,
3853 const expressionS *tok,
3854 int ntok,
3855 const struct arc_flags *pflags,
3856 int nflg)
3857{
3858 unsigned i;
5b7c81bd 3859 bool rv = false;
4670103e
CZ		 3860
3861 /* Check the relaxation table. */
3862 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3863 {
3864 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3865
3866 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3867 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3868 && relaxable_operand (arc_rlx_ins, tok, ntok)
3869 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3870 {
5b7c81bd 3871 rv = true;
4670103e
CZ		 3872 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3873 memcpy (&frag_now->tc_frag_data.tok, tok,
3874 sizeof (expressionS) * ntok);
3875 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3876 sizeof (struct arc_flags) * nflg);
3877 frag_now->tc_frag_data.nflg = nflg;
3878 frag_now->tc_frag_data.ntok = ntok;
3879 break;
3880 }
3881 }
3882
3883 return rv;
3884}
3885
886a2506
NC		 3886/* Turn an opcode description and a set of arguments into
3887 an instruction and a fixup. */
3888
3889static void
3890assemble_insn (const struct arc_opcode *opcode,
3891 const expressionS *tok,
3892 int ntok,
3893 const struct arc_flags *pflags,
3894 int nflg,
3895 struct arc_insn *insn)
3896{
3897 const expressionS *reloc_exp = NULL;
bdfe53e3 3898 unsigned long long image;
886a2506
NC		 3899 const unsigned char *argidx;
3900 int i;
3901 int tokidx = 0;
3902 unsigned char pcrel = 0;
5b7c81bd
AM		 3903 bool needGOTSymbol;
3904 bool has_delay_slot = false;
886a2506
NC		 3905 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3906
3907 memset (insn, 0, sizeof (*insn));
3908 image = opcode->opcode;
3909
bdfe53e3 3910 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3911 frag_now->fr_file, frag_now->fr_line, opcode->name,
3912 opcode->opcode);
3913
3914 /* Handle operands. */
3915 for (argidx = opcode->operands; *argidx; ++argidx)
3916 {
3917 const struct arc_operand *operand = &arc_operands[*argidx];
3918 const expressionS *t = (const expressionS *) 0;
3919
db18dbab 3920 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3921 continue;
3922
3923 if (operand->flags & ARC_OPERAND_DUPLICATE)
3924 {
3925 /* Duplicate operand, already inserted. */
3926 tokidx ++;
3927 continue;
3928 }
3929
3930 if (tokidx >= ntok)
3931 {
3932 abort ();
3933 }
3934 else
3935 t = &tok[tokidx++];
3936
3937 /* Regardless if we have a reloc or not mark the instruction
3938 limm if it is the case. */
3939 if (operand->flags & ARC_OPERAND_LIMM)
5b7c81bd 3940 insn->has_limm = true;
886a2506
NC		 3941
3942 switch (t->X_op)
3943 {
3944 case O_register:
3945 image = insert_operand (image, operand, regno (t->X_add_number),
3946 NULL, 0);
3947 break;
3948
3949 case O_constant:
3950 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3951 reloc_exp = t;
3952 if (operand->flags & ARC_OPERAND_LIMM)
3953 insn->limm = t->X_add_number;
3954 break;
3955
3956 case O_bracket:
db18dbab
GM		 3957 case O_colon:
3958 case O_addrtype:
3959 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3960 break;
3961
3962 case O_absent:
3963 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3964 break;
3965
3966 case O_subtract:
3967 /* Maybe register range. */
3968 if ((t->X_add_number == 0)
3969 && contains_register (t->X_add_symbol)
3970 && contains_register (t->X_op_symbol))
3971 {
3972 int regs;
3973
3974 regs = get_register (t->X_add_symbol);
3975 regs <<= 16;
3976 regs |= get_register (t->X_op_symbol);
3977 image = insert_operand (image, operand, regs, NULL, 0);
3978 break;
3979 }
1a0670f3 3980 /* Fall through. */
886a2506
NC		 3981
3982 default:
3983 /* This operand needs a relocation. */
5b7c81bd 3984 needGOTSymbol = false;
886a2506
NC		 3985
3986 switch (t->X_md)
3987 {
3988 case O_plt:
c810e0b8 3989 if (opcode->insn_class == JUMP)
6e3f3473 3990 as_bad (_("Unable to use @plt relocation for insn %s"),
3991 opcode->name);
5b7c81bd 3992 needGOTSymbol = true;
886a2506
NC		 3993 reloc = find_reloc ("plt", opcode->name,
3994 pflags, nflg,
3995 operand->default_reloc);
3996 break;
3997
3998 case O_gotoff:
3999 case O_gotpc:
5b7c81bd 4000 needGOTSymbol = true;
886a2506
NC		 4001 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4002 break;
4003 case O_pcl:
cc07cda6
CZ		 4004 if (operand->flags & ARC_OPERAND_LIMM)
4005 {
4006 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4007 if (arc_opcode_len (opcode) == 2
4008 || opcode->insn_class == JUMP)
6e3f3473 4009 as_bad (_("Unable to use @pcl relocation for insn %s"),
4010 opcode->name);
cc07cda6
CZ		 4011 }
4012 else
4013 {
4014 /* This is a relaxed operand which initially was
4015 limm, choose whatever we have defined in the
4016 opcode as reloc. */
4017 reloc = operand->default_reloc;
4018 }
886a2506
NC		 4019 break;
4020 case O_sda:
4021 reloc = find_reloc ("sda", opcode->name,
4022 pflags, nflg,
4023 operand->default_reloc);
4024 break;
4025 case O_tlsgd:
4026 case O_tlsie:
5b7c81bd 4027 needGOTSymbol = true;
886a2506
NC		 4028 /* Fall-through. */
4029
4030 case O_tpoff:
4031 case O_dtpoff:
4032 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4033 break;
4034
4035 case O_tpoff9: /*FIXME! Check for the conditionality of
4036 the insn. */
4037 case O_dtpoff9: /*FIXME! Check for the conditionality of
4038 the insn. */
4039 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4040 break;
4041
4042 default:
4043 /* Just consider the default relocation. */
4044 reloc = operand->default_reloc;
4045 break;
4046 }
4047
4048 if (needGOTSymbol && (GOT_symbol == NULL))
4049 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4050
4051 reloc_exp = t;
4052
4053#if 0
4054 if (reloc > 0)
4055 {
4056 /* sanity checks. */
4057 reloc_howto_type *reloc_howto
4058 = bfd_reloc_type_lookup (stdoutput,
4059 (bfd_reloc_code_real_type) reloc);
4060 unsigned reloc_bitsize = reloc_howto->bitsize;
4061 if (reloc_howto->rightshift)
4062 reloc_bitsize -= reloc_howto->rightshift;
4063 if (reloc_bitsize != operand->bits)
4064 {
4065 as_bad (_("invalid relocation %s for field"),
4066 bfd_get_reloc_code_name (reloc));
4067 return;
4068 }
4069 }
4070#endif
4071 if (insn->nfixups >= MAX_INSN_FIXUPS)
4072 as_fatal (_("too many fixups"));
4073
4074 struct arc_fixup *fixup;
4075 fixup = &insn->fixups[insn->nfixups++];
4076 fixup->exp = *t;
4077 fixup->reloc = reloc;
cc07cda6
CZ		 4078 if ((int) reloc < 0)
4079 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4080 else
4081 {
4082 reloc_howto_type *reloc_howto =
4083 bfd_reloc_type_lookup (stdoutput,
4084 (bfd_reloc_code_real_type) fixup->reloc);
4085 pcrel = reloc_howto->pc_relative;
4086 }
886a2506 4087 fixup->pcrel = pcrel;
63b4cc53 4088 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) != 0;
886a2506
NC		 4089 break;
4090 }
4091 }
4092
4093 /* Handle flags. */
4094 for (i = 0; i < nflg; i++)
4095 {
f36e33da 4096 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4097
4098 /* Check if the instruction has a delay slot. */
4099 if (!strcmp (flg_operand->name, "d"))
5b7c81bd 4100 has_delay_slot = true;
886a2506 4101
2c52e2e8
RZ		 4102 /* There is an exceptional case when we cannot insert a flag just as
4103 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4104 relation with the relative address. Unfortunately, some of the
4105 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4106 handled in the normal way.
4107
4108 Flag operands don't have an architecture field, so we can't
4109 directly validate that FLAG_OPERAND is valid for the current
4110 architecture, what we do instead is just validate that we're
4111 assembling for an ARCv2 architecture. */
4112 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4113 && (!strcmp (flg_operand->name, "t")
4114 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4115 {
4116 unsigned bitYoperand = 0;
4117 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4118 if (!strcmp (flg_operand->name, "t"))
4119 if (!strcmp (opcode->name, "bbit0")
4120 || !strcmp (opcode->name, "bbit1"))
4121 bitYoperand = arc_NToperand;
4122 else
4123 bitYoperand = arc_Toperand;
4124 else
4125 if (!strcmp (opcode->name, "bbit0")
4126 || !strcmp (opcode->name, "bbit1"))
4127 bitYoperand = arc_Toperand;
4128 else
4129 bitYoperand = arc_NToperand;
4130
4131 gas_assert (reloc_exp != NULL);
4132 if (reloc_exp->X_op == O_constant)
4133 {
4134 /* Check if we have a constant and solved it
4135 immediately. */
4136 offsetT val = reloc_exp->X_add_number;
4137 image |= insert_operand (image, &arc_operands[bitYoperand],
4138 val, NULL, 0);
4139 }
4140 else
4141 {
4142 struct arc_fixup *fixup;
4143
4144 if (insn->nfixups >= MAX_INSN_FIXUPS)
4145 as_fatal (_("too many fixups"));
4146
4147 fixup = &insn->fixups[insn->nfixups++];
4148 fixup->exp = *reloc_exp;
4149 fixup->reloc = -bitYoperand;
4150 fixup->pcrel = pcrel;
5b7c81bd 4151 fixup->islong = false;
886a2506
NC		 4152 }
4153 }
4154 else
4155 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4156 << flg_operand->shift;
4157 }
4158
4670103e
CZ		 4159 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4160
91fdca6f 4161 /* Instruction length. */
06fe285f 4162 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4163
4164 insn->insn = image;
4165
4166 /* Update last insn status. */
4167 arc_last_insns[1] = arc_last_insns[0];
4168 arc_last_insns[0].opcode = opcode;
4169 arc_last_insns[0].has_limm = insn->has_limm;
4170 arc_last_insns[0].has_delay_slot = has_delay_slot;
4171
4172 /* Check if the current instruction is legally used. */
4173 if (arc_last_insns[1].has_delay_slot
4174 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
6e3f3473 4175 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4176 arc_last_insns[1].opcode->name,
4177 arc_last_insns[0].opcode->name);
cf9bdae9 4178 if (arc_last_insns[1].has_delay_slot
4179 && arc_last_insns[0].has_limm)
4180 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4181 arc_last_insns[1].opcode->name,
4182 arc_last_insns[0].opcode->name);
886a2506
NC		 4183}
4184
886a2506
NC		 4185void
4186arc_handle_align (fragS* fragP)
4187{
4188 if ((fragP)->fr_type == rs_align_code)
4189 {
4190 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4191 valueT count = ((fragP)->fr_next->fr_address
4192 - (fragP)->fr_address - (fragP)->fr_fix);
4193
4194 (fragP)->fr_var = 2;
4195
4196 if (count & 1)/* Padding in the gap till the next 2-byte
4197 boundary with 0s. */
4198 {
4199 (fragP)->fr_fix++;
4200 *dest++ = 0;
4201 }
4202 /* Writing nop_s. */
4203 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4204 }
4205}
4206
4207/* Here we decide which fixups can be adjusted to make them relative
4208 to the beginning of the section instead of the symbol. Basically
4209 we need to make sure that the dynamic relocations are done
4210 correctly, so in some cases we force the original symbol to be
4211 used. */
4212
4213int
4214tc_arc_fix_adjustable (fixS *fixP)
4215{
4216
4217 /* Prevent all adjustments to global symbols. */
4218 if (S_IS_EXTERNAL (fixP->fx_addsy))
4219 return 0;
4220 if (S_IS_WEAK (fixP->fx_addsy))
4221 return 0;
4222
4223 /* Adjust_reloc_syms doesn't know about the GOT. */
4224 switch (fixP->fx_r_type)
4225 {
4226 case BFD_RELOC_ARC_GOTPC32:
4227 case BFD_RELOC_ARC_PLT32:
4228 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4229 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4230 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4231 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4232 return 0;
4233
4234 default:
4235 break;
4236 }
4237
841fdfcd 4238 return 1;
886a2506
NC		 4239}
4240
4241/* Compute the reloc type of an expression EXP. */
4242
4243static void
4244arc_check_reloc (expressionS *exp,
4245 bfd_reloc_code_real_type *r_type_p)
4246{
4247 if (*r_type_p == BFD_RELOC_32
4248 && exp->X_op == O_subtract
4249 && exp->X_op_symbol != NULL
8d1015a8 4250 && S_GET_SEGMENT (exp->X_op_symbol) == now_seg)
6f4b1afc 4251 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4252}
4253
4254
4255/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4256
4257void
4258arc_cons_fix_new (fragS *frag,
4259 int off,
4260 int size,
4261 expressionS *exp,
4262 bfd_reloc_code_real_type r_type)
4263{
4264 r_type = BFD_RELOC_UNUSED;
4265
4266 switch (size)
4267 {
4268 case 1:
4269 r_type = BFD_RELOC_8;
4270 break;
4271
4272 case 2:
4273 r_type = BFD_RELOC_16;
4274 break;
4275
4276 case 3:
4277 r_type = BFD_RELOC_24;
4278 break;
4279
4280 case 4:
4281 r_type = BFD_RELOC_32;
4282 arc_check_reloc (exp, &r_type);
4283 break;
4284
4285 case 8:
4286 r_type = BFD_RELOC_64;
4287 break;
4288
4289 default:
4290 as_bad (_("unsupported BFD relocation size %u"), size);
4291 r_type = BFD_RELOC_UNUSED;
4292 }
4293
4294 fix_new_exp (frag, off, size, exp, 0, r_type);
4295}
4296
4297/* The actual routine that checks the ZOL conditions. */
4298
4299static void
4300check_zol (symbolS *s)
4301{
bb65a718 4302 switch (selected_cpu.mach)
886a2506
NC		 4303 {
4304 case bfd_mach_arc_arcv2:
bb65a718 4305 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4306 return;
4307
4308 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4309 || arc_last_insns[1].has_delay_slot)
4310 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4311 S_GET_NAME (s));
4312
4313 break;
4314 case bfd_mach_arc_arc600:
4315
4316 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4317 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4318 S_GET_NAME (s));
4319
4320 if (arc_last_insns[0].has_limm
4321 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4322 as_bad (_("A jump instruction with long immediate detected at the \
4323end of the ZOL label @%s"), S_GET_NAME (s));
4324
4325 /* Fall through. */
4326 case bfd_mach_arc_arc700:
4327 if (arc_last_insns[0].has_delay_slot)
4328 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4329 S_GET_NAME (s));
4330
4331 break;
4332 default:
4333 break;
4334 }
4335}
4336
4337/* If ZOL end check the last two instruction for illegals. */
4338void
4339arc_frob_label (symbolS * sym)
4340{
4341 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4342 check_zol (sym);
4343
4344 dwarf2_emit_label (sym);
ea1562b3 4345}
4670103e
CZ		 4346
4347/* Used because generic relaxation assumes a pc-rel value whilst we
4348 also relax instructions that use an absolute value resolved out of
4349 relative values (if that makes any sense). An example: 'add r1,
4350 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4351 but if they're in the same section we can subtract the section
4352 offset relocation which ends up in a resolved value. So if @.L2 is
4353 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4354 .text + 0x40 = 0x10. */
4355int
4356arc_pcrel_adjust (fragS *fragP)
4357{
cc07cda6
CZ		 4358 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4359 fragP->fr_address, fragP->fr_fix,
4360 fragP->tc_frag_data.pcrel ? "Y" : "N");
4361
4670103e
CZ		 4362 if (!fragP->tc_frag_data.pcrel)
4363 return fragP->fr_address + fragP->fr_fix;
4364
cc07cda6
CZ		 4365 /* Take into account the PCL rounding. */
4366 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4367}
726c18e1
CZ		 4368
4369/* Initialize the DWARF-2 unwind information for this procedure. */
4370
4371void
4372tc_arc_frame_initial_instructions (void)
4373{
4374 /* Stack pointer is register 28. */
45a54ee5 4375 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4376}
4377
4378int
4379tc_arc_regname_to_dw2regnum (char *regname)
4380{
4381 struct symbol *sym;
4382
629310ab 4383 sym = str_hash_find (arc_reg_hash, regname);
726c18e1
CZ		 4384 if (sym)
4385 return S_GET_VALUE (sym);
4386
4387 return -1;
4388}
37ab9779
CZ		 4389
4390/* Adjust the symbol table. Delete found AUX register symbols. */
4391
4392void
4393arc_adjust_symtab (void)
4394{
4395 symbolS * sym;
4396
4397 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4398 {
4399 /* I've created a symbol during parsing process. Now, remove
4400 the symbol as it is found to be an AUX register. */
4401 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4402 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4403 }
4404
4405 /* Now do generic ELF adjustments. */
4406 elf_adjust_symtab ();
4407}
b99747ae
CZ		 4408
4409static void
4410tokenize_extinsn (extInstruction_t *einsn)
4411{
4412 char *p, c;
4413 char *insn_name;
4414 unsigned char major_opcode;
4415 unsigned char sub_opcode;
4416 unsigned char syntax_class = 0;
4417 unsigned char syntax_class_modifiers = 0;
4418 unsigned char suffix_class = 0;
4419 unsigned int i;
4420
4421 SKIP_WHITESPACE ();
4422
4423 /* 1st: get instruction name. */
4424 p = input_line_pointer;
4425 c = get_symbol_name (&p);
4426
4427 insn_name = xstrdup (p);
4428 restore_line_pointer (c);
4429
f02806be 4430 /* Convert to lower case. */
4431 for (p = insn_name; *p; ++p)
4432 *p = TOLOWER (*p);
4433
b99747ae
CZ		 4434 /* 2nd: get major opcode. */
4435 if (*input_line_pointer != ',')
4436 {
4437 as_bad (_("expected comma after instruction name"));
4438 ignore_rest_of_line ();
4439 return;
4440 }
4441 input_line_pointer++;
4442 major_opcode = get_absolute_expression ();
4443
4444 /* 3rd: get sub-opcode. */
4445 SKIP_WHITESPACE ();
4446
4447 if (*input_line_pointer != ',')
4448 {
4449 as_bad (_("expected comma after major opcode"));
4450 ignore_rest_of_line ();
4451 return;
4452 }
4453 input_line_pointer++;
4454 sub_opcode = get_absolute_expression ();
4455
4456 /* 4th: get suffix class. */
4457 SKIP_WHITESPACE ();
4458
4459 if (*input_line_pointer != ',')
4460 {
4461 as_bad ("expected comma after sub opcode");
4462 ignore_rest_of_line ();
4463 return;
4464 }
4465 input_line_pointer++;
4466
4467 while (1)
4468 {
4469 SKIP_WHITESPACE ();
4470
4471 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4472 {
4473 if (!strncmp (suffixclass[i].name, input_line_pointer,
4474 suffixclass[i].len))
4475 {
c810e0b8 4476 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4477 input_line_pointer += suffixclass[i].len;
4478 break;
4479 }
4480 }
4481
4482 if (i == ARRAY_SIZE (suffixclass))
4483 {
4484 as_bad ("invalid suffix class");
4485 ignore_rest_of_line ();
4486 return;
4487 }
4488
4489 SKIP_WHITESPACE ();
4490
4491 if (*input_line_pointer == '|')
4492 input_line_pointer++;
4493 else
4494 break;
4495 }
4496
4497 /* 5th: get syntax class and syntax class modifiers. */
4498 if (*input_line_pointer != ',')
4499 {
4500 as_bad ("expected comma after suffix class");
4501 ignore_rest_of_line ();
4502 return;
4503 }
4504 input_line_pointer++;
4505
4506 while (1)
4507 {
4508 SKIP_WHITESPACE ();
4509
4510 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4511 {
4512 if (!strncmp (syntaxclassmod[i].name,
4513 input_line_pointer,
4514 syntaxclassmod[i].len))
4515 {
c810e0b8 4516 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4517 input_line_pointer += syntaxclassmod[i].len;
4518 break;
4519 }
4520 }
4521
4522 if (i == ARRAY_SIZE (syntaxclassmod))
4523 {
4524 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4525 {
4526 if (!strncmp (syntaxclass[i].name,
4527 input_line_pointer,
4528 syntaxclass[i].len))
4529 {
c810e0b8 4530 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4531 input_line_pointer += syntaxclass[i].len;
4532 break;
4533 }
4534 }
4535
4536 if (i == ARRAY_SIZE (syntaxclass))
4537 {
4538 as_bad ("missing syntax class");
4539 ignore_rest_of_line ();
4540 return;
4541 }
4542 }
4543
4544 SKIP_WHITESPACE ();
4545
4546 if (*input_line_pointer == '|')
4547 input_line_pointer++;
4548 else
4549 break;
4550 }
4551
4552 demand_empty_rest_of_line ();
4553
4554 einsn->name = insn_name;
4555 einsn->major = major_opcode;
4556 einsn->minor = sub_opcode;
4557 einsn->syntax = syntax_class;
4558 einsn->modsyn = syntax_class_modifiers;
4559 einsn->suffix = suffix_class;
4560 einsn->flags = syntax_class
4561 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4562}
4563
4564/* Generate an extension section. */
4565
4566static int
4567arc_set_ext_seg (void)
4568{
4569 if (!arcext_section)
4570 {
4571 arcext_section = subseg_new (".arcextmap", 0);
fd361982 4572 bfd_set_section_flags (arcext_section, SEC_READONLY | SEC_HAS_CONTENTS);
b99747ae
CZ		 4573 }
4574 else
4575 subseg_set (arcext_section, 0);
4576 return 1;
4577}
4578
4579/* Create an extension instruction description in the arc extension
4580 section of the output file.
4581 The structure for an instruction is like this:
4582 [0]: Length of the record.
4583 [1]: Type of the record.
4584
4585 [2]: Major opcode.
4586 [3]: Sub-opcode.
4587 [4]: Syntax (flags).
4588 [5]+ Name instruction.
4589
4590 The sequence is terminated by an empty entry. */
4591
4592static void
4593create_extinst_section (extInstruction_t *einsn)
4594{
4595
4596 segT old_sec = now_seg;
4597 int old_subsec = now_subseg;
4598 char *p;
4599 int name_len = strlen (einsn->name);
4600
4601 arc_set_ext_seg ();
4602
4603 p = frag_more (1);
4604 *p = 5 + name_len + 1;
4605 p = frag_more (1);
4606 *p = EXT_INSTRUCTION;
4607 p = frag_more (1);
4608 *p = einsn->major;
4609 p = frag_more (1);
4610 *p = einsn->minor;
4611 p = frag_more (1);
4612 *p = einsn->flags;
4613 p = frag_more (name_len + 1);
4614 strcpy (p, einsn->name);
4615
4616 subseg_set (old_sec, old_subsec);
4617}
4618
4619/* Handler .extinstruction pseudo-op. */
4620
4621static void
4622arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4623{
4624 extInstruction_t einsn;
4625 struct arc_opcode *arc_ext_opcodes;
4626 const char *errmsg = NULL;
4627 unsigned char moplow, mophigh;
4628
4629 memset (&einsn, 0, sizeof (einsn));
4630 tokenize_extinsn (&einsn);
4631
4632 /* Check if the name is already used. */
4633 if (arc_find_opcode (einsn.name))
4634 as_warn (_("Pseudocode already used %s"), einsn.name);
4635
4636 /* Check the opcode ranges. */
4637 moplow = 0x05;
bb65a718
AB		 4638 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4639 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4640
4641 if ((einsn.major > mophigh) || (einsn.major < moplow))
4642 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4643
4644 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4645 && (einsn.major != 5) && (einsn.major != 9))
4646 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4647
945e0f82 4648 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4649 {
4650 case ARC_SYNTAX_3OP:
4651 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4652 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4653 break;
4654 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4655 case ARC_SYNTAX_1OP:
4656 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4657 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4658 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4659 break;
4660 default:
4661 break;
4662 }
4663
bb65a718 4664 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4665 if (arc_ext_opcodes == NULL)
4666 {
4667 if (errmsg)
4668 as_fatal ("%s", errmsg);
4669 else
4670 as_fatal (_("Couldn't generate extension instruction opcodes"));
4671 }
4672 else if (errmsg)
4673 as_warn ("%s", errmsg);
4674
4675 /* Insert the extension instruction. */
4676 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4677
4678 create_extinst_section (&einsn);
4679}
4680
5b7c81bd 4681static bool
f36e33da
CZ		 4682tokenize_extregister (extRegister_t *ereg, int opertype)
4683{
4684 char *name;
4685 char *mode;
4686 char c;
4687 char *p;
4688 int number, imode = 0;
5b7c81bd
AM		 4689 bool isCore_p = opertype == EXT_CORE_REGISTER;
4690 bool isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
f36e33da
CZ		 4691
4692 /* 1st: get register name. */
4693 SKIP_WHITESPACE ();
4694 p = input_line_pointer;
4695 c = get_symbol_name (&p);
4696
4697 name = xstrdup (p);
4698 restore_line_pointer (c);
4699
4700 /* 2nd: get register number. */
4701 SKIP_WHITESPACE ();
4702
4703 if (*input_line_pointer != ',')
4704 {
06911889 4705 as_bad (_("expected comma after name"));
f36e33da
CZ		 4706 ignore_rest_of_line ();
4707 free (name);
5b7c81bd 4708 return false;
f36e33da
CZ		 4709 }
4710 input_line_pointer++;
4711 number = get_absolute_expression ();
4712
06911889
CZ		 4713 if ((number < 0)
4714 && (opertype != EXT_AUX_REGISTER))
f36e33da 4715 {
06911889
CZ		 4716 as_bad (_("%s second argument cannot be a negative number %d"),
4717 isCore_p ? "extCoreRegister's" : "extCondCode's",
4718 number);
f36e33da
CZ		 4719 ignore_rest_of_line ();
4720 free (name);
5b7c81bd 4721 return false;
f36e33da
CZ		 4722 }
4723
4724 if (isReg_p)
4725 {
4726 /* 3rd: get register mode. */
4727 SKIP_WHITESPACE ();
4728
4729 if (*input_line_pointer != ',')
4730 {
4731 as_bad (_("expected comma after register number"));
4732 ignore_rest_of_line ();
4733 free (name);
5b7c81bd 4734 return false;
f36e33da
CZ		 4735 }
4736
4737 input_line_pointer++;
4738 mode = input_line_pointer;
4739
d34049e8 4740 if (startswith (mode, "r|w"))
f36e33da
CZ		 4741 {
4742 imode = 0;
4743 input_line_pointer += 3;
4744 }
d34049e8 4745 else if (startswith (mode, "r"))
f36e33da
CZ		 4746 {
4747 imode = ARC_REGISTER_READONLY;
4748 input_line_pointer += 1;
4749 }
d34049e8 4750 else if (!startswith (mode, "w"))
f36e33da
CZ		 4751 {
4752 as_bad (_("invalid mode"));
4753 ignore_rest_of_line ();
4754 free (name);
5b7c81bd 4755 return false;
f36e33da
CZ		 4756 }
4757 else
4758 {
4759 imode = ARC_REGISTER_WRITEONLY;
4760 input_line_pointer += 1;
4761 }
4762 }
4763
4764 if (isCore_p)
4765 {
4766 /* 4th: get core register shortcut. */
4767 SKIP_WHITESPACE ();
4768 if (*input_line_pointer != ',')
4769 {
4770 as_bad (_("expected comma after register mode"));
4771 ignore_rest_of_line ();
4772 free (name);
5b7c81bd 4773 return false;
f36e33da
CZ		 4774 }
4775
4776 input_line_pointer++;
4777
d34049e8 4778 if (startswith (input_line_pointer, "cannot_shortcut"))
f36e33da
CZ		 4779 {
4780 imode |= ARC_REGISTER_NOSHORT_CUT;
4781 input_line_pointer += 15;
4782 }
d34049e8 4783 else if (!startswith (input_line_pointer, "can_shortcut"))
f36e33da
CZ		 4784 {
4785 as_bad (_("shortcut designator invalid"));
4786 ignore_rest_of_line ();
4787 free (name);
5b7c81bd 4788 return false;
f36e33da
CZ		 4789 }
4790 else
4791 {
4792 input_line_pointer += 12;
4793 }
4794 }
4795 demand_empty_rest_of_line ();
4796
4797 ereg->name = name;
4798 ereg->number = number;
4799 ereg->imode = imode;
5b7c81bd 4800 return true;
f36e33da
CZ		 4801}
4802
4803/* Create an extension register/condition description in the arc
4804 extension section of the output file.
4805
4806 The structure for an instruction is like this:
4807 [0]: Length of the record.
4808 [1]: Type of the record.
4809
4810 For core regs and condition codes:
4811 [2]: Value.
4812 [3]+ Name.
4813
33eaf5de 4814 For auxiliary registers:
f36e33da
CZ		 4815 [2..5]: Value.
4816 [6]+ Name
4817
4818 The sequence is terminated by an empty entry. */
4819
4820static void
4821create_extcore_section (extRegister_t *ereg, int opertype)
4822{
4823 segT old_sec = now_seg;
4824 int old_subsec = now_subseg;
4825 char *p;
4826 int name_len = strlen (ereg->name);
4827
4828 arc_set_ext_seg ();
4829
4830 switch (opertype)
4831 {
4832 case EXT_COND_CODE:
4833 case EXT_CORE_REGISTER:
4834 p = frag_more (1);
4835 *p = 3 + name_len + 1;
4836 p = frag_more (1);
4837 *p = opertype;
4838 p = frag_more (1);
4839 *p = ereg->number;
4840 break;
4841 case EXT_AUX_REGISTER:
4842 p = frag_more (1);
4843 *p = 6 + name_len + 1;
4844 p = frag_more (1);
4845 *p = EXT_AUX_REGISTER;
4846 p = frag_more (1);
4847 *p = (ereg->number >> 24) & 0xff;
4848 p = frag_more (1);
4849 *p = (ereg->number >> 16) & 0xff;
4850 p = frag_more (1);
4851 *p = (ereg->number >> 8) & 0xff;
4852 p = frag_more (1);
4853 *p = (ereg->number) & 0xff;
4854 break;
4855 default:
4856 break;
4857 }
4858
4859 p = frag_more (name_len + 1);
4860 strcpy (p, ereg->name);
4861
4862 subseg_set (old_sec, old_subsec);
4863}
4864
4865/* Handler .extCoreRegister pseudo-op. */
4866
4867static void
4868arc_extcorereg (int opertype)
4869{
4870 extRegister_t ereg;
4871 struct arc_aux_reg *auxr;
f36e33da
CZ		 4872 struct arc_flag_operand *ccode;
4873
4874 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4875 if (!tokenize_extregister (&ereg, opertype))
4876 return;
f36e33da
CZ		 4877
4878 switch (opertype)
4879 {
4880 case EXT_CORE_REGISTER:
4881 /* Core register. */
4882 if (ereg.number > 60)
4883 as_bad (_("core register %s value (%d) too large"), ereg.name,
4884 ereg.number);
4885 declare_register (ereg.name, ereg.number);
4886 break;
4887 case EXT_AUX_REGISTER:
4888 /* Auxiliary register. */
add39d23 4889 auxr = XNEW (struct arc_aux_reg);
f36e33da 4890 auxr->name = ereg.name;
bb65a718 4891 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4892 auxr->subclass = NONE;
4893 auxr->address = ereg.number;
fe0e921f
AM		 4894 if (str_hash_insert (arc_aux_hash, auxr->name, auxr, 0) != NULL)
4895 as_bad (_("duplicate aux register %s"), auxr->name);
f36e33da
CZ		 4896 break;
4897 case EXT_COND_CODE:
4898 /* Condition code. */
4899 if (ereg.number > 31)
4900 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4901 ereg.number);
4902 ext_condcode.size ++;
4903 ext_condcode.arc_ext_condcode =
add39d23
TS		 4904 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4905 ext_condcode.size + 1);
f36e33da
CZ		 4906
4907 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4908 ccode->name = ereg.name;
4909 ccode->code = ereg.number;
4910 ccode->bits = 5;
4911 ccode->shift = 0;
4912 ccode->favail = 0; /* not used. */
4913 ccode++;
4914 memset (ccode, 0, sizeof (struct arc_flag_operand));
4915 break;
4916 default:
4917 as_bad (_("Unknown extension"));
4918 break;
4919 }
4920 create_extcore_section (&ereg, opertype);
4921}
4922
53a346d8
CZ		 4923/* Parse a .arc_attribute directive. */
4924
4925static void
4926arc_attribute (int ignored ATTRIBUTE_UNUSED)
4927{
4928 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4929
4930 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
5b7c81bd 4931 attributes_set_explicitly[tag] = true;
53a346d8
CZ		 4932}
4933
4934/* Set an attribute if it has not already been set by the user. */
4935
4936static void
4937arc_set_attribute_int (int tag, int value)
4938{
4939 if (tag < 1
4940 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4941 || !attributes_set_explicitly[tag])
4942 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4943}
4944
4945static void
4946arc_set_attribute_string (int tag, const char *value)
4947{
4948 if (tag < 1
4949 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4950 || !attributes_set_explicitly[tag])
4951 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4952}
4953
4954/* Allocate and concatenate two strings. s1 can be NULL but not
4955 s2. s1 pointer is freed at end of this procedure. */
4956
4957static char *
4958arc_stralloc (char * s1, const char * s2)
4959{
4960 char * p;
4961 int len = 0;
4962
4963 if (s1)
4964 len = strlen (s1) + 1;
4965
4966 /* Only s1 can be null. */
4967 gas_assert (s2);
4968 len += strlen (s2) + 1;
4969
4970 p = (char *) xmalloc (len);
53a346d8
CZ		 4971
4972 if (s1)
4973 {
4974 strcpy (p, s1);
4975 strcat (p, ",");
4976 strcat (p, s2);
4977 free (s1);
4978 }
4979 else
4980 strcpy (p, s2);
4981
4982 return p;
4983}
4984
4985/* Set the public ARC object attributes. */
4986
4987static void
4988arc_set_public_attributes (void)
4989{
4990 int base = 0;
4991 char *s = NULL;
4992 unsigned int i;
4993
4994 /* Tag_ARC_CPU_name. */
4995 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4996
4997 /* Tag_ARC_CPU_base. */
4998 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4999 {
5000 case E_ARC_MACH_ARC600:
5001 case E_ARC_MACH_ARC601:
5002 base = TAG_CPU_ARC6xx;
5003 break;
5004 case E_ARC_MACH_ARC700:
5005 base = TAG_CPU_ARC7xx;
5006 break;
5007 case EF_ARC_CPU_ARCV2EM:
5008 base = TAG_CPU_ARCEM;
5009 break;
5010 case EF_ARC_CPU_ARCV2HS:
5011 base = TAG_CPU_ARCHS;
5012 break;
5013 default:
5014 base = 0;
5015 break;
5016 }
5017 if (attributes_set_explicitly[Tag_ARC_CPU_base]
5018 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5019 Tag_ARC_CPU_base)))
5020 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5021 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
5022
5023 /* Tag_ARC_ABI_osver. */
5024 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
5025 {
5026 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5027 Tag_ARC_ABI_osver);
5028
5029 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
5030 | (val & 0x0f << 8));
5031 }
5032 else
5033 {
5034 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
5035 }
5036
5037 /* Tag_ARC_ISA_config. */
5038 arc_check_feature();
5039
5040 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
5041 if (selected_cpu.features & feature_list[i].feature)
5042 s = arc_stralloc (s, feature_list[i].attr);
5043
5044 if (s)
5045 arc_set_attribute_string (Tag_ARC_ISA_config, s);
5046
5047 /* Tag_ARC_ISA_mpy_option. */
5048 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
5049
5050 /* Tag_ARC_ABI_pic. */
5051 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
5052
5053 /* Tag_ARC_ABI_sda. */
5054 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5055
5056 /* Tag_ARC_ABI_tls. */
5057 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
db1e1b45 5058
5059 /* Tag_ARC_ATR_version. */
5060 arc_set_attribute_int (Tag_ARC_ATR_version, 1);
63741043 5061
5062 /* Tag_ARC_ABI_rf16. */
5063 if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
5064 && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5065 Tag_ARC_ABI_rf16)
5066 && !rf16_only)
5067 {
5068 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5069 "register file"));
5070 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
5071 }
53a346d8
CZ		 5072}
5073
5074/* Add the default contents for the .ARC.attributes section. */
5075
5076void
ed2917de 5077arc_md_finish (void)
53a346d8
CZ		 5078{
5079 arc_set_public_attributes ();
5080
5081 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5082 as_fatal (_("could not set architecture and machine"));
5083
5084 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5085}
5086
5087void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5088{
5089 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5090}
5091
5092int arc_convert_symbolic_attribute (const char *name)
5093{
5094 static const struct
5095 {
5096 const char * name;
5097 const int tag;
5098 }
5099 attribute_table[] =
5100 {
5101#define T(tag) {#tag, tag}
5102 T (Tag_ARC_PCS_config),
5103 T (Tag_ARC_CPU_base),
5104 T (Tag_ARC_CPU_variation),
5105 T (Tag_ARC_CPU_name),
5106 T (Tag_ARC_ABI_rf16),
5107 T (Tag_ARC_ABI_osver),
5108 T (Tag_ARC_ABI_sda),
5109 T (Tag_ARC_ABI_pic),
5110 T (Tag_ARC_ABI_tls),
5111 T (Tag_ARC_ABI_enumsize),
5112 T (Tag_ARC_ABI_exceptions),
5113 T (Tag_ARC_ABI_double_size),
5114 T (Tag_ARC_ISA_config),
5115 T (Tag_ARC_ISA_apex),
db1e1b45 5116 T (Tag_ARC_ISA_mpy_option),
5117 T (Tag_ARC_ATR_version)
53a346d8
CZ		 5118#undef T
5119 };
5120 unsigned int i;
5121
5122 if (name == NULL)
5123 return -1;
5124
5125 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5126 if (streq (name, attribute_table[i].name))
5127 return attribute_table[i].tag;
5128
5129 return -1;
5130}
5131
b99747ae
CZ		 5132/* Local variables:
5133 eval: (c-set-style "gnu")
5134 indent-tabs-mode: t
5135 End: */
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