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1 | /* tc-arm.c -- Assemble for the ARM |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 | |
3 | Free Software Foundation, Inc. | |
4 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
5 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
6 | ||
7 | This file is part of GAS, the GNU Assembler. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GAS; see the file COPYING. If not, write to the Free | |
21 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | 02111-1307, USA. */ | |
23 | ||
24 | #include <ctype.h> | |
25 | #include <string.h> | |
26 | #define NO_RELOC 0 | |
27 | #include "as.h" | |
28 | ||
29 | /* Need TARGET_CPU. */ | |
30 | #include "config.h" | |
31 | #include "subsegs.h" | |
32 | #include "obstack.h" | |
33 | #include "symbols.h" | |
34 | #include "listing.h" | |
35 | ||
36 | #ifdef OBJ_ELF | |
37 | #include "elf/arm.h" | |
38 | #include "dwarf2dbg.h" | |
39 | #endif | |
40 | ||
41 | /* Types of processor to assemble for. */ | |
42 | #define ARM_1 0x00000001 | |
43 | #define ARM_2 0x00000002 | |
44 | #define ARM_3 0x00000004 | |
45 | #define ARM_250 ARM_3 | |
46 | #define ARM_6 0x00000008 | |
47 | #define ARM_7 ARM_6 /* Same core instruction set. */ | |
48 | #define ARM_8 ARM_6 /* Same core instruction set. */ | |
49 | #define ARM_9 ARM_6 /* Same core instruction set. */ | |
50 | #define ARM_CPU_MASK 0x0000000f | |
51 | ||
52 | /* The following bitmasks control CPU extensions (ARM7 onwards): */ | |
53 | #define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */ | |
54 | #define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */ | |
55 | #define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */ | |
56 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ | |
57 | #define ARM_EXT_V5E 0x00000100 /* "El Segundo". */ | |
58 | #define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */ | |
59 | ||
60 | /* Architectures are the sum of the base and extensions. */ | |
61 | #define ARM_ARCH_V3M ARM_EXT_LONGMUL | |
62 | #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD) | |
63 | #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB) | |
64 | #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5) | |
65 | #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB) | |
66 | #define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E) | |
67 | #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE) | |
68 | ||
69 | /* Some useful combinations: */ | |
70 | #define ARM_ANY 0x00ffffff | |
71 | #define ARM_2UP (ARM_ANY - ARM_1) | |
72 | #define ARM_ALL ARM_2UP /* Not arm1 only. */ | |
73 | #define ARM_3UP 0x00fffffc | |
74 | #define ARM_6UP 0x00fffff8 /* Includes ARM7. */ | |
75 | ||
76 | #define FPU_CORE 0x80000000 | |
77 | #define FPU_FPA10 0x40000000 | |
78 | #define FPU_FPA11 0x40000000 | |
79 | #define FPU_NONE 0 | |
80 | ||
81 | /* Some useful combinations. */ | |
82 | #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */ | |
83 | #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */ | |
84 | ||
85 | #ifndef CPU_DEFAULT | |
86 | #if defined __XSCALE__ | |
87 | #define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE) | |
88 | #else | |
89 | #if defined __thumb__ | |
90 | #define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T) | |
91 | #else | |
92 | #define CPU_DEFAULT ARM_ALL | |
93 | #endif | |
94 | #endif | |
95 | #endif | |
96 | ||
97 | #ifndef FPU_DEFAULT | |
98 | #define FPU_DEFAULT FPU_ALL | |
99 | #endif | |
100 | ||
101 | #define streq(a, b) (strcmp (a, b) == 0) | |
102 | #define skip_whitespace(str) while (*(str) == ' ') ++(str) | |
103 | ||
104 | static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT; | |
105 | static int target_oabi = 0; | |
106 | ||
107 | #if defined OBJ_COFF || defined OBJ_ELF | |
108 | /* Flags stored in private area of BFD structure. */ | |
109 | static boolean uses_apcs_26 = false; | |
110 | static boolean atpcs = false; | |
111 | static boolean support_interwork = false; | |
112 | static boolean uses_apcs_float = false; | |
113 | static boolean pic_code = false; | |
114 | #endif | |
115 | ||
116 | /* This array holds the chars that always start a comment. If the | |
117 | pre-processor is disabled, these aren't very useful. */ | |
118 | CONST char comment_chars[] = "@"; | |
119 | ||
120 | /* This array holds the chars that only start a comment at the beginning of | |
121 | a line. If the line seems to have the form '# 123 filename' | |
122 | .line and .file directives will appear in the pre-processed output. */ | |
123 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
124 | first line of the input file. This is because the compiler outputs | |
125 | #NO_APP at the beginning of its output. */ | |
126 | /* Also note that comments like this one will always work. */ | |
127 | CONST char line_comment_chars[] = "#"; | |
128 | ||
129 | CONST char line_separator_chars[] = ";"; | |
130 | ||
131 | /* Chars that can be used to separate mant | |
132 | from exp in floating point numbers. */ | |
133 | CONST char EXP_CHARS[] = "eE"; | |
134 | ||
135 | /* Chars that mean this number is a floating point constant. */ | |
136 | /* As in 0f12.456 */ | |
137 | /* or 0d1.2345e12 */ | |
138 | ||
139 | CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP"; | |
140 | ||
141 | /* Prefix characters that indicate the start of an immediate | |
142 | value. */ | |
143 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
144 | ||
145 | #ifdef OBJ_ELF | |
146 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ | |
147 | symbolS * GOT_symbol; | |
148 | #endif | |
149 | ||
150 | /* Size of relocation record. */ | |
151 | CONST int md_reloc_size = 8; | |
152 | ||
153 | /* 0: assemble for ARM, | |
154 | 1: assemble for Thumb, | |
155 | 2: assemble for Thumb even though target CPU does not support thumb | |
156 | instructions. */ | |
157 | static int thumb_mode = 0; | |
158 | ||
159 | typedef struct arm_fix | |
160 | { | |
161 | int thumb_mode; | |
162 | } arm_fix_data; | |
163 | ||
164 | struct arm_it | |
165 | { | |
166 | CONST char * error; | |
167 | unsigned long instruction; | |
168 | int suffix; | |
169 | int size; | |
170 | struct | |
171 | { | |
172 | bfd_reloc_code_real_type type; | |
173 | expressionS exp; | |
174 | int pc_rel; | |
175 | } reloc; | |
176 | }; | |
177 | ||
178 | struct arm_it inst; | |
179 | ||
180 | enum asm_shift_index | |
181 | { | |
182 | SHIFT_LSL = 0, | |
183 | SHIFT_LSR, | |
184 | SHIFT_ASR, | |
185 | SHIFT_ROR, | |
186 | SHIFT_RRX | |
187 | }; | |
188 | ||
189 | struct asm_shift_properties | |
190 | { | |
191 | enum asm_shift_index index; | |
192 | unsigned long bit_field; | |
193 | unsigned int allows_0 : 1; | |
194 | unsigned int allows_32 : 1; | |
195 | }; | |
196 | ||
197 | static const struct asm_shift_properties shift_properties [] = | |
198 | { | |
199 | { SHIFT_LSL, 0, 1, 0}, | |
200 | { SHIFT_LSR, 0x20, 0, 1}, | |
201 | { SHIFT_ASR, 0x40, 0, 1}, | |
202 | { SHIFT_ROR, 0x60, 0, 0}, | |
203 | { SHIFT_RRX, 0x60, 0, 0} | |
204 | }; | |
205 | ||
206 | struct asm_shift_name | |
207 | { | |
208 | const char * name; | |
209 | const struct asm_shift_properties * properties; | |
210 | }; | |
211 | ||
212 | static const struct asm_shift_name shift_names [] = | |
213 | { | |
214 | { "asl", shift_properties + SHIFT_LSL }, | |
215 | { "lsl", shift_properties + SHIFT_LSL }, | |
216 | { "lsr", shift_properties + SHIFT_LSR }, | |
217 | { "asr", shift_properties + SHIFT_ASR }, | |
218 | { "ror", shift_properties + SHIFT_ROR }, | |
219 | { "rrx", shift_properties + SHIFT_RRX }, | |
220 | { "ASL", shift_properties + SHIFT_LSL }, | |
221 | { "LSL", shift_properties + SHIFT_LSL }, | |
222 | { "LSR", shift_properties + SHIFT_LSR }, | |
223 | { "ASR", shift_properties + SHIFT_ASR }, | |
224 | { "ROR", shift_properties + SHIFT_ROR }, | |
225 | { "RRX", shift_properties + SHIFT_RRX } | |
226 | }; | |
227 | ||
228 | #define NO_SHIFT_RESTRICT 1 | |
229 | #define SHIFT_RESTRICT 0 | |
230 | ||
231 | #define NUM_FLOAT_VALS 8 | |
232 | ||
233 | CONST char * fp_const[] = | |
234 | { | |
235 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
236 | }; | |
237 | ||
238 | /* Number of littlenums required to hold an extended precision number. */ | |
239 | #define MAX_LITTLENUMS 6 | |
240 | ||
241 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
242 | ||
243 | #define FAIL (-1) | |
244 | #define SUCCESS (0) | |
245 | ||
246 | #define SUFF_S 1 | |
247 | #define SUFF_D 2 | |
248 | #define SUFF_E 3 | |
249 | #define SUFF_P 4 | |
250 | ||
251 | #define CP_T_X 0x00008000 | |
252 | #define CP_T_Y 0x00400000 | |
253 | #define CP_T_Pre 0x01000000 | |
254 | #define CP_T_UD 0x00800000 | |
255 | #define CP_T_WB 0x00200000 | |
256 | ||
257 | #define CONDS_BIT 0x00100000 | |
258 | #define LOAD_BIT 0x00100000 | |
259 | #define TRANS_BIT 0x00200000 | |
260 | ||
261 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
262 | ||
263 | struct asm_cond | |
264 | { | |
265 | CONST char * template; | |
266 | unsigned long value; | |
267 | }; | |
268 | ||
269 | /* This is to save a hash look-up in the common case. */ | |
270 | #define COND_ALWAYS 0xe0000000 | |
271 | ||
272 | static CONST struct asm_cond conds[] = | |
273 | { | |
274 | {"eq", 0x00000000}, | |
275 | {"ne", 0x10000000}, | |
276 | {"cs", 0x20000000}, {"hs", 0x20000000}, | |
277 | {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000}, | |
278 | {"mi", 0x40000000}, | |
279 | {"pl", 0x50000000}, | |
280 | {"vs", 0x60000000}, | |
281 | {"vc", 0x70000000}, | |
282 | {"hi", 0x80000000}, | |
283 | {"ls", 0x90000000}, | |
284 | {"ge", 0xa0000000}, | |
285 | {"lt", 0xb0000000}, | |
286 | {"gt", 0xc0000000}, | |
287 | {"le", 0xd0000000}, | |
288 | {"al", 0xe0000000}, | |
289 | {"nv", 0xf0000000} | |
290 | }; | |
291 | ||
292 | /* Warning: If the top bit of the set_bits is set, then the standard | |
293 | instruction bitmask is ignored, and the new bitmask is taken from | |
294 | the set_bits: */ | |
295 | struct asm_flg | |
296 | { | |
297 | CONST char * template; /* Basic flag string. */ | |
298 | unsigned long set_bits; /* Bits to set. */ | |
299 | }; | |
300 | ||
301 | static CONST struct asm_flg s_flag[] = | |
302 | { | |
303 | {"s", CONDS_BIT}, | |
304 | {NULL, 0} | |
305 | }; | |
306 | ||
307 | static CONST struct asm_flg ldr_flags[] = | |
308 | { | |
309 | {"d", DOUBLE_LOAD_FLAG}, | |
310 | {"b", 0x00400000}, | |
311 | {"t", TRANS_BIT}, | |
312 | {"bt", 0x00400000 | TRANS_BIT}, | |
313 | {"h", 0x801000b0}, | |
314 | {"sh", 0x801000f0}, | |
315 | {"sb", 0x801000d0}, | |
316 | {NULL, 0} | |
317 | }; | |
318 | ||
319 | static CONST struct asm_flg str_flags[] = | |
320 | { | |
321 | {"d", DOUBLE_LOAD_FLAG}, | |
322 | {"b", 0x00400000}, | |
323 | {"t", TRANS_BIT}, | |
324 | {"bt", 0x00400000 | TRANS_BIT}, | |
325 | {"h", 0x800000b0}, | |
326 | {NULL, 0} | |
327 | }; | |
328 | ||
329 | static CONST struct asm_flg byte_flag[] = | |
330 | { | |
331 | {"b", 0x00400000}, | |
332 | {NULL, 0} | |
333 | }; | |
334 | ||
335 | static CONST struct asm_flg cmp_flags[] = | |
336 | { | |
337 | {"s", CONDS_BIT}, | |
338 | {"p", 0x0010f000}, | |
339 | {NULL, 0} | |
340 | }; | |
341 | ||
342 | static CONST struct asm_flg ldm_flags[] = | |
343 | { | |
344 | {"ed", 0x01800000}, | |
345 | {"fd", 0x00800000}, | |
346 | {"ea", 0x01000000}, | |
347 | {"fa", 0x00000000}, | |
348 | {"ib", 0x01800000}, | |
349 | {"ia", 0x00800000}, | |
350 | {"db", 0x01000000}, | |
351 | {"da", 0x00000000}, | |
352 | {NULL, 0} | |
353 | }; | |
354 | ||
355 | static CONST struct asm_flg stm_flags[] = | |
356 | { | |
357 | {"ed", 0x00000000}, | |
358 | {"fd", 0x01000000}, | |
359 | {"ea", 0x00800000}, | |
360 | {"fa", 0x01800000}, | |
361 | {"ib", 0x01800000}, | |
362 | {"ia", 0x00800000}, | |
363 | {"db", 0x01000000}, | |
364 | {"da", 0x00000000}, | |
365 | {NULL, 0} | |
366 | }; | |
367 | ||
368 | static CONST struct asm_flg lfm_flags[] = | |
369 | { | |
370 | {"fd", 0x00800000}, | |
371 | {"ea", 0x01000000}, | |
372 | {NULL, 0} | |
373 | }; | |
374 | ||
375 | static CONST struct asm_flg sfm_flags[] = | |
376 | { | |
377 | {"fd", 0x01000000}, | |
378 | {"ea", 0x00800000}, | |
379 | {NULL, 0} | |
380 | }; | |
381 | ||
382 | static CONST struct asm_flg round_flags[] = | |
383 | { | |
384 | {"p", 0x00000020}, | |
385 | {"m", 0x00000040}, | |
386 | {"z", 0x00000060}, | |
387 | {NULL, 0} | |
388 | }; | |
389 | ||
390 | /* The implementation of the FIX instruction is broken on some assemblers, | |
391 | in that it accepts a precision specifier as well as a rounding specifier, | |
392 | despite the fact that this is meaningless. To be more compatible, we | |
393 | accept it as well, though of course it does not set any bits. */ | |
394 | static CONST struct asm_flg fix_flags[] = | |
395 | { | |
396 | {"p", 0x00000020}, | |
397 | {"m", 0x00000040}, | |
398 | {"z", 0x00000060}, | |
399 | {"sp", 0x00000020}, | |
400 | {"sm", 0x00000040}, | |
401 | {"sz", 0x00000060}, | |
402 | {"dp", 0x00000020}, | |
403 | {"dm", 0x00000040}, | |
404 | {"dz", 0x00000060}, | |
405 | {"ep", 0x00000020}, | |
406 | {"em", 0x00000040}, | |
407 | {"ez", 0x00000060}, | |
408 | {NULL, 0} | |
409 | }; | |
410 | ||
411 | static CONST struct asm_flg except_flag[] = | |
412 | { | |
413 | {"e", 0x00400000}, | |
414 | {NULL, 0} | |
415 | }; | |
416 | ||
1cac9012 | 417 | static CONST struct asm_flg long_flag[] = |
b99bd4ef NC |
418 | { |
419 | {"l", 0x00400000}, | |
420 | {NULL, 0} | |
421 | }; | |
422 | ||
423 | struct asm_psr | |
424 | { | |
425 | CONST char * template; | |
426 | boolean cpsr; | |
427 | unsigned long field; | |
428 | }; | |
429 | ||
430 | /* The bit that distnguishes CPSR and SPSR. */ | |
431 | #define SPSR_BIT (1 << 22) | |
432 | ||
433 | /* How many bits to shift the PSR_xxx bits up by. */ | |
434 | #define PSR_SHIFT 16 | |
435 | ||
436 | #define PSR_c (1 << 0) | |
437 | #define PSR_x (1 << 1) | |
438 | #define PSR_s (1 << 2) | |
439 | #define PSR_f (1 << 3) | |
440 | ||
441 | static CONST struct asm_psr psrs[] = | |
442 | { | |
443 | {"CPSR", true, PSR_c | PSR_f}, | |
444 | {"CPSR_all", true, PSR_c | PSR_f}, | |
445 | {"SPSR", false, PSR_c | PSR_f}, | |
446 | {"SPSR_all", false, PSR_c | PSR_f}, | |
447 | {"CPSR_flg", true, PSR_f}, | |
448 | {"CPSR_f", true, PSR_f}, | |
449 | {"SPSR_flg", false, PSR_f}, | |
450 | {"SPSR_f", false, PSR_f}, | |
451 | {"CPSR_c", true, PSR_c}, | |
452 | {"CPSR_ctl", true, PSR_c}, | |
453 | {"SPSR_c", false, PSR_c}, | |
454 | {"SPSR_ctl", false, PSR_c}, | |
455 | {"CPSR_x", true, PSR_x}, | |
456 | {"CPSR_s", true, PSR_s}, | |
457 | {"SPSR_x", false, PSR_x}, | |
458 | {"SPSR_s", false, PSR_s}, | |
459 | /* Combinations of flags. */ | |
460 | {"CPSR_fs", true, PSR_f | PSR_s}, | |
461 | {"CPSR_fx", true, PSR_f | PSR_x}, | |
462 | {"CPSR_fc", true, PSR_f | PSR_c}, | |
463 | {"CPSR_sf", true, PSR_s | PSR_f}, | |
464 | {"CPSR_sx", true, PSR_s | PSR_x}, | |
465 | {"CPSR_sc", true, PSR_s | PSR_c}, | |
466 | {"CPSR_xf", true, PSR_x | PSR_f}, | |
467 | {"CPSR_xs", true, PSR_x | PSR_s}, | |
468 | {"CPSR_xc", true, PSR_x | PSR_c}, | |
469 | {"CPSR_cf", true, PSR_c | PSR_f}, | |
470 | {"CPSR_cs", true, PSR_c | PSR_s}, | |
471 | {"CPSR_cx", true, PSR_c | PSR_x}, | |
472 | {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x}, | |
473 | {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c}, | |
474 | {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s}, | |
475 | {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c}, | |
476 | {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s}, | |
477 | {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x}, | |
478 | {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x}, | |
479 | {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c}, | |
480 | {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f}, | |
481 | {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c}, | |
482 | {"CPSR_scf", true, PSR_s | PSR_c | PSR_f}, | |
483 | {"CPSR_scx", true, PSR_s | PSR_c | PSR_x}, | |
484 | {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s}, | |
485 | {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c}, | |
486 | {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f}, | |
487 | {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c}, | |
488 | {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f}, | |
489 | {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s}, | |
490 | {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s}, | |
491 | {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x}, | |
492 | {"CPSR_csf", true, PSR_c | PSR_s | PSR_f}, | |
493 | {"CPSR_csx", true, PSR_c | PSR_s | PSR_x}, | |
494 | {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f}, | |
495 | {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s}, | |
496 | {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c}, | |
497 | {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x}, | |
498 | {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c}, | |
499 | {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s}, | |
500 | {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x}, | |
501 | {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s}, | |
502 | {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c}, | |
503 | {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x}, | |
504 | {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c}, | |
505 | {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f}, | |
506 | {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x}, | |
507 | {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f}, | |
508 | {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c}, | |
509 | {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s}, | |
510 | {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c}, | |
511 | {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f}, | |
512 | {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s}, | |
513 | {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f}, | |
514 | {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x}, | |
515 | {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s}, | |
516 | {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x}, | |
517 | {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f}, | |
518 | {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s}, | |
519 | {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f}, | |
520 | {"SPSR_fs", false, PSR_f | PSR_s}, | |
521 | {"SPSR_fx", false, PSR_f | PSR_x}, | |
522 | {"SPSR_fc", false, PSR_f | PSR_c}, | |
523 | {"SPSR_sf", false, PSR_s | PSR_f}, | |
524 | {"SPSR_sx", false, PSR_s | PSR_x}, | |
525 | {"SPSR_sc", false, PSR_s | PSR_c}, | |
526 | {"SPSR_xf", false, PSR_x | PSR_f}, | |
527 | {"SPSR_xs", false, PSR_x | PSR_s}, | |
528 | {"SPSR_xc", false, PSR_x | PSR_c}, | |
529 | {"SPSR_cf", false, PSR_c | PSR_f}, | |
530 | {"SPSR_cs", false, PSR_c | PSR_s}, | |
531 | {"SPSR_cx", false, PSR_c | PSR_x}, | |
532 | {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x}, | |
533 | {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c}, | |
534 | {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s}, | |
535 | {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c}, | |
536 | {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s}, | |
537 | {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x}, | |
538 | {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x}, | |
539 | {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c}, | |
540 | {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f}, | |
541 | {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c}, | |
542 | {"SPSR_scf", false, PSR_s | PSR_c | PSR_f}, | |
543 | {"SPSR_scx", false, PSR_s | PSR_c | PSR_x}, | |
544 | {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s}, | |
545 | {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c}, | |
546 | {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f}, | |
547 | {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c}, | |
548 | {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f}, | |
549 | {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s}, | |
550 | {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s}, | |
551 | {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x}, | |
552 | {"SPSR_csf", false, PSR_c | PSR_s | PSR_f}, | |
553 | {"SPSR_csx", false, PSR_c | PSR_s | PSR_x}, | |
554 | {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f}, | |
555 | {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s}, | |
556 | {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c}, | |
557 | {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x}, | |
558 | {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c}, | |
559 | {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s}, | |
560 | {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x}, | |
561 | {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s}, | |
562 | {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c}, | |
563 | {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x}, | |
564 | {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c}, | |
565 | {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f}, | |
566 | {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x}, | |
567 | {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f}, | |
568 | {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c}, | |
569 | {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s}, | |
570 | {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c}, | |
571 | {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f}, | |
572 | {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s}, | |
573 | {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f}, | |
574 | {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x}, | |
575 | {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s}, | |
576 | {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x}, | |
577 | {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f}, | |
578 | {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s}, | |
579 | {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f}, | |
580 | }; | |
581 | ||
582 | /* Functions called by parser. */ | |
583 | /* ARM instructions. */ | |
584 | static void do_arit PARAMS ((char *, unsigned long)); | |
585 | static void do_cmp PARAMS ((char *, unsigned long)); | |
586 | static void do_mov PARAMS ((char *, unsigned long)); | |
587 | static void do_ldst PARAMS ((char *, unsigned long)); | |
588 | static void do_ldmstm PARAMS ((char *, unsigned long)); | |
589 | static void do_branch PARAMS ((char *, unsigned long)); | |
590 | static void do_swi PARAMS ((char *, unsigned long)); | |
591 | /* Pseudo Op codes. */ | |
592 | static void do_adr PARAMS ((char *, unsigned long)); | |
593 | static void do_adrl PARAMS ((char *, unsigned long)); | |
594 | static void do_nop PARAMS ((char *, unsigned long)); | |
595 | /* ARM 2. */ | |
596 | static void do_mul PARAMS ((char *, unsigned long)); | |
597 | static void do_mla PARAMS ((char *, unsigned long)); | |
598 | /* ARM 3. */ | |
599 | static void do_swap PARAMS ((char *, unsigned long)); | |
600 | /* ARM 6. */ | |
601 | static void do_msr PARAMS ((char *, unsigned long)); | |
602 | static void do_mrs PARAMS ((char *, unsigned long)); | |
603 | /* ARM 7M. */ | |
604 | static void do_mull PARAMS ((char *, unsigned long)); | |
605 | /* ARM THUMB. */ | |
606 | static void do_bx PARAMS ((char *, unsigned long)); | |
607 | ||
608 | /* ARM_EXT_XScale. */ | |
609 | static void do_mia PARAMS ((char *, unsigned long)); | |
610 | static void do_mar PARAMS ((char *, unsigned long)); | |
611 | static void do_mra PARAMS ((char *, unsigned long)); | |
612 | static void do_pld PARAMS ((char *, unsigned long)); | |
613 | static void do_ldrd PARAMS ((char *, unsigned long)); | |
614 | ||
615 | /* ARM_EXT_V5. */ | |
616 | static void do_blx PARAMS ((char *, unsigned long)); | |
617 | static void do_bkpt PARAMS ((char *, unsigned long)); | |
618 | static void do_clz PARAMS ((char *, unsigned long)); | |
619 | static void do_lstc2 PARAMS ((char *, unsigned long)); | |
620 | static void do_cdp2 PARAMS ((char *, unsigned long)); | |
621 | static void do_co_reg2 PARAMS ((char *, unsigned long)); | |
622 | ||
623 | static void do_t_blx PARAMS ((char *)); | |
624 | static void do_t_bkpt PARAMS ((char *)); | |
625 | ||
626 | /* ARM_EXT_V5E. */ | |
627 | static void do_smla PARAMS ((char *, unsigned long)); | |
628 | static void do_smlal PARAMS ((char *, unsigned long)); | |
629 | static void do_smul PARAMS ((char *, unsigned long)); | |
630 | static void do_qadd PARAMS ((char *, unsigned long)); | |
631 | static void do_co_reg2c PARAMS ((char *, unsigned long)); | |
632 | ||
633 | /* Coprocessor Instructions. */ | |
634 | static void do_cdp PARAMS ((char *, unsigned long)); | |
635 | static void do_lstc PARAMS ((char *, unsigned long)); | |
636 | static void do_co_reg PARAMS ((char *, unsigned long)); | |
637 | static void do_fp_ctrl PARAMS ((char *, unsigned long)); | |
638 | static void do_fp_ldst PARAMS ((char *, unsigned long)); | |
639 | static void do_fp_ldmstm PARAMS ((char *, unsigned long)); | |
640 | static void do_fp_dyadic PARAMS ((char *, unsigned long)); | |
641 | static void do_fp_monadic PARAMS ((char *, unsigned long)); | |
642 | static void do_fp_cmp PARAMS ((char *, unsigned long)); | |
643 | static void do_fp_from_reg PARAMS ((char *, unsigned long)); | |
644 | static void do_fp_to_reg PARAMS ((char *, unsigned long)); | |
645 | ||
646 | static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int)); | |
647 | static int arm_reg_parse PARAMS ((char **)); | |
648 | static CONST struct asm_psr * arm_psr_parse PARAMS ((char **)); | |
649 | static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *)); | |
650 | static int add_to_lit_pool PARAMS ((void)); | |
651 | static unsigned validate_immediate PARAMS ((unsigned)); | |
652 | static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *)); | |
653 | static int validate_offset_imm PARAMS ((unsigned int, int)); | |
654 | static void opcode_select PARAMS ((int)); | |
655 | static void end_of_line PARAMS ((char *)); | |
656 | static int reg_required_here PARAMS ((char **, int)); | |
657 | static int psr_required_here PARAMS ((char **)); | |
658 | static int co_proc_number PARAMS ((char **)); | |
659 | static int cp_opc_expr PARAMS ((char **, int, int)); | |
660 | static int cp_reg_required_here PARAMS ((char **, int)); | |
661 | static int fp_reg_required_here PARAMS ((char **, int)); | |
662 | static int cp_address_offset PARAMS ((char **)); | |
663 | static int cp_address_required_here PARAMS ((char **)); | |
664 | static int my_get_float_expression PARAMS ((char **)); | |
665 | static int skip_past_comma PARAMS ((char **)); | |
666 | static int walk_no_bignums PARAMS ((symbolS *)); | |
667 | static int negate_data_op PARAMS ((unsigned long *, unsigned long)); | |
668 | static int data_op2 PARAMS ((char **)); | |
669 | static int fp_op2 PARAMS ((char **)); | |
670 | static long reg_list PARAMS ((char **)); | |
671 | static void thumb_load_store PARAMS ((char *, int, int)); | |
672 | static int decode_shift PARAMS ((char **, int)); | |
673 | static int ldst_extend PARAMS ((char **, int)); | |
674 | static void thumb_add_sub PARAMS ((char *, int)); | |
675 | static void insert_reg PARAMS ((int)); | |
676 | static void thumb_shift PARAMS ((char *, int)); | |
677 | static void thumb_mov_compare PARAMS ((char *, int)); | |
678 | static void set_constant_flonums PARAMS ((void)); | |
679 | static valueT md_chars_to_number PARAMS ((char *, int)); | |
680 | static void insert_reg_alias PARAMS ((char *, int)); | |
681 | static void output_inst PARAMS ((void)); | |
682 | #ifdef OBJ_ELF | |
683 | static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void)); | |
684 | #endif | |
685 | ||
686 | /* ARM instructions take 4bytes in the object file, Thumb instructions | |
687 | take 2: */ | |
688 | #define INSN_SIZE 4 | |
689 | ||
690 | /* LONGEST_INST is the longest basic instruction name without | |
691 | conditions or flags. ARM7M has 4 of length 5. El Segundo | |
692 | has one basic instruction name of length 7 (SMLALxy). */ | |
693 | #define LONGEST_INST 7 | |
694 | ||
695 | struct asm_opcode | |
696 | { | |
697 | /* Basic string to match. */ | |
698 | CONST char * template; | |
699 | ||
700 | /* Basic instruction code. */ | |
701 | unsigned long value; | |
702 | ||
703 | /* Compulsory suffix that must follow conds. If "", then the | |
704 | instruction is not conditional and must have no suffix. */ | |
705 | CONST char * comp_suffix; | |
706 | ||
707 | /* Bits to toggle if flag 'n' set. */ | |
708 | CONST struct asm_flg * flags; | |
709 | ||
710 | /* Which CPU variants this exists for. */ | |
711 | unsigned long variants; | |
712 | ||
713 | /* Function to call to parse args. */ | |
714 | void (* parms) PARAMS ((char *, unsigned long)); | |
715 | }; | |
716 | ||
717 | static CONST struct asm_opcode insns[] = | |
718 | { | |
719 | /* Intel XScale extensions to ARM V5 ISA. */ | |
720 | {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
721 | {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
722 | {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
723 | {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
724 | {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
725 | {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, | |
726 | {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar}, | |
727 | {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra}, | |
728 | {"pld", 0xf450f000, "", NULL, ARM_EXT_XSCALE, do_pld}, | |
729 | {"ldr", 0x000000d0, NULL, ldr_flags, ARM_ANY, do_ldrd}, | |
730 | {"str", 0x000000f0, NULL, str_flags, ARM_ANY, do_ldrd}, | |
731 | ||
732 | /* ARM Instructions. */ | |
733 | {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit}, | |
734 | {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit}, | |
735 | {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit}, | |
736 | {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit}, | |
737 | {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit}, | |
738 | {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit}, | |
739 | {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit}, | |
740 | {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit}, | |
741 | {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit}, | |
742 | {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit}, | |
743 | {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp}, | |
744 | {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp}, | |
745 | {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp}, | |
746 | {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp}, | |
747 | {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov}, | |
748 | {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov}, | |
749 | {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst}, | |
750 | {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst}, | |
751 | {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm}, | |
752 | {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm}, | |
753 | {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi}, | |
754 | #ifdef TE_WINCE | |
755 | {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch}, | |
756 | {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch}, | |
757 | #else | |
758 | {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch}, | |
759 | {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch}, | |
760 | #endif | |
761 | ||
762 | /* Pseudo ops. */ | |
1cac9012 | 763 | {"adr", 0x028f0000, NULL, long_flag, ARM_ANY, do_adr}, |
b99bd4ef NC |
764 | {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop}, |
765 | ||
766 | /* ARM 2 multiplies. */ | |
767 | {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul}, | |
768 | {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla}, | |
769 | ||
770 | /* ARM 3 - swp instructions. */ | |
771 | {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap}, | |
772 | ||
773 | /* ARM 6 Coprocessor instructions. */ | |
774 | {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs}, | |
775 | {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr}, | |
776 | /* ScottB: our code uses 0x0128f000 for msr. | |
777 | NickC: but this is wrong because the bits 16 through 19 are | |
778 | handled by the PSR_xxx defines above. */ | |
779 | ||
780 | /* ARM 7M long multiplies - need signed/unsigned flags! */ | |
781 | {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull}, | |
782 | {"umull", 0x00800090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull}, | |
783 | {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull}, | |
784 | {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull}, | |
785 | ||
786 | /* ARM THUMB interworking. */ | |
787 | {"bx", 0x012fff10, NULL, NULL, ARM_EXT_THUMB, do_bx}, | |
788 | ||
789 | /* Floating point instructions. */ | |
790 | {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl}, | |
791 | {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl}, | |
792 | {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl}, | |
793 | {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl}, | |
794 | {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst}, | |
795 | {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst}, | |
796 | {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm}, | |
797 | {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm}, | |
798 | {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
799 | {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
800 | {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
801 | {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
802 | {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
803 | {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
804 | {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
805 | {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
806 | {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
807 | {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
808 | {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
809 | {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
810 | {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
811 | {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
812 | {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
813 | {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, | |
814 | {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
815 | {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
816 | {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
817 | {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
818 | {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
819 | {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
820 | {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
821 | {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
822 | {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
823 | {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
824 | {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
825 | {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
826 | {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, | |
827 | {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp}, | |
828 | {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp}, | |
829 | /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not | |
830 | be an optional suffix, but part of the instruction. To be compatible, | |
831 | we accept either. */ | |
832 | {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp}, | |
833 | {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp}, | |
834 | {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg}, | |
835 | {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg}, | |
836 | ||
837 | /* Generic copressor instructions. */ | |
838 | {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp}, | |
1cac9012 NC |
839 | {"ldc", 0x0c100000, NULL, long_flag, ARM_2UP, do_lstc}, |
840 | {"stc", 0x0c000000, NULL, long_flag, ARM_2UP, do_lstc}, | |
b99bd4ef NC |
841 | {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg}, |
842 | {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg}, | |
843 | ||
844 | /* ARM ISA extension 5. */ | |
845 | /* Note: blx is actually 2 opcodes, so the .value is set dynamically. | |
846 | And it's sometimes conditional and sometimes not. */ | |
847 | {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx}, | |
848 | {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz}, | |
849 | {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt}, | |
1cac9012 NC |
850 | {"ldc2", 0xfc100000, "", long_flag, ARM_EXT_V5, do_lstc2}, |
851 | {"stc2", 0xfc000000, "", long_flag, ARM_EXT_V5, do_lstc2}, | |
b99bd4ef NC |
852 | {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2}, |
853 | {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2}, | |
854 | {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2}, | |
855 | ||
856 | /* ARM ISA extension 5E, El Segundo. */ | |
857 | {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5E, do_smla}, | |
858 | {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5E, do_smla}, | |
859 | {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5E, do_smla}, | |
860 | {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5E, do_smla}, | |
861 | ||
862 | {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5E, do_smla}, | |
863 | {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5E, do_smla}, | |
864 | ||
865 | {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5E, do_smlal}, | |
866 | {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5E, do_smlal}, | |
867 | {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5E, do_smlal}, | |
868 | {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5E, do_smlal}, | |
869 | ||
870 | {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5E, do_smul}, | |
871 | {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5E, do_smul}, | |
872 | {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5E, do_smul}, | |
873 | {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5E, do_smul}, | |
874 | ||
875 | {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5E, do_smul}, | |
876 | {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5E, do_smul}, | |
877 | ||
878 | {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5E, do_qadd}, | |
879 | {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5E, do_qadd}, | |
880 | {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5E, do_qadd}, | |
881 | {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5E, do_qadd}, | |
882 | ||
883 | {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c}, | |
884 | {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c}, | |
885 | }; | |
886 | ||
887 | /* Defines for various bits that we will want to toggle. */ | |
888 | #define INST_IMMEDIATE 0x02000000 | |
889 | #define OFFSET_REG 0x02000000 | |
890 | #define HWOFFSET_IMM 0x00400000 | |
891 | #define SHIFT_BY_REG 0x00000010 | |
892 | #define PRE_INDEX 0x01000000 | |
893 | #define INDEX_UP 0x00800000 | |
894 | #define WRITE_BACK 0x00200000 | |
895 | #define LDM_TYPE_2_OR_3 0x00400000 | |
896 | ||
897 | #define LITERAL_MASK 0xf000f000 | |
898 | #define COND_MASK 0xf0000000 | |
899 | #define OPCODE_MASK 0xfe1fffff | |
900 | #define DATA_OP_SHIFT 21 | |
901 | ||
902 | /* Codes to distinguish the arithmetic instructions. */ | |
903 | #define OPCODE_AND 0 | |
904 | #define OPCODE_EOR 1 | |
905 | #define OPCODE_SUB 2 | |
906 | #define OPCODE_RSB 3 | |
907 | #define OPCODE_ADD 4 | |
908 | #define OPCODE_ADC 5 | |
909 | #define OPCODE_SBC 6 | |
910 | #define OPCODE_RSC 7 | |
911 | #define OPCODE_TST 8 | |
912 | #define OPCODE_TEQ 9 | |
913 | #define OPCODE_CMP 10 | |
914 | #define OPCODE_CMN 11 | |
915 | #define OPCODE_ORR 12 | |
916 | #define OPCODE_MOV 13 | |
917 | #define OPCODE_BIC 14 | |
918 | #define OPCODE_MVN 15 | |
919 | ||
920 | static void do_t_nop PARAMS ((char *)); | |
921 | static void do_t_arit PARAMS ((char *)); | |
922 | static void do_t_add PARAMS ((char *)); | |
923 | static void do_t_asr PARAMS ((char *)); | |
924 | static void do_t_branch9 PARAMS ((char *)); | |
925 | static void do_t_branch12 PARAMS ((char *)); | |
926 | static void do_t_branch23 PARAMS ((char *)); | |
927 | static void do_t_bx PARAMS ((char *)); | |
928 | static void do_t_compare PARAMS ((char *)); | |
929 | static void do_t_ldmstm PARAMS ((char *)); | |
930 | static void do_t_ldr PARAMS ((char *)); | |
931 | static void do_t_ldrb PARAMS ((char *)); | |
932 | static void do_t_ldrh PARAMS ((char *)); | |
933 | static void do_t_lds PARAMS ((char *)); | |
934 | static void do_t_lsl PARAMS ((char *)); | |
935 | static void do_t_lsr PARAMS ((char *)); | |
936 | static void do_t_mov PARAMS ((char *)); | |
937 | static void do_t_push_pop PARAMS ((char *)); | |
938 | static void do_t_str PARAMS ((char *)); | |
939 | static void do_t_strb PARAMS ((char *)); | |
940 | static void do_t_strh PARAMS ((char *)); | |
941 | static void do_t_sub PARAMS ((char *)); | |
942 | static void do_t_swi PARAMS ((char *)); | |
943 | static void do_t_adr PARAMS ((char *)); | |
944 | ||
945 | #define T_OPCODE_MUL 0x4340 | |
946 | #define T_OPCODE_TST 0x4200 | |
947 | #define T_OPCODE_CMN 0x42c0 | |
948 | #define T_OPCODE_NEG 0x4240 | |
949 | #define T_OPCODE_MVN 0x43c0 | |
950 | ||
951 | #define T_OPCODE_ADD_R3 0x1800 | |
952 | #define T_OPCODE_SUB_R3 0x1a00 | |
953 | #define T_OPCODE_ADD_HI 0x4400 | |
954 | #define T_OPCODE_ADD_ST 0xb000 | |
955 | #define T_OPCODE_SUB_ST 0xb080 | |
956 | #define T_OPCODE_ADD_SP 0xa800 | |
957 | #define T_OPCODE_ADD_PC 0xa000 | |
958 | #define T_OPCODE_ADD_I8 0x3000 | |
959 | #define T_OPCODE_SUB_I8 0x3800 | |
960 | #define T_OPCODE_ADD_I3 0x1c00 | |
961 | #define T_OPCODE_SUB_I3 0x1e00 | |
962 | ||
963 | #define T_OPCODE_ASR_R 0x4100 | |
964 | #define T_OPCODE_LSL_R 0x4080 | |
965 | #define T_OPCODE_LSR_R 0x40c0 | |
966 | #define T_OPCODE_ASR_I 0x1000 | |
967 | #define T_OPCODE_LSL_I 0x0000 | |
968 | #define T_OPCODE_LSR_I 0x0800 | |
969 | ||
970 | #define T_OPCODE_MOV_I8 0x2000 | |
971 | #define T_OPCODE_CMP_I8 0x2800 | |
972 | #define T_OPCODE_CMP_LR 0x4280 | |
973 | #define T_OPCODE_MOV_HR 0x4600 | |
974 | #define T_OPCODE_CMP_HR 0x4500 | |
975 | ||
976 | #define T_OPCODE_LDR_PC 0x4800 | |
977 | #define T_OPCODE_LDR_SP 0x9800 | |
978 | #define T_OPCODE_STR_SP 0x9000 | |
979 | #define T_OPCODE_LDR_IW 0x6800 | |
980 | #define T_OPCODE_STR_IW 0x6000 | |
981 | #define T_OPCODE_LDR_IH 0x8800 | |
982 | #define T_OPCODE_STR_IH 0x8000 | |
983 | #define T_OPCODE_LDR_IB 0x7800 | |
984 | #define T_OPCODE_STR_IB 0x7000 | |
985 | #define T_OPCODE_LDR_RW 0x5800 | |
986 | #define T_OPCODE_STR_RW 0x5000 | |
987 | #define T_OPCODE_LDR_RH 0x5a00 | |
988 | #define T_OPCODE_STR_RH 0x5200 | |
989 | #define T_OPCODE_LDR_RB 0x5c00 | |
990 | #define T_OPCODE_STR_RB 0x5400 | |
991 | ||
992 | #define T_OPCODE_PUSH 0xb400 | |
993 | #define T_OPCODE_POP 0xbc00 | |
994 | ||
995 | #define T_OPCODE_BRANCH 0xe7fe | |
996 | ||
997 | static int thumb_reg PARAMS ((char ** str, int hi_lo)); | |
998 | ||
999 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ | |
1000 | #define THUMB_REG_LO 0x1 | |
1001 | #define THUMB_REG_HI 0x2 | |
1002 | #define THUMB_REG_ANY 0x3 | |
1003 | ||
1004 | #define THUMB_H1 0x0080 | |
1005 | #define THUMB_H2 0x0040 | |
1006 | ||
1007 | #define THUMB_ASR 0 | |
1008 | #define THUMB_LSL 1 | |
1009 | #define THUMB_LSR 2 | |
1010 | ||
1011 | #define THUMB_MOVE 0 | |
1012 | #define THUMB_COMPARE 1 | |
1013 | ||
1014 | #define THUMB_LOAD 0 | |
1015 | #define THUMB_STORE 1 | |
1016 | ||
1017 | #define THUMB_PP_PC_LR 0x0100 | |
1018 | ||
1019 | /* These three are used for immediate shifts, do not alter. */ | |
1020 | #define THUMB_WORD 2 | |
1021 | #define THUMB_HALFWORD 1 | |
1022 | #define THUMB_BYTE 0 | |
1023 | ||
1024 | struct thumb_opcode | |
1025 | { | |
1026 | /* Basic string to match. */ | |
1027 | CONST char * template; | |
1028 | ||
1029 | /* Basic instruction code. */ | |
1030 | unsigned long value; | |
1031 | ||
1032 | int size; | |
1033 | ||
1034 | /* Which CPU variants this exists for. */ | |
1035 | unsigned long variants; | |
1036 | ||
1037 | /* Function to call to parse args. */ | |
1038 | void (* parms) PARAMS ((char *)); | |
1039 | }; | |
1040 | ||
1041 | static CONST struct thumb_opcode tinsns[] = | |
1042 | { | |
1043 | {"adc", 0x4140, 2, ARM_EXT_THUMB, do_t_arit}, | |
1044 | {"add", 0x0000, 2, ARM_EXT_THUMB, do_t_add}, | |
1045 | {"and", 0x4000, 2, ARM_EXT_THUMB, do_t_arit}, | |
1046 | {"asr", 0x0000, 2, ARM_EXT_THUMB, do_t_asr}, | |
1047 | {"b", T_OPCODE_BRANCH, 2, ARM_EXT_THUMB, do_t_branch12}, | |
1048 | {"beq", 0xd0fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1049 | {"bne", 0xd1fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1050 | {"bcs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1051 | {"bhs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1052 | {"bcc", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1053 | {"bul", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1054 | {"blo", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1055 | {"bmi", 0xd4fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1056 | {"bpl", 0xd5fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1057 | {"bvs", 0xd6fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1058 | {"bvc", 0xd7fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1059 | {"bhi", 0xd8fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1060 | {"bls", 0xd9fe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1061 | {"bge", 0xdafe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1062 | {"blt", 0xdbfe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1063 | {"bgt", 0xdcfe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1064 | {"ble", 0xddfe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1065 | {"bal", 0xdefe, 2, ARM_EXT_THUMB, do_t_branch9}, | |
1066 | {"bic", 0x4380, 2, ARM_EXT_THUMB, do_t_arit}, | |
1067 | {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB, do_t_branch23}, | |
1068 | {"blx", 0, 0, ARM_EXT_V5, do_t_blx}, | |
1069 | {"bkpt", 0xbe00, 2, ARM_EXT_V5, do_t_bkpt}, | |
1070 | {"bx", 0x4700, 2, ARM_EXT_THUMB, do_t_bx}, | |
1071 | {"cmn", T_OPCODE_CMN, 2, ARM_EXT_THUMB, do_t_arit}, | |
1072 | {"cmp", 0x0000, 2, ARM_EXT_THUMB, do_t_compare}, | |
1073 | {"eor", 0x4040, 2, ARM_EXT_THUMB, do_t_arit}, | |
1074 | {"ldmia", 0xc800, 2, ARM_EXT_THUMB, do_t_ldmstm}, | |
1075 | {"ldr", 0x0000, 2, ARM_EXT_THUMB, do_t_ldr}, | |
1076 | {"ldrb", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrb}, | |
1077 | {"ldrh", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrh}, | |
1078 | {"ldrsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds}, | |
1079 | {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds}, | |
1080 | {"ldsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds}, | |
1081 | {"ldsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds}, | |
1082 | {"lsl", 0x0000, 2, ARM_EXT_THUMB, do_t_lsl}, | |
1083 | {"lsr", 0x0000, 2, ARM_EXT_THUMB, do_t_lsr}, | |
1084 | {"mov", 0x0000, 2, ARM_EXT_THUMB, do_t_mov}, | |
1085 | {"mul", T_OPCODE_MUL, 2, ARM_EXT_THUMB, do_t_arit}, | |
1086 | {"mvn", T_OPCODE_MVN, 2, ARM_EXT_THUMB, do_t_arit}, | |
1087 | {"neg", T_OPCODE_NEG, 2, ARM_EXT_THUMB, do_t_arit}, | |
1088 | {"orr", 0x4300, 2, ARM_EXT_THUMB, do_t_arit}, | |
1089 | {"pop", 0xbc00, 2, ARM_EXT_THUMB, do_t_push_pop}, | |
1090 | {"push", 0xb400, 2, ARM_EXT_THUMB, do_t_push_pop}, | |
1091 | {"ror", 0x41c0, 2, ARM_EXT_THUMB, do_t_arit}, | |
1092 | {"sbc", 0x4180, 2, ARM_EXT_THUMB, do_t_arit}, | |
1093 | {"stmia", 0xc000, 2, ARM_EXT_THUMB, do_t_ldmstm}, | |
1094 | {"str", 0x0000, 2, ARM_EXT_THUMB, do_t_str}, | |
1095 | {"strb", 0x0000, 2, ARM_EXT_THUMB, do_t_strb}, | |
1096 | {"strh", 0x0000, 2, ARM_EXT_THUMB, do_t_strh}, | |
1097 | {"swi", 0xdf00, 2, ARM_EXT_THUMB, do_t_swi}, | |
1098 | {"sub", 0x0000, 2, ARM_EXT_THUMB, do_t_sub}, | |
1099 | {"tst", T_OPCODE_TST, 2, ARM_EXT_THUMB, do_t_arit}, | |
1100 | /* Pseudo ops: */ | |
1101 | {"adr", 0x0000, 2, ARM_EXT_THUMB, do_t_adr}, | |
1102 | {"nop", 0x46C0, 2, ARM_EXT_THUMB, do_t_nop}, /* mov r8,r8 */ | |
1103 | }; | |
1104 | ||
1105 | struct reg_entry | |
1106 | { | |
1107 | CONST char * name; | |
1108 | int number; | |
1109 | }; | |
1110 | ||
1111 | #define int_register(reg) ((reg) >= 0 && (reg) <= 15) | |
1112 | #define cp_register(reg) ((reg) >= 32 && (reg) <= 47) | |
1113 | #define fp_register(reg) ((reg) >= 16 && (reg) <= 23) | |
1114 | ||
1115 | #define REG_PC 15 | |
1116 | #define REG_LR 14 | |
1117 | #define REG_SP 13 | |
1118 | ||
1119 | /* These are the standard names. Users can add aliases with .req. */ | |
1120 | static CONST struct reg_entry reg_table[] = | |
1121 | { | |
1122 | /* Processor Register Numbers. */ | |
1123 | {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, | |
1124 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, | |
1125 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, | |
1126 | {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC}, | |
1127 | /* APCS conventions. */ | |
1128 | {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3}, | |
1129 | {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8}, | |
1130 | {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10}, | |
1131 | {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC}, | |
1132 | /* ATPCS additions to APCS conventions. */ | |
1133 | {"wr", 7}, {"v8", 11}, | |
1134 | /* FP Registers. */ | |
1135 | {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19}, | |
1136 | {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23}, | |
1137 | {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35}, | |
1138 | {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39}, | |
1139 | {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43}, | |
1140 | {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47}, | |
1141 | {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35}, | |
1142 | {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39}, | |
1143 | {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43}, | |
1144 | {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47}, | |
1145 | /* ATPCS additions to float register names. */ | |
1146 | {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19}, | |
1147 | {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23}, | |
1148 | {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19}, | |
1149 | {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23}, | |
1150 | /* FIXME: At some point we need to add VFP register names. */ | |
1151 | /* Array terminator. */ | |
1152 | {NULL, 0} | |
1153 | }; | |
1154 | ||
1155 | #define BAD_ARGS _("Bad arguments to instruction") | |
1156 | #define BAD_PC _("r15 not allowed here") | |
1157 | #define BAD_FLAGS _("Instruction should not have flags") | |
1158 | #define BAD_COND _("Instruction is not conditional") | |
1159 | #define ERR_NO_ACCUM _("acc0 expected") | |
1160 | ||
1161 | static struct hash_control * arm_ops_hsh = NULL; | |
1162 | static struct hash_control * arm_tops_hsh = NULL; | |
1163 | static struct hash_control * arm_cond_hsh = NULL; | |
1164 | static struct hash_control * arm_shift_hsh = NULL; | |
1165 | static struct hash_control * arm_reg_hsh = NULL; | |
1166 | static struct hash_control * arm_psr_hsh = NULL; | |
1167 | ||
1168 | /* This table describes all the machine specific pseudo-ops the assembler | |
1169 | has to support. The fields are: | |
1170 | pseudo-op name without dot | |
1171 | function to call to execute this pseudo-op | |
1172 | Integer arg to pass to the function. */ | |
1173 | ||
1174 | static void s_req PARAMS ((int)); | |
1175 | static void s_align PARAMS ((int)); | |
1176 | static void s_bss PARAMS ((int)); | |
1177 | static void s_even PARAMS ((int)); | |
1178 | static void s_ltorg PARAMS ((int)); | |
1179 | static void s_arm PARAMS ((int)); | |
1180 | static void s_thumb PARAMS ((int)); | |
1181 | static void s_code PARAMS ((int)); | |
1182 | static void s_force_thumb PARAMS ((int)); | |
1183 | static void s_thumb_func PARAMS ((int)); | |
1184 | static void s_thumb_set PARAMS ((int)); | |
1185 | static void arm_s_text PARAMS ((int)); | |
1186 | static void arm_s_data PARAMS ((int)); | |
1187 | #ifdef OBJ_ELF | |
1188 | static void arm_s_section PARAMS ((int)); | |
1189 | static void s_arm_elf_cons PARAMS ((int)); | |
1190 | #endif | |
1191 | ||
1192 | static int my_get_expression PARAMS ((expressionS *, char **)); | |
1193 | ||
1194 | CONST pseudo_typeS md_pseudo_table[] = | |
1195 | { | |
1196 | /* Never called becasue '.req' does not start line. */ | |
1197 | { "req", s_req, 0 }, | |
1198 | { "bss", s_bss, 0 }, | |
1199 | { "align", s_align, 0 }, | |
1200 | { "arm", s_arm, 0 }, | |
1201 | { "thumb", s_thumb, 0 }, | |
1202 | { "code", s_code, 0 }, | |
1203 | { "force_thumb", s_force_thumb, 0 }, | |
1204 | { "thumb_func", s_thumb_func, 0 }, | |
1205 | { "thumb_set", s_thumb_set, 0 }, | |
1206 | { "even", s_even, 0 }, | |
1207 | { "ltorg", s_ltorg, 0 }, | |
1208 | { "pool", s_ltorg, 0 }, | |
1209 | /* Allow for the effect of section changes. */ | |
1210 | { "text", arm_s_text, 0 }, | |
1211 | { "data", arm_s_data, 0 }, | |
1212 | #ifdef OBJ_ELF | |
1213 | { "section", arm_s_section, 0 }, | |
1214 | { "section.s", arm_s_section, 0 }, | |
1215 | { "sect", arm_s_section, 0 }, | |
1216 | { "sect.s", arm_s_section, 0 }, | |
1217 | { "word", s_arm_elf_cons, 4 }, | |
1218 | { "long", s_arm_elf_cons, 4 }, | |
1219 | { "file", dwarf2_directive_file, 0 }, | |
1220 | { "loc", dwarf2_directive_loc, 0 }, | |
1221 | #else | |
1222 | { "word", cons, 4}, | |
1223 | #endif | |
1224 | { "extend", float_cons, 'x' }, | |
1225 | { "ldouble", float_cons, 'x' }, | |
1226 | { "packed", float_cons, 'p' }, | |
1227 | { 0, 0, 0 } | |
1228 | }; | |
1229 | ||
1230 | /* Stuff needed to resolve the label ambiguity | |
1231 | As: | |
1232 | ... | |
1233 | label: <insn> | |
1234 | may differ from: | |
1235 | ... | |
1236 | label: | |
1237 | <insn> | |
1238 | */ | |
1239 | ||
1240 | symbolS * last_label_seen; | |
1241 | static int label_is_thumb_function_name = false; | |
1242 | ||
1243 | /* Literal stuff. */ | |
1244 | ||
1245 | #define MAX_LITERAL_POOL_SIZE 1024 | |
1246 | ||
1247 | typedef struct literalS | |
1248 | { | |
1249 | struct expressionS exp; | |
1250 | struct arm_it * inst; | |
1251 | } literalT; | |
1252 | ||
1253 | literalT literals[MAX_LITERAL_POOL_SIZE]; | |
1254 | ||
1255 | /* Next free entry in the pool. */ | |
1256 | int next_literal_pool_place = 0; | |
1257 | ||
1258 | /* Next literal pool number. */ | |
1259 | int lit_pool_num = 1; | |
1260 | ||
1261 | symbolS * current_poolP = NULL; | |
1262 | ||
1263 | static int | |
1264 | add_to_lit_pool () | |
1265 | { | |
1266 | int lit_count = 0; | |
1267 | ||
1268 | if (current_poolP == NULL) | |
1269 | current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section, | |
1270 | (valueT) 0, &zero_address_frag); | |
1271 | ||
1272 | /* Check if this literal value is already in the pool: */ | |
1273 | while (lit_count < next_literal_pool_place) | |
1274 | { | |
1275 | if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op | |
1276 | && inst.reloc.exp.X_op == O_constant | |
1277 | && (literals[lit_count].exp.X_add_number | |
1278 | == inst.reloc.exp.X_add_number) | |
1279 | && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned) | |
1280 | break; | |
1281 | ||
1282 | if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op | |
1283 | && inst.reloc.exp.X_op == O_symbol | |
1284 | && (literals[lit_count].exp.X_add_number | |
1285 | == inst.reloc.exp.X_add_number) | |
1286 | && (literals[lit_count].exp.X_add_symbol | |
1287 | == inst.reloc.exp.X_add_symbol) | |
1288 | && (literals[lit_count].exp.X_op_symbol | |
1289 | == inst.reloc.exp.X_op_symbol)) | |
1290 | break; | |
1291 | ||
1292 | lit_count++; | |
1293 | } | |
1294 | ||
1295 | if (lit_count == next_literal_pool_place) /* New entry. */ | |
1296 | { | |
1297 | if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE) | |
1298 | { | |
1299 | inst.error = _("Literal Pool Overflow"); | |
1300 | return FAIL; | |
1301 | } | |
1302 | ||
1303 | literals[next_literal_pool_place].exp = inst.reloc.exp; | |
1304 | lit_count = next_literal_pool_place++; | |
1305 | } | |
1306 | ||
1307 | inst.reloc.exp.X_op = O_symbol; | |
1308 | inst.reloc.exp.X_add_number = (lit_count) * 4 - 8; | |
1309 | inst.reloc.exp.X_add_symbol = current_poolP; | |
1310 | ||
1311 | return SUCCESS; | |
1312 | } | |
1313 | ||
1314 | /* Can't use symbol_new here, so have to create a symbol and then at | |
1315 | a later date assign it a value. Thats what these functions do. */ | |
1316 | ||
1317 | static void | |
1318 | symbol_locate (symbolP, name, segment, valu, frag) | |
1319 | symbolS * symbolP; | |
1320 | CONST char * name; /* It is copied, the caller can modify. */ | |
1321 | segT segment; /* Segment identifier (SEG_<something>). */ | |
1322 | valueT valu; /* Symbol value. */ | |
1323 | fragS * frag; /* Associated fragment. */ | |
1324 | { | |
1325 | unsigned int name_length; | |
1326 | char * preserved_copy_of_name; | |
1327 | ||
1328 | name_length = strlen (name) + 1; /* +1 for \0. */ | |
1329 | obstack_grow (¬es, name, name_length); | |
1330 | preserved_copy_of_name = obstack_finish (¬es); | |
1331 | #ifdef STRIP_UNDERSCORE | |
1332 | if (preserved_copy_of_name[0] == '_') | |
1333 | preserved_copy_of_name++; | |
1334 | #endif | |
1335 | ||
1336 | #ifdef tc_canonicalize_symbol_name | |
1337 | preserved_copy_of_name = | |
1338 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1339 | #endif | |
1340 | ||
1341 | S_SET_NAME (symbolP, preserved_copy_of_name); | |
1342 | ||
1343 | S_SET_SEGMENT (symbolP, segment); | |
1344 | S_SET_VALUE (symbolP, valu); | |
1345 | symbol_clear_list_pointers(symbolP); | |
1346 | ||
1347 | symbol_set_frag (symbolP, frag); | |
1348 | ||
1349 | /* Link to end of symbol chain. */ | |
1350 | { | |
1351 | extern int symbol_table_frozen; | |
1352 | if (symbol_table_frozen) | |
1353 | abort (); | |
1354 | } | |
1355 | ||
1356 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); | |
1357 | ||
1358 | obj_symbol_new_hook (symbolP); | |
1359 | ||
1360 | #ifdef tc_symbol_new_hook | |
1361 | tc_symbol_new_hook (symbolP); | |
1362 | #endif | |
1363 | ||
1364 | #ifdef DEBUG_SYMS | |
1365 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1366 | #endif /* DEBUG_SYMS */ | |
1367 | } | |
1368 | ||
1369 | /* Check that an immediate is valid. | |
1370 | If so, convert it to the right format. */ | |
1371 | ||
1372 | static unsigned int | |
1373 | validate_immediate (val) | |
1374 | unsigned int val; | |
1375 | { | |
1376 | unsigned int a; | |
1377 | unsigned int i; | |
1378 | ||
1379 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
1380 | ||
1381 | for (i = 0; i < 32; i += 2) | |
1382 | if ((a = rotate_left (val, i)) <= 0xff) | |
1383 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
1384 | ||
1385 | return FAIL; | |
1386 | } | |
1387 | ||
1388 | /* Check to see if an immediate can be computed as two seperate immediate | |
1389 | values, added together. We already know that this value cannot be | |
1390 | computed by just one ARM instruction. */ | |
1391 | ||
1392 | static unsigned int | |
1393 | validate_immediate_twopart (val, highpart) | |
1394 | unsigned int val; | |
1395 | unsigned int * highpart; | |
1396 | { | |
1397 | unsigned int a; | |
1398 | unsigned int i; | |
1399 | ||
1400 | for (i = 0; i < 32; i += 2) | |
1401 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
1402 | { | |
1403 | if (a & 0xff00) | |
1404 | { | |
1405 | if (a & ~ 0xffff) | |
1406 | continue; | |
1407 | * highpart = (a >> 8) | ((i + 24) << 7); | |
1408 | } | |
1409 | else if (a & 0xff0000) | |
1410 | { | |
1411 | if (a & 0xff000000) | |
1412 | continue; | |
1413 | * highpart = (a >> 16) | ((i + 16) << 7); | |
1414 | } | |
1415 | else | |
1416 | { | |
1417 | assert (a & 0xff000000); | |
1418 | * highpart = (a >> 24) | ((i + 8) << 7); | |
1419 | } | |
1420 | ||
1421 | return (a & 0xff) | (i << 7); | |
1422 | } | |
1423 | ||
1424 | return FAIL; | |
1425 | } | |
1426 | ||
1427 | static int | |
1428 | validate_offset_imm (val, hwse) | |
1429 | unsigned int val; | |
1430 | int hwse; | |
1431 | { | |
1432 | if ((hwse && val > 255) || val > 4095) | |
1433 | return FAIL; | |
1434 | return val; | |
1435 | } | |
1436 | ||
1437 | static void | |
1438 | s_req (a) | |
1439 | int a ATTRIBUTE_UNUSED; | |
1440 | { | |
1441 | as_bad (_("Invalid syntax for .req directive.")); | |
1442 | } | |
1443 | ||
1444 | static void | |
1445 | s_bss (ignore) | |
1446 | int ignore ATTRIBUTE_UNUSED; | |
1447 | { | |
1448 | /* We don't support putting frags in the BSS segment, we fake it by | |
1449 | marking in_bss, then looking at s_skip for clues. */ | |
1450 | subseg_set (bss_section, 0); | |
1451 | demand_empty_rest_of_line (); | |
1452 | } | |
1453 | ||
1454 | static void | |
1455 | s_even (ignore) | |
1456 | int ignore ATTRIBUTE_UNUSED; | |
1457 | { | |
1458 | /* Never make frag if expect extra pass. */ | |
1459 | if (!need_pass_2) | |
1460 | frag_align (1, 0, 0); | |
1461 | ||
1462 | record_alignment (now_seg, 1); | |
1463 | ||
1464 | demand_empty_rest_of_line (); | |
1465 | } | |
1466 | ||
1467 | static void | |
1468 | s_ltorg (ignored) | |
1469 | int ignored ATTRIBUTE_UNUSED; | |
1470 | { | |
1471 | int lit_count = 0; | |
1472 | char sym_name[20]; | |
1473 | ||
1474 | if (current_poolP == NULL) | |
1475 | return; | |
1476 | ||
1477 | /* Align pool as you have word accesses. | |
1478 | Only make a frag if we have to. */ | |
1479 | if (!need_pass_2) | |
1480 | frag_align (2, 0, 0); | |
1481 | ||
1482 | record_alignment (now_seg, 2); | |
1483 | ||
1484 | sprintf (sym_name, "$$lit_\002%x", lit_pool_num++); | |
1485 | ||
1486 | symbol_locate (current_poolP, sym_name, now_seg, | |
1487 | (valueT) frag_now_fix (), frag_now); | |
1488 | symbol_table_insert (current_poolP); | |
1489 | ||
1490 | ARM_SET_THUMB (current_poolP, thumb_mode); | |
1491 | ||
1492 | #if defined OBJ_COFF || defined OBJ_ELF | |
1493 | ARM_SET_INTERWORK (current_poolP, support_interwork); | |
1494 | #endif | |
1495 | ||
1496 | while (lit_count < next_literal_pool_place) | |
1497 | /* First output the expression in the instruction to the pool. */ | |
1498 | emit_expr (&(literals[lit_count++].exp), 4); /* .word */ | |
1499 | ||
1500 | next_literal_pool_place = 0; | |
1501 | current_poolP = NULL; | |
1502 | } | |
1503 | ||
1504 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
1505 | ||
1506 | static void | |
1507 | s_align (unused) | |
1508 | int unused ATTRIBUTE_UNUSED; | |
1509 | { | |
1510 | register int temp; | |
1511 | register long temp_fill; | |
1512 | long max_alignment = 15; | |
1513 | ||
1514 | temp = get_absolute_expression (); | |
1515 | if (temp > max_alignment) | |
1516 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
1517 | else if (temp < 0) | |
1518 | { | |
1519 | as_bad (_("Alignment negative. 0 assumed.")); | |
1520 | temp = 0; | |
1521 | } | |
1522 | ||
1523 | if (*input_line_pointer == ',') | |
1524 | { | |
1525 | input_line_pointer++; | |
1526 | temp_fill = get_absolute_expression (); | |
1527 | } | |
1528 | else | |
1529 | temp_fill = 0; | |
1530 | ||
1531 | if (!temp) | |
1532 | temp = 2; | |
1533 | ||
1534 | /* Only make a frag if we HAVE to. */ | |
1535 | if (temp && !need_pass_2) | |
1536 | frag_align (temp, (int) temp_fill, 0); | |
1537 | demand_empty_rest_of_line (); | |
1538 | ||
1539 | record_alignment (now_seg, temp); | |
1540 | } | |
1541 | ||
1542 | static void | |
1543 | s_force_thumb (ignore) | |
1544 | int ignore ATTRIBUTE_UNUSED; | |
1545 | { | |
1546 | /* If we are not already in thumb mode go into it, EVEN if | |
1547 | the target processor does not support thumb instructions. | |
1548 | This is used by gcc/config/arm/lib1funcs.asm for example | |
1549 | to compile interworking support functions even if the | |
1550 | target processor should not support interworking. */ | |
1551 | if (! thumb_mode) | |
1552 | { | |
1553 | thumb_mode = 2; | |
1554 | ||
1555 | record_alignment (now_seg, 1); | |
1556 | } | |
1557 | ||
1558 | demand_empty_rest_of_line (); | |
1559 | } | |
1560 | ||
1561 | static void | |
1562 | s_thumb_func (ignore) | |
1563 | int ignore ATTRIBUTE_UNUSED; | |
1564 | { | |
1565 | if (! thumb_mode) | |
1566 | opcode_select (16); | |
1567 | ||
1568 | /* The following label is the name/address of the start of a Thumb function. | |
1569 | We need to know this for the interworking support. */ | |
1570 | label_is_thumb_function_name = true; | |
1571 | ||
1572 | demand_empty_rest_of_line (); | |
1573 | } | |
1574 | ||
1575 | /* Perform a .set directive, but also mark the alias as | |
1576 | being a thumb function. */ | |
1577 | ||
1578 | static void | |
1579 | s_thumb_set (equiv) | |
1580 | int equiv; | |
1581 | { | |
1582 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
1583 | We cannot just call that code as we need to get at the symbol that | |
1584 | is created. */ | |
1585 | register char * name; | |
1586 | register char delim; | |
1587 | register char * end_name; | |
1588 | register symbolS * symbolP; | |
1589 | ||
1590 | /* Especial apologies for the random logic: | |
1591 | This just grew, and could be parsed much more simply! | |
1592 | Dean - in haste. */ | |
1593 | name = input_line_pointer; | |
1594 | delim = get_symbol_end (); | |
1595 | end_name = input_line_pointer; | |
1596 | *end_name = delim; | |
1597 | ||
1598 | SKIP_WHITESPACE (); | |
1599 | ||
1600 | if (*input_line_pointer != ',') | |
1601 | { | |
1602 | *end_name = 0; | |
1603 | as_bad (_("Expected comma after name \"%s\""), name); | |
1604 | *end_name = delim; | |
1605 | ignore_rest_of_line (); | |
1606 | return; | |
1607 | } | |
1608 | ||
1609 | input_line_pointer++; | |
1610 | *end_name = 0; | |
1611 | ||
1612 | if (name[0] == '.' && name[1] == '\0') | |
1613 | { | |
1614 | /* XXX - this should not happen to .thumb_set. */ | |
1615 | abort (); | |
1616 | } | |
1617 | ||
1618 | if ((symbolP = symbol_find (name)) == NULL | |
1619 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
1620 | { | |
1621 | #ifndef NO_LISTING | |
1622 | /* When doing symbol listings, play games with dummy fragments living | |
1623 | outside the normal fragment chain to record the file and line info | |
1624 | for this symbol. */ | |
1625 | if (listing & LISTING_SYMBOLS) | |
1626 | { | |
1627 | extern struct list_info_struct * listing_tail; | |
1628 | fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS)); | |
1629 | ||
1630 | memset (dummy_frag, 0, sizeof (fragS)); | |
1631 | dummy_frag->fr_type = rs_fill; | |
1632 | dummy_frag->line = listing_tail; | |
1633 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
1634 | dummy_frag->fr_symbol = symbolP; | |
1635 | } | |
1636 | else | |
1637 | #endif | |
1638 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
1639 | ||
1640 | #ifdef OBJ_COFF | |
1641 | /* "set" symbols are local unless otherwise specified. */ | |
1642 | SF_SET_LOCAL (symbolP); | |
1643 | #endif /* OBJ_COFF */ | |
1644 | } /* Make a new symbol. */ | |
1645 | ||
1646 | symbol_table_insert (symbolP); | |
1647 | ||
1648 | * end_name = delim; | |
1649 | ||
1650 | if (equiv | |
1651 | && S_IS_DEFINED (symbolP) | |
1652 | && S_GET_SEGMENT (symbolP) != reg_section) | |
1653 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
1654 | ||
1655 | pseudo_set (symbolP); | |
1656 | ||
1657 | demand_empty_rest_of_line (); | |
1658 | ||
1659 | /* XXX Now we come to the Thumb specific bit of code. */ | |
1660 | ||
1661 | THUMB_SET_FUNC (symbolP, 1); | |
1662 | ARM_SET_THUMB (symbolP, 1); | |
1663 | #if defined OBJ_ELF || defined OBJ_COFF | |
1664 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1665 | #endif | |
1666 | } | |
1667 | ||
1668 | /* If we change section we must dump the literal pool first. */ | |
1669 | ||
1670 | static void | |
1671 | arm_s_text (ignore) | |
1672 | int ignore; | |
1673 | { | |
1674 | if (now_seg != text_section) | |
1675 | s_ltorg (0); | |
1676 | ||
1677 | #ifdef OBJ_ELF | |
1678 | obj_elf_text (ignore); | |
1679 | #else | |
1680 | s_text (ignore); | |
1681 | #endif | |
1682 | } | |
1683 | ||
1684 | static void | |
1685 | arm_s_data (ignore) | |
1686 | int ignore; | |
1687 | { | |
1688 | if (flag_readonly_data_in_text) | |
1689 | { | |
1690 | if (now_seg != text_section) | |
1691 | s_ltorg (0); | |
1692 | } | |
1693 | else if (now_seg != data_section) | |
1694 | s_ltorg (0); | |
1695 | ||
1696 | #ifdef OBJ_ELF | |
1697 | obj_elf_data (ignore); | |
1698 | #else | |
1699 | s_data (ignore); | |
1700 | #endif | |
1701 | } | |
1702 | ||
1703 | #ifdef OBJ_ELF | |
1704 | static void | |
1705 | arm_s_section (ignore) | |
1706 | int ignore; | |
1707 | { | |
1708 | s_ltorg (0); | |
1709 | ||
1710 | obj_elf_section (ignore); | |
1711 | } | |
1712 | #endif | |
1713 | ||
1714 | static void | |
1715 | opcode_select (width) | |
1716 | int width; | |
1717 | { | |
1718 | switch (width) | |
1719 | { | |
1720 | case 16: | |
1721 | if (! thumb_mode) | |
1722 | { | |
1723 | if (! (cpu_variant & ARM_EXT_THUMB)) | |
1724 | as_bad (_("selected processor does not support THUMB opcodes")); | |
1725 | ||
1726 | thumb_mode = 1; | |
1727 | /* No need to force the alignment, since we will have been | |
1728 | coming from ARM mode, which is word-aligned. */ | |
1729 | record_alignment (now_seg, 1); | |
1730 | } | |
1731 | break; | |
1732 | ||
1733 | case 32: | |
1734 | if (thumb_mode) | |
1735 | { | |
1736 | if ((cpu_variant & ARM_ANY) == ARM_EXT_THUMB) | |
1737 | as_bad (_("selected processor does not support ARM opcodes")); | |
1738 | ||
1739 | thumb_mode = 0; | |
1740 | ||
1741 | if (!need_pass_2) | |
1742 | frag_align (2, 0, 0); | |
1743 | ||
1744 | record_alignment (now_seg, 1); | |
1745 | } | |
1746 | break; | |
1747 | ||
1748 | default: | |
1749 | as_bad (_("invalid instruction size selected (%d)"), width); | |
1750 | } | |
1751 | } | |
1752 | ||
1753 | static void | |
1754 | s_arm (ignore) | |
1755 | int ignore ATTRIBUTE_UNUSED; | |
1756 | { | |
1757 | opcode_select (32); | |
1758 | demand_empty_rest_of_line (); | |
1759 | } | |
1760 | ||
1761 | static void | |
1762 | s_thumb (ignore) | |
1763 | int ignore ATTRIBUTE_UNUSED; | |
1764 | { | |
1765 | opcode_select (16); | |
1766 | demand_empty_rest_of_line (); | |
1767 | } | |
1768 | ||
1769 | static void | |
1770 | s_code (unused) | |
1771 | int unused ATTRIBUTE_UNUSED; | |
1772 | { | |
1773 | register int temp; | |
1774 | ||
1775 | temp = get_absolute_expression (); | |
1776 | switch (temp) | |
1777 | { | |
1778 | case 16: | |
1779 | case 32: | |
1780 | opcode_select (temp); | |
1781 | break; | |
1782 | ||
1783 | default: | |
1784 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | static void | |
1789 | end_of_line (str) | |
1790 | char * str; | |
1791 | { | |
1792 | skip_whitespace (str); | |
1793 | ||
1794 | if (* str != '\0') | |
1795 | inst.error = _("Garbage following instruction"); | |
1796 | } | |
1797 | ||
1798 | static int | |
1799 | skip_past_comma (str) | |
1800 | char ** str; | |
1801 | { | |
1802 | char * p = * str, c; | |
1803 | int comma = 0; | |
1804 | ||
1805 | while ((c = *p) == ' ' || c == ',') | |
1806 | { | |
1807 | p++; | |
1808 | if (c == ',' && comma++) | |
1809 | return FAIL; | |
1810 | } | |
1811 | ||
1812 | if (c == '\0') | |
1813 | return FAIL; | |
1814 | ||
1815 | *str = p; | |
1816 | return comma ? SUCCESS : FAIL; | |
1817 | } | |
1818 | ||
1819 | /* A standard register must be given at this point. | |
1820 | SHIFT is the place to put it in inst.instruction. | |
1821 | Restores input start point on error. | |
1822 | Returns the reg#, or FAIL. */ | |
1823 | ||
1824 | static int | |
1825 | reg_required_here (str, shift) | |
1826 | char ** str; | |
1827 | int shift; | |
1828 | { | |
1829 | static char buff [128]; /* XXX */ | |
1830 | int reg; | |
1831 | char * start = * str; | |
1832 | ||
1833 | if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg)) | |
1834 | { | |
1835 | if (shift >= 0) | |
1836 | inst.instruction |= reg << shift; | |
1837 | return reg; | |
1838 | } | |
1839 | ||
1840 | /* Restore the start point, we may have got a reg of the wrong class. */ | |
1841 | *str = start; | |
1842 | ||
1843 | /* In the few cases where we might be able to accept something else | |
1844 | this error can be overridden. */ | |
1845 | sprintf (buff, _("Register expected, not '%.100s'"), start); | |
1846 | inst.error = buff; | |
1847 | ||
1848 | return FAIL; | |
1849 | } | |
1850 | ||
1851 | static CONST struct asm_psr * | |
1852 | arm_psr_parse (ccp) | |
1853 | register char ** ccp; | |
1854 | { | |
1855 | char * start = * ccp; | |
1856 | char c; | |
1857 | char * p; | |
1858 | CONST struct asm_psr * psr; | |
1859 | ||
1860 | p = start; | |
1861 | ||
1862 | /* Skip to the end of the next word in the input stream. */ | |
1863 | do | |
1864 | { | |
1865 | c = *p++; | |
1866 | } | |
1867 | while (isalpha (c) || c == '_'); | |
1868 | ||
1869 | /* Terminate the word. */ | |
1870 | *--p = 0; | |
1871 | ||
1872 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience | |
1873 | feature for ease of use and backwards compatibility. */ | |
1874 | if (!strncmp (start, "cpsr", 4)) | |
1875 | strncpy (start, "CPSR", 4); | |
1876 | else if (!strncmp (start, "spsr", 4)) | |
1877 | strncpy (start, "SPSR", 4); | |
1878 | ||
1879 | /* Now locate the word in the psr hash table. */ | |
1880 | psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start); | |
1881 | ||
1882 | /* Restore the input stream. */ | |
1883 | *p = c; | |
1884 | ||
1885 | /* If we found a valid match, advance the | |
1886 | stream pointer past the end of the word. */ | |
1887 | *ccp = p; | |
1888 | ||
1889 | return psr; | |
1890 | } | |
1891 | ||
1892 | /* Parse the input looking for a PSR flag. */ | |
1893 | ||
1894 | static int | |
1895 | psr_required_here (str) | |
1896 | char ** str; | |
1897 | { | |
1898 | char * start = * str; | |
1899 | CONST struct asm_psr * psr; | |
1900 | ||
1901 | psr = arm_psr_parse (str); | |
1902 | ||
1903 | if (psr) | |
1904 | { | |
1905 | /* If this is the SPSR that is being modified, set the R bit. */ | |
1906 | if (! psr->cpsr) | |
1907 | inst.instruction |= SPSR_BIT; | |
1908 | ||
1909 | /* Set the psr flags in the MSR instruction. */ | |
1910 | inst.instruction |= psr->field << PSR_SHIFT; | |
1911 | ||
1912 | return SUCCESS; | |
1913 | } | |
1914 | ||
1915 | /* In the few cases where we might be able to accept | |
1916 | something else this error can be overridden. */ | |
1917 | inst.error = _("flag for {c}psr instruction expected"); | |
1918 | ||
1919 | /* Restore the start point. */ | |
1920 | *str = start; | |
1921 | return FAIL; | |
1922 | } | |
1923 | ||
1924 | static int | |
1925 | co_proc_number (str) | |
1926 | char ** str; | |
1927 | { | |
1928 | int processor, pchar; | |
1929 | ||
1930 | skip_whitespace (* str); | |
1931 | ||
1932 | /* The data sheet seems to imply that just a number on its own is valid | |
1933 | here, but the RISC iX assembler seems to accept a prefix 'p'. We will | |
1934 | accept either. */ | |
1935 | if (**str == 'p' || **str == 'P') | |
1936 | (*str)++; | |
1937 | ||
1938 | pchar = *(*str)++; | |
1939 | if (pchar >= '0' && pchar <= '9') | |
1940 | { | |
1941 | processor = pchar - '0'; | |
1942 | if (**str >= '0' && **str <= '9') | |
1943 | { | |
1944 | processor = processor * 10 + *(*str)++ - '0'; | |
1945 | if (processor > 15) | |
1946 | { | |
1947 | inst.error = _("Illegal co-processor number"); | |
1948 | return FAIL; | |
1949 | } | |
1950 | } | |
1951 | } | |
1952 | else | |
1953 | { | |
1954 | inst.error = _("Bad or missing co-processor number"); | |
1955 | return FAIL; | |
1956 | } | |
1957 | ||
1958 | inst.instruction |= processor << 8; | |
1959 | return SUCCESS; | |
1960 | } | |
1961 | ||
1962 | static int | |
1963 | cp_opc_expr (str, where, length) | |
1964 | char ** str; | |
1965 | int where; | |
1966 | int length; | |
1967 | { | |
1968 | expressionS expr; | |
1969 | ||
1970 | skip_whitespace (* str); | |
1971 | ||
1972 | memset (&expr, '\0', sizeof (expr)); | |
1973 | ||
1974 | if (my_get_expression (&expr, str)) | |
1975 | return FAIL; | |
1976 | if (expr.X_op != O_constant) | |
1977 | { | |
1978 | inst.error = _("bad or missing expression"); | |
1979 | return FAIL; | |
1980 | } | |
1981 | ||
1982 | if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number) | |
1983 | { | |
1984 | inst.error = _("immediate co-processor expression too large"); | |
1985 | return FAIL; | |
1986 | } | |
1987 | ||
1988 | inst.instruction |= expr.X_add_number << where; | |
1989 | return SUCCESS; | |
1990 | } | |
1991 | ||
1992 | static int | |
1993 | cp_reg_required_here (str, where) | |
1994 | char ** str; | |
1995 | int where; | |
1996 | { | |
1997 | int reg; | |
1998 | char * start = *str; | |
1999 | ||
2000 | if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg)) | |
2001 | { | |
2002 | reg &= 15; | |
2003 | inst.instruction |= reg << where; | |
2004 | return reg; | |
2005 | } | |
2006 | ||
2007 | /* In the few cases where we might be able to accept something else | |
2008 | this error can be overridden. */ | |
2009 | inst.error = _("Co-processor register expected"); | |
2010 | ||
2011 | /* Restore the start point. */ | |
2012 | *str = start; | |
2013 | return FAIL; | |
2014 | } | |
2015 | ||
2016 | static int | |
2017 | fp_reg_required_here (str, where) | |
2018 | char ** str; | |
2019 | int where; | |
2020 | { | |
2021 | int reg; | |
2022 | char * start = * str; | |
2023 | ||
2024 | if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg)) | |
2025 | { | |
2026 | reg &= 7; | |
2027 | inst.instruction |= reg << where; | |
2028 | return reg; | |
2029 | } | |
2030 | ||
2031 | /* In the few cases where we might be able to accept something else | |
2032 | this error can be overridden. */ | |
2033 | inst.error = _("Floating point register expected"); | |
2034 | ||
2035 | /* Restore the start point. */ | |
2036 | *str = start; | |
2037 | return FAIL; | |
2038 | } | |
2039 | ||
2040 | static int | |
2041 | cp_address_offset (str) | |
2042 | char ** str; | |
2043 | { | |
2044 | int offset; | |
2045 | ||
2046 | skip_whitespace (* str); | |
2047 | ||
2048 | if (! is_immediate_prefix (**str)) | |
2049 | { | |
2050 | inst.error = _("immediate expression expected"); | |
2051 | return FAIL; | |
2052 | } | |
2053 | ||
2054 | (*str)++; | |
2055 | ||
2056 | if (my_get_expression (& inst.reloc.exp, str)) | |
2057 | return FAIL; | |
2058 | ||
2059 | if (inst.reloc.exp.X_op == O_constant) | |
2060 | { | |
2061 | offset = inst.reloc.exp.X_add_number; | |
2062 | ||
2063 | if (offset & 3) | |
2064 | { | |
2065 | inst.error = _("co-processor address must be word aligned"); | |
2066 | return FAIL; | |
2067 | } | |
2068 | ||
2069 | if (offset > 1023 || offset < -1023) | |
2070 | { | |
2071 | inst.error = _("offset too large"); | |
2072 | return FAIL; | |
2073 | } | |
2074 | ||
2075 | if (offset >= 0) | |
2076 | inst.instruction |= INDEX_UP; | |
2077 | else | |
2078 | offset = -offset; | |
2079 | ||
2080 | inst.instruction |= offset >> 2; | |
2081 | } | |
2082 | else | |
2083 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
2084 | ||
2085 | return SUCCESS; | |
2086 | } | |
2087 | ||
2088 | static int | |
2089 | cp_address_required_here (str) | |
2090 | char ** str; | |
2091 | { | |
2092 | char * p = * str; | |
2093 | int pre_inc = 0; | |
2094 | int write_back = 0; | |
2095 | ||
2096 | if (*p == '[') | |
2097 | { | |
2098 | int reg; | |
2099 | ||
2100 | p++; | |
2101 | skip_whitespace (p); | |
2102 | ||
2103 | if ((reg = reg_required_here (& p, 16)) == FAIL) | |
2104 | return FAIL; | |
2105 | ||
2106 | skip_whitespace (p); | |
2107 | ||
2108 | if (*p == ']') | |
2109 | { | |
2110 | p++; | |
2111 | ||
2112 | if (skip_past_comma (& p) == SUCCESS) | |
2113 | { | |
2114 | /* [Rn], #expr */ | |
2115 | write_back = WRITE_BACK; | |
2116 | ||
2117 | if (reg == REG_PC) | |
2118 | { | |
2119 | inst.error = _("pc may not be used in post-increment"); | |
2120 | return FAIL; | |
2121 | } | |
2122 | ||
2123 | if (cp_address_offset (& p) == FAIL) | |
2124 | return FAIL; | |
2125 | } | |
2126 | else | |
2127 | pre_inc = PRE_INDEX | INDEX_UP; | |
2128 | } | |
2129 | else | |
2130 | { | |
2131 | /* '['Rn, #expr']'[!] */ | |
2132 | ||
2133 | if (skip_past_comma (& p) == FAIL) | |
2134 | { | |
2135 | inst.error = _("pre-indexed expression expected"); | |
2136 | return FAIL; | |
2137 | } | |
2138 | ||
2139 | pre_inc = PRE_INDEX; | |
2140 | ||
2141 | if (cp_address_offset (& p) == FAIL) | |
2142 | return FAIL; | |
2143 | ||
2144 | skip_whitespace (p); | |
2145 | ||
2146 | if (*p++ != ']') | |
2147 | { | |
2148 | inst.error = _("missing ]"); | |
2149 | return FAIL; | |
2150 | } | |
2151 | ||
2152 | skip_whitespace (p); | |
2153 | ||
2154 | if (*p == '!') | |
2155 | { | |
2156 | if (reg == REG_PC) | |
2157 | { | |
2158 | inst.error = _("pc may not be used with write-back"); | |
2159 | return FAIL; | |
2160 | } | |
2161 | ||
2162 | p++; | |
2163 | write_back = WRITE_BACK; | |
2164 | } | |
2165 | } | |
2166 | } | |
2167 | else | |
2168 | { | |
2169 | if (my_get_expression (&inst.reloc.exp, &p)) | |
2170 | return FAIL; | |
2171 | ||
2172 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
2173 | inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */ | |
2174 | inst.reloc.pc_rel = 1; | |
2175 | inst.instruction |= (REG_PC << 16); | |
2176 | pre_inc = PRE_INDEX; | |
2177 | } | |
2178 | ||
2179 | inst.instruction |= write_back | pre_inc; | |
2180 | *str = p; | |
2181 | return SUCCESS; | |
2182 | } | |
2183 | ||
2184 | static void | |
2185 | do_nop (str, flags) | |
2186 | char * str; | |
2187 | unsigned long flags; | |
2188 | { | |
2189 | /* Do nothing really. */ | |
2190 | inst.instruction |= flags; /* This is pointless. */ | |
2191 | end_of_line (str); | |
2192 | return; | |
2193 | } | |
2194 | ||
2195 | static void | |
2196 | do_mrs (str, flags) | |
2197 | char *str; | |
2198 | unsigned long flags; | |
2199 | { | |
2200 | int skip = 0; | |
2201 | ||
2202 | /* Only one syntax. */ | |
2203 | skip_whitespace (str); | |
2204 | ||
2205 | if (reg_required_here (&str, 12) == FAIL) | |
2206 | { | |
2207 | inst.error = BAD_ARGS; | |
2208 | return; | |
2209 | } | |
2210 | ||
2211 | if (skip_past_comma (&str) == FAIL) | |
2212 | { | |
2213 | inst.error = _("comma expected after register name"); | |
2214 | return; | |
2215 | } | |
2216 | ||
2217 | skip_whitespace (str); | |
2218 | ||
2219 | if ( strcmp (str, "CPSR") == 0 | |
2220 | || strcmp (str, "SPSR") == 0 | |
2221 | /* Lower case versions for backwards compatability. */ | |
2222 | || strcmp (str, "cpsr") == 0 | |
2223 | || strcmp (str, "spsr") == 0) | |
2224 | skip = 4; | |
2225 | ||
2226 | /* This is for backwards compatability with older toolchains. */ | |
2227 | else if ( strcmp (str, "cpsr_all") == 0 | |
2228 | || strcmp (str, "spsr_all") == 0) | |
2229 | skip = 8; | |
2230 | else | |
2231 | { | |
2232 | inst.error = _("{C|S}PSR expected"); | |
2233 | return; | |
2234 | } | |
2235 | ||
2236 | if (* str == 's' || * str == 'S') | |
2237 | inst.instruction |= SPSR_BIT; | |
2238 | str += skip; | |
2239 | ||
2240 | inst.instruction |= flags; | |
2241 | end_of_line (str); | |
2242 | } | |
2243 | ||
2244 | /* Two possible forms: | |
2245 | "{C|S}PSR_<field>, Rm", | |
2246 | "{C|S}PSR_f, #expression". */ | |
2247 | ||
2248 | static void | |
2249 | do_msr (str, flags) | |
2250 | char * str; | |
2251 | unsigned long flags; | |
2252 | { | |
2253 | skip_whitespace (str); | |
2254 | ||
2255 | if (psr_required_here (& str) == FAIL) | |
2256 | return; | |
2257 | ||
2258 | if (skip_past_comma (& str) == FAIL) | |
2259 | { | |
2260 | inst.error = _("comma missing after psr flags"); | |
2261 | return; | |
2262 | } | |
2263 | ||
2264 | skip_whitespace (str); | |
2265 | ||
2266 | if (reg_required_here (& str, 0) != FAIL) | |
2267 | { | |
2268 | inst.error = NULL; | |
2269 | inst.instruction |= flags; | |
2270 | end_of_line (str); | |
2271 | return; | |
2272 | } | |
2273 | ||
2274 | if (! is_immediate_prefix (* str)) | |
2275 | { | |
2276 | inst.error = | |
2277 | _("only a register or immediate value can follow a psr flag"); | |
2278 | return; | |
2279 | } | |
2280 | ||
2281 | str ++; | |
2282 | inst.error = NULL; | |
2283 | ||
2284 | if (my_get_expression (& inst.reloc.exp, & str)) | |
2285 | { | |
2286 | inst.error = | |
2287 | _("only a register or immediate value can follow a psr flag"); | |
2288 | return; | |
2289 | } | |
2290 | ||
2291 | #if 0 /* The first edition of the ARM architecture manual stated that | |
2292 | writing anything other than the flags with an immediate operation | |
2293 | had UNPREDICTABLE effects. This constraint was removed in the | |
2294 | second edition of the specification. */ | |
2295 | if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5 | |
2296 | && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT)) | |
2297 | { | |
2298 | inst.error = _("immediate value cannot be used to set this field"); | |
2299 | return; | |
2300 | } | |
2301 | #endif | |
2302 | ||
2303 | flags |= INST_IMMEDIATE; | |
2304 | ||
2305 | if (inst.reloc.exp.X_add_symbol) | |
2306 | { | |
2307 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
2308 | inst.reloc.pc_rel = 0; | |
2309 | } | |
2310 | else | |
2311 | { | |
2312 | unsigned value = validate_immediate (inst.reloc.exp.X_add_number); | |
2313 | ||
2314 | if (value == (unsigned) FAIL) | |
2315 | { | |
2316 | inst.error = _("Invalid constant"); | |
2317 | return; | |
2318 | } | |
2319 | ||
2320 | inst.instruction |= value; | |
2321 | } | |
2322 | ||
2323 | inst.error = NULL; | |
2324 | inst.instruction |= flags; | |
2325 | end_of_line (str); | |
2326 | } | |
2327 | ||
2328 | /* Long Multiply Parser | |
2329 | UMULL RdLo, RdHi, Rm, Rs | |
2330 | SMULL RdLo, RdHi, Rm, Rs | |
2331 | UMLAL RdLo, RdHi, Rm, Rs | |
2332 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
2333 | ||
2334 | static void | |
2335 | do_mull (str, flags) | |
2336 | char * str; | |
2337 | unsigned long flags; | |
2338 | { | |
2339 | int rdlo, rdhi, rm, rs; | |
2340 | ||
2341 | /* Only one format "rdlo, rdhi, rm, rs". */ | |
2342 | skip_whitespace (str); | |
2343 | ||
2344 | if ((rdlo = reg_required_here (&str, 12)) == FAIL) | |
2345 | { | |
2346 | inst.error = BAD_ARGS; | |
2347 | return; | |
2348 | } | |
2349 | ||
2350 | if (skip_past_comma (&str) == FAIL | |
2351 | || (rdhi = reg_required_here (&str, 16)) == FAIL) | |
2352 | { | |
2353 | inst.error = BAD_ARGS; | |
2354 | return; | |
2355 | } | |
2356 | ||
2357 | if (skip_past_comma (&str) == FAIL | |
2358 | || (rm = reg_required_here (&str, 0)) == FAIL) | |
2359 | { | |
2360 | inst.error = BAD_ARGS; | |
2361 | return; | |
2362 | } | |
2363 | ||
2364 | /* rdhi, rdlo and rm must all be different. */ | |
2365 | if (rdlo == rdhi || rdlo == rm || rdhi == rm) | |
2366 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); | |
2367 | ||
2368 | if (skip_past_comma (&str) == FAIL | |
2369 | || (rs = reg_required_here (&str, 8)) == FAIL) | |
2370 | { | |
2371 | inst.error = BAD_ARGS; | |
2372 | return; | |
2373 | } | |
2374 | ||
2375 | if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC) | |
2376 | { | |
2377 | inst.error = BAD_PC; | |
2378 | return; | |
2379 | } | |
2380 | ||
2381 | inst.instruction |= flags; | |
2382 | end_of_line (str); | |
2383 | return; | |
2384 | } | |
2385 | ||
2386 | static void | |
2387 | do_mul (str, flags) | |
2388 | char * str; | |
2389 | unsigned long flags; | |
2390 | { | |
2391 | int rd, rm; | |
2392 | ||
2393 | /* Only one format "rd, rm, rs". */ | |
2394 | skip_whitespace (str); | |
2395 | ||
2396 | if ((rd = reg_required_here (&str, 16)) == FAIL) | |
2397 | { | |
2398 | inst.error = BAD_ARGS; | |
2399 | return; | |
2400 | } | |
2401 | ||
2402 | if (rd == REG_PC) | |
2403 | { | |
2404 | inst.error = BAD_PC; | |
2405 | return; | |
2406 | } | |
2407 | ||
2408 | if (skip_past_comma (&str) == FAIL | |
2409 | || (rm = reg_required_here (&str, 0)) == FAIL) | |
2410 | { | |
2411 | inst.error = BAD_ARGS; | |
2412 | return; | |
2413 | } | |
2414 | ||
2415 | if (rm == REG_PC) | |
2416 | { | |
2417 | inst.error = BAD_PC; | |
2418 | return; | |
2419 | } | |
2420 | ||
2421 | if (rm == rd) | |
2422 | as_tsktsk (_("rd and rm should be different in mul")); | |
2423 | ||
2424 | if (skip_past_comma (&str) == FAIL | |
2425 | || (rm = reg_required_here (&str, 8)) == FAIL) | |
2426 | { | |
2427 | inst.error = BAD_ARGS; | |
2428 | return; | |
2429 | } | |
2430 | ||
2431 | if (rm == REG_PC) | |
2432 | { | |
2433 | inst.error = BAD_PC; | |
2434 | return; | |
2435 | } | |
2436 | ||
2437 | inst.instruction |= flags; | |
2438 | end_of_line (str); | |
2439 | return; | |
2440 | } | |
2441 | ||
2442 | static void | |
2443 | do_mla (str, flags) | |
2444 | char * str; | |
2445 | unsigned long flags; | |
2446 | { | |
2447 | int rd, rm; | |
2448 | ||
2449 | /* Only one format "rd, rm, rs, rn". */ | |
2450 | skip_whitespace (str); | |
2451 | ||
2452 | if ((rd = reg_required_here (&str, 16)) == FAIL) | |
2453 | { | |
2454 | inst.error = BAD_ARGS; | |
2455 | return; | |
2456 | } | |
2457 | ||
2458 | if (rd == REG_PC) | |
2459 | { | |
2460 | inst.error = BAD_PC; | |
2461 | return; | |
2462 | } | |
2463 | ||
2464 | if (skip_past_comma (&str) == FAIL | |
2465 | || (rm = reg_required_here (&str, 0)) == FAIL) | |
2466 | { | |
2467 | inst.error = BAD_ARGS; | |
2468 | return; | |
2469 | } | |
2470 | ||
2471 | if (rm == REG_PC) | |
2472 | { | |
2473 | inst.error = BAD_PC; | |
2474 | return; | |
2475 | } | |
2476 | ||
2477 | if (rm == rd) | |
2478 | as_tsktsk (_("rd and rm should be different in mla")); | |
2479 | ||
2480 | if (skip_past_comma (&str) == FAIL | |
2481 | || (rd = reg_required_here (&str, 8)) == FAIL | |
2482 | || skip_past_comma (&str) == FAIL | |
2483 | || (rm = reg_required_here (&str, 12)) == FAIL) | |
2484 | { | |
2485 | inst.error = BAD_ARGS; | |
2486 | return; | |
2487 | } | |
2488 | ||
2489 | if (rd == REG_PC || rm == REG_PC) | |
2490 | { | |
2491 | inst.error = BAD_PC; | |
2492 | return; | |
2493 | } | |
2494 | ||
2495 | inst.instruction |= flags; | |
2496 | end_of_line (str); | |
2497 | return; | |
2498 | } | |
2499 | ||
2500 | /* Expects *str -> the characters "acc0", possibly with leading blanks. | |
2501 | Advances *str to the next non-alphanumeric. | |
2502 | Returns 0, or else FAIL (in which case sets inst.error). | |
2503 | ||
2504 | (In a future XScale, there may be accumulators other than zero. | |
2505 | At that time this routine and its callers can be upgraded to suit.) */ | |
2506 | ||
2507 | static int | |
2508 | accum0_required_here (str) | |
2509 | char ** str; | |
2510 | { | |
2511 | static char buff [128]; /* Note the address is taken. Hence, static. */ | |
2512 | char * p = * str; | |
2513 | char c; | |
2514 | int result = 0; /* The accum number. */ | |
2515 | ||
2516 | skip_whitespace (p); | |
2517 | ||
2518 | *str = p; /* Advance caller's string pointer too. */ | |
2519 | c = *p++; | |
2520 | while (isalnum (c)) | |
2521 | c = *p++; | |
2522 | ||
2523 | *--p = 0; /* Aap nul into input buffer at non-alnum. */ | |
2524 | ||
2525 | if (! ( streq (*str, "acc0") || streq (*str, "ACC0"))) | |
2526 | { | |
2527 | sprintf (buff, _("acc0 expected, not '%.100s'"), *str); | |
2528 | inst.error = buff; | |
2529 | result = FAIL; | |
2530 | } | |
2531 | ||
2532 | *p = c; /* Unzap. */ | |
2533 | *str = p; /* Caller's string pointer to after match. */ | |
2534 | return result; | |
2535 | } | |
2536 | ||
2537 | /* Expects **str -> after a comma. May be leading blanks. | |
2538 | Advances *str, recognizing a load mode, and setting inst.instruction. | |
2539 | Returns rn, or else FAIL (in which case may set inst.error | |
2540 | and not advance str) | |
2541 | ||
2542 | Note: doesn't know Rd, so no err checks that require such knowledge. */ | |
2543 | ||
2544 | static int | |
2545 | ld_mode_required_here (string) | |
2546 | char ** string; | |
2547 | { | |
2548 | char * str = * string; | |
2549 | int rn; | |
2550 | int pre_inc = 0; | |
2551 | ||
2552 | skip_whitespace (str); | |
2553 | ||
2554 | if (* str == '[') | |
2555 | { | |
2556 | str++; | |
2557 | ||
2558 | skip_whitespace (str); | |
2559 | ||
2560 | if ((rn = reg_required_here (& str, 16)) == FAIL) | |
2561 | return FAIL; | |
2562 | ||
2563 | skip_whitespace (str); | |
2564 | ||
2565 | if (* str == ']') | |
2566 | { | |
2567 | str ++; | |
2568 | ||
2569 | if (skip_past_comma (& str) == SUCCESS) | |
2570 | { | |
2571 | /* [Rn],... (post inc) */ | |
2572 | if (ldst_extend (& str, 1) == FAIL) | |
2573 | return FAIL; | |
2574 | } | |
2575 | else /* [Rn] */ | |
2576 | { | |
2577 | skip_whitespace (str); | |
2578 | ||
2579 | if (* str == '!') | |
2580 | { | |
2581 | str ++; | |
2582 | inst.instruction |= WRITE_BACK; | |
2583 | } | |
2584 | ||
2585 | inst.instruction |= INDEX_UP | HWOFFSET_IMM; | |
2586 | pre_inc = 1; | |
2587 | } | |
2588 | } | |
2589 | else /* [Rn,...] */ | |
2590 | { | |
2591 | if (skip_past_comma (& str) == FAIL) | |
2592 | { | |
2593 | inst.error = _("pre-indexed expression expected"); | |
2594 | return FAIL; | |
2595 | } | |
2596 | ||
2597 | pre_inc = 1; | |
2598 | ||
2599 | if (ldst_extend (& str, 1) == FAIL) | |
2600 | return FAIL; | |
2601 | ||
2602 | skip_whitespace (str); | |
2603 | ||
2604 | if (* str ++ != ']') | |
2605 | { | |
2606 | inst.error = _("missing ]"); | |
2607 | return FAIL; | |
2608 | } | |
2609 | ||
2610 | skip_whitespace (str); | |
2611 | ||
2612 | if (* str == '!') | |
2613 | { | |
2614 | str ++; | |
2615 | inst.instruction |= WRITE_BACK; | |
2616 | } | |
2617 | } | |
2618 | } | |
2619 | else if (* str == '=') /* ldr's "r,=label" syntax */ | |
2620 | /* We should never reach here, because <text> = <expression> is | |
2621 | caught gas/read.c read_a_source_file() as a .set operation. */ | |
2622 | return FAIL; | |
2623 | else /* PC +- 8 bit immediate offset. */ | |
2624 | { | |
2625 | if (my_get_expression (& inst.reloc.exp, & str)) | |
2626 | return FAIL; | |
2627 | ||
2628 | inst.instruction |= HWOFFSET_IMM; /* The I bit. */ | |
2629 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
2630 | inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */ | |
2631 | inst.reloc.pc_rel = 1; | |
2632 | inst.instruction |= (REG_PC << 16); | |
2633 | ||
2634 | rn = REG_PC; | |
2635 | pre_inc = 1; | |
2636 | } | |
2637 | ||
2638 | inst.instruction |= (pre_inc ? PRE_INDEX : 0); | |
2639 | * string = str; | |
2640 | ||
2641 | return rn; | |
2642 | } | |
2643 | ||
2644 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) | |
2645 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
2646 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
2647 | Error if any register is R15. */ | |
2648 | ||
2649 | static void | |
2650 | do_smla (str, flags) | |
2651 | char * str; | |
2652 | unsigned long flags; | |
2653 | { | |
2654 | int rd, rm, rs, rn; | |
2655 | ||
2656 | skip_whitespace (str); | |
2657 | ||
2658 | if ((rd = reg_required_here (& str, 16)) == FAIL | |
2659 | || skip_past_comma (& str) == FAIL | |
2660 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2661 | || skip_past_comma (& str) == FAIL | |
2662 | || (rs = reg_required_here (& str, 8)) == FAIL | |
2663 | || skip_past_comma (& str) == FAIL | |
2664 | || (rn = reg_required_here (& str, 12)) == FAIL) | |
2665 | inst.error = BAD_ARGS; | |
2666 | ||
2667 | else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC) | |
2668 | inst.error = BAD_PC; | |
2669 | ||
2670 | else if (flags) | |
2671 | inst.error = BAD_FLAGS; | |
2672 | ||
2673 | else | |
2674 | end_of_line (str); | |
2675 | } | |
2676 | ||
2677 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) | |
2678 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
2679 | Error if any register is R15. | |
2680 | Warning if Rdlo == Rdhi. */ | |
2681 | ||
2682 | static void | |
2683 | do_smlal (str, flags) | |
2684 | char * str; | |
2685 | unsigned long flags; | |
2686 | { | |
2687 | int rdlo, rdhi, rm, rs; | |
2688 | ||
2689 | skip_whitespace (str); | |
2690 | ||
2691 | if ((rdlo = reg_required_here (& str, 12)) == FAIL | |
2692 | || skip_past_comma (& str) == FAIL | |
2693 | || (rdhi = reg_required_here (& str, 16)) == FAIL | |
2694 | || skip_past_comma (& str) == FAIL | |
2695 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2696 | || skip_past_comma (& str) == FAIL | |
2697 | || (rs = reg_required_here (& str, 8)) == FAIL) | |
2698 | { | |
2699 | inst.error = BAD_ARGS; | |
2700 | return; | |
2701 | } | |
2702 | ||
2703 | if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC) | |
2704 | { | |
2705 | inst.error = BAD_PC; | |
2706 | return; | |
2707 | } | |
2708 | ||
2709 | if (rdlo == rdhi) | |
2710 | as_tsktsk (_("rdhi and rdlo must be different")); | |
2711 | ||
2712 | if (flags) | |
2713 | inst.error = BAD_FLAGS; | |
2714 | else | |
2715 | end_of_line (str); | |
2716 | } | |
2717 | ||
2718 | /* ARM V5E (El Segundo) signed-multiply (argument parse) | |
2719 | SMULxy{cond} Rd,Rm,Rs | |
2720 | Error if any register is R15. */ | |
2721 | ||
2722 | static void | |
2723 | do_smul (str, flags) | |
2724 | char * str; | |
2725 | unsigned long flags; | |
2726 | { | |
2727 | int rd, rm, rs; | |
2728 | ||
2729 | skip_whitespace (str); | |
2730 | ||
2731 | if ((rd = reg_required_here (& str, 16)) == FAIL | |
2732 | || skip_past_comma (& str) == FAIL | |
2733 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2734 | || skip_past_comma (& str) == FAIL | |
2735 | || (rs = reg_required_here (& str, 8)) == FAIL) | |
2736 | inst.error = BAD_ARGS; | |
2737 | ||
2738 | else if (rd == REG_PC || rm == REG_PC || rs == REG_PC) | |
2739 | inst.error = BAD_PC; | |
2740 | ||
2741 | else if (flags) | |
2742 | inst.error = BAD_FLAGS; | |
2743 | ||
2744 | else | |
2745 | end_of_line (str); | |
2746 | } | |
2747 | ||
2748 | /* ARM V5E (El Segundo) saturating-add/subtract (argument parse) | |
2749 | Q[D]{ADD,SUB}{cond} Rd,Rm,Rn | |
2750 | Error if any register is R15. */ | |
2751 | ||
2752 | static void | |
2753 | do_qadd (str, flags) | |
2754 | char * str; | |
2755 | unsigned long flags; | |
2756 | { | |
2757 | int rd, rm, rn; | |
2758 | ||
2759 | skip_whitespace (str); | |
2760 | ||
2761 | if ((rd = reg_required_here (& str, 12)) == FAIL | |
2762 | || skip_past_comma (& str) == FAIL | |
2763 | || (rm = reg_required_here (& str, 0)) == FAIL | |
2764 | || skip_past_comma (& str) == FAIL | |
2765 | || (rn = reg_required_here (& str, 16)) == FAIL) | |
2766 | inst.error = BAD_ARGS; | |
2767 | ||
2768 | else if (rd == REG_PC || rm == REG_PC || rn == REG_PC) | |
2769 | inst.error = BAD_PC; | |
2770 | ||
2771 | else if (flags) | |
2772 | inst.error = BAD_FLAGS; | |
2773 | ||
2774 | else | |
2775 | end_of_line (str); | |
2776 | } | |
2777 | ||
2778 | /* ARM V5E (el Segundo) | |
2779 | MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
2780 | MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
2781 | ||
2782 | These are equivalent to the XScale instructions MAR and MRA, | |
2783 | respectively, when coproc == 0, opcode == 0, and CRm == 0. | |
2784 | ||
2785 | Result unpredicatable if Rd or Rn is R15. */ | |
2786 | ||
2787 | static void | |
2788 | do_co_reg2c (str, flags) | |
2789 | char * str; | |
2790 | unsigned long flags; | |
2791 | { | |
2792 | int rd, rn; | |
2793 | ||
2794 | skip_whitespace (str); | |
2795 | ||
2796 | if (co_proc_number (& str) == FAIL) | |
2797 | { | |
2798 | if (!inst.error) | |
2799 | inst.error = BAD_ARGS; | |
2800 | return; | |
2801 | } | |
2802 | ||
2803 | if (skip_past_comma (& str) == FAIL | |
2804 | || cp_opc_expr (& str, 4, 4) == FAIL) | |
2805 | { | |
2806 | if (!inst.error) | |
2807 | inst.error = BAD_ARGS; | |
2808 | return; | |
2809 | } | |
2810 | ||
2811 | if (skip_past_comma (& str) == FAIL | |
2812 | || (rd = reg_required_here (& str, 12)) == FAIL) | |
2813 | { | |
2814 | if (!inst.error) | |
2815 | inst.error = BAD_ARGS; | |
2816 | return; | |
2817 | } | |
2818 | ||
2819 | if (skip_past_comma (& str) == FAIL | |
2820 | || (rn = reg_required_here (& str, 16)) == FAIL) | |
2821 | { | |
2822 | if (!inst.error) | |
2823 | inst.error = BAD_ARGS; | |
2824 | return; | |
2825 | } | |
2826 | ||
2827 | /* Unpredictable result if rd or rn is R15. */ | |
2828 | if (rd == REG_PC || rn == REG_PC) | |
2829 | as_tsktsk | |
2830 | (_("Warning: Instruction unpredictable when using r15")); | |
2831 | ||
2832 | if (skip_past_comma (& str) == FAIL | |
2833 | || cp_reg_required_here (& str, 0) == FAIL) | |
2834 | { | |
2835 | if (!inst.error) | |
2836 | inst.error = BAD_ARGS; | |
2837 | return; | |
2838 | } | |
2839 | ||
2840 | if (flags) | |
2841 | inst.error = BAD_COND; | |
2842 | ||
2843 | end_of_line (str); | |
2844 | } | |
2845 | ||
2846 | /* ARM V5 count-leading-zeroes instruction (argument parse) | |
2847 | CLZ{<cond>} <Rd>, <Rm> | |
2848 | Condition defaults to COND_ALWAYS. | |
2849 | Error if Rd or Rm are R15. */ | |
2850 | ||
2851 | static void | |
2852 | do_clz (str, flags) | |
2853 | char * str; | |
2854 | unsigned long flags; | |
2855 | { | |
2856 | int rd, rm; | |
2857 | ||
2858 | if (flags) | |
2859 | { | |
2860 | as_bad (BAD_FLAGS); | |
2861 | return; | |
2862 | } | |
2863 | ||
2864 | skip_whitespace (str); | |
2865 | ||
2866 | if (((rd = reg_required_here (& str, 12)) == FAIL) | |
2867 | || (skip_past_comma (& str) == FAIL) | |
2868 | || ((rm = reg_required_here (& str, 0)) == FAIL)) | |
2869 | inst.error = BAD_ARGS; | |
2870 | ||
2871 | else if (rd == REG_PC || rm == REG_PC ) | |
2872 | inst.error = BAD_PC; | |
2873 | ||
2874 | else | |
2875 | end_of_line (str); | |
2876 | } | |
2877 | ||
2878 | /* ARM V5 (argument parse) | |
2879 | LDC2{L} <coproc>, <CRd>, <addressing mode> | |
2880 | STC2{L} <coproc>, <CRd>, <addressing mode> | |
2881 | Instruction is not conditional, and has 0xf in the codition field. | |
2882 | Otherwise, it's the same as LDC/STC. */ | |
2883 | ||
2884 | static void | |
2885 | do_lstc2 (str, flags) | |
2886 | char * str; | |
2887 | unsigned long flags; | |
2888 | { | |
2889 | if (flags) | |
2890 | inst.error = BAD_COND; | |
2891 | ||
2892 | skip_whitespace (str); | |
2893 | ||
2894 | if (co_proc_number (& str) == FAIL) | |
2895 | { | |
2896 | if (!inst.error) | |
2897 | inst.error = BAD_ARGS; | |
2898 | } | |
2899 | else if (skip_past_comma (& str) == FAIL | |
2900 | || cp_reg_required_here (& str, 12) == FAIL) | |
2901 | { | |
2902 | if (!inst.error) | |
2903 | inst.error = BAD_ARGS; | |
2904 | } | |
2905 | else if (skip_past_comma (& str) == FAIL | |
2906 | || cp_address_required_here (& str) == FAIL) | |
2907 | { | |
2908 | if (! inst.error) | |
2909 | inst.error = BAD_ARGS; | |
2910 | } | |
2911 | else | |
2912 | end_of_line (str); | |
2913 | } | |
2914 | ||
2915 | /* ARM V5 (argument parse) | |
2916 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2> | |
2917 | Instruction is not conditional, and has 0xf in the condition field. | |
2918 | Otherwise, it's the same as CDP. */ | |
2919 | ||
2920 | static void | |
2921 | do_cdp2 (str, flags) | |
2922 | char * str; | |
2923 | unsigned long flags; | |
2924 | { | |
2925 | skip_whitespace (str); | |
2926 | ||
2927 | if (co_proc_number (& str) == FAIL) | |
2928 | { | |
2929 | if (!inst.error) | |
2930 | inst.error = BAD_ARGS; | |
2931 | return; | |
2932 | } | |
2933 | ||
2934 | if (skip_past_comma (& str) == FAIL | |
2935 | || cp_opc_expr (& str, 20,4) == FAIL) | |
2936 | { | |
2937 | if (!inst.error) | |
2938 | inst.error = BAD_ARGS; | |
2939 | return; | |
2940 | } | |
2941 | ||
2942 | if (skip_past_comma (& str) == FAIL | |
2943 | || cp_reg_required_here (& str, 12) == FAIL) | |
2944 | { | |
2945 | if (!inst.error) | |
2946 | inst.error = BAD_ARGS; | |
2947 | return; | |
2948 | } | |
2949 | ||
2950 | if (skip_past_comma (& str) == FAIL | |
2951 | || cp_reg_required_here (& str, 16) == FAIL) | |
2952 | { | |
2953 | if (!inst.error) | |
2954 | inst.error = BAD_ARGS; | |
2955 | return; | |
2956 | } | |
2957 | ||
2958 | if (skip_past_comma (& str) == FAIL | |
2959 | || cp_reg_required_here (& str, 0) == FAIL) | |
2960 | { | |
2961 | if (!inst.error) | |
2962 | inst.error = BAD_ARGS; | |
2963 | return; | |
2964 | } | |
2965 | ||
2966 | if (skip_past_comma (& str) == SUCCESS) | |
2967 | { | |
2968 | if (cp_opc_expr (& str, 5, 3) == FAIL) | |
2969 | { | |
2970 | if (!inst.error) | |
2971 | inst.error = BAD_ARGS; | |
2972 | return; | |
2973 | } | |
2974 | } | |
2975 | ||
2976 | if (flags) | |
2977 | inst.error = BAD_FLAGS; | |
2978 | ||
2979 | end_of_line (str); | |
2980 | } | |
2981 | ||
2982 | /* ARM V5 (argument parse) | |
2983 | MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2> | |
2984 | MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2> | |
2985 | Instruction is not conditional, and has 0xf in the condition field. | |
2986 | Otherwise, it's the same as MCR/MRC. */ | |
2987 | ||
2988 | static void | |
2989 | do_co_reg2 (str, flags) | |
2990 | char * str; | |
2991 | unsigned long flags; | |
2992 | { | |
2993 | skip_whitespace (str); | |
2994 | ||
2995 | if (co_proc_number (& str) == FAIL) | |
2996 | { | |
2997 | if (!inst.error) | |
2998 | inst.error = BAD_ARGS; | |
2999 | return; | |
3000 | } | |
3001 | ||
3002 | if (skip_past_comma (& str) == FAIL | |
3003 | || cp_opc_expr (& str, 21, 3) == FAIL) | |
3004 | { | |
3005 | if (!inst.error) | |
3006 | inst.error = BAD_ARGS; | |
3007 | return; | |
3008 | } | |
3009 | ||
3010 | if (skip_past_comma (& str) == FAIL | |
3011 | || reg_required_here (& str, 12) == FAIL) | |
3012 | { | |
3013 | if (!inst.error) | |
3014 | inst.error = BAD_ARGS; | |
3015 | return; | |
3016 | } | |
3017 | ||
3018 | if (skip_past_comma (& str) == FAIL | |
3019 | || cp_reg_required_here (& str, 16) == FAIL) | |
3020 | { | |
3021 | if (!inst.error) | |
3022 | inst.error = BAD_ARGS; | |
3023 | return; | |
3024 | } | |
3025 | ||
3026 | if (skip_past_comma (& str) == FAIL | |
3027 | || cp_reg_required_here (& str, 0) == FAIL) | |
3028 | { | |
3029 | if (!inst.error) | |
3030 | inst.error = BAD_ARGS; | |
3031 | return; | |
3032 | } | |
3033 | ||
3034 | if (skip_past_comma (& str) == SUCCESS) | |
3035 | { | |
3036 | if (cp_opc_expr (& str, 5, 3) == FAIL) | |
3037 | { | |
3038 | if (!inst.error) | |
3039 | inst.error = BAD_ARGS; | |
3040 | return; | |
3041 | } | |
3042 | } | |
3043 | ||
3044 | if (flags) | |
3045 | inst.error = BAD_COND; | |
3046 | ||
3047 | end_of_line (str); | |
3048 | } | |
3049 | ||
3050 | /* THUMB V5 breakpoint instruction (argument parse) | |
3051 | BKPT <immed_8>. */ | |
3052 | ||
3053 | static void | |
3054 | do_t_bkpt (str) | |
3055 | char * str; | |
3056 | { | |
3057 | expressionS expr; | |
3058 | unsigned long number; | |
3059 | ||
3060 | skip_whitespace (str); | |
3061 | ||
3062 | /* Allow optional leading '#'. */ | |
3063 | if (is_immediate_prefix (*str)) | |
3064 | str ++; | |
3065 | ||
3066 | memset (& expr, '\0', sizeof (expr)); | |
3067 | if (my_get_expression (& expr, & str) || (expr.X_op != O_constant)) | |
3068 | { | |
3069 | inst.error = _("bad or missing expression"); | |
3070 | return; | |
3071 | } | |
3072 | ||
3073 | number = expr.X_add_number; | |
3074 | ||
3075 | /* Check it fits an 8 bit unsigned. */ | |
3076 | if (number != (number & 0xff)) | |
3077 | { | |
3078 | inst.error = _("immediate value out of range"); | |
3079 | return; | |
3080 | } | |
3081 | ||
3082 | inst.instruction |= number; | |
3083 | ||
3084 | end_of_line (str); | |
3085 | } | |
3086 | ||
3087 | /* ARM V5 branch-link-exchange (argument parse) for BLX(1) only. | |
3088 | Expects inst.instruction is set for BLX(1). | |
3089 | Note: this is cloned from do_branch, and the reloc changed to be a | |
3090 | new one that can cope with setting one extra bit (the H bit). */ | |
3091 | ||
3092 | static void | |
3093 | do_branch25 (str, flags) | |
3094 | char * str; | |
3095 | unsigned long flags ATTRIBUTE_UNUSED; | |
3096 | { | |
3097 | if (my_get_expression (& inst.reloc.exp, & str)) | |
3098 | return; | |
3099 | ||
3100 | #ifdef OBJ_ELF | |
3101 | { | |
3102 | char * save_in; | |
3103 | ||
3104 | /* ScottB: February 5, 1998 */ | |
3105 | /* Check to see of PLT32 reloc required for the instruction. */ | |
3106 | ||
3107 | /* arm_parse_reloc() works on input_line_pointer. | |
3108 | We actually want to parse the operands to the branch instruction | |
3109 | passed in 'str'. Save the input pointer and restore it later. */ | |
3110 | save_in = input_line_pointer; | |
3111 | input_line_pointer = str; | |
3112 | ||
3113 | if (inst.reloc.exp.X_op == O_symbol | |
3114 | && *str == '(' | |
3115 | && arm_parse_reloc () == BFD_RELOC_ARM_PLT32) | |
3116 | { | |
3117 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
3118 | inst.reloc.pc_rel = 0; | |
3119 | /* Modify str to point to after parsed operands, otherwise | |
3120 | end_of_line() will complain about the (PLT) left in str. */ | |
3121 | str = input_line_pointer; | |
3122 | } | |
3123 | else | |
3124 | { | |
3125 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX; | |
3126 | inst.reloc.pc_rel = 1; | |
3127 | } | |
3128 | ||
3129 | input_line_pointer = save_in; | |
3130 | } | |
3131 | #else | |
3132 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX; | |
3133 | inst.reloc.pc_rel = 1; | |
3134 | #endif /* OBJ_ELF */ | |
3135 | ||
3136 | end_of_line (str); | |
3137 | } | |
3138 | ||
3139 | /* ARM V5 branch-link-exchange instruction (argument parse) | |
3140 | BLX <target_addr> ie BLX(1) | |
3141 | BLX{<condition>} <Rm> ie BLX(2) | |
3142 | Unfortunately, there are two different opcodes for this mnemonic. | |
3143 | So, the insns[].value is not used, and the code here zaps values | |
3144 | into inst.instruction. | |
3145 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
3146 | ||
3147 | static void | |
3148 | do_blx (str, flags) | |
3149 | char * str; | |
3150 | unsigned long flags; | |
3151 | { | |
3152 | char * mystr = str; | |
3153 | int rm; | |
3154 | ||
3155 | if (flags) | |
3156 | { | |
3157 | as_bad (BAD_FLAGS); | |
3158 | return; | |
3159 | } | |
3160 | ||
3161 | skip_whitespace (mystr); | |
3162 | rm = reg_required_here (& mystr, 0); | |
3163 | ||
3164 | /* The above may set inst.error. Ignore his opinion. */ | |
3165 | inst.error = 0; | |
3166 | ||
3167 | if (rm != FAIL) | |
3168 | { | |
3169 | /* Arg is a register. | |
3170 | Use the condition code our caller put in inst.instruction. | |
3171 | Pass ourselves off as a BX with a funny opcode. */ | |
3172 | inst.instruction |= 0x012fff30; | |
3173 | do_bx (str, flags); | |
3174 | } | |
3175 | else | |
3176 | { | |
3177 | /* This must be is BLX <target address>, no condition allowed. */ | |
3178 | if (inst.instruction != COND_ALWAYS) | |
3179 | { | |
3180 | inst.error = BAD_COND; | |
3181 | return; | |
3182 | } | |
3183 | ||
3184 | inst.instruction = 0xfafffffe; | |
3185 | ||
3186 | /* Process like a B/BL, but with a different reloc. | |
3187 | Note that B/BL expecte fffffe, not 0, offset in the opcode table. */ | |
3188 | do_branch25 (str, flags); | |
3189 | } | |
3190 | } | |
3191 | ||
3192 | /* ARM V5 Thumb BLX (argument parse) | |
3193 | BLX <target_addr> which is BLX(1) | |
3194 | BLX <Rm> which is BLX(2) | |
3195 | Unfortunately, there are two different opcodes for this mnemonic. | |
3196 | So, the tinsns[].value is not used, and the code here zaps values | |
3197 | into inst.instruction. */ | |
3198 | ||
3199 | static void | |
3200 | do_t_blx (str) | |
3201 | char * str; | |
3202 | { | |
3203 | char * mystr = str; | |
3204 | int rm; | |
3205 | ||
3206 | skip_whitespace (mystr); | |
3207 | inst.instruction = 0x4780; | |
3208 | ||
3209 | /* Note that this call is to the ARM register recognizer. BLX(2) | |
3210 | uses the ARM register space, not the Thumb one, so a call to | |
3211 | thumb_reg() would be wrong. */ | |
3212 | rm = reg_required_here (& mystr, 3); | |
3213 | inst.error = 0; | |
3214 | ||
3215 | if (rm != FAIL) | |
3216 | { | |
3217 | /* It's BLX(2). The .instruction was zapped with rm & is final. */ | |
3218 | inst.size = 2; | |
3219 | } | |
3220 | else | |
3221 | { | |
3222 | /* No ARM register. This must be BLX(1). Change the .instruction. */ | |
3223 | inst.instruction = 0xf7ffeffe; | |
3224 | inst.size = 4; | |
3225 | ||
3226 | if (my_get_expression (& inst.reloc.exp, & mystr)) | |
3227 | return; | |
3228 | ||
3229 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; | |
3230 | inst.reloc.pc_rel = 1; | |
3231 | } | |
3232 | ||
3233 | end_of_line (mystr); | |
3234 | } | |
3235 | ||
3236 | /* ARM V5 breakpoint instruction (argument parse) | |
3237 | BKPT <16 bit unsigned immediate> | |
3238 | Instruction is not conditional. | |
3239 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
3240 | and it is an error if the caller tried to override that. | |
3241 | Note "flags" is nonzero if a flag was supplied (which is an error). */ | |
3242 | ||
3243 | static void | |
3244 | do_bkpt (str, flags) | |
3245 | char * str; | |
3246 | unsigned long flags; | |
3247 | { | |
3248 | expressionS expr; | |
3249 | unsigned long number; | |
3250 | ||
3251 | skip_whitespace (str); | |
3252 | ||
3253 | /* Allow optional leading '#'. */ | |
3254 | if (is_immediate_prefix (* str)) | |
3255 | str++; | |
3256 | ||
3257 | memset (& expr, '\0', sizeof (expr)); | |
3258 | ||
3259 | if (my_get_expression (& expr, & str) || (expr.X_op != O_constant)) | |
3260 | { | |
3261 | inst.error = _("bad or missing expression"); | |
3262 | return; | |
3263 | } | |
3264 | ||
3265 | number = expr.X_add_number; | |
3266 | ||
3267 | /* Check it fits a 16 bit unsigned. */ | |
3268 | if (number != (number & 0xffff)) | |
3269 | { | |
3270 | inst.error = _("immediate value out of range"); | |
3271 | return; | |
3272 | } | |
3273 | ||
3274 | /* Top 12 of 16 bits to bits 19:8. */ | |
3275 | inst.instruction |= (number & 0xfff0) << 4; | |
3276 | ||
3277 | /* Bottom 4 of 16 bits to bits 3:0. */ | |
3278 | inst.instruction |= number & 0xf; | |
3279 | ||
3280 | end_of_line (str); | |
3281 | ||
3282 | if (flags) | |
3283 | inst.error = BAD_FLAGS; | |
3284 | } | |
3285 | ||
3286 | /* Xscale multiply-accumulate (argument parse) | |
3287 | MIAcc acc0,Rm,Rs | |
3288 | MIAPHcc acc0,Rm,Rs | |
3289 | MIAxycc acc0,Rm,Rs. */ | |
3290 | ||
3291 | static void | |
3292 | do_mia (str, flags) | |
3293 | char * str; | |
3294 | unsigned long flags; | |
3295 | { | |
3296 | int rs; | |
3297 | int rm; | |
3298 | ||
3299 | if (flags) | |
3300 | as_bad (BAD_FLAGS); | |
3301 | ||
3302 | else if (accum0_required_here (& str) == FAIL) | |
3303 | inst.error = ERR_NO_ACCUM; | |
3304 | ||
3305 | else if (skip_past_comma (& str) == FAIL | |
3306 | || (rm = reg_required_here (& str, 0)) == FAIL) | |
3307 | inst.error = BAD_ARGS; | |
3308 | ||
3309 | else if (skip_past_comma (& str) == FAIL | |
3310 | || (rs = reg_required_here (& str, 12)) == FAIL) | |
3311 | inst.error = BAD_ARGS; | |
3312 | ||
3313 | /* inst.instruction has now been zapped with both rm and rs. */ | |
3314 | else if (rm == REG_PC || rs == REG_PC) | |
3315 | inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */ | |
3316 | ||
3317 | else | |
3318 | end_of_line (str); | |
3319 | } | |
3320 | ||
3321 | /* Xscale move-accumulator-register (argument parse) | |
3322 | ||
3323 | MARcc acc0,RdLo,RdHi. */ | |
3324 | ||
3325 | static void | |
3326 | do_mar (str, flags) | |
3327 | char * str; | |
3328 | unsigned long flags; | |
3329 | { | |
3330 | int rdlo, rdhi; | |
3331 | ||
3332 | if (flags) | |
3333 | as_bad (BAD_FLAGS); | |
3334 | ||
3335 | else if (accum0_required_here (& str) == FAIL) | |
3336 | inst.error = ERR_NO_ACCUM; | |
3337 | ||
3338 | else if (skip_past_comma (& str) == FAIL | |
3339 | || (rdlo = reg_required_here (& str, 12)) == FAIL) | |
3340 | inst.error = BAD_ARGS; | |
3341 | ||
3342 | else if (skip_past_comma (& str) == FAIL | |
3343 | || (rdhi = reg_required_here (& str, 16)) == FAIL) | |
3344 | inst.error = BAD_ARGS; | |
3345 | ||
3346 | /* inst.instruction has now been zapped with both rdlo and rdhi. */ | |
3347 | else if (rdlo == REG_PC || rdhi == REG_PC) | |
3348 | inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */ | |
3349 | ||
3350 | else | |
3351 | end_of_line (str); | |
3352 | } | |
3353 | ||
3354 | /* Xscale move-register-accumulator (argument parse) | |
3355 | ||
3356 | MRAcc RdLo,RdHi,acc0. */ | |
3357 | ||
3358 | static void | |
3359 | do_mra (str, flags) | |
3360 | char * str; | |
3361 | unsigned long flags; | |
3362 | { | |
3363 | int rdlo; | |
3364 | int rdhi; | |
3365 | ||
3366 | if (flags) | |
3367 | { | |
3368 | as_bad (BAD_FLAGS); | |
3369 | return; | |
3370 | } | |
3371 | ||
3372 | skip_whitespace (str); | |
3373 | ||
3374 | if ((rdlo = reg_required_here (& str, 12)) == FAIL) | |
3375 | inst.error = BAD_ARGS; | |
3376 | ||
3377 | else if (skip_past_comma (& str) == FAIL | |
3378 | || (rdhi = reg_required_here (& str, 16)) == FAIL) | |
3379 | inst.error = BAD_ARGS; | |
3380 | ||
3381 | else if (skip_past_comma (& str) == FAIL | |
3382 | || accum0_required_here (& str) == FAIL) | |
3383 | inst.error = ERR_NO_ACCUM; | |
3384 | ||
3385 | /* inst.instruction has now been zapped with both rdlo and rdhi. */ | |
3386 | else if (rdlo == rdhi) | |
3387 | inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */ | |
3388 | ||
3389 | else if (rdlo == REG_PC || rdhi == REG_PC) | |
3390 | inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */ | |
3391 | else | |
3392 | end_of_line (str); | |
3393 | } | |
3394 | ||
3395 | /* Xscale: Preload-Cache | |
3396 | ||
3397 | PLD <addr_mode> | |
3398 | ||
3399 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
3400 | ||
3401 | static void | |
3402 | do_pld (str, flags) | |
3403 | char * str; | |
3404 | unsigned long flags; | |
3405 | { | |
3406 | int rd; | |
3407 | ||
3408 | if (flags) | |
3409 | { | |
3410 | as_bad (BAD_FLAGS); | |
3411 | return; | |
3412 | } | |
3413 | ||
3414 | skip_whitespace (str); | |
3415 | ||
3416 | if (* str != '[') | |
3417 | { | |
3418 | inst.error = _("'[' expected after PLD mnemonic"); | |
3419 | return; | |
3420 | } | |
3421 | ||
3422 | ++ str; | |
3423 | skip_whitespace (str); | |
3424 | ||
3425 | if ((rd = reg_required_here (& str, 16)) == FAIL) | |
3426 | return; | |
3427 | ||
3428 | skip_whitespace (str); | |
3429 | ||
3430 | if (* str == ']') | |
3431 | { | |
3432 | /* [Rn], ... ? */ | |
3433 | ++ str; | |
3434 | skip_whitespace (str); | |
3435 | ||
3436 | if (skip_past_comma (& str) == SUCCESS) | |
3437 | { | |
3438 | if (ldst_extend (& str, 0) == FAIL) | |
3439 | return; | |
3440 | } | |
3441 | else if (* str == '!') /* [Rn]! */ | |
3442 | { | |
3443 | inst.error = _("writeback used in preload instruction"); | |
3444 | ++ str; | |
3445 | } | |
3446 | else /* [Rn] */ | |
3447 | inst.instruction |= INDEX_UP | PRE_INDEX; | |
3448 | } | |
3449 | else /* [Rn, ...] */ | |
3450 | { | |
3451 | if (skip_past_comma (& str) == FAIL) | |
3452 | { | |
3453 | inst.error = _("pre-indexed expression expected"); | |
3454 | return; | |
3455 | } | |
3456 | ||
3457 | if (ldst_extend (& str, 0) == FAIL) | |
3458 | return; | |
3459 | ||
3460 | skip_whitespace (str); | |
3461 | ||
3462 | if (* str != ']') | |
3463 | { | |
3464 | inst.error = _("missing ]"); | |
3465 | return; | |
3466 | } | |
3467 | ||
3468 | ++ str; | |
3469 | skip_whitespace (str); | |
3470 | ||
3471 | if (* str == '!') /* [Rn]! */ | |
3472 | { | |
3473 | inst.error = _("writeback used in preload instruction"); | |
3474 | ++ str; | |
3475 | } | |
3476 | ||
3477 | inst.instruction |= PRE_INDEX; | |
3478 | } | |
3479 | ||
3480 | end_of_line (str); | |
3481 | } | |
3482 | ||
3483 | /* Xscale load-consecutive (argument parse) | |
3484 | Mode is like LDRH. | |
3485 | ||
3486 | LDRccD R, mode | |
3487 | STRccD R, mode. */ | |
3488 | ||
3489 | static void | |
3490 | do_ldrd (str, flags) | |
3491 | char * str; | |
3492 | unsigned long flags; | |
3493 | { | |
3494 | int rd; | |
3495 | int rn; | |
3496 | ||
3497 | if (flags != DOUBLE_LOAD_FLAG) | |
3498 | { | |
3499 | /* Change instruction pattern to normal ldr/str. */ | |
3500 | if (inst.instruction & 0x20) | |
3501 | inst.instruction = (inst.instruction & COND_MASK) | 0x04000000; /* str */ | |
3502 | else | |
3503 | inst.instruction = (inst.instruction & COND_MASK) | 0x04100000; /* ldr */ | |
3504 | ||
3505 | /* Perform a normal load/store instruction parse. */ | |
3506 | do_ldst (str, flags); | |
3507 | ||
3508 | return; | |
3509 | } | |
3510 | ||
3511 | if ((cpu_variant & ARM_EXT_XSCALE) != ARM_EXT_XSCALE) | |
3512 | { | |
3513 | static char buff[128]; | |
3514 | ||
3515 | --str; | |
3516 | while (isspace (*str)) | |
3517 | --str; | |
3518 | str -= 4; | |
3519 | ||
3520 | /* Deny all knowledge. */ | |
3521 | sprintf (buff, _("bad instruction '%.100s'"), str); | |
3522 | inst.error = buff; | |
3523 | return; | |
3524 | } | |
3525 | ||
3526 | skip_whitespace (str); | |
3527 | ||
3528 | if ((rd = reg_required_here (& str, 12)) == FAIL) | |
3529 | { | |
3530 | inst.error = BAD_ARGS; | |
3531 | return; | |
3532 | } | |
3533 | ||
3534 | if (skip_past_comma (& str) == FAIL | |
3535 | || (rn = ld_mode_required_here (& str)) == FAIL) | |
3536 | { | |
3537 | if (!inst.error) | |
3538 | inst.error = BAD_ARGS; | |
3539 | return; | |
3540 | } | |
3541 | ||
3542 | /* inst.instruction has now been zapped with Rd and the addressing mode. */ | |
3543 | if (rd & 1) /* Unpredictable result if Rd is odd. */ | |
3544 | { | |
3545 | inst.error = _("Destination register must be even"); | |
3546 | return; | |
3547 | } | |
3548 | ||
3549 | if (rd == REG_LR || rd == 12) | |
3550 | { | |
3551 | inst.error = _("r12 or r14 not allowed here"); | |
3552 | return; | |
3553 | } | |
3554 | ||
3555 | if (((rd == rn) || (rd + 1 == rn)) | |
3556 | && | |
3557 | ((inst.instruction & WRITE_BACK) | |
3558 | || (!(inst.instruction & PRE_INDEX)))) | |
3559 | as_warn (_("pre/post-indexing used when modified address register is destination")); | |
3560 | ||
3561 | end_of_line (str); | |
3562 | } | |
3563 | ||
3564 | /* Returns the index into fp_values of a floating point number, | |
3565 | or -1 if not in the table. */ | |
3566 | ||
3567 | static int | |
3568 | my_get_float_expression (str) | |
3569 | char ** str; | |
3570 | { | |
3571 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3572 | char * save_in; | |
3573 | expressionS exp; | |
3574 | int i; | |
3575 | int j; | |
3576 | ||
3577 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); | |
3578 | ||
3579 | /* Look for a raw floating point number. */ | |
3580 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
3581 | && is_end_of_line[(unsigned char) *save_in]) | |
3582 | { | |
3583 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3584 | { | |
3585 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
3586 | { | |
3587 | if (words[j] != fp_values[i][j]) | |
3588 | break; | |
3589 | } | |
3590 | ||
3591 | if (j == MAX_LITTLENUMS) | |
3592 | { | |
3593 | *str = save_in; | |
3594 | return i; | |
3595 | } | |
3596 | } | |
3597 | } | |
3598 | ||
3599 | /* Try and parse a more complex expression, this will probably fail | |
3600 | unless the code uses a floating point prefix (eg "0f"). */ | |
3601 | save_in = input_line_pointer; | |
3602 | input_line_pointer = *str; | |
3603 | if (expression (&exp) == absolute_section | |
3604 | && exp.X_op == O_big | |
3605 | && exp.X_add_number < 0) | |
3606 | { | |
3607 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
3608 | Ditto for 15. */ | |
3609 | if (gen_to_words (words, 5, (long) 15) == 0) | |
3610 | { | |
3611 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
3612 | { | |
3613 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
3614 | { | |
3615 | if (words[j] != fp_values[i][j]) | |
3616 | break; | |
3617 | } | |
3618 | ||
3619 | if (j == MAX_LITTLENUMS) | |
3620 | { | |
3621 | *str = input_line_pointer; | |
3622 | input_line_pointer = save_in; | |
3623 | return i; | |
3624 | } | |
3625 | } | |
3626 | } | |
3627 | } | |
3628 | ||
3629 | *str = input_line_pointer; | |
3630 | input_line_pointer = save_in; | |
3631 | return -1; | |
3632 | } | |
3633 | ||
3634 | /* Return true if anything in the expression is a bignum. */ | |
3635 | ||
3636 | static int | |
3637 | walk_no_bignums (sp) | |
3638 | symbolS * sp; | |
3639 | { | |
3640 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
3641 | return 1; | |
3642 | ||
3643 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3644 | { | |
3645 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) | |
3646 | || (symbol_get_value_expression (sp)->X_op_symbol | |
3647 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3648 | } | |
3649 | ||
3650 | return 0; | |
3651 | } | |
3652 | ||
3653 | static int | |
3654 | my_get_expression (ep, str) | |
3655 | expressionS * ep; | |
3656 | char ** str; | |
3657 | { | |
3658 | char * save_in; | |
3659 | segT seg; | |
3660 | ||
3661 | save_in = input_line_pointer; | |
3662 | input_line_pointer = *str; | |
3663 | seg = expression (ep); | |
3664 | ||
3665 | #ifdef OBJ_AOUT | |
3666 | if (seg != absolute_section | |
3667 | && seg != text_section | |
3668 | && seg != data_section | |
3669 | && seg != bss_section | |
3670 | && seg != undefined_section) | |
3671 | { | |
3672 | inst.error = _("bad_segment"); | |
3673 | *str = input_line_pointer; | |
3674 | input_line_pointer = save_in; | |
3675 | return 1; | |
3676 | } | |
3677 | #endif | |
3678 | ||
3679 | /* Get rid of any bignums now, so that we don't generate an error for which | |
3680 | we can't establish a line number later on. Big numbers are never valid | |
3681 | in instructions, which is where this routine is always called. */ | |
3682 | if (ep->X_op == O_big | |
3683 | || (ep->X_add_symbol | |
3684 | && (walk_no_bignums (ep->X_add_symbol) | |
3685 | || (ep->X_op_symbol | |
3686 | && walk_no_bignums (ep->X_op_symbol))))) | |
3687 | { | |
3688 | inst.error = _("Invalid constant"); | |
3689 | *str = input_line_pointer; | |
3690 | input_line_pointer = save_in; | |
3691 | return 1; | |
3692 | } | |
3693 | ||
3694 | *str = input_line_pointer; | |
3695 | input_line_pointer = save_in; | |
3696 | return 0; | |
3697 | } | |
3698 | ||
3699 | /* UNRESTRICT should be one if <shift> <register> is permitted for this | |
3700 | instruction. */ | |
3701 | ||
3702 | static int | |
3703 | decode_shift (str, unrestrict) | |
3704 | char ** str; | |
3705 | int unrestrict; | |
3706 | { | |
3707 | const struct asm_shift_name * shift; | |
3708 | char * p; | |
3709 | char c; | |
3710 | ||
3711 | skip_whitespace (* str); | |
3712 | ||
3713 | for (p = * str; isalpha (* p); p ++) | |
3714 | ; | |
3715 | ||
3716 | if (p == * str) | |
3717 | { | |
3718 | inst.error = _("Shift expression expected"); | |
3719 | return FAIL; | |
3720 | } | |
3721 | ||
3722 | c = * p; | |
3723 | * p = '\0'; | |
3724 | shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str); | |
3725 | * p = c; | |
3726 | ||
3727 | if (shift == NULL) | |
3728 | { | |
3729 | inst.error = _("Shift expression expected"); | |
3730 | return FAIL; | |
3731 | } | |
3732 | ||
3733 | assert (shift->properties->index == shift_properties[shift->properties->index].index); | |
3734 | ||
3735 | if (shift->properties->index == SHIFT_RRX) | |
3736 | { | |
3737 | * str = p; | |
3738 | inst.instruction |= shift->properties->bit_field; | |
3739 | return SUCCESS; | |
3740 | } | |
3741 | ||
3742 | skip_whitespace (p); | |
3743 | ||
3744 | if (unrestrict && reg_required_here (& p, 8) != FAIL) | |
3745 | { | |
3746 | inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG; | |
3747 | * str = p; | |
3748 | return SUCCESS; | |
3749 | } | |
3750 | else if (! is_immediate_prefix (* p)) | |
3751 | { | |
3752 | inst.error = (unrestrict | |
3753 | ? _("shift requires register or #expression") | |
3754 | : _("shift requires #expression")); | |
3755 | * str = p; | |
3756 | return FAIL; | |
3757 | } | |
3758 | ||
3759 | inst.error = NULL; | |
3760 | p ++; | |
3761 | ||
3762 | if (my_get_expression (& inst.reloc.exp, & p)) | |
3763 | return FAIL; | |
3764 | ||
3765 | /* Validate some simple #expressions. */ | |
3766 | if (inst.reloc.exp.X_op == O_constant) | |
3767 | { | |
3768 | unsigned num = inst.reloc.exp.X_add_number; | |
3769 | ||
3770 | /* Reject operations greater than 32. */ | |
3771 | if (num > 32 | |
3772 | /* Reject a shift of 0 unless the mode allows it. */ | |
3773 | || (num == 0 && shift->properties->allows_0 == 0) | |
3774 | /* Reject a shift of 32 unless the mode allows it. */ | |
3775 | || (num == 32 && shift->properties->allows_32 == 0) | |
3776 | ) | |
3777 | { | |
3778 | /* As a special case we allow a shift of zero for | |
3779 | modes that do not support it to be recoded as an | |
3780 | logical shift left of zero (ie nothing). We warn | |
3781 | about this though. */ | |
3782 | if (num == 0) | |
3783 | { | |
3784 | as_warn (_("Shift of 0 ignored.")); | |
3785 | shift = & shift_names[0]; | |
3786 | assert (shift->properties->index == SHIFT_LSL); | |
3787 | } | |
3788 | else | |
3789 | { | |
3790 | inst.error = _("Invalid immediate shift"); | |
3791 | return FAIL; | |
3792 | } | |
3793 | } | |
3794 | ||
3795 | /* Shifts of 32 are encoded as 0, for those shifts that | |
3796 | support it. */ | |
3797 | if (num == 32) | |
3798 | num = 0; | |
3799 | ||
3800 | inst.instruction |= (num << 7) | shift->properties->bit_field; | |
3801 | } | |
3802 | else | |
3803 | { | |
3804 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
3805 | inst.reloc.pc_rel = 0; | |
3806 | inst.instruction |= shift->properties->bit_field; | |
3807 | } | |
3808 | ||
3809 | * str = p; | |
3810 | return SUCCESS; | |
3811 | } | |
3812 | ||
3813 | /* Do those data_ops which can take a negative immediate constant | |
3814 | by altering the instuction. A bit of a hack really. | |
3815 | MOV <-> MVN | |
3816 | AND <-> BIC | |
3817 | ADC <-> SBC | |
3818 | by inverting the second operand, and | |
3819 | ADD <-> SUB | |
3820 | CMP <-> CMN | |
3821 | by negating the second operand. */ | |
3822 | ||
3823 | static int | |
3824 | negate_data_op (instruction, value) | |
3825 | unsigned long * instruction; | |
3826 | unsigned long value; | |
3827 | { | |
3828 | int op, new_inst; | |
3829 | unsigned long negated, inverted; | |
3830 | ||
3831 | negated = validate_immediate (-value); | |
3832 | inverted = validate_immediate (~value); | |
3833 | ||
3834 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; | |
3835 | switch (op) | |
3836 | { | |
3837 | /* First negates. */ | |
3838 | case OPCODE_SUB: /* ADD <-> SUB */ | |
3839 | new_inst = OPCODE_ADD; | |
3840 | value = negated; | |
3841 | break; | |
3842 | ||
3843 | case OPCODE_ADD: | |
3844 | new_inst = OPCODE_SUB; | |
3845 | value = negated; | |
3846 | break; | |
3847 | ||
3848 | case OPCODE_CMP: /* CMP <-> CMN */ | |
3849 | new_inst = OPCODE_CMN; | |
3850 | value = negated; | |
3851 | break; | |
3852 | ||
3853 | case OPCODE_CMN: | |
3854 | new_inst = OPCODE_CMP; | |
3855 | value = negated; | |
3856 | break; | |
3857 | ||
3858 | /* Now Inverted ops. */ | |
3859 | case OPCODE_MOV: /* MOV <-> MVN */ | |
3860 | new_inst = OPCODE_MVN; | |
3861 | value = inverted; | |
3862 | break; | |
3863 | ||
3864 | case OPCODE_MVN: | |
3865 | new_inst = OPCODE_MOV; | |
3866 | value = inverted; | |
3867 | break; | |
3868 | ||
3869 | case OPCODE_AND: /* AND <-> BIC */ | |
3870 | new_inst = OPCODE_BIC; | |
3871 | value = inverted; | |
3872 | break; | |
3873 | ||
3874 | case OPCODE_BIC: | |
3875 | new_inst = OPCODE_AND; | |
3876 | value = inverted; | |
3877 | break; | |
3878 | ||
3879 | case OPCODE_ADC: /* ADC <-> SBC */ | |
3880 | new_inst = OPCODE_SBC; | |
3881 | value = inverted; | |
3882 | break; | |
3883 | ||
3884 | case OPCODE_SBC: | |
3885 | new_inst = OPCODE_ADC; | |
3886 | value = inverted; | |
3887 | break; | |
3888 | ||
3889 | /* We cannot do anything. */ | |
3890 | default: | |
3891 | return FAIL; | |
3892 | } | |
3893 | ||
3894 | if (value == (unsigned) FAIL) | |
3895 | return FAIL; | |
3896 | ||
3897 | *instruction &= OPCODE_MASK; | |
3898 | *instruction |= new_inst << DATA_OP_SHIFT; | |
3899 | return value; | |
3900 | } | |
3901 | ||
3902 | static int | |
3903 | data_op2 (str) | |
3904 | char ** str; | |
3905 | { | |
3906 | int value; | |
3907 | expressionS expr; | |
3908 | ||
3909 | skip_whitespace (* str); | |
3910 | ||
3911 | if (reg_required_here (str, 0) != FAIL) | |
3912 | { | |
3913 | if (skip_past_comma (str) == SUCCESS) | |
3914 | /* Shift operation on register. */ | |
3915 | return decode_shift (str, NO_SHIFT_RESTRICT); | |
3916 | ||
3917 | return SUCCESS; | |
3918 | } | |
3919 | else | |
3920 | { | |
3921 | /* Immediate expression. */ | |
3922 | if (is_immediate_prefix (**str)) | |
3923 | { | |
3924 | (*str)++; | |
3925 | inst.error = NULL; | |
3926 | ||
3927 | if (my_get_expression (&inst.reloc.exp, str)) | |
3928 | return FAIL; | |
3929 | ||
3930 | if (inst.reloc.exp.X_add_symbol) | |
3931 | { | |
3932 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
3933 | inst.reloc.pc_rel = 0; | |
3934 | } | |
3935 | else | |
3936 | { | |
3937 | if (skip_past_comma (str) == SUCCESS) | |
3938 | { | |
3939 | /* #x, y -- ie explicit rotation by Y. */ | |
3940 | if (my_get_expression (&expr, str)) | |
3941 | return FAIL; | |
3942 | ||
3943 | if (expr.X_op != O_constant) | |
3944 | { | |
3945 | inst.error = _("Constant expression expected"); | |
3946 | return FAIL; | |
3947 | } | |
3948 | ||
3949 | /* Rotate must be a multiple of 2. */ | |
3950 | if (((unsigned) expr.X_add_number) > 30 | |
3951 | || (expr.X_add_number & 1) != 0 | |
3952 | || ((unsigned) inst.reloc.exp.X_add_number) > 255) | |
3953 | { | |
3954 | inst.error = _("Invalid constant"); | |
3955 | return FAIL; | |
3956 | } | |
3957 | inst.instruction |= INST_IMMEDIATE; | |
3958 | inst.instruction |= inst.reloc.exp.X_add_number; | |
3959 | inst.instruction |= expr.X_add_number << 7; | |
3960 | return SUCCESS; | |
3961 | } | |
3962 | ||
3963 | /* Implicit rotation, select a suitable one. */ | |
3964 | value = validate_immediate (inst.reloc.exp.X_add_number); | |
3965 | ||
3966 | if (value == FAIL) | |
3967 | { | |
3968 | /* Can't be done. Perhaps the code reads something like | |
3969 | "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */ | |
3970 | if ((value = negate_data_op (&inst.instruction, | |
3971 | inst.reloc.exp.X_add_number)) | |
3972 | == FAIL) | |
3973 | { | |
3974 | inst.error = _("Invalid constant"); | |
3975 | return FAIL; | |
3976 | } | |
3977 | } | |
3978 | ||
3979 | inst.instruction |= value; | |
3980 | } | |
3981 | ||
3982 | inst.instruction |= INST_IMMEDIATE; | |
3983 | return SUCCESS; | |
3984 | } | |
3985 | ||
3986 | (*str)++; | |
3987 | inst.error = _("Register or shift expression expected"); | |
3988 | return FAIL; | |
3989 | } | |
3990 | } | |
3991 | ||
3992 | static int | |
3993 | fp_op2 (str) | |
3994 | char ** str; | |
3995 | { | |
3996 | skip_whitespace (* str); | |
3997 | ||
3998 | if (fp_reg_required_here (str, 0) != FAIL) | |
3999 | return SUCCESS; | |
4000 | else | |
4001 | { | |
4002 | /* Immediate expression. */ | |
4003 | if (*((*str)++) == '#') | |
4004 | { | |
4005 | int i; | |
4006 | ||
4007 | inst.error = NULL; | |
4008 | ||
4009 | skip_whitespace (* str); | |
4010 | ||
4011 | /* First try and match exact strings, this is to guarantee | |
4012 | that some formats will work even for cross assembly. */ | |
4013 | ||
4014 | for (i = 0; fp_const[i]; i++) | |
4015 | { | |
4016 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
4017 | { | |
4018 | char *start = *str; | |
4019 | ||
4020 | *str += strlen (fp_const[i]); | |
4021 | if (is_end_of_line[(unsigned char) **str]) | |
4022 | { | |
4023 | inst.instruction |= i + 8; | |
4024 | return SUCCESS; | |
4025 | } | |
4026 | *str = start; | |
4027 | } | |
4028 | } | |
4029 | ||
4030 | /* Just because we didn't get a match doesn't mean that the | |
4031 | constant isn't valid, just that it is in a format that we | |
4032 | don't automatically recognize. Try parsing it with | |
4033 | the standard expression routines. */ | |
4034 | if ((i = my_get_float_expression (str)) >= 0) | |
4035 | { | |
4036 | inst.instruction |= i + 8; | |
4037 | return SUCCESS; | |
4038 | } | |
4039 | ||
4040 | inst.error = _("Invalid floating point immediate expression"); | |
4041 | return FAIL; | |
4042 | } | |
4043 | inst.error = | |
4044 | _("Floating point register or immediate expression expected"); | |
4045 | return FAIL; | |
4046 | } | |
4047 | } | |
4048 | ||
4049 | static void | |
4050 | do_arit (str, flags) | |
4051 | char * str; | |
4052 | unsigned long flags; | |
4053 | { | |
4054 | skip_whitespace (str); | |
4055 | ||
4056 | if (reg_required_here (&str, 12) == FAIL | |
4057 | || skip_past_comma (&str) == FAIL | |
4058 | || reg_required_here (&str, 16) == FAIL | |
4059 | || skip_past_comma (&str) == FAIL | |
4060 | || data_op2 (&str) == FAIL) | |
4061 | { | |
4062 | if (!inst.error) | |
4063 | inst.error = BAD_ARGS; | |
4064 | return; | |
4065 | } | |
4066 | ||
4067 | inst.instruction |= flags; | |
4068 | end_of_line (str); | |
4069 | return; | |
4070 | } | |
4071 | ||
4072 | static void | |
4073 | do_adr (str, flags) | |
4074 | char * str; | |
4075 | unsigned long flags; | |
4076 | { | |
b99bd4ef NC |
4077 | skip_whitespace (str); |
4078 | ||
4079 | if (reg_required_here (&str, 12) == FAIL | |
4080 | || skip_past_comma (&str) == FAIL | |
4081 | || my_get_expression (&inst.reloc.exp, &str)) | |
4082 | { | |
4083 | if (!inst.error) | |
4084 | inst.error = BAD_ARGS; | |
4085 | return; | |
4086 | } | |
4087 | ||
1cac9012 | 4088 | if (flags & 0x00400000) |
b99bd4ef | 4089 | { |
1cac9012 NC |
4090 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
4091 | into a relative address of the form: | |
4092 | add rd, pc, #low(label-.-8)" | |
4093 | add rd, rd, #high(label-.-8)" */ | |
4094 | /* Frag hacking will turn this into a sub instruction if the offset turns | |
4095 | out to be negative. */ | |
4096 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
4097 | inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */ | |
4098 | inst.reloc.pc_rel = 1; | |
4099 | inst.instruction |= flags & ~0x00400000; | |
4100 | inst.size = INSN_SIZE * 2; | |
4101 | } | |
4102 | else | |
4103 | { | |
4104 | /* This is a pseudo-op of the form "adr rd, label" to be converted | |
4105 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
4106 | /* Frag hacking will turn this into a sub instruction if the offset turns | |
4107 | out to be negative. */ | |
4108 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
4109 | inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */ | |
4110 | inst.reloc.pc_rel = 1; | |
4111 | inst.instruction |= flags; | |
b99bd4ef NC |
4112 | } |
4113 | ||
4114 | end_of_line (str); | |
b99bd4ef NC |
4115 | } |
4116 | ||
4117 | static void | |
4118 | do_cmp (str, flags) | |
4119 | char * str; | |
4120 | unsigned long flags; | |
4121 | { | |
4122 | skip_whitespace (str); | |
4123 | ||
4124 | if (reg_required_here (&str, 16) == FAIL) | |
4125 | { | |
4126 | if (!inst.error) | |
4127 | inst.error = BAD_ARGS; | |
4128 | return; | |
4129 | } | |
4130 | ||
4131 | if (skip_past_comma (&str) == FAIL | |
4132 | || data_op2 (&str) == FAIL) | |
4133 | { | |
4134 | if (!inst.error) | |
4135 | inst.error = BAD_ARGS; | |
4136 | return; | |
4137 | } | |
4138 | ||
4139 | inst.instruction |= flags; | |
4140 | if ((flags & 0x0000f000) == 0) | |
4141 | inst.instruction |= CONDS_BIT; | |
4142 | ||
4143 | end_of_line (str); | |
4144 | return; | |
4145 | } | |
4146 | ||
4147 | static void | |
4148 | do_mov (str, flags) | |
4149 | char * str; | |
4150 | unsigned long flags; | |
4151 | { | |
4152 | skip_whitespace (str); | |
4153 | ||
4154 | if (reg_required_here (&str, 12) == FAIL) | |
4155 | { | |
4156 | if (!inst.error) | |
4157 | inst.error = BAD_ARGS; | |
4158 | return; | |
4159 | } | |
4160 | ||
4161 | if (skip_past_comma (&str) == FAIL | |
4162 | || data_op2 (&str) == FAIL) | |
4163 | { | |
4164 | if (!inst.error) | |
4165 | inst.error = BAD_ARGS; | |
4166 | return; | |
4167 | } | |
4168 | ||
4169 | inst.instruction |= flags; | |
4170 | end_of_line (str); | |
4171 | return; | |
4172 | } | |
4173 | ||
4174 | static int | |
4175 | ldst_extend (str, hwse) | |
4176 | char ** str; | |
4177 | int hwse; | |
4178 | { | |
4179 | int add = INDEX_UP; | |
4180 | ||
4181 | switch (**str) | |
4182 | { | |
4183 | case '#': | |
4184 | case '$': | |
4185 | (*str)++; | |
4186 | if (my_get_expression (& inst.reloc.exp, str)) | |
4187 | return FAIL; | |
4188 | ||
4189 | if (inst.reloc.exp.X_op == O_constant) | |
4190 | { | |
4191 | int value = inst.reloc.exp.X_add_number; | |
4192 | ||
4193 | if ((hwse && (value < -255 || value > 255)) | |
4194 | || (value < -4095 || value > 4095)) | |
4195 | { | |
4196 | inst.error = _("address offset too large"); | |
4197 | return FAIL; | |
4198 | } | |
4199 | ||
4200 | if (value < 0) | |
4201 | { | |
4202 | value = -value; | |
4203 | add = 0; | |
4204 | } | |
4205 | ||
4206 | /* Halfword and signextension instructions have the | |
4207 | immediate value split across bits 11..8 and bits 3..0. */ | |
4208 | if (hwse) | |
4209 | inst.instruction |= (add | HWOFFSET_IMM | |
4210 | | ((value >> 4) << 8) | (value & 0xF)); | |
4211 | else | |
4212 | inst.instruction |= add | value; | |
4213 | } | |
4214 | else | |
4215 | { | |
4216 | if (hwse) | |
4217 | { | |
4218 | inst.instruction |= HWOFFSET_IMM; | |
4219 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
4220 | } | |
4221 | else | |
4222 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
4223 | inst.reloc.pc_rel = 0; | |
4224 | } | |
4225 | return SUCCESS; | |
4226 | ||
4227 | case '-': | |
4228 | add = 0; | |
4229 | /* Fall through. */ | |
4230 | ||
4231 | case '+': | |
4232 | (*str)++; | |
4233 | /* Fall through. */ | |
4234 | ||
4235 | default: | |
4236 | if (reg_required_here (str, 0) == FAIL) | |
4237 | return FAIL; | |
4238 | ||
4239 | if (hwse) | |
4240 | inst.instruction |= add; | |
4241 | else | |
4242 | { | |
4243 | inst.instruction |= add | OFFSET_REG; | |
4244 | if (skip_past_comma (str) == SUCCESS) | |
4245 | return decode_shift (str, SHIFT_RESTRICT); | |
4246 | } | |
4247 | ||
4248 | return SUCCESS; | |
4249 | } | |
4250 | } | |
4251 | ||
4252 | static void | |
4253 | do_ldst (str, flags) | |
4254 | char * str; | |
4255 | unsigned long flags; | |
4256 | { | |
4257 | int halfword = 0; | |
4258 | int pre_inc = 0; | |
4259 | int conflict_reg; | |
4260 | int value; | |
4261 | ||
4262 | /* This is not ideal, but it is the simplest way of dealing with the | |
4263 | ARM7T halfword instructions (since they use a different | |
4264 | encoding, but the same mnemonic): */ | |
4265 | halfword = (flags & 0x80000000) != 0; | |
4266 | if (halfword) | |
4267 | { | |
4268 | /* This is actually a load/store of a halfword, or a | |
4269 | signed-extension load. */ | |
4270 | if ((cpu_variant & ARM_EXT_HALFWORD) == 0) | |
4271 | { | |
4272 | inst.error | |
4273 | = _("Processor does not support halfwords or signed bytes"); | |
4274 | return; | |
4275 | } | |
4276 | ||
4277 | inst.instruction = ((inst.instruction & COND_MASK) | |
4278 | | (flags & ~COND_MASK)); | |
4279 | ||
4280 | flags = 0; | |
4281 | } | |
4282 | ||
4283 | skip_whitespace (str); | |
4284 | ||
4285 | if ((conflict_reg = reg_required_here (& str, 12)) == FAIL) | |
4286 | { | |
4287 | if (!inst.error) | |
4288 | inst.error = BAD_ARGS; | |
4289 | return; | |
4290 | } | |
4291 | ||
4292 | if (skip_past_comma (& str) == FAIL) | |
4293 | { | |
4294 | inst.error = _("Address expected"); | |
4295 | return; | |
4296 | } | |
4297 | ||
4298 | if (*str == '[') | |
4299 | { | |
4300 | int reg; | |
4301 | ||
4302 | str++; | |
4303 | ||
4304 | skip_whitespace (str); | |
4305 | ||
4306 | if ((reg = reg_required_here (&str, 16)) == FAIL) | |
4307 | return; | |
4308 | ||
4309 | /* Conflicts can occur on stores as well as loads. */ | |
4310 | conflict_reg = (conflict_reg == reg); | |
4311 | ||
4312 | skip_whitespace (str); | |
4313 | ||
4314 | if (*str == ']') | |
4315 | { | |
4316 | str ++; | |
4317 | ||
4318 | if (skip_past_comma (&str) == SUCCESS) | |
4319 | { | |
4320 | /* [Rn],... (post inc) */ | |
4321 | if (ldst_extend (&str, halfword) == FAIL) | |
4322 | return; | |
4323 | if (conflict_reg) | |
4324 | { | |
4325 | if (flags & TRANS_BIT) | |
4326 | as_warn (_("Rn and Rd must be different in %s"), | |
4327 | ((inst.instruction & LOAD_BIT) | |
4328 | ? "LDRT" : "STRT")); | |
4329 | else | |
4330 | as_warn (_("%s register same as write-back base"), | |
4331 | ((inst.instruction & LOAD_BIT) | |
4332 | ? _("destination") : _("source"))); | |
4333 | } | |
4334 | } | |
4335 | else | |
4336 | { | |
4337 | /* [Rn] */ | |
4338 | if (halfword) | |
4339 | inst.instruction |= HWOFFSET_IMM; | |
4340 | ||
4341 | skip_whitespace (str); | |
4342 | ||
4343 | if (*str == '!') | |
4344 | { | |
4345 | if (conflict_reg) | |
4346 | as_warn (_("%s register same as write-back base"), | |
4347 | ((inst.instruction & LOAD_BIT) | |
4348 | ? _("destination") : _("source"))); | |
4349 | str++; | |
4350 | inst.instruction |= WRITE_BACK; | |
4351 | } | |
4352 | ||
4353 | flags |= INDEX_UP; | |
4354 | if (flags & TRANS_BIT) | |
4355 | { | |
4356 | if (conflict_reg) | |
4357 | as_warn (_("Rn and Rd must be different in %s"), | |
4358 | ((inst.instruction & LOAD_BIT) | |
4359 | ? "LDRT" : "STRT")); | |
4360 | } | |
4361 | else | |
4362 | pre_inc = 1; | |
4363 | } | |
4364 | } | |
4365 | else | |
4366 | { | |
4367 | /* [Rn,...] */ | |
4368 | if (skip_past_comma (&str) == FAIL) | |
4369 | { | |
4370 | inst.error = _("pre-indexed expression expected"); | |
4371 | return; | |
4372 | } | |
4373 | ||
4374 | pre_inc = 1; | |
4375 | if (ldst_extend (&str, halfword) == FAIL) | |
4376 | return; | |
4377 | ||
4378 | skip_whitespace (str); | |
4379 | ||
4380 | if (*str++ != ']') | |
4381 | { | |
4382 | inst.error = _("missing ]"); | |
4383 | return; | |
4384 | } | |
4385 | ||
4386 | skip_whitespace (str); | |
4387 | ||
4388 | if (*str == '!') | |
4389 | { | |
4390 | if (conflict_reg) | |
4391 | as_warn (_("%s register same as write-back base"), | |
4392 | ((inst.instruction & LOAD_BIT) | |
4393 | ? _("destination") : _("source"))); | |
4394 | str++; | |
4395 | inst.instruction |= WRITE_BACK; | |
4396 | } | |
4397 | } | |
4398 | } | |
4399 | else if (*str == '=') | |
4400 | { | |
4401 | /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */ | |
4402 | str++; | |
4403 | ||
4404 | skip_whitespace (str); | |
4405 | ||
4406 | if (my_get_expression (&inst.reloc.exp, &str)) | |
4407 | return; | |
4408 | ||
4409 | if (inst.reloc.exp.X_op != O_constant | |
4410 | && inst.reloc.exp.X_op != O_symbol) | |
4411 | { | |
4412 | inst.error = _("Constant expression expected"); | |
4413 | return; | |
4414 | } | |
4415 | ||
4416 | if (inst.reloc.exp.X_op == O_constant | |
4417 | && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL) | |
4418 | { | |
4419 | /* This can be done with a mov instruction. */ | |
4420 | inst.instruction &= LITERAL_MASK; | |
4421 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
4422 | inst.instruction |= (flags & COND_MASK) | (value & 0xfff); | |
4423 | end_of_line (str); | |
4424 | return; | |
4425 | } | |
4426 | else | |
4427 | { | |
4428 | /* Insert into literal pool. */ | |
4429 | if (add_to_lit_pool () == FAIL) | |
4430 | { | |
4431 | if (!inst.error) | |
4432 | inst.error = _("literal pool insertion failed"); | |
4433 | return; | |
4434 | } | |
4435 | ||
4436 | /* Change the instruction exp to point to the pool. */ | |
4437 | if (halfword) | |
4438 | { | |
4439 | inst.instruction |= HWOFFSET_IMM; | |
4440 | inst.reloc.type = BFD_RELOC_ARM_HWLITERAL; | |
4441 | } | |
4442 | else | |
4443 | inst.reloc.type = BFD_RELOC_ARM_LITERAL; | |
4444 | inst.reloc.pc_rel = 1; | |
4445 | inst.instruction |= (REG_PC << 16); | |
4446 | pre_inc = 1; | |
4447 | } | |
4448 | } | |
4449 | else | |
4450 | { | |
4451 | if (my_get_expression (&inst.reloc.exp, &str)) | |
4452 | return; | |
4453 | ||
4454 | if (halfword) | |
4455 | { | |
4456 | inst.instruction |= HWOFFSET_IMM; | |
4457 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
4458 | } | |
4459 | else | |
4460 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
4461 | #ifndef TE_WINCE | |
4462 | /* PC rel adjust. */ | |
4463 | inst.reloc.exp.X_add_number -= 8; | |
4464 | #endif | |
4465 | inst.reloc.pc_rel = 1; | |
4466 | inst.instruction |= (REG_PC << 16); | |
4467 | pre_inc = 1; | |
4468 | } | |
4469 | ||
4470 | if (pre_inc && (flags & TRANS_BIT)) | |
4471 | inst.error = _("Pre-increment instruction with translate"); | |
4472 | ||
4473 | inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0); | |
4474 | end_of_line (str); | |
4475 | return; | |
4476 | } | |
4477 | ||
4478 | static long | |
4479 | reg_list (strp) | |
4480 | char ** strp; | |
4481 | { | |
4482 | char * str = * strp; | |
4483 | long range = 0; | |
4484 | int another_range; | |
4485 | ||
4486 | /* We come back here if we get ranges concatenated by '+' or '|'. */ | |
4487 | do | |
4488 | { | |
4489 | another_range = 0; | |
4490 | ||
4491 | if (*str == '{') | |
4492 | { | |
4493 | int in_range = 0; | |
4494 | int cur_reg = -1; | |
4495 | ||
4496 | str++; | |
4497 | do | |
4498 | { | |
4499 | int reg; | |
4500 | ||
4501 | skip_whitespace (str); | |
4502 | ||
4503 | if ((reg = reg_required_here (& str, -1)) == FAIL) | |
4504 | return FAIL; | |
4505 | ||
4506 | if (in_range) | |
4507 | { | |
4508 | int i; | |
4509 | ||
4510 | if (reg <= cur_reg) | |
4511 | { | |
4512 | inst.error = _("Bad range in register list"); | |
4513 | return FAIL; | |
4514 | } | |
4515 | ||
4516 | for (i = cur_reg + 1; i < reg; i++) | |
4517 | { | |
4518 | if (range & (1 << i)) | |
4519 | as_tsktsk | |
4520 | (_("Warning: Duplicated register (r%d) in register list"), | |
4521 | i); | |
4522 | else | |
4523 | range |= 1 << i; | |
4524 | } | |
4525 | in_range = 0; | |
4526 | } | |
4527 | ||
4528 | if (range & (1 << reg)) | |
4529 | as_tsktsk (_("Warning: Duplicated register (r%d) in register list"), | |
4530 | reg); | |
4531 | else if (reg <= cur_reg) | |
4532 | as_tsktsk (_("Warning: Register range not in ascending order")); | |
4533 | ||
4534 | range |= 1 << reg; | |
4535 | cur_reg = reg; | |
4536 | } | |
4537 | while (skip_past_comma (&str) != FAIL | |
4538 | || (in_range = 1, *str++ == '-')); | |
4539 | str--; | |
4540 | skip_whitespace (str); | |
4541 | ||
4542 | if (*str++ != '}') | |
4543 | { | |
4544 | inst.error = _("Missing `}'"); | |
4545 | return FAIL; | |
4546 | } | |
4547 | } | |
4548 | else | |
4549 | { | |
4550 | expressionS expr; | |
4551 | ||
4552 | if (my_get_expression (&expr, &str)) | |
4553 | return FAIL; | |
4554 | ||
4555 | if (expr.X_op == O_constant) | |
4556 | { | |
4557 | if (expr.X_add_number | |
4558 | != (expr.X_add_number & 0x0000ffff)) | |
4559 | { | |
4560 | inst.error = _("invalid register mask"); | |
4561 | return FAIL; | |
4562 | } | |
4563 | ||
4564 | if ((range & expr.X_add_number) != 0) | |
4565 | { | |
4566 | int regno = range & expr.X_add_number; | |
4567 | ||
4568 | regno &= -regno; | |
4569 | regno = (1 << regno) - 1; | |
4570 | as_tsktsk | |
4571 | (_("Warning: Duplicated register (r%d) in register list"), | |
4572 | regno); | |
4573 | } | |
4574 | ||
4575 | range |= expr.X_add_number; | |
4576 | } | |
4577 | else | |
4578 | { | |
4579 | if (inst.reloc.type != 0) | |
4580 | { | |
4581 | inst.error = _("expression too complex"); | |
4582 | return FAIL; | |
4583 | } | |
4584 | ||
4585 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); | |
4586 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
4587 | inst.reloc.pc_rel = 0; | |
4588 | } | |
4589 | } | |
4590 | ||
4591 | skip_whitespace (str); | |
4592 | ||
4593 | if (*str == '|' || *str == '+') | |
4594 | { | |
4595 | str++; | |
4596 | another_range = 1; | |
4597 | } | |
4598 | } | |
4599 | while (another_range); | |
4600 | ||
4601 | *strp = str; | |
4602 | return range; | |
4603 | } | |
4604 | ||
4605 | static void | |
4606 | do_ldmstm (str, flags) | |
4607 | char * str; | |
4608 | unsigned long flags; | |
4609 | { | |
4610 | int base_reg; | |
4611 | long range; | |
4612 | ||
4613 | skip_whitespace (str); | |
4614 | ||
4615 | if ((base_reg = reg_required_here (&str, 16)) == FAIL) | |
4616 | return; | |
4617 | ||
4618 | if (base_reg == REG_PC) | |
4619 | { | |
4620 | inst.error = _("r15 not allowed as base register"); | |
4621 | return; | |
4622 | } | |
4623 | ||
4624 | skip_whitespace (str); | |
4625 | ||
4626 | if (*str == '!') | |
4627 | { | |
4628 | flags |= WRITE_BACK; | |
4629 | str++; | |
4630 | } | |
4631 | ||
4632 | if (skip_past_comma (&str) == FAIL | |
4633 | || (range = reg_list (&str)) == FAIL) | |
4634 | { | |
4635 | if (! inst.error) | |
4636 | inst.error = BAD_ARGS; | |
4637 | return; | |
4638 | } | |
4639 | ||
4640 | if (*str == '^') | |
4641 | { | |
4642 | str++; | |
4643 | flags |= LDM_TYPE_2_OR_3; | |
4644 | } | |
4645 | ||
4646 | inst.instruction |= flags | range; | |
4647 | end_of_line (str); | |
4648 | return; | |
4649 | } | |
4650 | ||
4651 | static void | |
4652 | do_swi (str, flags) | |
4653 | char * str; | |
4654 | unsigned long flags; | |
4655 | { | |
4656 | skip_whitespace (str); | |
4657 | ||
4658 | /* Allow optional leading '#'. */ | |
4659 | if (is_immediate_prefix (*str)) | |
4660 | str++; | |
4661 | ||
4662 | if (my_get_expression (& inst.reloc.exp, & str)) | |
4663 | return; | |
4664 | ||
4665 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
4666 | inst.reloc.pc_rel = 0; | |
4667 | inst.instruction |= flags; | |
4668 | ||
4669 | end_of_line (str); | |
4670 | ||
4671 | return; | |
4672 | } | |
4673 | ||
4674 | static void | |
4675 | do_swap (str, flags) | |
4676 | char * str; | |
4677 | unsigned long flags; | |
4678 | { | |
4679 | int reg; | |
4680 | ||
4681 | skip_whitespace (str); | |
4682 | ||
4683 | if ((reg = reg_required_here (&str, 12)) == FAIL) | |
4684 | return; | |
4685 | ||
4686 | if (reg == REG_PC) | |
4687 | { | |
4688 | inst.error = _("r15 not allowed in swap"); | |
4689 | return; | |
4690 | } | |
4691 | ||
4692 | if (skip_past_comma (&str) == FAIL | |
4693 | || (reg = reg_required_here (&str, 0)) == FAIL) | |
4694 | { | |
4695 | if (!inst.error) | |
4696 | inst.error = BAD_ARGS; | |
4697 | return; | |
4698 | } | |
4699 | ||
4700 | if (reg == REG_PC) | |
4701 | { | |
4702 | inst.error = _("r15 not allowed in swap"); | |
4703 | return; | |
4704 | } | |
4705 | ||
4706 | if (skip_past_comma (&str) == FAIL | |
4707 | || *str++ != '[') | |
4708 | { | |
4709 | inst.error = BAD_ARGS; | |
4710 | return; | |
4711 | } | |
4712 | ||
4713 | skip_whitespace (str); | |
4714 | ||
4715 | if ((reg = reg_required_here (&str, 16)) == FAIL) | |
4716 | return; | |
4717 | ||
4718 | if (reg == REG_PC) | |
4719 | { | |
4720 | inst.error = BAD_PC; | |
4721 | return; | |
4722 | } | |
4723 | ||
4724 | skip_whitespace (str); | |
4725 | ||
4726 | if (*str++ != ']') | |
4727 | { | |
4728 | inst.error = _("missing ]"); | |
4729 | return; | |
4730 | } | |
4731 | ||
4732 | inst.instruction |= flags; | |
4733 | end_of_line (str); | |
4734 | return; | |
4735 | } | |
4736 | ||
4737 | static void | |
4738 | do_branch (str, flags) | |
4739 | char * str; | |
4740 | unsigned long flags ATTRIBUTE_UNUSED; | |
4741 | { | |
4742 | if (my_get_expression (&inst.reloc.exp, &str)) | |
4743 | return; | |
4744 | ||
4745 | #ifdef OBJ_ELF | |
4746 | { | |
4747 | char * save_in; | |
4748 | ||
4749 | /* ScottB: February 5, 1998 - Check to see of PLT32 reloc | |
4750 | required for the instruction. */ | |
4751 | ||
4752 | /* arm_parse_reloc () works on input_line_pointer. | |
4753 | We actually want to parse the operands to the branch instruction | |
4754 | passed in 'str'. Save the input pointer and restore it later. */ | |
4755 | save_in = input_line_pointer; | |
4756 | input_line_pointer = str; | |
4757 | if (inst.reloc.exp.X_op == O_symbol | |
4758 | && *str == '(' | |
4759 | && arm_parse_reloc () == BFD_RELOC_ARM_PLT32) | |
4760 | { | |
4761 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
4762 | inst.reloc.pc_rel = 0; | |
4763 | /* Modify str to point to after parsed operands, otherwise | |
4764 | end_of_line() will complain about the (PLT) left in str. */ | |
4765 | str = input_line_pointer; | |
4766 | } | |
4767 | else | |
4768 | { | |
4769 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH; | |
4770 | inst.reloc.pc_rel = 1; | |
4771 | } | |
4772 | input_line_pointer = save_in; | |
4773 | } | |
4774 | #else | |
4775 | inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH; | |
4776 | inst.reloc.pc_rel = 1; | |
4777 | #endif /* OBJ_ELF */ | |
4778 | ||
4779 | end_of_line (str); | |
4780 | return; | |
4781 | } | |
4782 | ||
4783 | static void | |
4784 | do_bx (str, flags) | |
4785 | char * str; | |
4786 | unsigned long flags ATTRIBUTE_UNUSED; | |
4787 | { | |
4788 | int reg; | |
4789 | ||
4790 | skip_whitespace (str); | |
4791 | ||
4792 | if ((reg = reg_required_here (&str, 0)) == FAIL) | |
4793 | { | |
4794 | inst.error = BAD_ARGS; | |
4795 | return; | |
4796 | } | |
4797 | ||
4798 | /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */ | |
4799 | if (reg == REG_PC) | |
4800 | as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful")); | |
4801 | ||
4802 | end_of_line (str); | |
4803 | } | |
4804 | ||
4805 | static void | |
4806 | do_cdp (str, flags) | |
4807 | char * str; | |
4808 | unsigned long flags ATTRIBUTE_UNUSED; | |
4809 | { | |
4810 | /* Co-processor data operation. | |
4811 | Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */ | |
4812 | skip_whitespace (str); | |
4813 | ||
4814 | if (co_proc_number (&str) == FAIL) | |
4815 | { | |
4816 | if (!inst.error) | |
4817 | inst.error = BAD_ARGS; | |
4818 | return; | |
4819 | } | |
4820 | ||
4821 | if (skip_past_comma (&str) == FAIL | |
4822 | || cp_opc_expr (&str, 20,4) == FAIL) | |
4823 | { | |
4824 | if (!inst.error) | |
4825 | inst.error = BAD_ARGS; | |
4826 | return; | |
4827 | } | |
4828 | ||
4829 | if (skip_past_comma (&str) == FAIL | |
4830 | || cp_reg_required_here (&str, 12) == FAIL) | |
4831 | { | |
4832 | if (!inst.error) | |
4833 | inst.error = BAD_ARGS; | |
4834 | return; | |
4835 | } | |
4836 | ||
4837 | if (skip_past_comma (&str) == FAIL | |
4838 | || cp_reg_required_here (&str, 16) == FAIL) | |
4839 | { | |
4840 | if (!inst.error) | |
4841 | inst.error = BAD_ARGS; | |
4842 | return; | |
4843 | } | |
4844 | ||
4845 | if (skip_past_comma (&str) == FAIL | |
4846 | || cp_reg_required_here (&str, 0) == FAIL) | |
4847 | { | |
4848 | if (!inst.error) | |
4849 | inst.error = BAD_ARGS; | |
4850 | return; | |
4851 | } | |
4852 | ||
4853 | if (skip_past_comma (&str) == SUCCESS) | |
4854 | { | |
4855 | if (cp_opc_expr (&str, 5, 3) == FAIL) | |
4856 | { | |
4857 | if (!inst.error) | |
4858 | inst.error = BAD_ARGS; | |
4859 | return; | |
4860 | } | |
4861 | } | |
4862 | ||
4863 | end_of_line (str); | |
4864 | return; | |
4865 | } | |
4866 | ||
4867 | static void | |
4868 | do_lstc (str, flags) | |
4869 | char * str; | |
4870 | unsigned long flags; | |
4871 | { | |
4872 | /* Co-processor register load/store. | |
4873 | Format: <LDC|STC{cond}[L] CP#,CRd,<address> */ | |
4874 | ||
4875 | skip_whitespace (str); | |
4876 | ||
4877 | if (co_proc_number (&str) == FAIL) | |
4878 | { | |
4879 | if (!inst.error) | |
4880 | inst.error = BAD_ARGS; | |
4881 | return; | |
4882 | } | |
4883 | ||
4884 | if (skip_past_comma (&str) == FAIL | |
4885 | || cp_reg_required_here (&str, 12) == FAIL) | |
4886 | { | |
4887 | if (!inst.error) | |
4888 | inst.error = BAD_ARGS; | |
4889 | return; | |
4890 | } | |
4891 | ||
4892 | if (skip_past_comma (&str) == FAIL | |
4893 | || cp_address_required_here (&str) == FAIL) | |
4894 | { | |
4895 | if (! inst.error) | |
4896 | inst.error = BAD_ARGS; | |
4897 | return; | |
4898 | } | |
4899 | ||
4900 | inst.instruction |= flags; | |
4901 | end_of_line (str); | |
4902 | return; | |
4903 | } | |
4904 | ||
4905 | static void | |
4906 | do_co_reg (str, flags) | |
4907 | char * str; | |
4908 | unsigned long flags; | |
4909 | { | |
4910 | /* Co-processor register transfer. | |
4911 | Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */ | |
4912 | ||
4913 | skip_whitespace (str); | |
4914 | ||
4915 | if (co_proc_number (&str) == FAIL) | |
4916 | { | |
4917 | if (!inst.error) | |
4918 | inst.error = BAD_ARGS; | |
4919 | return; | |
4920 | } | |
4921 | ||
4922 | if (skip_past_comma (&str) == FAIL | |
4923 | || cp_opc_expr (&str, 21, 3) == FAIL) | |
4924 | { | |
4925 | if (!inst.error) | |
4926 | inst.error = BAD_ARGS; | |
4927 | return; | |
4928 | } | |
4929 | ||
4930 | if (skip_past_comma (&str) == FAIL | |
4931 | || reg_required_here (&str, 12) == FAIL) | |
4932 | { | |
4933 | if (!inst.error) | |
4934 | inst.error = BAD_ARGS; | |
4935 | return; | |
4936 | } | |
4937 | ||
4938 | if (skip_past_comma (&str) == FAIL | |
4939 | || cp_reg_required_here (&str, 16) == FAIL) | |
4940 | { | |
4941 | if (!inst.error) | |
4942 | inst.error = BAD_ARGS; | |
4943 | return; | |
4944 | } | |
4945 | ||
4946 | if (skip_past_comma (&str) == FAIL | |
4947 | || cp_reg_required_here (&str, 0) == FAIL) | |
4948 | { | |
4949 | if (!inst.error) | |
4950 | inst.error = BAD_ARGS; | |
4951 | return; | |
4952 | } | |
4953 | ||
4954 | if (skip_past_comma (&str) == SUCCESS) | |
4955 | { | |
4956 | if (cp_opc_expr (&str, 5, 3) == FAIL) | |
4957 | { | |
4958 | if (!inst.error) | |
4959 | inst.error = BAD_ARGS; | |
4960 | return; | |
4961 | } | |
4962 | } | |
4963 | if (flags) | |
4964 | { | |
4965 | inst.error = BAD_COND; | |
4966 | } | |
4967 | ||
4968 | end_of_line (str); | |
4969 | return; | |
4970 | } | |
4971 | ||
4972 | static void | |
4973 | do_fp_ctrl (str, flags) | |
4974 | char * str; | |
4975 | unsigned long flags ATTRIBUTE_UNUSED; | |
4976 | { | |
4977 | /* FP control registers. | |
4978 | Format: <WFS|RFS|WFC|RFC>{cond} Rn */ | |
4979 | ||
4980 | skip_whitespace (str); | |
4981 | ||
4982 | if (reg_required_here (&str, 12) == FAIL) | |
4983 | { | |
4984 | if (!inst.error) | |
4985 | inst.error = BAD_ARGS; | |
4986 | return; | |
4987 | } | |
4988 | ||
4989 | end_of_line (str); | |
4990 | return; | |
4991 | } | |
4992 | ||
4993 | static void | |
4994 | do_fp_ldst (str, flags) | |
4995 | char * str; | |
4996 | unsigned long flags ATTRIBUTE_UNUSED; | |
4997 | { | |
4998 | skip_whitespace (str); | |
4999 | ||
5000 | switch (inst.suffix) | |
5001 | { | |
5002 | case SUFF_S: | |
5003 | break; | |
5004 | case SUFF_D: | |
5005 | inst.instruction |= CP_T_X; | |
5006 | break; | |
5007 | case SUFF_E: | |
5008 | inst.instruction |= CP_T_Y; | |
5009 | break; | |
5010 | case SUFF_P: | |
5011 | inst.instruction |= CP_T_X | CP_T_Y; | |
5012 | break; | |
5013 | default: | |
5014 | abort (); | |
5015 | } | |
5016 | ||
5017 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5018 | { | |
5019 | if (!inst.error) | |
5020 | inst.error = BAD_ARGS; | |
5021 | return; | |
5022 | } | |
5023 | ||
5024 | if (skip_past_comma (&str) == FAIL | |
5025 | || cp_address_required_here (&str) == FAIL) | |
5026 | { | |
5027 | if (!inst.error) | |
5028 | inst.error = BAD_ARGS; | |
5029 | return; | |
5030 | } | |
5031 | ||
5032 | end_of_line (str); | |
5033 | } | |
5034 | ||
5035 | static void | |
5036 | do_fp_ldmstm (str, flags) | |
5037 | char * str; | |
5038 | unsigned long flags; | |
5039 | { | |
5040 | int num_regs; | |
5041 | ||
5042 | skip_whitespace (str); | |
5043 | ||
5044 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5045 | { | |
5046 | if (! inst.error) | |
5047 | inst.error = BAD_ARGS; | |
5048 | return; | |
5049 | } | |
5050 | ||
5051 | /* Get Number of registers to transfer. */ | |
5052 | if (skip_past_comma (&str) == FAIL | |
5053 | || my_get_expression (&inst.reloc.exp, &str)) | |
5054 | { | |
5055 | if (! inst.error) | |
5056 | inst.error = _("constant expression expected"); | |
5057 | return; | |
5058 | } | |
5059 | ||
5060 | if (inst.reloc.exp.X_op != O_constant) | |
5061 | { | |
5062 | inst.error = _("Constant value required for number of registers"); | |
5063 | return; | |
5064 | } | |
5065 | ||
5066 | num_regs = inst.reloc.exp.X_add_number; | |
5067 | ||
5068 | if (num_regs < 1 || num_regs > 4) | |
5069 | { | |
5070 | inst.error = _("number of registers must be in the range [1:4]"); | |
5071 | return; | |
5072 | } | |
5073 | ||
5074 | switch (num_regs) | |
5075 | { | |
5076 | case 1: | |
5077 | inst.instruction |= CP_T_X; | |
5078 | break; | |
5079 | case 2: | |
5080 | inst.instruction |= CP_T_Y; | |
5081 | break; | |
5082 | case 3: | |
5083 | inst.instruction |= CP_T_Y | CP_T_X; | |
5084 | break; | |
5085 | case 4: | |
5086 | break; | |
5087 | default: | |
5088 | abort (); | |
5089 | } | |
5090 | ||
5091 | if (flags) | |
5092 | { | |
5093 | int reg; | |
5094 | int write_back; | |
5095 | int offset; | |
5096 | ||
5097 | /* The instruction specified "ea" or "fd", so we can only accept | |
5098 | [Rn]{!}. The instruction does not really support stacking or | |
5099 | unstacking, so we have to emulate these by setting appropriate | |
5100 | bits and offsets. */ | |
5101 | if (skip_past_comma (&str) == FAIL | |
5102 | || *str != '[') | |
5103 | { | |
5104 | if (! inst.error) | |
5105 | inst.error = BAD_ARGS; | |
5106 | return; | |
5107 | } | |
5108 | ||
5109 | str++; | |
5110 | skip_whitespace (str); | |
5111 | ||
5112 | if ((reg = reg_required_here (&str, 16)) == FAIL) | |
5113 | return; | |
5114 | ||
5115 | skip_whitespace (str); | |
5116 | ||
5117 | if (*str != ']') | |
5118 | { | |
5119 | inst.error = BAD_ARGS; | |
5120 | return; | |
5121 | } | |
5122 | ||
5123 | str++; | |
5124 | if (*str == '!') | |
5125 | { | |
5126 | write_back = 1; | |
5127 | str++; | |
5128 | if (reg == REG_PC) | |
5129 | { | |
5130 | inst.error = | |
5131 | _("R15 not allowed as base register with write-back"); | |
5132 | return; | |
5133 | } | |
5134 | } | |
5135 | else | |
5136 | write_back = 0; | |
5137 | ||
5138 | if (flags & CP_T_Pre) | |
5139 | { | |
5140 | /* Pre-decrement. */ | |
5141 | offset = 3 * num_regs; | |
5142 | if (write_back) | |
5143 | flags |= CP_T_WB; | |
5144 | } | |
5145 | else | |
5146 | { | |
5147 | /* Post-increment. */ | |
5148 | if (write_back) | |
5149 | { | |
5150 | flags |= CP_T_WB; | |
5151 | offset = 3 * num_regs; | |
5152 | } | |
5153 | else | |
5154 | { | |
5155 | /* No write-back, so convert this into a standard pre-increment | |
5156 | instruction -- aesthetically more pleasing. */ | |
5157 | flags = CP_T_Pre | CP_T_UD; | |
5158 | offset = 0; | |
5159 | } | |
5160 | } | |
5161 | ||
5162 | inst.instruction |= flags | offset; | |
5163 | } | |
5164 | else if (skip_past_comma (&str) == FAIL | |
5165 | || cp_address_required_here (&str) == FAIL) | |
5166 | { | |
5167 | if (! inst.error) | |
5168 | inst.error = BAD_ARGS; | |
5169 | return; | |
5170 | } | |
5171 | ||
5172 | end_of_line (str); | |
5173 | } | |
5174 | ||
5175 | static void | |
5176 | do_fp_dyadic (str, flags) | |
5177 | char * str; | |
5178 | unsigned long flags; | |
5179 | { | |
5180 | skip_whitespace (str); | |
5181 | ||
5182 | switch (inst.suffix) | |
5183 | { | |
5184 | case SUFF_S: | |
5185 | break; | |
5186 | case SUFF_D: | |
5187 | inst.instruction |= 0x00000080; | |
5188 | break; | |
5189 | case SUFF_E: | |
5190 | inst.instruction |= 0x00080000; | |
5191 | break; | |
5192 | default: | |
5193 | abort (); | |
5194 | } | |
5195 | ||
5196 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5197 | { | |
5198 | if (! inst.error) | |
5199 | inst.error = BAD_ARGS; | |
5200 | return; | |
5201 | } | |
5202 | ||
5203 | if (skip_past_comma (&str) == FAIL | |
5204 | || fp_reg_required_here (&str, 16) == FAIL) | |
5205 | { | |
5206 | if (! inst.error) | |
5207 | inst.error = BAD_ARGS; | |
5208 | return; | |
5209 | } | |
5210 | ||
5211 | if (skip_past_comma (&str) == FAIL | |
5212 | || fp_op2 (&str) == FAIL) | |
5213 | { | |
5214 | if (! inst.error) | |
5215 | inst.error = BAD_ARGS; | |
5216 | return; | |
5217 | } | |
5218 | ||
5219 | inst.instruction |= flags; | |
5220 | end_of_line (str); | |
5221 | return; | |
5222 | } | |
5223 | ||
5224 | static void | |
5225 | do_fp_monadic (str, flags) | |
5226 | char * str; | |
5227 | unsigned long flags; | |
5228 | { | |
5229 | skip_whitespace (str); | |
5230 | ||
5231 | switch (inst.suffix) | |
5232 | { | |
5233 | case SUFF_S: | |
5234 | break; | |
5235 | case SUFF_D: | |
5236 | inst.instruction |= 0x00000080; | |
5237 | break; | |
5238 | case SUFF_E: | |
5239 | inst.instruction |= 0x00080000; | |
5240 | break; | |
5241 | default: | |
5242 | abort (); | |
5243 | } | |
5244 | ||
5245 | if (fp_reg_required_here (&str, 12) == FAIL) | |
5246 | { | |
5247 | if (! inst.error) | |
5248 | inst.error = BAD_ARGS; | |
5249 | return; | |
5250 | } | |
5251 | ||
5252 | if (skip_past_comma (&str) == FAIL | |
5253 | || fp_op2 (&str) == FAIL) | |
5254 | { | |
5255 | if (! inst.error) | |
5256 | inst.error = BAD_ARGS; | |
5257 | return; | |
5258 | } | |
5259 | ||
5260 | inst.instruction |= flags; | |
5261 | end_of_line (str); | |
5262 | return; | |
5263 | } | |
5264 | ||
5265 | static void | |
5266 | do_fp_cmp (str, flags) | |
5267 | char * str; | |
5268 | unsigned long flags; | |
5269 | { | |
5270 | skip_whitespace (str); | |
5271 | ||
5272 | if (fp_reg_required_here (&str, 16) == FAIL) | |
5273 | { | |
5274 | if (! inst.error) | |
5275 | inst.error = BAD_ARGS; | |
5276 | return; | |
5277 | } | |
5278 | ||
5279 | if (skip_past_comma (&str) == FAIL | |
5280 | || fp_op2 (&str) == FAIL) | |
5281 | { | |
5282 | if (! inst.error) | |
5283 | inst.error = BAD_ARGS; | |
5284 | return; | |
5285 | } | |
5286 | ||
5287 | inst.instruction |= flags; | |
5288 | end_of_line (str); | |
5289 | return; | |
5290 | } | |
5291 | ||
5292 | static void | |
5293 | do_fp_from_reg (str, flags) | |
5294 | char * str; | |
5295 | unsigned long flags; | |
5296 | { | |
5297 | skip_whitespace (str); | |
5298 | ||
5299 | switch (inst.suffix) | |
5300 | { | |
5301 | case SUFF_S: | |
5302 | break; | |
5303 | case SUFF_D: | |
5304 | inst.instruction |= 0x00000080; | |
5305 | break; | |
5306 | case SUFF_E: | |
5307 | inst.instruction |= 0x00080000; | |
5308 | break; | |
5309 | default: | |
5310 | abort (); | |
5311 | } | |
5312 | ||
5313 | if (fp_reg_required_here (&str, 16) == FAIL) | |
5314 | { | |
5315 | if (! inst.error) | |
5316 | inst.error = BAD_ARGS; | |
5317 | return; | |
5318 | } | |
5319 | ||
5320 | if (skip_past_comma (&str) == FAIL | |
5321 | || reg_required_here (&str, 12) == FAIL) | |
5322 | { | |
5323 | if (! inst.error) | |
5324 | inst.error = BAD_ARGS; | |
5325 | return; | |
5326 | } | |
5327 | ||
5328 | inst.instruction |= flags; | |
5329 | end_of_line (str); | |
5330 | return; | |
5331 | } | |
5332 | ||
5333 | static void | |
5334 | do_fp_to_reg (str, flags) | |
5335 | char * str; | |
5336 | unsigned long flags; | |
5337 | { | |
5338 | skip_whitespace (str); | |
5339 | ||
5340 | if (reg_required_here (&str, 12) == FAIL) | |
5341 | return; | |
5342 | ||
5343 | if (skip_past_comma (&str) == FAIL | |
5344 | || fp_reg_required_here (&str, 0) == FAIL) | |
5345 | { | |
5346 | if (! inst.error) | |
5347 | inst.error = BAD_ARGS; | |
5348 | return; | |
5349 | } | |
5350 | ||
5351 | inst.instruction |= flags; | |
5352 | end_of_line (str); | |
5353 | return; | |
5354 | } | |
5355 | ||
5356 | /* Thumb specific routines. */ | |
5357 | ||
5358 | /* Parse and validate that a register is of the right form, this saves | |
5359 | repeated checking of this information in many similar cases. | |
5360 | Unlike the 32-bit case we do not insert the register into the opcode | |
5361 | here, since the position is often unknown until the full instruction | |
5362 | has been parsed. */ | |
5363 | ||
5364 | static int | |
5365 | thumb_reg (strp, hi_lo) | |
5366 | char ** strp; | |
5367 | int hi_lo; | |
5368 | { | |
5369 | int reg; | |
5370 | ||
5371 | if ((reg = reg_required_here (strp, -1)) == FAIL) | |
5372 | return FAIL; | |
5373 | ||
5374 | switch (hi_lo) | |
5375 | { | |
5376 | case THUMB_REG_LO: | |
5377 | if (reg > 7) | |
5378 | { | |
5379 | inst.error = _("lo register required"); | |
5380 | return FAIL; | |
5381 | } | |
5382 | break; | |
5383 | ||
5384 | case THUMB_REG_HI: | |
5385 | if (reg < 8) | |
5386 | { | |
5387 | inst.error = _("hi register required"); | |
5388 | return FAIL; | |
5389 | } | |
5390 | break; | |
5391 | ||
5392 | default: | |
5393 | break; | |
5394 | } | |
5395 | ||
5396 | return reg; | |
5397 | } | |
5398 | ||
5399 | /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode | |
5400 | was SUB. */ | |
5401 | ||
5402 | static void | |
5403 | thumb_add_sub (str, subtract) | |
5404 | char * str; | |
5405 | int subtract; | |
5406 | { | |
5407 | int Rd, Rs, Rn = FAIL; | |
5408 | ||
5409 | skip_whitespace (str); | |
5410 | ||
5411 | if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL | |
5412 | || skip_past_comma (&str) == FAIL) | |
5413 | { | |
5414 | if (! inst.error) | |
5415 | inst.error = BAD_ARGS; | |
5416 | return; | |
5417 | } | |
5418 | ||
5419 | if (is_immediate_prefix (*str)) | |
5420 | { | |
5421 | Rs = Rd; | |
5422 | str++; | |
5423 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5424 | return; | |
5425 | } | |
5426 | else | |
5427 | { | |
5428 | if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
5429 | return; | |
5430 | ||
5431 | if (skip_past_comma (&str) == FAIL) | |
5432 | { | |
5433 | /* Two operand format, shuffle the registers | |
5434 | and pretend there are 3. */ | |
5435 | Rn = Rs; | |
5436 | Rs = Rd; | |
5437 | } | |
5438 | else if (is_immediate_prefix (*str)) | |
5439 | { | |
5440 | str++; | |
5441 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5442 | return; | |
5443 | } | |
5444 | else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
5445 | return; | |
5446 | } | |
5447 | ||
5448 | /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL; | |
5449 | for the latter case, EXPR contains the immediate that was found. */ | |
5450 | if (Rn != FAIL) | |
5451 | { | |
5452 | /* All register format. */ | |
5453 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
5454 | { | |
5455 | if (Rs != Rd) | |
5456 | { | |
5457 | inst.error = _("dest and source1 must be the same register"); | |
5458 | return; | |
5459 | } | |
5460 | ||
5461 | /* Can't do this for SUB. */ | |
5462 | if (subtract) | |
5463 | { | |
5464 | inst.error = _("subtract valid only on lo regs"); | |
5465 | return; | |
5466 | } | |
5467 | ||
5468 | inst.instruction = (T_OPCODE_ADD_HI | |
5469 | | (Rd > 7 ? THUMB_H1 : 0) | |
5470 | | (Rn > 7 ? THUMB_H2 : 0)); | |
5471 | inst.instruction |= (Rd & 7) | ((Rn & 7) << 3); | |
5472 | } | |
5473 | else | |
5474 | { | |
5475 | inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3; | |
5476 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
5477 | } | |
5478 | } | |
5479 | else | |
5480 | { | |
5481 | /* Immediate expression, now things start to get nasty. */ | |
5482 | ||
5483 | /* First deal with HI regs, only very restricted cases allowed: | |
5484 | Adjusting SP, and using PC or SP to get an address. */ | |
5485 | if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) | |
5486 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC)) | |
5487 | { | |
5488 | inst.error = _("invalid Hi register with immediate"); | |
5489 | return; | |
5490 | } | |
5491 | ||
5492 | if (inst.reloc.exp.X_op != O_constant) | |
5493 | { | |
5494 | /* Value isn't known yet, all we can do is store all the fragments | |
5495 | we know about in the instruction and let the reloc hacking | |
5496 | work it all out. */ | |
5497 | inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs; | |
5498 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
5499 | } | |
5500 | else | |
5501 | { | |
5502 | int offset = inst.reloc.exp.X_add_number; | |
5503 | ||
5504 | if (subtract) | |
5505 | offset = -offset; | |
5506 | ||
5507 | if (offset < 0) | |
5508 | { | |
5509 | offset = -offset; | |
5510 | subtract = 1; | |
5511 | ||
5512 | /* Quick check, in case offset is MIN_INT. */ | |
5513 | if (offset < 0) | |
5514 | { | |
5515 | inst.error = _("immediate value out of range"); | |
5516 | return; | |
5517 | } | |
5518 | } | |
5519 | else | |
5520 | subtract = 0; | |
5521 | ||
5522 | if (Rd == REG_SP) | |
5523 | { | |
5524 | if (offset & ~0x1fc) | |
5525 | { | |
5526 | inst.error = _("invalid immediate value for stack adjust"); | |
5527 | return; | |
5528 | } | |
5529 | inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
5530 | inst.instruction |= offset >> 2; | |
5531 | } | |
5532 | else if (Rs == REG_PC || Rs == REG_SP) | |
5533 | { | |
5534 | if (subtract | |
5535 | || (offset & ~0x3fc)) | |
5536 | { | |
5537 | inst.error = _("invalid immediate for address calculation"); | |
5538 | return; | |
5539 | } | |
5540 | inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC | |
5541 | : T_OPCODE_ADD_SP); | |
5542 | inst.instruction |= (Rd << 8) | (offset >> 2); | |
5543 | } | |
5544 | else if (Rs == Rd) | |
5545 | { | |
5546 | if (offset & ~0xff) | |
5547 | { | |
5548 | inst.error = _("immediate value out of range"); | |
5549 | return; | |
5550 | } | |
5551 | inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
5552 | inst.instruction |= (Rd << 8) | offset; | |
5553 | } | |
5554 | else | |
5555 | { | |
5556 | if (offset & ~0x7) | |
5557 | { | |
5558 | inst.error = _("immediate value out of range"); | |
5559 | return; | |
5560 | } | |
5561 | inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
5562 | inst.instruction |= Rd | (Rs << 3) | (offset << 6); | |
5563 | } | |
5564 | } | |
5565 | } | |
5566 | ||
5567 | end_of_line (str); | |
5568 | } | |
5569 | ||
5570 | static void | |
5571 | thumb_shift (str, shift) | |
5572 | char * str; | |
5573 | int shift; | |
5574 | { | |
5575 | int Rd, Rs, Rn = FAIL; | |
5576 | ||
5577 | skip_whitespace (str); | |
5578 | ||
5579 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
5580 | || skip_past_comma (&str) == FAIL) | |
5581 | { | |
5582 | if (! inst.error) | |
5583 | inst.error = BAD_ARGS; | |
5584 | return; | |
5585 | } | |
5586 | ||
5587 | if (is_immediate_prefix (*str)) | |
5588 | { | |
5589 | /* Two operand immediate format, set Rs to Rd. */ | |
5590 | Rs = Rd; | |
5591 | str ++; | |
5592 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5593 | return; | |
5594 | } | |
5595 | else | |
5596 | { | |
5597 | if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
5598 | return; | |
5599 | ||
5600 | if (skip_past_comma (&str) == FAIL) | |
5601 | { | |
5602 | /* Two operand format, shuffle the registers | |
5603 | and pretend there are 3. */ | |
5604 | Rn = Rs; | |
5605 | Rs = Rd; | |
5606 | } | |
5607 | else if (is_immediate_prefix (*str)) | |
5608 | { | |
5609 | str++; | |
5610 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5611 | return; | |
5612 | } | |
5613 | else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
5614 | return; | |
5615 | } | |
5616 | ||
5617 | /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL; | |
5618 | for the latter case, EXPR contains the immediate that was found. */ | |
5619 | ||
5620 | if (Rn != FAIL) | |
5621 | { | |
5622 | if (Rs != Rd) | |
5623 | { | |
5624 | inst.error = _("source1 and dest must be same register"); | |
5625 | return; | |
5626 | } | |
5627 | ||
5628 | switch (shift) | |
5629 | { | |
5630 | case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break; | |
5631 | case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
5632 | case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
5633 | } | |
5634 | ||
5635 | inst.instruction |= Rd | (Rn << 3); | |
5636 | } | |
5637 | else | |
5638 | { | |
5639 | switch (shift) | |
5640 | { | |
5641 | case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
5642 | case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
5643 | case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
5644 | } | |
5645 | ||
5646 | if (inst.reloc.exp.X_op != O_constant) | |
5647 | { | |
5648 | /* Value isn't known yet, create a dummy reloc and let reloc | |
5649 | hacking fix it up. */ | |
5650 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
5651 | } | |
5652 | else | |
5653 | { | |
5654 | unsigned shift_value = inst.reloc.exp.X_add_number; | |
5655 | ||
5656 | if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL)) | |
5657 | { | |
5658 | inst.error = _("Invalid immediate for shift"); | |
5659 | return; | |
5660 | } | |
5661 | ||
5662 | /* Shifts of zero are handled by converting to LSL. */ | |
5663 | if (shift_value == 0) | |
5664 | inst.instruction = T_OPCODE_LSL_I; | |
5665 | ||
5666 | /* Shifts of 32 are encoded as a shift of zero. */ | |
5667 | if (shift_value == 32) | |
5668 | shift_value = 0; | |
5669 | ||
5670 | inst.instruction |= shift_value << 6; | |
5671 | } | |
5672 | ||
5673 | inst.instruction |= Rd | (Rs << 3); | |
5674 | } | |
5675 | ||
5676 | end_of_line (str); | |
5677 | } | |
5678 | ||
5679 | static void | |
5680 | thumb_mov_compare (str, move) | |
5681 | char * str; | |
5682 | int move; | |
5683 | { | |
5684 | int Rd, Rs = FAIL; | |
5685 | ||
5686 | skip_whitespace (str); | |
5687 | ||
5688 | if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL | |
5689 | || skip_past_comma (&str) == FAIL) | |
5690 | { | |
5691 | if (! inst.error) | |
5692 | inst.error = BAD_ARGS; | |
5693 | return; | |
5694 | } | |
5695 | ||
5696 | if (is_immediate_prefix (*str)) | |
5697 | { | |
5698 | str++; | |
5699 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5700 | return; | |
5701 | } | |
5702 | else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
5703 | return; | |
5704 | ||
5705 | if (Rs != FAIL) | |
5706 | { | |
5707 | if (Rs < 8 && Rd < 8) | |
5708 | { | |
5709 | if (move == THUMB_MOVE) | |
5710 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 | |
5711 | since a MOV instruction produces unpredictable results. */ | |
5712 | inst.instruction = T_OPCODE_ADD_I3; | |
5713 | else | |
5714 | inst.instruction = T_OPCODE_CMP_LR; | |
5715 | inst.instruction |= Rd | (Rs << 3); | |
5716 | } | |
5717 | else | |
5718 | { | |
5719 | if (move == THUMB_MOVE) | |
5720 | inst.instruction = T_OPCODE_MOV_HR; | |
5721 | else | |
5722 | inst.instruction = T_OPCODE_CMP_HR; | |
5723 | ||
5724 | if (Rd > 7) | |
5725 | inst.instruction |= THUMB_H1; | |
5726 | ||
5727 | if (Rs > 7) | |
5728 | inst.instruction |= THUMB_H2; | |
5729 | ||
5730 | inst.instruction |= (Rd & 7) | ((Rs & 7) << 3); | |
5731 | } | |
5732 | } | |
5733 | else | |
5734 | { | |
5735 | if (Rd > 7) | |
5736 | { | |
5737 | inst.error = _("only lo regs allowed with immediate"); | |
5738 | return; | |
5739 | } | |
5740 | ||
5741 | if (move == THUMB_MOVE) | |
5742 | inst.instruction = T_OPCODE_MOV_I8; | |
5743 | else | |
5744 | inst.instruction = T_OPCODE_CMP_I8; | |
5745 | ||
5746 | inst.instruction |= Rd << 8; | |
5747 | ||
5748 | if (inst.reloc.exp.X_op != O_constant) | |
5749 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
5750 | else | |
5751 | { | |
5752 | unsigned value = inst.reloc.exp.X_add_number; | |
5753 | ||
5754 | if (value > 255) | |
5755 | { | |
5756 | inst.error = _("invalid immediate"); | |
5757 | return; | |
5758 | } | |
5759 | ||
5760 | inst.instruction |= value; | |
5761 | } | |
5762 | } | |
5763 | ||
5764 | end_of_line (str); | |
5765 | } | |
5766 | ||
5767 | static void | |
5768 | thumb_load_store (str, load_store, size) | |
5769 | char * str; | |
5770 | int load_store; | |
5771 | int size; | |
5772 | { | |
5773 | int Rd, Rb, Ro = FAIL; | |
5774 | ||
5775 | skip_whitespace (str); | |
5776 | ||
5777 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
5778 | || skip_past_comma (&str) == FAIL) | |
5779 | { | |
5780 | if (! inst.error) | |
5781 | inst.error = BAD_ARGS; | |
5782 | return; | |
5783 | } | |
5784 | ||
5785 | if (*str == '[') | |
5786 | { | |
5787 | str++; | |
5788 | if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
5789 | return; | |
5790 | ||
5791 | if (skip_past_comma (&str) != FAIL) | |
5792 | { | |
5793 | if (is_immediate_prefix (*str)) | |
5794 | { | |
5795 | str++; | |
5796 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5797 | return; | |
5798 | } | |
5799 | else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
5800 | return; | |
5801 | } | |
5802 | else | |
5803 | { | |
5804 | inst.reloc.exp.X_op = O_constant; | |
5805 | inst.reloc.exp.X_add_number = 0; | |
5806 | } | |
5807 | ||
5808 | if (*str != ']') | |
5809 | { | |
5810 | inst.error = _("expected ']'"); | |
5811 | return; | |
5812 | } | |
5813 | str++; | |
5814 | } | |
5815 | else if (*str == '=') | |
5816 | { | |
5817 | /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */ | |
5818 | str++; | |
5819 | ||
5820 | skip_whitespace (str); | |
5821 | ||
5822 | if (my_get_expression (& inst.reloc.exp, & str)) | |
5823 | return; | |
5824 | ||
5825 | end_of_line (str); | |
5826 | ||
5827 | if ( inst.reloc.exp.X_op != O_constant | |
5828 | && inst.reloc.exp.X_op != O_symbol) | |
5829 | { | |
5830 | inst.error = "Constant expression expected"; | |
5831 | return; | |
5832 | } | |
5833 | ||
5834 | if (inst.reloc.exp.X_op == O_constant | |
5835 | && ((inst.reloc.exp.X_add_number & ~0xFF) == 0)) | |
5836 | { | |
5837 | /* This can be done with a mov instruction. */ | |
5838 | ||
5839 | inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8); | |
5840 | inst.instruction |= inst.reloc.exp.X_add_number; | |
5841 | return; | |
5842 | } | |
5843 | ||
5844 | /* Insert into literal pool. */ | |
5845 | if (add_to_lit_pool () == FAIL) | |
5846 | { | |
5847 | if (!inst.error) | |
5848 | inst.error = "literal pool insertion failed"; | |
5849 | return; | |
5850 | } | |
5851 | ||
5852 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
5853 | inst.reloc.pc_rel = 1; | |
5854 | inst.instruction = T_OPCODE_LDR_PC | (Rd << 8); | |
5855 | /* Adjust ARM pipeline offset to Thumb. */ | |
5856 | inst.reloc.exp.X_add_number += 4; | |
5857 | ||
5858 | return; | |
5859 | } | |
5860 | else | |
5861 | { | |
5862 | if (my_get_expression (&inst.reloc.exp, &str)) | |
5863 | return; | |
5864 | ||
5865 | inst.instruction = T_OPCODE_LDR_PC | (Rd << 8); | |
5866 | inst.reloc.pc_rel = 1; | |
5867 | inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */ | |
5868 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
5869 | end_of_line (str); | |
5870 | return; | |
5871 | } | |
5872 | ||
5873 | if (Rb == REG_PC || Rb == REG_SP) | |
5874 | { | |
5875 | if (size != THUMB_WORD) | |
5876 | { | |
5877 | inst.error = _("byte or halfword not valid for base register"); | |
5878 | return; | |
5879 | } | |
5880 | else if (Rb == REG_PC && load_store != THUMB_LOAD) | |
5881 | { | |
5882 | inst.error = _("R15 based store not allowed"); | |
5883 | return; | |
5884 | } | |
5885 | else if (Ro != FAIL) | |
5886 | { | |
5887 | inst.error = _("Invalid base register for register offset"); | |
5888 | return; | |
5889 | } | |
5890 | ||
5891 | if (Rb == REG_PC) | |
5892 | inst.instruction = T_OPCODE_LDR_PC; | |
5893 | else if (load_store == THUMB_LOAD) | |
5894 | inst.instruction = T_OPCODE_LDR_SP; | |
5895 | else | |
5896 | inst.instruction = T_OPCODE_STR_SP; | |
5897 | ||
5898 | inst.instruction |= Rd << 8; | |
5899 | if (inst.reloc.exp.X_op == O_constant) | |
5900 | { | |
5901 | unsigned offset = inst.reloc.exp.X_add_number; | |
5902 | ||
5903 | if (offset & ~0x3fc) | |
5904 | { | |
5905 | inst.error = _("invalid offset"); | |
5906 | return; | |
5907 | } | |
5908 | ||
5909 | inst.instruction |= offset >> 2; | |
5910 | } | |
5911 | else | |
5912 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
5913 | } | |
5914 | else if (Rb > 7) | |
5915 | { | |
5916 | inst.error = _("invalid base register in load/store"); | |
5917 | return; | |
5918 | } | |
5919 | else if (Ro == FAIL) | |
5920 | { | |
5921 | /* Immediate offset. */ | |
5922 | if (size == THUMB_WORD) | |
5923 | inst.instruction = (load_store == THUMB_LOAD | |
5924 | ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW); | |
5925 | else if (size == THUMB_HALFWORD) | |
5926 | inst.instruction = (load_store == THUMB_LOAD | |
5927 | ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH); | |
5928 | else | |
5929 | inst.instruction = (load_store == THUMB_LOAD | |
5930 | ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB); | |
5931 | ||
5932 | inst.instruction |= Rd | (Rb << 3); | |
5933 | ||
5934 | if (inst.reloc.exp.X_op == O_constant) | |
5935 | { | |
5936 | unsigned offset = inst.reloc.exp.X_add_number; | |
5937 | ||
5938 | if (offset & ~(0x1f << size)) | |
5939 | { | |
5940 | inst.error = _("Invalid offset"); | |
5941 | return; | |
5942 | } | |
5943 | inst.instruction |= (offset >> size) << 6; | |
5944 | } | |
5945 | else | |
5946 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
5947 | } | |
5948 | else | |
5949 | { | |
5950 | /* Register offset. */ | |
5951 | if (size == THUMB_WORD) | |
5952 | inst.instruction = (load_store == THUMB_LOAD | |
5953 | ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW); | |
5954 | else if (size == THUMB_HALFWORD) | |
5955 | inst.instruction = (load_store == THUMB_LOAD | |
5956 | ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH); | |
5957 | else | |
5958 | inst.instruction = (load_store == THUMB_LOAD | |
5959 | ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB); | |
5960 | ||
5961 | inst.instruction |= Rd | (Rb << 3) | (Ro << 6); | |
5962 | } | |
5963 | ||
5964 | end_of_line (str); | |
5965 | } | |
5966 | ||
5967 | static void | |
5968 | do_t_nop (str) | |
5969 | char * str; | |
5970 | { | |
5971 | /* Do nothing. */ | |
5972 | end_of_line (str); | |
5973 | return; | |
5974 | } | |
5975 | ||
5976 | /* Handle the Format 4 instructions that do not have equivalents in other | |
5977 | formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL, | |
5978 | BIC and MVN. */ | |
5979 | ||
5980 | static void | |
5981 | do_t_arit (str) | |
5982 | char * str; | |
5983 | { | |
5984 | int Rd, Rs, Rn; | |
5985 | ||
5986 | skip_whitespace (str); | |
5987 | ||
5988 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
5989 | || skip_past_comma (&str) == FAIL | |
5990 | || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
5991 | { | |
5992 | inst.error = BAD_ARGS; | |
5993 | return; | |
5994 | } | |
5995 | ||
5996 | if (skip_past_comma (&str) != FAIL) | |
5997 | { | |
5998 | /* Three operand format not allowed for TST, CMN, NEG and MVN. | |
5999 | (It isn't allowed for CMP either, but that isn't handled by this | |
6000 | function.) */ | |
6001 | if (inst.instruction == T_OPCODE_TST | |
6002 | || inst.instruction == T_OPCODE_CMN | |
6003 | || inst.instruction == T_OPCODE_NEG | |
6004 | || inst.instruction == T_OPCODE_MVN) | |
6005 | { | |
6006 | inst.error = BAD_ARGS; | |
6007 | return; | |
6008 | } | |
6009 | ||
6010 | if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
6011 | return; | |
6012 | ||
6013 | if (Rs != Rd) | |
6014 | { | |
6015 | inst.error = _("dest and source1 must be the same register"); | |
6016 | return; | |
6017 | } | |
6018 | Rs = Rn; | |
6019 | } | |
6020 | ||
6021 | if (inst.instruction == T_OPCODE_MUL | |
6022 | && Rs == Rd) | |
6023 | as_tsktsk (_("Rs and Rd must be different in MUL")); | |
6024 | ||
6025 | inst.instruction |= Rd | (Rs << 3); | |
6026 | end_of_line (str); | |
6027 | } | |
6028 | ||
6029 | static void | |
6030 | do_t_add (str) | |
6031 | char * str; | |
6032 | { | |
6033 | thumb_add_sub (str, 0); | |
6034 | } | |
6035 | ||
6036 | static void | |
6037 | do_t_asr (str) | |
6038 | char * str; | |
6039 | { | |
6040 | thumb_shift (str, THUMB_ASR); | |
6041 | } | |
6042 | ||
6043 | static void | |
6044 | do_t_branch9 (str) | |
6045 | char * str; | |
6046 | { | |
6047 | if (my_get_expression (&inst.reloc.exp, &str)) | |
6048 | return; | |
6049 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
6050 | inst.reloc.pc_rel = 1; | |
6051 | end_of_line (str); | |
6052 | } | |
6053 | ||
6054 | static void | |
6055 | do_t_branch12 (str) | |
6056 | char * str; | |
6057 | { | |
6058 | if (my_get_expression (&inst.reloc.exp, &str)) | |
6059 | return; | |
6060 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
6061 | inst.reloc.pc_rel = 1; | |
6062 | end_of_line (str); | |
6063 | } | |
6064 | ||
6065 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
6066 | ||
6067 | static symbolS * | |
6068 | find_real_start (symbolP) | |
6069 | symbolS * symbolP; | |
6070 | { | |
6071 | char * real_start; | |
6072 | const char * name = S_GET_NAME (symbolP); | |
6073 | symbolS * new_target; | |
6074 | ||
6075 | /* This definiton must agree with the one in gcc/config/arm/thumb.c. */ | |
6076 | #define STUB_NAME ".real_start_of" | |
6077 | ||
6078 | if (name == NULL) | |
6079 | abort (); | |
6080 | ||
6081 | /* Names that start with '.' are local labels, not function entry points. | |
6082 | The compiler may generate BL instructions to these labels because it | |
6083 | needs to perform a branch to a far away location. */ | |
6084 | if (name[0] == '.') | |
6085 | return symbolP; | |
6086 | ||
6087 | real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1); | |
6088 | sprintf (real_start, "%s%s", STUB_NAME, name); | |
6089 | ||
6090 | new_target = symbol_find (real_start); | |
6091 | ||
6092 | if (new_target == NULL) | |
6093 | { | |
6094 | as_warn ("Failed to find real start of function: %s\n", name); | |
6095 | new_target = symbolP; | |
6096 | } | |
6097 | ||
6098 | free (real_start); | |
6099 | ||
6100 | return new_target; | |
6101 | } | |
6102 | ||
6103 | static void | |
6104 | do_t_branch23 (str) | |
6105 | char * str; | |
6106 | { | |
6107 | if (my_get_expression (& inst.reloc.exp, & str)) | |
6108 | return; | |
6109 | ||
6110 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
6111 | inst.reloc.pc_rel = 1; | |
6112 | end_of_line (str); | |
6113 | ||
6114 | /* If the destination of the branch is a defined symbol which does not have | |
6115 | the THUMB_FUNC attribute, then we must be calling a function which has | |
6116 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
6117 | function and change the branch to refer to that function instead. */ | |
6118 | if ( inst.reloc.exp.X_op == O_symbol | |
6119 | && inst.reloc.exp.X_add_symbol != NULL | |
6120 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
6121 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
6122 | inst.reloc.exp.X_add_symbol = | |
6123 | find_real_start (inst.reloc.exp.X_add_symbol); | |
6124 | } | |
6125 | ||
6126 | static void | |
6127 | do_t_bx (str) | |
6128 | char * str; | |
6129 | { | |
6130 | int reg; | |
6131 | ||
6132 | skip_whitespace (str); | |
6133 | ||
6134 | if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL) | |
6135 | return; | |
6136 | ||
6137 | /* This sets THUMB_H2 from the top bit of reg. */ | |
6138 | inst.instruction |= reg << 3; | |
6139 | ||
6140 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
6141 | should cause the alignment to be checked once it is known. This is | |
6142 | because BX PC only works if the instruction is word aligned. */ | |
6143 | ||
6144 | end_of_line (str); | |
6145 | } | |
6146 | ||
6147 | static void | |
6148 | do_t_compare (str) | |
6149 | char * str; | |
6150 | { | |
6151 | thumb_mov_compare (str, THUMB_COMPARE); | |
6152 | } | |
6153 | ||
6154 | static void | |
6155 | do_t_ldmstm (str) | |
6156 | char * str; | |
6157 | { | |
6158 | int Rb; | |
6159 | long range; | |
6160 | ||
6161 | skip_whitespace (str); | |
6162 | ||
6163 | if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL) | |
6164 | return; | |
6165 | ||
6166 | if (*str != '!') | |
6167 | as_warn (_("Inserted missing '!': load/store multiple always writes back base register")); | |
6168 | else | |
6169 | str++; | |
6170 | ||
6171 | if (skip_past_comma (&str) == FAIL | |
6172 | || (range = reg_list (&str)) == FAIL) | |
6173 | { | |
6174 | if (! inst.error) | |
6175 | inst.error = BAD_ARGS; | |
6176 | return; | |
6177 | } | |
6178 | ||
6179 | if (inst.reloc.type != BFD_RELOC_NONE) | |
6180 | { | |
6181 | /* This really doesn't seem worth it. */ | |
6182 | inst.reloc.type = BFD_RELOC_NONE; | |
6183 | inst.error = _("Expression too complex"); | |
6184 | return; | |
6185 | } | |
6186 | ||
6187 | if (range & ~0xff) | |
6188 | { | |
6189 | inst.error = _("only lo-regs valid in load/store multiple"); | |
6190 | return; | |
6191 | } | |
6192 | ||
6193 | inst.instruction |= (Rb << 8) | range; | |
6194 | end_of_line (str); | |
6195 | } | |
6196 | ||
6197 | static void | |
6198 | do_t_ldr (str) | |
6199 | char * str; | |
6200 | { | |
6201 | thumb_load_store (str, THUMB_LOAD, THUMB_WORD); | |
6202 | } | |
6203 | ||
6204 | static void | |
6205 | do_t_ldrb (str) | |
6206 | char * str; | |
6207 | { | |
6208 | thumb_load_store (str, THUMB_LOAD, THUMB_BYTE); | |
6209 | } | |
6210 | ||
6211 | static void | |
6212 | do_t_ldrh (str) | |
6213 | char * str; | |
6214 | { | |
6215 | thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD); | |
6216 | } | |
6217 | ||
6218 | static void | |
6219 | do_t_lds (str) | |
6220 | char * str; | |
6221 | { | |
6222 | int Rd, Rb, Ro; | |
6223 | ||
6224 | skip_whitespace (str); | |
6225 | ||
6226 | if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
6227 | || skip_past_comma (&str) == FAIL | |
6228 | || *str++ != '[' | |
6229 | || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
6230 | || skip_past_comma (&str) == FAIL | |
6231 | || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL | |
6232 | || *str++ != ']') | |
6233 | { | |
6234 | if (! inst.error) | |
6235 | inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]"); | |
6236 | return; | |
6237 | } | |
6238 | ||
6239 | inst.instruction |= Rd | (Rb << 3) | (Ro << 6); | |
6240 | end_of_line (str); | |
6241 | } | |
6242 | ||
6243 | static void | |
6244 | do_t_lsl (str) | |
6245 | char * str; | |
6246 | { | |
6247 | thumb_shift (str, THUMB_LSL); | |
6248 | } | |
6249 | ||
6250 | static void | |
6251 | do_t_lsr (str) | |
6252 | char * str; | |
6253 | { | |
6254 | thumb_shift (str, THUMB_LSR); | |
6255 | } | |
6256 | ||
6257 | static void | |
6258 | do_t_mov (str) | |
6259 | char * str; | |
6260 | { | |
6261 | thumb_mov_compare (str, THUMB_MOVE); | |
6262 | } | |
6263 | ||
6264 | static void | |
6265 | do_t_push_pop (str) | |
6266 | char * str; | |
6267 | { | |
6268 | long range; | |
6269 | ||
6270 | skip_whitespace (str); | |
6271 | ||
6272 | if ((range = reg_list (&str)) == FAIL) | |
6273 | { | |
6274 | if (! inst.error) | |
6275 | inst.error = BAD_ARGS; | |
6276 | return; | |
6277 | } | |
6278 | ||
6279 | if (inst.reloc.type != BFD_RELOC_NONE) | |
6280 | { | |
6281 | /* This really doesn't seem worth it. */ | |
6282 | inst.reloc.type = BFD_RELOC_NONE; | |
6283 | inst.error = _("Expression too complex"); | |
6284 | return; | |
6285 | } | |
6286 | ||
6287 | if (range & ~0xff) | |
6288 | { | |
6289 | if ((inst.instruction == T_OPCODE_PUSH | |
6290 | && (range & ~0xff) == 1 << REG_LR) | |
6291 | || (inst.instruction == T_OPCODE_POP | |
6292 | && (range & ~0xff) == 1 << REG_PC)) | |
6293 | { | |
6294 | inst.instruction |= THUMB_PP_PC_LR; | |
6295 | range &= 0xff; | |
6296 | } | |
6297 | else | |
6298 | { | |
6299 | inst.error = _("invalid register list to push/pop instruction"); | |
6300 | return; | |
6301 | } | |
6302 | } | |
6303 | ||
6304 | inst.instruction |= range; | |
6305 | end_of_line (str); | |
6306 | } | |
6307 | ||
6308 | static void | |
6309 | do_t_str (str) | |
6310 | char * str; | |
6311 | { | |
6312 | thumb_load_store (str, THUMB_STORE, THUMB_WORD); | |
6313 | } | |
6314 | ||
6315 | static void | |
6316 | do_t_strb (str) | |
6317 | char * str; | |
6318 | { | |
6319 | thumb_load_store (str, THUMB_STORE, THUMB_BYTE); | |
6320 | } | |
6321 | ||
6322 | static void | |
6323 | do_t_strh (str) | |
6324 | char * str; | |
6325 | { | |
6326 | thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD); | |
6327 | } | |
6328 | ||
6329 | static void | |
6330 | do_t_sub (str) | |
6331 | char * str; | |
6332 | { | |
6333 | thumb_add_sub (str, 1); | |
6334 | } | |
6335 | ||
6336 | static void | |
6337 | do_t_swi (str) | |
6338 | char * str; | |
6339 | { | |
6340 | skip_whitespace (str); | |
6341 | ||
6342 | if (my_get_expression (&inst.reloc.exp, &str)) | |
6343 | return; | |
6344 | ||
6345 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
6346 | end_of_line (str); | |
6347 | return; | |
6348 | } | |
6349 | ||
6350 | static void | |
6351 | do_t_adr (str) | |
6352 | char * str; | |
6353 | { | |
6354 | int reg; | |
6355 | ||
6356 | /* This is a pseudo-op of the form "adr rd, label" to be converted | |
6357 | into a relative address of the form "add rd, pc, #label-.-4". */ | |
6358 | skip_whitespace (str); | |
6359 | ||
6360 | /* Store Rd in temporary location inside instruction. */ | |
6361 | if ((reg = reg_required_here (&str, 4)) == FAIL | |
6362 | || (reg > 7) /* For Thumb reg must be r0..r7. */ | |
6363 | || skip_past_comma (&str) == FAIL | |
6364 | || my_get_expression (&inst.reloc.exp, &str)) | |
6365 | { | |
6366 | if (!inst.error) | |
6367 | inst.error = BAD_ARGS; | |
6368 | return; | |
6369 | } | |
6370 | ||
6371 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
6372 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
6373 | inst.reloc.pc_rel = 1; | |
6374 | inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */ | |
6375 | ||
6376 | end_of_line (str); | |
6377 | } | |
6378 | ||
6379 | static void | |
6380 | insert_reg (entry) | |
6381 | int entry; | |
6382 | { | |
6383 | int len = strlen (reg_table[entry].name) + 2; | |
6384 | char * buf = (char *) xmalloc (len); | |
6385 | char * buf2 = (char *) xmalloc (len); | |
6386 | int i = 0; | |
6387 | ||
6388 | #ifdef REGISTER_PREFIX | |
6389 | buf[i++] = REGISTER_PREFIX; | |
6390 | #endif | |
6391 | ||
6392 | strcpy (buf + i, reg_table[entry].name); | |
6393 | ||
6394 | for (i = 0; buf[i]; i++) | |
6395 | buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i]; | |
6396 | ||
6397 | buf2[i] = '\0'; | |
6398 | ||
6399 | hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]); | |
6400 | hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]); | |
6401 | } | |
6402 | ||
6403 | static void | |
6404 | insert_reg_alias (str, regnum) | |
6405 | char *str; | |
6406 | int regnum; | |
6407 | { | |
6408 | struct reg_entry *new = | |
6409 | (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); | |
6410 | char *name = xmalloc (strlen (str) + 1); | |
6411 | strcpy (name, str); | |
6412 | ||
6413 | new->name = name; | |
6414 | new->number = regnum; | |
6415 | ||
6416 | hash_insert (arm_reg_hsh, name, (PTR) new); | |
6417 | } | |
6418 | ||
6419 | static void | |
6420 | set_constant_flonums () | |
6421 | { | |
6422 | int i; | |
6423 | ||
6424 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
6425 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
6426 | abort (); | |
6427 | } | |
6428 | ||
6429 | void | |
6430 | md_begin () | |
6431 | { | |
6432 | unsigned mach; | |
6433 | unsigned int i; | |
6434 | ||
6435 | if ( (arm_ops_hsh = hash_new ()) == NULL | |
6436 | || (arm_tops_hsh = hash_new ()) == NULL | |
6437 | || (arm_cond_hsh = hash_new ()) == NULL | |
6438 | || (arm_shift_hsh = hash_new ()) == NULL | |
6439 | || (arm_reg_hsh = hash_new ()) == NULL | |
6440 | || (arm_psr_hsh = hash_new ()) == NULL) | |
6441 | as_fatal (_("Virtual memory exhausted")); | |
6442 | ||
6443 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
6444 | hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); | |
6445 | for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++) | |
6446 | hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i)); | |
6447 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) | |
6448 | hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); | |
6449 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) | |
6450 | hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); | |
6451 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) | |
6452 | hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); | |
6453 | ||
6454 | for (i = 0; reg_table[i].name; i++) | |
6455 | insert_reg (i); | |
6456 | ||
6457 | set_constant_flonums (); | |
6458 | ||
6459 | #if defined OBJ_COFF || defined OBJ_ELF | |
6460 | { | |
6461 | unsigned int flags = 0; | |
6462 | ||
6463 | /* Set the flags in the private structure. */ | |
6464 | if (uses_apcs_26) flags |= F_APCS26; | |
6465 | if (support_interwork) flags |= F_INTERWORK; | |
6466 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
6467 | if (pic_code) flags |= F_PIC; | |
6468 | if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT; | |
6469 | ||
6470 | bfd_set_private_flags (stdoutput, flags); | |
6471 | ||
6472 | /* We have run out flags in the COFF header to encode the | |
6473 | status of ATPCS support, so instead we create a dummy, | |
6474 | empty, debug section called .arm.atpcs. */ | |
6475 | if (atpcs) | |
6476 | { | |
6477 | asection * sec; | |
6478 | ||
6479 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
6480 | ||
6481 | if (sec != NULL) | |
6482 | { | |
6483 | bfd_set_section_flags | |
6484 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
6485 | bfd_set_section_size (stdoutput, sec, 0); | |
6486 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
6487 | } | |
6488 | } | |
6489 | } | |
6490 | #endif | |
6491 | ||
6492 | /* Record the CPU type as well. */ | |
6493 | switch (cpu_variant & ARM_CPU_MASK) | |
6494 | { | |
6495 | case ARM_2: | |
6496 | mach = bfd_mach_arm_2; | |
6497 | break; | |
6498 | ||
6499 | case ARM_3: /* Also ARM_250. */ | |
6500 | mach = bfd_mach_arm_2a; | |
6501 | break; | |
6502 | ||
6503 | default: | |
6504 | case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */ | |
6505 | mach = bfd_mach_arm_4; | |
6506 | break; | |
6507 | ||
6508 | case ARM_7: /* Also ARM_6. */ | |
6509 | mach = bfd_mach_arm_3; | |
6510 | break; | |
6511 | } | |
6512 | ||
6513 | /* Catch special cases. */ | |
6514 | if (cpu_variant & ARM_EXT_XSCALE) | |
6515 | mach = bfd_mach_arm_XScale; | |
6516 | else if (cpu_variant & ARM_EXT_V5E) | |
6517 | mach = bfd_mach_arm_5TE; | |
6518 | else if (cpu_variant & ARM_EXT_V5) | |
6519 | { | |
6520 | if (cpu_variant & ARM_EXT_THUMB) | |
6521 | mach = bfd_mach_arm_5T; | |
6522 | else | |
6523 | mach = bfd_mach_arm_5; | |
6524 | } | |
6525 | else if (cpu_variant & ARM_EXT_HALFWORD) | |
6526 | { | |
6527 | if (cpu_variant & ARM_EXT_THUMB) | |
6528 | mach = bfd_mach_arm_4T; | |
6529 | else | |
6530 | mach = bfd_mach_arm_4; | |
6531 | } | |
6532 | else if (cpu_variant & ARM_EXT_LONGMUL) | |
6533 | mach = bfd_mach_arm_3M; | |
6534 | ||
6535 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
6536 | } | |
6537 | ||
6538 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate | |
6539 | for use in the a.out file, and stores them in the array pointed to by buf. | |
6540 | This knows about the endian-ness of the target machine and does | |
6541 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
6542 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
6543 | LITTLENUMS (shorts, here at least). */ | |
6544 | ||
6545 | void | |
6546 | md_number_to_chars (buf, val, n) | |
6547 | char * buf; | |
6548 | valueT val; | |
6549 | int n; | |
6550 | { | |
6551 | if (target_big_endian) | |
6552 | number_to_chars_bigendian (buf, val, n); | |
6553 | else | |
6554 | number_to_chars_littleendian (buf, val, n); | |
6555 | } | |
6556 | ||
6557 | static valueT | |
6558 | md_chars_to_number (buf, n) | |
6559 | char * buf; | |
6560 | int n; | |
6561 | { | |
6562 | valueT result = 0; | |
6563 | unsigned char * where = (unsigned char *) buf; | |
6564 | ||
6565 | if (target_big_endian) | |
6566 | { | |
6567 | while (n--) | |
6568 | { | |
6569 | result <<= 8; | |
6570 | result |= (*where++ & 255); | |
6571 | } | |
6572 | } | |
6573 | else | |
6574 | { | |
6575 | while (n--) | |
6576 | { | |
6577 | result <<= 8; | |
6578 | result |= (where[n] & 255); | |
6579 | } | |
6580 | } | |
6581 | ||
6582 | return result; | |
6583 | } | |
6584 | ||
6585 | /* Turn a string in input_line_pointer into a floating point constant | |
6586 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
6587 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
6588 | returned, or NULL on OK. | |
6589 | ||
6590 | Note that fp constants aren't represent in the normal way on the ARM. | |
6591 | In big endian mode, things are as expected. However, in little endian | |
6592 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
6593 | within the words. For example, (double) 1.1 in big endian mode is | |
6594 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
6595 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
6596 | ||
6597 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ | |
6598 | ||
6599 | char * | |
6600 | md_atof (type, litP, sizeP) | |
6601 | char type; | |
6602 | char * litP; | |
6603 | int * sizeP; | |
6604 | { | |
6605 | int prec; | |
6606 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
6607 | char *t; | |
6608 | int i; | |
6609 | ||
6610 | switch (type) | |
6611 | { | |
6612 | case 'f': | |
6613 | case 'F': | |
6614 | case 's': | |
6615 | case 'S': | |
6616 | prec = 2; | |
6617 | break; | |
6618 | ||
6619 | case 'd': | |
6620 | case 'D': | |
6621 | case 'r': | |
6622 | case 'R': | |
6623 | prec = 4; | |
6624 | break; | |
6625 | ||
6626 | case 'x': | |
6627 | case 'X': | |
6628 | prec = 6; | |
6629 | break; | |
6630 | ||
6631 | case 'p': | |
6632 | case 'P': | |
6633 | prec = 6; | |
6634 | break; | |
6635 | ||
6636 | default: | |
6637 | *sizeP = 0; | |
6638 | return _("Bad call to MD_ATOF()"); | |
6639 | } | |
6640 | ||
6641 | t = atof_ieee (input_line_pointer, type, words); | |
6642 | if (t) | |
6643 | input_line_pointer = t; | |
6644 | *sizeP = prec * 2; | |
6645 | ||
6646 | if (target_big_endian) | |
6647 | { | |
6648 | for (i = 0; i < prec; i++) | |
6649 | { | |
6650 | md_number_to_chars (litP, (valueT) words[i], 2); | |
6651 | litP += 2; | |
6652 | } | |
6653 | } | |
6654 | else | |
6655 | { | |
6656 | /* For a 4 byte float the order of elements in `words' is 1 0. For an | |
6657 | 8 byte float the order is 1 0 3 2. */ | |
6658 | for (i = 0; i < prec; i += 2) | |
6659 | { | |
6660 | md_number_to_chars (litP, (valueT) words[i + 1], 2); | |
6661 | md_number_to_chars (litP + 2, (valueT) words[i], 2); | |
6662 | litP += 4; | |
6663 | } | |
6664 | } | |
6665 | ||
6666 | return 0; | |
6667 | } | |
6668 | ||
6669 | /* The knowledge of the PC's pipeline offset is built into the insns | |
6670 | themselves. */ | |
6671 | ||
6672 | long | |
6673 | md_pcrel_from (fixP) | |
6674 | fixS * fixP; | |
6675 | { | |
6676 | if (fixP->fx_addsy | |
6677 | && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section | |
6678 | && fixP->fx_subsy == NULL) | |
6679 | return 0; | |
6680 | ||
6681 | if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD)) | |
6682 | { | |
6683 | /* PC relative addressing on the Thumb is slightly odd | |
6684 | as the bottom two bits of the PC are forced to zero | |
6685 | for the calculation. */ | |
6686 | return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3; | |
6687 | } | |
6688 | ||
6689 | #ifdef TE_WINCE | |
6690 | /* The pattern was adjusted to accomodate CE's off-by-one fixups, | |
6691 | so we un-adjust here to compensate for the accomodation. */ | |
6692 | return fixP->fx_where + fixP->fx_frag->fr_address + 8; | |
6693 | #else | |
6694 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
6695 | #endif | |
6696 | } | |
6697 | ||
6698 | /* Round up a section size to the appropriate boundary. */ | |
6699 | ||
6700 | valueT | |
6701 | md_section_align (segment, size) | |
6702 | segT segment ATTRIBUTE_UNUSED; | |
6703 | valueT size; | |
6704 | { | |
6705 | #ifdef OBJ_ELF | |
6706 | return size; | |
6707 | #else | |
6708 | /* Round all sects to multiple of 4. */ | |
6709 | return (size + 3) & ~3; | |
6710 | #endif | |
6711 | } | |
6712 | ||
6713 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. | |
6714 | Otherwise we have no need to default values of symbols. */ | |
6715 | ||
6716 | symbolS * | |
6717 | md_undefined_symbol (name) | |
6718 | char * name ATTRIBUTE_UNUSED; | |
6719 | { | |
6720 | #ifdef OBJ_ELF | |
6721 | if (name[0] == '_' && name[1] == 'G' | |
6722 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
6723 | { | |
6724 | if (!GOT_symbol) | |
6725 | { | |
6726 | if (symbol_find (name)) | |
6727 | as_bad ("GOT already in the symbol table"); | |
6728 | ||
6729 | GOT_symbol = symbol_new (name, undefined_section, | |
6730 | (valueT) 0, & zero_address_frag); | |
6731 | } | |
6732 | ||
6733 | return GOT_symbol; | |
6734 | } | |
6735 | #endif | |
6736 | ||
6737 | return 0; | |
6738 | } | |
6739 | ||
6740 | /* arm_reg_parse () := if it looks like a register, return its token and | |
6741 | advance the pointer. */ | |
6742 | ||
6743 | static int | |
6744 | arm_reg_parse (ccp) | |
6745 | register char ** ccp; | |
6746 | { | |
6747 | char * start = * ccp; | |
6748 | char c; | |
6749 | char * p; | |
6750 | struct reg_entry * reg; | |
6751 | ||
6752 | #ifdef REGISTER_PREFIX | |
6753 | if (*start != REGISTER_PREFIX) | |
6754 | return FAIL; | |
6755 | p = start + 1; | |
6756 | #else | |
6757 | p = start; | |
6758 | #ifdef OPTIONAL_REGISTER_PREFIX | |
6759 | if (*p == OPTIONAL_REGISTER_PREFIX) | |
6760 | p++, start++; | |
6761 | #endif | |
6762 | #endif | |
6763 | if (!isalpha (*p) || !is_name_beginner (*p)) | |
6764 | return FAIL; | |
6765 | ||
6766 | c = *p++; | |
6767 | while (isalpha (c) || isdigit (c) || c == '_') | |
6768 | c = *p++; | |
6769 | ||
6770 | *--p = 0; | |
6771 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, start); | |
6772 | *p = c; | |
6773 | ||
6774 | if (reg) | |
6775 | { | |
6776 | *ccp = p; | |
6777 | return reg->number; | |
6778 | } | |
6779 | ||
6780 | return FAIL; | |
6781 | } | |
6782 | ||
6783 | int | |
6784 | md_apply_fix3 (fixP, val, seg) | |
6785 | fixS * fixP; | |
6786 | valueT * val; | |
6787 | segT seg; | |
6788 | { | |
6789 | offsetT value = * val; | |
6790 | offsetT newval; | |
6791 | unsigned int newimm; | |
6792 | unsigned long temp; | |
6793 | int sign; | |
6794 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
6795 | arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data; | |
6796 | ||
6797 | assert (fixP->fx_r_type < BFD_RELOC_UNUSED); | |
6798 | ||
6799 | /* Note whether this will delete the relocation. */ | |
6800 | #if 0 | |
6801 | /* Patch from REarnshaw to JDavis (disabled for the moment, since it | |
6802 | doesn't work fully.) */ | |
6803 | if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy)) | |
6804 | && !fixP->fx_pcrel) | |
6805 | #else | |
6806 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
6807 | #endif | |
6808 | fixP->fx_done = 1; | |
6809 | ||
6810 | /* If this symbol is in a different section then we need to leave it for | |
6811 | the linker to deal with. Unfortunately, md_pcrel_from can't tell, | |
6812 | so we have to undo it's effects here. */ | |
6813 | if (fixP->fx_pcrel) | |
6814 | { | |
6815 | if (fixP->fx_addsy != NULL | |
6816 | && S_IS_DEFINED (fixP->fx_addsy) | |
6817 | && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
6818 | { | |
6819 | if (target_oabi | |
6820 | && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH | |
6821 | || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX | |
6822 | )) | |
6823 | value = 0; | |
6824 | else | |
6825 | value += md_pcrel_from (fixP); | |
6826 | } | |
6827 | } | |
6828 | ||
6829 | /* Remember value for emit_reloc. */ | |
6830 | fixP->fx_addnumber = value; | |
6831 | ||
6832 | switch (fixP->fx_r_type) | |
6833 | { | |
6834 | case BFD_RELOC_ARM_IMMEDIATE: | |
6835 | newimm = validate_immediate (value); | |
6836 | temp = md_chars_to_number (buf, INSN_SIZE); | |
6837 | ||
6838 | /* If the instruction will fail, see if we can fix things up by | |
6839 | changing the opcode. */ | |
6840 | if (newimm == (unsigned int) FAIL | |
6841 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
6842 | { | |
6843 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6844 | _("invalid constant (%lx) after fixup"), | |
6845 | (unsigned long) value); | |
6846 | break; | |
6847 | } | |
6848 | ||
6849 | newimm |= (temp & 0xfffff000); | |
6850 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
6851 | break; | |
6852 | ||
6853 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: | |
6854 | { | |
6855 | unsigned int highpart = 0; | |
6856 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
6857 | newimm = validate_immediate (value); | |
6858 | temp = md_chars_to_number (buf, INSN_SIZE); | |
6859 | ||
6860 | /* If the instruction will fail, see if we can fix things up by | |
6861 | changing the opcode. */ | |
6862 | if (newimm == (unsigned int) FAIL | |
6863 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
6864 | { | |
6865 | /* No ? OK - try using two ADD instructions to generate | |
6866 | the value. */ | |
6867 | newimm = validate_immediate_twopart (value, & highpart); | |
6868 | ||
6869 | /* Yes - then make sure that the second instruction is | |
6870 | also an add. */ | |
6871 | if (newimm != (unsigned int) FAIL) | |
6872 | newinsn = temp; | |
6873 | /* Still No ? Try using a negated value. */ | |
6874 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
6875 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
6876 | /* Otherwise - give up. */ | |
6877 | else | |
6878 | { | |
6879 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6880 | _("Unable to compute ADRL instructions for PC offset of 0x%lx"), | |
6881 | value); | |
6882 | break; | |
6883 | } | |
6884 | ||
6885 | /* Replace the first operand in the 2nd instruction (which | |
6886 | is the PC) with the destination register. We have | |
6887 | already added in the PC in the first instruction and we | |
6888 | do not want to do it again. */ | |
6889 | newinsn &= ~ 0xf0000; | |
6890 | newinsn |= ((newinsn & 0x0f000) << 4); | |
6891 | } | |
6892 | ||
6893 | newimm |= (temp & 0xfffff000); | |
6894 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
6895 | ||
6896 | highpart |= (newinsn & 0xfffff000); | |
6897 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
6898 | } | |
6899 | break; | |
6900 | ||
6901 | case BFD_RELOC_ARM_OFFSET_IMM: | |
6902 | sign = value >= 0; | |
6903 | ||
6904 | if (value < 0) | |
6905 | value = - value; | |
6906 | ||
6907 | if (validate_offset_imm (value, 0) == FAIL) | |
6908 | { | |
6909 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6910 | _("bad immediate value for offset (%ld)"), | |
6911 | (long) value); | |
6912 | break; | |
6913 | } | |
6914 | ||
6915 | newval = md_chars_to_number (buf, INSN_SIZE); | |
6916 | newval &= 0xff7ff000; | |
6917 | newval |= value | (sign ? INDEX_UP : 0); | |
6918 | md_number_to_chars (buf, newval, INSN_SIZE); | |
6919 | break; | |
6920 | ||
6921 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
6922 | case BFD_RELOC_ARM_HWLITERAL: | |
6923 | sign = value >= 0; | |
6924 | ||
6925 | if (value < 0) | |
6926 | value = - value; | |
6927 | ||
6928 | if (validate_offset_imm (value, 1) == FAIL) | |
6929 | { | |
6930 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) | |
6931 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6932 | _("invalid literal constant: pool needs to be closer")); | |
6933 | else | |
6934 | as_bad (_("bad immediate value for half-word offset (%ld)"), | |
6935 | (long) value); | |
6936 | break; | |
6937 | } | |
6938 | ||
6939 | newval = md_chars_to_number (buf, INSN_SIZE); | |
6940 | newval &= 0xff7ff0f0; | |
6941 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
6942 | md_number_to_chars (buf, newval, INSN_SIZE); | |
6943 | break; | |
6944 | ||
6945 | case BFD_RELOC_ARM_LITERAL: | |
6946 | sign = value >= 0; | |
6947 | ||
6948 | if (value < 0) | |
6949 | value = - value; | |
6950 | ||
6951 | if (validate_offset_imm (value, 0) == FAIL) | |
6952 | { | |
6953 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6954 | _("invalid literal constant: pool needs to be closer")); | |
6955 | break; | |
6956 | } | |
6957 | ||
6958 | newval = md_chars_to_number (buf, INSN_SIZE); | |
6959 | newval &= 0xff7ff000; | |
6960 | newval |= value | (sign ? INDEX_UP : 0); | |
6961 | md_number_to_chars (buf, newval, INSN_SIZE); | |
6962 | break; | |
6963 | ||
6964 | case BFD_RELOC_ARM_SHIFT_IMM: | |
6965 | newval = md_chars_to_number (buf, INSN_SIZE); | |
6966 | if (((unsigned long) value) > 32 | |
6967 | || (value == 32 | |
6968 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
6969 | { | |
6970 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6971 | _("shift expression is too large")); | |
6972 | break; | |
6973 | } | |
6974 | ||
6975 | if (value == 0) | |
6976 | /* Shifts of zero must be done as lsl. */ | |
6977 | newval &= ~0x60; | |
6978 | else if (value == 32) | |
6979 | value = 0; | |
6980 | newval &= 0xfffff07f; | |
6981 | newval |= (value & 0x1f) << 7; | |
6982 | md_number_to_chars (buf, newval, INSN_SIZE); | |
6983 | break; | |
6984 | ||
6985 | case BFD_RELOC_ARM_SWI: | |
6986 | if (arm_data->thumb_mode) | |
6987 | { | |
6988 | if (((unsigned long) value) > 0xff) | |
6989 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6990 | _("Invalid swi expression")); | |
6991 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00; | |
6992 | newval |= value; | |
6993 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
6994 | } | |
6995 | else | |
6996 | { | |
6997 | if (((unsigned long) value) > 0x00ffffff) | |
6998 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6999 | _("Invalid swi expression")); | |
7000 | newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000; | |
7001 | newval |= value; | |
7002 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7003 | } | |
7004 | break; | |
7005 | ||
7006 | case BFD_RELOC_ARM_MULTI: | |
7007 | if (((unsigned long) value) > 0xffff) | |
7008 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7009 | _("Invalid expression in load/store multiple")); | |
7010 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
7011 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7012 | break; | |
7013 | ||
7014 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
7015 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7016 | ||
7017 | /* Sign-extend a 24-bit number. */ | |
7018 | #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000) | |
7019 | ||
7020 | #ifdef OBJ_ELF | |
7021 | if (! target_oabi) | |
7022 | value = fixP->fx_offset; | |
7023 | #endif | |
7024 | ||
7025 | /* We are going to store value (shifted right by two) in the | |
7026 | instruction, in a 24 bit, signed field. Thus we need to check | |
7027 | that none of the top 8 bits of the shifted value (top 7 bits of | |
7028 | the unshifted, unsigned value) are set, or that they are all set. */ | |
7029 | if ((value & ~ ((offsetT) 0x1ffffff)) != 0 | |
7030 | && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff))) | |
7031 | { | |
7032 | #ifdef OBJ_ELF | |
7033 | /* Normally we would be stuck at this point, since we cannot store | |
7034 | the absolute address that is the destination of the branch in the | |
7035 | 24 bits of the branch instruction. If however, we happen to know | |
7036 | that the destination of the branch is in the same section as the | |
7037 | branch instruciton itself, then we can compute the relocation for | |
7038 | ourselves and not have to bother the linker with it. | |
7039 | ||
7040 | FIXME: The tests for OBJ_ELF and ! target_oabi are only here | |
7041 | because I have not worked out how to do this for OBJ_COFF or | |
7042 | target_oabi. */ | |
7043 | if (! target_oabi | |
7044 | && fixP->fx_addsy != NULL | |
7045 | && S_IS_DEFINED (fixP->fx_addsy) | |
7046 | && S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
7047 | { | |
7048 | /* Get pc relative value to go into the branch. */ | |
7049 | value = * val; | |
7050 | ||
7051 | /* Permit a backward branch provided that enough bits | |
7052 | are set. Allow a forwards branch, provided that | |
7053 | enough bits are clear. */ | |
7054 | if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff) | |
7055 | || (value & ~ ((offsetT) 0x1ffffff)) == 0) | |
7056 | fixP->fx_done = 1; | |
7057 | } | |
7058 | ||
7059 | if (! fixP->fx_done) | |
7060 | #endif | |
7061 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7062 | _("gas can't handle same-section branch dest >= 0x04000000")); | |
7063 | } | |
7064 | ||
7065 | value >>= 2; | |
7066 | value += SEXT24 (newval); | |
7067 | ||
7068 | if ( (value & ~ ((offsetT) 0xffffff)) != 0 | |
7069 | && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff))) | |
7070 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7071 | _("out of range branch")); | |
7072 | ||
7073 | newval = (value & 0x00ffffff) | (newval & 0xff000000); | |
7074 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7075 | break; | |
7076 | ||
7077 | case BFD_RELOC_ARM_PCREL_BLX: | |
7078 | { | |
7079 | offsetT hbit; | |
7080 | newval = md_chars_to_number (buf, INSN_SIZE); | |
7081 | ||
7082 | #ifdef OBJ_ELF | |
7083 | if (! target_oabi) | |
7084 | value = fixP->fx_offset; | |
7085 | #endif | |
7086 | hbit = (value >> 1) & 1; | |
7087 | value = (value >> 2) & 0x00ffffff; | |
7088 | value = (value + (newval & 0x00ffffff)) & 0x00ffffff; | |
7089 | newval = value | (newval & 0xfe000000) | (hbit << 24); | |
7090 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7091 | } | |
7092 | break; | |
7093 | ||
7094 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ | |
7095 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7096 | { | |
7097 | addressT diff = (newval & 0xff) << 1; | |
7098 | if (diff & 0x100) | |
7099 | diff |= ~0xff; | |
7100 | ||
7101 | value += diff; | |
7102 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) | |
7103 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7104 | _("Branch out of range")); | |
7105 | newval = (newval & 0xff00) | ((value & 0x1ff) >> 1); | |
7106 | } | |
7107 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7108 | break; | |
7109 | ||
7110 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ | |
7111 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7112 | { | |
7113 | addressT diff = (newval & 0x7ff) << 1; | |
7114 | if (diff & 0x800) | |
7115 | diff |= ~0x7ff; | |
7116 | ||
7117 | value += diff; | |
7118 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) | |
7119 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7120 | _("Branch out of range")); | |
7121 | newval = (newval & 0xf800) | ((value & 0xfff) >> 1); | |
7122 | } | |
7123 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7124 | break; | |
7125 | ||
7126 | case BFD_RELOC_THUMB_PCREL_BLX: | |
7127 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
7128 | { | |
7129 | offsetT newval2; | |
7130 | addressT diff; | |
7131 | ||
7132 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7133 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
7134 | diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1); | |
7135 | if (diff & 0x400000) | |
7136 | diff |= ~0x3fffff; | |
7137 | #ifdef OBJ_ELF | |
7138 | value = fixP->fx_offset; | |
7139 | #endif | |
7140 | value += diff; | |
7141 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) | |
7142 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7143 | _("Branch with link out of range")); | |
7144 | ||
7145 | newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12); | |
7146 | newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1); | |
7147 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
7148 | /* Remove bit zero of the adjusted offset. Bit zero can only be | |
7149 | set if the upper insn is at a half-word boundary, since the | |
7150 | destination address, an ARM instruction, must always be on a | |
7151 | word boundary. The semantics of the BLX (1) instruction, however, | |
7152 | are that bit zero in the offset must always be zero, and the | |
7153 | corresponding bit one in the target address will be set from bit | |
7154 | one of the source address. */ | |
7155 | newval2 &= ~1; | |
7156 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7157 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
7158 | } | |
7159 | break; | |
7160 | ||
7161 | case BFD_RELOC_8: | |
7162 | if (fixP->fx_done || fixP->fx_pcrel) | |
7163 | md_number_to_chars (buf, value, 1); | |
7164 | #ifdef OBJ_ELF | |
7165 | else if (!target_oabi) | |
7166 | { | |
7167 | value = fixP->fx_offset; | |
7168 | md_number_to_chars (buf, value, 1); | |
7169 | } | |
7170 | #endif | |
7171 | break; | |
7172 | ||
7173 | case BFD_RELOC_16: | |
7174 | if (fixP->fx_done || fixP->fx_pcrel) | |
7175 | md_number_to_chars (buf, value, 2); | |
7176 | #ifdef OBJ_ELF | |
7177 | else if (!target_oabi) | |
7178 | { | |
7179 | value = fixP->fx_offset; | |
7180 | md_number_to_chars (buf, value, 2); | |
7181 | } | |
7182 | #endif | |
7183 | break; | |
7184 | ||
7185 | #ifdef OBJ_ELF | |
7186 | case BFD_RELOC_ARM_GOT32: | |
7187 | case BFD_RELOC_ARM_GOTOFF: | |
7188 | md_number_to_chars (buf, 0, 4); | |
7189 | break; | |
7190 | #endif | |
7191 | ||
7192 | case BFD_RELOC_RVA: | |
7193 | case BFD_RELOC_32: | |
7194 | if (fixP->fx_done || fixP->fx_pcrel) | |
7195 | md_number_to_chars (buf, value, 4); | |
7196 | #ifdef OBJ_ELF | |
7197 | else if (!target_oabi) | |
7198 | { | |
7199 | value = fixP->fx_offset; | |
7200 | md_number_to_chars (buf, value, 4); | |
7201 | } | |
7202 | #endif | |
7203 | break; | |
7204 | ||
7205 | #ifdef OBJ_ELF | |
7206 | case BFD_RELOC_ARM_PLT32: | |
7207 | /* It appears the instruction is fully prepared at this point. */ | |
7208 | break; | |
7209 | #endif | |
7210 | ||
7211 | case BFD_RELOC_ARM_GOTPC: | |
7212 | md_number_to_chars (buf, value, 4); | |
7213 | break; | |
7214 | ||
7215 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
7216 | sign = value >= 0; | |
7217 | if (value < -1023 || value > 1023 || (value & 3)) | |
7218 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7219 | _("Illegal value for co-processor offset")); | |
7220 | if (value < 0) | |
7221 | value = -value; | |
7222 | newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00; | |
7223 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
7224 | md_number_to_chars (buf, newval, INSN_SIZE); | |
7225 | break; | |
7226 | ||
7227 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
7228 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7229 | /* Exactly what ranges, and where the offset is inserted depends | |
7230 | on the type of instruction, we can establish this from the | |
7231 | top 4 bits. */ | |
7232 | switch (newval >> 12) | |
7233 | { | |
7234 | case 4: /* PC load. */ | |
7235 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
7236 | forced to zero for these loads, so we will need to round | |
7237 | up the offset if the instruction address is not word | |
7238 | aligned (since the final address produced must be, and | |
7239 | we can only describe word-aligned immediate offsets). */ | |
7240 | ||
7241 | if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3) | |
7242 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7243 | _("Invalid offset, target not word aligned (0x%08X)"), | |
7244 | (unsigned int) (fixP->fx_frag->fr_address | |
7245 | + fixP->fx_where + value)); | |
7246 | ||
7247 | if ((value + 2) & ~0x3fe) | |
7248 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7249 | _("Invalid offset, value too big (0x%08lX)"), value); | |
7250 | ||
7251 | /* Round up, since pc will be rounded down. */ | |
7252 | newval |= (value + 2) >> 2; | |
7253 | break; | |
7254 | ||
7255 | case 9: /* SP load/store. */ | |
7256 | if (value & ~0x3fc) | |
7257 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7258 | _("Invalid offset, value too big (0x%08lX)"), value); | |
7259 | newval |= value >> 2; | |
7260 | break; | |
7261 | ||
7262 | case 6: /* Word load/store. */ | |
7263 | if (value & ~0x7c) | |
7264 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7265 | _("Invalid offset, value too big (0x%08lX)"), value); | |
7266 | newval |= value << 4; /* 6 - 2. */ | |
7267 | break; | |
7268 | ||
7269 | case 7: /* Byte load/store. */ | |
7270 | if (value & ~0x1f) | |
7271 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7272 | _("Invalid offset, value too big (0x%08lX)"), value); | |
7273 | newval |= value << 6; | |
7274 | break; | |
7275 | ||
7276 | case 8: /* Halfword load/store. */ | |
7277 | if (value & ~0x3e) | |
7278 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7279 | _("Invalid offset, value too big (0x%08lX)"), value); | |
7280 | newval |= value << 5; /* 6 - 1. */ | |
7281 | break; | |
7282 | ||
7283 | default: | |
7284 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7285 | "Unable to process relocation for thumb opcode: %lx", | |
7286 | (unsigned long) newval); | |
7287 | break; | |
7288 | } | |
7289 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7290 | break; | |
7291 | ||
7292 | case BFD_RELOC_ARM_THUMB_ADD: | |
7293 | /* This is a complicated relocation, since we use it for all of | |
7294 | the following immediate relocations: | |
7295 | ||
7296 | 3bit ADD/SUB | |
7297 | 8bit ADD/SUB | |
7298 | 9bit ADD/SUB SP word-aligned | |
7299 | 10bit ADD PC/SP word-aligned | |
7300 | ||
7301 | The type of instruction being processed is encoded in the | |
7302 | instruction field: | |
7303 | ||
7304 | 0x8000 SUB | |
7305 | 0x00F0 Rd | |
7306 | 0x000F Rs | |
7307 | */ | |
7308 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7309 | { | |
7310 | int rd = (newval >> 4) & 0xf; | |
7311 | int rs = newval & 0xf; | |
7312 | int subtract = newval & 0x8000; | |
7313 | ||
7314 | if (rd == REG_SP) | |
7315 | { | |
7316 | if (value & ~0x1fc) | |
7317 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7318 | _("Invalid immediate for stack address calculation")); | |
7319 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
7320 | newval |= value >> 2; | |
7321 | } | |
7322 | else if (rs == REG_PC || rs == REG_SP) | |
7323 | { | |
7324 | if (subtract || | |
7325 | value & ~0x3fc) | |
7326 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7327 | _("Invalid immediate for address calculation (value = 0x%08lX)"), | |
7328 | (unsigned long) value); | |
7329 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
7330 | newval |= rd << 8; | |
7331 | newval |= value >> 2; | |
7332 | } | |
7333 | else if (rs == rd) | |
7334 | { | |
7335 | if (value & ~0xff) | |
7336 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7337 | _("Invalid 8bit immediate")); | |
7338 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
7339 | newval |= (rd << 8) | value; | |
7340 | } | |
7341 | else | |
7342 | { | |
7343 | if (value & ~0x7) | |
7344 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7345 | _("Invalid 3bit immediate")); | |
7346 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
7347 | newval |= rd | (rs << 3) | (value << 6); | |
7348 | } | |
7349 | } | |
7350 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7351 | break; | |
7352 | ||
7353 | case BFD_RELOC_ARM_THUMB_IMM: | |
7354 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
7355 | switch (newval >> 11) | |
7356 | { | |
7357 | case 0x04: /* 8bit immediate MOV. */ | |
7358 | case 0x05: /* 8bit immediate CMP. */ | |
7359 | if (value < 0 || value > 255) | |
7360 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7361 | _("Invalid immediate: %ld is too large"), | |
7362 | (long) value); | |
7363 | newval |= value; | |
7364 | break; | |
7365 | ||
7366 | default: | |
7367 | abort (); | |
7368 | } | |
7369 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7370 | break; | |
7371 | ||
7372 | case BFD_RELOC_ARM_THUMB_SHIFT: | |
7373 | /* 5bit shift value (0..31). */ | |
7374 | if (value < 0 || value > 31) | |
7375 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7376 | _("Illegal Thumb shift value: %ld"), (long) value); | |
7377 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f; | |
7378 | newval |= value << 6; | |
7379 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
7380 | break; | |
7381 | ||
7382 | case BFD_RELOC_VTABLE_INHERIT: | |
7383 | case BFD_RELOC_VTABLE_ENTRY: | |
7384 | fixP->fx_done = 0; | |
7385 | return 1; | |
7386 | ||
7387 | case BFD_RELOC_NONE: | |
7388 | default: | |
7389 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7390 | _("Bad relocation fixup type (%d)"), fixP->fx_r_type); | |
7391 | } | |
7392 | ||
7393 | return 1; | |
7394 | } | |
7395 | ||
7396 | /* Translate internal representation of relocation info to BFD target | |
7397 | format. */ | |
7398 | ||
7399 | arelent * | |
7400 | tc_gen_reloc (section, fixp) | |
7401 | asection * section ATTRIBUTE_UNUSED; | |
7402 | fixS * fixp; | |
7403 | { | |
7404 | arelent * reloc; | |
7405 | bfd_reloc_code_real_type code; | |
7406 | ||
7407 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
7408 | ||
7409 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
7410 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
7411 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
7412 | ||
7413 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
7414 | #ifndef OBJ_ELF | |
7415 | if (fixp->fx_pcrel == 0) | |
7416 | reloc->addend = fixp->fx_offset; | |
7417 | else | |
7418 | reloc->addend = fixp->fx_offset = reloc->address; | |
7419 | #else /* OBJ_ELF */ | |
7420 | reloc->addend = fixp->fx_offset; | |
7421 | #endif | |
7422 | ||
7423 | switch (fixp->fx_r_type) | |
7424 | { | |
7425 | case BFD_RELOC_8: | |
7426 | if (fixp->fx_pcrel) | |
7427 | { | |
7428 | code = BFD_RELOC_8_PCREL; | |
7429 | break; | |
7430 | } | |
7431 | ||
7432 | case BFD_RELOC_16: | |
7433 | if (fixp->fx_pcrel) | |
7434 | { | |
7435 | code = BFD_RELOC_16_PCREL; | |
7436 | break; | |
7437 | } | |
7438 | ||
7439 | case BFD_RELOC_32: | |
7440 | if (fixp->fx_pcrel) | |
7441 | { | |
7442 | code = BFD_RELOC_32_PCREL; | |
7443 | break; | |
7444 | } | |
7445 | ||
7446 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
7447 | case BFD_RELOC_ARM_PCREL_BLX: | |
7448 | case BFD_RELOC_RVA: | |
7449 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
7450 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
7451 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
7452 | case BFD_RELOC_THUMB_PCREL_BLX: | |
7453 | case BFD_RELOC_VTABLE_ENTRY: | |
7454 | case BFD_RELOC_VTABLE_INHERIT: | |
7455 | code = fixp->fx_r_type; | |
7456 | break; | |
7457 | ||
7458 | case BFD_RELOC_ARM_LITERAL: | |
7459 | case BFD_RELOC_ARM_HWLITERAL: | |
7460 | /* If this is called then the a literal has been referenced across | |
7461 | a section boundary - possibly due to an implicit dump. */ | |
7462 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7463 | _("Literal referenced across section boundary (Implicit dump?)")); | |
7464 | return NULL; | |
7465 | ||
7466 | #ifdef OBJ_ELF | |
7467 | case BFD_RELOC_ARM_GOT32: | |
7468 | case BFD_RELOC_ARM_GOTOFF: | |
7469 | case BFD_RELOC_ARM_PLT32: | |
7470 | code = fixp->fx_r_type; | |
7471 | break; | |
7472 | #endif | |
7473 | ||
7474 | case BFD_RELOC_ARM_IMMEDIATE: | |
7475 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7476 | _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"), | |
7477 | fixp->fx_r_type); | |
7478 | return NULL; | |
7479 | ||
7480 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: | |
7481 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7482 | _("ADRL used for a symbol not defined in the same file")); | |
7483 | return NULL; | |
7484 | ||
7485 | case BFD_RELOC_ARM_OFFSET_IMM: | |
7486 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7487 | _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"), | |
7488 | fixp->fx_r_type); | |
7489 | return NULL; | |
7490 | ||
7491 | default: | |
7492 | { | |
7493 | char * type; | |
7494 | ||
7495 | switch (fixp->fx_r_type) | |
7496 | { | |
7497 | case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break; | |
7498 | case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break; | |
7499 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
7500 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
7501 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; | |
7502 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
7503 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
7504 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; | |
7505 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
7506 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
7507 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
7508 | default: type = _("<unknown>"); break; | |
7509 | } | |
7510 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7511 | _("Cannot represent %s relocation in this object file format"), | |
7512 | type); | |
7513 | return NULL; | |
7514 | } | |
7515 | } | |
7516 | ||
7517 | #ifdef OBJ_ELF | |
7518 | if (code == BFD_RELOC_32_PCREL | |
7519 | && GOT_symbol | |
7520 | && fixp->fx_addsy == GOT_symbol) | |
7521 | { | |
7522 | code = BFD_RELOC_ARM_GOTPC; | |
7523 | reloc->addend = fixp->fx_offset = reloc->address; | |
7524 | } | |
7525 | #endif | |
7526 | ||
7527 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
7528 | ||
7529 | if (reloc->howto == NULL) | |
7530 | { | |
7531 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
7532 | _("Can not represent %s relocation in this object file format"), | |
7533 | bfd_get_reloc_code_name (code)); | |
7534 | return NULL; | |
7535 | } | |
7536 | ||
7537 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the | |
7538 | vtable entry to be used in the relocation's section offset. */ | |
7539 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
7540 | reloc->address = fixp->fx_offset; | |
7541 | ||
7542 | return reloc; | |
7543 | } | |
7544 | ||
7545 | int | |
7546 | md_estimate_size_before_relax (fragP, segtype) | |
7547 | fragS * fragP ATTRIBUTE_UNUSED; | |
7548 | segT segtype ATTRIBUTE_UNUSED; | |
7549 | { | |
7550 | as_fatal (_("md_estimate_size_before_relax\n")); | |
7551 | return 1; | |
7552 | } | |
7553 | ||
7554 | static void | |
7555 | output_inst PARAMS ((void)) | |
7556 | { | |
7557 | char * to = NULL; | |
7558 | ||
7559 | if (inst.error) | |
7560 | { | |
7561 | as_bad (inst.error); | |
7562 | return; | |
7563 | } | |
7564 | ||
7565 | to = frag_more (inst.size); | |
7566 | ||
7567 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
7568 | { | |
7569 | assert (inst.size == (2 * THUMB_SIZE)); | |
7570 | md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE); | |
7571 | md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE); | |
7572 | } | |
7573 | else if (inst.size > INSN_SIZE) | |
7574 | { | |
7575 | assert (inst.size == (2 * INSN_SIZE)); | |
7576 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
7577 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
7578 | } | |
7579 | else | |
7580 | md_number_to_chars (to, inst.instruction, inst.size); | |
7581 | ||
7582 | if (inst.reloc.type != BFD_RELOC_NONE) | |
7583 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
7584 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
7585 | inst.reloc.type); | |
7586 | ||
7587 | #ifdef OBJ_ELF | |
7588 | dwarf2_emit_insn (inst.size); | |
7589 | #endif | |
7590 | } | |
7591 | ||
7592 | void | |
7593 | md_assemble (str) | |
7594 | char * str; | |
7595 | { | |
7596 | char c; | |
7597 | char * p; | |
7598 | char * q; | |
7599 | char * start; | |
7600 | ||
7601 | /* Align the instruction. | |
7602 | This may not be the right thing to do but ... */ | |
7603 | #if 0 | |
7604 | arm_align (2, 0); | |
7605 | #endif | |
7606 | listing_prev_line (); /* Defined in listing.h. */ | |
7607 | ||
7608 | /* Align the previous label if needed. */ | |
7609 | if (last_label_seen != NULL) | |
7610 | { | |
7611 | symbol_set_frag (last_label_seen, frag_now); | |
7612 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
7613 | S_SET_SEGMENT (last_label_seen, now_seg); | |
7614 | } | |
7615 | ||
7616 | memset (&inst, '\0', sizeof (inst)); | |
7617 | inst.reloc.type = BFD_RELOC_NONE; | |
7618 | ||
7619 | skip_whitespace (str); | |
7620 | ||
7621 | /* Scan up to the end of the op-code, which must end in white space or | |
7622 | end of string. */ | |
7623 | for (start = p = str; *p != '\0'; p++) | |
7624 | if (*p == ' ') | |
7625 | break; | |
7626 | ||
7627 | if (p == str) | |
7628 | { | |
7629 | as_bad (_("No operator -- statement `%s'\n"), str); | |
7630 | return; | |
7631 | } | |
7632 | ||
7633 | if (thumb_mode) | |
7634 | { | |
7635 | CONST struct thumb_opcode * opcode; | |
7636 | ||
7637 | c = *p; | |
7638 | *p = '\0'; | |
7639 | opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str); | |
7640 | *p = c; | |
7641 | ||
7642 | if (opcode) | |
7643 | { | |
7644 | /* Check that this instruction is supported for this CPU. */ | |
7645 | if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0) | |
7646 | { | |
7647 | as_bad (_("selected processor does not support this opcode")); | |
7648 | return; | |
7649 | } | |
7650 | ||
7651 | inst.instruction = opcode->value; | |
7652 | inst.size = opcode->size; | |
7653 | (*opcode->parms) (p); | |
7654 | output_inst (); | |
7655 | return; | |
7656 | } | |
7657 | } | |
7658 | else | |
7659 | { | |
7660 | CONST struct asm_opcode * opcode; | |
7661 | unsigned long cond_code; | |
7662 | ||
7663 | inst.size = INSN_SIZE; | |
7664 | /* P now points to the end of the opcode, probably white space, but we | |
7665 | have to break the opcode up in case it contains condionals and flags; | |
7666 | keep trying with progressively smaller basic instructions until one | |
7667 | matches, or we run out of opcode. */ | |
7668 | q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p; | |
7669 | ||
7670 | for (; q != str; q--) | |
7671 | { | |
7672 | c = *q; | |
7673 | *q = '\0'; | |
7674 | ||
7675 | opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str); | |
7676 | *q = c; | |
7677 | ||
7678 | if (opcode && opcode->template) | |
7679 | { | |
7680 | unsigned long flag_bits = 0; | |
7681 | char * r; | |
7682 | ||
7683 | /* Check that this instruction is supported for this CPU. */ | |
7684 | if ((opcode->variants & cpu_variant) == 0) | |
7685 | goto try_shorter; | |
7686 | ||
7687 | inst.instruction = opcode->value; | |
7688 | if (q == p) /* Just a simple opcode. */ | |
7689 | { | |
7690 | if (opcode->comp_suffix) | |
7691 | { | |
7692 | if (*opcode->comp_suffix != '\0') | |
7693 | as_bad (_("Opcode `%s' must have suffix from list: <%s>"), | |
7694 | str, opcode->comp_suffix); | |
7695 | else | |
7696 | /* Not a conditional instruction. */ | |
7697 | (*opcode->parms) (q, 0); | |
7698 | } | |
7699 | else | |
7700 | { | |
7701 | /* A conditional instruction with default condition. */ | |
7702 | inst.instruction |= COND_ALWAYS; | |
7703 | (*opcode->parms) (q, 0); | |
7704 | } | |
7705 | output_inst (); | |
7706 | return; | |
7707 | } | |
7708 | ||
7709 | /* Not just a simple opcode. Check if extra is a | |
7710 | conditional. */ | |
7711 | r = q; | |
7712 | if (p - r >= 2) | |
7713 | { | |
7714 | CONST struct asm_cond *cond; | |
7715 | char d = *(r + 2); | |
7716 | ||
7717 | *(r + 2) = '\0'; | |
7718 | cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r); | |
7719 | *(r + 2) = d; | |
7720 | if (cond) | |
7721 | { | |
7722 | if (cond->value == 0xf0000000) | |
7723 | as_tsktsk ( | |
7724 | _("Warning: Use of the 'nv' conditional is deprecated\n")); | |
7725 | ||
7726 | cond_code = cond->value; | |
7727 | r += 2; | |
7728 | } | |
7729 | else | |
7730 | cond_code = COND_ALWAYS; | |
7731 | } | |
7732 | else | |
7733 | cond_code = COND_ALWAYS; | |
7734 | ||
7735 | /* Apply the conditional, or complain it's not allowed. */ | |
7736 | if (opcode->comp_suffix && *opcode->comp_suffix == '\0') | |
7737 | { | |
7738 | /* Instruction isn't conditional. */ | |
7739 | if (cond_code != COND_ALWAYS) | |
7740 | { | |
7741 | as_bad (_("Opcode `%s' is unconditional\n"), str); | |
7742 | return; | |
7743 | } | |
7744 | } | |
7745 | else | |
7746 | /* Instruction is conditional: set the condition into it. */ | |
7747 | inst.instruction |= cond_code; | |
7748 | ||
7749 | /* If there is a compulsory suffix, it should come here | |
7750 | before any optional flags. */ | |
7751 | if (opcode->comp_suffix && *opcode->comp_suffix != '\0') | |
7752 | { | |
7753 | CONST char *s = opcode->comp_suffix; | |
7754 | ||
7755 | while (*s) | |
7756 | { | |
7757 | inst.suffix++; | |
7758 | if (*r == *s) | |
7759 | break; | |
7760 | s++; | |
7761 | } | |
7762 | ||
7763 | if (*s == '\0') | |
7764 | { | |
7765 | as_bad (_("Opcode `%s' must have suffix from <%s>\n"), | |
7766 | str, opcode->comp_suffix); | |
7767 | return; | |
7768 | } | |
7769 | ||
7770 | r++; | |
7771 | } | |
7772 | ||
7773 | /* The remainder, if any should now be flags for the instruction; | |
7774 | Scan these checking each one found with the opcode. */ | |
7775 | if (r != p) | |
7776 | { | |
7777 | char d; | |
7778 | CONST struct asm_flg *flag = opcode->flags; | |
7779 | ||
7780 | if (flag) | |
7781 | { | |
7782 | int flagno; | |
7783 | ||
7784 | d = *p; | |
7785 | *p = '\0'; | |
7786 | ||
7787 | for (flagno = 0; flag[flagno].template; flagno++) | |
7788 | { | |
7789 | if (streq (r, flag[flagno].template)) | |
7790 | { | |
7791 | flag_bits |= flag[flagno].set_bits; | |
7792 | break; | |
7793 | } | |
7794 | } | |
7795 | ||
7796 | *p = d; | |
7797 | if (! flag[flagno].template) | |
7798 | goto try_shorter; | |
7799 | } | |
7800 | else | |
7801 | goto try_shorter; | |
7802 | } | |
7803 | ||
7804 | (*opcode->parms) (p, flag_bits); | |
7805 | output_inst (); | |
7806 | return; | |
7807 | } | |
7808 | ||
7809 | try_shorter: | |
7810 | ; | |
7811 | } | |
7812 | } | |
7813 | ||
7814 | /* It wasn't an instruction, but it might be a register alias of the form | |
7815 | alias .req reg. */ | |
7816 | q = p; | |
7817 | skip_whitespace (q); | |
7818 | ||
7819 | c = *p; | |
7820 | *p = '\0'; | |
7821 | ||
7822 | if (*q && !strncmp (q, ".req ", 4)) | |
7823 | { | |
7824 | int reg; | |
7825 | char * copy_of_str; | |
7826 | char * r; | |
7827 | ||
7828 | #ifdef IGNORE_OPCODE_CASE | |
7829 | str = original_case_string; | |
7830 | #endif | |
7831 | copy_of_str = str; | |
7832 | ||
7833 | q += 4; | |
7834 | skip_whitespace (q); | |
7835 | ||
7836 | for (r = q; *r != '\0'; r++) | |
7837 | if (*r == ' ') | |
7838 | break; | |
7839 | ||
7840 | if (r != q) | |
7841 | { | |
7842 | int regnum; | |
7843 | char d = *r; | |
7844 | ||
7845 | *r = '\0'; | |
7846 | regnum = arm_reg_parse (& q); | |
7847 | *r = d; | |
7848 | ||
7849 | reg = arm_reg_parse (& str); | |
7850 | ||
7851 | if (reg == FAIL) | |
7852 | { | |
7853 | if (regnum != FAIL) | |
7854 | insert_reg_alias (str, regnum); | |
7855 | else | |
7856 | as_warn (_("register '%s' does not exist\n"), q); | |
7857 | } | |
7858 | else if (regnum != FAIL) | |
7859 | { | |
7860 | if (reg != regnum) | |
7861 | as_warn (_("ignoring redefinition of register alias '%s'"), | |
7862 | copy_of_str); | |
7863 | ||
7864 | /* Do not warn about redefinitions to the same alias. */ | |
7865 | } | |
7866 | else | |
7867 | as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"), | |
7868 | copy_of_str, q); | |
7869 | } | |
7870 | else | |
7871 | as_warn (_("ignoring incomplete .req pseuso op")); | |
7872 | ||
7873 | *p = c; | |
7874 | return; | |
7875 | } | |
7876 | ||
7877 | *p = c; | |
7878 | as_bad (_("bad instruction `%s'"), start); | |
7879 | } | |
7880 | ||
7881 | /* md_parse_option | |
7882 | Invocation line includes a switch not recognized by the base assembler. | |
7883 | See if it's a processor-specific option. These are: | |
7884 | Cpu variants, the arm part is optional: | |
7885 | -m[arm]1 Currently not supported. | |
7886 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
7887 | -m[arm]3 Arm 3 processor | |
7888 | -m[arm]6[xx], Arm 6 processors | |
7889 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
7890 | -m[arm]8[10] Arm 8 processors | |
7891 | -m[arm]9[20][tdmi] Arm 9 processors | |
7892 | -mstrongarm[110[0]] StrongARM processors | |
7893 | -mxscale XScale processors | |
7894 | -m[arm]v[2345[t[e]]] Arm architectures | |
7895 | -mall All (except the ARM1) | |
7896 | FP variants: | |
7897 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
7898 | -mfpe-old (No float load/store multiples) | |
7899 | -mno-fpu Disable all floating point instructions | |
7900 | Run-time endian selection: | |
7901 | -EB big endian cpu | |
7902 | -EL little endian cpu | |
7903 | ARM Procedure Calling Standard: | |
7904 | -mapcs-32 32 bit APCS | |
7905 | -mapcs-26 26 bit APCS | |
7906 | -mapcs-float Pass floats in float regs | |
7907 | -mapcs-reentrant Position independent code | |
7908 | -mthumb-interwork Code supports Arm/Thumb interworking | |
7909 | -matpcs ARM/Thumb Procedure Call Standard | |
7910 | -moabi Old ELF ABI */ | |
7911 | ||
7912 | CONST char * md_shortopts = "m:k"; | |
7913 | ||
7914 | struct option md_longopts[] = | |
7915 | { | |
7916 | #ifdef ARM_BI_ENDIAN | |
7917 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
7918 | {"EB", no_argument, NULL, OPTION_EB}, | |
7919 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
7920 | {"EL", no_argument, NULL, OPTION_EL}, | |
7921 | #ifdef OBJ_ELF | |
7922 | #define OPTION_OABI (OPTION_MD_BASE +2) | |
7923 | {"oabi", no_argument, NULL, OPTION_OABI}, | |
7924 | #endif | |
7925 | #endif | |
7926 | {NULL, no_argument, NULL, 0} | |
7927 | }; | |
7928 | ||
7929 | size_t md_longopts_size = sizeof (md_longopts); | |
7930 | ||
7931 | int | |
7932 | md_parse_option (c, arg) | |
7933 | int c; | |
7934 | char * arg; | |
7935 | { | |
7936 | char * str = arg; | |
7937 | ||
7938 | switch (c) | |
7939 | { | |
7940 | #ifdef ARM_BI_ENDIAN | |
7941 | case OPTION_EB: | |
7942 | target_big_endian = 1; | |
7943 | break; | |
7944 | case OPTION_EL: | |
7945 | target_big_endian = 0; | |
7946 | break; | |
7947 | #endif | |
7948 | ||
7949 | case 'm': | |
7950 | switch (*str) | |
7951 | { | |
7952 | case 'f': | |
7953 | if (streq (str, "fpa10")) | |
7954 | cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10; | |
7955 | else if (streq (str, "fpa11")) | |
7956 | cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11; | |
7957 | else if (streq (str, "fpe-old")) | |
7958 | cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE; | |
7959 | else | |
7960 | goto bad; | |
7961 | break; | |
7962 | ||
7963 | case 'n': | |
7964 | if (streq (str, "no-fpu")) | |
7965 | cpu_variant &= ~FPU_ALL; | |
7966 | break; | |
7967 | ||
7968 | #ifdef OBJ_ELF | |
7969 | case 'o': | |
7970 | if (streq (str, "oabi")) | |
7971 | target_oabi = true; | |
7972 | break; | |
7973 | #endif | |
7974 | ||
7975 | case 't': | |
7976 | /* Limit assembler to generating only Thumb instructions: */ | |
7977 | if (streq (str, "thumb")) | |
7978 | { | |
7979 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_THUMB; | |
7980 | cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE; | |
7981 | thumb_mode = 1; | |
7982 | } | |
7983 | else if (streq (str, "thumb-interwork")) | |
7984 | { | |
7985 | if ((cpu_variant & ARM_EXT_THUMB) == 0) | |
7986 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T; | |
7987 | #if defined OBJ_COFF || defined OBJ_ELF | |
7988 | support_interwork = true; | |
7989 | #endif | |
7990 | } | |
7991 | else | |
7992 | goto bad; | |
7993 | break; | |
7994 | ||
7995 | default: | |
7996 | if (streq (str, "all")) | |
7997 | { | |
7998 | cpu_variant = ARM_ALL | FPU_ALL; | |
7999 | return 1; | |
8000 | } | |
8001 | #if defined OBJ_COFF || defined OBJ_ELF | |
8002 | if (! strncmp (str, "apcs-", 5)) | |
8003 | { | |
8004 | /* GCC passes on all command line options starting "-mapcs-..." | |
8005 | to us, so we must parse them here. */ | |
8006 | ||
8007 | str += 5; | |
8008 | ||
8009 | if (streq (str, "32")) | |
8010 | { | |
8011 | uses_apcs_26 = false; | |
8012 | return 1; | |
8013 | } | |
8014 | else if (streq (str, "26")) | |
8015 | { | |
8016 | uses_apcs_26 = true; | |
8017 | return 1; | |
8018 | } | |
8019 | else if (streq (str, "frame")) | |
8020 | { | |
8021 | /* Stack frames are being generated - does not affect | |
8022 | linkage of code. */ | |
8023 | return 1; | |
8024 | } | |
8025 | else if (streq (str, "stack-check")) | |
8026 | { | |
8027 | /* Stack checking is being performed - does not affect | |
8028 | linkage, but does require that the functions | |
8029 | __rt_stkovf_split_small and __rt_stkovf_split_big be | |
8030 | present in the final link. */ | |
8031 | ||
8032 | return 1; | |
8033 | } | |
8034 | else if (streq (str, "float")) | |
8035 | { | |
8036 | /* Floating point arguments are being passed in the floating | |
8037 | point registers. This does affect linking, since this | |
8038 | version of the APCS is incompatible with the version that | |
8039 | passes floating points in the integer registers. */ | |
8040 | ||
8041 | uses_apcs_float = true; | |
8042 | return 1; | |
8043 | } | |
8044 | else if (streq (str, "reentrant")) | |
8045 | { | |
8046 | /* Reentrant code has been generated. This does affect | |
8047 | linking, since there is no point in linking reentrant/ | |
8048 | position independent code with absolute position code. */ | |
8049 | pic_code = true; | |
8050 | return 1; | |
8051 | } | |
8052 | ||
8053 | as_bad (_("Unrecognised APCS switch -m%s"), arg); | |
8054 | return 0; | |
8055 | } | |
8056 | ||
8057 | if (! strcmp (str, "atpcs")) | |
8058 | { | |
8059 | atpcs = true; | |
8060 | return 1; | |
8061 | } | |
8062 | #endif | |
8063 | /* Strip off optional "arm". */ | |
8064 | if (! strncmp (str, "arm", 3)) | |
8065 | str += 3; | |
8066 | ||
8067 | switch (*str) | |
8068 | { | |
8069 | case '1': | |
8070 | if (streq (str, "1")) | |
8071 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1; | |
8072 | else | |
8073 | goto bad; | |
8074 | break; | |
8075 | ||
8076 | case '2': | |
8077 | if (streq (str, "2")) | |
8078 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; | |
8079 | else if (streq (str, "250")) | |
8080 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250; | |
8081 | else | |
8082 | goto bad; | |
8083 | break; | |
8084 | ||
8085 | case '3': | |
8086 | if (streq (str, "3")) | |
8087 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; | |
8088 | else | |
8089 | goto bad; | |
8090 | break; | |
8091 | ||
8092 | case '6': | |
8093 | switch (strtol (str, NULL, 10)) | |
8094 | { | |
8095 | case 6: | |
8096 | case 60: | |
8097 | case 600: | |
8098 | case 610: | |
8099 | case 620: | |
8100 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6; | |
8101 | break; | |
8102 | default: | |
8103 | goto bad; | |
8104 | } | |
8105 | break; | |
8106 | ||
8107 | case '7': | |
8108 | /* Eat the processor name. */ | |
8109 | switch (strtol (str, & str, 10)) | |
8110 | { | |
8111 | case 7: | |
8112 | case 70: | |
8113 | case 700: | |
8114 | case 710: | |
8115 | case 720: | |
8116 | case 7100: | |
8117 | case 7500: | |
8118 | break; | |
8119 | default: | |
8120 | goto bad; | |
8121 | } | |
8122 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7; | |
8123 | for (; *str; str++) | |
8124 | { | |
8125 | switch (*str) | |
8126 | { | |
8127 | case 't': | |
8128 | cpu_variant |= ARM_ARCH_V4T; | |
8129 | break; | |
8130 | ||
8131 | case 'm': | |
8132 | cpu_variant |= ARM_EXT_LONGMUL; | |
8133 | break; | |
8134 | ||
8135 | case 'f': /* fe => fp enabled cpu. */ | |
8136 | if (str[1] == 'e') | |
8137 | ++ str; | |
8138 | else | |
8139 | goto bad; | |
8140 | ||
8141 | case 'c': /* Left over from 710c processor name. */ | |
8142 | case 'd': /* Debug. */ | |
8143 | case 'i': /* Embedded ICE. */ | |
8144 | /* Included for completeness in ARM processor naming. */ | |
8145 | break; | |
8146 | ||
8147 | default: | |
8148 | goto bad; | |
8149 | } | |
8150 | } | |
8151 | break; | |
8152 | ||
8153 | case '8': | |
8154 | if (streq (str, "8") || streq (str, "810")) | |
8155 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8156 | | ARM_8 | ARM_ARCH_V4; | |
8157 | else | |
8158 | goto bad; | |
8159 | break; | |
8160 | ||
8161 | case '9': | |
8162 | if (streq (str, "9")) | |
8163 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8164 | | ARM_9 | ARM_ARCH_V4T; | |
8165 | else if (streq (str, "920")) | |
8166 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8167 | | ARM_9 | ARM_ARCH_V4; | |
8168 | else if (streq (str, "920t")) | |
8169 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8170 | | ARM_9 | ARM_ARCH_V4T; | |
8171 | else if (streq (str, "9tdmi")) | |
8172 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8173 | | ARM_9 | ARM_ARCH_V4T; | |
8174 | else | |
8175 | goto bad; | |
8176 | break; | |
8177 | ||
8178 | case 's': | |
8179 | if (streq (str, "strongarm") | |
8180 | || streq (str, "strongarm110") | |
8181 | || streq (str, "strongarm1100")) | |
8182 | cpu_variant = (cpu_variant & ~ARM_ANY) | |
8183 | | ARM_8 | ARM_ARCH_V4; | |
8184 | else | |
8185 | goto bad; | |
8186 | break; | |
8187 | ||
8188 | case 'x': | |
8189 | if (streq (str, "xscale")) | |
8190 | cpu_variant = ARM_9 | ARM_ARCH_XSCALE; | |
8191 | else | |
8192 | goto bad; | |
8193 | break; | |
8194 | ||
8195 | case 'v': | |
8196 | /* Select variant based on architecture rather than | |
8197 | processor. */ | |
8198 | switch (*++str) | |
8199 | { | |
8200 | case '2': | |
8201 | switch (*++str) | |
8202 | { | |
8203 | case 'a': | |
8204 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; | |
8205 | break; | |
8206 | case 0: | |
8207 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; | |
8208 | break; | |
8209 | default: | |
8210 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
8211 | break; | |
8212 | } | |
8213 | break; | |
8214 | ||
8215 | case '3': | |
8216 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7; | |
8217 | ||
8218 | switch (*++str) | |
8219 | { | |
8220 | case 'm': cpu_variant |= ARM_EXT_LONGMUL; break; | |
8221 | case 0: break; | |
8222 | default: | |
8223 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
8224 | break; | |
8225 | } | |
8226 | break; | |
8227 | ||
8228 | case '4': | |
8229 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4; | |
8230 | ||
8231 | switch (*++str) | |
8232 | { | |
8233 | case 't': cpu_variant |= ARM_EXT_THUMB; break; | |
8234 | case 0: break; | |
8235 | default: | |
8236 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
8237 | break; | |
8238 | } | |
8239 | break; | |
8240 | ||
8241 | case '5': | |
8242 | cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5; | |
8243 | switch (*++str) | |
8244 | { | |
8245 | case 't': cpu_variant |= ARM_EXT_THUMB; break; | |
8246 | case 'e': cpu_variant |= ARM_EXT_V5E; break; | |
8247 | case 0: break; | |
8248 | default: | |
8249 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
8250 | break; | |
8251 | } | |
8252 | break; | |
8253 | ||
8254 | default: | |
8255 | as_bad (_("Invalid architecture variant -m%s"), arg); | |
8256 | break; | |
8257 | } | |
8258 | break; | |
8259 | ||
8260 | default: | |
8261 | bad: | |
8262 | as_bad (_("Invalid processor variant -m%s"), arg); | |
8263 | return 0; | |
8264 | } | |
8265 | } | |
8266 | break; | |
8267 | ||
8268 | #if defined OBJ_ELF || defined OBJ_COFF | |
8269 | case 'k': | |
8270 | pic_code = 1; | |
8271 | break; | |
8272 | #endif | |
8273 | ||
8274 | default: | |
8275 | return 0; | |
8276 | } | |
8277 | ||
8278 | return 1; | |
8279 | } | |
8280 | ||
8281 | void | |
8282 | md_show_usage (fp) | |
8283 | FILE * fp; | |
8284 | { | |
8285 | fprintf (fp, _("\ | |
8286 | ARM Specific Assembler Options:\n\ | |
8287 | -m[arm][<processor name>] select processor variant\n\ | |
8288 | -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\ | |
8289 | -mthumb only allow Thumb instructions\n\ | |
8290 | -mthumb-interwork mark the assembled code as supporting interworking\n\ | |
8291 | -mall allow any instruction\n\ | |
8292 | -mfpa10, -mfpa11 select floating point architecture\n\ | |
8293 | -mfpe-old don't allow floating-point multiple instructions\n\ | |
8294 | -mno-fpu don't allow any floating-point instructions.\n\ | |
8295 | -k generate PIC code.\n")); | |
8296 | #if defined OBJ_COFF || defined OBJ_ELF | |
8297 | fprintf (fp, _("\ | |
8298 | -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\ | |
8299 | -matpcs use ARM/Thumb Procedure Calling Standard\n\ | |
8300 | -mapcs-float floating point args are passed in FP regs\n\ | |
8301 | -mapcs-reentrant the code is position independent/reentrant\n")); | |
8302 | #endif | |
8303 | #ifdef OBJ_ELF | |
8304 | fprintf (fp, _("\ | |
8305 | -moabi support the old ELF ABI\n")); | |
8306 | #endif | |
8307 | #ifdef ARM_BI_ENDIAN | |
8308 | fprintf (fp, _("\ | |
8309 | -EB assemble code for a big endian cpu\n\ | |
8310 | -EL assemble code for a little endian cpu\n")); | |
8311 | #endif | |
8312 | } | |
8313 | ||
8314 | /* We need to be able to fix up arbitrary expressions in some statements. | |
8315 | This is so that we can handle symbols that are an arbitrary distance from | |
8316 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
8317 | which returns part of an address in a form which will be valid for | |
8318 | a data instruction. We do this by pushing the expression into a symbol | |
8319 | in the expr_section, and creating a fix for that. */ | |
8320 | ||
8321 | static void | |
8322 | fix_new_arm (frag, where, size, exp, pc_rel, reloc) | |
8323 | fragS * frag; | |
8324 | int where; | |
8325 | short int size; | |
8326 | expressionS * exp; | |
8327 | int pc_rel; | |
8328 | int reloc; | |
8329 | { | |
8330 | fixS * new_fix; | |
8331 | arm_fix_data * arm_data; | |
8332 | ||
8333 | switch (exp->X_op) | |
8334 | { | |
8335 | case O_constant: | |
8336 | case O_symbol: | |
8337 | case O_add: | |
8338 | case O_subtract: | |
8339 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
8340 | break; | |
8341 | ||
8342 | default: | |
8343 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
8344 | pc_rel, reloc); | |
8345 | break; | |
8346 | } | |
8347 | ||
8348 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
8349 | instruction. */ | |
8350 | arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data)); | |
8351 | new_fix->tc_fix_data = (PTR) arm_data; | |
8352 | arm_data->thumb_mode = thumb_mode; | |
8353 | ||
8354 | return; | |
8355 | } | |
8356 | ||
8357 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ | |
8358 | ||
8359 | void | |
8360 | cons_fix_new_arm (frag, where, size, exp) | |
8361 | fragS * frag; | |
8362 | int where; | |
8363 | int size; | |
8364 | expressionS * exp; | |
8365 | { | |
8366 | bfd_reloc_code_real_type type; | |
8367 | int pcrel = 0; | |
8368 | ||
8369 | /* Pick a reloc. | |
8370 | FIXME: @@ Should look at CPU word size. */ | |
8371 | switch (size) | |
8372 | { | |
8373 | case 1: | |
8374 | type = BFD_RELOC_8; | |
8375 | break; | |
8376 | case 2: | |
8377 | type = BFD_RELOC_16; | |
8378 | break; | |
8379 | case 4: | |
8380 | default: | |
8381 | type = BFD_RELOC_32; | |
8382 | break; | |
8383 | case 8: | |
8384 | type = BFD_RELOC_64; | |
8385 | break; | |
8386 | } | |
8387 | ||
8388 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); | |
8389 | } | |
8390 | ||
8391 | /* A good place to do this, although this was probably not intended | |
8392 | for this kind of use. We need to dump the literal pool before | |
8393 | references are made to a null symbol pointer. */ | |
8394 | ||
8395 | void | |
8396 | arm_cleanup () | |
8397 | { | |
8398 | if (current_poolP == NULL) | |
8399 | return; | |
8400 | ||
8401 | /* Put it at the end of text section. */ | |
8402 | subseg_set (text_section, 0); | |
8403 | s_ltorg (0); | |
8404 | listing_prev_line (); | |
8405 | } | |
8406 | ||
8407 | void | |
8408 | arm_start_line_hook () | |
8409 | { | |
8410 | last_label_seen = NULL; | |
8411 | } | |
8412 | ||
8413 | void | |
8414 | arm_frob_label (sym) | |
8415 | symbolS * sym; | |
8416 | { | |
8417 | last_label_seen = sym; | |
8418 | ||
8419 | ARM_SET_THUMB (sym, thumb_mode); | |
8420 | ||
8421 | #if defined OBJ_COFF || defined OBJ_ELF | |
8422 | ARM_SET_INTERWORK (sym, support_interwork); | |
8423 | #endif | |
8424 | ||
8425 | /* Note - do not allow local symbols (.Lxxx) to be labeled | |
8426 | as Thumb functions. This is because these labels, whilst | |
8427 | they exist inside Thumb code, are not the entry points for | |
8428 | possible ARM->Thumb calls. Also, these labels can be used | |
8429 | as part of a computed goto or switch statement. eg gcc | |
8430 | can generate code that looks like this: | |
8431 | ||
8432 | ldr r2, [pc, .Laaa] | |
8433 | lsl r3, r3, #2 | |
8434 | ldr r2, [r3, r2] | |
8435 | mov pc, r2 | |
8436 | ||
8437 | .Lbbb: .word .Lxxx | |
8438 | .Lccc: .word .Lyyy | |
8439 | ..etc... | |
8440 | .Laaa: .word Lbbb | |
8441 | ||
8442 | The first instruction loads the address of the jump table. | |
8443 | The second instruction converts a table index into a byte offset. | |
8444 | The third instruction gets the jump address out of the table. | |
8445 | The fourth instruction performs the jump. | |
8446 | ||
8447 | If the address stored at .Laaa is that of a symbol which has the | |
8448 | Thumb_Func bit set, then the linker will arrange for this address | |
8449 | to have the bottom bit set, which in turn would mean that the | |
8450 | address computation performed by the third instruction would end | |
8451 | up with the bottom bit set. Since the ARM is capable of unaligned | |
8452 | word loads, the instruction would then load the incorrect address | |
8453 | out of the jump table, and chaos would ensue. */ | |
8454 | if (label_is_thumb_function_name | |
8455 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
8456 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
8457 | { | |
8458 | /* When the address of a Thumb function is taken the bottom | |
8459 | bit of that address should be set. This will allow | |
8460 | interworking between Arm and Thumb functions to work | |
8461 | correctly. */ | |
8462 | ||
8463 | THUMB_SET_FUNC (sym, 1); | |
8464 | ||
8465 | label_is_thumb_function_name = false; | |
8466 | } | |
8467 | } | |
8468 | ||
8469 | /* Adjust the symbol table. This marks Thumb symbols as distinct from | |
8470 | ARM ones. */ | |
8471 | ||
8472 | void | |
8473 | arm_adjust_symtab () | |
8474 | { | |
8475 | #ifdef OBJ_COFF | |
8476 | symbolS * sym; | |
8477 | ||
8478 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
8479 | { | |
8480 | if (ARM_IS_THUMB (sym)) | |
8481 | { | |
8482 | if (THUMB_IS_FUNC (sym)) | |
8483 | { | |
8484 | /* Mark the symbol as a Thumb function. */ | |
8485 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
8486 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
8487 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
8488 | ||
8489 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) | |
8490 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
8491 | else | |
8492 | as_bad (_("%s: unexpected function type: %d"), | |
8493 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
8494 | } | |
8495 | else switch (S_GET_STORAGE_CLASS (sym)) | |
8496 | { | |
8497 | case C_EXT: | |
8498 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
8499 | break; | |
8500 | case C_STAT: | |
8501 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
8502 | break; | |
8503 | case C_LABEL: | |
8504 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
8505 | break; | |
8506 | default: | |
8507 | /* Do nothing. */ | |
8508 | break; | |
8509 | } | |
8510 | } | |
8511 | ||
8512 | if (ARM_IS_INTERWORK (sym)) | |
8513 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
8514 | } | |
8515 | #endif | |
8516 | #ifdef OBJ_ELF | |
8517 | symbolS * sym; | |
8518 | char bind; | |
8519 | ||
8520 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
8521 | { | |
8522 | if (ARM_IS_THUMB (sym)) | |
8523 | { | |
8524 | elf_symbol_type * elf_sym; | |
8525 | ||
8526 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); | |
8527 | bind = ELF_ST_BIND (elf_sym); | |
8528 | ||
8529 | /* If it's a .thumb_func, declare it as so, | |
8530 | otherwise tag label as .code 16. */ | |
8531 | if (THUMB_IS_FUNC (sym)) | |
8532 | elf_sym->internal_elf_sym.st_info = | |
8533 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
8534 | else | |
8535 | elf_sym->internal_elf_sym.st_info = | |
8536 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
8537 | } | |
8538 | } | |
8539 | #endif | |
8540 | } | |
8541 | ||
8542 | int | |
8543 | arm_data_in_code () | |
8544 | { | |
8545 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) | |
8546 | { | |
8547 | *input_line_pointer = '/'; | |
8548 | input_line_pointer += 5; | |
8549 | *input_line_pointer = 0; | |
8550 | return 1; | |
8551 | } | |
8552 | ||
8553 | return 0; | |
8554 | } | |
8555 | ||
8556 | char * | |
8557 | arm_canonicalize_symbol_name (name) | |
8558 | char * name; | |
8559 | { | |
8560 | int len; | |
8561 | ||
8562 | if (thumb_mode && (len = strlen (name)) > 5 | |
8563 | && streq (name + len - 5, "/data")) | |
8564 | *(name + len - 5) = 0; | |
8565 | ||
8566 | return name; | |
8567 | } | |
8568 | ||
8569 | boolean | |
8570 | arm_validate_fix (fixP) | |
8571 | fixS * fixP; | |
8572 | { | |
8573 | /* If the destination of the branch is a defined symbol which does not have | |
8574 | the THUMB_FUNC attribute, then we must be calling a function which has | |
8575 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
8576 | function and change the branch to refer to that function instead. */ | |
8577 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
8578 | && fixP->fx_addsy != NULL | |
8579 | && S_IS_DEFINED (fixP->fx_addsy) | |
8580 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
8581 | { | |
8582 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); | |
8583 | return true; | |
8584 | } | |
8585 | ||
8586 | return false; | |
8587 | } | |
8588 | ||
8589 | #ifdef OBJ_COFF | |
8590 | /* This is a little hack to help the gas/arm/adrl.s test. It prevents | |
8591 | local labels from being added to the output symbol table when they | |
8592 | are used with the ADRL pseudo op. The ADRL relocation should always | |
8593 | be resolved before the binbary is emitted, so it is safe to say that | |
8594 | it is adjustable. */ | |
8595 | ||
8596 | boolean | |
8597 | arm_fix_adjustable (fixP) | |
8598 | fixS * fixP; | |
8599 | { | |
8600 | if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) | |
8601 | return 1; | |
8602 | return 0; | |
8603 | } | |
8604 | #endif | |
8605 | #ifdef OBJ_ELF | |
8606 | /* Relocations against Thumb function names must be left unadjusted, | |
8607 | so that the linker can use this information to correctly set the | |
8608 | bottom bit of their addresses. The MIPS version of this function | |
8609 | also prevents relocations that are mips-16 specific, but I do not | |
8610 | know why it does this. | |
8611 | ||
8612 | FIXME: | |
8613 | There is one other problem that ought to be addressed here, but | |
8614 | which currently is not: Taking the address of a label (rather | |
8615 | than a function) and then later jumping to that address. Such | |
8616 | addresses also ought to have their bottom bit set (assuming that | |
8617 | they reside in Thumb code), but at the moment they will not. */ | |
8618 | ||
8619 | boolean | |
8620 | arm_fix_adjustable (fixP) | |
8621 | fixS * fixP; | |
8622 | { | |
8623 | if (fixP->fx_addsy == NULL) | |
8624 | return 1; | |
8625 | ||
8626 | /* Prevent all adjustments to global symbols. */ | |
8627 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
8628 | return 0; | |
8629 | ||
8630 | if (S_IS_WEAK (fixP->fx_addsy)) | |
8631 | return 0; | |
8632 | ||
8633 | if (THUMB_IS_FUNC (fixP->fx_addsy) | |
8634 | && fixP->fx_subsy == NULL) | |
8635 | return 0; | |
8636 | ||
8637 | /* We need the symbol name for the VTABLE entries. */ | |
8638 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
8639 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
8640 | return 0; | |
8641 | ||
8642 | return 1; | |
8643 | } | |
8644 | ||
8645 | const char * | |
8646 | elf32_arm_target_format () | |
8647 | { | |
8648 | if (target_big_endian) | |
8649 | { | |
8650 | if (target_oabi) | |
8651 | return "elf32-bigarm-oabi"; | |
8652 | else | |
8653 | return "elf32-bigarm"; | |
8654 | } | |
8655 | else | |
8656 | { | |
8657 | if (target_oabi) | |
8658 | return "elf32-littlearm-oabi"; | |
8659 | else | |
8660 | return "elf32-littlearm"; | |
8661 | } | |
8662 | } | |
8663 | ||
8664 | void | |
8665 | armelf_frob_symbol (symp, puntp) | |
8666 | symbolS * symp; | |
8667 | int * puntp; | |
8668 | { | |
8669 | elf_frob_symbol (symp, puntp); | |
8670 | } | |
8671 | ||
8672 | int | |
8673 | arm_force_relocation (fixp) | |
8674 | struct fix * fixp; | |
8675 | { | |
8676 | if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
8677 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
8678 | || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH | |
8679 | || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX | |
8680 | || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX | |
8681 | || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23) | |
8682 | return 1; | |
8683 | ||
8684 | return 0; | |
8685 | } | |
8686 | ||
8687 | static bfd_reloc_code_real_type | |
8688 | arm_parse_reloc () | |
8689 | { | |
8690 | char id [16]; | |
8691 | char * ip; | |
8692 | unsigned int i; | |
8693 | static struct | |
8694 | { | |
8695 | char * str; | |
8696 | int len; | |
8697 | bfd_reloc_code_real_type reloc; | |
8698 | } | |
8699 | reloc_map[] = | |
8700 | { | |
8701 | #define MAP(str,reloc) { str, sizeof (str) - 1, reloc } | |
8702 | MAP ("(got)", BFD_RELOC_ARM_GOT32), | |
8703 | MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF), | |
8704 | /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)" | |
8705 | branch instructions generated by GCC for PLT relocs. */ | |
8706 | MAP ("(plt)", BFD_RELOC_ARM_PLT32), | |
8707 | { NULL, 0, BFD_RELOC_UNUSED } | |
8708 | #undef MAP | |
8709 | }; | |
8710 | ||
8711 | for (i = 0, ip = input_line_pointer; | |
8712 | i < sizeof (id) && (isalnum (*ip) || ispunct (*ip)); | |
8713 | i++, ip++) | |
8714 | id[i] = tolower (*ip); | |
8715 | ||
8716 | for (i = 0; reloc_map[i].str; i++) | |
8717 | if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0) | |
8718 | break; | |
8719 | ||
8720 | input_line_pointer += reloc_map[i].len; | |
8721 | ||
8722 | return reloc_map[i].reloc; | |
8723 | } | |
8724 | ||
8725 | static void | |
8726 | s_arm_elf_cons (nbytes) | |
8727 | int nbytes; | |
8728 | { | |
8729 | expressionS exp; | |
8730 | ||
8731 | #ifdef md_flush_pending_output | |
8732 | md_flush_pending_output (); | |
8733 | #endif | |
8734 | ||
8735 | if (is_it_end_of_statement ()) | |
8736 | { | |
8737 | demand_empty_rest_of_line (); | |
8738 | return; | |
8739 | } | |
8740 | ||
8741 | #ifdef md_cons_align | |
8742 | md_cons_align (nbytes); | |
8743 | #endif | |
8744 | ||
8745 | do | |
8746 | { | |
8747 | bfd_reloc_code_real_type reloc; | |
8748 | ||
8749 | expression (& exp); | |
8750 | ||
8751 | if (exp.X_op == O_symbol | |
8752 | && * input_line_pointer == '(' | |
8753 | && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED) | |
8754 | { | |
8755 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
8756 | int size = bfd_get_reloc_size (howto); | |
8757 | ||
8758 | if (size > nbytes) | |
8759 | as_bad ("%s relocations do not fit in %d bytes", | |
8760 | howto->name, nbytes); | |
8761 | else | |
8762 | { | |
8763 | register char *p = frag_more ((int) nbytes); | |
8764 | int offset = nbytes - size; | |
8765 | ||
8766 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, | |
8767 | &exp, 0, reloc); | |
8768 | } | |
8769 | } | |
8770 | else | |
8771 | emit_expr (&exp, (unsigned int) nbytes); | |
8772 | } | |
8773 | while (*input_line_pointer++ == ','); | |
8774 | ||
8775 | /* Put terminator back into stream. */ | |
8776 | input_line_pointer --; | |
8777 | demand_empty_rest_of_line (); | |
8778 | } | |
8779 | ||
8780 | #endif /* OBJ_ELF */ | |
8781 | ||
8782 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents | |
8783 | of an rs_align_code fragment. */ | |
8784 | ||
8785 | void | |
8786 | arm_handle_align (fragP) | |
8787 | fragS *fragP; | |
8788 | { | |
8789 | static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; | |
8790 | static char const thumb_noop[2] = { 0xc0, 0x46 }; | |
8791 | static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; | |
8792 | static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; | |
8793 | ||
8794 | int bytes, fix, noop_size; | |
8795 | char * p; | |
8796 | const char * noop; | |
8797 | ||
8798 | if (fragP->fr_type != rs_align_code) | |
8799 | return; | |
8800 | ||
8801 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
8802 | p = fragP->fr_literal + fragP->fr_fix; | |
8803 | fix = 0; | |
8804 | ||
8805 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) | |
8806 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
8807 | ||
8808 | if (fragP->tc_frag_data) | |
8809 | { | |
8810 | if (target_big_endian) | |
8811 | noop = thumb_bigend_noop; | |
8812 | else | |
8813 | noop = thumb_noop; | |
8814 | noop_size = sizeof (thumb_noop); | |
8815 | } | |
8816 | else | |
8817 | { | |
8818 | if (target_big_endian) | |
8819 | noop = arm_bigend_noop; | |
8820 | else | |
8821 | noop = arm_noop; | |
8822 | noop_size = sizeof (arm_noop); | |
8823 | } | |
8824 | ||
8825 | if (bytes & (noop_size - 1)) | |
8826 | { | |
8827 | fix = bytes & (noop_size - 1); | |
8828 | memset (p, 0, fix); | |
8829 | p += fix; | |
8830 | bytes -= fix; | |
8831 | } | |
8832 | ||
8833 | while (bytes >= noop_size) | |
8834 | { | |
8835 | memcpy (p, noop, noop_size); | |
8836 | p += noop_size; | |
8837 | bytes -= noop_size; | |
8838 | fix += noop_size; | |
8839 | } | |
8840 | ||
8841 | fragP->fr_fix += fix; | |
8842 | fragP->fr_var = noop_size; | |
8843 | } | |
8844 | ||
8845 | /* Called from md_do_align. Used to create an alignment | |
8846 | frag in a code section. */ | |
8847 | ||
8848 | void | |
8849 | arm_frag_align_code (n, max) | |
8850 | int n; | |
8851 | int max; | |
8852 | { | |
8853 | char * p; | |
8854 | ||
8855 | /* We assume that there will never be a requirment | |
8856 | to support alignments greater than 32 bytes. */ | |
8857 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
8858 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
8859 | ||
8860 | p = frag_var (rs_align_code, | |
8861 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
8862 | 1, | |
8863 | (relax_substateT) max, | |
8864 | (symbolS *) NULL, | |
8865 | (offsetT) n, | |
8866 | (char *) NULL); | |
8867 | *p = 0; | |
8868 | ||
8869 | } | |
8870 | ||
8871 | /* Perform target specific initialisation of a frag. */ | |
8872 | ||
8873 | void | |
8874 | arm_init_frag (fragP) | |
8875 | fragS *fragP; | |
8876 | { | |
8877 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
8878 | fragP->tc_frag_data = thumb_mode; | |
8879 | } |