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Fix typo introduced during the most recent synchronization update.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
d3ce72d0 176static const insn_template *match_template (void);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132
RH		 328
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
333
334 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 335 addressing modes of this insn are encoded. */
252b5132 336 modrm_byte rm;
3e73aa7c 337 rex_byte rex;
43234a1e 338 rex_byte vrex;
252b5132 339 sib_byte sib;
c0f3af97 340 vex_prefix vex;
b6169b20 341
43234a1e
L		 342 /* Masking attributes. */
343 struct Mask_Operation *mask;
344
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
347
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
350
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
353
b6169b20 354 /* Swap operand in encoding. */
4473e004 355 unsigned int swap_operand;
891edac4 356
a501d77e
L		 357 /* Prefer 8bit or 32bit displacement in encoding. */
358 enum
359 {
360 disp_encoding_default = 0,
361 disp_encoding_8bit,
362 disp_encoding_32bit
363 } disp_encoding;
f8a5c266 364
d5de92cf
L		 365 /* REP prefix. */
366 const char *rep_prefix;
367
165de32a
L		 368 /* HLE prefix. */
369 const char *hle_prefix;
42164a71 370
7e8b059b
L		 371 /* Have BND prefix. */
372 const char *bnd_prefix;
373
43234a1e
L		 374 /* Need VREX to support upper 16 registers. */
375 int need_vrex;
376
891edac4 377 /* Error message. */
a65babc9 378 enum i386_error error;
252b5132
RH		 379 };
380
381typedef struct _i386_insn i386_insn;
382
43234a1e
L		 383/* Link RC type with corresponding string, that'll be looked for in
384 asm. */
385struct RC_name
386{
387 enum rc_type type;
388 const char *name;
389 unsigned int len;
390};
391
392static const struct RC_name RC_NamesTable[] =
393{
394 { rne, STRING_COMMA_LEN ("rn-sae") },
395 { rd, STRING_COMMA_LEN ("rd-sae") },
396 { ru, STRING_COMMA_LEN ("ru-sae") },
397 { rz, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly, STRING_COMMA_LEN ("sae") },
399};
400
252b5132
RH		 401/* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 403const char extra_symbol_chars[] = "*%-([{"
252b5132 404#ifdef LEX_AT
32137342
NC		 405 "@"
406#endif
407#ifdef LEX_QM
408 "?"
252b5132 409#endif
32137342 410 ;
252b5132 411
29b0f896
AM		 412#if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 414 && !defined (TE_GNU) \
29b0f896 415 && !defined (TE_LINUX) \
8d63c93e
RM		 416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
29b0f896 418 && !defined (TE_FreeBSD) \
5b806d27 419 && !defined (TE_DragonFly) \
29b0f896 420 && !defined (TE_NetBSD)))
252b5132 421/* This array holds the chars that always start a comment. If the
b3b91714
AM		 422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424const char *i386_comment_chars = "#/";
425#define SVR4_COMMENT_CHARS 1
252b5132 426#define PREFIX_SEPARATOR '\\'
252b5132 427
b3b91714
AM		 428#else
429const char *i386_comment_chars = "#";
430#define PREFIX_SEPARATOR '/'
431#endif
432
252b5132
RH		 433/* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 437 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
252b5132 440 '/' isn't otherwise defined. */
b3b91714 441const char line_comment_chars[] = "#/";
252b5132 442
63a0b638 443const char line_separator_chars[] = ";";
252b5132 444
ce8a8b2f
AM		 445/* Chars that can be used to separate mant from exp in floating point
446 nums. */
252b5132
RH		 447const char EXP_CHARS[] = "eE";
448
ce8a8b2f
AM		 449/* Chars that mean this number is a floating point constant
450 As in 0f12.456
451 or 0d1.2345e12. */
252b5132
RH		 452const char FLT_CHARS[] = "fFdDxX";
453
ce8a8b2f 454/* Tables for lexical analysis. */
252b5132
RH		 455static char mnemonic_chars[256];
456static char register_chars[256];
457static char operand_chars[256];
458static char identifier_chars[256];
459static char digit_chars[256];
460
ce8a8b2f 461/* Lexical macros. */
252b5132
RH		 462#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463#define is_operand_char(x) (operand_chars[(unsigned char) x])
464#define is_register_char(x) (register_chars[(unsigned char) x])
465#define is_space_char(x) ((x) == ' ')
466#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467#define is_digit_char(x) (digit_chars[(unsigned char) x])
468
0234cb7c 469/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 470static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
471
472/* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
47926f60 475 assembler instruction). */
252b5132 476static char save_stack[32];
ce8a8b2f 477static char *save_stack_p;
252b5132
RH		 478#define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480#define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
482
47926f60 483/* The instruction we're assembling. */
252b5132
RH		 484static i386_insn i;
485
486/* Possible templates for current insn. */
487static const templates *current_templates;
488
31b2323c
L		 489/* Per instruction expressionS buffers: max displacements & immediates. */
490static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
491static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 492
47926f60 493/* Current operand we are working on. */
ee86248c 494static int this_operand = -1;
252b5132 495
3e73aa7c
JH		 496/* We support four different modes. FLAG_CODE variable is used to distinguish
497 these. */
498
499enum flag_code {
500 CODE_32BIT,
501 CODE_16BIT,
502 CODE_64BIT };
503
504static enum flag_code flag_code;
4fa24527 505static unsigned int object_64bit;
862be3fb 506static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 507static int use_rela_relocations = 0;
508
7af8ed2d
NC		 509#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
512
351f65ca
L		 513/* The ELF ABI to use. */
514enum x86_elf_abi
515{
516 I386_ABI,
7f56bc95
L		 517 X86_64_ABI,
518 X86_64_X32_ABI
351f65ca
L		 519};
520
521static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 522#endif
351f65ca 523
167ad85b
TG		 524#if defined (TE_PE) || defined (TE_PEP)
525/* Use big object file format. */
526static int use_big_obj = 0;
527#endif
528
8dcea932
L		 529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530/* 1 if generating code for a shared library. */
531static int shared = 0;
532#endif
533
47926f60
KH		 534/* 1 for intel syntax,
535 0 if att syntax. */
536static int intel_syntax = 0;
252b5132 537
1efbbeb4
L		 538/* 1 for intel mnemonic,
539 0 if att mnemonic. */
540static int intel_mnemonic = !SYSV386_COMPAT;
541
5209009a 542/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 543static int old_gcc = OLDGCC_COMPAT;
544
a60de03c
JB		 545/* 1 if pseudo registers are permitted. */
546static int allow_pseudo_reg = 0;
547
47926f60
KH		 548/* 1 if register prefix % not required. */
549static int allow_naked_reg = 0;
252b5132 550
7e8b059b
L		 551/* 1 if the assembler should add BND prefix for all control-tranferring
552 instructions supporting it, even if this prefix wasn't specified
553 explicitly. */
554static int add_bnd_prefix = 0;
555
ba104c83 556/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 557static int allow_index_reg = 0;
558
d022bddd
IT		 559/* 1 if the assembler should ignore LOCK prefix, even if it was
560 specified explicitly. */
561static int omit_lock_prefix = 0;
562
e4e00185
AS		 563/* 1 if the assembler should encode lfence, mfence, and sfence as
564 "lock addl $0, (%{re}sp)". */
565static int avoid_fence = 0;
566
0cb4071e
L		 567/* 1 if the assembler should generate relax relocations. */
568
569static int generate_relax_relocations
570 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
571
7bab8ab5 572static enum check_kind
daf50ae7 573 {
7bab8ab5
JB		 574 check_none = 0,
575 check_warning,
576 check_error
daf50ae7 577 }
7bab8ab5 578sse_check, operand_check = check_warning;
daf50ae7 579
2ca3ace5
L		 580/* Register prefix used for error message. */
581static const char *register_prefix = "%";
582
47926f60
KH		 583/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
584 leave, push, and pop instructions so that gcc has the same stack
585 frame as in 32 bit mode. */
586static char stackop_size = '\0';
eecb386c 587
12b55ccc
L		 588/* Non-zero to optimize code alignment. */
589int optimize_align_code = 1;
590
47926f60
KH		 591/* Non-zero to quieten some warnings. */
592static int quiet_warnings = 0;
a38cf1db 593
47926f60
KH		 594/* CPU name. */
595static const char *cpu_arch_name = NULL;
6305a203 596static char *cpu_sub_arch_name = NULL;
a38cf1db 597
47926f60 598/* CPU feature flags. */
40fb9820
L		 599static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
600
ccc9c027
L		 601/* If we have selected a cpu we are generating instructions for. */
602static int cpu_arch_tune_set = 0;
603
9103f4f4 604/* Cpu we are generating instructions for. */
fbf3f584 605enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 606
607/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 608static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 609
ccc9c027 610/* CPU instruction set architecture used. */
fbf3f584 611enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 612
9103f4f4 613/* CPU feature flags of instruction set architecture used. */
fbf3f584 614i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 615
fddf5b5b
AM		 616/* If set, conditional jumps are not automatically promoted to handle
617 larger than a byte offset. */
618static unsigned int no_cond_jump_promotion = 0;
619
c0f3af97
L		 620/* Encode SSE instructions with VEX prefix. */
621static unsigned int sse2avx;
622
539f890d
L		 623/* Encode scalar AVX instructions with specific vector length. */
624static enum
625 {
626 vex128 = 0,
627 vex256
628 } avxscalar;
629
43234a1e
L		 630/* Encode scalar EVEX LIG instructions with specific vector length. */
631static enum
632 {
633 evexl128 = 0,
634 evexl256,
635 evexl512
636 } evexlig;
637
638/* Encode EVEX WIG instructions with specific evex.w. */
639static enum
640 {
641 evexw0 = 0,
642 evexw1
643 } evexwig;
644
d3d3c6db
IT		 645/* Value to encode in EVEX RC bits, for SAE-only instructions. */
646static enum rc_type evexrcig = rne;
647
29b0f896 648/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 649static symbolS *GOT_symbol;
29b0f896 650
a4447b93
RH		 651/* The dwarf2 return column, adjusted for 32 or 64 bit. */
652unsigned int x86_dwarf2_return_column;
653
654/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
655int x86_cie_data_alignment;
656
252b5132 657/* Interface to relax_segment.
fddf5b5b
AM		 658 There are 3 major relax states for 386 jump insns because the
659 different types of jumps add different sizes to frags when we're
660 figuring out what sort of jump to choose to reach a given label. */
252b5132 661
47926f60 662/* Types. */
93c2a809
AM		 663#define UNCOND_JUMP 0
664#define COND_JUMP 1
665#define COND_JUMP86 2
fddf5b5b 666
47926f60 667/* Sizes. */
252b5132
RH		 668#define CODE16 1
669#define SMALL 0
29b0f896 670#define SMALL16 (SMALL | CODE16)
252b5132 671#define BIG 2
29b0f896 672#define BIG16 (BIG | CODE16)
252b5132
RH		 673
674#ifndef INLINE
675#ifdef __GNUC__
676#define INLINE __inline__
677#else
678#define INLINE
679#endif
680#endif
681
fddf5b5b
AM		 682#define ENCODE_RELAX_STATE(type, size) \
683 ((relax_substateT) (((type) << 2) | (size)))
684#define TYPE_FROM_RELAX_STATE(s) \
685 ((s) >> 2)
686#define DISP_SIZE_FROM_RELAX_STATE(s) \
687 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 688
689/* This table is used by relax_frag to promote short jumps to long
690 ones where necessary. SMALL (short) jumps may be promoted to BIG
691 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
692 don't allow a short jump in a 32 bit code segment to be promoted to
693 a 16 bit offset jump because it's slower (requires data size
694 prefix), and doesn't work, unless the destination is in the bottom
695 64k of the code segment (The top 16 bits of eip are zeroed). */
696
697const relax_typeS md_relax_table[] =
698{
24eab124
AM		 699 /* The fields are:
700 1) most positive reach of this state,
701 2) most negative reach of this state,
93c2a809 702 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 703 4) which index into the table to try if we can't fit into this one. */
252b5132 704
fddf5b5b 705 /* UNCOND_JUMP states. */
93c2a809
AM		 706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
707 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
708 /* dword jmp adds 4 bytes to frag:
709 0 extra opcode bytes, 4 displacement bytes. */
252b5132 710 {0, 0, 4, 0},
93c2a809
AM		 711 /* word jmp adds 2 byte2 to frag:
712 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 713 {0, 0, 2, 0},
714
93c2a809
AM		 715 /* COND_JUMP states. */
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
717 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
718 /* dword conditionals adds 5 bytes to frag:
719 1 extra opcode byte, 4 displacement bytes. */
720 {0, 0, 5, 0},
fddf5b5b 721 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 722 1 extra opcode byte, 2 displacement bytes. */
723 {0, 0, 3, 0},
724
725 /* COND_JUMP86 states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
728 /* dword conditionals adds 5 bytes to frag:
729 1 extra opcode byte, 4 displacement bytes. */
730 {0, 0, 5, 0},
731 /* word conditionals add 4 bytes to frag:
732 1 displacement byte and a 3 byte long branch insn. */
733 {0, 0, 4, 0}
252b5132
RH		 734};
735
9103f4f4
L		 736static const arch_entry cpu_arch[] =
737{
89507696
JB		 738 /* Do not replace the first two entries - i386_target_format()
739 relies on them being there in this order. */
8a2c8fef 740 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 741 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 743 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 745 CPU_NONE_FLAGS, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 747 CPU_I186_FLAGS, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 749 CPU_I286_FLAGS, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 751 CPU_I386_FLAGS, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 753 CPU_I486_FLAGS, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 755 CPU_I586_FLAGS, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 757 CPU_I686_FLAGS, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 759 CPU_I586_FLAGS, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 761 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 763 CPU_P2_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 765 CPU_P3_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 767 CPU_P4_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 769 CPU_CORE_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 771 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 773 CPU_CORE_FLAGS, 1 },
8a2c8fef 774 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 775 CPU_CORE_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 777 CPU_CORE2_FLAGS, 1 },
8a2c8fef 778 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 779 CPU_CORE2_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 781 CPU_COREI7_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 783 CPU_L1OM_FLAGS, 0 },
7a9068fe 784 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 785 CPU_K1OM_FLAGS, 0 },
81486035 786 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 787 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 789 CPU_K6_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 791 CPU_K6_2_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 793 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 795 CPU_K8_FLAGS, 1 },
8a2c8fef 796 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 797 CPU_K8_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 799 CPU_K8_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 801 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 802 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 803 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 804 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 805 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 806 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 807 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 808 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 809 CPU_BDVER4_FLAGS, 0 },
029f3522 810 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 811 CPU_ZNVER1_FLAGS, 0 },
7b458c12 812 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 813 CPU_BTVER1_FLAGS, 0 },
7b458c12 814 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 815 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 817 CPU_8087_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 819 CPU_287_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 821 CPU_387_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 823 CPU_MMX_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 825 CPU_SSE_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 827 CPU_SSE2_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 829 CPU_SSE3_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 831 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 833 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 835 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_AVX_FLAGS, 0 },
6c30d220 840 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_AVX2_FLAGS, 0 },
43234a1e 842 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 843 CPU_AVX512F_FLAGS, 0 },
43234a1e 844 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_AVX512CD_FLAGS, 0 },
43234a1e 846 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_AVX512ER_FLAGS, 0 },
43234a1e 848 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 850 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 852 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 854 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_VMX_FLAGS, 0 },
8729a6f6 858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_SMX_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_AES_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_F16C_FLAGS, 0 },
6c30d220 882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_BMI2_FLAGS, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_FMA_FLAGS, 0 },
8a2c8fef 886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_FMA4_FLAGS, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_XOP_FLAGS, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_LWP_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_MOVBE_FLAGS, 0 },
60aa667e 894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_CX16_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_EPT_FLAGS, 0 },
6c30d220 898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_LZCNT_FLAGS, 0 },
42164a71 900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_HLE_FLAGS, 0 },
42164a71 902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_RTM_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_CLFLUSH_FLAGS, 0 },
22109423 908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_NOP_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_SVME_FLAGS, 1 },
8a2c8fef 922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_SVME_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_ABM_FLAGS, 0 },
87973e9f 928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_BMI_FLAGS, 0 },
2a2a0f38 930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_TBM_FLAGS, 0 },
e2e1fcde 932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_ADX_FLAGS, 0 },
e2e1fcde 934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_PRFCHW_FLAGS, 0 },
5c111e37 938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_SMAP_FLAGS, 0 },
7e8b059b 940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_MPX_FLAGS, 0 },
a0046408 942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SHA_FLAGS, 0 },
963f3586 944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SE1_FLAGS, 0 },
c5e7287a 950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_CLWB_FLAGS, 0 },
9d8596f0 952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_CLZERO_FLAGS, 0 },
9916071f 960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_MWAITX_FLAGS, 0 },
8eab4136 962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_OSPKE_FLAGS, 0 },
8bc52696 964 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65
L		 965 CPU_RDPID_FLAGS, 0 },
966};
967
968static const noarch_entry cpu_noarch[] =
969{
970 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
971 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
972 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
973 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
e413e4e9
AM		 974};
975
704209c0 976#ifdef I386COFF
a6c24e68
NC		 977/* Like s_lcomm_internal in gas/read.c but the alignment string
978 is allowed to be optional. */
979
980static symbolS *
981pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
982{
983 addressT align = 0;
984
985 SKIP_WHITESPACE ();
986
7ab9ffdd 987 if (needs_align
a6c24e68
NC		 988 && *input_line_pointer == ',')
989 {
990 align = parse_align (needs_align - 1);
7ab9ffdd 991
a6c24e68
NC		 992 if (align == (addressT) -1)
993 return NULL;
994 }
995 else
996 {
997 if (size >= 8)
998 align = 3;
999 else if (size >= 4)
1000 align = 2;
1001 else if (size >= 2)
1002 align = 1;
1003 else
1004 align = 0;
1005 }
1006
1007 bss_alloc (symbolP, size, align);
1008 return symbolP;
1009}
1010
704209c0 1011static void
a6c24e68
NC		 1012pe_lcomm (int needs_align)
1013{
1014 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1015}
704209c0 1016#endif
a6c24e68 1017
29b0f896
AM		 1018const pseudo_typeS md_pseudo_table[] =
1019{
1020#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1021 {"align", s_align_bytes, 0},
1022#else
1023 {"align", s_align_ptwo, 0},
1024#endif
1025 {"arch", set_cpu_arch, 0},
1026#ifndef I386COFF
1027 {"bss", s_bss, 0},
a6c24e68
NC		 1028#else
1029 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1030#endif
1031 {"ffloat", float_cons, 'f'},
1032 {"dfloat", float_cons, 'd'},
1033 {"tfloat", float_cons, 'x'},
1034 {"value", cons, 2},
d182319b 1035 {"slong", signed_cons, 4},
29b0f896
AM		 1036 {"noopt", s_ignore, 0},
1037 {"optim", s_ignore, 0},
1038 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1039 {"code16", set_code_flag, CODE_16BIT},
1040 {"code32", set_code_flag, CODE_32BIT},
1041 {"code64", set_code_flag, CODE_64BIT},
1042 {"intel_syntax", set_intel_syntax, 1},
1043 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1044 {"intel_mnemonic", set_intel_mnemonic, 1},
1045 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1046 {"allow_index_reg", set_allow_index_reg, 1},
1047 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1048 {"sse_check", set_check, 0},
1049 {"operand_check", set_check, 1},
3b22753a
L		 1050#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1051 {"largecomm", handle_large_common, 0},
07a53e5c 1052#else
e3bb37b5 1053 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1054 {"loc", dwarf2_directive_loc, 0},
1055 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1056#endif
6482c264
NC		 1057#ifdef TE_PE
1058 {"secrel32", pe_directive_secrel, 0},
1059#endif
29b0f896
AM		 1060 {0, 0, 0}
1061};
1062
1063/* For interface with expression (). */
1064extern char *input_line_pointer;
1065
1066/* Hash table for instruction mnemonic lookup. */
1067static struct hash_control *op_hash;
1068
1069/* Hash table for register lookup. */
1070static struct hash_control *reg_hash;
1071\f
252b5132 1072void
e3bb37b5 1073i386_align_code (fragS *fragP, int count)
252b5132 1074{
ce8a8b2f
AM		 1075 /* Various efficient no-op patterns for aligning code labels.
1076 Note: Don't try to assemble the instructions in the comments.
1077 0L and 0w are not legal. */
bad6e36d 1078 static const unsigned char f32_1[] =
252b5132 1079 {0x90}; /* nop */
bad6e36d 1080 static const unsigned char f32_2[] =
ccc9c027 1081 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1082 static const unsigned char f32_3[] =
252b5132 1083 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1084 static const unsigned char f32_4[] =
252b5132 1085 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1086 static const unsigned char f32_5[] =
252b5132
RH		 1087 {0x90, /* nop */
1088 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1089 static const unsigned char f32_6[] =
252b5132 1090 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1091 static const unsigned char f32_7[] =
252b5132 1092 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1093 static const unsigned char f32_8[] =
252b5132
RH		 1094 {0x90, /* nop */
1095 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1096 static const unsigned char f32_9[] =
252b5132
RH		 1097 {0x89,0xf6, /* movl %esi,%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1099 static const unsigned char f32_10[] =
252b5132
RH		 1100 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1101 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1102 static const unsigned char f32_11[] =
252b5132
RH		 1103 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1104 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1105 static const unsigned char f32_12[] =
252b5132
RH		 1106 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1107 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1108 static const unsigned char f32_13[] =
252b5132
RH		 1109 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1110 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1111 static const unsigned char f32_14[] =
252b5132
RH		 1112 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1113 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1114 static const unsigned char f16_3[] =
c3332e24 1115 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1116 static const unsigned char f16_4[] =
252b5132 1117 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1118 static const unsigned char f16_5[] =
252b5132
RH		 1119 {0x90, /* nop */
1120 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1121 static const unsigned char f16_6[] =
252b5132
RH		 1122 {0x89,0xf6, /* mov %si,%si */
1123 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1124 static const unsigned char f16_7[] =
252b5132
RH		 1125 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1126 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1127 static const unsigned char f16_8[] =
252b5132
RH		 1128 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1129 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1130 static const unsigned char jump_31[] =
76bc74dc
L		 1131 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1132 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1133 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1134 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1135 static const unsigned char *const f32_patt[] = {
252b5132 1136 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1137 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1138 };
bad6e36d 1139 static const unsigned char *const f16_patt[] = {
76bc74dc 1140 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1141 };
ccc9c027 1142 /* nopl (%[re]ax) */
bad6e36d 1143 static const unsigned char alt_3[] =
ccc9c027
L		 1144 {0x0f,0x1f,0x00};
1145 /* nopl 0(%[re]ax) */
bad6e36d 1146 static const unsigned char alt_4[] =
ccc9c027
L		 1147 {0x0f,0x1f,0x40,0x00};
1148 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1149 static const unsigned char alt_5[] =
ccc9c027
L		 1150 {0x0f,0x1f,0x44,0x00,0x00};
1151 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1152 static const unsigned char alt_6[] =
ccc9c027
L		 1153 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopl 0L(%[re]ax) */
bad6e36d 1155 static const unsigned char alt_7[] =
ccc9c027
L		 1156 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1157 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1158 static const unsigned char alt_8[] =
ccc9c027
L		 1159 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1160 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1161 static const unsigned char alt_9[] =
ccc9c027
L		 1162 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1163 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1164 static const unsigned char alt_10[] =
ccc9c027 1165 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1166 static const unsigned char *const alt_patt[] = {
ccc9c027 1167 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1168 alt_9, alt_10
ccc9c027 1169 };
252b5132 1170
76bc74dc
L		 1171 /* Only align for at least a positive non-zero boundary. */
1172 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1173 return;
3e73aa7c 1174
ccc9c027
L		 1175 /* We need to decide which NOP sequence to use for 32bit and
1176 64bit. When -mtune= is used:
4eed87de 1177
76bc74dc
L		 1178 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1179 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1180 2. For the rest, alt_patt will be used.
1181
1182 When -mtune= isn't used, alt_patt will be used if
22109423 1183 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1184 be used.
ccc9c027
L		 1185
1186 When -march= or .arch is used, we can't use anything beyond
1187 cpu_arch_isa_flags. */
1188
1189 if (flag_code == CODE_16BIT)
1190 {
ccc9c027 1191 if (count > 8)
33fef721 1192 {
76bc74dc
L		 1193 memcpy (fragP->fr_literal + fragP->fr_fix,
1194 jump_31, count);
1195 /* Adjust jump offset. */
1196 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1197 }
76bc74dc
L		 1198 else
1199 memcpy (fragP->fr_literal + fragP->fr_fix,
1200 f16_patt[count - 1], count);
252b5132 1201 }
33fef721 1202 else
ccc9c027 1203 {
bad6e36d 1204 const unsigned char *const *patt = NULL;
ccc9c027 1205
fbf3f584 1206 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1207 {
1208 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1209 switch (cpu_arch_tune)
1210 {
1211 case PROCESSOR_UNKNOWN:
1212 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1213 optimize with nops. */
1214 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1215 patt = alt_patt;
ccc9c027
L		 1216 else
1217 patt = f32_patt;
1218 break;
ccc9c027
L		 1219 case PROCESSOR_PENTIUM4:
1220 case PROCESSOR_NOCONA:
ef05d495 1221 case PROCESSOR_CORE:
76bc74dc 1222 case PROCESSOR_CORE2:
bd5295b2 1223 case PROCESSOR_COREI7:
3632d14b 1224 case PROCESSOR_L1OM:
7a9068fe 1225 case PROCESSOR_K1OM:
76bc74dc 1226 case PROCESSOR_GENERIC64:
ccc9c027
L		 1227 case PROCESSOR_K6:
1228 case PROCESSOR_ATHLON:
1229 case PROCESSOR_K8:
4eed87de 1230 case PROCESSOR_AMDFAM10:
8aedb9fe 1231 case PROCESSOR_BD:
029f3522 1232 case PROCESSOR_ZNVER:
7b458c12 1233 case PROCESSOR_BT:
80b8656c 1234 patt = alt_patt;
ccc9c027 1235 break;
76bc74dc 1236 case PROCESSOR_I386:
ccc9c027
L		 1237 case PROCESSOR_I486:
1238 case PROCESSOR_PENTIUM:
2dde1948 1239 case PROCESSOR_PENTIUMPRO:
81486035 1240 case PROCESSOR_IAMCU:
ccc9c027
L		 1241 case PROCESSOR_GENERIC32:
1242 patt = f32_patt;
1243 break;
4eed87de 1244 }
ccc9c027
L		 1245 }
1246 else
1247 {
fbf3f584 1248 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1249 {
1250 case PROCESSOR_UNKNOWN:
e6a14101 1251 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1252 PROCESSOR_UNKNOWN. */
1253 abort ();
1254 break;
1255
76bc74dc 1256 case PROCESSOR_I386:
ccc9c027
L		 1257 case PROCESSOR_I486:
1258 case PROCESSOR_PENTIUM:
81486035 1259 case PROCESSOR_IAMCU:
ccc9c027
L		 1260 case PROCESSOR_K6:
1261 case PROCESSOR_ATHLON:
1262 case PROCESSOR_K8:
4eed87de 1263 case PROCESSOR_AMDFAM10:
8aedb9fe 1264 case PROCESSOR_BD:
029f3522 1265 case PROCESSOR_ZNVER:
7b458c12 1266 case PROCESSOR_BT:
ccc9c027
L		 1267 case PROCESSOR_GENERIC32:
1268 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1269 with nops. */
1270 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1271 patt = alt_patt;
ccc9c027
L		 1272 else
1273 patt = f32_patt;
1274 break;
76bc74dc
L		 1275 case PROCESSOR_PENTIUMPRO:
1276 case PROCESSOR_PENTIUM4:
1277 case PROCESSOR_NOCONA:
1278 case PROCESSOR_CORE:
ef05d495 1279 case PROCESSOR_CORE2:
bd5295b2 1280 case PROCESSOR_COREI7:
3632d14b 1281 case PROCESSOR_L1OM:
7a9068fe 1282 case PROCESSOR_K1OM:
22109423 1283 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1284 patt = alt_patt;
ccc9c027
L		 1285 else
1286 patt = f32_patt;
1287 break;
1288 case PROCESSOR_GENERIC64:
80b8656c 1289 patt = alt_patt;
ccc9c027 1290 break;
4eed87de 1291 }
ccc9c027
L		 1292 }
1293
76bc74dc
L		 1294 if (patt == f32_patt)
1295 {
1296 /* If the padding is less than 15 bytes, we use the normal
1297 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1298 its offset. */
1299 int limit;
76ba9986 1300
711eedef
L		 1301 /* For 64bit, the limit is 3 bytes. */
1302 if (flag_code == CODE_64BIT
1303 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1304 limit = 3;
1305 else
1306 limit = 15;
1307 if (count < limit)
76bc74dc
L		 1308 memcpy (fragP->fr_literal + fragP->fr_fix,
1309 patt[count - 1], count);
1310 else
1311 {
1312 memcpy (fragP->fr_literal + fragP->fr_fix,
1313 jump_31, count);
1314 /* Adjust jump offset. */
1315 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1316 }
1317 }
1318 else
1319 {
80b8656c
L		 1320 /* Maximum length of an instruction is 10 byte. If the
1321 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1322 we have to break it into smaller pieces. */
1323 int padding = count;
80b8656c 1324 while (padding > 10)
76bc74dc 1325 {
80b8656c 1326 padding -= 10;
76bc74dc 1327 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1328 patt [9], 10);
76bc74dc
L		 1329 }
1330
1331 if (padding)
1332 memcpy (fragP->fr_literal + fragP->fr_fix,
1333 patt [padding - 1], padding);
1334 }
ccc9c027 1335 }
33fef721 1336 fragP->fr_var = count;
252b5132
RH		 1337}
1338
c6fb90c8 1339static INLINE int
0dfbf9d7 1340operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1341{
0dfbf9d7 1342 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1343 {
1344 case 3:
0dfbf9d7 1345 if (x->array[2])
c6fb90c8
L		 1346 return 0;
1347 case 2:
0dfbf9d7 1348 if (x->array[1])
c6fb90c8
L		 1349 return 0;
1350 case 1:
0dfbf9d7 1351 return !x->array[0];
c6fb90c8
L		 1352 default:
1353 abort ();
1354 }
40fb9820
L		 1355}
1356
c6fb90c8 1357static INLINE void
0dfbf9d7 1358operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1359{
0dfbf9d7 1360 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1361 {
1362 case 3:
0dfbf9d7 1363 x->array[2] = v;
c6fb90c8 1364 case 2:
0dfbf9d7 1365 x->array[1] = v;
c6fb90c8 1366 case 1:
0dfbf9d7 1367 x->array[0] = v;
c6fb90c8
L		 1368 break;
1369 default:
1370 abort ();
1371 }
1372}
40fb9820 1373
c6fb90c8 1374static INLINE int
0dfbf9d7
L		 1375operand_type_equal (const union i386_operand_type *x,
1376 const union i386_operand_type *y)
c6fb90c8 1377{
0dfbf9d7 1378 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1379 {
1380 case 3:
0dfbf9d7 1381 if (x->array[2] != y->array[2])
c6fb90c8
L		 1382 return 0;
1383 case 2:
0dfbf9d7 1384 if (x->array[1] != y->array[1])
c6fb90c8
L		 1385 return 0;
1386 case 1:
0dfbf9d7 1387 return x->array[0] == y->array[0];
c6fb90c8
L		 1388 break;
1389 default:
1390 abort ();
1391 }
1392}
40fb9820 1393
0dfbf9d7
L		 1394static INLINE int
1395cpu_flags_all_zero (const union i386_cpu_flags *x)
1396{
1397 switch (ARRAY_SIZE(x->array))
1398 {
1399 case 3:
1400 if (x->array[2])
1401 return 0;
1402 case 2:
1403 if (x->array[1])
1404 return 0;
1405 case 1:
1406 return !x->array[0];
1407 default:
1408 abort ();
1409 }
1410}
1411
0dfbf9d7
L		 1412static INLINE int
1413cpu_flags_equal (const union i386_cpu_flags *x,
1414 const union i386_cpu_flags *y)
1415{
1416 switch (ARRAY_SIZE(x->array))
1417 {
1418 case 3:
1419 if (x->array[2] != y->array[2])
1420 return 0;
1421 case 2:
1422 if (x->array[1] != y->array[1])
1423 return 0;
1424 case 1:
1425 return x->array[0] == y->array[0];
1426 break;
1427 default:
1428 abort ();
1429 }
1430}
c6fb90c8
L		 1431
1432static INLINE int
1433cpu_flags_check_cpu64 (i386_cpu_flags f)
1434{
1435 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1436 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1437}
1438
c6fb90c8
L		 1439static INLINE i386_cpu_flags
1440cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1441{
c6fb90c8
L		 1442 switch (ARRAY_SIZE (x.array))
1443 {
1444 case 3:
1445 x.array [2] &= y.array [2];
1446 case 2:
1447 x.array [1] &= y.array [1];
1448 case 1:
1449 x.array [0] &= y.array [0];
1450 break;
1451 default:
1452 abort ();
1453 }
1454 return x;
1455}
40fb9820 1456
c6fb90c8
L		 1457static INLINE i386_cpu_flags
1458cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1459{
c6fb90c8 1460 switch (ARRAY_SIZE (x.array))
40fb9820 1461 {
c6fb90c8
L		 1462 case 3:
1463 x.array [2] |= y.array [2];
1464 case 2:
1465 x.array [1] |= y.array [1];
1466 case 1:
1467 x.array [0] |= y.array [0];
40fb9820
L		 1468 break;
1469 default:
1470 abort ();
1471 }
40fb9820
L		 1472 return x;
1473}
1474
309d3373
JB		 1475static INLINE i386_cpu_flags
1476cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1477{
1478 switch (ARRAY_SIZE (x.array))
1479 {
1480 case 3:
1481 x.array [2] &= ~y.array [2];
1482 case 2:
1483 x.array [1] &= ~y.array [1];
1484 case 1:
1485 x.array [0] &= ~y.array [0];
1486 break;
1487 default:
1488 abort ();
1489 }
1490 return x;
1491}
1492
81486035
L		 1493static int
1494valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1495{
1496 if (cpu_arch_isa == PROCESSOR_IAMCU)
1497 {
1498 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1499 i386_cpu_flags compat_flags;
1500 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1501 return cpu_flags_all_zero (&compat_flags);
1502 }
1503 else
1504 return 1;
1505}
1506
c0f3af97
L		 1507#define CPU_FLAGS_ARCH_MATCH 0x1
1508#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1509#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1510#define CPU_FLAGS_PCLMUL_MATCH 0x8
1511#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1512
a5ff0eb2 1513#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1514 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1515 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1516#define CPU_FLAGS_PERFECT_MATCH \
1517 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1518
1519/* Return CPU flags match bits. */
3629bb00 1520
40fb9820 1521static int
d3ce72d0 1522cpu_flags_match (const insn_template *t)
40fb9820 1523{
c0f3af97
L		 1524 i386_cpu_flags x = t->cpu_flags;
1525 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1526
1527 x.bitfield.cpu64 = 0;
1528 x.bitfield.cpuno64 = 0;
1529
0dfbf9d7 1530 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1531 {
1532 /* This instruction is available on all archs. */
1533 match |= CPU_FLAGS_32BIT_MATCH;
1534 }
3629bb00
L		 1535 else
1536 {
c0f3af97 1537 /* This instruction is available only on some archs. */
3629bb00
L		 1538 i386_cpu_flags cpu = cpu_arch_flags;
1539
3629bb00 1540 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1541 if (!cpu_flags_all_zero (&cpu))
1542 {
a5ff0eb2
L		 1543 if (x.bitfield.cpuavx)
1544 {
ce2f5b3c 1545 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1546 if (cpu.bitfield.cpuavx)
1547 {
1548 /* Check SSE2AVX. */
1549 if (!t->opcode_modifier.sse2avx|| sse2avx)
1550 {
1551 match |= (CPU_FLAGS_ARCH_MATCH
1552 | CPU_FLAGS_AVX_MATCH);
1553 /* Check AES. */
1554 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1555 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1556 /* Check PCLMUL. */
1557 if (!x.bitfield.cpupclmul
1558 || cpu.bitfield.cpupclmul)
1559 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1560 }
1561 }
1562 else
1563 match |= CPU_FLAGS_ARCH_MATCH;
1564 }
73b090a9
L		 1565 else if (x.bitfield.cpuavx512vl)
1566 {
1567 /* Match AVX512VL. */
1568 if (cpu.bitfield.cpuavx512vl)
1569 {
1570 /* Need another match. */
1571 cpu.bitfield.cpuavx512vl = 0;
1572 if (!cpu_flags_all_zero (&cpu))
1573 match |= CPU_FLAGS_32BIT_MATCH;
1574 else
1575 match |= CPU_FLAGS_ARCH_MATCH;
1576 }
1577 else
1578 match |= CPU_FLAGS_ARCH_MATCH;
1579 }
a5ff0eb2 1580 else
c0f3af97
L		 1581 match |= CPU_FLAGS_32BIT_MATCH;
1582 }
3629bb00 1583 }
c0f3af97 1584 return match;
40fb9820
L		 1585}
1586
c6fb90c8
L		 1587static INLINE i386_operand_type
1588operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1589{
c6fb90c8
L		 1590 switch (ARRAY_SIZE (x.array))
1591 {
1592 case 3:
1593 x.array [2] &= y.array [2];
1594 case 2:
1595 x.array [1] &= y.array [1];
1596 case 1:
1597 x.array [0] &= y.array [0];
1598 break;
1599 default:
1600 abort ();
1601 }
1602 return x;
40fb9820
L		 1603}
1604
c6fb90c8
L		 1605static INLINE i386_operand_type
1606operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1607{
c6fb90c8 1608 switch (ARRAY_SIZE (x.array))
40fb9820 1609 {
c6fb90c8
L		 1610 case 3:
1611 x.array [2] |= y.array [2];
1612 case 2:
1613 x.array [1] |= y.array [1];
1614 case 1:
1615 x.array [0] |= y.array [0];
40fb9820
L		 1616 break;
1617 default:
1618 abort ();
1619 }
c6fb90c8
L		 1620 return x;
1621}
40fb9820 1622
c6fb90c8
L		 1623static INLINE i386_operand_type
1624operand_type_xor (i386_operand_type x, i386_operand_type y)
1625{
1626 switch (ARRAY_SIZE (x.array))
1627 {
1628 case 3:
1629 x.array [2] ^= y.array [2];
1630 case 2:
1631 x.array [1] ^= y.array [1];
1632 case 1:
1633 x.array [0] ^= y.array [0];
1634 break;
1635 default:
1636 abort ();
1637 }
40fb9820
L		 1638 return x;
1639}
1640
1641static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1642static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1643static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1644static const i386_operand_type inoutportreg
1645 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1646static const i386_operand_type reg16_inoutportreg
1647 = OPERAND_TYPE_REG16_INOUTPORTREG;
1648static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1649static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1650static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1651static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1652static const i386_operand_type anydisp
1653 = OPERAND_TYPE_ANYDISP;
40fb9820 1654static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1655static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1656static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1657static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1658static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1659static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1660static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1661static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1662static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1663static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1664static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1665static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1666static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1667static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1668
1669enum operand_type
1670{
1671 reg,
40fb9820
L		 1672 imm,
1673 disp,
1674 anymem
1675};
1676
c6fb90c8 1677static INLINE int
40fb9820
L		 1678operand_type_check (i386_operand_type t, enum operand_type c)
1679{
1680 switch (c)
1681 {
1682 case reg:
1683 return (t.bitfield.reg8
1684 || t.bitfield.reg16
1685 || t.bitfield.reg32
1686 || t.bitfield.reg64);
1687
40fb9820
L		 1688 case imm:
1689 return (t.bitfield.imm8
1690 || t.bitfield.imm8s
1691 || t.bitfield.imm16
1692 || t.bitfield.imm32
1693 || t.bitfield.imm32s
1694 || t.bitfield.imm64);
1695
1696 case disp:
1697 return (t.bitfield.disp8
1698 || t.bitfield.disp16
1699 || t.bitfield.disp32
1700 || t.bitfield.disp32s
1701 || t.bitfield.disp64);
1702
1703 case anymem:
1704 return (t.bitfield.disp8
1705 || t.bitfield.disp16
1706 || t.bitfield.disp32
1707 || t.bitfield.disp32s
1708 || t.bitfield.disp64
1709 || t.bitfield.baseindex);
1710
1711 default:
1712 abort ();
1713 }
2cfe26b6
AM		 1714
1715 return 0;
40fb9820
L		 1716}
1717
5c07affc
L		 1718/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1719 operand J for instruction template T. */
1720
1721static INLINE int
d3ce72d0 1722match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1723{
1724 return !((i.types[j].bitfield.byte
1725 && !t->operand_types[j].bitfield.byte)
1726 || (i.types[j].bitfield.word
1727 && !t->operand_types[j].bitfield.word)
1728 || (i.types[j].bitfield.dword
1729 && !t->operand_types[j].bitfield.dword)
1730 || (i.types[j].bitfield.qword
1731 && !t->operand_types[j].bitfield.qword));
1732}
1733
1734/* Return 1 if there is no conflict in any size on operand J for
1735 instruction template T. */
1736
1737static INLINE int
d3ce72d0 1738match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1739{
1740 return (match_reg_size (t, j)
1741 && !((i.types[j].bitfield.unspecified
af508cb9 1742 && !i.broadcast
5c07affc
L		 1743 && !t->operand_types[j].bitfield.unspecified)
1744 || (i.types[j].bitfield.fword
1745 && !t->operand_types[j].bitfield.fword)
1746 || (i.types[j].bitfield.tbyte
1747 && !t->operand_types[j].bitfield.tbyte)
1748 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1749 && !t->operand_types[j].bitfield.xmmword)
1750 || (i.types[j].bitfield.ymmword
43234a1e
L		 1751 && !t->operand_types[j].bitfield.ymmword)
1752 || (i.types[j].bitfield.zmmword
1753 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1754}
1755
1756/* Return 1 if there is no size conflict on any operands for
1757 instruction template T. */
1758
1759static INLINE int
d3ce72d0 1760operand_size_match (const insn_template *t)
5c07affc
L		 1761{
1762 unsigned int j;
1763 int match = 1;
1764
1765 /* Don't check jump instructions. */
1766 if (t->opcode_modifier.jump
1767 || t->opcode_modifier.jumpbyte
1768 || t->opcode_modifier.jumpdword
1769 || t->opcode_modifier.jumpintersegment)
1770 return match;
1771
1772 /* Check memory and accumulator operand size. */
1773 for (j = 0; j < i.operands; j++)
1774 {
1775 if (t->operand_types[j].bitfield.anysize)
1776 continue;
1777
1778 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1779 {
1780 match = 0;
1781 break;
1782 }
1783
1784 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1785 {
1786 match = 0;
1787 break;
1788 }
1789 }
1790
891edac4 1791 if (match)
5c07affc 1792 return match;
891edac4
L		 1793 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1794 {
1795mismatch:
86e026a4 1796 i.error = operand_size_mismatch;
891edac4
L		 1797 return 0;
1798 }
5c07affc
L		 1799
1800 /* Check reverse. */
9c2799c2 1801 gas_assert (i.operands == 2);
5c07affc
L		 1802
1803 match = 1;
1804 for (j = 0; j < 2; j++)
1805 {
1806 if (t->operand_types[j].bitfield.acc
1807 && !match_reg_size (t, j ? 0 : 1))
891edac4 1808 goto mismatch;
5c07affc
L		 1809
1810 if (i.types[j].bitfield.mem
1811 && !match_mem_size (t, j ? 0 : 1))
891edac4 1812 goto mismatch;
5c07affc
L		 1813 }
1814
1815 return match;
1816}
1817
c6fb90c8 1818static INLINE int
40fb9820
L		 1819operand_type_match (i386_operand_type overlap,
1820 i386_operand_type given)
1821{
1822 i386_operand_type temp = overlap;
1823
1824 temp.bitfield.jumpabsolute = 0;
7d5e4556 1825 temp.bitfield.unspecified = 0;
5c07affc
L		 1826 temp.bitfield.byte = 0;
1827 temp.bitfield.word = 0;
1828 temp.bitfield.dword = 0;
1829 temp.bitfield.fword = 0;
1830 temp.bitfield.qword = 0;
1831 temp.bitfield.tbyte = 0;
1832 temp.bitfield.xmmword = 0;
c0f3af97 1833 temp.bitfield.ymmword = 0;
43234a1e 1834 temp.bitfield.zmmword = 0;
0dfbf9d7 1835 if (operand_type_all_zero (&temp))
891edac4 1836 goto mismatch;
40fb9820 1837
891edac4
L		 1838 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1839 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1840 return 1;
1841
1842mismatch:
a65babc9 1843 i.error = operand_type_mismatch;
891edac4 1844 return 0;
40fb9820
L		 1845}
1846
7d5e4556 1847/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1848 unless the expected operand type register overlap is null.
1849 Note that Acc in a template matches every size of reg. */
1850
c6fb90c8 1851static INLINE int
40fb9820
L		 1852operand_type_register_match (i386_operand_type m0,
1853 i386_operand_type g0,
1854 i386_operand_type t0,
1855 i386_operand_type m1,
1856 i386_operand_type g1,
1857 i386_operand_type t1)
1858{
1859 if (!operand_type_check (g0, reg))
1860 return 1;
1861
1862 if (!operand_type_check (g1, reg))
1863 return 1;
1864
1865 if (g0.bitfield.reg8 == g1.bitfield.reg8
1866 && g0.bitfield.reg16 == g1.bitfield.reg16
1867 && g0.bitfield.reg32 == g1.bitfield.reg32
1868 && g0.bitfield.reg64 == g1.bitfield.reg64)
1869 return 1;
1870
1871 if (m0.bitfield.acc)
1872 {
1873 t0.bitfield.reg8 = 1;
1874 t0.bitfield.reg16 = 1;
1875 t0.bitfield.reg32 = 1;
1876 t0.bitfield.reg64 = 1;
1877 }
1878
1879 if (m1.bitfield.acc)
1880 {
1881 t1.bitfield.reg8 = 1;
1882 t1.bitfield.reg16 = 1;
1883 t1.bitfield.reg32 = 1;
1884 t1.bitfield.reg64 = 1;
1885 }
1886
891edac4
L		 1887 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1888 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1889 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1890 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1891 return 1;
1892
a65babc9 1893 i.error = register_type_mismatch;
891edac4
L		 1894
1895 return 0;
40fb9820
L		 1896}
1897
4c692bc7
JB		 1898static INLINE unsigned int
1899register_number (const reg_entry *r)
1900{
1901 unsigned int nr = r->reg_num;
1902
1903 if (r->reg_flags & RegRex)
1904 nr += 8;
1905
200cbe0f
L		 1906 if (r->reg_flags & RegVRex)
1907 nr += 16;
1908
4c692bc7
JB		 1909 return nr;
1910}
1911
252b5132 1912static INLINE unsigned int
40fb9820 1913mode_from_disp_size (i386_operand_type t)
252b5132 1914{
43234a1e 1915 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1916 return 1;
1917 else if (t.bitfield.disp16
1918 || t.bitfield.disp32
1919 || t.bitfield.disp32s)
1920 return 2;
1921 else
1922 return 0;
252b5132
RH		 1923}
1924
1925static INLINE int
65879393 1926fits_in_signed_byte (addressT num)
252b5132 1927{
65879393 1928 return num + 0x80 <= 0xff;
47926f60 1929}
252b5132
RH		 1930
1931static INLINE int
65879393 1932fits_in_unsigned_byte (addressT num)
252b5132 1933{
65879393 1934 return num <= 0xff;
47926f60 1935}
252b5132
RH		 1936
1937static INLINE int
65879393 1938fits_in_unsigned_word (addressT num)
252b5132 1939{
65879393 1940 return num <= 0xffff;
47926f60 1941}
252b5132
RH		 1942
1943static INLINE int
65879393 1944fits_in_signed_word (addressT num)
252b5132 1945{
65879393 1946 return num + 0x8000 <= 0xffff;
47926f60 1947}
2a962e6d 1948
3e73aa7c 1949static INLINE int
65879393 1950fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1951{
1952#ifndef BFD64
1953 return 1;
1954#else
65879393 1955 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1956#endif
1957} /* fits_in_signed_long() */
2a962e6d 1958
3e73aa7c 1959static INLINE int
65879393 1960fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1961{
1962#ifndef BFD64
1963 return 1;
1964#else
65879393 1965 return num <= 0xffffffff;
3e73aa7c
JH		 1966#endif
1967} /* fits_in_unsigned_long() */
252b5132 1968
43234a1e
L		 1969static INLINE int
1970fits_in_vec_disp8 (offsetT num)
1971{
1972 int shift = i.memshift;
1973 unsigned int mask;
1974
1975 if (shift == -1)
1976 abort ();
1977
1978 mask = (1 << shift) - 1;
1979
1980 /* Return 0 if NUM isn't properly aligned. */
1981 if ((num & mask))
1982 return 0;
1983
1984 /* Check if NUM will fit in 8bit after shift. */
1985 return fits_in_signed_byte (num >> shift);
1986}
1987
a683cc34
SP		 1988static INLINE int
1989fits_in_imm4 (offsetT num)
1990{
1991 return (num & 0xf) == num;
1992}
1993
40fb9820 1994static i386_operand_type
e3bb37b5 1995smallest_imm_type (offsetT num)
252b5132 1996{
40fb9820 1997 i386_operand_type t;
7ab9ffdd 1998
0dfbf9d7 1999 operand_type_set (&t, 0);
40fb9820
L		 2000 t.bitfield.imm64 = 1;
2001
2002 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2003 {
2004 /* This code is disabled on the 486 because all the Imm1 forms
2005 in the opcode table are slower on the i486. They're the
2006 versions with the implicitly specified single-position
2007 displacement, which has another syntax if you really want to
2008 use that form. */
40fb9820
L		 2009 t.bitfield.imm1 = 1;
2010 t.bitfield.imm8 = 1;
2011 t.bitfield.imm8s = 1;
2012 t.bitfield.imm16 = 1;
2013 t.bitfield.imm32 = 1;
2014 t.bitfield.imm32s = 1;
2015 }
2016 else if (fits_in_signed_byte (num))
2017 {
2018 t.bitfield.imm8 = 1;
2019 t.bitfield.imm8s = 1;
2020 t.bitfield.imm16 = 1;
2021 t.bitfield.imm32 = 1;
2022 t.bitfield.imm32s = 1;
2023 }
2024 else if (fits_in_unsigned_byte (num))
2025 {
2026 t.bitfield.imm8 = 1;
2027 t.bitfield.imm16 = 1;
2028 t.bitfield.imm32 = 1;
2029 t.bitfield.imm32s = 1;
2030 }
2031 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2032 {
2033 t.bitfield.imm16 = 1;
2034 t.bitfield.imm32 = 1;
2035 t.bitfield.imm32s = 1;
2036 }
2037 else if (fits_in_signed_long (num))
2038 {
2039 t.bitfield.imm32 = 1;
2040 t.bitfield.imm32s = 1;
2041 }
2042 else if (fits_in_unsigned_long (num))
2043 t.bitfield.imm32 = 1;
2044
2045 return t;
47926f60 2046}
252b5132 2047
847f7ad4 2048static offsetT
e3bb37b5 2049offset_in_range (offsetT val, int size)
847f7ad4 2050{
508866be 2051 addressT mask;
ba2adb93 2052
847f7ad4
AM		 2053 switch (size)
2054 {
508866be
L		 2055 case 1: mask = ((addressT) 1 << 8) - 1; break;
2056 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2057 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2058#ifdef BFD64
2059 case 8: mask = ((addressT) 2 << 63) - 1; break;
2060#endif
47926f60 2061 default: abort ();
847f7ad4
AM		 2062 }
2063
9de868bf
L		 2064#ifdef BFD64
2065 /* If BFD64, sign extend val for 32bit address mode. */
2066 if (flag_code != CODE_64BIT
2067 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2068 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2069 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2070#endif
ba2adb93 2071
47926f60 2072 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2073 {
2074 char buf1[40], buf2[40];
2075
2076 sprint_value (buf1, val);
2077 sprint_value (buf2, val & mask);
2078 as_warn (_("%s shortened to %s"), buf1, buf2);
2079 }
2080 return val & mask;
2081}
2082
c32fa91d
L		 2083enum PREFIX_GROUP
2084{
2085 PREFIX_EXIST = 0,
2086 PREFIX_LOCK,
2087 PREFIX_REP,
2088 PREFIX_OTHER
2089};
2090
2091/* Returns
2092 a. PREFIX_EXIST if attempting to add a prefix where one from the
2093 same class already exists.
2094 b. PREFIX_LOCK if lock prefix is added.
2095 c. PREFIX_REP if rep/repne prefix is added.
2096 d. PREFIX_OTHER if other prefix is added.
2097 */
2098
2099static enum PREFIX_GROUP
e3bb37b5 2100add_prefix (unsigned int prefix)
252b5132 2101{
c32fa91d 2102 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2103 unsigned int q;
252b5132 2104
29b0f896
AM		 2105 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2106 && flag_code == CODE_64BIT)
b1905489 2107 {
161a04f6
L		 2108 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2109 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2110 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2111 ret = PREFIX_EXIST;
b1905489
JB		 2112 q = REX_PREFIX;
2113 }
3e73aa7c 2114 else
b1905489
JB		 2115 {
2116 switch (prefix)
2117 {
2118 default:
2119 abort ();
2120
2121 case CS_PREFIX_OPCODE:
2122 case DS_PREFIX_OPCODE:
2123 case ES_PREFIX_OPCODE:
2124 case FS_PREFIX_OPCODE:
2125 case GS_PREFIX_OPCODE:
2126 case SS_PREFIX_OPCODE:
2127 q = SEG_PREFIX;
2128 break;
2129
2130 case REPNE_PREFIX_OPCODE:
2131 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2132 q = REP_PREFIX;
2133 ret = PREFIX_REP;
2134 break;
2135
b1905489 2136 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2137 q = LOCK_PREFIX;
2138 ret = PREFIX_LOCK;
b1905489
JB		 2139 break;
2140
2141 case FWAIT_OPCODE:
2142 q = WAIT_PREFIX;
2143 break;
2144
2145 case ADDR_PREFIX_OPCODE:
2146 q = ADDR_PREFIX;
2147 break;
2148
2149 case DATA_PREFIX_OPCODE:
2150 q = DATA_PREFIX;
2151 break;
2152 }
2153 if (i.prefix[q] != 0)
c32fa91d 2154 ret = PREFIX_EXIST;
b1905489 2155 }
252b5132 2156
b1905489 2157 if (ret)
252b5132 2158 {
b1905489
JB		 2159 if (!i.prefix[q])
2160 ++i.prefixes;
2161 i.prefix[q] |= prefix;
252b5132 2162 }
b1905489
JB		 2163 else
2164 as_bad (_("same type of prefix used twice"));
252b5132 2165
252b5132
RH		 2166 return ret;
2167}
2168
2169static void
78f12dd3 2170update_code_flag (int value, int check)
eecb386c 2171{
78f12dd3
L		 2172 PRINTF_LIKE ((*as_error));
2173
1e9cc1c2 2174 flag_code = (enum flag_code) value;
40fb9820
L		 2175 if (flag_code == CODE_64BIT)
2176 {
2177 cpu_arch_flags.bitfield.cpu64 = 1;
2178 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2179 }
2180 else
2181 {
2182 cpu_arch_flags.bitfield.cpu64 = 0;
2183 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2184 }
2185 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2186 {
78f12dd3
L		 2187 if (check)
2188 as_error = as_fatal;
2189 else
2190 as_error = as_bad;
2191 (*as_error) (_("64bit mode not supported on `%s'."),
2192 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2193 }
40fb9820 2194 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2195 {
78f12dd3
L		 2196 if (check)
2197 as_error = as_fatal;
2198 else
2199 as_error = as_bad;
2200 (*as_error) (_("32bit mode not supported on `%s'."),
2201 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2202 }
eecb386c
AM		 2203 stackop_size = '\0';
2204}
2205
78f12dd3
L		 2206static void
2207set_code_flag (int value)
2208{
2209 update_code_flag (value, 0);
2210}
2211
eecb386c 2212static void
e3bb37b5 2213set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2214{
1e9cc1c2 2215 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2216 if (flag_code != CODE_16BIT)
2217 abort ();
2218 cpu_arch_flags.bitfield.cpu64 = 0;
2219 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2220 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2221}
2222
2223static void
e3bb37b5 2224set_intel_syntax (int syntax_flag)
252b5132
RH		 2225{
2226 /* Find out if register prefixing is specified. */
2227 int ask_naked_reg = 0;
2228
2229 SKIP_WHITESPACE ();
29b0f896 2230 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2231 {
d02603dc
NC		 2232 char *string;
2233 int e = get_symbol_name (&string);
252b5132 2234
47926f60 2235 if (strcmp (string, "prefix") == 0)
252b5132 2236 ask_naked_reg = 1;
47926f60 2237 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2238 ask_naked_reg = -1;
2239 else
d0b47220 2240 as_bad (_("bad argument to syntax directive."));
d02603dc 2241 (void) restore_line_pointer (e);
252b5132
RH		 2242 }
2243 demand_empty_rest_of_line ();
c3332e24 2244
252b5132
RH		 2245 intel_syntax = syntax_flag;
2246
2247 if (ask_naked_reg == 0)
f86103b7
AM		 2248 allow_naked_reg = (intel_syntax
2249 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2250 else
2251 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2252
ee86248c 2253 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2254
e4a3b5a4 2255 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2256 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2257 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2258}
2259
1efbbeb4
L		 2260static void
2261set_intel_mnemonic (int mnemonic_flag)
2262{
e1d4d893 2263 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2264}
2265
db51cc60
L		 2266static void
2267set_allow_index_reg (int flag)
2268{
2269 allow_index_reg = flag;
2270}
2271
cb19c032 2272static void
7bab8ab5 2273set_check (int what)
cb19c032 2274{
7bab8ab5
JB		 2275 enum check_kind *kind;
2276 const char *str;
2277
2278 if (what)
2279 {
2280 kind = &operand_check;
2281 str = "operand";
2282 }
2283 else
2284 {
2285 kind = &sse_check;
2286 str = "sse";
2287 }
2288
cb19c032
L		 2289 SKIP_WHITESPACE ();
2290
2291 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2292 {
d02603dc
NC		 2293 char *string;
2294 int e = get_symbol_name (&string);
cb19c032
L		 2295
2296 if (strcmp (string, "none") == 0)
7bab8ab5 2297 *kind = check_none;
cb19c032 2298 else if (strcmp (string, "warning") == 0)
7bab8ab5 2299 *kind = check_warning;
cb19c032 2300 else if (strcmp (string, "error") == 0)
7bab8ab5 2301 *kind = check_error;
cb19c032 2302 else
7bab8ab5 2303 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2304 (void) restore_line_pointer (e);
cb19c032
L		 2305 }
2306 else
7bab8ab5 2307 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2308
2309 demand_empty_rest_of_line ();
2310}
2311
8a9036a4
L		 2312static void
2313check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2314 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2315{
2316#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2317 static const char *arch;
2318
2319 /* Intel LIOM is only supported on ELF. */
2320 if (!IS_ELF)
2321 return;
2322
2323 if (!arch)
2324 {
2325 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2326 use default_arch. */
2327 arch = cpu_arch_name;
2328 if (!arch)
2329 arch = default_arch;
2330 }
2331
81486035
L		 2332 /* If we are targeting Intel MCU, we must enable it. */
2333 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2334 || new_flag.bitfield.cpuiamcu)
2335 return;
2336
3632d14b 2337 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2338 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2339 || new_flag.bitfield.cpul1om)
8a9036a4 2340 return;
76ba9986 2341
7a9068fe
L		 2342 /* If we are targeting Intel K1OM, we must enable it. */
2343 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2344 || new_flag.bitfield.cpuk1om)
2345 return;
2346
8a9036a4
L		 2347 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2348#endif
2349}
2350
e413e4e9 2351static void
e3bb37b5 2352set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2353{
47926f60 2354 SKIP_WHITESPACE ();
e413e4e9 2355
29b0f896 2356 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2357 {
d02603dc
NC		 2358 char *string;
2359 int e = get_symbol_name (&string);
91d6fa6a 2360 unsigned int j;
40fb9820 2361 i386_cpu_flags flags;
e413e4e9 2362
91d6fa6a 2363 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2364 {
91d6fa6a 2365 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2366 {
91d6fa6a 2367 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2368
5c6af06e
JB		 2369 if (*string != '.')
2370 {
91d6fa6a 2371 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2372 cpu_sub_arch_name = NULL;
91d6fa6a 2373 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2374 if (flag_code == CODE_64BIT)
2375 {
2376 cpu_arch_flags.bitfield.cpu64 = 1;
2377 cpu_arch_flags.bitfield.cpuno64 = 0;
2378 }
2379 else
2380 {
2381 cpu_arch_flags.bitfield.cpu64 = 0;
2382 cpu_arch_flags.bitfield.cpuno64 = 1;
2383 }
91d6fa6a
NC		 2384 cpu_arch_isa = cpu_arch[j].type;
2385 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2386 if (!cpu_arch_tune_set)
2387 {
2388 cpu_arch_tune = cpu_arch_isa;
2389 cpu_arch_tune_flags = cpu_arch_isa_flags;
2390 }
5c6af06e
JB		 2391 break;
2392 }
40fb9820 2393
293f5f65
L		 2394 flags = cpu_flags_or (cpu_arch_flags,
2395 cpu_arch[j].flags);
81486035
L		 2396
2397 if (!valid_iamcu_cpu_flags (&flags))
2398 as_fatal (_("`%s' isn't valid for Intel MCU"),
2399 cpu_arch[j].name);
2400 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2401 {
6305a203
L		 2402 if (cpu_sub_arch_name)
2403 {
2404 char *name = cpu_sub_arch_name;
2405 cpu_sub_arch_name = concat (name,
91d6fa6a 2406 cpu_arch[j].name,
1bf57e9f 2407 (const char *) NULL);
6305a203
L		 2408 free (name);
2409 }
2410 else
91d6fa6a 2411 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2412 cpu_arch_flags = flags;
a586129e 2413 cpu_arch_isa_flags = flags;
5c6af06e 2414 }
d02603dc 2415 (void) restore_line_pointer (e);
5c6af06e
JB		 2416 demand_empty_rest_of_line ();
2417 return;
e413e4e9
AM		 2418 }
2419 }
293f5f65
L		 2420
2421 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2422 {
2423 /* Disable an ISA entension. */
2424 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2425 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2426 {
2427 flags = cpu_flags_and_not (cpu_arch_flags,
2428 cpu_noarch[j].flags);
2429 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2430 {
2431 if (cpu_sub_arch_name)
2432 {
2433 char *name = cpu_sub_arch_name;
2434 cpu_sub_arch_name = concat (name, string,
2435 (const char *) NULL);
2436 free (name);
2437 }
2438 else
2439 cpu_sub_arch_name = xstrdup (string);
2440 cpu_arch_flags = flags;
2441 cpu_arch_isa_flags = flags;
2442 }
2443 (void) restore_line_pointer (e);
2444 demand_empty_rest_of_line ();
2445 return;
2446 }
2447
2448 j = ARRAY_SIZE (cpu_arch);
2449 }
2450
91d6fa6a 2451 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2452 as_bad (_("no such architecture: `%s'"), string);
2453
2454 *input_line_pointer = e;
2455 }
2456 else
2457 as_bad (_("missing cpu architecture"));
2458
fddf5b5b
AM		 2459 no_cond_jump_promotion = 0;
2460 if (*input_line_pointer == ','
29b0f896 2461 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2462 {
d02603dc
NC		 2463 char *string;
2464 char e;
2465
2466 ++input_line_pointer;
2467 e = get_symbol_name (&string);
fddf5b5b
AM		 2468
2469 if (strcmp (string, "nojumps") == 0)
2470 no_cond_jump_promotion = 1;
2471 else if (strcmp (string, "jumps") == 0)
2472 ;
2473 else
2474 as_bad (_("no such architecture modifier: `%s'"), string);
2475
d02603dc 2476 (void) restore_line_pointer (e);
fddf5b5b
AM		 2477 }
2478
e413e4e9
AM		 2479 demand_empty_rest_of_line ();
2480}
2481
8a9036a4
L		 2482enum bfd_architecture
2483i386_arch (void)
2484{
3632d14b 2485 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2486 {
2487 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2488 || flag_code != CODE_64BIT)
2489 as_fatal (_("Intel L1OM is 64bit ELF only"));
2490 return bfd_arch_l1om;
2491 }
7a9068fe
L		 2492 else if (cpu_arch_isa == PROCESSOR_K1OM)
2493 {
2494 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2495 || flag_code != CODE_64BIT)
2496 as_fatal (_("Intel K1OM is 64bit ELF only"));
2497 return bfd_arch_k1om;
2498 }
81486035
L		 2499 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2500 {
2501 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2502 || flag_code == CODE_64BIT)
2503 as_fatal (_("Intel MCU is 32bit ELF only"));
2504 return bfd_arch_iamcu;
2505 }
8a9036a4
L		 2506 else
2507 return bfd_arch_i386;
2508}
2509
b9d79e03 2510unsigned long
7016a5d5 2511i386_mach (void)
b9d79e03 2512{
351f65ca 2513 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2514 {
3632d14b 2515 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2516 {
351f65ca
L		 2517 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2518 || default_arch[6] != '\0')
8a9036a4
L		 2519 as_fatal (_("Intel L1OM is 64bit ELF only"));
2520 return bfd_mach_l1om;
2521 }
7a9068fe
L		 2522 else if (cpu_arch_isa == PROCESSOR_K1OM)
2523 {
2524 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2525 || default_arch[6] != '\0')
2526 as_fatal (_("Intel K1OM is 64bit ELF only"));
2527 return bfd_mach_k1om;
2528 }
351f65ca 2529 else if (default_arch[6] == '\0')
8a9036a4 2530 return bfd_mach_x86_64;
351f65ca
L		 2531 else
2532 return bfd_mach_x64_32;
8a9036a4 2533 }
5197d474
L		 2534 else if (!strcmp (default_arch, "i386")
2535 || !strcmp (default_arch, "iamcu"))
81486035
L		 2536 {
2537 if (cpu_arch_isa == PROCESSOR_IAMCU)
2538 {
2539 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2540 as_fatal (_("Intel MCU is 32bit ELF only"));
2541 return bfd_mach_i386_iamcu;
2542 }
2543 else
2544 return bfd_mach_i386_i386;
2545 }
b9d79e03 2546 else
2b5d6a91 2547 as_fatal (_("unknown architecture"));
b9d79e03 2548}
b9d79e03 2549\f
252b5132 2550void
7016a5d5 2551md_begin (void)
252b5132
RH		 2552{
2553 const char *hash_err;
2554
47926f60 2555 /* Initialize op_hash hash table. */
252b5132
RH		 2556 op_hash = hash_new ();
2557
2558 {
d3ce72d0 2559 const insn_template *optab;
29b0f896 2560 templates *core_optab;
252b5132 2561
47926f60
KH		 2562 /* Setup for loop. */
2563 optab = i386_optab;
add39d23 2564 core_optab = XNEW (templates);
252b5132
RH		 2565 core_optab->start = optab;
2566
2567 while (1)
2568 {
2569 ++optab;
2570 if (optab->name == NULL
2571 || strcmp (optab->name, (optab - 1)->name) != 0)
2572 {
2573 /* different name --> ship out current template list;
47926f60 2574 add to hash table; & begin anew. */
252b5132
RH		 2575 core_optab->end = optab;
2576 hash_err = hash_insert (op_hash,
2577 (optab - 1)->name,
5a49b8ac 2578 (void *) core_optab);
252b5132
RH		 2579 if (hash_err)
2580 {
b37df7c4 2581 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2582 (optab - 1)->name,
2583 hash_err);
2584 }
2585 if (optab->name == NULL)
2586 break;
add39d23 2587 core_optab = XNEW (templates);
252b5132
RH		 2588 core_optab->start = optab;
2589 }
2590 }
2591 }
2592
47926f60 2593 /* Initialize reg_hash hash table. */
252b5132
RH		 2594 reg_hash = hash_new ();
2595 {
29b0f896 2596 const reg_entry *regtab;
c3fe08fa 2597 unsigned int regtab_size = i386_regtab_size;
252b5132 2598
c3fe08fa 2599 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2600 {
5a49b8ac 2601 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2602 if (hash_err)
b37df7c4 2603 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2604 regtab->reg_name,
2605 hash_err);
252b5132
RH		 2606 }
2607 }
2608
47926f60 2609 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2610 {
29b0f896
AM		 2611 int c;
2612 char *p;
252b5132
RH		 2613
2614 for (c = 0; c < 256; c++)
2615 {
3882b010 2616 if (ISDIGIT (c))
252b5132
RH		 2617 {
2618 digit_chars[c] = c;
2619 mnemonic_chars[c] = c;
2620 register_chars[c] = c;
2621 operand_chars[c] = c;
2622 }
3882b010 2623 else if (ISLOWER (c))
252b5132
RH		 2624 {
2625 mnemonic_chars[c] = c;
2626 register_chars[c] = c;
2627 operand_chars[c] = c;
2628 }
3882b010 2629 else if (ISUPPER (c))
252b5132 2630 {
3882b010 2631 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2632 register_chars[c] = mnemonic_chars[c];
2633 operand_chars[c] = c;
2634 }
43234a1e
L		 2635 else if (c == '{' || c == '}')
2636 operand_chars[c] = c;
252b5132 2637
3882b010 2638 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2639 identifier_chars[c] = c;
2640 else if (c >= 128)
2641 {
2642 identifier_chars[c] = c;
2643 operand_chars[c] = c;
2644 }
2645 }
2646
2647#ifdef LEX_AT
2648 identifier_chars['@'] = '@';
32137342
NC		 2649#endif
2650#ifdef LEX_QM
2651 identifier_chars['?'] = '?';
2652 operand_chars['?'] = '?';
252b5132 2653#endif
252b5132 2654 digit_chars['-'] = '-';
c0f3af97 2655 mnemonic_chars['_'] = '_';
791fe849 2656 mnemonic_chars['-'] = '-';
0003779b 2657 mnemonic_chars['.'] = '.';
252b5132
RH		 2658 identifier_chars['_'] = '_';
2659 identifier_chars['.'] = '.';
2660
2661 for (p = operand_special_chars; *p != '\0'; p++)
2662 operand_chars[(unsigned char) *p] = *p;
2663 }
2664
a4447b93
RH		 2665 if (flag_code == CODE_64BIT)
2666 {
ca19b261
KT		 2667#if defined (OBJ_COFF) && defined (TE_PE)
2668 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2669 ? 32 : 16);
2670#else
a4447b93 2671 x86_dwarf2_return_column = 16;
ca19b261 2672#endif
61ff971f 2673 x86_cie_data_alignment = -8;
a4447b93
RH		 2674 }
2675 else
2676 {
2677 x86_dwarf2_return_column = 8;
2678 x86_cie_data_alignment = -4;
2679 }
252b5132
RH		 2680}
2681
2682void
e3bb37b5 2683i386_print_statistics (FILE *file)
252b5132
RH		 2684{
2685 hash_print_statistics (file, "i386 opcode", op_hash);
2686 hash_print_statistics (file, "i386 register", reg_hash);
2687}
2688\f
252b5132
RH		 2689#ifdef DEBUG386
2690
ce8a8b2f 2691/* Debugging routines for md_assemble. */
d3ce72d0 2692static void pte (insn_template *);
40fb9820 2693static void pt (i386_operand_type);
e3bb37b5
L		 2694static void pe (expressionS *);
2695static void ps (symbolS *);
252b5132
RH		 2696
2697static void
e3bb37b5 2698pi (char *line, i386_insn *x)
252b5132 2699{
09137c09 2700 unsigned int j;
252b5132
RH		 2701
2702 fprintf (stdout, "%s: template ", line);
2703 pte (&x->tm);
09f131f2
JH		 2704 fprintf (stdout, " address: base %s index %s scale %x\n",
2705 x->base_reg ? x->base_reg->reg_name : "none",
2706 x->index_reg ? x->index_reg->reg_name : "none",
2707 x->log2_scale_factor);
2708 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2709 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2710 fprintf (stdout, " sib: base %x index %x scale %x\n",
2711 x->sib.base, x->sib.index, x->sib.scale);
2712 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2713 (x->rex & REX_W) != 0,
2714 (x->rex & REX_R) != 0,
2715 (x->rex & REX_X) != 0,
2716 (x->rex & REX_B) != 0);
09137c09 2717 for (j = 0; j < x->operands; j++)
252b5132 2718 {
09137c09
SP		 2719 fprintf (stdout, " #%d: ", j + 1);
2720 pt (x->types[j]);
252b5132 2721 fprintf (stdout, "\n");
09137c09
SP		 2722 if (x->types[j].bitfield.reg8
2723 || x->types[j].bitfield.reg16
2724 || x->types[j].bitfield.reg32
2725 || x->types[j].bitfield.reg64
2726 || x->types[j].bitfield.regmmx
2727 || x->types[j].bitfield.regxmm
2728 || x->types[j].bitfield.regymm
43234a1e 2729 || x->types[j].bitfield.regzmm
09137c09
SP		 2730 || x->types[j].bitfield.sreg2
2731 || x->types[j].bitfield.sreg3
2732 || x->types[j].bitfield.control
2733 || x->types[j].bitfield.debug
2734 || x->types[j].bitfield.test)
2735 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2736 if (operand_type_check (x->types[j], imm))
2737 pe (x->op[j].imms);
2738 if (operand_type_check (x->types[j], disp))
2739 pe (x->op[j].disps);
252b5132
RH		 2740 }
2741}
2742
2743static void
d3ce72d0 2744pte (insn_template *t)
252b5132 2745{
09137c09 2746 unsigned int j;
252b5132 2747 fprintf (stdout, " %d operands ", t->operands);
47926f60 2748 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2749 if (t->extension_opcode != None)
2750 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2751 if (t->opcode_modifier.d)
252b5132 2752 fprintf (stdout, "D");
40fb9820 2753 if (t->opcode_modifier.w)
252b5132
RH		 2754 fprintf (stdout, "W");
2755 fprintf (stdout, "\n");
09137c09 2756 for (j = 0; j < t->operands; j++)
252b5132 2757 {
09137c09
SP		 2758 fprintf (stdout, " #%d type ", j + 1);
2759 pt (t->operand_types[j]);
252b5132
RH		 2760 fprintf (stdout, "\n");
2761 }
2762}
2763
2764static void
e3bb37b5 2765pe (expressionS *e)
252b5132 2766{
24eab124 2767 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2768 fprintf (stdout, " add_number %ld (%lx)\n",
2769 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2770 if (e->X_add_symbol)
2771 {
2772 fprintf (stdout, " add_symbol ");
2773 ps (e->X_add_symbol);
2774 fprintf (stdout, "\n");
2775 }
2776 if (e->X_op_symbol)
2777 {
2778 fprintf (stdout, " op_symbol ");
2779 ps (e->X_op_symbol);
2780 fprintf (stdout, "\n");
2781 }
2782}
2783
2784static void
e3bb37b5 2785ps (symbolS *s)
252b5132
RH		 2786{
2787 fprintf (stdout, "%s type %s%s",
2788 S_GET_NAME (s),
2789 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2790 segment_name (S_GET_SEGMENT (s)));
2791}
2792
7b81dfbb 2793static struct type_name
252b5132 2794 {
40fb9820
L		 2795 i386_operand_type mask;
2796 const char *name;
252b5132 2797 }
7b81dfbb 2798const type_names[] =
252b5132 2799{
40fb9820
L		 2800 { OPERAND_TYPE_REG8, "r8" },
2801 { OPERAND_TYPE_REG16, "r16" },
2802 { OPERAND_TYPE_REG32, "r32" },
2803 { OPERAND_TYPE_REG64, "r64" },
2804 { OPERAND_TYPE_IMM8, "i8" },
2805 { OPERAND_TYPE_IMM8, "i8s" },
2806 { OPERAND_TYPE_IMM16, "i16" },
2807 { OPERAND_TYPE_IMM32, "i32" },
2808 { OPERAND_TYPE_IMM32S, "i32s" },
2809 { OPERAND_TYPE_IMM64, "i64" },
2810 { OPERAND_TYPE_IMM1, "i1" },
2811 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2812 { OPERAND_TYPE_DISP8, "d8" },
2813 { OPERAND_TYPE_DISP16, "d16" },
2814 { OPERAND_TYPE_DISP32, "d32" },
2815 { OPERAND_TYPE_DISP32S, "d32s" },
2816 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2817 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2818 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2819 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2820 { OPERAND_TYPE_CONTROL, "control reg" },
2821 { OPERAND_TYPE_TEST, "test reg" },
2822 { OPERAND_TYPE_DEBUG, "debug reg" },
2823 { OPERAND_TYPE_FLOATREG, "FReg" },
2824 { OPERAND_TYPE_FLOATACC, "FAcc" },
2825 { OPERAND_TYPE_SREG2, "SReg2" },
2826 { OPERAND_TYPE_SREG3, "SReg3" },
2827 { OPERAND_TYPE_ACC, "Acc" },
2828 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2829 { OPERAND_TYPE_REGMMX, "rMMX" },
2830 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2831 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2832 { OPERAND_TYPE_REGZMM, "rZMM" },
2833 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2834 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2835};
2836
2837static void
40fb9820 2838pt (i386_operand_type t)
252b5132 2839{
40fb9820 2840 unsigned int j;
c6fb90c8 2841 i386_operand_type a;
252b5132 2842
40fb9820 2843 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2844 {
2845 a = operand_type_and (t, type_names[j].mask);
0349dc08 2846 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2847 fprintf (stdout, "%s, ", type_names[j].name);
2848 }
252b5132
RH		 2849 fflush (stdout);
2850}
2851
2852#endif /* DEBUG386 */
2853\f
252b5132 2854static bfd_reloc_code_real_type
3956db08 2855reloc (unsigned int size,
64e74474
AM		 2856 int pcrel,
2857 int sign,
2858 bfd_reloc_code_real_type other)
252b5132 2859{
47926f60 2860 if (other != NO_RELOC)
3956db08 2861 {
91d6fa6a 2862 reloc_howto_type *rel;
3956db08
JB		 2863
2864 if (size == 8)
2865 switch (other)
2866 {
64e74474
AM		 2867 case BFD_RELOC_X86_64_GOT32:
2868 return BFD_RELOC_X86_64_GOT64;
2869 break;
553d1284
L		 2870 case BFD_RELOC_X86_64_GOTPLT64:
2871 return BFD_RELOC_X86_64_GOTPLT64;
2872 break;
64e74474
AM		 2873 case BFD_RELOC_X86_64_PLTOFF64:
2874 return BFD_RELOC_X86_64_PLTOFF64;
2875 break;
2876 case BFD_RELOC_X86_64_GOTPC32:
2877 other = BFD_RELOC_X86_64_GOTPC64;
2878 break;
2879 case BFD_RELOC_X86_64_GOTPCREL:
2880 other = BFD_RELOC_X86_64_GOTPCREL64;
2881 break;
2882 case BFD_RELOC_X86_64_TPOFF32:
2883 other = BFD_RELOC_X86_64_TPOFF64;
2884 break;
2885 case BFD_RELOC_X86_64_DTPOFF32:
2886 other = BFD_RELOC_X86_64_DTPOFF64;
2887 break;
2888 default:
2889 break;
3956db08 2890 }
e05278af 2891
8ce3d284 2892#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2893 if (other == BFD_RELOC_SIZE32)
2894 {
2895 if (size == 8)
1ab668bf 2896 other = BFD_RELOC_SIZE64;
8fd4256d 2897 if (pcrel)
1ab668bf
AM		 2898 {
2899 as_bad (_("there are no pc-relative size relocations"));
2900 return NO_RELOC;
2901 }
8fd4256d 2902 }
8ce3d284 2903#endif
8fd4256d 2904
e05278af 2905 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2906 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2907 sign = -1;
2908
91d6fa6a
NC		 2909 rel = bfd_reloc_type_lookup (stdoutput, other);
2910 if (!rel)
3956db08 2911 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2912 else if (size != bfd_get_reloc_size (rel))
3956db08 2913 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2914 bfd_get_reloc_size (rel),
3956db08 2915 size);
91d6fa6a 2916 else if (pcrel && !rel->pc_relative)
3956db08 2917 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2918 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2919 && !sign)
91d6fa6a 2920 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2921 && sign > 0))
3956db08
JB		 2922 as_bad (_("relocated field and relocation type differ in signedness"));
2923 else
2924 return other;
2925 return NO_RELOC;
2926 }
252b5132
RH		 2927
2928 if (pcrel)
2929 {
3e73aa7c 2930 if (!sign)
3956db08 2931 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2932 switch (size)
2933 {
2934 case 1: return BFD_RELOC_8_PCREL;
2935 case 2: return BFD_RELOC_16_PCREL;
d258b828 2936 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2937 case 8: return BFD_RELOC_64_PCREL;
252b5132 2938 }
3956db08 2939 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2940 }
2941 else
2942 {
3956db08 2943 if (sign > 0)
e5cb08ac 2944 switch (size)
3e73aa7c
JH		 2945 {
2946 case 4: return BFD_RELOC_X86_64_32S;
2947 }
2948 else
2949 switch (size)
2950 {
2951 case 1: return BFD_RELOC_8;
2952 case 2: return BFD_RELOC_16;
2953 case 4: return BFD_RELOC_32;
2954 case 8: return BFD_RELOC_64;
2955 }
3956db08
JB		 2956 as_bad (_("cannot do %s %u byte relocation"),
2957 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2958 }
2959
0cc9e1d3 2960 return NO_RELOC;
252b5132
RH		 2961}
2962
47926f60
KH		 2963/* Here we decide which fixups can be adjusted to make them relative to
2964 the beginning of the section instead of the symbol. Basically we need
2965 to make sure that the dynamic relocations are done correctly, so in
2966 some cases we force the original symbol to be used. */
2967
252b5132 2968int
e3bb37b5 2969tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2970{
6d249963 2971#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2972 if (!IS_ELF)
31312f95
AM		 2973 return 1;
2974
a161fe53
AM		 2975 /* Don't adjust pc-relative references to merge sections in 64-bit
2976 mode. */
2977 if (use_rela_relocations
2978 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2979 && fixP->fx_pcrel)
252b5132 2980 return 0;
31312f95 2981
8d01d9a9
AJ		 2982 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2983 and changed later by validate_fix. */
2984 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2985 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2986 return 0;
2987
8fd4256d
L		 2988 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2989 for size relocations. */
2990 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2991 || fixP->fx_r_type == BFD_RELOC_SIZE64
2992 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2993 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2994 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 2995 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 2996 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2997 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2998 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2999 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3000 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3001 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3002 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3003 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3004 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3005 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3006 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3007 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3008 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3009 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3010 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3011 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3012 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3013 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3014 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3015 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3016 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3017 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3018 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3019 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3020 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3021 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3022 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3023 return 0;
31312f95 3024#endif
252b5132
RH		 3025 return 1;
3026}
252b5132 3027
b4cac588 3028static int
e3bb37b5 3029intel_float_operand (const char *mnemonic)
252b5132 3030{
9306ca4a
JB		 3031 /* Note that the value returned is meaningful only for opcodes with (memory)
3032 operands, hence the code here is free to improperly handle opcodes that
3033 have no operands (for better performance and smaller code). */
3034
3035 if (mnemonic[0] != 'f')
3036 return 0; /* non-math */
3037
3038 switch (mnemonic[1])
3039 {
3040 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3041 the fs segment override prefix not currently handled because no
3042 call path can make opcodes without operands get here */
3043 case 'i':
3044 return 2 /* integer op */;
3045 case 'l':
3046 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3047 return 3; /* fldcw/fldenv */
3048 break;
3049 case 'n':
3050 if (mnemonic[2] != 'o' /* fnop */)
3051 return 3; /* non-waiting control op */
3052 break;
3053 case 'r':
3054 if (mnemonic[2] == 's')
3055 return 3; /* frstor/frstpm */
3056 break;
3057 case 's':
3058 if (mnemonic[2] == 'a')
3059 return 3; /* fsave */
3060 if (mnemonic[2] == 't')
3061 {
3062 switch (mnemonic[3])
3063 {
3064 case 'c': /* fstcw */
3065 case 'd': /* fstdw */
3066 case 'e': /* fstenv */
3067 case 's': /* fsts[gw] */
3068 return 3;
3069 }
3070 }
3071 break;
3072 case 'x':
3073 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3074 return 0; /* fxsave/fxrstor are not really math ops */
3075 break;
3076 }
252b5132 3077
9306ca4a 3078 return 1;
252b5132
RH		 3079}
3080
c0f3af97
L		 3081/* Build the VEX prefix. */
3082
3083static void
d3ce72d0 3084build_vex_prefix (const insn_template *t)
c0f3af97
L		 3085{
3086 unsigned int register_specifier;
3087 unsigned int implied_prefix;
3088 unsigned int vector_length;
3089
3090 /* Check register specifier. */
3091 if (i.vex.register_specifier)
43234a1e
L		 3092 {
3093 register_specifier =
3094 ~register_number (i.vex.register_specifier) & 0xf;
3095 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3096 }
c0f3af97
L		 3097 else
3098 register_specifier = 0xf;
3099
fa99fab2
L		 3100 /* Use 2-byte VEX prefix by swappping destination and source
3101 operand. */
3102 if (!i.swap_operand
3103 && i.operands == i.reg_operands
7f399153 3104 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3105 && i.tm.opcode_modifier.s
3106 && i.rex == REX_B)
3107 {
3108 unsigned int xchg = i.operands - 1;
3109 union i386_op temp_op;
3110 i386_operand_type temp_type;
3111
3112 temp_type = i.types[xchg];
3113 i.types[xchg] = i.types[0];
3114 i.types[0] = temp_type;
3115 temp_op = i.op[xchg];
3116 i.op[xchg] = i.op[0];
3117 i.op[0] = temp_op;
3118
9c2799c2 3119 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3120
3121 i.rex = REX_R;
3122 xchg = i.rm.regmem;
3123 i.rm.regmem = i.rm.reg;
3124 i.rm.reg = xchg;
3125
3126 /* Use the next insn. */
3127 i.tm = t[1];
3128 }
3129
539f890d
L		 3130 if (i.tm.opcode_modifier.vex == VEXScalar)
3131 vector_length = avxscalar;
3132 else
3133 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3134
3135 switch ((i.tm.base_opcode >> 8) & 0xff)
3136 {
3137 case 0:
3138 implied_prefix = 0;
3139 break;
3140 case DATA_PREFIX_OPCODE:
3141 implied_prefix = 1;
3142 break;
3143 case REPE_PREFIX_OPCODE:
3144 implied_prefix = 2;
3145 break;
3146 case REPNE_PREFIX_OPCODE:
3147 implied_prefix = 3;
3148 break;
3149 default:
3150 abort ();
3151 }
3152
3153 /* Use 2-byte VEX prefix if possible. */
7f399153 3154 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3155 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3156 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3157 {
3158 /* 2-byte VEX prefix. */
3159 unsigned int r;
3160
3161 i.vex.length = 2;
3162 i.vex.bytes[0] = 0xc5;
3163
3164 /* Check the REX.R bit. */
3165 r = (i.rex & REX_R) ? 0 : 1;
3166 i.vex.bytes[1] = (r << 7
3167 | register_specifier << 3
3168 | vector_length << 2
3169 | implied_prefix);
3170 }
3171 else
3172 {
3173 /* 3-byte VEX prefix. */
3174 unsigned int m, w;
3175
f88c9eb0 3176 i.vex.length = 3;
f88c9eb0 3177
7f399153 3178 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3179 {
7f399153
L		 3180 case VEX0F:
3181 m = 0x1;
80de6e00 3182 i.vex.bytes[0] = 0xc4;
7f399153
L		 3183 break;
3184 case VEX0F38:
3185 m = 0x2;
80de6e00 3186 i.vex.bytes[0] = 0xc4;
7f399153
L		 3187 break;
3188 case VEX0F3A:
3189 m = 0x3;
80de6e00 3190 i.vex.bytes[0] = 0xc4;
7f399153
L		 3191 break;
3192 case XOP08:
5dd85c99
SP		 3193 m = 0x8;
3194 i.vex.bytes[0] = 0x8f;
7f399153
L		 3195 break;
3196 case XOP09:
f88c9eb0
SP		 3197 m = 0x9;
3198 i.vex.bytes[0] = 0x8f;
7f399153
L		 3199 break;
3200 case XOP0A:
f88c9eb0
SP		 3201 m = 0xa;
3202 i.vex.bytes[0] = 0x8f;
7f399153
L		 3203 break;
3204 default:
3205 abort ();
f88c9eb0 3206 }
c0f3af97 3207
c0f3af97
L		 3208 /* The high 3 bits of the second VEX byte are 1's compliment
3209 of RXB bits from REX. */
3210 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3211
3212 /* Check the REX.W bit. */
3213 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3214 if (i.tm.opcode_modifier.vexw == VEXW1)
3215 w = 1;
c0f3af97
L		 3216
3217 i.vex.bytes[2] = (w << 7
3218 | register_specifier << 3
3219 | vector_length << 2
3220 | implied_prefix);
3221 }
3222}
3223
43234a1e
L		 3224/* Build the EVEX prefix. */
3225
3226static void
3227build_evex_prefix (void)
3228{
3229 unsigned int register_specifier;
3230 unsigned int implied_prefix;
3231 unsigned int m, w;
3232 rex_byte vrex_used = 0;
3233
3234 /* Check register specifier. */
3235 if (i.vex.register_specifier)
3236 {
3237 gas_assert ((i.vrex & REX_X) == 0);
3238
3239 register_specifier = i.vex.register_specifier->reg_num;
3240 if ((i.vex.register_specifier->reg_flags & RegRex))
3241 register_specifier += 8;
3242 /* The upper 16 registers are encoded in the fourth byte of the
3243 EVEX prefix. */
3244 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3245 i.vex.bytes[3] = 0x8;
3246 register_specifier = ~register_specifier & 0xf;
3247 }
3248 else
3249 {
3250 register_specifier = 0xf;
3251
3252 /* Encode upper 16 vector index register in the fourth byte of
3253 the EVEX prefix. */
3254 if (!(i.vrex & REX_X))
3255 i.vex.bytes[3] = 0x8;
3256 else
3257 vrex_used |= REX_X;
3258 }
3259
3260 switch ((i.tm.base_opcode >> 8) & 0xff)
3261 {
3262 case 0:
3263 implied_prefix = 0;
3264 break;
3265 case DATA_PREFIX_OPCODE:
3266 implied_prefix = 1;
3267 break;
3268 case REPE_PREFIX_OPCODE:
3269 implied_prefix = 2;
3270 break;
3271 case REPNE_PREFIX_OPCODE:
3272 implied_prefix = 3;
3273 break;
3274 default:
3275 abort ();
3276 }
3277
3278 /* 4 byte EVEX prefix. */
3279 i.vex.length = 4;
3280 i.vex.bytes[0] = 0x62;
3281
3282 /* mmmm bits. */
3283 switch (i.tm.opcode_modifier.vexopcode)
3284 {
3285 case VEX0F:
3286 m = 1;
3287 break;
3288 case VEX0F38:
3289 m = 2;
3290 break;
3291 case VEX0F3A:
3292 m = 3;
3293 break;
3294 default:
3295 abort ();
3296 break;
3297 }
3298
3299 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3300 bits from REX. */
3301 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3302
3303 /* The fifth bit of the second EVEX byte is 1's compliment of the
3304 REX_R bit in VREX. */
3305 if (!(i.vrex & REX_R))
3306 i.vex.bytes[1] |= 0x10;
3307 else
3308 vrex_used |= REX_R;
3309
3310 if ((i.reg_operands + i.imm_operands) == i.operands)
3311 {
3312 /* When all operands are registers, the REX_X bit in REX is not
3313 used. We reuse it to encode the upper 16 registers, which is
3314 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3315 as 1's compliment. */
3316 if ((i.vrex & REX_B))
3317 {
3318 vrex_used |= REX_B;
3319 i.vex.bytes[1] &= ~0x40;
3320 }
3321 }
3322
3323 /* EVEX instructions shouldn't need the REX prefix. */
3324 i.vrex &= ~vrex_used;
3325 gas_assert (i.vrex == 0);
3326
3327 /* Check the REX.W bit. */
3328 w = (i.rex & REX_W) ? 1 : 0;
3329 if (i.tm.opcode_modifier.vexw)
3330 {
3331 if (i.tm.opcode_modifier.vexw == VEXW1)
3332 w = 1;
3333 }
3334 /* If w is not set it means we are dealing with WIG instruction. */
3335 else if (!w)
3336 {
3337 if (evexwig == evexw1)
3338 w = 1;
3339 }
3340
3341 /* Encode the U bit. */
3342 implied_prefix |= 0x4;
3343
3344 /* The third byte of the EVEX prefix. */
3345 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3346
3347 /* The fourth byte of the EVEX prefix. */
3348 /* The zeroing-masking bit. */
3349 if (i.mask && i.mask->zeroing)
3350 i.vex.bytes[3] |= 0x80;
3351
3352 /* Don't always set the broadcast bit if there is no RC. */
3353 if (!i.rounding)
3354 {
3355 /* Encode the vector length. */
3356 unsigned int vec_length;
3357
3358 switch (i.tm.opcode_modifier.evex)
3359 {
3360 case EVEXLIG: /* LL' is ignored */
3361 vec_length = evexlig << 5;
3362 break;
3363 case EVEX128:
3364 vec_length = 0 << 5;
3365 break;
3366 case EVEX256:
3367 vec_length = 1 << 5;
3368 break;
3369 case EVEX512:
3370 vec_length = 2 << 5;
3371 break;
3372 default:
3373 abort ();
3374 break;
3375 }
3376 i.vex.bytes[3] |= vec_length;
3377 /* Encode the broadcast bit. */
3378 if (i.broadcast)
3379 i.vex.bytes[3] |= 0x10;
3380 }
3381 else
3382 {
3383 if (i.rounding->type != saeonly)
3384 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3385 else
d3d3c6db 3386 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3387 }
3388
3389 if (i.mask && i.mask->mask)
3390 i.vex.bytes[3] |= i.mask->mask->reg_num;
3391}
3392
65da13b5
L		 3393static void
3394process_immext (void)
3395{
3396 expressionS *exp;
3397
4c692bc7
JB		 3398 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3399 && i.operands > 0)
65da13b5 3400 {
4c692bc7
JB		 3401 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3402 with an opcode suffix which is coded in the same place as an
3403 8-bit immediate field would be.
3404 Here we check those operands and remove them afterwards. */
65da13b5
L		 3405 unsigned int x;
3406
3407 for (x = 0; x < i.operands; x++)
4c692bc7 3408 if (register_number (i.op[x].regs) != x)
65da13b5 3409 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3410 register_prefix, i.op[x].regs->reg_name, x + 1,
3411 i.tm.name);
3412
3413 i.operands = 0;
65da13b5
L		 3414 }
3415
9916071f
AP		 3416 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3417 {
3418 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3419 suffix which is coded in the same place as an 8-bit immediate
3420 field would be.
3421 Here we check those operands and remove them afterwards. */
3422 unsigned int x;
3423
3424 if (i.operands != 3)
3425 abort();
3426
3427 for (x = 0; x < 2; x++)
3428 if (register_number (i.op[x].regs) != x)
3429 goto bad_register_operand;
3430
3431 /* Check for third operand for mwaitx/monitorx insn. */
3432 if (register_number (i.op[x].regs)
3433 != (x + (i.tm.extension_opcode == 0xfb)))
3434 {
3435bad_register_operand:
3436 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3437 register_prefix, i.op[x].regs->reg_name, x+1,
3438 i.tm.name);
3439 }
3440
3441 i.operands = 0;
3442 }
3443
c0f3af97 3444 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3445 which is coded in the same place as an 8-bit immediate field
3446 would be. Here we fake an 8-bit immediate operand from the
3447 opcode suffix stored in tm.extension_opcode.
3448
c1e679ec 3449 AVX instructions also use this encoding, for some of
c0f3af97 3450 3 argument instructions. */
65da13b5 3451
43234a1e 3452 gas_assert (i.imm_operands <= 1
7ab9ffdd 3453 && (i.operands <= 2
43234a1e
L		 3454 || ((i.tm.opcode_modifier.vex
3455 || i.tm.opcode_modifier.evex)
7ab9ffdd 3456 && i.operands <= 4)));
65da13b5
L		 3457
3458 exp = &im_expressions[i.imm_operands++];
3459 i.op[i.operands].imms = exp;
3460 i.types[i.operands] = imm8;
3461 i.operands++;
3462 exp->X_op = O_constant;
3463 exp->X_add_number = i.tm.extension_opcode;
3464 i.tm.extension_opcode = None;
3465}
3466
42164a71
L		 3467
3468static int
3469check_hle (void)
3470{
3471 switch (i.tm.opcode_modifier.hleprefixok)
3472 {
3473 default:
3474 abort ();
82c2def5 3475 case HLEPrefixNone:
165de32a
L		 3476 as_bad (_("invalid instruction `%s' after `%s'"),
3477 i.tm.name, i.hle_prefix);
42164a71 3478 return 0;
82c2def5 3479 case HLEPrefixLock:
42164a71
L		 3480 if (i.prefix[LOCK_PREFIX])
3481 return 1;
165de32a 3482 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3483 return 0;
82c2def5 3484 case HLEPrefixAny:
42164a71 3485 return 1;
82c2def5 3486 case HLEPrefixRelease:
42164a71
L		 3487 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3488 {
3489 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3490 i.tm.name);
3491 return 0;
3492 }
3493 if (i.mem_operands == 0
3494 || !operand_type_check (i.types[i.operands - 1], anymem))
3495 {
3496 as_bad (_("memory destination needed for instruction `%s'"
3497 " after `xrelease'"), i.tm.name);
3498 return 0;
3499 }
3500 return 1;
3501 }
3502}
3503
252b5132
RH		 3504/* This is the guts of the machine-dependent assembler. LINE points to a
3505 machine dependent instruction. This function is supposed to emit
3506 the frags/bytes it assembles to. */
3507
3508void
65da13b5 3509md_assemble (char *line)
252b5132 3510{
40fb9820 3511 unsigned int j;
252b5132 3512 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3513 const insn_template *t;
252b5132 3514
47926f60 3515 /* Initialize globals. */
252b5132
RH		 3516 memset (&i, '\0', sizeof (i));
3517 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3518 i.reloc[j] = NO_RELOC;
252b5132
RH		 3519 memset (disp_expressions, '\0', sizeof (disp_expressions));
3520 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3521 save_stack_p = save_stack;
252b5132
RH		 3522
3523 /* First parse an instruction mnemonic & call i386_operand for the operands.
3524 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3525 start of a (possibly prefixed) mnemonic. */
252b5132 3526
29b0f896
AM		 3527 line = parse_insn (line, mnemonic);
3528 if (line == NULL)
3529 return;
252b5132 3530
29b0f896 3531 line = parse_operands (line, mnemonic);
ee86248c 3532 this_operand = -1;
29b0f896
AM		 3533 if (line == NULL)
3534 return;
252b5132 3535
29b0f896
AM		 3536 /* Now we've parsed the mnemonic into a set of templates, and have the
3537 operands at hand. */
3538
3539 /* All intel opcodes have reversed operands except for "bound" and
3540 "enter". We also don't reverse intersegment "jmp" and "call"
3541 instructions with 2 immediate operands so that the immediate segment
050dfa73 3542 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3543 if (intel_syntax
3544 && i.operands > 1
29b0f896 3545 && (strcmp (mnemonic, "bound") != 0)
30123838 3546 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3547 && !(operand_type_check (i.types[0], imm)
3548 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3549 swap_operands ();
3550
ec56d5c0
JB		 3551 /* The order of the immediates should be reversed
3552 for 2 immediates extrq and insertq instructions */
3553 if (i.imm_operands == 2
3554 && (strcmp (mnemonic, "extrq") == 0
3555 || strcmp (mnemonic, "insertq") == 0))
3556 swap_2_operands (0, 1);
3557
29b0f896
AM		 3558 if (i.imm_operands)
3559 optimize_imm ();
3560
b300c311
L		 3561 /* Don't optimize displacement for movabs since it only takes 64bit
3562 displacement. */
3563 if (i.disp_operands
a501d77e 3564 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3565 && (flag_code != CODE_64BIT
3566 || strcmp (mnemonic, "movabs") != 0))
3567 optimize_disp ();
29b0f896
AM		 3568
3569 /* Next, we find a template that matches the given insn,
3570 making sure the overlap of the given operands types is consistent
3571 with the template operand types. */
252b5132 3572
fa99fab2 3573 if (!(t = match_template ()))
29b0f896 3574 return;
252b5132 3575
7bab8ab5 3576 if (sse_check != check_none
81f8a913 3577 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3578 && (i.tm.cpu_flags.bitfield.cpusse
3579 || i.tm.cpu_flags.bitfield.cpusse2
3580 || i.tm.cpu_flags.bitfield.cpusse3
3581 || i.tm.cpu_flags.bitfield.cpussse3
3582 || i.tm.cpu_flags.bitfield.cpusse4_1
3583 || i.tm.cpu_flags.bitfield.cpusse4_2))
3584 {
7bab8ab5 3585 (sse_check == check_warning
daf50ae7
L		 3586 ? as_warn
3587 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3588 }
3589
321fd21e
L		 3590 /* Zap movzx and movsx suffix. The suffix has been set from
3591 "word ptr" or "byte ptr" on the source operand in Intel syntax
3592 or extracted from mnemonic in AT&T syntax. But we'll use
3593 the destination register to choose the suffix for encoding. */
3594 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3595 {
321fd21e
L		 3596 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3597 there is no suffix, the default will be byte extension. */
3598 if (i.reg_operands != 2
3599 && !i.suffix
7ab9ffdd 3600 && intel_syntax)
321fd21e
L		 3601 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3602
3603 i.suffix = 0;
cd61ebfe 3604 }
24eab124 3605
40fb9820 3606 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3607 if (!add_prefix (FWAIT_OPCODE))
3608 return;
252b5132 3609
d5de92cf
L		 3610 /* Check if REP prefix is OK. */
3611 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3612 {
3613 as_bad (_("invalid instruction `%s' after `%s'"),
3614 i.tm.name, i.rep_prefix);
3615 return;
3616 }
3617
c1ba0266
L		 3618 /* Check for lock without a lockable instruction. Destination operand
3619 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3620 if (i.prefix[LOCK_PREFIX]
3621 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3622 || i.mem_operands == 0
3623 || (i.tm.base_opcode != 0x86
3624 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3625 {
3626 as_bad (_("expecting lockable instruction after `lock'"));
3627 return;
3628 }
3629
42164a71 3630 /* Check if HLE prefix is OK. */
165de32a 3631 if (i.hle_prefix && !check_hle ())
42164a71
L		 3632 return;
3633
7e8b059b
L		 3634 /* Check BND prefix. */
3635 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3636 as_bad (_("expecting valid branch instruction after `bnd'"));
3637
3638 if (i.tm.cpu_flags.bitfield.cpumpx
3639 && flag_code == CODE_64BIT
3640 && i.prefix[ADDR_PREFIX])
3641 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3642
3643 /* Insert BND prefix. */
3644 if (add_bnd_prefix
3645 && i.tm.opcode_modifier.bndprefixok
3646 && !i.prefix[BND_PREFIX])
3647 add_prefix (BND_PREFIX_OPCODE);
3648
29b0f896 3649 /* Check string instruction segment overrides. */
40fb9820 3650 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3651 {
3652 if (!check_string ())
5dd0794d 3653 return;
fc0763e6 3654 i.disp_operands = 0;
29b0f896 3655 }
5dd0794d 3656
29b0f896
AM		 3657 if (!process_suffix ())
3658 return;
e413e4e9 3659
bc0844ae
L		 3660 /* Update operand types. */
3661 for (j = 0; j < i.operands; j++)
3662 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3663
29b0f896
AM		 3664 /* Make still unresolved immediate matches conform to size of immediate
3665 given in i.suffix. */
3666 if (!finalize_imm ())
3667 return;
252b5132 3668
40fb9820 3669 if (i.types[0].bitfield.imm1)
29b0f896 3670 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3671
9afe6eb8
L		 3672 /* We only need to check those implicit registers for instructions
3673 with 3 operands or less. */
3674 if (i.operands <= 3)
3675 for (j = 0; j < i.operands; j++)
3676 if (i.types[j].bitfield.inoutportreg
3677 || i.types[j].bitfield.shiftcount
3678 || i.types[j].bitfield.acc
3679 || i.types[j].bitfield.floatacc)
3680 i.reg_operands--;
40fb9820 3681
c0f3af97
L		 3682 /* ImmExt should be processed after SSE2AVX. */
3683 if (!i.tm.opcode_modifier.sse2avx
3684 && i.tm.opcode_modifier.immext)
65da13b5 3685 process_immext ();
252b5132 3686
29b0f896
AM		 3687 /* For insns with operands there are more diddles to do to the opcode. */
3688 if (i.operands)
3689 {
3690 if (!process_operands ())
3691 return;
3692 }
40fb9820 3693 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3694 {
3695 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3696 as_warn (_("translating to `%sp'"), i.tm.name);
3697 }
252b5132 3698
9e5e5283
L		 3699 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3700 {
3701 if (flag_code == CODE_16BIT)
3702 {
3703 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3704 i.tm.name);
3705 return;
3706 }
c0f3af97 3707
9e5e5283
L		 3708 if (i.tm.opcode_modifier.vex)
3709 build_vex_prefix (t);
3710 else
3711 build_evex_prefix ();
3712 }
43234a1e 3713
5dd85c99
SP		 3714 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3715 instructions may define INT_OPCODE as well, so avoid this corner
3716 case for those instructions that use MODRM. */
3717 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3718 && !i.tm.opcode_modifier.modrm
3719 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3720 {
3721 i.tm.base_opcode = INT3_OPCODE;
3722 i.imm_operands = 0;
3723 }
252b5132 3724
40fb9820
L		 3725 if ((i.tm.opcode_modifier.jump
3726 || i.tm.opcode_modifier.jumpbyte
3727 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3728 && i.op[0].disps->X_op == O_constant)
3729 {
3730 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3731 the absolute address given by the constant. Since ix86 jumps and
3732 calls are pc relative, we need to generate a reloc. */
3733 i.op[0].disps->X_add_symbol = &abs_symbol;
3734 i.op[0].disps->X_op = O_symbol;
3735 }
252b5132 3736
40fb9820 3737 if (i.tm.opcode_modifier.rex64)
161a04f6 3738 i.rex |= REX_W;
252b5132 3739
29b0f896
AM		 3740 /* For 8 bit registers we need an empty rex prefix. Also if the
3741 instruction already has a prefix, we need to convert old
3742 registers to new ones. */
773f551c 3743
40fb9820 3744 if ((i.types[0].bitfield.reg8
29b0f896 3745 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3746 || (i.types[1].bitfield.reg8
29b0f896 3747 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3748 || ((i.types[0].bitfield.reg8
3749 || i.types[1].bitfield.reg8)
29b0f896
AM		 3750 && i.rex != 0))
3751 {
3752 int x;
726c5dcd 3753
29b0f896
AM		 3754 i.rex |= REX_OPCODE;
3755 for (x = 0; x < 2; x++)
3756 {
3757 /* Look for 8 bit operand that uses old registers. */
40fb9820 3758 if (i.types[x].bitfield.reg8
29b0f896 3759 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3760 {
29b0f896
AM		 3761 /* In case it is "hi" register, give up. */
3762 if (i.op[x].regs->reg_num > 3)
a540244d 3763 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3764 "instruction requiring REX prefix."),
a540244d 3765 register_prefix, i.op[x].regs->reg_name);
773f551c 3766
29b0f896
AM		 3767 /* Otherwise it is equivalent to the extended register.
3768 Since the encoding doesn't change this is merely
3769 cosmetic cleanup for debug output. */
3770
3771 i.op[x].regs = i.op[x].regs + 8;
773f551c 3772 }
29b0f896
AM		 3773 }
3774 }
773f551c 3775
7ab9ffdd 3776 if (i.rex != 0)
29b0f896
AM		 3777 add_prefix (REX_OPCODE | i.rex);
3778
3779 /* We are ready to output the insn. */
3780 output_insn ();
3781}
3782
3783static char *
e3bb37b5 3784parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3785{
3786 char *l = line;
3787 char *token_start = l;
3788 char *mnem_p;
5c6af06e 3789 int supported;
d3ce72d0 3790 const insn_template *t;
b6169b20 3791 char *dot_p = NULL;
29b0f896 3792
29b0f896
AM		 3793 while (1)
3794 {
3795 mnem_p = mnemonic;
3796 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3797 {
b6169b20
L		 3798 if (*mnem_p == '.')
3799 dot_p = mnem_p;
29b0f896
AM		 3800 mnem_p++;
3801 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3802 {
29b0f896
AM		 3803 as_bad (_("no such instruction: `%s'"), token_start);
3804 return NULL;
3805 }
3806 l++;
3807 }
3808 if (!is_space_char (*l)
3809 && *l != END_OF_INSN
e44823cf
JB		 3810 && (intel_syntax
3811 || (*l != PREFIX_SEPARATOR
3812 && *l != ',')))
29b0f896
AM		 3813 {
3814 as_bad (_("invalid character %s in mnemonic"),
3815 output_invalid (*l));
3816 return NULL;
3817 }
3818 if (token_start == l)
3819 {
e44823cf 3820 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3821 as_bad (_("expecting prefix; got nothing"));
3822 else
3823 as_bad (_("expecting mnemonic; got nothing"));
3824 return NULL;
3825 }
45288df1 3826
29b0f896 3827 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3828 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3829
29b0f896
AM		 3830 if (*l != END_OF_INSN
3831 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3832 && current_templates
40fb9820 3833 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3834 {
c6fb90c8 3835 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3836 {
3837 as_bad ((flag_code != CODE_64BIT
3838 ? _("`%s' is only supported in 64-bit mode")
3839 : _("`%s' is not supported in 64-bit mode")),
3840 current_templates->start->name);
3841 return NULL;
3842 }
29b0f896
AM		 3843 /* If we are in 16-bit mode, do not allow addr16 or data16.
3844 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3845 if ((current_templates->start->opcode_modifier.size16
3846 || current_templates->start->opcode_modifier.size32)
29b0f896 3847 && flag_code != CODE_64BIT
40fb9820 3848 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3849 ^ (flag_code == CODE_16BIT)))
3850 {
3851 as_bad (_("redundant %s prefix"),
3852 current_templates->start->name);
3853 return NULL;
45288df1 3854 }
29b0f896
AM		 3855 /* Add prefix, checking for repeated prefixes. */
3856 switch (add_prefix (current_templates->start->base_opcode))
3857 {
c32fa91d 3858 case PREFIX_EXIST:
29b0f896 3859 return NULL;
c32fa91d 3860 case PREFIX_REP:
42164a71 3861 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3862 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3863 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3864 i.bnd_prefix = current_templates->start->name;
42164a71 3865 else
d5de92cf 3866 i.rep_prefix = current_templates->start->name;
29b0f896 3867 break;
c32fa91d
L		 3868 default:
3869 break;
29b0f896
AM		 3870 }
3871 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3872 token_start = ++l;
3873 }
3874 else
3875 break;
3876 }
45288df1 3877
30a55f88 3878 if (!current_templates)
b6169b20 3879 {
f8a5c266
L		 3880 /* Check if we should swap operand or force 32bit displacement in
3881 encoding. */
30a55f88
L		 3882 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3883 i.swap_operand = 1;
8d63c93e 3884 else if (mnem_p - 3 == dot_p
a501d77e
L		 3885 && dot_p[1] == 'd'
3886 && dot_p[2] == '8')
3887 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3888 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3889 && dot_p[1] == 'd'
3890 && dot_p[2] == '3'
3891 && dot_p[3] == '2')
a501d77e 3892 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3893 else
3894 goto check_suffix;
3895 mnem_p = dot_p;
3896 *dot_p = '\0';
d3ce72d0 3897 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3898 }
3899
29b0f896
AM		 3900 if (!current_templates)
3901 {
b6169b20 3902check_suffix:
29b0f896
AM		 3903 /* See if we can get a match by trimming off a suffix. */
3904 switch (mnem_p[-1])
3905 {
3906 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3907 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3908 i.suffix = SHORT_MNEM_SUFFIX;
3909 else
29b0f896
AM		 3910 case BYTE_MNEM_SUFFIX:
3911 case QWORD_MNEM_SUFFIX:
3912 i.suffix = mnem_p[-1];
3913 mnem_p[-1] = '\0';
d3ce72d0
NC		 3914 current_templates = (const templates *) hash_find (op_hash,
3915 mnemonic);
29b0f896
AM		 3916 break;
3917 case SHORT_MNEM_SUFFIX:
3918 case LONG_MNEM_SUFFIX:
3919 if (!intel_syntax)
3920 {
3921 i.suffix = mnem_p[-1];
3922 mnem_p[-1] = '\0';
d3ce72d0
NC		 3923 current_templates = (const templates *) hash_find (op_hash,
3924 mnemonic);
29b0f896
AM		 3925 }
3926 break;
252b5132 3927
29b0f896
AM		 3928 /* Intel Syntax. */
3929 case 'd':
3930 if (intel_syntax)
3931 {
9306ca4a 3932 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3933 i.suffix = SHORT_MNEM_SUFFIX;
3934 else
3935 i.suffix = LONG_MNEM_SUFFIX;
3936 mnem_p[-1] = '\0';
d3ce72d0
NC		 3937 current_templates = (const templates *) hash_find (op_hash,
3938 mnemonic);
29b0f896
AM		 3939 }
3940 break;
3941 }
3942 if (!current_templates)
3943 {
3944 as_bad (_("no such instruction: `%s'"), token_start);
3945 return NULL;
3946 }
3947 }
252b5132 3948
40fb9820
L		 3949 if (current_templates->start->opcode_modifier.jump
3950 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3951 {
3952 /* Check for a branch hint. We allow ",pt" and ",pn" for
3953 predict taken and predict not taken respectively.
3954 I'm not sure that branch hints actually do anything on loop
3955 and jcxz insns (JumpByte) for current Pentium4 chips. They
3956 may work in the future and it doesn't hurt to accept them
3957 now. */
3958 if (l[0] == ',' && l[1] == 'p')
3959 {
3960 if (l[2] == 't')
3961 {
3962 if (!add_prefix (DS_PREFIX_OPCODE))
3963 return NULL;
3964 l += 3;
3965 }
3966 else if (l[2] == 'n')
3967 {
3968 if (!add_prefix (CS_PREFIX_OPCODE))
3969 return NULL;
3970 l += 3;
3971 }
3972 }
3973 }
3974 /* Any other comma loses. */
3975 if (*l == ',')
3976 {
3977 as_bad (_("invalid character %s in mnemonic"),
3978 output_invalid (*l));
3979 return NULL;
3980 }
252b5132 3981
29b0f896 3982 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3983 supported = 0;
3984 for (t = current_templates->start; t < current_templates->end; ++t)
3985 {
c0f3af97
L		 3986 supported |= cpu_flags_match (t);
3987 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3988 goto skip;
5c6af06e 3989 }
3629bb00 3990
c0f3af97 3991 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3992 {
3993 as_bad (flag_code == CODE_64BIT
3994 ? _("`%s' is not supported in 64-bit mode")
3995 : _("`%s' is only supported in 64-bit mode"),
3996 current_templates->start->name);
3997 return NULL;
3998 }
c0f3af97 3999 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4000 {
3629bb00 4001 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4002 current_templates->start->name,
41aacd83 4003 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4004 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4005 return NULL;
29b0f896 4006 }
3629bb00
L		 4007
4008skip:
4009 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4010 && (flag_code != CODE_16BIT))
29b0f896
AM		 4011 {
4012 as_warn (_("use .code16 to ensure correct addressing mode"));
4013 }
252b5132 4014
29b0f896
AM		 4015 return l;
4016}
252b5132 4017
29b0f896 4018static char *
e3bb37b5 4019parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4020{
4021 char *token_start;
3138f287 4022
29b0f896
AM		 4023 /* 1 if operand is pending after ','. */
4024 unsigned int expecting_operand = 0;
252b5132 4025
29b0f896
AM		 4026 /* Non-zero if operand parens not balanced. */
4027 unsigned int paren_not_balanced;
4028
4029 while (*l != END_OF_INSN)
4030 {
4031 /* Skip optional white space before operand. */
4032 if (is_space_char (*l))
4033 ++l;
d02603dc 4034 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4035 {
4036 as_bad (_("invalid character %s before operand %d"),
4037 output_invalid (*l),
4038 i.operands + 1);
4039 return NULL;
4040 }
d02603dc 4041 token_start = l; /* After white space. */
29b0f896
AM		 4042 paren_not_balanced = 0;
4043 while (paren_not_balanced || *l != ',')
4044 {
4045 if (*l == END_OF_INSN)
4046 {
4047 if (paren_not_balanced)
4048 {
4049 if (!intel_syntax)
4050 as_bad (_("unbalanced parenthesis in operand %d."),
4051 i.operands + 1);
4052 else
4053 as_bad (_("unbalanced brackets in operand %d."),
4054 i.operands + 1);
4055 return NULL;
4056 }
4057 else
4058 break; /* we are done */
4059 }
d02603dc 4060 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4061 {
4062 as_bad (_("invalid character %s in operand %d"),
4063 output_invalid (*l),
4064 i.operands + 1);
4065 return NULL;
4066 }
4067 if (!intel_syntax)
4068 {
4069 if (*l == '(')
4070 ++paren_not_balanced;
4071 if (*l == ')')
4072 --paren_not_balanced;
4073 }
4074 else
4075 {
4076 if (*l == '[')
4077 ++paren_not_balanced;
4078 if (*l == ']')
4079 --paren_not_balanced;
4080 }
4081 l++;
4082 }
4083 if (l != token_start)
4084 { /* Yes, we've read in another operand. */
4085 unsigned int operand_ok;
4086 this_operand = i.operands++;
7d5e4556 4087 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4088 if (i.operands > MAX_OPERANDS)
4089 {
4090 as_bad (_("spurious operands; (%d operands/instruction max)"),
4091 MAX_OPERANDS);
4092 return NULL;
4093 }
4094 /* Now parse operand adding info to 'i' as we go along. */
4095 END_STRING_AND_SAVE (l);
4096
4097 if (intel_syntax)
4098 operand_ok =
4099 i386_intel_operand (token_start,
4100 intel_float_operand (mnemonic));
4101 else
a7619375 4102 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4103
4104 RESTORE_END_STRING (l);
4105 if (!operand_ok)
4106 return NULL;
4107 }
4108 else
4109 {
4110 if (expecting_operand)
4111 {
4112 expecting_operand_after_comma:
4113 as_bad (_("expecting operand after ','; got nothing"));
4114 return NULL;
4115 }
4116 if (*l == ',')
4117 {
4118 as_bad (_("expecting operand before ','; got nothing"));
4119 return NULL;
4120 }
4121 }
7f3f1ea2 4122
29b0f896
AM		 4123 /* Now *l must be either ',' or END_OF_INSN. */
4124 if (*l == ',')
4125 {
4126 if (*++l == END_OF_INSN)
4127 {
4128 /* Just skip it, if it's \n complain. */
4129 goto expecting_operand_after_comma;
4130 }
4131 expecting_operand = 1;
4132 }
4133 }
4134 return l;
4135}
7f3f1ea2 4136
050dfa73 4137static void
4d456e3d 4138swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4139{
4140 union i386_op temp_op;
40fb9820 4141 i386_operand_type temp_type;
050dfa73 4142 enum bfd_reloc_code_real temp_reloc;
4eed87de 4143
050dfa73
MM		 4144 temp_type = i.types[xchg2];
4145 i.types[xchg2] = i.types[xchg1];
4146 i.types[xchg1] = temp_type;
4147 temp_op = i.op[xchg2];
4148 i.op[xchg2] = i.op[xchg1];
4149 i.op[xchg1] = temp_op;
4150 temp_reloc = i.reloc[xchg2];
4151 i.reloc[xchg2] = i.reloc[xchg1];
4152 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4153
4154 if (i.mask)
4155 {
4156 if (i.mask->operand == xchg1)
4157 i.mask->operand = xchg2;
4158 else if (i.mask->operand == xchg2)
4159 i.mask->operand = xchg1;
4160 }
4161 if (i.broadcast)
4162 {
4163 if (i.broadcast->operand == xchg1)
4164 i.broadcast->operand = xchg2;
4165 else if (i.broadcast->operand == xchg2)
4166 i.broadcast->operand = xchg1;
4167 }
4168 if (i.rounding)
4169 {
4170 if (i.rounding->operand == xchg1)
4171 i.rounding->operand = xchg2;
4172 else if (i.rounding->operand == xchg2)
4173 i.rounding->operand = xchg1;
4174 }
050dfa73
MM		 4175}
4176
29b0f896 4177static void
e3bb37b5 4178swap_operands (void)
29b0f896 4179{
b7c61d9a 4180 switch (i.operands)
050dfa73 4181 {
c0f3af97 4182 case 5:
b7c61d9a 4183 case 4:
4d456e3d 4184 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4185 case 3:
4186 case 2:
4d456e3d 4187 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4188 break;
4189 default:
4190 abort ();
29b0f896 4191 }
29b0f896
AM		 4192
4193 if (i.mem_operands == 2)
4194 {
4195 const seg_entry *temp_seg;
4196 temp_seg = i.seg[0];
4197 i.seg[0] = i.seg[1];
4198 i.seg[1] = temp_seg;
4199 }
4200}
252b5132 4201
29b0f896
AM		 4202/* Try to ensure constant immediates are represented in the smallest
4203 opcode possible. */
4204static void
e3bb37b5 4205optimize_imm (void)
29b0f896
AM		 4206{
4207 char guess_suffix = 0;
4208 int op;
252b5132 4209
29b0f896
AM		 4210 if (i.suffix)
4211 guess_suffix = i.suffix;
4212 else if (i.reg_operands)
4213 {
4214 /* Figure out a suffix from the last register operand specified.
4215 We can't do this properly yet, ie. excluding InOutPortReg,
4216 but the following works for instructions with immediates.
4217 In any case, we can't set i.suffix yet. */
4218 for (op = i.operands; --op >= 0;)
40fb9820 4219 if (i.types[op].bitfield.reg8)
7ab9ffdd 4220 {
40fb9820
L		 4221 guess_suffix = BYTE_MNEM_SUFFIX;
4222 break;
4223 }
4224 else if (i.types[op].bitfield.reg16)
252b5132 4225 {
40fb9820
L		 4226 guess_suffix = WORD_MNEM_SUFFIX;
4227 break;
4228 }
4229 else if (i.types[op].bitfield.reg32)
4230 {
4231 guess_suffix = LONG_MNEM_SUFFIX;
4232 break;
4233 }
4234 else if (i.types[op].bitfield.reg64)
4235 {
4236 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4237 break;
252b5132 4238 }
29b0f896
AM		 4239 }
4240 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4241 guess_suffix = WORD_MNEM_SUFFIX;
4242
4243 for (op = i.operands; --op >= 0;)
40fb9820 4244 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4245 {
4246 switch (i.op[op].imms->X_op)
252b5132 4247 {
29b0f896
AM		 4248 case O_constant:
4249 /* If a suffix is given, this operand may be shortened. */
4250 switch (guess_suffix)
252b5132 4251 {
29b0f896 4252 case LONG_MNEM_SUFFIX:
40fb9820
L		 4253 i.types[op].bitfield.imm32 = 1;
4254 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4255 break;
4256 case WORD_MNEM_SUFFIX:
40fb9820
L		 4257 i.types[op].bitfield.imm16 = 1;
4258 i.types[op].bitfield.imm32 = 1;
4259 i.types[op].bitfield.imm32s = 1;
4260 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4261 break;
4262 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4263 i.types[op].bitfield.imm8 = 1;
4264 i.types[op].bitfield.imm8s = 1;
4265 i.types[op].bitfield.imm16 = 1;
4266 i.types[op].bitfield.imm32 = 1;
4267 i.types[op].bitfield.imm32s = 1;
4268 i.types[op].bitfield.imm64 = 1;
29b0f896 4269 break;
252b5132 4270 }
252b5132 4271
29b0f896
AM		 4272 /* If this operand is at most 16 bits, convert it
4273 to a signed 16 bit number before trying to see
4274 whether it will fit in an even smaller size.
4275 This allows a 16-bit operand such as $0xffe0 to
4276 be recognised as within Imm8S range. */
40fb9820 4277 if ((i.types[op].bitfield.imm16)
29b0f896 4278 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4279 {
29b0f896
AM		 4280 i.op[op].imms->X_add_number =
4281 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4282 }
a28def75
L		 4283#ifdef BFD64
4284 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4285 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4286 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4287 == 0))
4288 {
4289 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4290 ^ ((offsetT) 1 << 31))
4291 - ((offsetT) 1 << 31));
4292 }
a28def75 4293#endif
40fb9820 4294 i.types[op]
c6fb90c8
L		 4295 = operand_type_or (i.types[op],
4296 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4297
29b0f896
AM		 4298 /* We must avoid matching of Imm32 templates when 64bit
4299 only immediate is available. */
4300 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4301 i.types[op].bitfield.imm32 = 0;
29b0f896 4302 break;
252b5132 4303
29b0f896
AM		 4304 case O_absent:
4305 case O_register:
4306 abort ();
4307
4308 /* Symbols and expressions. */
4309 default:
9cd96992
JB		 4310 /* Convert symbolic operand to proper sizes for matching, but don't
4311 prevent matching a set of insns that only supports sizes other
4312 than those matching the insn suffix. */
4313 {
40fb9820 4314 i386_operand_type mask, allowed;
d3ce72d0 4315 const insn_template *t;
9cd96992 4316
0dfbf9d7
L		 4317 operand_type_set (&mask, 0);
4318 operand_type_set (&allowed, 0);
40fb9820 4319
4eed87de
AM		 4320 for (t = current_templates->start;
4321 t < current_templates->end;
4322 ++t)
c6fb90c8
L		 4323 allowed = operand_type_or (allowed,
4324 t->operand_types[op]);
9cd96992
JB		 4325 switch (guess_suffix)
4326 {
4327 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4328 mask.bitfield.imm64 = 1;
4329 mask.bitfield.imm32s = 1;
9cd96992
JB		 4330 break;
4331 case LONG_MNEM_SUFFIX:
40fb9820 4332 mask.bitfield.imm32 = 1;
9cd96992
JB		 4333 break;
4334 case WORD_MNEM_SUFFIX:
40fb9820 4335 mask.bitfield.imm16 = 1;
9cd96992
JB		 4336 break;
4337 case BYTE_MNEM_SUFFIX:
40fb9820 4338 mask.bitfield.imm8 = 1;
9cd96992
JB		 4339 break;
4340 default:
9cd96992
JB		 4341 break;
4342 }
c6fb90c8 4343 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4344 if (!operand_type_all_zero (&allowed))
c6fb90c8 4345 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4346 }
29b0f896 4347 break;
252b5132 4348 }
29b0f896
AM		 4349 }
4350}
47926f60 4351
29b0f896
AM		 4352/* Try to use the smallest displacement type too. */
4353static void
e3bb37b5 4354optimize_disp (void)
29b0f896
AM		 4355{
4356 int op;
3e73aa7c 4357
29b0f896 4358 for (op = i.operands; --op >= 0;)
40fb9820 4359 if (operand_type_check (i.types[op], disp))
252b5132 4360 {
b300c311 4361 if (i.op[op].disps->X_op == O_constant)
252b5132 4362 {
91d6fa6a 4363 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4364
40fb9820 4365 if (i.types[op].bitfield.disp16
91d6fa6a 4366 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4367 {
4368 /* If this operand is at most 16 bits, convert
4369 to a signed 16 bit number and don't use 64bit
4370 displacement. */
91d6fa6a 4371 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4372 i.types[op].bitfield.disp64 = 0;
b300c311 4373 }
a28def75
L		 4374#ifdef BFD64
4375 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4376 if (i.types[op].bitfield.disp32
91d6fa6a 4377 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4378 {
4379 /* If this operand is at most 32 bits, convert
4380 to a signed 32 bit number and don't use 64bit
4381 displacement. */
91d6fa6a
NC		 4382 op_disp &= (((offsetT) 2 << 31) - 1);
4383 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4384 i.types[op].bitfield.disp64 = 0;
b300c311 4385 }
a28def75 4386#endif
91d6fa6a 4387 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4388 {
40fb9820
L		 4389 i.types[op].bitfield.disp8 = 0;
4390 i.types[op].bitfield.disp16 = 0;
4391 i.types[op].bitfield.disp32 = 0;
4392 i.types[op].bitfield.disp32s = 0;
4393 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4394 i.op[op].disps = 0;
4395 i.disp_operands--;
4396 }
4397 else if (flag_code == CODE_64BIT)
4398 {
91d6fa6a 4399 if (fits_in_signed_long (op_disp))
28a9d8f5 4400 {
40fb9820
L		 4401 i.types[op].bitfield.disp64 = 0;
4402 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4403 }
0e1147d9 4404 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4405 && fits_in_unsigned_long (op_disp))
40fb9820 4406 i.types[op].bitfield.disp32 = 1;
b300c311 4407 }
40fb9820
L		 4408 if ((i.types[op].bitfield.disp32
4409 || i.types[op].bitfield.disp32s
4410 || i.types[op].bitfield.disp16)
91d6fa6a 4411 && fits_in_signed_byte (op_disp))
40fb9820 4412 i.types[op].bitfield.disp8 = 1;
252b5132 4413 }
67a4f2b7
AO		 4414 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4415 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4416 {
4417 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4418 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4419 i.types[op].bitfield.disp8 = 0;
4420 i.types[op].bitfield.disp16 = 0;
4421 i.types[op].bitfield.disp32 = 0;
4422 i.types[op].bitfield.disp32s = 0;
4423 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4424 }
4425 else
b300c311 4426 /* We only support 64bit displacement on constants. */
40fb9820 4427 i.types[op].bitfield.disp64 = 0;
252b5132 4428 }
29b0f896
AM		 4429}
4430
6c30d220
L		 4431/* Check if operands are valid for the instruction. */
4432
4433static int
4434check_VecOperands (const insn_template *t)
4435{
43234a1e
L		 4436 unsigned int op;
4437
6c30d220
L		 4438 /* Without VSIB byte, we can't have a vector register for index. */
4439 if (!t->opcode_modifier.vecsib
4440 && i.index_reg
4441 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4442 || i.index_reg->reg_type.bitfield.regymm
4443 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4444 {
4445 i.error = unsupported_vector_index_register;
4446 return 1;
4447 }
4448
ad8ecc81
MZ		 4449 /* Check if default mask is allowed. */
4450 if (t->opcode_modifier.nodefmask
4451 && (!i.mask || i.mask->mask->reg_num == 0))
4452 {
4453 i.error = no_default_mask;
4454 return 1;
4455 }
4456
7bab8ab5
JB		 4457 /* For VSIB byte, we need a vector register for index, and all vector
4458 registers must be distinct. */
4459 if (t->opcode_modifier.vecsib)
4460 {
4461 if (!i.index_reg
6c30d220
L		 4462 || !((t->opcode_modifier.vecsib == VecSIB128
4463 && i.index_reg->reg_type.bitfield.regxmm)
4464 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4465 && i.index_reg->reg_type.bitfield.regymm)
4466 || (t->opcode_modifier.vecsib == VecSIB512
4467 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4468 {
4469 i.error = invalid_vsib_address;
4470 return 1;
4471 }
4472
43234a1e
L		 4473 gas_assert (i.reg_operands == 2 || i.mask);
4474 if (i.reg_operands == 2 && !i.mask)
4475 {
4476 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4477 || i.types[0].bitfield.regymm);
43234a1e 4478 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4479 || i.types[2].bitfield.regymm);
43234a1e
L		 4480 if (operand_check == check_none)
4481 return 0;
4482 if (register_number (i.op[0].regs)
4483 != register_number (i.index_reg)
4484 && register_number (i.op[2].regs)
4485 != register_number (i.index_reg)
4486 && register_number (i.op[0].regs)
4487 != register_number (i.op[2].regs))
4488 return 0;
4489 if (operand_check == check_error)
4490 {
4491 i.error = invalid_vector_register_set;
4492 return 1;
4493 }
4494 as_warn (_("mask, index, and destination registers should be distinct"));
4495 }
8444f82a
MZ		 4496 else if (i.reg_operands == 1 && i.mask)
4497 {
4498 if ((i.types[1].bitfield.regymm
4499 || i.types[1].bitfield.regzmm)
4500 && (register_number (i.op[1].regs)
4501 == register_number (i.index_reg)))
4502 {
4503 if (operand_check == check_error)
4504 {
4505 i.error = invalid_vector_register_set;
4506 return 1;
4507 }
4508 if (operand_check != check_none)
4509 as_warn (_("index and destination registers should be distinct"));
4510 }
4511 }
43234a1e 4512 }
7bab8ab5 4513
43234a1e
L		 4514 /* Check if broadcast is supported by the instruction and is applied
4515 to the memory operand. */
4516 if (i.broadcast)
4517 {
4518 int broadcasted_opnd_size;
4519
4520 /* Check if specified broadcast is supported in this instruction,
4521 and it's applied to memory operand of DWORD or QWORD type,
4522 depending on VecESize. */
4523 if (i.broadcast->type != t->opcode_modifier.broadcast
4524 || !i.types[i.broadcast->operand].bitfield.mem
4525 || (t->opcode_modifier.vecesize == 0
4526 && !i.types[i.broadcast->operand].bitfield.dword
4527 && !i.types[i.broadcast->operand].bitfield.unspecified)
4528 || (t->opcode_modifier.vecesize == 1
4529 && !i.types[i.broadcast->operand].bitfield.qword
4530 && !i.types[i.broadcast->operand].bitfield.unspecified))
4531 goto bad_broadcast;
4532
4533 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4534 if (i.broadcast->type == BROADCAST_1TO16)
4535 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4536 else if (i.broadcast->type == BROADCAST_1TO8)
4537 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4538 else if (i.broadcast->type == BROADCAST_1TO4)
4539 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4540 else if (i.broadcast->type == BROADCAST_1TO2)
4541 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4542 else
4543 goto bad_broadcast;
4544
4545 if ((broadcasted_opnd_size == 256
4546 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4547 || (broadcasted_opnd_size == 512
4548 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4549 {
4550 bad_broadcast:
4551 i.error = unsupported_broadcast;
4552 return 1;
4553 }
4554 }
4555 /* If broadcast is supported in this instruction, we need to check if
4556 operand of one-element size isn't specified without broadcast. */
4557 else if (t->opcode_modifier.broadcast && i.mem_operands)
4558 {
4559 /* Find memory operand. */
4560 for (op = 0; op < i.operands; op++)
4561 if (operand_type_check (i.types[op], anymem))
4562 break;
4563 gas_assert (op < i.operands);
4564 /* Check size of the memory operand. */
4565 if ((t->opcode_modifier.vecesize == 0
4566 && i.types[op].bitfield.dword)
4567 || (t->opcode_modifier.vecesize == 1
4568 && i.types[op].bitfield.qword))
4569 {
4570 i.error = broadcast_needed;
4571 return 1;
4572 }
4573 }
4574
4575 /* Check if requested masking is supported. */
4576 if (i.mask
4577 && (!t->opcode_modifier.masking
4578 || (i.mask->zeroing
4579 && t->opcode_modifier.masking == MERGING_MASKING)))
4580 {
4581 i.error = unsupported_masking;
4582 return 1;
4583 }
4584
4585 /* Check if masking is applied to dest operand. */
4586 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4587 {
4588 i.error = mask_not_on_destination;
4589 return 1;
4590 }
4591
43234a1e
L		 4592 /* Check RC/SAE. */
4593 if (i.rounding)
4594 {
4595 if ((i.rounding->type != saeonly
4596 && !t->opcode_modifier.staticrounding)
4597 || (i.rounding->type == saeonly
4598 && (t->opcode_modifier.staticrounding
4599 || !t->opcode_modifier.sae)))
4600 {
4601 i.error = unsupported_rc_sae;
4602 return 1;
4603 }
4604 /* If the instruction has several immediate operands and one of
4605 them is rounding, the rounding operand should be the last
4606 immediate operand. */
4607 if (i.imm_operands > 1
4608 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4609 {
43234a1e 4610 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4611 return 1;
4612 }
6c30d220
L		 4613 }
4614
43234a1e
L		 4615 /* Check vector Disp8 operand. */
4616 if (t->opcode_modifier.disp8memshift)
4617 {
4618 if (i.broadcast)
4619 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4620 else
4621 i.memshift = t->opcode_modifier.disp8memshift;
4622
4623 for (op = 0; op < i.operands; op++)
4624 if (operand_type_check (i.types[op], disp)
4625 && i.op[op].disps->X_op == O_constant)
4626 {
4627 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4628 int vec_disp8_ok
4629 = (i.disp_encoding != disp_encoding_32bit
4630 && fits_in_vec_disp8 (value));
43234a1e
L		 4631 if (t->operand_types [op].bitfield.vec_disp8)
4632 {
4633 if (vec_disp8_ok)
4634 i.types[op].bitfield.vec_disp8 = 1;
4635 else
4636 {
4637 /* Vector insn can only have Vec_Disp8/Disp32 in
4638 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4639 mode. */
4640 i.types[op].bitfield.disp8 = 0;
4641 if (flag_code != CODE_16BIT)
4642 i.types[op].bitfield.disp16 = 0;
4643 }
4644 }
4645 else if (flag_code != CODE_16BIT)
4646 {
4647 /* One form of this instruction supports vector Disp8.
4648 Try vector Disp8 if we need to use Disp32. */
4649 if (vec_disp8_ok && !fits_in_signed_byte (value))
4650 {
4651 i.error = try_vector_disp8;
4652 return 1;
4653 }
4654 }
4655 }
4656 }
4657 else
4658 i.memshift = -1;
4659
6c30d220
L		 4660 return 0;
4661}
4662
43f3e2ee 4663/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4664 operand types. */
4665
4666static int
4667VEX_check_operands (const insn_template *t)
4668{
43234a1e
L		 4669 /* VREX is only valid with EVEX prefix. */
4670 if (i.need_vrex && !t->opcode_modifier.evex)
4671 {
4672 i.error = invalid_register_operand;
4673 return 1;
4674 }
4675
a683cc34
SP		 4676 if (!t->opcode_modifier.vex)
4677 return 0;
4678
4679 /* Only check VEX_Imm4, which must be the first operand. */
4680 if (t->operand_types[0].bitfield.vec_imm4)
4681 {
4682 if (i.op[0].imms->X_op != O_constant
4683 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4684 {
a65babc9 4685 i.error = bad_imm4;
891edac4
L		 4686 return 1;
4687 }
a683cc34
SP		 4688
4689 /* Turn off Imm8 so that update_imm won't complain. */
4690 i.types[0] = vec_imm4;
4691 }
4692
4693 return 0;
4694}
4695
d3ce72d0 4696static const insn_template *
e3bb37b5 4697match_template (void)
29b0f896
AM		 4698{
4699 /* Points to template once we've found it. */
d3ce72d0 4700 const insn_template *t;
40fb9820 4701 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4702 i386_operand_type overlap4;
29b0f896 4703 unsigned int found_reverse_match;
40fb9820
L		 4704 i386_opcode_modifier suffix_check;
4705 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4706 int addr_prefix_disp;
a5c311ca 4707 unsigned int j;
3629bb00 4708 unsigned int found_cpu_match;
45664ddb 4709 unsigned int check_register;
5614d22c 4710 enum i386_error specific_error = 0;
29b0f896 4711
c0f3af97
L		 4712#if MAX_OPERANDS != 5
4713# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4714#endif
4715
29b0f896 4716 found_reverse_match = 0;
539e75ad 4717 addr_prefix_disp = -1;
40fb9820
L		 4718
4719 memset (&suffix_check, 0, sizeof (suffix_check));
4720 if (i.suffix == BYTE_MNEM_SUFFIX)
4721 suffix_check.no_bsuf = 1;
4722 else if (i.suffix == WORD_MNEM_SUFFIX)
4723 suffix_check.no_wsuf = 1;
4724 else if (i.suffix == SHORT_MNEM_SUFFIX)
4725 suffix_check.no_ssuf = 1;
4726 else if (i.suffix == LONG_MNEM_SUFFIX)
4727 suffix_check.no_lsuf = 1;
4728 else if (i.suffix == QWORD_MNEM_SUFFIX)
4729 suffix_check.no_qsuf = 1;
4730 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4731 suffix_check.no_ldsuf = 1;
29b0f896 4732
01559ecc
L		 4733 /* Must have right number of operands. */
4734 i.error = number_of_operands_mismatch;
4735
45aa61fe 4736 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4737 {
539e75ad
L		 4738 addr_prefix_disp = -1;
4739
29b0f896
AM		 4740 if (i.operands != t->operands)
4741 continue;
4742
50aecf8c 4743 /* Check processor support. */
a65babc9 4744 i.error = unsupported;
c0f3af97
L		 4745 found_cpu_match = (cpu_flags_match (t)
4746 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4747 if (!found_cpu_match)
4748 continue;
4749
e1d4d893 4750 /* Check old gcc support. */
a65babc9 4751 i.error = old_gcc_only;
e1d4d893
L		 4752 if (!old_gcc && t->opcode_modifier.oldgcc)
4753 continue;
4754
4755 /* Check AT&T mnemonic. */
a65babc9 4756 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4757 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4758 continue;
4759
891edac4 4760 /* Check AT&T/Intel syntax. */
a65babc9 4761 i.error = unsupported_syntax;
5c07affc
L		 4762 if ((intel_syntax && t->opcode_modifier.attsyntax)
4763 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4764 continue;
4765
20592a94 4766 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4767 i.error = invalid_instruction_suffix;
567e4e96
L		 4768 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4769 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4770 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4771 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4772 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4773 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4774 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4775 continue;
4776
5c07affc 4777 if (!operand_size_match (t))
7d5e4556 4778 continue;
539e75ad 4779
5c07affc
L		 4780 for (j = 0; j < MAX_OPERANDS; j++)
4781 operand_types[j] = t->operand_types[j];
4782
45aa61fe
AM		 4783 /* In general, don't allow 64-bit operands in 32-bit mode. */
4784 if (i.suffix == QWORD_MNEM_SUFFIX
4785 && flag_code != CODE_64BIT
4786 && (intel_syntax
40fb9820 4787 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4788 && !intel_float_operand (t->name))
4789 : intel_float_operand (t->name) != 2)
40fb9820 4790 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4791 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4792 && !operand_types[0].bitfield.regymm
4793 && !operand_types[0].bitfield.regzmm)
40fb9820 4794 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4795 && operand_types[t->operands > 1].bitfield.regxmm
4796 && operand_types[t->operands > 1].bitfield.regymm
4797 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4798 && (t->base_opcode != 0x0fc7
4799 || t->extension_opcode != 1 /* cmpxchg8b */))
4800 continue;
4801
192dc9c6
JB		 4802 /* In general, don't allow 32-bit operands on pre-386. */
4803 else if (i.suffix == LONG_MNEM_SUFFIX
4804 && !cpu_arch_flags.bitfield.cpui386
4805 && (intel_syntax
4806 ? (!t->opcode_modifier.ignoresize
4807 && !intel_float_operand (t->name))
4808 : intel_float_operand (t->name) != 2)
4809 && ((!operand_types[0].bitfield.regmmx
4810 && !operand_types[0].bitfield.regxmm)
4811 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4812 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4813 continue;
4814
29b0f896 4815 /* Do not verify operands when there are none. */
50aecf8c 4816 else
29b0f896 4817 {
c6fb90c8 4818 if (!t->operands)
2dbab7d5
L		 4819 /* We've found a match; break out of loop. */
4820 break;
29b0f896 4821 }
252b5132 4822
539e75ad
L		 4823 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4824 into Disp32/Disp16/Disp32 operand. */
4825 if (i.prefix[ADDR_PREFIX] != 0)
4826 {
40fb9820 4827 /* There should be only one Disp operand. */
539e75ad
L		 4828 switch (flag_code)
4829 {
4830 case CODE_16BIT:
40fb9820
L		 4831 for (j = 0; j < MAX_OPERANDS; j++)
4832 {
4833 if (operand_types[j].bitfield.disp16)
4834 {
4835 addr_prefix_disp = j;
4836 operand_types[j].bitfield.disp32 = 1;
4837 operand_types[j].bitfield.disp16 = 0;
4838 break;
4839 }
4840 }
539e75ad
L		 4841 break;
4842 case CODE_32BIT:
40fb9820
L		 4843 for (j = 0; j < MAX_OPERANDS; j++)
4844 {
4845 if (operand_types[j].bitfield.disp32)
4846 {
4847 addr_prefix_disp = j;
4848 operand_types[j].bitfield.disp32 = 0;
4849 operand_types[j].bitfield.disp16 = 1;
4850 break;
4851 }
4852 }
539e75ad
L		 4853 break;
4854 case CODE_64BIT:
40fb9820
L		 4855 for (j = 0; j < MAX_OPERANDS; j++)
4856 {
4857 if (operand_types[j].bitfield.disp64)
4858 {
4859 addr_prefix_disp = j;
4860 operand_types[j].bitfield.disp64 = 0;
4861 operand_types[j].bitfield.disp32 = 1;
4862 break;
4863 }
4864 }
539e75ad
L		 4865 break;
4866 }
539e75ad
L		 4867 }
4868
02a86693
L		 4869 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4870 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4871 continue;
4872
56ffb741
L		 4873 /* We check register size if needed. */
4874 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4875 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4876 switch (t->operands)
4877 {
4878 case 1:
40fb9820 4879 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4880 continue;
4881 break;
4882 case 2:
8b38ad71
L		 4883 /* xchg %eax, %eax is a special case. It is an aliase for nop
4884 only in 32bit mode and we can use opcode 0x90. In 64bit
4885 mode, we can't use 0x90 for xchg %eax, %eax since it should
4886 zero-extend %eax to %rax. */
4887 if (flag_code == CODE_64BIT
4888 && t->base_opcode == 0x90
0dfbf9d7
L		 4889 && operand_type_equal (&i.types [0], &acc32)
4890 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4891 continue;
b6169b20
L		 4892 if (i.swap_operand)
4893 {
4894 /* If we swap operand in encoding, we either match
4895 the next one or reverse direction of operands. */
4896 if (t->opcode_modifier.s)
4897 continue;
4898 else if (t->opcode_modifier.d)
4899 goto check_reverse;
4900 }
4901
29b0f896 4902 case 3:
fa99fab2
L		 4903 /* If we swap operand in encoding, we match the next one. */
4904 if (i.swap_operand && t->opcode_modifier.s)
4905 continue;
f48ff2ae 4906 case 4:
c0f3af97 4907 case 5:
c6fb90c8 4908 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4909 if (!operand_type_match (overlap0, i.types[0])
4910 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4911 || (check_register
4912 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4913 operand_types[0],
4914 overlap1, i.types[1],
4915 operand_types[1])))
29b0f896
AM		 4916 {
4917 /* Check if other direction is valid ... */
40fb9820 4918 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4919 continue;
4920
b6169b20 4921check_reverse:
29b0f896 4922 /* Try reversing direction of operands. */
c6fb90c8
L		 4923 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4924 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4925 if (!operand_type_match (overlap0, i.types[0])
4926 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4927 || (check_register
4928 && !operand_type_register_match (overlap0,
4929 i.types[0],
4930 operand_types[1],
4931 overlap1,
4932 i.types[1],
4933 operand_types[0])))
29b0f896
AM		 4934 {
4935 /* Does not match either direction. */
4936 continue;
4937 }
4938 /* found_reverse_match holds which of D or FloatDR
4939 we've found. */
40fb9820 4940 if (t->opcode_modifier.d)
8a2ed489 4941 found_reverse_match = Opcode_D;
40fb9820 4942 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4943 found_reverse_match = Opcode_FloatD;
4944 else
4945 found_reverse_match = 0;
40fb9820 4946 if (t->opcode_modifier.floatr)
8a2ed489 4947 found_reverse_match |= Opcode_FloatR;
29b0f896 4948 }
f48ff2ae 4949 else
29b0f896 4950 {
f48ff2ae 4951 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4952 switch (t->operands)
4953 {
c0f3af97
L		 4954 case 5:
4955 overlap4 = operand_type_and (i.types[4],
4956 operand_types[4]);
d1cbb4db 4957 case 4:
c6fb90c8
L		 4958 overlap3 = operand_type_and (i.types[3],
4959 operand_types[3]);
d1cbb4db 4960 case 3:
c6fb90c8
L		 4961 overlap2 = operand_type_and (i.types[2],
4962 operand_types[2]);
d1cbb4db
L		 4963 break;
4964 }
29b0f896 4965
f48ff2ae
L		 4966 switch (t->operands)
4967 {
c0f3af97
L		 4968 case 5:
4969 if (!operand_type_match (overlap4, i.types[4])
4970 || !operand_type_register_match (overlap3,
4971 i.types[3],
4972 operand_types[3],
4973 overlap4,
4974 i.types[4],
4975 operand_types[4]))
4976 continue;
f48ff2ae 4977 case 4:
40fb9820 4978 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4979 || (check_register
4980 && !operand_type_register_match (overlap2,
4981 i.types[2],
4982 operand_types[2],
4983 overlap3,
4984 i.types[3],
4985 operand_types[3])))
f48ff2ae
L		 4986 continue;
4987 case 3:
4988 /* Here we make use of the fact that there are no
4989 reverse match 3 operand instructions, and all 3
4990 operand instructions only need to be checked for
4991 register consistency between operands 2 and 3. */
40fb9820 4992 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4993 || (check_register
4994 && !operand_type_register_match (overlap1,
4995 i.types[1],
4996 operand_types[1],
4997 overlap2,
4998 i.types[2],
4999 operand_types[2])))
f48ff2ae
L		 5000 continue;
5001 break;
5002 }
29b0f896 5003 }
f48ff2ae 5004 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5005 slip through to break. */
5006 }
3629bb00 5007 if (!found_cpu_match)
29b0f896
AM		 5008 {
5009 found_reverse_match = 0;
5010 continue;
5011 }
c0f3af97 5012
5614d22c
JB		 5013 /* Check if vector and VEX operands are valid. */
5014 if (check_VecOperands (t) || VEX_check_operands (t))
5015 {
5016 specific_error = i.error;
5017 continue;
5018 }
a683cc34 5019
29b0f896
AM		 5020 /* We've found a match; break out of loop. */
5021 break;
5022 }
5023
5024 if (t == current_templates->end)
5025 {
5026 /* We found no match. */
a65babc9 5027 const char *err_msg;
5614d22c 5028 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5029 {
5030 default:
5031 abort ();
86e026a4 5032 case operand_size_mismatch:
a65babc9
L		 5033 err_msg = _("operand size mismatch");
5034 break;
5035 case operand_type_mismatch:
5036 err_msg = _("operand type mismatch");
5037 break;
5038 case register_type_mismatch:
5039 err_msg = _("register type mismatch");
5040 break;
5041 case number_of_operands_mismatch:
5042 err_msg = _("number of operands mismatch");
5043 break;
5044 case invalid_instruction_suffix:
5045 err_msg = _("invalid instruction suffix");
5046 break;
5047 case bad_imm4:
4a2608e3 5048 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5049 break;
5050 case old_gcc_only:
5051 err_msg = _("only supported with old gcc");
5052 break;
5053 case unsupported_with_intel_mnemonic:
5054 err_msg = _("unsupported with Intel mnemonic");
5055 break;
5056 case unsupported_syntax:
5057 err_msg = _("unsupported syntax");
5058 break;
5059 case unsupported:
35262a23 5060 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5061 current_templates->start->name);
5062 return NULL;
6c30d220
L		 5063 case invalid_vsib_address:
5064 err_msg = _("invalid VSIB address");
5065 break;
7bab8ab5
JB		 5066 case invalid_vector_register_set:
5067 err_msg = _("mask, index, and destination registers must be distinct");
5068 break;
6c30d220
L		 5069 case unsupported_vector_index_register:
5070 err_msg = _("unsupported vector index register");
5071 break;
43234a1e
L		 5072 case unsupported_broadcast:
5073 err_msg = _("unsupported broadcast");
5074 break;
5075 case broadcast_not_on_src_operand:
5076 err_msg = _("broadcast not on source memory operand");
5077 break;
5078 case broadcast_needed:
5079 err_msg = _("broadcast is needed for operand of such type");
5080 break;
5081 case unsupported_masking:
5082 err_msg = _("unsupported masking");
5083 break;
5084 case mask_not_on_destination:
5085 err_msg = _("mask not on destination operand");
5086 break;
5087 case no_default_mask:
5088 err_msg = _("default mask isn't allowed");
5089 break;
5090 case unsupported_rc_sae:
5091 err_msg = _("unsupported static rounding/sae");
5092 break;
5093 case rc_sae_operand_not_last_imm:
5094 if (intel_syntax)
5095 err_msg = _("RC/SAE operand must precede immediate operands");
5096 else
5097 err_msg = _("RC/SAE operand must follow immediate operands");
5098 break;
5099 case invalid_register_operand:
5100 err_msg = _("invalid register operand");
5101 break;
a65babc9
L		 5102 }
5103 as_bad (_("%s for `%s'"), err_msg,
891edac4 5104 current_templates->start->name);
fa99fab2 5105 return NULL;
29b0f896 5106 }
252b5132 5107
29b0f896
AM		 5108 if (!quiet_warnings)
5109 {
5110 if (!intel_syntax
40fb9820
L		 5111 && (i.types[0].bitfield.jumpabsolute
5112 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5113 {
5114 as_warn (_("indirect %s without `*'"), t->name);
5115 }
5116
40fb9820
L		 5117 if (t->opcode_modifier.isprefix
5118 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5119 {
5120 /* Warn them that a data or address size prefix doesn't
5121 affect assembly of the next line of code. */
5122 as_warn (_("stand-alone `%s' prefix"), t->name);
5123 }
5124 }
5125
5126 /* Copy the template we found. */
5127 i.tm = *t;
539e75ad
L		 5128
5129 if (addr_prefix_disp != -1)
5130 i.tm.operand_types[addr_prefix_disp]
5131 = operand_types[addr_prefix_disp];
5132
29b0f896
AM		 5133 if (found_reverse_match)
5134 {
5135 /* If we found a reverse match we must alter the opcode
5136 direction bit. found_reverse_match holds bits to change
5137 (different for int & float insns). */
5138
5139 i.tm.base_opcode ^= found_reverse_match;
5140
539e75ad
L		 5141 i.tm.operand_types[0] = operand_types[1];
5142 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5143 }
5144
fa99fab2 5145 return t;
29b0f896
AM		 5146}
5147
5148static int
e3bb37b5 5149check_string (void)
29b0f896 5150{
40fb9820
L		 5151 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5152 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5153 {
5154 if (i.seg[0] != NULL && i.seg[0] != &es)
5155 {
a87af027 5156 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5157 i.tm.name,
a87af027
JB		 5158 mem_op + 1,
5159 register_prefix);
29b0f896
AM		 5160 return 0;
5161 }
5162 /* There's only ever one segment override allowed per instruction.
5163 This instruction possibly has a legal segment override on the
5164 second operand, so copy the segment to where non-string
5165 instructions store it, allowing common code. */
5166 i.seg[0] = i.seg[1];
5167 }
40fb9820 5168 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5169 {
5170 if (i.seg[1] != NULL && i.seg[1] != &es)
5171 {
a87af027 5172 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5173 i.tm.name,
a87af027
JB		 5174 mem_op + 2,
5175 register_prefix);
29b0f896
AM		 5176 return 0;
5177 }
5178 }
5179 return 1;
5180}
5181
5182static int
543613e9 5183process_suffix (void)
29b0f896
AM		 5184{
5185 /* If matched instruction specifies an explicit instruction mnemonic
5186 suffix, use it. */
40fb9820
L		 5187 if (i.tm.opcode_modifier.size16)
5188 i.suffix = WORD_MNEM_SUFFIX;
5189 else if (i.tm.opcode_modifier.size32)
5190 i.suffix = LONG_MNEM_SUFFIX;
5191 else if (i.tm.opcode_modifier.size64)
5192 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5193 else if (i.reg_operands)
5194 {
5195 /* If there's no instruction mnemonic suffix we try to invent one
5196 based on register operands. */
5197 if (!i.suffix)
5198 {
5199 /* We take i.suffix from the last register operand specified,
5200 Destination register type is more significant than source
381d071f
L		 5201 register type. crc32 in SSE4.2 prefers source register
5202 type. */
5203 if (i.tm.base_opcode == 0xf20f38f1)
5204 {
40fb9820
L		 5205 if (i.types[0].bitfield.reg16)
5206 i.suffix = WORD_MNEM_SUFFIX;
5207 else if (i.types[0].bitfield.reg32)
5208 i.suffix = LONG_MNEM_SUFFIX;
5209 else if (i.types[0].bitfield.reg64)
5210 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5211 }
9344ff29 5212 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5213 {
40fb9820 5214 if (i.types[0].bitfield.reg8)
20592a94
L		 5215 i.suffix = BYTE_MNEM_SUFFIX;
5216 }
381d071f
L		 5217
5218 if (!i.suffix)
5219 {
5220 int op;
5221
20592a94
L		 5222 if (i.tm.base_opcode == 0xf20f38f1
5223 || i.tm.base_opcode == 0xf20f38f0)
5224 {
5225 /* We have to know the operand size for crc32. */
5226 as_bad (_("ambiguous memory operand size for `%s`"),
5227 i.tm.name);
5228 return 0;
5229 }
5230
381d071f 5231 for (op = i.operands; --op >= 0;)
40fb9820 5232 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5233 {
40fb9820
L		 5234 if (i.types[op].bitfield.reg8)
5235 {
5236 i.suffix = BYTE_MNEM_SUFFIX;
5237 break;
5238 }
5239 else if (i.types[op].bitfield.reg16)
5240 {
5241 i.suffix = WORD_MNEM_SUFFIX;
5242 break;
5243 }
5244 else if (i.types[op].bitfield.reg32)
5245 {
5246 i.suffix = LONG_MNEM_SUFFIX;
5247 break;
5248 }
5249 else if (i.types[op].bitfield.reg64)
5250 {
5251 i.suffix = QWORD_MNEM_SUFFIX;
5252 break;
5253 }
381d071f
L		 5254 }
5255 }
29b0f896
AM		 5256 }
5257 else if (i.suffix == BYTE_MNEM_SUFFIX)
5258 {
2eb952a4
L		 5259 if (intel_syntax
5260 && i.tm.opcode_modifier.ignoresize
5261 && i.tm.opcode_modifier.no_bsuf)
5262 i.suffix = 0;
5263 else if (!check_byte_reg ())
29b0f896
AM		 5264 return 0;
5265 }
5266 else if (i.suffix == LONG_MNEM_SUFFIX)
5267 {
2eb952a4
L		 5268 if (intel_syntax
5269 && i.tm.opcode_modifier.ignoresize
5270 && i.tm.opcode_modifier.no_lsuf)
5271 i.suffix = 0;
5272 else if (!check_long_reg ())
29b0f896
AM		 5273 return 0;
5274 }
5275 else if (i.suffix == QWORD_MNEM_SUFFIX)
5276 {
955e1e6a
L		 5277 if (intel_syntax
5278 && i.tm.opcode_modifier.ignoresize
5279 && i.tm.opcode_modifier.no_qsuf)
5280 i.suffix = 0;
5281 else if (!check_qword_reg ())
29b0f896
AM		 5282 return 0;
5283 }
5284 else if (i.suffix == WORD_MNEM_SUFFIX)
5285 {
2eb952a4
L		 5286 if (intel_syntax
5287 && i.tm.opcode_modifier.ignoresize
5288 && i.tm.opcode_modifier.no_wsuf)
5289 i.suffix = 0;
5290 else if (!check_word_reg ())
29b0f896
AM		 5291 return 0;
5292 }
c0f3af97 5293 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5294 || i.suffix == YMMWORD_MNEM_SUFFIX
5295 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5296 {
43234a1e 5297 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5298 should check if it is a valid suffix. */
5299 }
40fb9820 5300 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5301 /* Do nothing if the instruction is going to ignore the prefix. */
5302 ;
5303 else
5304 abort ();
5305 }
40fb9820 5306 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5307 && !i.suffix
5308 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5309 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5310 {
5311 i.suffix = stackop_size;
5312 }
9306ca4a
JB		 5313 else if (intel_syntax
5314 && !i.suffix
40fb9820
L		 5315 && (i.tm.operand_types[0].bitfield.jumpabsolute
5316 || i.tm.opcode_modifier.jumpbyte
5317 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5318 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5319 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5320 {
5321 switch (flag_code)
5322 {
5323 case CODE_64BIT:
40fb9820 5324 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5325 {
5326 i.suffix = QWORD_MNEM_SUFFIX;
5327 break;
5328 }
5329 case CODE_32BIT:
40fb9820 5330 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5331 i.suffix = LONG_MNEM_SUFFIX;
5332 break;
5333 case CODE_16BIT:
40fb9820 5334 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5335 i.suffix = WORD_MNEM_SUFFIX;
5336 break;
5337 }
5338 }
252b5132 5339
9306ca4a 5340 if (!i.suffix)
29b0f896 5341 {
9306ca4a
JB		 5342 if (!intel_syntax)
5343 {
40fb9820 5344 if (i.tm.opcode_modifier.w)
9306ca4a 5345 {
4eed87de
AM		 5346 as_bad (_("no instruction mnemonic suffix given and "
5347 "no register operands; can't size instruction"));
9306ca4a
JB		 5348 return 0;
5349 }
5350 }
5351 else
5352 {
40fb9820 5353 unsigned int suffixes;
7ab9ffdd 5354
40fb9820
L		 5355 suffixes = !i.tm.opcode_modifier.no_bsuf;
5356 if (!i.tm.opcode_modifier.no_wsuf)
5357 suffixes |= 1 << 1;
5358 if (!i.tm.opcode_modifier.no_lsuf)
5359 suffixes |= 1 << 2;
fc4adea1 5360 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5361 suffixes |= 1 << 3;
5362 if (!i.tm.opcode_modifier.no_ssuf)
5363 suffixes |= 1 << 4;
5364 if (!i.tm.opcode_modifier.no_qsuf)
5365 suffixes |= 1 << 5;
5366
5367 /* There are more than suffix matches. */
5368 if (i.tm.opcode_modifier.w
9306ca4a 5369 || ((suffixes & (suffixes - 1))
40fb9820
L		 5370 && !i.tm.opcode_modifier.defaultsize
5371 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5372 {
5373 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5374 return 0;
5375 }
5376 }
29b0f896 5377 }
252b5132 5378
9306ca4a
JB		 5379 /* Change the opcode based on the operand size given by i.suffix;
5380 We don't need to change things for byte insns. */
5381
582d5edd
L		 5382 if (i.suffix
5383 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5384 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5385 && i.suffix != YMMWORD_MNEM_SUFFIX
5386 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5387 {
5388 /* It's not a byte, select word/dword operation. */
40fb9820 5389 if (i.tm.opcode_modifier.w)
29b0f896 5390 {
40fb9820 5391 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5392 i.tm.base_opcode |= 8;
5393 else
5394 i.tm.base_opcode |= 1;
5395 }
0f3f3d8b 5396
29b0f896
AM		 5397 /* Now select between word & dword operations via the operand
5398 size prefix, except for instructions that will ignore this
5399 prefix anyway. */
ca61edf2 5400 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5401 {
ca61edf2
L		 5402 /* The address size override prefix changes the size of the
5403 first operand. */
40fb9820
L		 5404 if ((flag_code == CODE_32BIT
5405 && i.op->regs[0].reg_type.bitfield.reg16)
5406 || (flag_code != CODE_32BIT
5407 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5408 if (!add_prefix (ADDR_PREFIX_OPCODE))
5409 return 0;
5410 }
5411 else if (i.suffix != QWORD_MNEM_SUFFIX
5412 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5413 && !i.tm.opcode_modifier.ignoresize
5414 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5415 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5416 || (flag_code == CODE_64BIT
40fb9820 5417 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5418 {
5419 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5420
40fb9820 5421 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5422 prefix = ADDR_PREFIX_OPCODE;
252b5132 5423
29b0f896
AM		 5424 if (!add_prefix (prefix))
5425 return 0;
24eab124 5426 }
252b5132 5427
29b0f896
AM		 5428 /* Set mode64 for an operand. */
5429 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5430 && flag_code == CODE_64BIT
40fb9820 5431 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5432 {
5433 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5434 need rex64. cmpxchg8b is also a special case. */
5435 if (! (i.operands == 2
5436 && i.tm.base_opcode == 0x90
5437 && i.tm.extension_opcode == None
0dfbf9d7
L		 5438 && operand_type_equal (&i.types [0], &acc64)
5439 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5440 && ! (i.operands == 1
5441 && i.tm.base_opcode == 0xfc7
5442 && i.tm.extension_opcode == 1
40fb9820
L		 5443 && !operand_type_check (i.types [0], reg)
5444 && operand_type_check (i.types [0], anymem)))
f6bee062 5445 i.rex |= REX_W;
46e883c5 5446 }
3e73aa7c 5447
29b0f896
AM		 5448 /* Size floating point instruction. */
5449 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5450 if (i.tm.opcode_modifier.floatmf)
543613e9 5451 i.tm.base_opcode ^= 4;
29b0f896 5452 }
7ecd2f8b 5453
29b0f896
AM		 5454 return 1;
5455}
3e73aa7c 5456
29b0f896 5457static int
543613e9 5458check_byte_reg (void)
29b0f896
AM		 5459{
5460 int op;
543613e9 5461
29b0f896
AM		 5462 for (op = i.operands; --op >= 0;)
5463 {
5464 /* If this is an eight bit register, it's OK. If it's the 16 or
5465 32 bit version of an eight bit register, we will just use the
5466 low portion, and that's OK too. */
40fb9820 5467 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5468 continue;
5469
5a819eb9
JB		 5470 /* I/O port address operands are OK too. */
5471 if (i.tm.operand_types[op].bitfield.inoutportreg)
5472 continue;
5473
9344ff29
L		 5474 /* crc32 doesn't generate this warning. */
5475 if (i.tm.base_opcode == 0xf20f38f0)
5476 continue;
5477
40fb9820
L		 5478 if ((i.types[op].bitfield.reg16
5479 || i.types[op].bitfield.reg32
5480 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5481 && i.op[op].regs->reg_num < 4
5482 /* Prohibit these changes in 64bit mode, since the lowering
5483 would be more complicated. */
5484 && flag_code != CODE_64BIT)
29b0f896 5485 {
29b0f896 5486#if REGISTER_WARNINGS
5a819eb9 5487 if (!quiet_warnings)
a540244d
L		 5488 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5489 register_prefix,
40fb9820 5490 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5491 ? REGNAM_AL - REGNAM_AX
5492 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5493 register_prefix,
29b0f896
AM		 5494 i.op[op].regs->reg_name,
5495 i.suffix);
5496#endif
5497 continue;
5498 }
5499 /* Any other register is bad. */
40fb9820
L		 5500 if (i.types[op].bitfield.reg16
5501 || i.types[op].bitfield.reg32
5502 || i.types[op].bitfield.reg64
5503 || i.types[op].bitfield.regmmx
5504 || i.types[op].bitfield.regxmm
c0f3af97 5505 || i.types[op].bitfield.regymm
43234a1e 5506 || i.types[op].bitfield.regzmm
40fb9820
L		 5507 || i.types[op].bitfield.sreg2
5508 || i.types[op].bitfield.sreg3
5509 || i.types[op].bitfield.control
5510 || i.types[op].bitfield.debug
5511 || i.types[op].bitfield.test
5512 || i.types[op].bitfield.floatreg
5513 || i.types[op].bitfield.floatacc)
29b0f896 5514 {
a540244d
L		 5515 as_bad (_("`%s%s' not allowed with `%s%c'"),
5516 register_prefix,
29b0f896
AM		 5517 i.op[op].regs->reg_name,
5518 i.tm.name,
5519 i.suffix);
5520 return 0;
5521 }
5522 }
5523 return 1;
5524}
5525
5526static int
e3bb37b5 5527check_long_reg (void)
29b0f896
AM		 5528{
5529 int op;
5530
5531 for (op = i.operands; --op >= 0;)
5532 /* Reject eight bit registers, except where the template requires
5533 them. (eg. movzb) */
40fb9820
L		 5534 if (i.types[op].bitfield.reg8
5535 && (i.tm.operand_types[op].bitfield.reg16
5536 || i.tm.operand_types[op].bitfield.reg32
5537 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5538 {
a540244d
L		 5539 as_bad (_("`%s%s' not allowed with `%s%c'"),
5540 register_prefix,
29b0f896
AM		 5541 i.op[op].regs->reg_name,
5542 i.tm.name,
5543 i.suffix);
5544 return 0;
5545 }
e4630f71 5546 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5547 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5548 && i.types[op].bitfield.reg16
5549 && (i.tm.operand_types[op].bitfield.reg32
5550 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5551 {
5552 /* Prohibit these changes in the 64bit mode, since the
5553 lowering is more complicated. */
5554 if (flag_code == CODE_64BIT)
252b5132 5555 {
2b5d6a91 5556 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5557 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5558 i.suffix);
5559 return 0;
252b5132 5560 }
29b0f896 5561#if REGISTER_WARNINGS
cecf1424
JB		 5562 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5563 register_prefix,
5564 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5565 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5566#endif
252b5132 5567 }
e4630f71 5568 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5569 else if (i.types[op].bitfield.reg64
5570 && (i.tm.operand_types[op].bitfield.reg32
5571 || i.tm.operand_types[op].bitfield.acc))
252b5132 5572 {
34828aad 5573 if (intel_syntax
ca61edf2 5574 && i.tm.opcode_modifier.toqword
40fb9820 5575 && !i.types[0].bitfield.regxmm)
34828aad 5576 {
ca61edf2 5577 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5578 i.suffix = QWORD_MNEM_SUFFIX;
5579 }
5580 else
5581 {
2b5d6a91 5582 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5583 register_prefix, i.op[op].regs->reg_name,
5584 i.suffix);
5585 return 0;
5586 }
29b0f896
AM		 5587 }
5588 return 1;
5589}
252b5132 5590
29b0f896 5591static int
e3bb37b5 5592check_qword_reg (void)
29b0f896
AM		 5593{
5594 int op;
252b5132 5595
29b0f896
AM		 5596 for (op = i.operands; --op >= 0; )
5597 /* Reject eight bit registers, except where the template requires
5598 them. (eg. movzb) */
40fb9820
L		 5599 if (i.types[op].bitfield.reg8
5600 && (i.tm.operand_types[op].bitfield.reg16
5601 || i.tm.operand_types[op].bitfield.reg32
5602 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5603 {
a540244d
L		 5604 as_bad (_("`%s%s' not allowed with `%s%c'"),
5605 register_prefix,
29b0f896
AM		 5606 i.op[op].regs->reg_name,
5607 i.tm.name,
5608 i.suffix);
5609 return 0;
5610 }
e4630f71 5611 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5612 else if ((i.types[op].bitfield.reg16
5613 || i.types[op].bitfield.reg32)
5614 && (i.tm.operand_types[op].bitfield.reg32
5615 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5616 {
5617 /* Prohibit these changes in the 64bit mode, since the
5618 lowering is more complicated. */
34828aad 5619 if (intel_syntax
ca61edf2 5620 && i.tm.opcode_modifier.todword
40fb9820 5621 && !i.types[0].bitfield.regxmm)
34828aad 5622 {
ca61edf2 5623 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5624 i.suffix = LONG_MNEM_SUFFIX;
5625 }
5626 else
5627 {
2b5d6a91 5628 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5629 register_prefix, i.op[op].regs->reg_name,
5630 i.suffix);
5631 return 0;
5632 }
252b5132 5633 }
29b0f896
AM		 5634 return 1;
5635}
252b5132 5636
29b0f896 5637static int
e3bb37b5 5638check_word_reg (void)
29b0f896
AM		 5639{
5640 int op;
5641 for (op = i.operands; --op >= 0;)
5642 /* Reject eight bit registers, except where the template requires
5643 them. (eg. movzb) */
40fb9820
L		 5644 if (i.types[op].bitfield.reg8
5645 && (i.tm.operand_types[op].bitfield.reg16
5646 || i.tm.operand_types[op].bitfield.reg32
5647 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5648 {
a540244d
L		 5649 as_bad (_("`%s%s' not allowed with `%s%c'"),
5650 register_prefix,
29b0f896
AM		 5651 i.op[op].regs->reg_name,
5652 i.tm.name,
5653 i.suffix);
5654 return 0;
5655 }
e4630f71 5656 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5657 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5658 && (i.types[op].bitfield.reg32
5659 || i.types[op].bitfield.reg64)
40fb9820
L		 5660 && (i.tm.operand_types[op].bitfield.reg16
5661 || i.tm.operand_types[op].bitfield.acc))
252b5132 5662 {
29b0f896
AM		 5663 /* Prohibit these changes in the 64bit mode, since the
5664 lowering is more complicated. */
5665 if (flag_code == CODE_64BIT)
252b5132 5666 {
2b5d6a91 5667 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5668 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5669 i.suffix);
5670 return 0;
252b5132 5671 }
29b0f896 5672#if REGISTER_WARNINGS
cecf1424
JB		 5673 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5674 register_prefix,
5675 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5676 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5677#endif
5678 }
5679 return 1;
5680}
252b5132 5681
29b0f896 5682static int
40fb9820 5683update_imm (unsigned int j)
29b0f896 5684{
bc0844ae 5685 i386_operand_type overlap = i.types[j];
40fb9820
L		 5686 if ((overlap.bitfield.imm8
5687 || overlap.bitfield.imm8s
5688 || overlap.bitfield.imm16
5689 || overlap.bitfield.imm32
5690 || overlap.bitfield.imm32s
5691 || overlap.bitfield.imm64)
0dfbf9d7
L		 5692 && !operand_type_equal (&overlap, &imm8)
5693 && !operand_type_equal (&overlap, &imm8s)
5694 && !operand_type_equal (&overlap, &imm16)
5695 && !operand_type_equal (&overlap, &imm32)
5696 && !operand_type_equal (&overlap, &imm32s)
5697 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5698 {
5699 if (i.suffix)
5700 {
40fb9820
L		 5701 i386_operand_type temp;
5702
0dfbf9d7 5703 operand_type_set (&temp, 0);
7ab9ffdd 5704 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5705 {
5706 temp.bitfield.imm8 = overlap.bitfield.imm8;
5707 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5708 }
5709 else if (i.suffix == WORD_MNEM_SUFFIX)
5710 temp.bitfield.imm16 = overlap.bitfield.imm16;
5711 else if (i.suffix == QWORD_MNEM_SUFFIX)
5712 {
5713 temp.bitfield.imm64 = overlap.bitfield.imm64;
5714 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5715 }
5716 else
5717 temp.bitfield.imm32 = overlap.bitfield.imm32;
5718 overlap = temp;
29b0f896 5719 }
0dfbf9d7
L		 5720 else if (operand_type_equal (&overlap, &imm16_32_32s)
5721 || operand_type_equal (&overlap, &imm16_32)
5722 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5723 {
40fb9820 5724 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5725 overlap = imm16;
40fb9820 5726 else
65da13b5 5727 overlap = imm32s;
29b0f896 5728 }
0dfbf9d7
L		 5729 if (!operand_type_equal (&overlap, &imm8)
5730 && !operand_type_equal (&overlap, &imm8s)
5731 && !operand_type_equal (&overlap, &imm16)
5732 && !operand_type_equal (&overlap, &imm32)
5733 && !operand_type_equal (&overlap, &imm32s)
5734 && !operand_type_equal (&overlap, &imm64))
29b0f896 5735 {
4eed87de
AM		 5736 as_bad (_("no instruction mnemonic suffix given; "
5737 "can't determine immediate size"));
29b0f896
AM		 5738 return 0;
5739 }
5740 }
40fb9820 5741 i.types[j] = overlap;
29b0f896 5742
40fb9820
L		 5743 return 1;
5744}
5745
5746static int
5747finalize_imm (void)
5748{
bc0844ae 5749 unsigned int j, n;
29b0f896 5750
bc0844ae
L		 5751 /* Update the first 2 immediate operands. */
5752 n = i.operands > 2 ? 2 : i.operands;
5753 if (n)
5754 {
5755 for (j = 0; j < n; j++)
5756 if (update_imm (j) == 0)
5757 return 0;
40fb9820 5758
bc0844ae
L		 5759 /* The 3rd operand can't be immediate operand. */
5760 gas_assert (operand_type_check (i.types[2], imm) == 0);
5761 }
29b0f896
AM		 5762
5763 return 1;
5764}
5765
c0f3af97
L		 5766static int
5767bad_implicit_operand (int xmm)
5768{
91d6fa6a
NC		 5769 const char *ireg = xmm ? "xmm0" : "ymm0";
5770
c0f3af97
L		 5771 if (intel_syntax)
5772 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5773 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5774 else
5775 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5776 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5777 return 0;
5778}
5779
29b0f896 5780static int
e3bb37b5 5781process_operands (void)
29b0f896
AM		 5782{
5783 /* Default segment register this instruction will use for memory
5784 accesses. 0 means unknown. This is only for optimizing out
5785 unnecessary segment overrides. */
5786 const seg_entry *default_seg = 0;
5787
2426c15f 5788 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5789 {
91d6fa6a
NC		 5790 unsigned int dupl = i.operands;
5791 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5792 unsigned int j;
5793
c0f3af97 5794 /* The destination must be an xmm register. */
9c2799c2 5795 gas_assert (i.reg_operands
91d6fa6a 5796 && MAX_OPERANDS > dupl
7ab9ffdd 5797 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5798
5799 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5800 {
c0f3af97 5801 /* The first operand is implicit and must be xmm0. */
9c2799c2 5802 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5803 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5804 return bad_implicit_operand (1);
5805
8cd7925b 5806 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5807 {
5808 /* Keep xmm0 for instructions with VEX prefix and 3
5809 sources. */
5810 goto duplicate;
5811 }
e2ec9d29 5812 else
c0f3af97
L		 5813 {
5814 /* We remove the first xmm0 and keep the number of
5815 operands unchanged, which in fact duplicates the
5816 destination. */
5817 for (j = 1; j < i.operands; j++)
5818 {
5819 i.op[j - 1] = i.op[j];
5820 i.types[j - 1] = i.types[j];
5821 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5822 }
5823 }
5824 }
5825 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5826 {
91d6fa6a 5827 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5828 && (i.tm.opcode_modifier.vexsources
5829 == VEX3SOURCES));
c0f3af97
L		 5830
5831 /* Add the implicit xmm0 for instructions with VEX prefix
5832 and 3 sources. */
5833 for (j = i.operands; j > 0; j--)
5834 {
5835 i.op[j] = i.op[j - 1];
5836 i.types[j] = i.types[j - 1];
5837 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5838 }
5839 i.op[0].regs
5840 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5841 i.types[0] = regxmm;
c0f3af97
L		 5842 i.tm.operand_types[0] = regxmm;
5843
5844 i.operands += 2;
5845 i.reg_operands += 2;
5846 i.tm.operands += 2;
5847
91d6fa6a 5848 dupl++;
c0f3af97 5849 dest++;
91d6fa6a
NC		 5850 i.op[dupl] = i.op[dest];
5851 i.types[dupl] = i.types[dest];
5852 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5853 }
c0f3af97
L		 5854 else
5855 {
5856duplicate:
5857 i.operands++;
5858 i.reg_operands++;
5859 i.tm.operands++;
5860
91d6fa6a
NC		 5861 i.op[dupl] = i.op[dest];
5862 i.types[dupl] = i.types[dest];
5863 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5864 }
5865
5866 if (i.tm.opcode_modifier.immext)
5867 process_immext ();
5868 }
5869 else if (i.tm.opcode_modifier.firstxmm0)
5870 {
5871 unsigned int j;
5872
43234a1e 5873 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5874 gas_assert (i.reg_operands
7ab9ffdd 5875 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5876 || operand_type_equal (&i.types[0], &regymm)
5877 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5878 if (register_number (i.op[0].regs) != 0)
c0f3af97 5879 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5880
5881 for (j = 1; j < i.operands; j++)
5882 {
5883 i.op[j - 1] = i.op[j];
5884 i.types[j - 1] = i.types[j];
5885
5886 /* We need to adjust fields in i.tm since they are used by
5887 build_modrm_byte. */
5888 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5889 }
5890
e2ec9d29
L		 5891 i.operands--;
5892 i.reg_operands--;
e2ec9d29
L		 5893 i.tm.operands--;
5894 }
5895 else if (i.tm.opcode_modifier.regkludge)
5896 {
5897 /* The imul $imm, %reg instruction is converted into
5898 imul $imm, %reg, %reg, and the clr %reg instruction
5899 is converted into xor %reg, %reg. */
5900
5901 unsigned int first_reg_op;
5902
5903 if (operand_type_check (i.types[0], reg))
5904 first_reg_op = 0;
5905 else
5906 first_reg_op = 1;
5907 /* Pretend we saw the extra register operand. */
9c2799c2 5908 gas_assert (i.reg_operands == 1
7ab9ffdd 5909 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5910 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5911 i.types[first_reg_op + 1] = i.types[first_reg_op];
5912 i.operands++;
5913 i.reg_operands++;
29b0f896
AM		 5914 }
5915
40fb9820 5916 if (i.tm.opcode_modifier.shortform)
29b0f896 5917 {
40fb9820
L		 5918 if (i.types[0].bitfield.sreg2
5919 || i.types[0].bitfield.sreg3)
29b0f896 5920 {
4eed87de
AM		 5921 if (i.tm.base_opcode == POP_SEG_SHORT
5922 && i.op[0].regs->reg_num == 1)
29b0f896 5923 {
a87af027 5924 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5925 return 0;
29b0f896 5926 }
4eed87de
AM		 5927 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5928 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5929 i.rex |= REX_B;
4eed87de
AM		 5930 }
5931 else
5932 {
7ab9ffdd 5933 /* The register or float register operand is in operand
85f10a01 5934 0 or 1. */
40fb9820 5935 unsigned int op;
7ab9ffdd
L		 5936
5937 if (i.types[0].bitfield.floatreg
5938 || operand_type_check (i.types[0], reg))
5939 op = 0;
5940 else
5941 op = 1;
4eed87de
AM		 5942 /* Register goes in low 3 bits of opcode. */
5943 i.tm.base_opcode |= i.op[op].regs->reg_num;
5944 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5945 i.rex |= REX_B;
40fb9820 5946 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5947 {
4eed87de
AM		 5948 /* Warn about some common errors, but press on regardless.
5949 The first case can be generated by gcc (<= 2.8.1). */
5950 if (i.operands == 2)
5951 {
5952 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5953 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5954 register_prefix, i.op[!intel_syntax].regs->reg_name,
5955 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5956 }
5957 else
5958 {
5959 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5960 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5961 register_prefix, i.op[0].regs->reg_name);
4eed87de 5962 }
29b0f896
AM		 5963 }
5964 }
5965 }
40fb9820 5966 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5967 {
5968 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5969 must be put into the modrm byte). Now, we make the modrm and
5970 index base bytes based on all the info we've collected. */
29b0f896
AM		 5971
5972 default_seg = build_modrm_byte ();
5973 }
8a2ed489 5974 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5975 {
5976 default_seg = &ds;
5977 }
40fb9820 5978 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5979 {
5980 /* For the string instructions that allow a segment override
5981 on one of their operands, the default segment is ds. */
5982 default_seg = &ds;
5983 }
5984
75178d9d
L		 5985 if (i.tm.base_opcode == 0x8d /* lea */
5986 && i.seg[0]
5987 && !quiet_warnings)
30123838 5988 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5989
5990 /* If a segment was explicitly specified, and the specified segment
5991 is not the default, use an opcode prefix to select it. If we
5992 never figured out what the default segment is, then default_seg
5993 will be zero at this point, and the specified segment prefix will
5994 always be used. */
29b0f896
AM		 5995 if ((i.seg[0]) && (i.seg[0] != default_seg))
5996 {
5997 if (!add_prefix (i.seg[0]->seg_prefix))
5998 return 0;
5999 }
6000 return 1;
6001}
6002
6003static const seg_entry *
e3bb37b5 6004build_modrm_byte (void)
29b0f896
AM		 6005{
6006 const seg_entry *default_seg = 0;
c0f3af97 6007 unsigned int source, dest;
8cd7925b 6008 int vex_3_sources;
c0f3af97
L		 6009
6010 /* The first operand of instructions with VEX prefix and 3 sources
6011 must be VEX_Imm4. */
8cd7925b 6012 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6013 if (vex_3_sources)
6014 {
91d6fa6a 6015 unsigned int nds, reg_slot;
4c2c6516 6016 expressionS *exp;
c0f3af97 6017
922d8de8 6018 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6019 && i.tm.opcode_modifier.immext)
6020 {
6021 dest = i.operands - 2;
6022 gas_assert (dest == 3);
6023 }
922d8de8 6024 else
a683cc34 6025 dest = i.operands - 1;
c0f3af97 6026 nds = dest - 1;
922d8de8 6027
a683cc34
SP		 6028 /* There are 2 kinds of instructions:
6029 1. 5 operands: 4 register operands or 3 register operands
6030 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6031 VexW0 or VexW1. The destination must be either XMM, YMM or
6032 ZMM register.
a683cc34
SP		 6033 2. 4 operands: 4 register operands or 3 register operands
6034 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6035 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6036 || (i.reg_operands == 3 && i.mem_operands == 1))
6037 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6038 && (i.tm.opcode_modifier.veximmext
6039 || (i.imm_operands == 1
6040 && i.types[0].bitfield.vec_imm4
6041 && (i.tm.opcode_modifier.vexw == VEXW0
6042 || i.tm.opcode_modifier.vexw == VEXW1)
6043 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6044 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6045 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6046
6047 if (i.imm_operands == 0)
6048 {
6049 /* When there is no immediate operand, generate an 8bit
6050 immediate operand to encode the first operand. */
6051 exp = &im_expressions[i.imm_operands++];
6052 i.op[i.operands].imms = exp;
6053 i.types[i.operands] = imm8;
6054 i.operands++;
6055 /* If VexW1 is set, the first operand is the source and
6056 the second operand is encoded in the immediate operand. */
6057 if (i.tm.opcode_modifier.vexw == VEXW1)
6058 {
6059 source = 0;
6060 reg_slot = 1;
6061 }
6062 else
6063 {
6064 source = 1;
6065 reg_slot = 0;
6066 }
6067
6068 /* FMA swaps REG and NDS. */
6069 if (i.tm.cpu_flags.bitfield.cpufma)
6070 {
6071 unsigned int tmp;
6072 tmp = reg_slot;
6073 reg_slot = nds;
6074 nds = tmp;
6075 }
6076
24981e7b
L		 6077 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6078 &regxmm)
a683cc34 6079 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6080 &regymm)
6081 || operand_type_equal (&i.tm.operand_types[reg_slot],
6082 &regzmm));
a683cc34 6083 exp->X_op = O_constant;
4c692bc7 6084 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6085 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6086 }
922d8de8 6087 else
a683cc34
SP		 6088 {
6089 unsigned int imm_slot;
6090
6091 if (i.tm.opcode_modifier.vexw == VEXW0)
6092 {
6093 /* If VexW0 is set, the third operand is the source and
6094 the second operand is encoded in the immediate
6095 operand. */
6096 source = 2;
6097 reg_slot = 1;
6098 }
6099 else
6100 {
6101 /* VexW1 is set, the second operand is the source and
6102 the third operand is encoded in the immediate
6103 operand. */
6104 source = 1;
6105 reg_slot = 2;
6106 }
6107
6108 if (i.tm.opcode_modifier.immext)
6109 {
6110 /* When ImmExt is set, the immdiate byte is the last
6111 operand. */
6112 imm_slot = i.operands - 1;
6113 source--;
6114 reg_slot--;
6115 }
6116 else
6117 {
6118 imm_slot = 0;
6119
6120 /* Turn on Imm8 so that output_imm will generate it. */
6121 i.types[imm_slot].bitfield.imm8 = 1;
6122 }
6123
24981e7b
L		 6124 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6125 &regxmm)
6126 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6127 &regymm)
6128 || operand_type_equal (&i.tm.operand_types[reg_slot],
6129 &regzmm));
a683cc34 6130 i.op[imm_slot].imms->X_add_number
4c692bc7 6131 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6132 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6133 }
6134
6135 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6136 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6137 &regymm)
6138 || operand_type_equal (&i.tm.operand_types[nds],
6139 &regzmm));
dae39acc 6140 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6141 }
6142 else
6143 source = dest = 0;
29b0f896
AM		 6144
6145 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6146 implicit registers do not count. If there are 3 register
6147 operands, it must be a instruction with VexNDS. For a
6148 instruction with VexNDD, the destination register is encoded
6149 in VEX prefix. If there are 4 register operands, it must be
6150 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6151 if (i.mem_operands == 0
6152 && ((i.reg_operands == 2
2426c15f 6153 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6154 || (i.reg_operands == 3
2426c15f 6155 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6156 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6157 {
cab737b9
L		 6158 switch (i.operands)
6159 {
6160 case 2:
6161 source = 0;
6162 break;
6163 case 3:
c81128dc
L		 6164 /* When there are 3 operands, one of them may be immediate,
6165 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6166 the first operand must be shift count register (cl) or it
6167 is an instruction with VexNDS. */
9c2799c2 6168 gas_assert (i.imm_operands == 1
7ab9ffdd 6169 || (i.imm_operands == 0
2426c15f 6170 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6171 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6172 if (operand_type_check (i.types[0], imm)
6173 || i.types[0].bitfield.shiftcount)
6174 source = 1;
6175 else
6176 source = 0;
cab737b9
L		 6177 break;
6178 case 4:
368d64cc
L		 6179 /* When there are 4 operands, the first two must be 8bit
6180 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6181 one.
6182
6183 For instructions with VexNDS, if the first operand
6184 an imm8, the source operand is the 2nd one. If the last
6185 operand is imm8, the source operand is the first one. */
9c2799c2 6186 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6187 && i.types[0].bitfield.imm8
6188 && i.types[1].bitfield.imm8)
2426c15f 6189 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6190 && i.imm_operands == 1
6191 && (i.types[0].bitfield.imm8
43234a1e
L		 6192 || i.types[i.operands - 1].bitfield.imm8
6193 || i.rounding)));
9f2670f2
L		 6194 if (i.imm_operands == 2)
6195 source = 2;
6196 else
c0f3af97
L		 6197 {
6198 if (i.types[0].bitfield.imm8)
6199 source = 1;
6200 else
6201 source = 0;
6202 }
c0f3af97
L		 6203 break;
6204 case 5:
43234a1e
L		 6205 if (i.tm.opcode_modifier.evex)
6206 {
6207 /* For EVEX instructions, when there are 5 operands, the
6208 first one must be immediate operand. If the second one
6209 is immediate operand, the source operand is the 3th
6210 one. If the last one is immediate operand, the source
6211 operand is the 2nd one. */
6212 gas_assert (i.imm_operands == 2
6213 && i.tm.opcode_modifier.sae
6214 && operand_type_check (i.types[0], imm));
6215 if (operand_type_check (i.types[1], imm))
6216 source = 2;
6217 else if (operand_type_check (i.types[4], imm))
6218 source = 1;
6219 else
6220 abort ();
6221 }
cab737b9
L		 6222 break;
6223 default:
6224 abort ();
6225 }
6226
c0f3af97
L		 6227 if (!vex_3_sources)
6228 {
6229 dest = source + 1;
6230
43234a1e
L		 6231 /* RC/SAE operand could be between DEST and SRC. That happens
6232 when one operand is GPR and the other one is XMM/YMM/ZMM
6233 register. */
6234 if (i.rounding && i.rounding->operand == (int) dest)
6235 dest++;
6236
2426c15f 6237 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6238 {
43234a1e
L		 6239 /* For instructions with VexNDS, the register-only source
6240 operand must be 32/64bit integer, XMM, YMM or ZMM
6241 register. It is encoded in VEX prefix. We need to
6242 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6243
6244 i386_operand_type op;
6245 unsigned int vvvv;
6246
6247 /* Check register-only source operand when two source
6248 operands are swapped. */
6249 if (!i.tm.operand_types[source].bitfield.baseindex
6250 && i.tm.operand_types[dest].bitfield.baseindex)
6251 {
6252 vvvv = source;
6253 source = dest;
6254 }
6255 else
6256 vvvv = dest;
6257
6258 op = i.tm.operand_types[vvvv];
fa99fab2 6259 op.bitfield.regmem = 0;
c0f3af97 6260 if ((dest + 1) >= i.operands
ac4eb736
AM		 6261 || (!op.bitfield.reg32
6262 && op.bitfield.reg64
f12dc422 6263 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6264 && !operand_type_equal (&op, &regymm)
6265 && !operand_type_equal (&op, &regzmm)
6266 && !operand_type_equal (&op, &regmask)))
c0f3af97 6267 abort ();
f12dc422 6268 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6269 dest++;
6270 }
6271 }
29b0f896
AM		 6272
6273 i.rm.mode = 3;
6274 /* One of the register operands will be encoded in the i.tm.reg
6275 field, the other in the combined i.tm.mode and i.tm.regmem
6276 fields. If no form of this instruction supports a memory
6277 destination operand, then we assume the source operand may
6278 sometimes be a memory operand and so we need to store the
6279 destination in the i.rm.reg field. */
40fb9820
L		 6280 if (!i.tm.operand_types[dest].bitfield.regmem
6281 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6282 {
6283 i.rm.reg = i.op[dest].regs->reg_num;
6284 i.rm.regmem = i.op[source].regs->reg_num;
6285 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6286 i.rex |= REX_R;
43234a1e
L		 6287 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6288 i.vrex |= REX_R;
29b0f896 6289 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6290 i.rex |= REX_B;
43234a1e
L		 6291 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6292 i.vrex |= REX_B;
29b0f896
AM		 6293 }
6294 else
6295 {
6296 i.rm.reg = i.op[source].regs->reg_num;
6297 i.rm.regmem = i.op[dest].regs->reg_num;
6298 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6299 i.rex |= REX_B;
43234a1e
L		 6300 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6301 i.vrex |= REX_B;
29b0f896 6302 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6303 i.rex |= REX_R;
43234a1e
L		 6304 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6305 i.vrex |= REX_R;
29b0f896 6306 }
161a04f6 6307 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6308 {
40fb9820
L		 6309 if (!i.types[0].bitfield.control
6310 && !i.types[1].bitfield.control)
c4a530c5 6311 abort ();
161a04f6 6312 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6313 add_prefix (LOCK_PREFIX_OPCODE);
6314 }
29b0f896
AM		 6315 }
6316 else
6317 { /* If it's not 2 reg operands... */
c0f3af97
L		 6318 unsigned int mem;
6319
29b0f896
AM		 6320 if (i.mem_operands)
6321 {
6322 unsigned int fake_zero_displacement = 0;
99018f42 6323 unsigned int op;
4eed87de 6324
7ab9ffdd
L		 6325 for (op = 0; op < i.operands; op++)
6326 if (operand_type_check (i.types[op], anymem))
6327 break;
7ab9ffdd 6328 gas_assert (op < i.operands);
29b0f896 6329
6c30d220
L		 6330 if (i.tm.opcode_modifier.vecsib)
6331 {
6332 if (i.index_reg->reg_num == RegEiz
6333 || i.index_reg->reg_num == RegRiz)
6334 abort ();
6335
6336 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6337 if (!i.base_reg)
6338 {
6339 i.sib.base = NO_BASE_REGISTER;
6340 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6341 /* No Vec_Disp8 if there is no base. */
6342 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6343 i.types[op].bitfield.disp8 = 0;
6344 i.types[op].bitfield.disp16 = 0;
6345 i.types[op].bitfield.disp64 = 0;
6346 if (flag_code != CODE_64BIT)
6347 {
6348 /* Must be 32 bit */
6349 i.types[op].bitfield.disp32 = 1;
6350 i.types[op].bitfield.disp32s = 0;
6351 }
6352 else
6353 {
6354 i.types[op].bitfield.disp32 = 0;
6355 i.types[op].bitfield.disp32s = 1;
6356 }
6357 }
6358 i.sib.index = i.index_reg->reg_num;
6359 if ((i.index_reg->reg_flags & RegRex) != 0)
6360 i.rex |= REX_X;
43234a1e
L		 6361 if ((i.index_reg->reg_flags & RegVRex) != 0)
6362 i.vrex |= REX_X;
6c30d220
L		 6363 }
6364
29b0f896
AM		 6365 default_seg = &ds;
6366
6367 if (i.base_reg == 0)
6368 {
6369 i.rm.mode = 0;
6370 if (!i.disp_operands)
6c30d220
L		 6371 {
6372 fake_zero_displacement = 1;
6373 /* Instructions with VSIB byte need 32bit displacement
6374 if there is no base register. */
6375 if (i.tm.opcode_modifier.vecsib)
6376 i.types[op].bitfield.disp32 = 1;
6377 }
29b0f896
AM		 6378 if (i.index_reg == 0)
6379 {
6c30d220 6380 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6381 /* Operand is just <disp> */
20f0a1fc 6382 if (flag_code == CODE_64BIT)
29b0f896
AM		 6383 {
6384 /* 64bit mode overwrites the 32bit absolute
6385 addressing by RIP relative addressing and
6386 absolute addressing is encoded by one of the
6387 redundant SIB forms. */
6388 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6389 i.sib.base = NO_BASE_REGISTER;
6390 i.sib.index = NO_INDEX_REGISTER;
fc225355 6391 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6392 ? disp32s : disp32);
20f0a1fc 6393 }
fc225355
L		 6394 else if ((flag_code == CODE_16BIT)
6395 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6396 {
6397 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6398 i.types[op] = disp16;
20f0a1fc
NC		 6399 }
6400 else
6401 {
6402 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6403 i.types[op] = disp32;
29b0f896
AM		 6404 }
6405 }
6c30d220 6406 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6407 {
6c30d220 6408 /* !i.base_reg && i.index_reg */
db51cc60
L		 6409 if (i.index_reg->reg_num == RegEiz
6410 || i.index_reg->reg_num == RegRiz)
6411 i.sib.index = NO_INDEX_REGISTER;
6412 else
6413 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6414 i.sib.base = NO_BASE_REGISTER;
6415 i.sib.scale = i.log2_scale_factor;
6416 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6417 /* No Vec_Disp8 if there is no base. */
6418 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6419 i.types[op].bitfield.disp8 = 0;
6420 i.types[op].bitfield.disp16 = 0;
6421 i.types[op].bitfield.disp64 = 0;
29b0f896 6422 if (flag_code != CODE_64BIT)
40fb9820
L		 6423 {
6424 /* Must be 32 bit */
6425 i.types[op].bitfield.disp32 = 1;
6426 i.types[op].bitfield.disp32s = 0;
6427 }
29b0f896 6428 else
40fb9820
L		 6429 {
6430 i.types[op].bitfield.disp32 = 0;
6431 i.types[op].bitfield.disp32s = 1;
6432 }
29b0f896 6433 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6434 i.rex |= REX_X;
29b0f896
AM		 6435 }
6436 }
6437 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6438 else if (i.base_reg->reg_num == RegRip ||
6439 i.base_reg->reg_num == RegEip)
29b0f896 6440 {
6c30d220 6441 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6442 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6443 i.types[op].bitfield.disp8 = 0;
6444 i.types[op].bitfield.disp16 = 0;
6445 i.types[op].bitfield.disp32 = 0;
6446 i.types[op].bitfield.disp32s = 1;
6447 i.types[op].bitfield.disp64 = 0;
43234a1e 6448 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6449 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6450 if (! i.disp_operands)
6451 fake_zero_displacement = 1;
29b0f896 6452 }
40fb9820 6453 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6454 {
6c30d220 6455 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6456 switch (i.base_reg->reg_num)
6457 {
6458 case 3: /* (%bx) */
6459 if (i.index_reg == 0)
6460 i.rm.regmem = 7;
6461 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6462 i.rm.regmem = i.index_reg->reg_num - 6;
6463 break;
6464 case 5: /* (%bp) */
6465 default_seg = &ss;
6466 if (i.index_reg == 0)
6467 {
6468 i.rm.regmem = 6;
40fb9820 6469 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6470 {
6471 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6472 if (i.tm.operand_types[op].bitfield.vec_disp8)
6473 i.types[op].bitfield.vec_disp8 = 1;
6474 else
6475 i.types[op].bitfield.disp8 = 1;
252b5132 6476 fake_zero_displacement = 1;
29b0f896
AM		 6477 }
6478 }
6479 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6480 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6481 break;
6482 default: /* (%si) -> 4 or (%di) -> 5 */
6483 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6484 }
6485 i.rm.mode = mode_from_disp_size (i.types[op]);
6486 }
6487 else /* i.base_reg and 32/64 bit mode */
6488 {
6489 if (flag_code == CODE_64BIT
40fb9820
L		 6490 && operand_type_check (i.types[op], disp))
6491 {
6492 i386_operand_type temp;
0dfbf9d7 6493 operand_type_set (&temp, 0);
40fb9820 6494 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6495 temp.bitfield.vec_disp8
6496 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6497 i.types[op] = temp;
6498 if (i.prefix[ADDR_PREFIX] == 0)
6499 i.types[op].bitfield.disp32s = 1;
6500 else
6501 i.types[op].bitfield.disp32 = 1;
6502 }
20f0a1fc 6503
6c30d220
L		 6504 if (!i.tm.opcode_modifier.vecsib)
6505 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6506 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6507 i.rex |= REX_B;
29b0f896
AM		 6508 i.sib.base = i.base_reg->reg_num;
6509 /* x86-64 ignores REX prefix bit here to avoid decoder
6510 complications. */
848930b2
JB		 6511 if (!(i.base_reg->reg_flags & RegRex)
6512 && (i.base_reg->reg_num == EBP_REG_NUM
6513 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6514 default_seg = &ss;
848930b2 6515 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6516 {
848930b2 6517 fake_zero_displacement = 1;
43234a1e
L		 6518 if (i.tm.operand_types [op].bitfield.vec_disp8)
6519 i.types[op].bitfield.vec_disp8 = 1;
6520 else
6521 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6522 }
6523 i.sib.scale = i.log2_scale_factor;
6524 if (i.index_reg == 0)
6525 {
6c30d220 6526 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6527 /* <disp>(%esp) becomes two byte modrm with no index
6528 register. We've already stored the code for esp
6529 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6530 Any base register besides %esp will not use the
6531 extra modrm byte. */
6532 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6533 }
6c30d220 6534 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6535 {
db51cc60
L		 6536 if (i.index_reg->reg_num == RegEiz
6537 || i.index_reg->reg_num == RegRiz)
6538 i.sib.index = NO_INDEX_REGISTER;
6539 else
6540 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6541 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6542 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6543 i.rex |= REX_X;
29b0f896 6544 }
67a4f2b7
AO		 6545
6546 if (i.disp_operands
6547 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6548 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6549 i.rm.mode = 0;
6550 else
a501d77e
L		 6551 {
6552 if (!fake_zero_displacement
6553 && !i.disp_operands
6554 && i.disp_encoding)
6555 {
6556 fake_zero_displacement = 1;
6557 if (i.disp_encoding == disp_encoding_8bit)
6558 i.types[op].bitfield.disp8 = 1;
6559 else
6560 i.types[op].bitfield.disp32 = 1;
6561 }
6562 i.rm.mode = mode_from_disp_size (i.types[op]);
6563 }
29b0f896 6564 }
252b5132 6565
29b0f896
AM		 6566 if (fake_zero_displacement)
6567 {
6568 /* Fakes a zero displacement assuming that i.types[op]
6569 holds the correct displacement size. */
6570 expressionS *exp;
6571
9c2799c2 6572 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6573 exp = &disp_expressions[i.disp_operands++];
6574 i.op[op].disps = exp;
6575 exp->X_op = O_constant;
6576 exp->X_add_number = 0;
6577 exp->X_add_symbol = (symbolS *) 0;
6578 exp->X_op_symbol = (symbolS *) 0;
6579 }
c0f3af97
L		 6580
6581 mem = op;
29b0f896 6582 }
c0f3af97
L		 6583 else
6584 mem = ~0;
252b5132 6585
8c43a48b 6586 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6587 {
6588 if (operand_type_check (i.types[0], imm))
6589 i.vex.register_specifier = NULL;
6590 else
6591 {
6592 /* VEX.vvvv encodes one of the sources when the first
6593 operand is not an immediate. */
1ef99a7b 6594 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6595 i.vex.register_specifier = i.op[0].regs;
6596 else
6597 i.vex.register_specifier = i.op[1].regs;
6598 }
6599
6600 /* Destination is a XMM register encoded in the ModRM.reg
6601 and VEX.R bit. */
6602 i.rm.reg = i.op[2].regs->reg_num;
6603 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6604 i.rex |= REX_R;
6605
6606 /* ModRM.rm and VEX.B encodes the other source. */
6607 if (!i.mem_operands)
6608 {
6609 i.rm.mode = 3;
6610
1ef99a7b 6611 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6612 i.rm.regmem = i.op[1].regs->reg_num;
6613 else
6614 i.rm.regmem = i.op[0].regs->reg_num;
6615
6616 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6617 i.rex |= REX_B;
6618 }
6619 }
2426c15f 6620 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6621 {
6622 i.vex.register_specifier = i.op[2].regs;
6623 if (!i.mem_operands)
6624 {
6625 i.rm.mode = 3;
6626 i.rm.regmem = i.op[1].regs->reg_num;
6627 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6628 i.rex |= REX_B;
6629 }
6630 }
29b0f896
AM		 6631 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6632 (if any) based on i.tm.extension_opcode. Again, we must be
6633 careful to make sure that segment/control/debug/test/MMX
6634 registers are coded into the i.rm.reg field. */
f88c9eb0 6635 else if (i.reg_operands)
29b0f896 6636 {
99018f42 6637 unsigned int op;
7ab9ffdd
L		 6638 unsigned int vex_reg = ~0;
6639
6640 for (op = 0; op < i.operands; op++)
6641 if (i.types[op].bitfield.reg8
6642 || i.types[op].bitfield.reg16
6643 || i.types[op].bitfield.reg32
6644 || i.types[op].bitfield.reg64
6645 || i.types[op].bitfield.regmmx
6646 || i.types[op].bitfield.regxmm
6647 || i.types[op].bitfield.regymm
7e8b059b 6648 || i.types[op].bitfield.regbnd
43234a1e
L		 6649 || i.types[op].bitfield.regzmm
6650 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6651 || i.types[op].bitfield.sreg2
6652 || i.types[op].bitfield.sreg3
6653 || i.types[op].bitfield.control
6654 || i.types[op].bitfield.debug
6655 || i.types[op].bitfield.test)
6656 break;
c0209578 6657
7ab9ffdd
L		 6658 if (vex_3_sources)
6659 op = dest;
2426c15f 6660 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6661 {
6662 /* For instructions with VexNDS, the register-only
6663 source operand is encoded in VEX prefix. */
6664 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6665
7ab9ffdd 6666 if (op > mem)
c0f3af97 6667 {
7ab9ffdd
L		 6668 vex_reg = op++;
6669 gas_assert (op < i.operands);
c0f3af97
L		 6670 }
6671 else
c0f3af97 6672 {
f12dc422
L		 6673 /* Check register-only source operand when two source
6674 operands are swapped. */
6675 if (!i.tm.operand_types[op].bitfield.baseindex
6676 && i.tm.operand_types[op + 1].bitfield.baseindex)
6677 {
6678 vex_reg = op;
6679 op += 2;
6680 gas_assert (mem == (vex_reg + 1)
6681 && op < i.operands);
6682 }
6683 else
6684 {
6685 vex_reg = op + 1;
6686 gas_assert (vex_reg < i.operands);
6687 }
c0f3af97 6688 }
7ab9ffdd 6689 }
2426c15f 6690 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6691 {
f12dc422 6692 /* For instructions with VexNDD, the register destination
7ab9ffdd 6693 is encoded in VEX prefix. */
f12dc422
L		 6694 if (i.mem_operands == 0)
6695 {
6696 /* There is no memory operand. */
6697 gas_assert ((op + 2) == i.operands);
6698 vex_reg = op + 1;
6699 }
6700 else
8d63c93e 6701 {
f12dc422
L		 6702 /* There are only 2 operands. */
6703 gas_assert (op < 2 && i.operands == 2);
6704 vex_reg = 1;
6705 }
7ab9ffdd
L		 6706 }
6707 else
6708 gas_assert (op < i.operands);
99018f42 6709
7ab9ffdd
L		 6710 if (vex_reg != (unsigned int) ~0)
6711 {
f12dc422 6712 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6713
f12dc422
L		 6714 if (type->bitfield.reg32 != 1
6715 && type->bitfield.reg64 != 1
6716 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6717 && !operand_type_equal (type, &regymm)
6718 && !operand_type_equal (type, &regzmm)
6719 && !operand_type_equal (type, &regmask))
7ab9ffdd 6720 abort ();
f88c9eb0 6721
7ab9ffdd
L		 6722 i.vex.register_specifier = i.op[vex_reg].regs;
6723 }
6724
1b9f0c97
L		 6725 /* Don't set OP operand twice. */
6726 if (vex_reg != op)
7ab9ffdd 6727 {
1b9f0c97
L		 6728 /* If there is an extension opcode to put here, the
6729 register number must be put into the regmem field. */
6730 if (i.tm.extension_opcode != None)
6731 {
6732 i.rm.regmem = i.op[op].regs->reg_num;
6733 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6734 i.rex |= REX_B;
43234a1e
L		 6735 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6736 i.vrex |= REX_B;
1b9f0c97
L		 6737 }
6738 else
6739 {
6740 i.rm.reg = i.op[op].regs->reg_num;
6741 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6742 i.rex |= REX_R;
43234a1e
L		 6743 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6744 i.vrex |= REX_R;
1b9f0c97 6745 }
7ab9ffdd 6746 }
252b5132 6747
29b0f896
AM		 6748 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6749 must set it to 3 to indicate this is a register operand
6750 in the regmem field. */
6751 if (!i.mem_operands)
6752 i.rm.mode = 3;
6753 }
252b5132 6754
29b0f896 6755 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6756 if (i.tm.extension_opcode != None)
29b0f896
AM		 6757 i.rm.reg = i.tm.extension_opcode;
6758 }
6759 return default_seg;
6760}
252b5132 6761
29b0f896 6762static void
e3bb37b5 6763output_branch (void)
29b0f896
AM		 6764{
6765 char *p;
f8a5c266 6766 int size;
29b0f896
AM		 6767 int code16;
6768 int prefix;
6769 relax_substateT subtype;
6770 symbolS *sym;
6771 offsetT off;
6772
f8a5c266 6773 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6774 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6775
6776 prefix = 0;
6777 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6778 {
29b0f896
AM		 6779 prefix = 1;
6780 i.prefixes -= 1;
6781 code16 ^= CODE16;
252b5132 6782 }
29b0f896
AM		 6783 /* Pentium4 branch hints. */
6784 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6785 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6786 {
29b0f896
AM		 6787 prefix++;
6788 i.prefixes--;
6789 }
6790 if (i.prefix[REX_PREFIX] != 0)
6791 {
6792 prefix++;
6793 i.prefixes--;
2f66722d
AM		 6794 }
6795
7e8b059b
L		 6796 /* BND prefixed jump. */
6797 if (i.prefix[BND_PREFIX] != 0)
6798 {
6799 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6800 i.prefixes -= 1;
6801 }
6802
29b0f896
AM		 6803 if (i.prefixes != 0 && !intel_syntax)
6804 as_warn (_("skipping prefixes on this instruction"));
6805
6806 /* It's always a symbol; End frag & setup for relax.
6807 Make sure there is enough room in this frag for the largest
6808 instruction we may generate in md_convert_frag. This is 2
6809 bytes for the opcode and room for the prefix and largest
6810 displacement. */
6811 frag_grow (prefix + 2 + 4);
6812 /* Prefix and 1 opcode byte go in fr_fix. */
6813 p = frag_more (prefix + 1);
6814 if (i.prefix[DATA_PREFIX] != 0)
6815 *p++ = DATA_PREFIX_OPCODE;
6816 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6817 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6818 *p++ = i.prefix[SEG_PREFIX];
6819 if (i.prefix[REX_PREFIX] != 0)
6820 *p++ = i.prefix[REX_PREFIX];
6821 *p = i.tm.base_opcode;
6822
6823 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6824 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6825 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6826 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6827 else
f8a5c266 6828 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6829 subtype |= code16;
3e73aa7c 6830
29b0f896
AM		 6831 sym = i.op[0].disps->X_add_symbol;
6832 off = i.op[0].disps->X_add_number;
3e73aa7c 6833
29b0f896
AM		 6834 if (i.op[0].disps->X_op != O_constant
6835 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6836 {
29b0f896
AM		 6837 /* Handle complex expressions. */
6838 sym = make_expr_symbol (i.op[0].disps);
6839 off = 0;
6840 }
3e73aa7c 6841
29b0f896
AM		 6842 /* 1 possible extra opcode + 4 byte displacement go in var part.
6843 Pass reloc in fr_var. */
d258b828 6844 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6845}
3e73aa7c 6846
29b0f896 6847static void
e3bb37b5 6848output_jump (void)
29b0f896
AM		 6849{
6850 char *p;
6851 int size;
3e02c1cc 6852 fixS *fixP;
29b0f896 6853
40fb9820 6854 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6855 {
6856 /* This is a loop or jecxz type instruction. */
6857 size = 1;
6858 if (i.prefix[ADDR_PREFIX] != 0)
6859 {
6860 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6861 i.prefixes -= 1;
6862 }
6863 /* Pentium4 branch hints. */
6864 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6865 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6866 {
6867 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6868 i.prefixes--;
3e73aa7c
JH		 6869 }
6870 }
29b0f896
AM		 6871 else
6872 {
6873 int code16;
3e73aa7c 6874
29b0f896
AM		 6875 code16 = 0;
6876 if (flag_code == CODE_16BIT)
6877 code16 = CODE16;
3e73aa7c 6878
29b0f896
AM		 6879 if (i.prefix[DATA_PREFIX] != 0)
6880 {
6881 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6882 i.prefixes -= 1;
6883 code16 ^= CODE16;
6884 }
252b5132 6885
29b0f896
AM		 6886 size = 4;
6887 if (code16)
6888 size = 2;
6889 }
9fcc94b6 6890
29b0f896
AM		 6891 if (i.prefix[REX_PREFIX] != 0)
6892 {
6893 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6894 i.prefixes -= 1;
6895 }
252b5132 6896
7e8b059b
L		 6897 /* BND prefixed jump. */
6898 if (i.prefix[BND_PREFIX] != 0)
6899 {
6900 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6901 i.prefixes -= 1;
6902 }
6903
29b0f896
AM		 6904 if (i.prefixes != 0 && !intel_syntax)
6905 as_warn (_("skipping prefixes on this instruction"));
e0890092 6906
42164a71
L		 6907 p = frag_more (i.tm.opcode_length + size);
6908 switch (i.tm.opcode_length)
6909 {
6910 case 2:
6911 *p++ = i.tm.base_opcode >> 8;
6912 case 1:
6913 *p++ = i.tm.base_opcode;
6914 break;
6915 default:
6916 abort ();
6917 }
e0890092 6918
3e02c1cc 6919 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6920 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6921
6922 /* All jumps handled here are signed, but don't use a signed limit
6923 check for 32 and 16 bit jumps as we want to allow wrap around at
6924 4G and 64k respectively. */
6925 if (size == 1)
6926 fixP->fx_signed = 1;
29b0f896 6927}
e0890092 6928
29b0f896 6929static void
e3bb37b5 6930output_interseg_jump (void)
29b0f896
AM		 6931{
6932 char *p;
6933 int size;
6934 int prefix;
6935 int code16;
252b5132 6936
29b0f896
AM		 6937 code16 = 0;
6938 if (flag_code == CODE_16BIT)
6939 code16 = CODE16;
a217f122 6940
29b0f896
AM		 6941 prefix = 0;
6942 if (i.prefix[DATA_PREFIX] != 0)
6943 {
6944 prefix = 1;
6945 i.prefixes -= 1;
6946 code16 ^= CODE16;
6947 }
6948 if (i.prefix[REX_PREFIX] != 0)
6949 {
6950 prefix++;
6951 i.prefixes -= 1;
6952 }
252b5132 6953
29b0f896
AM		 6954 size = 4;
6955 if (code16)
6956 size = 2;
252b5132 6957
29b0f896
AM		 6958 if (i.prefixes != 0 && !intel_syntax)
6959 as_warn (_("skipping prefixes on this instruction"));
252b5132 6960
29b0f896
AM		 6961 /* 1 opcode; 2 segment; offset */
6962 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6963
29b0f896
AM		 6964 if (i.prefix[DATA_PREFIX] != 0)
6965 *p++ = DATA_PREFIX_OPCODE;
252b5132 6966
29b0f896
AM		 6967 if (i.prefix[REX_PREFIX] != 0)
6968 *p++ = i.prefix[REX_PREFIX];
252b5132 6969
29b0f896
AM		 6970 *p++ = i.tm.base_opcode;
6971 if (i.op[1].imms->X_op == O_constant)
6972 {
6973 offsetT n = i.op[1].imms->X_add_number;
252b5132 6974
29b0f896
AM		 6975 if (size == 2
6976 && !fits_in_unsigned_word (n)
6977 && !fits_in_signed_word (n))
6978 {
6979 as_bad (_("16-bit jump out of range"));
6980 return;
6981 }
6982 md_number_to_chars (p, n, size);
6983 }
6984 else
6985 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6986 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6987 if (i.op[0].imms->X_op != O_constant)
6988 as_bad (_("can't handle non absolute segment in `%s'"),
6989 i.tm.name);
6990 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6991}
a217f122 6992
29b0f896 6993static void
e3bb37b5 6994output_insn (void)
29b0f896 6995{
2bbd9c25
JJ		 6996 fragS *insn_start_frag;
6997 offsetT insn_start_off;
6998
29b0f896
AM		 6999 /* Tie dwarf2 debug info to the address at the start of the insn.
7000 We can't do this after the insn has been output as the current
7001 frag may have been closed off. eg. by frag_var. */
7002 dwarf2_emit_insn (0);
7003
2bbd9c25
JJ		 7004 insn_start_frag = frag_now;
7005 insn_start_off = frag_now_fix ();
7006
29b0f896 7007 /* Output jumps. */
40fb9820 7008 if (i.tm.opcode_modifier.jump)
29b0f896 7009 output_branch ();
40fb9820
L		 7010 else if (i.tm.opcode_modifier.jumpbyte
7011 || i.tm.opcode_modifier.jumpdword)
29b0f896 7012 output_jump ();
40fb9820 7013 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7014 output_interseg_jump ();
7015 else
7016 {
7017 /* Output normal instructions here. */
7018 char *p;
7019 unsigned char *q;
47465058 7020 unsigned int j;
331d2d0d 7021 unsigned int prefix;
4dffcebc 7022
e4e00185
AS		 7023 if (avoid_fence
7024 && i.tm.base_opcode == 0xfae
7025 && i.operands == 1
7026 && i.imm_operands == 1
7027 && (i.op[0].imms->X_add_number == 0xe8
7028 || i.op[0].imms->X_add_number == 0xf0
7029 || i.op[0].imms->X_add_number == 0xf8))
7030 {
7031 /* Encode lfence, mfence, and sfence as
7032 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7033 offsetT val = 0x240483f0ULL;
7034 p = frag_more (5);
7035 md_number_to_chars (p, val, 5);
7036 return;
7037 }
7038
d022bddd
IT		 7039 /* Some processors fail on LOCK prefix. This options makes
7040 assembler ignore LOCK prefix and serves as a workaround. */
7041 if (omit_lock_prefix)
7042 {
7043 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7044 return;
7045 i.prefix[LOCK_PREFIX] = 0;
7046 }
7047
43234a1e
L		 7048 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7049 don't need the explicit prefix. */
7050 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7051 {
c0f3af97 7052 switch (i.tm.opcode_length)
bc4bd9ab 7053 {
c0f3af97
L		 7054 case 3:
7055 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7056 {
c0f3af97
L		 7057 prefix = (i.tm.base_opcode >> 24) & 0xff;
7058 goto check_prefix;
7059 }
7060 break;
7061 case 2:
7062 if ((i.tm.base_opcode & 0xff0000) != 0)
7063 {
7064 prefix = (i.tm.base_opcode >> 16) & 0xff;
7065 if (i.tm.cpu_flags.bitfield.cpupadlock)
7066 {
4dffcebc 7067check_prefix:
c0f3af97 7068 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7069 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7070 != REPE_PREFIX_OPCODE))
7071 add_prefix (prefix);
7072 }
7073 else
4dffcebc
L		 7074 add_prefix (prefix);
7075 }
c0f3af97
L		 7076 break;
7077 case 1:
7078 break;
7079 default:
7080 abort ();
bc4bd9ab 7081 }
c0f3af97 7082
6d19a37a 7083#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7084 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7085 R_X86_64_GOTTPOFF relocation so that linker can safely
7086 perform IE->LE optimization. */
7087 if (x86_elf_abi == X86_64_X32_ABI
7088 && i.operands == 2
7089 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7090 && i.prefix[REX_PREFIX] == 0)
7091 add_prefix (REX_OPCODE);
6d19a37a 7092#endif
cf61b747 7093
c0f3af97
L		 7094 /* The prefix bytes. */
7095 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7096 if (*q)
7097 FRAG_APPEND_1_CHAR (*q);
0f10071e 7098 }
ae5c1c7b 7099 else
c0f3af97
L		 7100 {
7101 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7102 if (*q)
7103 switch (j)
7104 {
7105 case REX_PREFIX:
7106 /* REX byte is encoded in VEX prefix. */
7107 break;
7108 case SEG_PREFIX:
7109 case ADDR_PREFIX:
7110 FRAG_APPEND_1_CHAR (*q);
7111 break;
7112 default:
7113 /* There should be no other prefixes for instructions
7114 with VEX prefix. */
7115 abort ();
7116 }
7117
43234a1e
L		 7118 /* For EVEX instructions i.vrex should become 0 after
7119 build_evex_prefix. For VEX instructions upper 16 registers
7120 aren't available, so VREX should be 0. */
7121 if (i.vrex)
7122 abort ();
c0f3af97
L		 7123 /* Now the VEX prefix. */
7124 p = frag_more (i.vex.length);
7125 for (j = 0; j < i.vex.length; j++)
7126 p[j] = i.vex.bytes[j];
7127 }
252b5132 7128
29b0f896 7129 /* Now the opcode; be careful about word order here! */
4dffcebc 7130 if (i.tm.opcode_length == 1)
29b0f896
AM		 7131 {
7132 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7133 }
7134 else
7135 {
4dffcebc 7136 switch (i.tm.opcode_length)
331d2d0d 7137 {
43234a1e
L		 7138 case 4:
7139 p = frag_more (4);
7140 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7141 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7142 break;
4dffcebc 7143 case 3:
331d2d0d
L		 7144 p = frag_more (3);
7145 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7146 break;
7147 case 2:
7148 p = frag_more (2);
7149 break;
7150 default:
7151 abort ();
7152 break;
331d2d0d 7153 }
0f10071e 7154
29b0f896
AM		 7155 /* Put out high byte first: can't use md_number_to_chars! */
7156 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7157 *p = i.tm.base_opcode & 0xff;
7158 }
3e73aa7c 7159
29b0f896 7160 /* Now the modrm byte and sib byte (if present). */
40fb9820 7161 if (i.tm.opcode_modifier.modrm)
29b0f896 7162 {
4a3523fa
L		 7163 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7164 | i.rm.reg << 3
7165 | i.rm.mode << 6));
29b0f896
AM		 7166 /* If i.rm.regmem == ESP (4)
7167 && i.rm.mode != (Register mode)
7168 && not 16 bit
7169 ==> need second modrm byte. */
7170 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7171 && i.rm.mode != 3
40fb9820 7172 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7173 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7174 | i.sib.index << 3
7175 | i.sib.scale << 6));
29b0f896 7176 }
3e73aa7c 7177
29b0f896 7178 if (i.disp_operands)
2bbd9c25 7179 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7180
29b0f896 7181 if (i.imm_operands)
2bbd9c25 7182 output_imm (insn_start_frag, insn_start_off);
29b0f896 7183 }
252b5132 7184
29b0f896
AM		 7185#ifdef DEBUG386
7186 if (flag_debug)
7187 {
7b81dfbb 7188 pi ("" /*line*/, &i);
29b0f896
AM		 7189 }
7190#endif /* DEBUG386 */
7191}
252b5132 7192
e205caa7
L		 7193/* Return the size of the displacement operand N. */
7194
7195static int
7196disp_size (unsigned int n)
7197{
7198 int size = 4;
43234a1e
L		 7199
7200 /* Vec_Disp8 has to be 8bit. */
7201 if (i.types[n].bitfield.vec_disp8)
7202 size = 1;
7203 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7204 size = 8;
7205 else if (i.types[n].bitfield.disp8)
7206 size = 1;
7207 else if (i.types[n].bitfield.disp16)
7208 size = 2;
e205caa7
L		 7209 return size;
7210}
7211
7212/* Return the size of the immediate operand N. */
7213
7214static int
7215imm_size (unsigned int n)
7216{
7217 int size = 4;
40fb9820
L		 7218 if (i.types[n].bitfield.imm64)
7219 size = 8;
7220 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7221 size = 1;
7222 else if (i.types[n].bitfield.imm16)
7223 size = 2;
e205caa7
L		 7224 return size;
7225}
7226
29b0f896 7227static void
64e74474 7228output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7229{
7230 char *p;
7231 unsigned int n;
252b5132 7232
29b0f896
AM		 7233 for (n = 0; n < i.operands; n++)
7234 {
43234a1e
L		 7235 if (i.types[n].bitfield.vec_disp8
7236 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7237 {
7238 if (i.op[n].disps->X_op == O_constant)
7239 {
e205caa7 7240 int size = disp_size (n);
43234a1e 7241 offsetT val = i.op[n].disps->X_add_number;
252b5132 7242
43234a1e
L		 7243 if (i.types[n].bitfield.vec_disp8)
7244 val >>= i.memshift;
7245 val = offset_in_range (val, size);
29b0f896
AM		 7246 p = frag_more (size);
7247 md_number_to_chars (p, val, size);
7248 }
7249 else
7250 {
f86103b7 7251 enum bfd_reloc_code_real reloc_type;
e205caa7 7252 int size = disp_size (n);
40fb9820 7253 int sign = i.types[n].bitfield.disp32s;
29b0f896 7254 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7255 fixS *fixP;
29b0f896 7256
e205caa7 7257 /* We can't have 8 bit displacement here. */
9c2799c2 7258 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7259
29b0f896
AM		 7260 /* The PC relative address is computed relative
7261 to the instruction boundary, so in case immediate
7262 fields follows, we need to adjust the value. */
7263 if (pcrel && i.imm_operands)
7264 {
29b0f896 7265 unsigned int n1;
e205caa7 7266 int sz = 0;
252b5132 7267
29b0f896 7268 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7269 if (operand_type_check (i.types[n1], imm))
252b5132 7270 {
e205caa7
L		 7271 /* Only one immediate is allowed for PC
7272 relative address. */
9c2799c2 7273 gas_assert (sz == 0);
e205caa7
L		 7274 sz = imm_size (n1);
7275 i.op[n].disps->X_add_number -= sz;
252b5132 7276 }
29b0f896 7277 /* We should find the immediate. */
9c2799c2 7278 gas_assert (sz != 0);
29b0f896 7279 }
520dc8e8 7280
29b0f896 7281 p = frag_more (size);
d258b828 7282 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7283 if (GOT_symbol
2bbd9c25 7284 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7285 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7286 || reloc_type == BFD_RELOC_X86_64_32S
7287 || (reloc_type == BFD_RELOC_64
7288 && object_64bit))
d6ab8113
JB		 7289 && (i.op[n].disps->X_op == O_symbol
7290 || (i.op[n].disps->X_op == O_add
7291 && ((symbol_get_value_expression
7292 (i.op[n].disps->X_op_symbol)->X_op)
7293 == O_subtract))))
7294 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7295 {
7296 offsetT add;
7297
7298 if (insn_start_frag == frag_now)
7299 add = (p - frag_now->fr_literal) - insn_start_off;
7300 else
7301 {
7302 fragS *fr;
7303
7304 add = insn_start_frag->fr_fix - insn_start_off;
7305 for (fr = insn_start_frag->fr_next;
7306 fr && fr != frag_now; fr = fr->fr_next)
7307 add += fr->fr_fix;
7308 add += p - frag_now->fr_literal;
7309 }
7310
4fa24527 7311 if (!object_64bit)
7b81dfbb
AJ		 7312 {
7313 reloc_type = BFD_RELOC_386_GOTPC;
7314 i.op[n].imms->X_add_number += add;
7315 }
7316 else if (reloc_type == BFD_RELOC_64)
7317 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7318 else
7b81dfbb
AJ		 7319 /* Don't do the adjustment for x86-64, as there
7320 the pcrel addressing is relative to the _next_
7321 insn, and that is taken care of in other code. */
d6ab8113 7322 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7323 }
02a86693
L		 7324 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7325 size, i.op[n].disps, pcrel,
7326 reloc_type);
7327 /* Check for "call/jmp *mem", "mov mem, %reg",
7328 "test %reg, mem" and "binop mem, %reg" where binop
7329 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7330 instructions. Always generate R_386_GOT32X for
7331 "sym*GOT" operand in 32-bit mode. */
7332 if ((generate_relax_relocations
7333 || (!object_64bit
7334 && i.rm.mode == 0
7335 && i.rm.regmem == 5))
7336 && (i.rm.mode == 2
7337 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7338 && ((i.operands == 1
7339 && i.tm.base_opcode == 0xff
7340 && (i.rm.reg == 2 || i.rm.reg == 4))
7341 || (i.operands == 2
7342 && (i.tm.base_opcode == 0x8b
7343 || i.tm.base_opcode == 0x85
7344 || (i.tm.base_opcode & 0xc7) == 0x03))))
7345 {
7346 if (object_64bit)
7347 {
7348 fixP->fx_tcbit = i.rex != 0;
7349 if (i.base_reg
7350 && (i.base_reg->reg_num == RegRip
7351 || i.base_reg->reg_num == RegEip))
7352 fixP->fx_tcbit2 = 1;
7353 }
7354 else
7355 fixP->fx_tcbit2 = 1;
7356 }
29b0f896
AM		 7357 }
7358 }
7359 }
7360}
252b5132 7361
29b0f896 7362static void
64e74474 7363output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7364{
7365 char *p;
7366 unsigned int n;
252b5132 7367
29b0f896
AM		 7368 for (n = 0; n < i.operands; n++)
7369 {
43234a1e
L		 7370 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7371 if (i.rounding && (int) n == i.rounding->operand)
7372 continue;
7373
40fb9820 7374 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7375 {
7376 if (i.op[n].imms->X_op == O_constant)
7377 {
e205caa7 7378 int size = imm_size (n);
29b0f896 7379 offsetT val;
b4cac588 7380
29b0f896
AM		 7381 val = offset_in_range (i.op[n].imms->X_add_number,
7382 size);
7383 p = frag_more (size);
7384 md_number_to_chars (p, val, size);
7385 }
7386 else
7387 {
7388 /* Not absolute_section.
7389 Need a 32-bit fixup (don't support 8bit
7390 non-absolute imms). Try to support other
7391 sizes ... */
f86103b7 7392 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7393 int size = imm_size (n);
7394 int sign;
29b0f896 7395
40fb9820 7396 if (i.types[n].bitfield.imm32s
a7d61044 7397 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7398 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7399 sign = 1;
e205caa7
L		 7400 else
7401 sign = 0;
520dc8e8 7402
29b0f896 7403 p = frag_more (size);
d258b828 7404 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7405
2bbd9c25
JJ		 7406 /* This is tough to explain. We end up with this one if we
7407 * have operands that look like
7408 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7409 * obtain the absolute address of the GOT, and it is strongly
7410 * preferable from a performance point of view to avoid using
7411 * a runtime relocation for this. The actual sequence of
7412 * instructions often look something like:
7413 *
7414 * call .L66
7415 * .L66:
7416 * popl %ebx
7417 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7418 *
7419 * The call and pop essentially return the absolute address
7420 * of the label .L66 and store it in %ebx. The linker itself
7421 * will ultimately change the first operand of the addl so
7422 * that %ebx points to the GOT, but to keep things simple, the
7423 * .o file must have this operand set so that it generates not
7424 * the absolute address of .L66, but the absolute address of
7425 * itself. This allows the linker itself simply treat a GOTPC
7426 * relocation as asking for a pcrel offset to the GOT to be
7427 * added in, and the addend of the relocation is stored in the
7428 * operand field for the instruction itself.
7429 *
7430 * Our job here is to fix the operand so that it would add
7431 * the correct offset so that %ebx would point to itself. The
7432 * thing that is tricky is that .-.L66 will point to the
7433 * beginning of the instruction, so we need to further modify
7434 * the operand so that it will point to itself. There are
7435 * other cases where you have something like:
7436 *
7437 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7438 *
7439 * and here no correction would be required. Internally in
7440 * the assembler we treat operands of this form as not being
7441 * pcrel since the '.' is explicitly mentioned, and I wonder
7442 * whether it would simplify matters to do it this way. Who
7443 * knows. In earlier versions of the PIC patches, the
7444 * pcrel_adjust field was used to store the correction, but
7445 * since the expression is not pcrel, I felt it would be
7446 * confusing to do it this way. */
7447
d6ab8113 7448 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7449 || reloc_type == BFD_RELOC_X86_64_32S
7450 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7451 && GOT_symbol
7452 && GOT_symbol == i.op[n].imms->X_add_symbol
7453 && (i.op[n].imms->X_op == O_symbol
7454 || (i.op[n].imms->X_op == O_add
7455 && ((symbol_get_value_expression
7456 (i.op[n].imms->X_op_symbol)->X_op)
7457 == O_subtract))))
7458 {
2bbd9c25
JJ		 7459 offsetT add;
7460
7461 if (insn_start_frag == frag_now)
7462 add = (p - frag_now->fr_literal) - insn_start_off;
7463 else
7464 {
7465 fragS *fr;
7466
7467 add = insn_start_frag->fr_fix - insn_start_off;
7468 for (fr = insn_start_frag->fr_next;
7469 fr && fr != frag_now; fr = fr->fr_next)
7470 add += fr->fr_fix;
7471 add += p - frag_now->fr_literal;
7472 }
7473
4fa24527 7474 if (!object_64bit)
d6ab8113 7475 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7476 else if (size == 4)
d6ab8113 7477 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7478 else if (size == 8)
7479 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7480 i.op[n].imms->X_add_number += add;
29b0f896 7481 }
29b0f896
AM		 7482 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7483 i.op[n].imms, 0, reloc_type);
7484 }
7485 }
7486 }
252b5132
RH		 7487}
7488\f
d182319b
JB		 7489/* x86_cons_fix_new is called via the expression parsing code when a
7490 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7491static int cons_sign = -1;
7492
7493void
e3bb37b5 7494x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7495 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7496{
d258b828 7497 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7498
7499#ifdef TE_PE
7500 if (exp->X_op == O_secrel)
7501 {
7502 exp->X_op = O_symbol;
7503 r = BFD_RELOC_32_SECREL;
7504 }
7505#endif
7506
7507 fix_new_exp (frag, off, len, exp, 0, r);
7508}
7509
357d1bd8
L		 7510/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7511 purpose of the `.dc.a' internal pseudo-op. */
7512
7513int
7514x86_address_bytes (void)
7515{
7516 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7517 return 4;
7518 return stdoutput->arch_info->bits_per_address / 8;
7519}
7520
d382c579
TG		 7521#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7522 || defined (LEX_AT)
d258b828 7523# define lex_got(reloc, adjust, types) NULL
718ddfc0 7524#else
f3c180ae
AM		 7525/* Parse operands of the form
7526 <symbol>@GOTOFF+<nnn>
7527 and similar .plt or .got references.
7528
7529 If we find one, set up the correct relocation in RELOC and copy the
7530 input string, minus the `@GOTOFF' into a malloc'd buffer for
7531 parsing by the calling routine. Return this buffer, and if ADJUST
7532 is non-null set it to the length of the string we removed from the
7533 input line. Otherwise return NULL. */
7534static char *
91d6fa6a 7535lex_got (enum bfd_reloc_code_real *rel,
64e74474 7536 int *adjust,
d258b828 7537 i386_operand_type *types)
f3c180ae 7538{
7b81dfbb
AJ		 7539 /* Some of the relocations depend on the size of what field is to
7540 be relocated. But in our callers i386_immediate and i386_displacement
7541 we don't yet know the operand size (this will be set by insn
7542 matching). Hence we record the word32 relocation here,
7543 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7544 static const struct {
7545 const char *str;
cff8d58a 7546 int len;
4fa24527 7547 const enum bfd_reloc_code_real rel[2];
40fb9820 7548 const i386_operand_type types64;
f3c180ae 7549 } gotrel[] = {
8ce3d284 7550#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7551 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7552 BFD_RELOC_SIZE32 },
7553 OPERAND_TYPE_IMM32_64 },
8ce3d284 7554#endif
cff8d58a
L		 7555 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7556 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7557 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7558 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7559 BFD_RELOC_X86_64_PLT32 },
40fb9820 7560 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7561 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7562 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7563 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7564 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7565 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7566 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7567 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7568 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7569 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7570 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7571 BFD_RELOC_X86_64_TLSGD },
40fb9820 7572 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7573 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7574 _dummy_first_bfd_reloc_code_real },
40fb9820 7575 OPERAND_TYPE_NONE },
cff8d58a
L		 7576 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7577 BFD_RELOC_X86_64_TLSLD },
40fb9820 7578 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7579 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7580 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7581 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7582 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7583 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7584 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7585 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7586 _dummy_first_bfd_reloc_code_real },
40fb9820 7587 OPERAND_TYPE_NONE },
cff8d58a
L		 7588 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7589 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7590 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7591 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7592 _dummy_first_bfd_reloc_code_real },
40fb9820 7593 OPERAND_TYPE_NONE },
cff8d58a
L		 7594 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7595 _dummy_first_bfd_reloc_code_real },
40fb9820 7596 OPERAND_TYPE_NONE },
cff8d58a
L		 7597 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7598 BFD_RELOC_X86_64_GOT32 },
40fb9820 7599 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7600 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7601 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7602 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7603 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7604 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7605 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7606 };
7607 char *cp;
7608 unsigned int j;
7609
d382c579 7610#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7611 if (!IS_ELF)
7612 return NULL;
d382c579 7613#endif
718ddfc0 7614
f3c180ae 7615 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7616 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7617 return NULL;
7618
47465058 7619 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7620 {
cff8d58a 7621 int len = gotrel[j].len;
28f81592 7622 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7623 {
4fa24527 7624 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7625 {
28f81592
AM		 7626 int first, second;
7627 char *tmpbuf, *past_reloc;
f3c180ae 7628
91d6fa6a 7629 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7630
3956db08
JB		 7631 if (types)
7632 {
7633 if (flag_code != CODE_64BIT)
40fb9820
L		 7634 {
7635 types->bitfield.imm32 = 1;
7636 types->bitfield.disp32 = 1;
7637 }
3956db08
JB		 7638 else
7639 *types = gotrel[j].types64;
7640 }
7641
8fd4256d 7642 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7643 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7644
28f81592 7645 /* The length of the first part of our input line. */
f3c180ae 7646 first = cp - input_line_pointer;
28f81592
AM		 7647
7648 /* The second part goes from after the reloc token until
67c11a9b 7649 (and including) an end_of_line char or comma. */
28f81592 7650 past_reloc = cp + 1 + len;
67c11a9b
AM		 7651 cp = past_reloc;
7652 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7653 ++cp;
7654 second = cp + 1 - past_reloc;
28f81592
AM		 7655
7656 /* Allocate and copy string. The trailing NUL shouldn't
7657 be necessary, but be safe. */
add39d23 7658 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7659 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7660 if (second != 0 && *past_reloc != ' ')
7661 /* Replace the relocation token with ' ', so that
7662 errors like foo@GOTOFF1 will be detected. */
7663 tmpbuf[first++] = ' ';
af89796a
L		 7664 else
7665 /* Increment length by 1 if the relocation token is
7666 removed. */
7667 len++;
7668 if (adjust)
7669 *adjust = len;
0787a12d
AM		 7670 memcpy (tmpbuf + first, past_reloc, second);
7671 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7672 return tmpbuf;
7673 }
7674
4fa24527
JB		 7675 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7676 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7677 return NULL;
7678 }
7679 }
7680
7681 /* Might be a symbol version string. Don't as_bad here. */
7682 return NULL;
7683}
4e4f7c87 7684#endif
f3c180ae 7685
a988325c
NC		 7686#ifdef TE_PE
7687#ifdef lex_got
7688#undef lex_got
7689#endif
7690/* Parse operands of the form
7691 <symbol>@SECREL32+<nnn>
7692
7693 If we find one, set up the correct relocation in RELOC and copy the
7694 input string, minus the `@SECREL32' into a malloc'd buffer for
7695 parsing by the calling routine. Return this buffer, and if ADJUST
7696 is non-null set it to the length of the string we removed from the
34bca508
L		 7697 input line. Otherwise return NULL.
7698
a988325c
NC		 7699 This function is copied from the ELF version above adjusted for PE targets. */
7700
7701static char *
7702lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7703 int *adjust ATTRIBUTE_UNUSED,
d258b828 7704 i386_operand_type *types)
a988325c
NC		 7705{
7706 static const struct
7707 {
7708 const char *str;
7709 int len;
7710 const enum bfd_reloc_code_real rel[2];
7711 const i386_operand_type types64;
7712 }
7713 gotrel[] =
7714 {
7715 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7716 BFD_RELOC_32_SECREL },
7717 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7718 };
7719
7720 char *cp;
7721 unsigned j;
7722
7723 for (cp = input_line_pointer; *cp != '@'; cp++)
7724 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7725 return NULL;
7726
7727 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7728 {
7729 int len = gotrel[j].len;
7730
7731 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7732 {
7733 if (gotrel[j].rel[object_64bit] != 0)
7734 {
7735 int first, second;
7736 char *tmpbuf, *past_reloc;
7737
7738 *rel = gotrel[j].rel[object_64bit];
7739 if (adjust)
7740 *adjust = len;
7741
7742 if (types)
7743 {
7744 if (flag_code != CODE_64BIT)
7745 {
7746 types->bitfield.imm32 = 1;
7747 types->bitfield.disp32 = 1;
7748 }
7749 else
7750 *types = gotrel[j].types64;
7751 }
7752
7753 /* The length of the first part of our input line. */
7754 first = cp - input_line_pointer;
7755
7756 /* The second part goes from after the reloc token until
7757 (and including) an end_of_line char or comma. */
7758 past_reloc = cp + 1 + len;
7759 cp = past_reloc;
7760 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7761 ++cp;
7762 second = cp + 1 - past_reloc;
7763
7764 /* Allocate and copy string. The trailing NUL shouldn't
7765 be necessary, but be safe. */
add39d23 7766 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7767 memcpy (tmpbuf, input_line_pointer, first);
7768 if (second != 0 && *past_reloc != ' ')
7769 /* Replace the relocation token with ' ', so that
7770 errors like foo@SECLREL321 will be detected. */
7771 tmpbuf[first++] = ' ';
7772 memcpy (tmpbuf + first, past_reloc, second);
7773 tmpbuf[first + second] = '\0';
7774 return tmpbuf;
7775 }
7776
7777 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7778 gotrel[j].str, 1 << (5 + object_64bit));
7779 return NULL;
7780 }
7781 }
7782
7783 /* Might be a symbol version string. Don't as_bad here. */
7784 return NULL;
7785}
7786
7787#endif /* TE_PE */
7788
62ebcb5c 7789bfd_reloc_code_real_type
e3bb37b5 7790x86_cons (expressionS *exp, int size)
f3c180ae 7791{
62ebcb5c
AM		 7792 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7793
ee86248c
JB		 7794 intel_syntax = -intel_syntax;
7795
3c7b9c2c 7796 exp->X_md = 0;
4fa24527 7797 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7798 {
7799 /* Handle @GOTOFF and the like in an expression. */
7800 char *save;
7801 char *gotfree_input_line;
4a57f2cf 7802 int adjust = 0;
f3c180ae
AM		 7803
7804 save = input_line_pointer;
d258b828 7805 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7806 if (gotfree_input_line)
7807 input_line_pointer = gotfree_input_line;
7808
7809 expression (exp);
7810
7811 if (gotfree_input_line)
7812 {
7813 /* expression () has merrily parsed up to the end of line,
7814 or a comma - in the wrong buffer. Transfer how far
7815 input_line_pointer has moved to the right buffer. */
7816 input_line_pointer = (save
7817 + (input_line_pointer - gotfree_input_line)
7818 + adjust);
7819 free (gotfree_input_line);
3992d3b7
AM		 7820 if (exp->X_op == O_constant
7821 || exp->X_op == O_absent
7822 || exp->X_op == O_illegal
0398aac5 7823 || exp->X_op == O_register
3992d3b7
AM		 7824 || exp->X_op == O_big)
7825 {
7826 char c = *input_line_pointer;
7827 *input_line_pointer = 0;
7828 as_bad (_("missing or invalid expression `%s'"), save);
7829 *input_line_pointer = c;
7830 }
f3c180ae
AM		 7831 }
7832 }
7833 else
7834 expression (exp);
ee86248c
JB		 7835
7836 intel_syntax = -intel_syntax;
7837
7838 if (intel_syntax)
7839 i386_intel_simplify (exp);
62ebcb5c
AM		 7840
7841 return got_reloc;
f3c180ae 7842}
f3c180ae 7843
9f32dd5b
L		 7844static void
7845signed_cons (int size)
6482c264 7846{
d182319b
JB		 7847 if (flag_code == CODE_64BIT)
7848 cons_sign = 1;
7849 cons (size);
7850 cons_sign = -1;
6482c264
NC		 7851}
7852
d182319b 7853#ifdef TE_PE
6482c264 7854static void
7016a5d5 7855pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7856{
7857 expressionS exp;
7858
7859 do
7860 {
7861 expression (&exp);
7862 if (exp.X_op == O_symbol)
7863 exp.X_op = O_secrel;
7864
7865 emit_expr (&exp, 4);
7866 }
7867 while (*input_line_pointer++ == ',');
7868
7869 input_line_pointer--;
7870 demand_empty_rest_of_line ();
7871}
6482c264
NC		 7872#endif
7873
43234a1e
L		 7874/* Handle Vector operations. */
7875
7876static char *
7877check_VecOperations (char *op_string, char *op_end)
7878{
7879 const reg_entry *mask;
7880 const char *saved;
7881 char *end_op;
7882
7883 while (*op_string
7884 && (op_end == NULL || op_string < op_end))
7885 {
7886 saved = op_string;
7887 if (*op_string == '{')
7888 {
7889 op_string++;
7890
7891 /* Check broadcasts. */
7892 if (strncmp (op_string, "1to", 3) == 0)
7893 {
7894 int bcst_type;
7895
7896 if (i.broadcast)
7897 goto duplicated_vec_op;
7898
7899 op_string += 3;
7900 if (*op_string == '8')
7901 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7902 else if (*op_string == '4')
7903 bcst_type = BROADCAST_1TO4;
7904 else if (*op_string == '2')
7905 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7906 else if (*op_string == '1'
7907 && *(op_string+1) == '6')
7908 {
7909 bcst_type = BROADCAST_1TO16;
7910 op_string++;
7911 }
7912 else
7913 {
7914 as_bad (_("Unsupported broadcast: `%s'"), saved);
7915 return NULL;
7916 }
7917 op_string++;
7918
7919 broadcast_op.type = bcst_type;
7920 broadcast_op.operand = this_operand;
7921 i.broadcast = &broadcast_op;
7922 }
7923 /* Check masking operation. */
7924 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7925 {
7926 /* k0 can't be used for write mask. */
7927 if (mask->reg_num == 0)
7928 {
7929 as_bad (_("`%s' can't be used for write mask"),
7930 op_string);
7931 return NULL;
7932 }
7933
7934 if (!i.mask)
7935 {
7936 mask_op.mask = mask;
7937 mask_op.zeroing = 0;
7938 mask_op.operand = this_operand;
7939 i.mask = &mask_op;
7940 }
7941 else
7942 {
7943 if (i.mask->mask)
7944 goto duplicated_vec_op;
7945
7946 i.mask->mask = mask;
7947
7948 /* Only "{z}" is allowed here. No need to check
7949 zeroing mask explicitly. */
7950 if (i.mask->operand != this_operand)
7951 {
7952 as_bad (_("invalid write mask `%s'"), saved);
7953 return NULL;
7954 }
7955 }
7956
7957 op_string = end_op;
7958 }
7959 /* Check zeroing-flag for masking operation. */
7960 else if (*op_string == 'z')
7961 {
7962 if (!i.mask)
7963 {
7964 mask_op.mask = NULL;
7965 mask_op.zeroing = 1;
7966 mask_op.operand = this_operand;
7967 i.mask = &mask_op;
7968 }
7969 else
7970 {
7971 if (i.mask->zeroing)
7972 {
7973 duplicated_vec_op:
7974 as_bad (_("duplicated `%s'"), saved);
7975 return NULL;
7976 }
7977
7978 i.mask->zeroing = 1;
7979
7980 /* Only "{%k}" is allowed here. No need to check mask
7981 register explicitly. */
7982 if (i.mask->operand != this_operand)
7983 {
7984 as_bad (_("invalid zeroing-masking `%s'"),
7985 saved);
7986 return NULL;
7987 }
7988 }
7989
7990 op_string++;
7991 }
7992 else
7993 goto unknown_vec_op;
7994
7995 if (*op_string != '}')
7996 {
7997 as_bad (_("missing `}' in `%s'"), saved);
7998 return NULL;
7999 }
8000 op_string++;
8001 continue;
8002 }
8003 unknown_vec_op:
8004 /* We don't know this one. */
8005 as_bad (_("unknown vector operation: `%s'"), saved);
8006 return NULL;
8007 }
8008
8009 return op_string;
8010}
8011
252b5132 8012static int
70e41ade 8013i386_immediate (char *imm_start)
252b5132
RH		 8014{
8015 char *save_input_line_pointer;
f3c180ae 8016 char *gotfree_input_line;
252b5132 8017 segT exp_seg = 0;
47926f60 8018 expressionS *exp;
40fb9820
L		 8019 i386_operand_type types;
8020
0dfbf9d7 8021 operand_type_set (&types, ~0);
252b5132
RH		 8022
8023 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8024 {
31b2323c
L		 8025 as_bad (_("at most %d immediate operands are allowed"),
8026 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8027 return 0;
8028 }
8029
8030 exp = &im_expressions[i.imm_operands++];
520dc8e8 8031 i.op[this_operand].imms = exp;
252b5132
RH		 8032
8033 if (is_space_char (*imm_start))
8034 ++imm_start;
8035
8036 save_input_line_pointer = input_line_pointer;
8037 input_line_pointer = imm_start;
8038
d258b828 8039 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8040 if (gotfree_input_line)
8041 input_line_pointer = gotfree_input_line;
252b5132
RH		 8042
8043 exp_seg = expression (exp);
8044
83183c0c 8045 SKIP_WHITESPACE ();
43234a1e
L		 8046
8047 /* Handle vector operations. */
8048 if (*input_line_pointer == '{')
8049 {
8050 input_line_pointer = check_VecOperations (input_line_pointer,
8051 NULL);
8052 if (input_line_pointer == NULL)
8053 return 0;
8054 }
8055
252b5132 8056 if (*input_line_pointer)
f3c180ae 8057 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8058
8059 input_line_pointer = save_input_line_pointer;
f3c180ae 8060 if (gotfree_input_line)
ee86248c
JB		 8061 {
8062 free (gotfree_input_line);
8063
8064 if (exp->X_op == O_constant || exp->X_op == O_register)
8065 exp->X_op = O_illegal;
8066 }
8067
8068 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8069}
252b5132 8070
ee86248c
JB		 8071static int
8072i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8073 i386_operand_type types, const char *imm_start)
8074{
8075 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8076 {
313c53d1
L		 8077 if (imm_start)
8078 as_bad (_("missing or invalid immediate expression `%s'"),
8079 imm_start);
3992d3b7 8080 return 0;
252b5132 8081 }
3e73aa7c 8082 else if (exp->X_op == O_constant)
252b5132 8083 {
47926f60 8084 /* Size it properly later. */
40fb9820 8085 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8086 /* If not 64bit, sign extend val. */
8087 if (flag_code != CODE_64BIT
4eed87de
AM		 8088 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8089 exp->X_add_number
8090 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8091 }
4c63da97 8092#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8093 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8094 && exp_seg != absolute_section
47926f60 8095 && exp_seg != text_section
24eab124
AM		 8096 && exp_seg != data_section
8097 && exp_seg != bss_section
8098 && exp_seg != undefined_section
f86103b7 8099 && !bfd_is_com_section (exp_seg))
252b5132 8100 {
d0b47220 8101 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8102 return 0;
8103 }
8104#endif
a841bdf5 8105 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8106 {
313c53d1
L		 8107 if (imm_start)
8108 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8109 return 0;
8110 }
252b5132
RH		 8111 else
8112 {
8113 /* This is an address. The size of the address will be
24eab124 8114 determined later, depending on destination register,
3e73aa7c 8115 suffix, or the default for the section. */
40fb9820
L		 8116 i.types[this_operand].bitfield.imm8 = 1;
8117 i.types[this_operand].bitfield.imm16 = 1;
8118 i.types[this_operand].bitfield.imm32 = 1;
8119 i.types[this_operand].bitfield.imm32s = 1;
8120 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8121 i.types[this_operand] = operand_type_and (i.types[this_operand],
8122 types);
252b5132
RH		 8123 }
8124
8125 return 1;
8126}
8127
551c1ca1 8128static char *
e3bb37b5 8129i386_scale (char *scale)
252b5132 8130{
551c1ca1
AM		 8131 offsetT val;
8132 char *save = input_line_pointer;
252b5132 8133
551c1ca1
AM		 8134 input_line_pointer = scale;
8135 val = get_absolute_expression ();
8136
8137 switch (val)
252b5132 8138 {
551c1ca1 8139 case 1:
252b5132
RH		 8140 i.log2_scale_factor = 0;
8141 break;
551c1ca1 8142 case 2:
252b5132
RH		 8143 i.log2_scale_factor = 1;
8144 break;
551c1ca1 8145 case 4:
252b5132
RH		 8146 i.log2_scale_factor = 2;
8147 break;
551c1ca1 8148 case 8:
252b5132
RH		 8149 i.log2_scale_factor = 3;
8150 break;
8151 default:
a724f0f4
JB		 8152 {
8153 char sep = *input_line_pointer;
8154
8155 *input_line_pointer = '\0';
8156 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8157 scale);
8158 *input_line_pointer = sep;
8159 input_line_pointer = save;
8160 return NULL;
8161 }
252b5132 8162 }
29b0f896 8163 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8164 {
8165 as_warn (_("scale factor of %d without an index register"),
24eab124 8166 1 << i.log2_scale_factor);
252b5132 8167 i.log2_scale_factor = 0;
252b5132 8168 }
551c1ca1
AM		 8169 scale = input_line_pointer;
8170 input_line_pointer = save;
8171 return scale;
252b5132
RH		 8172}
8173
252b5132 8174static int
e3bb37b5 8175i386_displacement (char *disp_start, char *disp_end)
252b5132 8176{
29b0f896 8177 expressionS *exp;
252b5132
RH		 8178 segT exp_seg = 0;
8179 char *save_input_line_pointer;
f3c180ae 8180 char *gotfree_input_line;
40fb9820
L		 8181 int override;
8182 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8183 int ret;
252b5132 8184
31b2323c
L		 8185 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8186 {
8187 as_bad (_("at most %d displacement operands are allowed"),
8188 MAX_MEMORY_OPERANDS);
8189 return 0;
8190 }
8191
0dfbf9d7 8192 operand_type_set (&bigdisp, 0);
40fb9820
L		 8193 if ((i.types[this_operand].bitfield.jumpabsolute)
8194 || (!current_templates->start->opcode_modifier.jump
8195 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8196 {
40fb9820 8197 bigdisp.bitfield.disp32 = 1;
e05278af 8198 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8199 if (flag_code == CODE_64BIT)
8200 {
8201 if (!override)
8202 {
8203 bigdisp.bitfield.disp32s = 1;
8204 bigdisp.bitfield.disp64 = 1;
8205 }
8206 }
8207 else if ((flag_code == CODE_16BIT) ^ override)
8208 {
8209 bigdisp.bitfield.disp32 = 0;
8210 bigdisp.bitfield.disp16 = 1;
8211 }
e05278af
JB		 8212 }
8213 else
8214 {
8215 /* For PC-relative branches, the width of the displacement
8216 is dependent upon data size, not address size. */
e05278af 8217 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8218 if (flag_code == CODE_64BIT)
8219 {
8220 if (override || i.suffix == WORD_MNEM_SUFFIX)
8221 bigdisp.bitfield.disp16 = 1;
8222 else
8223 {
8224 bigdisp.bitfield.disp32 = 1;
8225 bigdisp.bitfield.disp32s = 1;
8226 }
8227 }
8228 else
e05278af
JB		 8229 {
8230 if (!override)
8231 override = (i.suffix == (flag_code != CODE_16BIT
8232 ? WORD_MNEM_SUFFIX
8233 : LONG_MNEM_SUFFIX));
40fb9820
L		 8234 bigdisp.bitfield.disp32 = 1;
8235 if ((flag_code == CODE_16BIT) ^ override)
8236 {
8237 bigdisp.bitfield.disp32 = 0;
8238 bigdisp.bitfield.disp16 = 1;
8239 }
e05278af 8240 }
e05278af 8241 }
c6fb90c8
L		 8242 i.types[this_operand] = operand_type_or (i.types[this_operand],
8243 bigdisp);
252b5132
RH		 8244
8245 exp = &disp_expressions[i.disp_operands];
520dc8e8 8246 i.op[this_operand].disps = exp;
252b5132
RH		 8247 i.disp_operands++;
8248 save_input_line_pointer = input_line_pointer;
8249 input_line_pointer = disp_start;
8250 END_STRING_AND_SAVE (disp_end);
8251
8252#ifndef GCC_ASM_O_HACK
8253#define GCC_ASM_O_HACK 0
8254#endif
8255#if GCC_ASM_O_HACK
8256 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8257 if (i.types[this_operand].bitfield.baseIndex
24eab124 8258 && displacement_string_end[-1] == '+')
252b5132
RH		 8259 {
8260 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8261 constraint within gcc asm statements.
8262 For instance:
8263
8264 #define _set_tssldt_desc(n,addr,limit,type) \
8265 __asm__ __volatile__ ( \
8266 "movw %w2,%0\n\t" \
8267 "movw %w1,2+%0\n\t" \
8268 "rorl $16,%1\n\t" \
8269 "movb %b1,4+%0\n\t" \
8270 "movb %4,5+%0\n\t" \
8271 "movb $0,6+%0\n\t" \
8272 "movb %h1,7+%0\n\t" \
8273 "rorl $16,%1" \
8274 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8275
8276 This works great except that the output assembler ends
8277 up looking a bit weird if it turns out that there is
8278 no offset. You end up producing code that looks like:
8279
8280 #APP
8281 movw $235,(%eax)
8282 movw %dx,2+(%eax)
8283 rorl $16,%edx
8284 movb %dl,4+(%eax)
8285 movb $137,5+(%eax)
8286 movb $0,6+(%eax)
8287 movb %dh,7+(%eax)
8288 rorl $16,%edx
8289 #NO_APP
8290
47926f60 8291 So here we provide the missing zero. */
24eab124
AM		 8292
8293 *displacement_string_end = '0';
252b5132
RH		 8294 }
8295#endif
d258b828 8296 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8297 if (gotfree_input_line)
8298 input_line_pointer = gotfree_input_line;
252b5132 8299
24eab124 8300 exp_seg = expression (exp);
252b5132 8301
636c26b0
AM		 8302 SKIP_WHITESPACE ();
8303 if (*input_line_pointer)
8304 as_bad (_("junk `%s' after expression"), input_line_pointer);
8305#if GCC_ASM_O_HACK
8306 RESTORE_END_STRING (disp_end + 1);
8307#endif
636c26b0 8308 input_line_pointer = save_input_line_pointer;
636c26b0 8309 if (gotfree_input_line)
ee86248c
JB		 8310 {
8311 free (gotfree_input_line);
8312
8313 if (exp->X_op == O_constant || exp->X_op == O_register)
8314 exp->X_op = O_illegal;
8315 }
8316
8317 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8318
8319 RESTORE_END_STRING (disp_end);
8320
8321 return ret;
8322}
8323
8324static int
8325i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8326 i386_operand_type types, const char *disp_start)
8327{
8328 i386_operand_type bigdisp;
8329 int ret = 1;
636c26b0 8330
24eab124
AM		 8331 /* We do this to make sure that the section symbol is in
8332 the symbol table. We will ultimately change the relocation
47926f60 8333 to be relative to the beginning of the section. */
1ae12ab7 8334 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8335 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8336 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8337 {
636c26b0 8338 if (exp->X_op != O_symbol)
3992d3b7 8339 goto inv_disp;
636c26b0 8340
e5cb08ac 8341 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8342 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8343 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8344 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8345 exp->X_op = O_subtract;
8346 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8347 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8348 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8349 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8350 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8351 else
29b0f896 8352 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8353 }
252b5132 8354
3992d3b7
AM		 8355 else if (exp->X_op == O_absent
8356 || exp->X_op == O_illegal
ee86248c 8357 || exp->X_op == O_big)
2daf4fd8 8358 {
3992d3b7
AM		 8359 inv_disp:
8360 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8361 disp_start);
3992d3b7 8362 ret = 0;
2daf4fd8
AM		 8363 }
8364
0e1147d9
L		 8365 else if (flag_code == CODE_64BIT
8366 && !i.prefix[ADDR_PREFIX]
8367 && exp->X_op == O_constant)
8368 {
8369 /* Since displacement is signed extended to 64bit, don't allow
8370 disp32 and turn off disp32s if they are out of range. */
8371 i.types[this_operand].bitfield.disp32 = 0;
8372 if (!fits_in_signed_long (exp->X_add_number))
8373 {
8374 i.types[this_operand].bitfield.disp32s = 0;
8375 if (i.types[this_operand].bitfield.baseindex)
8376 {
8377 as_bad (_("0x%lx out range of signed 32bit displacement"),
8378 (long) exp->X_add_number);
8379 ret = 0;
8380 }
8381 }
8382 }
8383
4c63da97 8384#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8385 else if (exp->X_op != O_constant
8386 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8387 && exp_seg != absolute_section
8388 && exp_seg != text_section
8389 && exp_seg != data_section
8390 && exp_seg != bss_section
8391 && exp_seg != undefined_section
8392 && !bfd_is_com_section (exp_seg))
24eab124 8393 {
d0b47220 8394 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8395 ret = 0;
24eab124 8396 }
252b5132 8397#endif
3956db08 8398
40fb9820
L		 8399 /* Check if this is a displacement only operand. */
8400 bigdisp = i.types[this_operand];
8401 bigdisp.bitfield.disp8 = 0;
8402 bigdisp.bitfield.disp16 = 0;
8403 bigdisp.bitfield.disp32 = 0;
8404 bigdisp.bitfield.disp32s = 0;
8405 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8406 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8407 i.types[this_operand] = operand_type_and (i.types[this_operand],
8408 types);
3956db08 8409
3992d3b7 8410 return ret;
252b5132
RH		 8411}
8412
eecb386c 8413/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8414 Return 1 on success, 0 on a failure. */
8415
252b5132 8416static int
e3bb37b5 8417i386_index_check (const char *operand_string)
252b5132 8418{
fc0763e6 8419 const char *kind = "base/index";
be05d201
L		 8420 enum flag_code addr_mode;
8421
8422 if (i.prefix[ADDR_PREFIX])
8423 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8424 else
8425 {
8426 addr_mode = flag_code;
8427
24eab124 8428#if INFER_ADDR_PREFIX
be05d201
L		 8429 if (i.mem_operands == 0)
8430 {
8431 /* Infer address prefix from the first memory operand. */
8432 const reg_entry *addr_reg = i.base_reg;
8433
8434 if (addr_reg == NULL)
8435 addr_reg = i.index_reg;
eecb386c 8436
be05d201
L		 8437 if (addr_reg)
8438 {
8439 if (addr_reg->reg_num == RegEip
8440 || addr_reg->reg_num == RegEiz
8441 || addr_reg->reg_type.bitfield.reg32)
8442 addr_mode = CODE_32BIT;
8443 else if (flag_code != CODE_64BIT
8444 && addr_reg->reg_type.bitfield.reg16)
8445 addr_mode = CODE_16BIT;
8446
8447 if (addr_mode != flag_code)
8448 {
8449 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8450 i.prefixes += 1;
8451 /* Change the size of any displacement too. At most one
8452 of Disp16 or Disp32 is set.
8453 FIXME. There doesn't seem to be any real need for
8454 separate Disp16 and Disp32 flags. The same goes for
8455 Imm16 and Imm32. Removing them would probably clean
8456 up the code quite a lot. */
8457 if (flag_code != CODE_64BIT
8458 && (i.types[this_operand].bitfield.disp16
8459 || i.types[this_operand].bitfield.disp32))
8460 i.types[this_operand]
8461 = operand_type_xor (i.types[this_operand], disp16_32);
8462 }
8463 }
8464 }
24eab124 8465#endif
be05d201
L		 8466 }
8467
fc0763e6
JB		 8468 if (current_templates->start->opcode_modifier.isstring
8469 && !current_templates->start->opcode_modifier.immext
8470 && (current_templates->end[-1].opcode_modifier.isstring
8471 || i.mem_operands))
8472 {
8473 /* Memory operands of string insns are special in that they only allow
8474 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8475 const reg_entry *expected_reg;
8476 static const char *di_si[][2] =
8477 {
8478 { "esi", "edi" },
8479 { "si", "di" },
8480 { "rsi", "rdi" }
8481 };
8482 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8483
8484 kind = "string address";
8485
8486 if (current_templates->start->opcode_modifier.w)
8487 {
8488 i386_operand_type type = current_templates->end[-1].operand_types[0];
8489
8490 if (!type.bitfield.baseindex
8491 || ((!i.mem_operands != !intel_syntax)
8492 && current_templates->end[-1].operand_types[1]
8493 .bitfield.baseindex))
8494 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8495 expected_reg = hash_find (reg_hash,
8496 di_si[addr_mode][type.bitfield.esseg]);
8497
fc0763e6
JB		 8498 }
8499 else
be05d201 8500 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8501
be05d201
L		 8502 if (i.base_reg != expected_reg
8503 || i.index_reg
fc0763e6 8504 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8505 {
be05d201
L		 8506 /* The second memory operand must have the same size as
8507 the first one. */
8508 if (i.mem_operands
8509 && i.base_reg
8510 && !((addr_mode == CODE_64BIT
8511 && i.base_reg->reg_type.bitfield.reg64)
8512 || (addr_mode == CODE_32BIT
8513 ? i.base_reg->reg_type.bitfield.reg32
8514 : i.base_reg->reg_type.bitfield.reg16)))
8515 goto bad_address;
8516
fc0763e6
JB		 8517 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8518 operand_string,
8519 intel_syntax ? '[' : '(',
8520 register_prefix,
be05d201 8521 expected_reg->reg_name,
fc0763e6 8522 intel_syntax ? ']' : ')');
be05d201 8523 return 1;
fc0763e6 8524 }
be05d201
L		 8525 else
8526 return 1;
8527
8528bad_address:
8529 as_bad (_("`%s' is not a valid %s expression"),
8530 operand_string, kind);
8531 return 0;
3e73aa7c
JH		 8532 }
8533 else
8534 {
be05d201
L		 8535 if (addr_mode != CODE_16BIT)
8536 {
8537 /* 32-bit/64-bit checks. */
8538 if ((i.base_reg
8539 && (addr_mode == CODE_64BIT
8540 ? !i.base_reg->reg_type.bitfield.reg64
8541 : !i.base_reg->reg_type.bitfield.reg32)
8542 && (i.index_reg
8543 || (i.base_reg->reg_num
8544 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8545 || (i.index_reg
8546 && !i.index_reg->reg_type.bitfield.regxmm
8547 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8548 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8549 && ((addr_mode == CODE_64BIT
8550 ? !(i.index_reg->reg_type.bitfield.reg64
8551 || i.index_reg->reg_num == RegRiz)
8552 : !(i.index_reg->reg_type.bitfield.reg32
8553 || i.index_reg->reg_num == RegEiz))
8554 || !i.index_reg->reg_type.bitfield.baseindex)))
8555 goto bad_address;
8556 }
8557 else
3e73aa7c 8558 {
be05d201 8559 /* 16-bit checks. */
3e73aa7c 8560 if ((i.base_reg
40fb9820
L		 8561 && (!i.base_reg->reg_type.bitfield.reg16
8562 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8563 || (i.index_reg
40fb9820
L		 8564 && (!i.index_reg->reg_type.bitfield.reg16
8565 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8566 || !(i.base_reg
8567 && i.base_reg->reg_num < 6
8568 && i.index_reg->reg_num >= 6
8569 && i.log2_scale_factor == 0))))
be05d201 8570 goto bad_address;
3e73aa7c
JH		 8571 }
8572 }
be05d201 8573 return 1;
24eab124 8574}
252b5132 8575
43234a1e
L		 8576/* Handle vector immediates. */
8577
8578static int
8579RC_SAE_immediate (const char *imm_start)
8580{
8581 unsigned int match_found, j;
8582 const char *pstr = imm_start;
8583 expressionS *exp;
8584
8585 if (*pstr != '{')
8586 return 0;
8587
8588 pstr++;
8589 match_found = 0;
8590 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8591 {
8592 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8593 {
8594 if (!i.rounding)
8595 {
8596 rc_op.type = RC_NamesTable[j].type;
8597 rc_op.operand = this_operand;
8598 i.rounding = &rc_op;
8599 }
8600 else
8601 {
8602 as_bad (_("duplicated `%s'"), imm_start);
8603 return 0;
8604 }
8605 pstr += RC_NamesTable[j].len;
8606 match_found = 1;
8607 break;
8608 }
8609 }
8610 if (!match_found)
8611 return 0;
8612
8613 if (*pstr++ != '}')
8614 {
8615 as_bad (_("Missing '}': '%s'"), imm_start);
8616 return 0;
8617 }
8618 /* RC/SAE immediate string should contain nothing more. */;
8619 if (*pstr != 0)
8620 {
8621 as_bad (_("Junk after '}': '%s'"), imm_start);
8622 return 0;
8623 }
8624
8625 exp = &im_expressions[i.imm_operands++];
8626 i.op[this_operand].imms = exp;
8627
8628 exp->X_op = O_constant;
8629 exp->X_add_number = 0;
8630 exp->X_add_symbol = (symbolS *) 0;
8631 exp->X_op_symbol = (symbolS *) 0;
8632
8633 i.types[this_operand].bitfield.imm8 = 1;
8634 return 1;
8635}
8636
fc0763e6 8637/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8638 on error. */
252b5132 8639
252b5132 8640static int
a7619375 8641i386_att_operand (char *operand_string)
252b5132 8642{
af6bdddf
AM		 8643 const reg_entry *r;
8644 char *end_op;
24eab124 8645 char *op_string = operand_string;
252b5132 8646
24eab124 8647 if (is_space_char (*op_string))
252b5132
RH		 8648 ++op_string;
8649
24eab124 8650 /* We check for an absolute prefix (differentiating,
47926f60 8651 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8652 if (*op_string == ABSOLUTE_PREFIX)
8653 {
8654 ++op_string;
8655 if (is_space_char (*op_string))
8656 ++op_string;
40fb9820 8657 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8658 }
252b5132 8659
47926f60 8660 /* Check if operand is a register. */
4d1bb795 8661 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8662 {
40fb9820
L		 8663 i386_operand_type temp;
8664
24eab124
AM		 8665 /* Check for a segment override by searching for ':' after a
8666 segment register. */
8667 op_string = end_op;
8668 if (is_space_char (*op_string))
8669 ++op_string;
40fb9820
L		 8670 if (*op_string == ':'
8671 && (r->reg_type.bitfield.sreg2
8672 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8673 {
8674 switch (r->reg_num)
8675 {
8676 case 0:
8677 i.seg[i.mem_operands] = &es;
8678 break;
8679 case 1:
8680 i.seg[i.mem_operands] = &cs;
8681 break;
8682 case 2:
8683 i.seg[i.mem_operands] = &ss;
8684 break;
8685 case 3:
8686 i.seg[i.mem_operands] = &ds;
8687 break;
8688 case 4:
8689 i.seg[i.mem_operands] = &fs;
8690 break;
8691 case 5:
8692 i.seg[i.mem_operands] = &gs;
8693 break;
8694 }
252b5132 8695
24eab124 8696 /* Skip the ':' and whitespace. */
252b5132
RH		 8697 ++op_string;
8698 if (is_space_char (*op_string))
24eab124 8699 ++op_string;
252b5132 8700
24eab124
AM		 8701 if (!is_digit_char (*op_string)
8702 && !is_identifier_char (*op_string)
8703 && *op_string != '('
8704 && *op_string != ABSOLUTE_PREFIX)
8705 {
8706 as_bad (_("bad memory operand `%s'"), op_string);
8707 return 0;
8708 }
47926f60 8709 /* Handle case of %es:*foo. */
24eab124
AM		 8710 if (*op_string == ABSOLUTE_PREFIX)
8711 {
8712 ++op_string;
8713 if (is_space_char (*op_string))
8714 ++op_string;
40fb9820 8715 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8716 }
8717 goto do_memory_reference;
8718 }
43234a1e
L		 8719
8720 /* Handle vector operations. */
8721 if (*op_string == '{')
8722 {
8723 op_string = check_VecOperations (op_string, NULL);
8724 if (op_string == NULL)
8725 return 0;
8726 }
8727
24eab124
AM		 8728 if (*op_string)
8729 {
d0b47220 8730 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8731 return 0;
8732 }
40fb9820
L		 8733 temp = r->reg_type;
8734 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8735 i.types[this_operand] = operand_type_or (i.types[this_operand],
8736 temp);
7d5e4556 8737 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8738 i.op[this_operand].regs = r;
24eab124
AM		 8739 i.reg_operands++;
8740 }
af6bdddf
AM		 8741 else if (*op_string == REGISTER_PREFIX)
8742 {
8743 as_bad (_("bad register name `%s'"), op_string);
8744 return 0;
8745 }
24eab124 8746 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8747 {
24eab124 8748 ++op_string;
40fb9820 8749 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8750 {
d0b47220 8751 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8752 return 0;
8753 }
8754 if (!i386_immediate (op_string))
8755 return 0;
8756 }
43234a1e
L		 8757 else if (RC_SAE_immediate (operand_string))
8758 {
8759 /* If it is a RC or SAE immediate, do nothing. */
8760 ;
8761 }
24eab124
AM		 8762 else if (is_digit_char (*op_string)
8763 || is_identifier_char (*op_string)
d02603dc 8764 || *op_string == '"'
e5cb08ac 8765 || *op_string == '(')
24eab124 8766 {
47926f60 8767 /* This is a memory reference of some sort. */
af6bdddf 8768 char *base_string;
252b5132 8769
47926f60 8770 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8771 char *displacement_string_start;
8772 char *displacement_string_end;
43234a1e 8773 char *vop_start;
252b5132 8774
24eab124 8775 do_memory_reference:
24eab124 8776 if ((i.mem_operands == 1
40fb9820 8777 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8778 || i.mem_operands == 2)
8779 {
8780 as_bad (_("too many memory references for `%s'"),
8781 current_templates->start->name);
8782 return 0;
8783 }
252b5132 8784
24eab124
AM		 8785 /* Check for base index form. We detect the base index form by
8786 looking for an ')' at the end of the operand, searching
8787 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8788 after the '('. */
af6bdddf 8789 base_string = op_string + strlen (op_string);
c3332e24 8790
43234a1e
L		 8791 /* Handle vector operations. */
8792 vop_start = strchr (op_string, '{');
8793 if (vop_start && vop_start < base_string)
8794 {
8795 if (check_VecOperations (vop_start, base_string) == NULL)
8796 return 0;
8797 base_string = vop_start;
8798 }
8799
af6bdddf
AM		 8800 --base_string;
8801 if (is_space_char (*base_string))
8802 --base_string;
252b5132 8803
47926f60 8804 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8805 displacement_string_start = op_string;
8806 displacement_string_end = base_string + 1;
252b5132 8807
24eab124
AM		 8808 if (*base_string == ')')
8809 {
af6bdddf 8810 char *temp_string;
24eab124
AM		 8811 unsigned int parens_balanced = 1;
8812 /* We've already checked that the number of left & right ()'s are
47926f60 8813 equal, so this loop will not be infinite. */
24eab124
AM		 8814 do
8815 {
8816 base_string--;
8817 if (*base_string == ')')
8818 parens_balanced++;
8819 if (*base_string == '(')
8820 parens_balanced--;
8821 }
8822 while (parens_balanced);
c3332e24 8823
af6bdddf 8824 temp_string = base_string;
c3332e24 8825
24eab124 8826 /* Skip past '(' and whitespace. */
252b5132
RH		 8827 ++base_string;
8828 if (is_space_char (*base_string))
24eab124 8829 ++base_string;
252b5132 8830
af6bdddf 8831 if (*base_string == ','
4eed87de
AM		 8832 || ((i.base_reg = parse_register (base_string, &end_op))
8833 != NULL))
252b5132 8834 {
af6bdddf 8835 displacement_string_end = temp_string;
252b5132 8836
40fb9820 8837 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8838
af6bdddf 8839 if (i.base_reg)
24eab124 8840 {
24eab124
AM		 8841 base_string = end_op;
8842 if (is_space_char (*base_string))
8843 ++base_string;
af6bdddf
AM		 8844 }
8845
8846 /* There may be an index reg or scale factor here. */
8847 if (*base_string == ',')
8848 {
8849 ++base_string;
8850 if (is_space_char (*base_string))
8851 ++base_string;
8852
4eed87de
AM		 8853 if ((i.index_reg = parse_register (base_string, &end_op))
8854 != NULL)
24eab124 8855 {
af6bdddf 8856 base_string = end_op;
24eab124
AM		 8857 if (is_space_char (*base_string))
8858 ++base_string;
af6bdddf
AM		 8859 if (*base_string == ',')
8860 {
8861 ++base_string;
8862 if (is_space_char (*base_string))
8863 ++base_string;
8864 }
e5cb08ac 8865 else if (*base_string != ')')
af6bdddf 8866 {
4eed87de
AM		 8867 as_bad (_("expecting `,' or `)' "
8868 "after index register in `%s'"),
af6bdddf
AM		 8869 operand_string);
8870 return 0;
8871 }
24eab124 8872 }
af6bdddf 8873 else if (*base_string == REGISTER_PREFIX)
24eab124 8874 {
f76bf5e0
L		 8875 end_op = strchr (base_string, ',');
8876 if (end_op)
8877 *end_op = '\0';
af6bdddf 8878 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8879 return 0;
8880 }
252b5132 8881
47926f60 8882 /* Check for scale factor. */
551c1ca1 8883 if (*base_string != ')')
af6bdddf 8884 {
551c1ca1
AM		 8885 char *end_scale = i386_scale (base_string);
8886
8887 if (!end_scale)
af6bdddf 8888 return 0;
24eab124 8889
551c1ca1 8890 base_string = end_scale;
af6bdddf
AM		 8891 if (is_space_char (*base_string))
8892 ++base_string;
8893 if (*base_string != ')')
8894 {
4eed87de
AM		 8895 as_bad (_("expecting `)' "
8896 "after scale factor in `%s'"),
af6bdddf
AM		 8897 operand_string);
8898 return 0;
8899 }
8900 }
8901 else if (!i.index_reg)
24eab124 8902 {
4eed87de
AM		 8903 as_bad (_("expecting index register or scale factor "
8904 "after `,'; got '%c'"),
af6bdddf 8905 *base_string);
24eab124
AM		 8906 return 0;
8907 }
8908 }
af6bdddf 8909 else if (*base_string != ')')
24eab124 8910 {
4eed87de
AM		 8911 as_bad (_("expecting `,' or `)' "
8912 "after base register in `%s'"),
af6bdddf 8913 operand_string);
24eab124
AM		 8914 return 0;
8915 }
c3332e24 8916 }
af6bdddf 8917 else if (*base_string == REGISTER_PREFIX)
c3332e24 8918 {
f76bf5e0
L		 8919 end_op = strchr (base_string, ',');
8920 if (end_op)
8921 *end_op = '\0';
af6bdddf 8922 as_bad (_("bad register name `%s'"), base_string);
24eab124 8923 return 0;
c3332e24 8924 }
24eab124
AM		 8925 }
8926
8927 /* If there's an expression beginning the operand, parse it,
8928 assuming displacement_string_start and
8929 displacement_string_end are meaningful. */
8930 if (displacement_string_start != displacement_string_end)
8931 {
8932 if (!i386_displacement (displacement_string_start,
8933 displacement_string_end))
8934 return 0;
8935 }
8936
8937 /* Special case for (%dx) while doing input/output op. */
8938 if (i.base_reg
0dfbf9d7
L		 8939 && operand_type_equal (&i.base_reg->reg_type,
8940 &reg16_inoutportreg)
24eab124
AM		 8941 && i.index_reg == 0
8942 && i.log2_scale_factor == 0
8943 && i.seg[i.mem_operands] == 0
40fb9820 8944 && !operand_type_check (i.types[this_operand], disp))
24eab124 8945 {
65da13b5 8946 i.types[this_operand] = inoutportreg;
24eab124
AM		 8947 return 1;
8948 }
8949
eecb386c
AM		 8950 if (i386_index_check (operand_string) == 0)
8951 return 0;
5c07affc 8952 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8953 i.mem_operands++;
8954 }
8955 else
ce8a8b2f
AM		 8956 {
8957 /* It's not a memory operand; argh! */
24eab124
AM		 8958 as_bad (_("invalid char %s beginning operand %d `%s'"),
8959 output_invalid (*op_string),
8960 this_operand + 1,
8961 op_string);
8962 return 0;
8963 }
47926f60 8964 return 1; /* Normal return. */
252b5132
RH		 8965}
8966\f
fa94de6b
RM		 8967/* Calculate the maximum variable size (i.e., excluding fr_fix)
8968 that an rs_machine_dependent frag may reach. */
8969
8970unsigned int
8971i386_frag_max_var (fragS *frag)
8972{
8973 /* The only relaxable frags are for jumps.
8974 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8975 gas_assert (frag->fr_type == rs_machine_dependent);
8976 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8977}
8978
b084df0b
L		 8979#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8980static int
8dcea932 8981elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8982{
8983 /* STT_GNU_IFUNC symbol must go through PLT. */
8984 if ((symbol_get_bfdsym (fr_symbol)->flags
8985 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8986 return 0;
8987
8988 if (!S_IS_EXTERNAL (fr_symbol))
8989 /* Symbol may be weak or local. */
8990 return !S_IS_WEAK (fr_symbol);
8991
8dcea932
L		 8992 /* Global symbols with non-default visibility can't be preempted. */
8993 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8994 return 1;
8995
8996 if (fr_var != NO_RELOC)
8997 switch ((enum bfd_reloc_code_real) fr_var)
8998 {
8999 case BFD_RELOC_386_PLT32:
9000 case BFD_RELOC_X86_64_PLT32:
9001 /* Symbol with PLT relocatin may be preempted. */
9002 return 0;
9003 default:
9004 abort ();
9005 }
9006
b084df0b
L		 9007 /* Global symbols with default visibility in a shared library may be
9008 preempted by another definition. */
8dcea932 9009 return !shared;
b084df0b
L		 9010}
9011#endif
9012
ee7fcc42
AM		 9013/* md_estimate_size_before_relax()
9014
9015 Called just before relax() for rs_machine_dependent frags. The x86
9016 assembler uses these frags to handle variable size jump
9017 instructions.
9018
9019 Any symbol that is now undefined will not become defined.
9020 Return the correct fr_subtype in the frag.
9021 Return the initial "guess for variable size of frag" to caller.
9022 The guess is actually the growth beyond the fixed part. Whatever
9023 we do to grow the fixed or variable part contributes to our
9024 returned value. */
9025
252b5132 9026int
7016a5d5 9027md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9028{
252b5132 9029 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9030 check for un-relaxable symbols. On an ELF system, we can't relax
9031 an externally visible symbol, because it may be overridden by a
9032 shared library. */
9033 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9034#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9035 || (IS_ELF
8dcea932
L		 9036 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9037 fragP->fr_var))
fbeb56a4
DK		 9038#endif
9039#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9040 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9041 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9042#endif
9043 )
252b5132 9044 {
b98ef147
AM		 9045 /* Symbol is undefined in this segment, or we need to keep a
9046 reloc so that weak symbols can be overridden. */
9047 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9048 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9049 unsigned char *opcode;
9050 int old_fr_fix;
f6af82bd 9051
ee7fcc42 9052 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9053 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9054 else if (size == 2)
f6af82bd
AM		 9055 reloc_type = BFD_RELOC_16_PCREL;
9056 else
9057 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9058
ee7fcc42
AM		 9059 old_fr_fix = fragP->fr_fix;
9060 opcode = (unsigned char *) fragP->fr_opcode;
9061
fddf5b5b 9062 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9063 {
fddf5b5b
AM		 9064 case UNCOND_JUMP:
9065 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9066 opcode[0] = 0xe9;
252b5132 9067 fragP->fr_fix += size;
062cd5e7
AS		 9068 fix_new (fragP, old_fr_fix, size,
9069 fragP->fr_symbol,
9070 fragP->fr_offset, 1,
9071 reloc_type);
252b5132
RH		 9072 break;
9073
fddf5b5b 9074 case COND_JUMP86:
412167cb
AM		 9075 if (size == 2
9076 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9077 {
9078 /* Negate the condition, and branch past an
9079 unconditional jump. */
9080 opcode[0] ^= 1;
9081 opcode[1] = 3;
9082 /* Insert an unconditional jump. */
9083 opcode[2] = 0xe9;
9084 /* We added two extra opcode bytes, and have a two byte
9085 offset. */
9086 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9087 fix_new (fragP, old_fr_fix + 2, 2,
9088 fragP->fr_symbol,
9089 fragP->fr_offset, 1,
9090 reloc_type);
fddf5b5b
AM		 9091 break;
9092 }
9093 /* Fall through. */
9094
9095 case COND_JUMP:
412167cb
AM		 9096 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9097 {
3e02c1cc
AM		 9098 fixS *fixP;
9099
412167cb 9100 fragP->fr_fix += 1;
3e02c1cc
AM		 9101 fixP = fix_new (fragP, old_fr_fix, 1,
9102 fragP->fr_symbol,
9103 fragP->fr_offset, 1,
9104 BFD_RELOC_8_PCREL);
9105 fixP->fx_signed = 1;
412167cb
AM		 9106 break;
9107 }
93c2a809 9108
24eab124 9109 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9110 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9111 opcode[1] = opcode[0] + 0x10;
f6af82bd 9112 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9113 /* We've added an opcode byte. */
9114 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9115 fix_new (fragP, old_fr_fix + 1, size,
9116 fragP->fr_symbol,
9117 fragP->fr_offset, 1,
9118 reloc_type);
252b5132 9119 break;
fddf5b5b
AM		 9120
9121 default:
9122 BAD_CASE (fragP->fr_subtype);
9123 break;
252b5132
RH		 9124 }
9125 frag_wane (fragP);
ee7fcc42 9126 return fragP->fr_fix - old_fr_fix;
252b5132 9127 }
93c2a809 9128
93c2a809
AM		 9129 /* Guess size depending on current relax state. Initially the relax
9130 state will correspond to a short jump and we return 1, because
9131 the variable part of the frag (the branch offset) is one byte
9132 long. However, we can relax a section more than once and in that
9133 case we must either set fr_subtype back to the unrelaxed state,
9134 or return the value for the appropriate branch. */
9135 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9136}
9137
47926f60
KH		 9138/* Called after relax() is finished.
9139
9140 In: Address of frag.
9141 fr_type == rs_machine_dependent.
9142 fr_subtype is what the address relaxed to.
9143
9144 Out: Any fixSs and constants are set up.
9145 Caller will turn frag into a ".space 0". */
9146
252b5132 9147void
7016a5d5
TG		 9148md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9149 fragS *fragP)
252b5132 9150{
29b0f896 9151 unsigned char *opcode;
252b5132 9152 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9153 offsetT target_address;
9154 offsetT opcode_address;
252b5132 9155 unsigned int extension = 0;
847f7ad4 9156 offsetT displacement_from_opcode_start;
252b5132
RH		 9157
9158 opcode = (unsigned char *) fragP->fr_opcode;
9159
47926f60 9160 /* Address we want to reach in file space. */
252b5132 9161 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9162
47926f60 9163 /* Address opcode resides at in file space. */
252b5132
RH		 9164 opcode_address = fragP->fr_address + fragP->fr_fix;
9165
47926f60 9166 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9167 displacement_from_opcode_start = target_address - opcode_address;
9168
fddf5b5b 9169 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9170 {
47926f60
KH		 9171 /* Don't have to change opcode. */
9172 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9173 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9174 }
9175 else
9176 {
9177 if (no_cond_jump_promotion
9178 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9179 as_warn_where (fragP->fr_file, fragP->fr_line,
9180 _("long jump required"));
252b5132 9181
fddf5b5b
AM		 9182 switch (fragP->fr_subtype)
9183 {
9184 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9185 extension = 4; /* 1 opcode + 4 displacement */
9186 opcode[0] = 0xe9;
9187 where_to_put_displacement = &opcode[1];
9188 break;
252b5132 9189
fddf5b5b
AM		 9190 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9191 extension = 2; /* 1 opcode + 2 displacement */
9192 opcode[0] = 0xe9;
9193 where_to_put_displacement = &opcode[1];
9194 break;
252b5132 9195
fddf5b5b
AM		 9196 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9197 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9198 extension = 5; /* 2 opcode + 4 displacement */
9199 opcode[1] = opcode[0] + 0x10;
9200 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9201 where_to_put_displacement = &opcode[2];
9202 break;
252b5132 9203
fddf5b5b
AM		 9204 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9205 extension = 3; /* 2 opcode + 2 displacement */
9206 opcode[1] = opcode[0] + 0x10;
9207 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9208 where_to_put_displacement = &opcode[2];
9209 break;
252b5132 9210
fddf5b5b
AM		 9211 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9212 extension = 4;
9213 opcode[0] ^= 1;
9214 opcode[1] = 3;
9215 opcode[2] = 0xe9;
9216 where_to_put_displacement = &opcode[3];
9217 break;
9218
9219 default:
9220 BAD_CASE (fragP->fr_subtype);
9221 break;
9222 }
252b5132 9223 }
fddf5b5b 9224
7b81dfbb
AJ		 9225 /* If size if less then four we are sure that the operand fits,
9226 but if it's 4, then it could be that the displacement is larger
9227 then -/+ 2GB. */
9228 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9229 && object_64bit
9230 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9231 + ((addressT) 1 << 31))
9232 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9233 {
9234 as_bad_where (fragP->fr_file, fragP->fr_line,
9235 _("jump target out of range"));
9236 /* Make us emit 0. */
9237 displacement_from_opcode_start = extension;
9238 }
47926f60 9239 /* Now put displacement after opcode. */
252b5132
RH		 9240 md_number_to_chars ((char *) where_to_put_displacement,
9241 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9242 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9243 fragP->fr_fix += extension;
9244}
9245\f
7016a5d5 9246/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9247 by our caller that we have all the info we need to fix it up.
9248
7016a5d5
TG		 9249 Parameter valP is the pointer to the value of the bits.
9250
252b5132
RH		 9251 On the 386, immediates, displacements, and data pointers are all in
9252 the same (little-endian) format, so we don't need to care about which
9253 we are handling. */
9254
94f592af 9255void
7016a5d5 9256md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9257{
94f592af 9258 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9259 valueT value = *valP;
252b5132 9260
f86103b7 9261#if !defined (TE_Mach)
93382f6d
AM		 9262 if (fixP->fx_pcrel)
9263 {
9264 switch (fixP->fx_r_type)
9265 {
5865bb77
ILT		 9266 default:
9267 break;
9268
d6ab8113
JB		 9269 case BFD_RELOC_64:
9270 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9271 break;
93382f6d 9272 case BFD_RELOC_32:
ae8887b5 9273 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9274 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9275 break;
9276 case BFD_RELOC_16:
9277 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9278 break;
9279 case BFD_RELOC_8:
9280 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9281 break;
9282 }
9283 }
252b5132 9284
a161fe53 9285 if (fixP->fx_addsy != NULL
31312f95 9286 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9287 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9288 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9289 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9290 && !use_rela_relocations)
252b5132 9291 {
31312f95
AM		 9292 /* This is a hack. There should be a better way to handle this.
9293 This covers for the fact that bfd_install_relocation will
9294 subtract the current location (for partial_inplace, PC relative
9295 relocations); see more below. */
252b5132 9296#ifndef OBJ_AOUT
718ddfc0 9297 if (IS_ELF
252b5132
RH		 9298#ifdef TE_PE
9299 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9300#endif
9301 )
9302 value += fixP->fx_where + fixP->fx_frag->fr_address;
9303#endif
9304#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9305 if (IS_ELF)
252b5132 9306 {
6539b54b 9307 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9308
6539b54b 9309 if ((sym_seg == seg
2f66722d 9310 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9311 && sym_seg != absolute_section))
af65af87 9312 && !generic_force_reloc (fixP))
2f66722d
AM		 9313 {
9314 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9315 bfd_install_relocation subtracts them out again. I think
9316 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9317 it. FIXME. */
9318 value += fixP->fx_where + fixP->fx_frag->fr_address;
9319 }
252b5132
RH		 9320 }
9321#endif
9322#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9323 /* For some reason, the PE format does not store a
9324 section address offset for a PC relative symbol. */
9325 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9326 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9327 value += md_pcrel_from (fixP);
9328#endif
9329 }
fbeb56a4 9330#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9331 if (fixP->fx_addsy != NULL
9332 && S_IS_WEAK (fixP->fx_addsy)
9333 /* PR 16858: Do not modify weak function references. */
9334 && ! fixP->fx_pcrel)
fbeb56a4 9335 {
296a8689
NC		 9336#if !defined (TE_PEP)
9337 /* For x86 PE weak function symbols are neither PC-relative
9338 nor do they set S_IS_FUNCTION. So the only reliable way
9339 to detect them is to check the flags of their containing
9340 section. */
9341 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9342 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9343 ;
9344 else
9345#endif
fbeb56a4
DK		 9346 value -= S_GET_VALUE (fixP->fx_addsy);
9347 }
9348#endif
252b5132
RH		 9349
9350 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9351 and we must not disappoint it. */
252b5132 9352#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9353 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9354 switch (fixP->fx_r_type)
9355 {
9356 case BFD_RELOC_386_PLT32:
3e73aa7c 9357 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9358 /* Make the jump instruction point to the address of the operand. At
9359 runtime we merely add the offset to the actual PLT entry. */
9360 value = -4;
9361 break;
31312f95 9362
13ae64f3
JJ		 9363 case BFD_RELOC_386_TLS_GD:
9364 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9365 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9366 case BFD_RELOC_386_TLS_IE:
9367 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9368 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9369 case BFD_RELOC_X86_64_TLSGD:
9370 case BFD_RELOC_X86_64_TLSLD:
9371 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9372 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9373 value = 0; /* Fully resolved at runtime. No addend. */
9374 /* Fallthrough */
9375 case BFD_RELOC_386_TLS_LE:
9376 case BFD_RELOC_386_TLS_LDO_32:
9377 case BFD_RELOC_386_TLS_LE_32:
9378 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9379 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9380 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9381 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9382 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9383 break;
9384
67a4f2b7
AO		 9385 case BFD_RELOC_386_TLS_DESC_CALL:
9386 case BFD_RELOC_X86_64_TLSDESC_CALL:
9387 value = 0; /* Fully resolved at runtime. No addend. */
9388 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9389 fixP->fx_done = 0;
9390 return;
9391
47926f60
KH		 9392 case BFD_RELOC_VTABLE_INHERIT:
9393 case BFD_RELOC_VTABLE_ENTRY:
9394 fixP->fx_done = 0;
94f592af 9395 return;
47926f60
KH		 9396
9397 default:
9398 break;
9399 }
9400#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9401 *valP = value;
f86103b7 9402#endif /* !defined (TE_Mach) */
3e73aa7c 9403
3e73aa7c 9404 /* Are we finished with this relocation now? */
c6682705 9405 if (fixP->fx_addsy == NULL)
3e73aa7c 9406 fixP->fx_done = 1;
fbeb56a4
DK		 9407#if defined (OBJ_COFF) && defined (TE_PE)
9408 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9409 {
9410 fixP->fx_done = 0;
9411 /* Remember value for tc_gen_reloc. */
9412 fixP->fx_addnumber = value;
9413 /* Clear out the frag for now. */
9414 value = 0;
9415 }
9416#endif
3e73aa7c
JH		 9417 else if (use_rela_relocations)
9418 {
9419 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9420 /* Remember value for tc_gen_reloc. */
9421 fixP->fx_addnumber = value;
3e73aa7c
JH		 9422 value = 0;
9423 }
f86103b7 9424
94f592af 9425 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9426}
252b5132 9427\f
6d4af3c2 9428const char *
499ac353 9429md_atof (int type, char *litP, int *sizeP)
252b5132 9430{
499ac353
NC		 9431 /* This outputs the LITTLENUMs in REVERSE order;
9432 in accord with the bigendian 386. */
9433 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9434}
9435\f
2d545b82 9436static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9437
252b5132 9438static char *
e3bb37b5 9439output_invalid (int c)
252b5132 9440{
3882b010 9441 if (ISPRINT (c))
f9f21a03
L		 9442 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9443 "'%c'", c);
252b5132 9444 else
f9f21a03 9445 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9446 "(0x%x)", (unsigned char) c);
252b5132
RH		 9447 return output_invalid_buf;
9448}
9449
af6bdddf 9450/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9451
9452static const reg_entry *
4d1bb795 9453parse_real_register (char *reg_string, char **end_op)
252b5132 9454{
af6bdddf
AM		 9455 char *s = reg_string;
9456 char *p;
252b5132
RH		 9457 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9458 const reg_entry *r;
9459
9460 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9461 if (*s == REGISTER_PREFIX)
9462 ++s;
9463
9464 if (is_space_char (*s))
9465 ++s;
9466
9467 p = reg_name_given;
af6bdddf 9468 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9469 {
9470 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9471 return (const reg_entry *) NULL;
9472 s++;
252b5132
RH		 9473 }
9474
6588847e
DN		 9475 /* For naked regs, make sure that we are not dealing with an identifier.
9476 This prevents confusing an identifier like `eax_var' with register
9477 `eax'. */
9478 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9479 return (const reg_entry *) NULL;
9480
af6bdddf 9481 *end_op = s;
252b5132
RH		 9482
9483 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9484
5f47d35b 9485 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9486 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9487 {
5f47d35b
AM		 9488 if (is_space_char (*s))
9489 ++s;
9490 if (*s == '(')
9491 {
af6bdddf 9492 ++s;
5f47d35b
AM		 9493 if (is_space_char (*s))
9494 ++s;
9495 if (*s >= '0' && *s <= '7')
9496 {
db557034 9497 int fpr = *s - '0';
af6bdddf 9498 ++s;
5f47d35b
AM		 9499 if (is_space_char (*s))
9500 ++s;
9501 if (*s == ')')
9502 {
9503 *end_op = s + 1;
1e9cc1c2 9504 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9505 know (r);
9506 return r + fpr;
5f47d35b 9507 }
5f47d35b 9508 }
47926f60 9509 /* We have "%st(" then garbage. */
5f47d35b
AM		 9510 return (const reg_entry *) NULL;
9511 }
9512 }
9513
a60de03c
JB		 9514 if (r == NULL || allow_pseudo_reg)
9515 return r;
9516
0dfbf9d7 9517 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9518 return (const reg_entry *) NULL;
9519
192dc9c6
JB		 9520 if ((r->reg_type.bitfield.reg32
9521 || r->reg_type.bitfield.sreg3
9522 || r->reg_type.bitfield.control
9523 || r->reg_type.bitfield.debug
9524 || r->reg_type.bitfield.test)
9525 && !cpu_arch_flags.bitfield.cpui386)
9526 return (const reg_entry *) NULL;
9527
309d3373
JB		 9528 if (r->reg_type.bitfield.floatreg
9529 && !cpu_arch_flags.bitfield.cpu8087
9530 && !cpu_arch_flags.bitfield.cpu287
9531 && !cpu_arch_flags.bitfield.cpu387)
9532 return (const reg_entry *) NULL;
9533
192dc9c6
JB		 9534 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9535 return (const reg_entry *) NULL;
9536
9537 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9538 return (const reg_entry *) NULL;
9539
40f12533
L		 9540 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9541 return (const reg_entry *) NULL;
9542
43234a1e
L		 9543 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9544 && !cpu_arch_flags.bitfield.cpuavx512f)
9545 return (const reg_entry *) NULL;
9546
db51cc60 9547 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9548 if (!allow_index_reg
db51cc60
L		 9549 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9550 return (const reg_entry *) NULL;
9551
43234a1e
L		 9552 /* Upper 16 vector register is only available with VREX in 64bit
9553 mode. */
9554 if ((r->reg_flags & RegVRex))
9555 {
9556 if (!cpu_arch_flags.bitfield.cpuvrex
9557 || flag_code != CODE_64BIT)
9558 return (const reg_entry *) NULL;
9559
9560 i.need_vrex = 1;
9561 }
9562
a60de03c
JB		 9563 if (((r->reg_flags & (RegRex64 | RegRex))
9564 || r->reg_type.bitfield.reg64)
40fb9820 9565 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9566 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9567 && flag_code != CODE_64BIT)
20f0a1fc 9568 return (const reg_entry *) NULL;
1ae00879 9569
b7240065
JB		 9570 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9571 return (const reg_entry *) NULL;
9572
252b5132
RH		 9573 return r;
9574}
4d1bb795
JB		 9575
9576/* REG_STRING starts *before* REGISTER_PREFIX. */
9577
9578static const reg_entry *
9579parse_register (char *reg_string, char **end_op)
9580{
9581 const reg_entry *r;
9582
9583 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9584 r = parse_real_register (reg_string, end_op);
9585 else
9586 r = NULL;
9587 if (!r)
9588 {
9589 char *save = input_line_pointer;
9590 char c;
9591 symbolS *symbolP;
9592
9593 input_line_pointer = reg_string;
d02603dc 9594 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9595 symbolP = symbol_find (reg_string);
9596 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9597 {
9598 const expressionS *e = symbol_get_value_expression (symbolP);
9599
0398aac5 9600 know (e->X_op == O_register);
4eed87de 9601 know (e->X_add_number >= 0
c3fe08fa 9602 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9603 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9604 if ((r->reg_flags & RegVRex))
9605 i.need_vrex = 1;
4d1bb795
JB		 9606 *end_op = input_line_pointer;
9607 }
9608 *input_line_pointer = c;
9609 input_line_pointer = save;
9610 }
9611 return r;
9612}
9613
9614int
9615i386_parse_name (char *name, expressionS *e, char *nextcharP)
9616{
9617 const reg_entry *r;
9618 char *end = input_line_pointer;
9619
9620 *end = *nextcharP;
9621 r = parse_register (name, &input_line_pointer);
9622 if (r && end <= input_line_pointer)
9623 {
9624 *nextcharP = *input_line_pointer;
9625 *input_line_pointer = 0;
9626 e->X_op = O_register;
9627 e->X_add_number = r - i386_regtab;
9628 return 1;
9629 }
9630 input_line_pointer = end;
9631 *end = 0;
ee86248c 9632 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9633}
9634
9635void
9636md_operand (expressionS *e)
9637{
ee86248c
JB		 9638 char *end;
9639 const reg_entry *r;
4d1bb795 9640
ee86248c
JB		 9641 switch (*input_line_pointer)
9642 {
9643 case REGISTER_PREFIX:
9644 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9645 if (r)
9646 {
9647 e->X_op = O_register;
9648 e->X_add_number = r - i386_regtab;
9649 input_line_pointer = end;
9650 }
ee86248c
JB		 9651 break;
9652
9653 case '[':
9c2799c2 9654 gas_assert (intel_syntax);
ee86248c
JB		 9655 end = input_line_pointer++;
9656 expression (e);
9657 if (*input_line_pointer == ']')
9658 {
9659 ++input_line_pointer;
9660 e->X_op_symbol = make_expr_symbol (e);
9661 e->X_add_symbol = NULL;
9662 e->X_add_number = 0;
9663 e->X_op = O_index;
9664 }
9665 else
9666 {
9667 e->X_op = O_absent;
9668 input_line_pointer = end;
9669 }
9670 break;
4d1bb795
JB		 9671 }
9672}
9673
252b5132 9674\f
4cc782b5 9675#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9676const char *md_shortopts = "kVQ:sqn";
252b5132 9677#else
12b55ccc 9678const char *md_shortopts = "qn";
252b5132 9679#endif
6e0b89ee 9680
3e73aa7c 9681#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9682#define OPTION_64 (OPTION_MD_BASE + 1)
9683#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9684#define OPTION_MARCH (OPTION_MD_BASE + 3)
9685#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9686#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9687#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9688#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9689#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9690#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9691#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9692#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9693#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9694#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9695#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9696#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9697#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9698#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9699#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9700#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9701#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9702#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9703#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9704#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9705#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9706#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9707
99ad8390
NC		 9708struct option md_longopts[] =
9709{
3e73aa7c 9710 {"32", no_argument, NULL, OPTION_32},
321098a5 9711#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9712 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9713 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9714#endif
9715#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9716 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9717 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9718#endif
b3b91714 9719 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9720 {"march", required_argument, NULL, OPTION_MARCH},
9721 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9722 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9723 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9724 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9725 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9726 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9727 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9728 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9729 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9730 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9731 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9732 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9733 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9734# if defined (TE_PE) || defined (TE_PEP)
9735 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9736#endif
d1982f93 9737 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9738 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9739 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9740 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9741 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9742 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9743 {NULL, no_argument, NULL, 0}
9744};
9745size_t md_longopts_size = sizeof (md_longopts);
9746
9747int
17b9d67d 9748md_parse_option (int c, const char *arg)
252b5132 9749{
91d6fa6a 9750 unsigned int j;
293f5f65 9751 char *arch, *next, *saved;
9103f4f4 9752
252b5132
RH		 9753 switch (c)
9754 {
12b55ccc
L		 9755 case 'n':
9756 optimize_align_code = 0;
9757 break;
9758
a38cf1db
AM		 9759 case 'q':
9760 quiet_warnings = 1;
252b5132
RH		 9761 break;
9762
9763#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9764 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9765 should be emitted or not. FIXME: Not implemented. */
9766 case 'Q':
252b5132
RH		 9767 break;
9768
9769 /* -V: SVR4 argument to print version ID. */
9770 case 'V':
9771 print_version_id ();
9772 break;
9773
a38cf1db
AM		 9774 /* -k: Ignore for FreeBSD compatibility. */
9775 case 'k':
252b5132 9776 break;
4cc782b5
ILT		 9777
9778 case 's':
9779 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9780 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9781 break;
8dcea932
L		 9782
9783 case OPTION_MSHARED:
9784 shared = 1;
9785 break;
99ad8390 9786#endif
321098a5 9787#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9788 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9789 case OPTION_64:
9790 {
9791 const char **list, **l;
9792
3e73aa7c
JH		 9793 list = bfd_target_list ();
9794 for (l = list; *l != NULL; l++)
8620418b 9795 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9796 || strcmp (*l, "coff-x86-64") == 0
9797 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9798 || strcmp (*l, "pei-x86-64") == 0
9799 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9800 {
9801 default_arch = "x86_64";
9802 break;
9803 }
3e73aa7c 9804 if (*l == NULL)
2b5d6a91 9805 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9806 free (list);
9807 }
9808 break;
9809#endif
252b5132 9810
351f65ca 9811#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9812 case OPTION_X32:
351f65ca
L		 9813 if (IS_ELF)
9814 {
9815 const char **list, **l;
9816
9817 list = bfd_target_list ();
9818 for (l = list; *l != NULL; l++)
9819 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9820 {
9821 default_arch = "x86_64:32";
9822 break;
9823 }
9824 if (*l == NULL)
2b5d6a91 9825 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9826 free (list);
9827 }
9828 else
9829 as_fatal (_("32bit x86_64 is only supported for ELF"));
9830 break;
9831#endif
9832
6e0b89ee
AM		 9833 case OPTION_32:
9834 default_arch = "i386";
9835 break;
9836
b3b91714
AM		 9837 case OPTION_DIVIDE:
9838#ifdef SVR4_COMMENT_CHARS
9839 {
9840 char *n, *t;
9841 const char *s;
9842
add39d23 9843 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9844 t = n;
9845 for (s = i386_comment_chars; *s != '\0'; s++)
9846 if (*s != '/')
9847 *t++ = *s;
9848 *t = '\0';
9849 i386_comment_chars = n;
9850 }
9851#endif
9852 break;
9853
9103f4f4 9854 case OPTION_MARCH:
293f5f65
L		 9855 saved = xstrdup (arg);
9856 arch = saved;
9857 /* Allow -march=+nosse. */
9858 if (*arch == '+')
9859 arch++;
6305a203 9860 do
9103f4f4 9861 {
6305a203 9862 if (*arch == '.')
2b5d6a91 9863 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9864 next = strchr (arch, '+');
9865 if (next)
9866 *next++ = '\0';
91d6fa6a 9867 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9868 {
91d6fa6a 9869 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9870 {
6305a203 9871 /* Processor. */
1ded5609
JB		 9872 if (! cpu_arch[j].flags.bitfield.cpui386)
9873 continue;
9874
91d6fa6a 9875 cpu_arch_name = cpu_arch[j].name;
6305a203 9876 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9877 cpu_arch_flags = cpu_arch[j].flags;
9878 cpu_arch_isa = cpu_arch[j].type;
9879 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9880 if (!cpu_arch_tune_set)
9881 {
9882 cpu_arch_tune = cpu_arch_isa;
9883 cpu_arch_tune_flags = cpu_arch_isa_flags;
9884 }
9885 break;
9886 }
91d6fa6a
NC		 9887 else if (*cpu_arch [j].name == '.'
9888 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9889 {
9890 /* ISA entension. */
9891 i386_cpu_flags flags;
309d3373 9892
293f5f65
L		 9893 flags = cpu_flags_or (cpu_arch_flags,
9894 cpu_arch[j].flags);
81486035
L		 9895
9896 if (!valid_iamcu_cpu_flags (&flags))
9897 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9898 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9899 {
9900 if (cpu_sub_arch_name)
9901 {
9902 char *name = cpu_sub_arch_name;
9903 cpu_sub_arch_name = concat (name,
91d6fa6a 9904 cpu_arch[j].name,
1bf57e9f 9905 (const char *) NULL);
6305a203
L		 9906 free (name);
9907 }
9908 else
91d6fa6a 9909 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9910 cpu_arch_flags = flags;
a586129e 9911 cpu_arch_isa_flags = flags;
6305a203
L		 9912 }
9913 break;
ccc9c027 9914 }
9103f4f4 9915 }
6305a203 9916
293f5f65
L		 9917 if (j >= ARRAY_SIZE (cpu_arch))
9918 {
9919 /* Disable an ISA entension. */
9920 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
9921 if (strcmp (arch, cpu_noarch [j].name) == 0)
9922 {
9923 i386_cpu_flags flags;
9924
9925 flags = cpu_flags_and_not (cpu_arch_flags,
9926 cpu_noarch[j].flags);
9927 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9928 {
9929 if (cpu_sub_arch_name)
9930 {
9931 char *name = cpu_sub_arch_name;
9932 cpu_sub_arch_name = concat (arch,
9933 (const char *) NULL);
9934 free (name);
9935 }
9936 else
9937 cpu_sub_arch_name = xstrdup (arch);
9938 cpu_arch_flags = flags;
9939 cpu_arch_isa_flags = flags;
9940 }
9941 break;
9942 }
9943
9944 if (j >= ARRAY_SIZE (cpu_noarch))
9945 j = ARRAY_SIZE (cpu_arch);
9946 }
9947
91d6fa6a 9948 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9949 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9950
9951 arch = next;
9103f4f4 9952 }
293f5f65
L		 9953 while (next != NULL);
9954 free (saved);
9103f4f4
L		 9955 break;
9956
9957 case OPTION_MTUNE:
9958 if (*arg == '.')
2b5d6a91 9959 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9960 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9961 {
91d6fa6a 9962 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9963 {
ccc9c027 9964 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9965 cpu_arch_tune = cpu_arch [j].type;
9966 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9967 break;
9968 }
9969 }
91d6fa6a 9970 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9971 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9972 break;
9973
1efbbeb4
L		 9974 case OPTION_MMNEMONIC:
9975 if (strcasecmp (arg, "att") == 0)
9976 intel_mnemonic = 0;
9977 else if (strcasecmp (arg, "intel") == 0)
9978 intel_mnemonic = 1;
9979 else
2b5d6a91 9980 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9981 break;
9982
9983 case OPTION_MSYNTAX:
9984 if (strcasecmp (arg, "att") == 0)
9985 intel_syntax = 0;
9986 else if (strcasecmp (arg, "intel") == 0)
9987 intel_syntax = 1;
9988 else
2b5d6a91 9989 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9990 break;
9991
9992 case OPTION_MINDEX_REG:
9993 allow_index_reg = 1;
9994 break;
9995
9996 case OPTION_MNAKED_REG:
9997 allow_naked_reg = 1;
9998 break;
9999
10000 case OPTION_MOLD_GCC:
10001 old_gcc = 1;
1efbbeb4
L		 10002 break;
10003
c0f3af97
L		 10004 case OPTION_MSSE2AVX:
10005 sse2avx = 1;
10006 break;
10007
daf50ae7
L		 10008 case OPTION_MSSE_CHECK:
10009 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10010 sse_check = check_error;
daf50ae7 10011 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10012 sse_check = check_warning;
daf50ae7 10013 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10014 sse_check = check_none;
daf50ae7 10015 else
2b5d6a91 10016 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10017 break;
10018
7bab8ab5
JB		 10019 case OPTION_MOPERAND_CHECK:
10020 if (strcasecmp (arg, "error") == 0)
10021 operand_check = check_error;
10022 else if (strcasecmp (arg, "warning") == 0)
10023 operand_check = check_warning;
10024 else if (strcasecmp (arg, "none") == 0)
10025 operand_check = check_none;
10026 else
10027 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10028 break;
10029
539f890d
L		 10030 case OPTION_MAVXSCALAR:
10031 if (strcasecmp (arg, "128") == 0)
10032 avxscalar = vex128;
10033 else if (strcasecmp (arg, "256") == 0)
10034 avxscalar = vex256;
10035 else
2b5d6a91 10036 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10037 break;
10038
7e8b059b
L		 10039 case OPTION_MADD_BND_PREFIX:
10040 add_bnd_prefix = 1;
10041 break;
10042
43234a1e
L		 10043 case OPTION_MEVEXLIG:
10044 if (strcmp (arg, "128") == 0)
10045 evexlig = evexl128;
10046 else if (strcmp (arg, "256") == 0)
10047 evexlig = evexl256;
10048 else if (strcmp (arg, "512") == 0)
10049 evexlig = evexl512;
10050 else
10051 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10052 break;
10053
d3d3c6db
IT		 10054 case OPTION_MEVEXRCIG:
10055 if (strcmp (arg, "rne") == 0)
10056 evexrcig = rne;
10057 else if (strcmp (arg, "rd") == 0)
10058 evexrcig = rd;
10059 else if (strcmp (arg, "ru") == 0)
10060 evexrcig = ru;
10061 else if (strcmp (arg, "rz") == 0)
10062 evexrcig = rz;
10063 else
10064 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10065 break;
10066
43234a1e
L		 10067 case OPTION_MEVEXWIG:
10068 if (strcmp (arg, "0") == 0)
10069 evexwig = evexw0;
10070 else if (strcmp (arg, "1") == 0)
10071 evexwig = evexw1;
10072 else
10073 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10074 break;
10075
167ad85b
TG		 10076# if defined (TE_PE) || defined (TE_PEP)
10077 case OPTION_MBIG_OBJ:
10078 use_big_obj = 1;
10079 break;
10080#endif
10081
d1982f93 10082 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10083 if (strcasecmp (arg, "yes") == 0)
10084 omit_lock_prefix = 1;
10085 else if (strcasecmp (arg, "no") == 0)
10086 omit_lock_prefix = 0;
10087 else
10088 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10089 break;
10090
e4e00185
AS		 10091 case OPTION_MFENCE_AS_LOCK_ADD:
10092 if (strcasecmp (arg, "yes") == 0)
10093 avoid_fence = 1;
10094 else if (strcasecmp (arg, "no") == 0)
10095 avoid_fence = 0;
10096 else
10097 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10098 break;
10099
0cb4071e
L		 10100 case OPTION_MRELAX_RELOCATIONS:
10101 if (strcasecmp (arg, "yes") == 0)
10102 generate_relax_relocations = 1;
10103 else if (strcasecmp (arg, "no") == 0)
10104 generate_relax_relocations = 0;
10105 else
10106 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10107 break;
10108
5db04b09
L		 10109 case OPTION_MAMD64:
10110 cpu_arch_flags.bitfield.cpuamd64 = 1;
10111 cpu_arch_flags.bitfield.cpuintel64 = 0;
10112 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
10113 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
10114 break;
10115
10116 case OPTION_MINTEL64:
10117 cpu_arch_flags.bitfield.cpuamd64 = 0;
10118 cpu_arch_flags.bitfield.cpuintel64 = 1;
10119 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
10120 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
10121 break;
10122
252b5132
RH		 10123 default:
10124 return 0;
10125 }
10126 return 1;
10127}
10128
8a2c8fef
L		 10129#define MESSAGE_TEMPLATE \
10130" "
10131
293f5f65
L		 10132static char *
10133output_message (FILE *stream, char *p, char *message, char *start,
10134 int *left_p, const char *name, int len)
10135{
10136 int size = sizeof (MESSAGE_TEMPLATE);
10137 int left = *left_p;
10138
10139 /* Reserve 2 spaces for ", " or ",\0" */
10140 left -= len + 2;
10141
10142 /* Check if there is any room. */
10143 if (left >= 0)
10144 {
10145 if (p != start)
10146 {
10147 *p++ = ',';
10148 *p++ = ' ';
10149 }
10150 p = mempcpy (p, name, len);
10151 }
10152 else
10153 {
10154 /* Output the current message now and start a new one. */
10155 *p++ = ',';
10156 *p = '\0';
10157 fprintf (stream, "%s\n", message);
10158 p = start;
10159 left = size - (start - message) - len - 2;
10160
10161 gas_assert (left >= 0);
10162
10163 p = mempcpy (p, name, len);
10164 }
10165
10166 *left_p = left;
10167 return p;
10168}
10169
8a2c8fef 10170static void
1ded5609 10171show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10172{
10173 static char message[] = MESSAGE_TEMPLATE;
10174 char *start = message + 27;
10175 char *p;
10176 int size = sizeof (MESSAGE_TEMPLATE);
10177 int left;
10178 const char *name;
10179 int len;
10180 unsigned int j;
10181
10182 p = start;
10183 left = size - (start - message);
10184 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10185 {
10186 /* Should it be skipped? */
10187 if (cpu_arch [j].skip)
10188 continue;
10189
10190 name = cpu_arch [j].name;
10191 len = cpu_arch [j].len;
10192 if (*name == '.')
10193 {
10194 /* It is an extension. Skip if we aren't asked to show it. */
10195 if (ext)
10196 {
10197 name++;
10198 len--;
10199 }
10200 else
10201 continue;
10202 }
10203 else if (ext)
10204 {
10205 /* It is an processor. Skip if we show only extension. */
10206 continue;
10207 }
1ded5609
JB		 10208 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10209 {
10210 /* It is an impossible processor - skip. */
10211 continue;
10212 }
8a2c8fef 10213
293f5f65 10214 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10215 }
10216
293f5f65
L		 10217 /* Display disabled extensions. */
10218 if (ext)
10219 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10220 {
10221 name = cpu_noarch [j].name;
10222 len = cpu_noarch [j].len;
10223 p = output_message (stream, p, message, start, &left, name,
10224 len);
10225 }
10226
8a2c8fef
L		 10227 *p = '\0';
10228 fprintf (stream, "%s\n", message);
10229}
10230
252b5132 10231void
8a2c8fef 10232md_show_usage (FILE *stream)
252b5132 10233{
4cc782b5
ILT		 10234#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10235 fprintf (stream, _("\
a38cf1db
AM		 10236 -Q ignored\n\
10237 -V print assembler version number\n\
b3b91714
AM		 10238 -k ignored\n"));
10239#endif
10240 fprintf (stream, _("\
12b55ccc 10241 -n Do not optimize code alignment\n\
b3b91714
AM		 10242 -q quieten some warnings\n"));
10243#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10244 fprintf (stream, _("\
a38cf1db 10245 -s ignored\n"));
b3b91714 10246#endif
321098a5
L		 10247#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10248 || defined (TE_PE) || defined (TE_PEP))
751d281c 10249 fprintf (stream, _("\
570561f7 10250 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10251#endif
b3b91714
AM		 10252#ifdef SVR4_COMMENT_CHARS
10253 fprintf (stream, _("\
10254 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10255#else
10256 fprintf (stream, _("\
b3b91714 10257 --divide ignored\n"));
4cc782b5 10258#endif
9103f4f4 10259 fprintf (stream, _("\
6305a203 10260 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10261 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10262 show_arch (stream, 0, 1);
8a2c8fef
L		 10263 fprintf (stream, _("\
10264 EXTENSION is combination of:\n"));
1ded5609 10265 show_arch (stream, 1, 0);
6305a203 10266 fprintf (stream, _("\
8a2c8fef 10267 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10268 show_arch (stream, 0, 0);
ba104c83 10269 fprintf (stream, _("\
c0f3af97
L		 10270 -msse2avx encode SSE instructions with VEX prefix\n"));
10271 fprintf (stream, _("\
daf50ae7
L		 10272 -msse-check=[none|error|warning]\n\
10273 check SSE instructions\n"));
10274 fprintf (stream, _("\
7bab8ab5
JB		 10275 -moperand-check=[none|error|warning]\n\
10276 check operand combinations for validity\n"));
10277 fprintf (stream, _("\
539f890d
L		 10278 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10279 length\n"));
10280 fprintf (stream, _("\
43234a1e
L		 10281 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10282 length\n"));
10283 fprintf (stream, _("\
10284 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10285 for EVEX.W bit ignored instructions\n"));
10286 fprintf (stream, _("\
d3d3c6db
IT		 10287 -mevexrcig=[rne|rd|ru|rz]\n\
10288 encode EVEX instructions with specific EVEX.RC value\n\
10289 for SAE-only ignored instructions\n"));
10290 fprintf (stream, _("\
ba104c83
L		 10291 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10292 fprintf (stream, _("\
10293 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10294 fprintf (stream, _("\
10295 -mindex-reg support pseudo index registers\n"));
10296 fprintf (stream, _("\
10297 -mnaked-reg don't require `%%' prefix for registers\n"));
10298 fprintf (stream, _("\
10299 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10300 fprintf (stream, _("\
10301 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10302 fprintf (stream, _("\
10303 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10304# if defined (TE_PE) || defined (TE_PEP)
10305 fprintf (stream, _("\
10306 -mbig-obj generate big object files\n"));
10307#endif
d022bddd
IT		 10308 fprintf (stream, _("\
10309 -momit-lock-prefix=[no|yes]\n\
10310 strip all lock prefixes\n"));
5db04b09 10311 fprintf (stream, _("\
e4e00185
AS		 10312 -mfence-as-lock-add=[no|yes]\n\
10313 encode lfence, mfence and sfence as\n\
10314 lock addl $0x0, (%%{re}sp)\n"));
10315 fprintf (stream, _("\
0cb4071e
L		 10316 -mrelax-relocations=[no|yes]\n\
10317 generate relax relocations\n"));
10318 fprintf (stream, _("\
5db04b09
L		 10319 -mamd64 accept only AMD64 ISA\n"));
10320 fprintf (stream, _("\
10321 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10322}
10323
3e73aa7c 10324#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10325 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10326 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10327
10328/* Pick the target format to use. */
10329
47926f60 10330const char *
e3bb37b5 10331i386_target_format (void)
252b5132 10332{
351f65ca
L		 10333 if (!strncmp (default_arch, "x86_64", 6))
10334 {
10335 update_code_flag (CODE_64BIT, 1);
10336 if (default_arch[6] == '\0')
7f56bc95 10337 x86_elf_abi = X86_64_ABI;
351f65ca 10338 else
7f56bc95 10339 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10340 }
3e73aa7c 10341 else if (!strcmp (default_arch, "i386"))
78f12dd3 10342 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10343 else if (!strcmp (default_arch, "iamcu"))
10344 {
10345 update_code_flag (CODE_32BIT, 1);
10346 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10347 {
10348 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10349 cpu_arch_name = "iamcu";
10350 cpu_sub_arch_name = NULL;
10351 cpu_arch_flags = iamcu_flags;
10352 cpu_arch_isa = PROCESSOR_IAMCU;
10353 cpu_arch_isa_flags = iamcu_flags;
10354 if (!cpu_arch_tune_set)
10355 {
10356 cpu_arch_tune = cpu_arch_isa;
10357 cpu_arch_tune_flags = cpu_arch_isa_flags;
10358 }
10359 }
10360 else
10361 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10362 cpu_arch_name);
10363 }
3e73aa7c 10364 else
2b5d6a91 10365 as_fatal (_("unknown architecture"));
89507696
JB		 10366
10367 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10368 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10369 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10370 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10371
252b5132
RH		 10372 switch (OUTPUT_FLAVOR)
10373 {
9384f2ff 10374#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10375 case bfd_target_aout_flavour:
47926f60 10376 return AOUT_TARGET_FORMAT;
4c63da97 10377#endif
9384f2ff
AM		 10378#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10379# if defined (TE_PE) || defined (TE_PEP)
10380 case bfd_target_coff_flavour:
167ad85b
TG		 10381 if (flag_code == CODE_64BIT)
10382 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10383 else
10384 return "pe-i386";
9384f2ff 10385# elif defined (TE_GO32)
0561d57c
JK		 10386 case bfd_target_coff_flavour:
10387 return "coff-go32";
9384f2ff 10388# else
252b5132
RH		 10389 case bfd_target_coff_flavour:
10390 return "coff-i386";
9384f2ff 10391# endif
4c63da97 10392#endif
3e73aa7c 10393#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10394 case bfd_target_elf_flavour:
3e73aa7c 10395 {
351f65ca
L		 10396 const char *format;
10397
10398 switch (x86_elf_abi)
4fa24527 10399 {
351f65ca
L		 10400 default:
10401 format = ELF_TARGET_FORMAT;
10402 break;
7f56bc95 10403 case X86_64_ABI:
351f65ca 10404 use_rela_relocations = 1;
4fa24527 10405 object_64bit = 1;
351f65ca
L		 10406 format = ELF_TARGET_FORMAT64;
10407 break;
7f56bc95 10408 case X86_64_X32_ABI:
4fa24527 10409 use_rela_relocations = 1;
351f65ca 10410 object_64bit = 1;
862be3fb 10411 disallow_64bit_reloc = 1;
351f65ca
L		 10412 format = ELF_TARGET_FORMAT32;
10413 break;
4fa24527 10414 }
3632d14b 10415 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10416 {
7f56bc95 10417 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10418 as_fatal (_("Intel L1OM is 64bit only"));
10419 return ELF_TARGET_L1OM_FORMAT;
10420 }
b49f93f6 10421 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10422 {
10423 if (x86_elf_abi != X86_64_ABI)
10424 as_fatal (_("Intel K1OM is 64bit only"));
10425 return ELF_TARGET_K1OM_FORMAT;
10426 }
81486035
L		 10427 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10428 {
10429 if (x86_elf_abi != I386_ABI)
10430 as_fatal (_("Intel MCU is 32bit only"));
10431 return ELF_TARGET_IAMCU_FORMAT;
10432 }
8a9036a4 10433 else
351f65ca 10434 return format;
3e73aa7c 10435 }
e57f8c65
TG		 10436#endif
10437#if defined (OBJ_MACH_O)
10438 case bfd_target_mach_o_flavour:
d382c579
TG		 10439 if (flag_code == CODE_64BIT)
10440 {
10441 use_rela_relocations = 1;
10442 object_64bit = 1;
10443 return "mach-o-x86-64";
10444 }
10445 else
10446 return "mach-o-i386";
4c63da97 10447#endif
252b5132
RH		 10448 default:
10449 abort ();
10450 return NULL;
10451 }
10452}
10453
47926f60 10454#endif /* OBJ_MAYBE_ more than one */
252b5132 10455\f
252b5132 10456symbolS *
7016a5d5 10457md_undefined_symbol (char *name)
252b5132 10458{
18dc2407
ILT		 10459 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10460 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10461 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10462 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10463 {
10464 if (!GOT_symbol)
10465 {
10466 if (symbol_find (name))
10467 as_bad (_("GOT already in symbol table"));
10468 GOT_symbol = symbol_new (name, undefined_section,
10469 (valueT) 0, &zero_address_frag);
10470 };
10471 return GOT_symbol;
10472 }
252b5132
RH		 10473 return 0;
10474}
10475
10476/* Round up a section size to the appropriate boundary. */
47926f60 10477
252b5132 10478valueT
7016a5d5 10479md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10480{
4c63da97
AM		 10481#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10482 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10483 {
10484 /* For a.out, force the section size to be aligned. If we don't do
10485 this, BFD will align it for us, but it will not write out the
10486 final bytes of the section. This may be a bug in BFD, but it is
10487 easier to fix it here since that is how the other a.out targets
10488 work. */
10489 int align;
10490
10491 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10492 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10493 }
252b5132
RH		 10494#endif
10495
10496 return size;
10497}
10498
10499/* On the i386, PC-relative offsets are relative to the start of the
10500 next instruction. That is, the address of the offset, plus its
10501 size, since the offset is always the last part of the insn. */
10502
10503long
e3bb37b5 10504md_pcrel_from (fixS *fixP)
252b5132
RH		 10505{
10506 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10507}
10508
10509#ifndef I386COFF
10510
10511static void
e3bb37b5 10512s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10513{
29b0f896 10514 int temp;
252b5132 10515
8a75718c
JB		 10516#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10517 if (IS_ELF)
10518 obj_elf_section_change_hook ();
10519#endif
252b5132
RH		 10520 temp = get_absolute_expression ();
10521 subseg_set (bss_section, (subsegT) temp);
10522 demand_empty_rest_of_line ();
10523}
10524
10525#endif
10526
252b5132 10527void
e3bb37b5 10528i386_validate_fix (fixS *fixp)
252b5132 10529{
02a86693 10530 if (fixp->fx_subsy)
252b5132 10531 {
02a86693 10532 if (fixp->fx_subsy == GOT_symbol)
23df1078 10533 {
02a86693
L		 10534 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10535 {
10536 if (!object_64bit)
10537 abort ();
10538#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10539 if (fixp->fx_tcbit2)
56ceb5b5
L		 10540 fixp->fx_r_type = (fixp->fx_tcbit
10541 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10542 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10543 else
10544#endif
10545 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10546 }
d6ab8113 10547 else
02a86693
L		 10548 {
10549 if (!object_64bit)
10550 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10551 else
10552 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10553 }
10554 fixp->fx_subsy = 0;
23df1078 10555 }
252b5132 10556 }
02a86693
L		 10557#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10558 else if (!object_64bit)
10559 {
10560 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10561 && fixp->fx_tcbit2)
10562 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10563 }
10564#endif
252b5132
RH		 10565}
10566
252b5132 10567arelent *
7016a5d5 10568tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10569{
10570 arelent *rel;
10571 bfd_reloc_code_real_type code;
10572
10573 switch (fixp->fx_r_type)
10574 {
8ce3d284 10575#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10576 case BFD_RELOC_SIZE32:
10577 case BFD_RELOC_SIZE64:
10578 if (S_IS_DEFINED (fixp->fx_addsy)
10579 && !S_IS_EXTERNAL (fixp->fx_addsy))
10580 {
10581 /* Resolve size relocation against local symbol to size of
10582 the symbol plus addend. */
10583 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10584 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10585 && !fits_in_unsigned_long (value))
10586 as_bad_where (fixp->fx_file, fixp->fx_line,
10587 _("symbol size computation overflow"));
10588 fixp->fx_addsy = NULL;
10589 fixp->fx_subsy = NULL;
10590 md_apply_fix (fixp, (valueT *) &value, NULL);
10591 return NULL;
10592 }
8ce3d284 10593#endif
8fd4256d 10594
3e73aa7c
JH		 10595 case BFD_RELOC_X86_64_PLT32:
10596 case BFD_RELOC_X86_64_GOT32:
10597 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10598 case BFD_RELOC_X86_64_GOTPCRELX:
10599 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10600 case BFD_RELOC_386_PLT32:
10601 case BFD_RELOC_386_GOT32:
02a86693 10602 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10603 case BFD_RELOC_386_GOTOFF:
10604 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10605 case BFD_RELOC_386_TLS_GD:
10606 case BFD_RELOC_386_TLS_LDM:
10607 case BFD_RELOC_386_TLS_LDO_32:
10608 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10609 case BFD_RELOC_386_TLS_IE:
10610 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10611 case BFD_RELOC_386_TLS_LE_32:
10612 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10613 case BFD_RELOC_386_TLS_GOTDESC:
10614 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10615 case BFD_RELOC_X86_64_TLSGD:
10616 case BFD_RELOC_X86_64_TLSLD:
10617 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10618 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10619 case BFD_RELOC_X86_64_GOTTPOFF:
10620 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10621 case BFD_RELOC_X86_64_TPOFF64:
10622 case BFD_RELOC_X86_64_GOTOFF64:
10623 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10624 case BFD_RELOC_X86_64_GOT64:
10625 case BFD_RELOC_X86_64_GOTPCREL64:
10626 case BFD_RELOC_X86_64_GOTPC64:
10627 case BFD_RELOC_X86_64_GOTPLT64:
10628 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10629 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10630 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10631 case BFD_RELOC_RVA:
10632 case BFD_RELOC_VTABLE_ENTRY:
10633 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10634#ifdef TE_PE
10635 case BFD_RELOC_32_SECREL:
10636#endif
252b5132
RH		 10637 code = fixp->fx_r_type;
10638 break;
dbbaec26
L		 10639 case BFD_RELOC_X86_64_32S:
10640 if (!fixp->fx_pcrel)
10641 {
10642 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10643 code = fixp->fx_r_type;
10644 break;
10645 }
252b5132 10646 default:
93382f6d 10647 if (fixp->fx_pcrel)
252b5132 10648 {
93382f6d
AM		 10649 switch (fixp->fx_size)
10650 {
10651 default:
b091f402
AM		 10652 as_bad_where (fixp->fx_file, fixp->fx_line,
10653 _("can not do %d byte pc-relative relocation"),
10654 fixp->fx_size);
93382f6d
AM		 10655 code = BFD_RELOC_32_PCREL;
10656 break;
10657 case 1: code = BFD_RELOC_8_PCREL; break;
10658 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10659 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10660#ifdef BFD64
10661 case 8: code = BFD_RELOC_64_PCREL; break;
10662#endif
93382f6d
AM		 10663 }
10664 }
10665 else
10666 {
10667 switch (fixp->fx_size)
10668 {
10669 default:
b091f402
AM		 10670 as_bad_where (fixp->fx_file, fixp->fx_line,
10671 _("can not do %d byte relocation"),
10672 fixp->fx_size);
93382f6d
AM		 10673 code = BFD_RELOC_32;
10674 break;
10675 case 1: code = BFD_RELOC_8; break;
10676 case 2: code = BFD_RELOC_16; break;
10677 case 4: code = BFD_RELOC_32; break;
937149dd 10678#ifdef BFD64
3e73aa7c 10679 case 8: code = BFD_RELOC_64; break;
937149dd 10680#endif
93382f6d 10681 }
252b5132
RH		 10682 }
10683 break;
10684 }
252b5132 10685
d182319b
JB		 10686 if ((code == BFD_RELOC_32
10687 || code == BFD_RELOC_32_PCREL
10688 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10689 && GOT_symbol
10690 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10691 {
4fa24527 10692 if (!object_64bit)
d6ab8113
JB		 10693 code = BFD_RELOC_386_GOTPC;
10694 else
10695 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10696 }
7b81dfbb
AJ		 10697 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10698 && GOT_symbol
10699 && fixp->fx_addsy == GOT_symbol)
10700 {
10701 code = BFD_RELOC_X86_64_GOTPC64;
10702 }
252b5132 10703
add39d23
TS		 10704 rel = XNEW (arelent);
10705 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10706 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10707
10708 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10709
3e73aa7c
JH		 10710 if (!use_rela_relocations)
10711 {
10712 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10713 vtable entry to be used in the relocation's section offset. */
10714 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10715 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10716#if defined (OBJ_COFF) && defined (TE_PE)
10717 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10718 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10719 else
10720#endif
c6682705 10721 rel->addend = 0;
3e73aa7c
JH		 10722 }
10723 /* Use the rela in 64bit mode. */
252b5132 10724 else
3e73aa7c 10725 {
862be3fb
L		 10726 if (disallow_64bit_reloc)
10727 switch (code)
10728 {
862be3fb
L		 10729 case BFD_RELOC_X86_64_DTPOFF64:
10730 case BFD_RELOC_X86_64_TPOFF64:
10731 case BFD_RELOC_64_PCREL:
10732 case BFD_RELOC_X86_64_GOTOFF64:
10733 case BFD_RELOC_X86_64_GOT64:
10734 case BFD_RELOC_X86_64_GOTPCREL64:
10735 case BFD_RELOC_X86_64_GOTPC64:
10736 case BFD_RELOC_X86_64_GOTPLT64:
10737 case BFD_RELOC_X86_64_PLTOFF64:
10738 as_bad_where (fixp->fx_file, fixp->fx_line,
10739 _("cannot represent relocation type %s in x32 mode"),
10740 bfd_get_reloc_code_name (code));
10741 break;
10742 default:
10743 break;
10744 }
10745
062cd5e7
AS		 10746 if (!fixp->fx_pcrel)
10747 rel->addend = fixp->fx_offset;
10748 else
10749 switch (code)
10750 {
10751 case BFD_RELOC_X86_64_PLT32:
10752 case BFD_RELOC_X86_64_GOT32:
10753 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10754 case BFD_RELOC_X86_64_GOTPCRELX:
10755 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10756 case BFD_RELOC_X86_64_TLSGD:
10757 case BFD_RELOC_X86_64_TLSLD:
10758 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10759 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10760 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10761 rel->addend = fixp->fx_offset - fixp->fx_size;
10762 break;
10763 default:
10764 rel->addend = (section->vma
10765 - fixp->fx_size
10766 + fixp->fx_addnumber
10767 + md_pcrel_from (fixp));
10768 break;
10769 }
3e73aa7c
JH		 10770 }
10771
252b5132
RH		 10772 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10773 if (rel->howto == NULL)
10774 {
10775 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10776 _("cannot represent relocation type %s"),
252b5132
RH		 10777 bfd_get_reloc_code_name (code));
10778 /* Set howto to a garbage value so that we can keep going. */
10779 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10780 gas_assert (rel->howto != NULL);
252b5132
RH		 10781 }
10782
10783 return rel;
10784}
10785
ee86248c 10786#include "tc-i386-intel.c"
54cfded0 10787
a60de03c
JB		 10788void
10789tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10790{
a60de03c
JB		 10791 int saved_naked_reg;
10792 char saved_register_dot;
54cfded0 10793
a60de03c
JB		 10794 saved_naked_reg = allow_naked_reg;
10795 allow_naked_reg = 1;
10796 saved_register_dot = register_chars['.'];
10797 register_chars['.'] = '.';
10798 allow_pseudo_reg = 1;
10799 expression_and_evaluate (exp);
10800 allow_pseudo_reg = 0;
10801 register_chars['.'] = saved_register_dot;
10802 allow_naked_reg = saved_naked_reg;
10803
e96d56a1 10804 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10805 {
a60de03c
JB		 10806 if ((addressT) exp->X_add_number < i386_regtab_size)
10807 {
10808 exp->X_op = O_constant;
10809 exp->X_add_number = i386_regtab[exp->X_add_number]
10810 .dw2_regnum[flag_code >> 1];
10811 }
10812 else
10813 exp->X_op = O_illegal;
54cfded0 10814 }
54cfded0
AM		 10815}
10816
10817void
10818tc_x86_frame_initial_instructions (void)
10819{
a60de03c
JB		 10820 static unsigned int sp_regno[2];
10821
10822 if (!sp_regno[flag_code >> 1])
10823 {
10824 char *saved_input = input_line_pointer;
10825 char sp[][4] = {"esp", "rsp"};
10826 expressionS exp;
a4447b93 10827
a60de03c
JB		 10828 input_line_pointer = sp[flag_code >> 1];
10829 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10830 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10831 sp_regno[flag_code >> 1] = exp.X_add_number;
10832 input_line_pointer = saved_input;
10833 }
a4447b93 10834
61ff971f
L		 10835 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10836 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10837}
d2b2c203 10838
d7921315
L		 10839int
10840x86_dwarf2_addr_size (void)
10841{
10842#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10843 if (x86_elf_abi == X86_64_X32_ABI)
10844 return 4;
10845#endif
10846 return bfd_arch_bits_per_address (stdoutput) / 8;
10847}
10848
d2b2c203
DJ		 10849int
10850i386_elf_section_type (const char *str, size_t len)
10851{
10852 if (flag_code == CODE_64BIT
10853 && len == sizeof ("unwind") - 1
10854 && strncmp (str, "unwind", 6) == 0)
10855 return SHT_X86_64_UNWIND;
10856
10857 return -1;
10858}
bb41ade5 10859
ad5fec3b
EB		 10860#ifdef TE_SOLARIS
10861void
10862i386_solaris_fix_up_eh_frame (segT sec)
10863{
10864 if (flag_code == CODE_64BIT)
10865 elf_section_type (sec) = SHT_X86_64_UNWIND;
10866}
10867#endif
10868
bb41ade5
AM		 10869#ifdef TE_PE
10870void
10871tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10872{
91d6fa6a 10873 expressionS exp;
bb41ade5 10874
91d6fa6a
NC		 10875 exp.X_op = O_secrel;
10876 exp.X_add_symbol = symbol;
10877 exp.X_add_number = 0;
10878 emit_expr (&exp, size);
bb41ade5
AM		 10879}
10880#endif
3b22753a
L		 10881
10882#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10883/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10884
01e1a5bc 10885bfd_vma
6d4af3c2 10886x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10887{
10888 if (flag_code == CODE_64BIT)
10889 {
10890 if (letter == 'l')
10891 return SHF_X86_64_LARGE;
10892
8f3bae45 10893 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10894 }
3b22753a 10895 else
8f3bae45 10896 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10897 return -1;
10898}
10899
01e1a5bc 10900bfd_vma
3b22753a
L		 10901x86_64_section_word (char *str, size_t len)
10902{
8620418b 10903 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10904 return SHF_X86_64_LARGE;
10905
10906 return -1;
10907}
10908
10909static void
10910handle_large_common (int small ATTRIBUTE_UNUSED)
10911{
10912 if (flag_code != CODE_64BIT)
10913 {
10914 s_comm_internal (0, elf_common_parse);
10915 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10916 }
10917 else
10918 {
10919 static segT lbss_section;
10920 asection *saved_com_section_ptr = elf_com_section_ptr;
10921 asection *saved_bss_section = bss_section;
10922
10923 if (lbss_section == NULL)
10924 {
10925 flagword applicable;
10926 segT seg = now_seg;
10927 subsegT subseg = now_subseg;
10928
10929 /* The .lbss section is for local .largecomm symbols. */
10930 lbss_section = subseg_new (".lbss", 0);
10931 applicable = bfd_applicable_section_flags (stdoutput);
10932 bfd_set_section_flags (stdoutput, lbss_section,
10933 applicable & SEC_ALLOC);
10934 seg_info (lbss_section)->bss = 1;
10935
10936 subseg_set (seg, subseg);
10937 }
10938
10939 elf_com_section_ptr = &_bfd_elf_large_com_section;
10940 bss_section = lbss_section;
10941
10942 s_comm_internal (0, elf_common_parse);
10943
10944 elf_com_section_ptr = saved_com_section_ptr;
10945 bss_section = saved_bss_section;
10946 }
10947}
10948#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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