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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
219d1afa | 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
84 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 85 | #define YMMWORD_MNEM_SUFFIX 'y' |
43234a1e | 86 | #define ZMMWORD_MNEM_SUFFIX 'z' |
6305a203 L |
87 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
88 | in instructions. */ | |
89 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
90 | ||
91 | #define END_OF_INSN '\0' | |
92 | ||
93 | /* | |
94 | 'templates' is for grouping together 'template' structures for opcodes | |
95 | of the same name. This is only used for storing the insns in the grand | |
96 | ole hash table of insns. | |
97 | The templates themselves start at START and range up to (but not including) | |
98 | END. | |
99 | */ | |
100 | typedef struct | |
101 | { | |
d3ce72d0 NC |
102 | const insn_template *start; |
103 | const insn_template *end; | |
6305a203 L |
104 | } |
105 | templates; | |
106 | ||
107 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
108 | typedef struct | |
109 | { | |
110 | unsigned int regmem; /* codes register or memory operand */ | |
111 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
112 | unsigned int mode; /* how to interpret regmem & reg */ | |
113 | } | |
114 | modrm_byte; | |
115 | ||
116 | /* x86-64 extension prefix. */ | |
117 | typedef int rex_byte; | |
118 | ||
6305a203 L |
119 | /* 386 opcode byte to code indirect addressing. */ |
120 | typedef struct | |
121 | { | |
122 | unsigned base; | |
123 | unsigned index; | |
124 | unsigned scale; | |
125 | } | |
126 | sib_byte; | |
127 | ||
6305a203 L |
128 | /* x86 arch names, types and features */ |
129 | typedef struct | |
130 | { | |
131 | const char *name; /* arch name */ | |
8a2c8fef | 132 | unsigned int len; /* arch string length */ |
6305a203 L |
133 | enum processor_type type; /* arch type */ |
134 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 135 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
136 | } |
137 | arch_entry; | |
138 | ||
293f5f65 L |
139 | /* Used to turn off indicated flags. */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
143 | unsigned int len; /* arch string length */ | |
144 | i386_cpu_flags flags; /* cpu feature flags */ | |
145 | } | |
146 | noarch_entry; | |
147 | ||
78f12dd3 | 148 | static void update_code_flag (int, int); |
e3bb37b5 L |
149 | static void set_code_flag (int); |
150 | static void set_16bit_gcc_code_flag (int); | |
151 | static void set_intel_syntax (int); | |
1efbbeb4 | 152 | static void set_intel_mnemonic (int); |
db51cc60 | 153 | static void set_allow_index_reg (int); |
7bab8ab5 | 154 | static void set_check (int); |
e3bb37b5 | 155 | static void set_cpu_arch (int); |
6482c264 | 156 | #ifdef TE_PE |
e3bb37b5 | 157 | static void pe_directive_secrel (int); |
6482c264 | 158 | #endif |
e3bb37b5 L |
159 | static void signed_cons (int); |
160 | static char *output_invalid (int c); | |
ee86248c JB |
161 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
162 | const char *); | |
163 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
164 | const char *); | |
a7619375 | 165 | static int i386_att_operand (char *); |
e3bb37b5 | 166 | static int i386_intel_operand (char *, int); |
ee86248c JB |
167 | static int i386_intel_simplify (expressionS *); |
168 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
169 | static const reg_entry *parse_register (char *, char **); |
170 | static char *parse_insn (char *, char *); | |
171 | static char *parse_operands (char *, const char *); | |
172 | static void swap_operands (void); | |
4d456e3d | 173 | static void swap_2_operands (int, int); |
e3bb37b5 L |
174 | static void optimize_imm (void); |
175 | static void optimize_disp (void); | |
83b16ac6 | 176 | static const insn_template *match_template (char); |
e3bb37b5 L |
177 | static int check_string (void); |
178 | static int process_suffix (void); | |
179 | static int check_byte_reg (void); | |
180 | static int check_long_reg (void); | |
181 | static int check_qword_reg (void); | |
182 | static int check_word_reg (void); | |
183 | static int finalize_imm (void); | |
184 | static int process_operands (void); | |
185 | static const seg_entry *build_modrm_byte (void); | |
186 | static void output_insn (void); | |
187 | static void output_imm (fragS *, offsetT); | |
188 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 189 | #ifndef I386COFF |
e3bb37b5 | 190 | static void s_bss (int); |
252b5132 | 191 | #endif |
17d4e2a2 L |
192 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
193 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
194 | #endif | |
252b5132 | 195 | |
a847613f | 196 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 197 | |
43234a1e L |
198 | /* This struct describes rounding control and SAE in the instruction. */ |
199 | struct RC_Operation | |
200 | { | |
201 | enum rc_type | |
202 | { | |
203 | rne = 0, | |
204 | rd, | |
205 | ru, | |
206 | rz, | |
207 | saeonly | |
208 | } type; | |
209 | int operand; | |
210 | }; | |
211 | ||
212 | static struct RC_Operation rc_op; | |
213 | ||
214 | /* The struct describes masking, applied to OPERAND in the instruction. | |
215 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
216 | whether merging or zeroing mask is used. */ | |
217 | struct Mask_Operation | |
218 | { | |
219 | const reg_entry *mask; | |
220 | unsigned int zeroing; | |
221 | /* The operand where this operation is associated. */ | |
222 | int operand; | |
223 | }; | |
224 | ||
225 | static struct Mask_Operation mask_op; | |
226 | ||
227 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
228 | broadcast factor. */ | |
229 | struct Broadcast_Operation | |
230 | { | |
231 | /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ | |
232 | int type; | |
233 | ||
234 | /* Index of broadcasted operand. */ | |
235 | int operand; | |
236 | }; | |
237 | ||
238 | static struct Broadcast_Operation broadcast_op; | |
239 | ||
c0f3af97 L |
240 | /* VEX prefix. */ |
241 | typedef struct | |
242 | { | |
43234a1e L |
243 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
244 | unsigned char bytes[4]; | |
c0f3af97 L |
245 | unsigned int length; |
246 | /* Destination or source register specifier. */ | |
247 | const reg_entry *register_specifier; | |
248 | } vex_prefix; | |
249 | ||
252b5132 | 250 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 251 | i386_insn. */ |
252b5132 | 252 | |
520dc8e8 AM |
253 | union i386_op |
254 | { | |
255 | expressionS *disps; | |
256 | expressionS *imms; | |
257 | const reg_entry *regs; | |
258 | }; | |
259 | ||
a65babc9 L |
260 | enum i386_error |
261 | { | |
86e026a4 | 262 | operand_size_mismatch, |
a65babc9 L |
263 | operand_type_mismatch, |
264 | register_type_mismatch, | |
265 | number_of_operands_mismatch, | |
266 | invalid_instruction_suffix, | |
267 | bad_imm4, | |
268 | old_gcc_only, | |
269 | unsupported_with_intel_mnemonic, | |
270 | unsupported_syntax, | |
6c30d220 L |
271 | unsupported, |
272 | invalid_vsib_address, | |
7bab8ab5 | 273 | invalid_vector_register_set, |
43234a1e L |
274 | unsupported_vector_index_register, |
275 | unsupported_broadcast, | |
276 | broadcast_not_on_src_operand, | |
277 | broadcast_needed, | |
278 | unsupported_masking, | |
279 | mask_not_on_destination, | |
280 | no_default_mask, | |
281 | unsupported_rc_sae, | |
282 | rc_sae_operand_not_last_imm, | |
283 | invalid_register_operand, | |
a65babc9 L |
284 | }; |
285 | ||
252b5132 RH |
286 | struct _i386_insn |
287 | { | |
47926f60 | 288 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 289 | insn_template tm; |
252b5132 | 290 | |
7d5e4556 L |
291 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
292 | or qword, if given. */ | |
252b5132 RH |
293 | char suffix; |
294 | ||
47926f60 | 295 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
296 | unsigned int operands; |
297 | ||
298 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
299 | of given register, displacement, memory operands and immediate | |
47926f60 | 300 | operands. */ |
252b5132 RH |
301 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
302 | ||
303 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 304 | use OP[i] for the corresponding operand. */ |
40fb9820 | 305 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 306 | |
520dc8e8 AM |
307 | /* Displacement expression, immediate expression, or register for each |
308 | operand. */ | |
309 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 310 | |
3e73aa7c JH |
311 | /* Flags for operands. */ |
312 | unsigned int flags[MAX_OPERANDS]; | |
313 | #define Operand_PCrel 1 | |
314 | ||
252b5132 | 315 | /* Relocation type for operand */ |
f86103b7 | 316 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 317 | |
252b5132 RH |
318 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
319 | the base index byte below. */ | |
320 | const reg_entry *base_reg; | |
321 | const reg_entry *index_reg; | |
322 | unsigned int log2_scale_factor; | |
323 | ||
324 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 325 | explicit segment overrides are given. */ |
ce8a8b2f | 326 | const seg_entry *seg[2]; |
252b5132 | 327 | |
8325cc63 JB |
328 | /* Copied first memory operand string, for re-checking. */ |
329 | char *memop1_string; | |
330 | ||
252b5132 RH |
331 | /* PREFIX holds all the given prefix opcodes (usually null). |
332 | PREFIXES is the number of prefix opcodes. */ | |
333 | unsigned int prefixes; | |
334 | unsigned char prefix[MAX_PREFIXES]; | |
335 | ||
336 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 337 | addressing modes of this insn are encoded. */ |
252b5132 | 338 | modrm_byte rm; |
3e73aa7c | 339 | rex_byte rex; |
43234a1e | 340 | rex_byte vrex; |
252b5132 | 341 | sib_byte sib; |
c0f3af97 | 342 | vex_prefix vex; |
b6169b20 | 343 | |
43234a1e L |
344 | /* Masking attributes. */ |
345 | struct Mask_Operation *mask; | |
346 | ||
347 | /* Rounding control and SAE attributes. */ | |
348 | struct RC_Operation *rounding; | |
349 | ||
350 | /* Broadcasting attributes. */ | |
351 | struct Broadcast_Operation *broadcast; | |
352 | ||
353 | /* Compressed disp8*N attribute. */ | |
354 | unsigned int memshift; | |
355 | ||
86fa6981 L |
356 | /* Prefer load or store in encoding. */ |
357 | enum | |
358 | { | |
359 | dir_encoding_default = 0, | |
360 | dir_encoding_load, | |
361 | dir_encoding_store | |
362 | } dir_encoding; | |
891edac4 | 363 | |
a501d77e L |
364 | /* Prefer 8bit or 32bit displacement in encoding. */ |
365 | enum | |
366 | { | |
367 | disp_encoding_default = 0, | |
368 | disp_encoding_8bit, | |
369 | disp_encoding_32bit | |
370 | } disp_encoding; | |
f8a5c266 | 371 | |
6b6b6807 L |
372 | /* Prefer the REX byte in encoding. */ |
373 | bfd_boolean rex_encoding; | |
374 | ||
b6f8c7c4 L |
375 | /* Disable instruction size optimization. */ |
376 | bfd_boolean no_optimize; | |
377 | ||
86fa6981 L |
378 | /* How to encode vector instructions. */ |
379 | enum | |
380 | { | |
381 | vex_encoding_default = 0, | |
382 | vex_encoding_vex2, | |
383 | vex_encoding_vex3, | |
384 | vex_encoding_evex | |
385 | } vec_encoding; | |
386 | ||
d5de92cf L |
387 | /* REP prefix. */ |
388 | const char *rep_prefix; | |
389 | ||
165de32a L |
390 | /* HLE prefix. */ |
391 | const char *hle_prefix; | |
42164a71 | 392 | |
7e8b059b L |
393 | /* Have BND prefix. */ |
394 | const char *bnd_prefix; | |
395 | ||
04ef582a L |
396 | /* Have NOTRACK prefix. */ |
397 | const char *notrack_prefix; | |
398 | ||
891edac4 | 399 | /* Error message. */ |
a65babc9 | 400 | enum i386_error error; |
252b5132 RH |
401 | }; |
402 | ||
403 | typedef struct _i386_insn i386_insn; | |
404 | ||
43234a1e L |
405 | /* Link RC type with corresponding string, that'll be looked for in |
406 | asm. */ | |
407 | struct RC_name | |
408 | { | |
409 | enum rc_type type; | |
410 | const char *name; | |
411 | unsigned int len; | |
412 | }; | |
413 | ||
414 | static const struct RC_name RC_NamesTable[] = | |
415 | { | |
416 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
417 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
418 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
419 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
420 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
421 | }; | |
422 | ||
252b5132 RH |
423 | /* List of chars besides those in app.c:symbol_chars that can start an |
424 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 425 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 426 | #ifdef LEX_AT |
32137342 NC |
427 | "@" |
428 | #endif | |
429 | #ifdef LEX_QM | |
430 | "?" | |
252b5132 | 431 | #endif |
32137342 | 432 | ; |
252b5132 | 433 | |
29b0f896 AM |
434 | #if (defined (TE_I386AIX) \ |
435 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 436 | && !defined (TE_GNU) \ |
29b0f896 | 437 | && !defined (TE_LINUX) \ |
8d63c93e RM |
438 | && !defined (TE_NACL) \ |
439 | && !defined (TE_NETWARE) \ | |
29b0f896 | 440 | && !defined (TE_FreeBSD) \ |
5b806d27 | 441 | && !defined (TE_DragonFly) \ |
29b0f896 | 442 | && !defined (TE_NetBSD))) |
252b5132 | 443 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
444 | pre-processor is disabled, these aren't very useful. The option |
445 | --divide will remove '/' from this list. */ | |
446 | const char *i386_comment_chars = "#/"; | |
447 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 448 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 449 | |
b3b91714 AM |
450 | #else |
451 | const char *i386_comment_chars = "#"; | |
452 | #define PREFIX_SEPARATOR '/' | |
453 | #endif | |
454 | ||
252b5132 RH |
455 | /* This array holds the chars that only start a comment at the beginning of |
456 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
457 | .line and .file directives will appear in the pre-processed output. |
458 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 459 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
460 | #NO_APP at the beginning of its output. |
461 | Also note that comments started like this one will always work if | |
252b5132 | 462 | '/' isn't otherwise defined. */ |
b3b91714 | 463 | const char line_comment_chars[] = "#/"; |
252b5132 | 464 | |
63a0b638 | 465 | const char line_separator_chars[] = ";"; |
252b5132 | 466 | |
ce8a8b2f AM |
467 | /* Chars that can be used to separate mant from exp in floating point |
468 | nums. */ | |
252b5132 RH |
469 | const char EXP_CHARS[] = "eE"; |
470 | ||
ce8a8b2f AM |
471 | /* Chars that mean this number is a floating point constant |
472 | As in 0f12.456 | |
473 | or 0d1.2345e12. */ | |
252b5132 RH |
474 | const char FLT_CHARS[] = "fFdDxX"; |
475 | ||
ce8a8b2f | 476 | /* Tables for lexical analysis. */ |
252b5132 RH |
477 | static char mnemonic_chars[256]; |
478 | static char register_chars[256]; | |
479 | static char operand_chars[256]; | |
480 | static char identifier_chars[256]; | |
481 | static char digit_chars[256]; | |
482 | ||
ce8a8b2f | 483 | /* Lexical macros. */ |
252b5132 RH |
484 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
485 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
486 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
487 | #define is_space_char(x) ((x) == ' ') | |
488 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
489 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
490 | ||
0234cb7c | 491 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
492 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
493 | ||
494 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
495 | effect this we maintain a stack of saved characters that we've smashed | |
496 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 497 | assembler instruction). */ |
252b5132 | 498 | static char save_stack[32]; |
ce8a8b2f | 499 | static char *save_stack_p; |
252b5132 RH |
500 | #define END_STRING_AND_SAVE(s) \ |
501 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
502 | #define RESTORE_END_STRING(s) \ | |
503 | do { *(s) = *--save_stack_p; } while (0) | |
504 | ||
47926f60 | 505 | /* The instruction we're assembling. */ |
252b5132 RH |
506 | static i386_insn i; |
507 | ||
508 | /* Possible templates for current insn. */ | |
509 | static const templates *current_templates; | |
510 | ||
31b2323c L |
511 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
512 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
513 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 514 | |
47926f60 | 515 | /* Current operand we are working on. */ |
ee86248c | 516 | static int this_operand = -1; |
252b5132 | 517 | |
3e73aa7c JH |
518 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
519 | these. */ | |
520 | ||
521 | enum flag_code { | |
522 | CODE_32BIT, | |
523 | CODE_16BIT, | |
524 | CODE_64BIT }; | |
525 | ||
526 | static enum flag_code flag_code; | |
4fa24527 | 527 | static unsigned int object_64bit; |
862be3fb | 528 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
529 | static int use_rela_relocations = 0; |
530 | ||
7af8ed2d NC |
531 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
532 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
533 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
534 | ||
351f65ca L |
535 | /* The ELF ABI to use. */ |
536 | enum x86_elf_abi | |
537 | { | |
538 | I386_ABI, | |
7f56bc95 L |
539 | X86_64_ABI, |
540 | X86_64_X32_ABI | |
351f65ca L |
541 | }; |
542 | ||
543 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 544 | #endif |
351f65ca | 545 | |
167ad85b TG |
546 | #if defined (TE_PE) || defined (TE_PEP) |
547 | /* Use big object file format. */ | |
548 | static int use_big_obj = 0; | |
549 | #endif | |
550 | ||
8dcea932 L |
551 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
552 | /* 1 if generating code for a shared library. */ | |
553 | static int shared = 0; | |
554 | #endif | |
555 | ||
47926f60 KH |
556 | /* 1 for intel syntax, |
557 | 0 if att syntax. */ | |
558 | static int intel_syntax = 0; | |
252b5132 | 559 | |
e89c5eaa L |
560 | /* 1 for Intel64 ISA, |
561 | 0 if AMD64 ISA. */ | |
562 | static int intel64; | |
563 | ||
1efbbeb4 L |
564 | /* 1 for intel mnemonic, |
565 | 0 if att mnemonic. */ | |
566 | static int intel_mnemonic = !SYSV386_COMPAT; | |
567 | ||
5209009a | 568 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
569 | static int old_gcc = OLDGCC_COMPAT; |
570 | ||
a60de03c JB |
571 | /* 1 if pseudo registers are permitted. */ |
572 | static int allow_pseudo_reg = 0; | |
573 | ||
47926f60 KH |
574 | /* 1 if register prefix % not required. */ |
575 | static int allow_naked_reg = 0; | |
252b5132 | 576 | |
33eaf5de | 577 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
578 | instructions supporting it, even if this prefix wasn't specified |
579 | explicitly. */ | |
580 | static int add_bnd_prefix = 0; | |
581 | ||
ba104c83 | 582 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
583 | static int allow_index_reg = 0; |
584 | ||
d022bddd IT |
585 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
586 | specified explicitly. */ | |
587 | static int omit_lock_prefix = 0; | |
588 | ||
e4e00185 AS |
589 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
590 | "lock addl $0, (%{re}sp)". */ | |
591 | static int avoid_fence = 0; | |
592 | ||
0cb4071e L |
593 | /* 1 if the assembler should generate relax relocations. */ |
594 | ||
595 | static int generate_relax_relocations | |
596 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
597 | ||
7bab8ab5 | 598 | static enum check_kind |
daf50ae7 | 599 | { |
7bab8ab5 JB |
600 | check_none = 0, |
601 | check_warning, | |
602 | check_error | |
daf50ae7 | 603 | } |
7bab8ab5 | 604 | sse_check, operand_check = check_warning; |
daf50ae7 | 605 | |
b6f8c7c4 L |
606 | /* Optimization: |
607 | 1. Clear the REX_W bit with register operand if possible. | |
608 | 2. Above plus use 128bit vector instruction to clear the full vector | |
609 | register. | |
610 | */ | |
611 | static int optimize = 0; | |
612 | ||
613 | /* Optimization: | |
614 | 1. Clear the REX_W bit with register operand if possible. | |
615 | 2. Above plus use 128bit vector instruction to clear the full vector | |
616 | register. | |
617 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
618 | "testb $imm7,%r8". | |
619 | */ | |
620 | static int optimize_for_space = 0; | |
621 | ||
2ca3ace5 L |
622 | /* Register prefix used for error message. */ |
623 | static const char *register_prefix = "%"; | |
624 | ||
47926f60 KH |
625 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
626 | leave, push, and pop instructions so that gcc has the same stack | |
627 | frame as in 32 bit mode. */ | |
628 | static char stackop_size = '\0'; | |
eecb386c | 629 | |
12b55ccc L |
630 | /* Non-zero to optimize code alignment. */ |
631 | int optimize_align_code = 1; | |
632 | ||
47926f60 KH |
633 | /* Non-zero to quieten some warnings. */ |
634 | static int quiet_warnings = 0; | |
a38cf1db | 635 | |
47926f60 KH |
636 | /* CPU name. */ |
637 | static const char *cpu_arch_name = NULL; | |
6305a203 | 638 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 639 | |
47926f60 | 640 | /* CPU feature flags. */ |
40fb9820 L |
641 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
642 | ||
ccc9c027 L |
643 | /* If we have selected a cpu we are generating instructions for. */ |
644 | static int cpu_arch_tune_set = 0; | |
645 | ||
9103f4f4 | 646 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 647 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
648 | |
649 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 650 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 651 | |
ccc9c027 | 652 | /* CPU instruction set architecture used. */ |
fbf3f584 | 653 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 654 | |
9103f4f4 | 655 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 656 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 657 | |
fddf5b5b AM |
658 | /* If set, conditional jumps are not automatically promoted to handle |
659 | larger than a byte offset. */ | |
660 | static unsigned int no_cond_jump_promotion = 0; | |
661 | ||
c0f3af97 L |
662 | /* Encode SSE instructions with VEX prefix. */ |
663 | static unsigned int sse2avx; | |
664 | ||
539f890d L |
665 | /* Encode scalar AVX instructions with specific vector length. */ |
666 | static enum | |
667 | { | |
668 | vex128 = 0, | |
669 | vex256 | |
670 | } avxscalar; | |
671 | ||
43234a1e L |
672 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
673 | static enum | |
674 | { | |
675 | evexl128 = 0, | |
676 | evexl256, | |
677 | evexl512 | |
678 | } evexlig; | |
679 | ||
680 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
681 | static enum | |
682 | { | |
683 | evexw0 = 0, | |
684 | evexw1 | |
685 | } evexwig; | |
686 | ||
d3d3c6db IT |
687 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
688 | static enum rc_type evexrcig = rne; | |
689 | ||
29b0f896 | 690 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 691 | static symbolS *GOT_symbol; |
29b0f896 | 692 | |
a4447b93 RH |
693 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
694 | unsigned int x86_dwarf2_return_column; | |
695 | ||
696 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
697 | int x86_cie_data_alignment; | |
698 | ||
252b5132 | 699 | /* Interface to relax_segment. |
fddf5b5b AM |
700 | There are 3 major relax states for 386 jump insns because the |
701 | different types of jumps add different sizes to frags when we're | |
702 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 703 | |
47926f60 | 704 | /* Types. */ |
93c2a809 AM |
705 | #define UNCOND_JUMP 0 |
706 | #define COND_JUMP 1 | |
707 | #define COND_JUMP86 2 | |
fddf5b5b | 708 | |
47926f60 | 709 | /* Sizes. */ |
252b5132 RH |
710 | #define CODE16 1 |
711 | #define SMALL 0 | |
29b0f896 | 712 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 713 | #define BIG 2 |
29b0f896 | 714 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
715 | |
716 | #ifndef INLINE | |
717 | #ifdef __GNUC__ | |
718 | #define INLINE __inline__ | |
719 | #else | |
720 | #define INLINE | |
721 | #endif | |
722 | #endif | |
723 | ||
fddf5b5b AM |
724 | #define ENCODE_RELAX_STATE(type, size) \ |
725 | ((relax_substateT) (((type) << 2) | (size))) | |
726 | #define TYPE_FROM_RELAX_STATE(s) \ | |
727 | ((s) >> 2) | |
728 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
729 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
730 | |
731 | /* This table is used by relax_frag to promote short jumps to long | |
732 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
733 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
734 | don't allow a short jump in a 32 bit code segment to be promoted to | |
735 | a 16 bit offset jump because it's slower (requires data size | |
736 | prefix), and doesn't work, unless the destination is in the bottom | |
737 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
738 | ||
739 | const relax_typeS md_relax_table[] = | |
740 | { | |
24eab124 AM |
741 | /* The fields are: |
742 | 1) most positive reach of this state, | |
743 | 2) most negative reach of this state, | |
93c2a809 | 744 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 745 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 746 | |
fddf5b5b | 747 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
748 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
749 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
750 | /* dword jmp adds 4 bytes to frag: | |
751 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 752 | {0, 0, 4, 0}, |
93c2a809 AM |
753 | /* word jmp adds 2 byte2 to frag: |
754 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
755 | {0, 0, 2, 0}, |
756 | ||
93c2a809 AM |
757 | /* COND_JUMP states. */ |
758 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
759 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
760 | /* dword conditionals adds 5 bytes to frag: | |
761 | 1 extra opcode byte, 4 displacement bytes. */ | |
762 | {0, 0, 5, 0}, | |
fddf5b5b | 763 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
764 | 1 extra opcode byte, 2 displacement bytes. */ |
765 | {0, 0, 3, 0}, | |
766 | ||
767 | /* COND_JUMP86 states. */ | |
768 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
769 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
770 | /* dword conditionals adds 5 bytes to frag: | |
771 | 1 extra opcode byte, 4 displacement bytes. */ | |
772 | {0, 0, 5, 0}, | |
773 | /* word conditionals add 4 bytes to frag: | |
774 | 1 displacement byte and a 3 byte long branch insn. */ | |
775 | {0, 0, 4, 0} | |
252b5132 RH |
776 | }; |
777 | ||
9103f4f4 L |
778 | static const arch_entry cpu_arch[] = |
779 | { | |
89507696 JB |
780 | /* Do not replace the first two entries - i386_target_format() |
781 | relies on them being there in this order. */ | |
8a2c8fef | 782 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 783 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 784 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 785 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 786 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 787 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 788 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 789 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 790 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 791 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 792 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 793 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 794 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 795 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 796 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 797 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 798 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 799 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 800 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 801 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 802 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 803 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 804 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 805 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 806 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 807 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 808 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 809 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 810 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 811 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 812 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 813 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 814 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 815 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 816 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 817 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 818 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 819 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 820 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 821 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 822 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 823 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 824 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 825 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 826 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 827 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 828 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 829 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 830 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 831 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 832 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 833 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 834 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 835 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 836 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 837 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 838 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 839 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 840 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 841 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 842 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 843 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 844 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 845 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 846 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 847 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 848 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 849 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 850 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 851 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 852 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 853 | CPU_ZNVER1_FLAGS, 0 }, |
7b458c12 | 854 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 855 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 856 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 857 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 858 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 859 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 860 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 861 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 862 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 863 | CPU_387_FLAGS, 0 }, |
1848e567 L |
864 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
865 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 866 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 867 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 868 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 869 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 870 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 871 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 872 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 873 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 874 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 875 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 876 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 877 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 878 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 879 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 880 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 881 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 882 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 883 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 884 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 885 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 886 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 887 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 888 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 889 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 890 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 891 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 892 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 893 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 894 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 895 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 896 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 897 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 898 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 899 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 900 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 901 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 902 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 903 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 904 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 905 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 906 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 907 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 908 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 909 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 910 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 911 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 912 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 913 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 914 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 915 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 916 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 917 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 918 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 919 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 920 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 921 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 922 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 923 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 924 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 925 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 926 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 927 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 928 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 929 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 930 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 931 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 932 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 933 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 934 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 935 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 937 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 938 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 940 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 942 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 944 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 945 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 946 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 947 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 948 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 949 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 950 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 951 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 952 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 953 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 954 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 955 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 956 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 957 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 958 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 959 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 960 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 961 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 962 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 963 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 964 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 965 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 966 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 967 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 968 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 969 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 970 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 971 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 972 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 973 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 974 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 975 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 976 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 977 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 978 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 979 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 980 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 981 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 982 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 983 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 984 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 985 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 986 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 987 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 988 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 989 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 990 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 991 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 992 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 993 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 994 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 995 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 996 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 997 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 998 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 999 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1000 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1001 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1002 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1003 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1004 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1005 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1006 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1007 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1008 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1009 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1010 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1011 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1012 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1013 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1014 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1016 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1017 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1018 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1019 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1020 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1021 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1022 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1023 | CPU_IBT_FLAGS, 0 }, | |
1024 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1025 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1026 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1027 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1028 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1029 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1030 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1031 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1032 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1033 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1034 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1035 | CPU_PCONFIG_FLAGS, 0 }, | |
293f5f65 L |
1036 | }; |
1037 | ||
1038 | static const noarch_entry cpu_noarch[] = | |
1039 | { | |
1040 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1041 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1042 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1043 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
1044 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1045 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1046 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1047 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1048 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1049 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1050 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1051 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1052 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1053 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1054 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1055 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1056 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1057 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1058 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1059 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1060 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1061 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1062 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1063 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1064 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1065 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1066 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1067 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1068 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1069 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1070 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
e413e4e9 AM |
1071 | }; |
1072 | ||
704209c0 | 1073 | #ifdef I386COFF |
a6c24e68 NC |
1074 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1075 | is allowed to be optional. */ | |
1076 | ||
1077 | static symbolS * | |
1078 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1079 | { | |
1080 | addressT align = 0; | |
1081 | ||
1082 | SKIP_WHITESPACE (); | |
1083 | ||
7ab9ffdd | 1084 | if (needs_align |
a6c24e68 NC |
1085 | && *input_line_pointer == ',') |
1086 | { | |
1087 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1088 | |
a6c24e68 NC |
1089 | if (align == (addressT) -1) |
1090 | return NULL; | |
1091 | } | |
1092 | else | |
1093 | { | |
1094 | if (size >= 8) | |
1095 | align = 3; | |
1096 | else if (size >= 4) | |
1097 | align = 2; | |
1098 | else if (size >= 2) | |
1099 | align = 1; | |
1100 | else | |
1101 | align = 0; | |
1102 | } | |
1103 | ||
1104 | bss_alloc (symbolP, size, align); | |
1105 | return symbolP; | |
1106 | } | |
1107 | ||
704209c0 | 1108 | static void |
a6c24e68 NC |
1109 | pe_lcomm (int needs_align) |
1110 | { | |
1111 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1112 | } | |
704209c0 | 1113 | #endif |
a6c24e68 | 1114 | |
29b0f896 AM |
1115 | const pseudo_typeS md_pseudo_table[] = |
1116 | { | |
1117 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1118 | {"align", s_align_bytes, 0}, | |
1119 | #else | |
1120 | {"align", s_align_ptwo, 0}, | |
1121 | #endif | |
1122 | {"arch", set_cpu_arch, 0}, | |
1123 | #ifndef I386COFF | |
1124 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1125 | #else |
1126 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1127 | #endif |
1128 | {"ffloat", float_cons, 'f'}, | |
1129 | {"dfloat", float_cons, 'd'}, | |
1130 | {"tfloat", float_cons, 'x'}, | |
1131 | {"value", cons, 2}, | |
d182319b | 1132 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1133 | {"noopt", s_ignore, 0}, |
1134 | {"optim", s_ignore, 0}, | |
1135 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1136 | {"code16", set_code_flag, CODE_16BIT}, | |
1137 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1138 | #ifdef BFD64 |
29b0f896 | 1139 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1140 | #endif |
29b0f896 AM |
1141 | {"intel_syntax", set_intel_syntax, 1}, |
1142 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1143 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1144 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1145 | {"allow_index_reg", set_allow_index_reg, 1}, |
1146 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1147 | {"sse_check", set_check, 0}, |
1148 | {"operand_check", set_check, 1}, | |
3b22753a L |
1149 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1150 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1151 | #else |
68d20676 | 1152 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1153 | {"loc", dwarf2_directive_loc, 0}, |
1154 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1155 | #endif |
6482c264 NC |
1156 | #ifdef TE_PE |
1157 | {"secrel32", pe_directive_secrel, 0}, | |
1158 | #endif | |
29b0f896 AM |
1159 | {0, 0, 0} |
1160 | }; | |
1161 | ||
1162 | /* For interface with expression (). */ | |
1163 | extern char *input_line_pointer; | |
1164 | ||
1165 | /* Hash table for instruction mnemonic lookup. */ | |
1166 | static struct hash_control *op_hash; | |
1167 | ||
1168 | /* Hash table for register lookup. */ | |
1169 | static struct hash_control *reg_hash; | |
1170 | \f | |
ce8a8b2f AM |
1171 | /* Various efficient no-op patterns for aligning code labels. |
1172 | Note: Don't try to assemble the instructions in the comments. | |
1173 | 0L and 0w are not legal. */ | |
62a02d25 L |
1174 | static const unsigned char f32_1[] = |
1175 | {0x90}; /* nop */ | |
1176 | static const unsigned char f32_2[] = | |
1177 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1178 | static const unsigned char f32_3[] = | |
1179 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1180 | static const unsigned char f32_4[] = | |
1181 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1182 | static const unsigned char f32_6[] = |
1183 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1184 | static const unsigned char f32_7[] = | |
1185 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1186 | static const unsigned char f16_3[] = |
3ae729d5 | 1187 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1188 | static const unsigned char f16_4[] = |
3ae729d5 L |
1189 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1190 | static const unsigned char jump_disp8[] = | |
1191 | {0xeb}; /* jmp disp8 */ | |
1192 | static const unsigned char jump32_disp32[] = | |
1193 | {0xe9}; /* jmp disp32 */ | |
1194 | static const unsigned char jump16_disp32[] = | |
1195 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1196 | /* 32-bit NOPs patterns. */ |
1197 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1198 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1199 | }; |
1200 | /* 16-bit NOPs patterns. */ | |
1201 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1202 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1203 | }; |
1204 | /* nopl (%[re]ax) */ | |
1205 | static const unsigned char alt_3[] = | |
1206 | {0x0f,0x1f,0x00}; | |
1207 | /* nopl 0(%[re]ax) */ | |
1208 | static const unsigned char alt_4[] = | |
1209 | {0x0f,0x1f,0x40,0x00}; | |
1210 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1211 | static const unsigned char alt_5[] = | |
1212 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1213 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1214 | static const unsigned char alt_6[] = | |
1215 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1216 | /* nopl 0L(%[re]ax) */ | |
1217 | static const unsigned char alt_7[] = | |
1218 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1219 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1220 | static const unsigned char alt_8[] = | |
1221 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1222 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1223 | static const unsigned char alt_9[] = | |
1224 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1225 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1226 | static const unsigned char alt_10[] = | |
1227 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1228 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1229 | static const unsigned char alt_11[] = | |
1230 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1231 | /* 32-bit and 64-bit NOPs patterns. */ |
1232 | static const unsigned char *const alt_patt[] = { | |
1233 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1234 | alt_9, alt_10, alt_11 |
62a02d25 L |
1235 | }; |
1236 | ||
1237 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1238 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1239 | ||
1240 | static void | |
1241 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1242 | int count, int max_single_nop_size) | |
1243 | ||
1244 | { | |
3ae729d5 L |
1245 | /* Place the longer NOP first. */ |
1246 | int last; | |
1247 | int offset; | |
1248 | const unsigned char *nops = patt[max_single_nop_size - 1]; | |
1249 | ||
1250 | /* Use the smaller one if the requsted one isn't available. */ | |
1251 | if (nops == NULL) | |
62a02d25 | 1252 | { |
3ae729d5 L |
1253 | max_single_nop_size--; |
1254 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1255 | } |
1256 | ||
3ae729d5 L |
1257 | last = count % max_single_nop_size; |
1258 | ||
1259 | count -= last; | |
1260 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1261 | memcpy (where + offset, nops, max_single_nop_size); | |
1262 | ||
1263 | if (last) | |
1264 | { | |
1265 | nops = patt[last - 1]; | |
1266 | if (nops == NULL) | |
1267 | { | |
1268 | /* Use the smaller one plus one-byte NOP if the needed one | |
1269 | isn't available. */ | |
1270 | last--; | |
1271 | nops = patt[last - 1]; | |
1272 | memcpy (where + offset, nops, last); | |
1273 | where[offset + last] = *patt[0]; | |
1274 | } | |
1275 | else | |
1276 | memcpy (where + offset, nops, last); | |
1277 | } | |
62a02d25 L |
1278 | } |
1279 | ||
3ae729d5 L |
1280 | static INLINE int |
1281 | fits_in_imm7 (offsetT num) | |
1282 | { | |
1283 | return (num & 0x7f) == num; | |
1284 | } | |
1285 | ||
1286 | static INLINE int | |
1287 | fits_in_imm31 (offsetT num) | |
1288 | { | |
1289 | return (num & 0x7fffffff) == num; | |
1290 | } | |
62a02d25 L |
1291 | |
1292 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1293 | single NOP instruction LIMIT. */ | |
1294 | ||
1295 | void | |
3ae729d5 | 1296 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1297 | { |
3ae729d5 | 1298 | const unsigned char *const *patt = NULL; |
62a02d25 | 1299 | int max_single_nop_size; |
3ae729d5 L |
1300 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1301 | int max_number_of_nops; | |
62a02d25 | 1302 | |
3ae729d5 | 1303 | switch (fragP->fr_type) |
62a02d25 | 1304 | { |
3ae729d5 L |
1305 | case rs_fill_nop: |
1306 | case rs_align_code: | |
1307 | break; | |
1308 | default: | |
62a02d25 L |
1309 | return; |
1310 | } | |
1311 | ||
ccc9c027 L |
1312 | /* We need to decide which NOP sequence to use for 32bit and |
1313 | 64bit. When -mtune= is used: | |
4eed87de | 1314 | |
76bc74dc L |
1315 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1316 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1317 | 2. For the rest, alt_patt will be used. |
1318 | ||
1319 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1320 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1321 | be used. |
ccc9c027 L |
1322 | |
1323 | When -march= or .arch is used, we can't use anything beyond | |
1324 | cpu_arch_isa_flags. */ | |
1325 | ||
1326 | if (flag_code == CODE_16BIT) | |
1327 | { | |
3ae729d5 L |
1328 | patt = f16_patt; |
1329 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1330 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1331 | max_number_of_nops = 2; | |
252b5132 | 1332 | } |
33fef721 | 1333 | else |
ccc9c027 | 1334 | { |
fbf3f584 | 1335 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1336 | { |
1337 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1338 | switch (cpu_arch_tune) | |
1339 | { | |
1340 | case PROCESSOR_UNKNOWN: | |
1341 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1342 | optimize with nops. */ |
1343 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1344 | patt = alt_patt; |
ccc9c027 L |
1345 | else |
1346 | patt = f32_patt; | |
1347 | break; | |
ccc9c027 L |
1348 | case PROCESSOR_PENTIUM4: |
1349 | case PROCESSOR_NOCONA: | |
ef05d495 | 1350 | case PROCESSOR_CORE: |
76bc74dc | 1351 | case PROCESSOR_CORE2: |
bd5295b2 | 1352 | case PROCESSOR_COREI7: |
3632d14b | 1353 | case PROCESSOR_L1OM: |
7a9068fe | 1354 | case PROCESSOR_K1OM: |
76bc74dc | 1355 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1356 | case PROCESSOR_K6: |
1357 | case PROCESSOR_ATHLON: | |
1358 | case PROCESSOR_K8: | |
4eed87de | 1359 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1360 | case PROCESSOR_BD: |
029f3522 | 1361 | case PROCESSOR_ZNVER: |
7b458c12 | 1362 | case PROCESSOR_BT: |
80b8656c | 1363 | patt = alt_patt; |
ccc9c027 | 1364 | break; |
76bc74dc | 1365 | case PROCESSOR_I386: |
ccc9c027 L |
1366 | case PROCESSOR_I486: |
1367 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1368 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1369 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1370 | case PROCESSOR_GENERIC32: |
1371 | patt = f32_patt; | |
1372 | break; | |
4eed87de | 1373 | } |
ccc9c027 L |
1374 | } |
1375 | else | |
1376 | { | |
fbf3f584 | 1377 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1378 | { |
1379 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1380 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1381 | PROCESSOR_UNKNOWN. */ |
1382 | abort (); | |
1383 | break; | |
1384 | ||
76bc74dc | 1385 | case PROCESSOR_I386: |
ccc9c027 L |
1386 | case PROCESSOR_I486: |
1387 | case PROCESSOR_PENTIUM: | |
81486035 | 1388 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1389 | case PROCESSOR_K6: |
1390 | case PROCESSOR_ATHLON: | |
1391 | case PROCESSOR_K8: | |
4eed87de | 1392 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1393 | case PROCESSOR_BD: |
029f3522 | 1394 | case PROCESSOR_ZNVER: |
7b458c12 | 1395 | case PROCESSOR_BT: |
ccc9c027 L |
1396 | case PROCESSOR_GENERIC32: |
1397 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1398 | with nops. */ |
1399 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1400 | patt = alt_patt; |
ccc9c027 L |
1401 | else |
1402 | patt = f32_patt; | |
1403 | break; | |
76bc74dc L |
1404 | case PROCESSOR_PENTIUMPRO: |
1405 | case PROCESSOR_PENTIUM4: | |
1406 | case PROCESSOR_NOCONA: | |
1407 | case PROCESSOR_CORE: | |
ef05d495 | 1408 | case PROCESSOR_CORE2: |
bd5295b2 | 1409 | case PROCESSOR_COREI7: |
3632d14b | 1410 | case PROCESSOR_L1OM: |
7a9068fe | 1411 | case PROCESSOR_K1OM: |
22109423 | 1412 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1413 | patt = alt_patt; |
ccc9c027 L |
1414 | else |
1415 | patt = f32_patt; | |
1416 | break; | |
1417 | case PROCESSOR_GENERIC64: | |
80b8656c | 1418 | patt = alt_patt; |
ccc9c027 | 1419 | break; |
4eed87de | 1420 | } |
ccc9c027 L |
1421 | } |
1422 | ||
76bc74dc L |
1423 | if (patt == f32_patt) |
1424 | { | |
3ae729d5 L |
1425 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1426 | /* Limit number of NOPs to 2 for older processors. */ | |
1427 | max_number_of_nops = 2; | |
76bc74dc L |
1428 | } |
1429 | else | |
1430 | { | |
3ae729d5 L |
1431 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1432 | /* Limit number of NOPs to 7 for newer processors. */ | |
1433 | max_number_of_nops = 7; | |
1434 | } | |
1435 | } | |
1436 | ||
1437 | if (limit == 0) | |
1438 | limit = max_single_nop_size; | |
1439 | ||
1440 | if (fragP->fr_type == rs_fill_nop) | |
1441 | { | |
1442 | /* Output NOPs for .nop directive. */ | |
1443 | if (limit > max_single_nop_size) | |
1444 | { | |
1445 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1446 | _("invalid single nop size: %d " | |
1447 | "(expect within [0, %d])"), | |
1448 | limit, max_single_nop_size); | |
1449 | return; | |
1450 | } | |
1451 | } | |
1452 | else | |
1453 | fragP->fr_var = count; | |
1454 | ||
1455 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1456 | { | |
1457 | /* Generate jump over NOPs. */ | |
1458 | offsetT disp = count - 2; | |
1459 | if (fits_in_imm7 (disp)) | |
1460 | { | |
1461 | /* Use "jmp disp8" if possible. */ | |
1462 | count = disp; | |
1463 | where[0] = jump_disp8[0]; | |
1464 | where[1] = count; | |
1465 | where += 2; | |
1466 | } | |
1467 | else | |
1468 | { | |
1469 | unsigned int size_of_jump; | |
1470 | ||
1471 | if (flag_code == CODE_16BIT) | |
1472 | { | |
1473 | where[0] = jump16_disp32[0]; | |
1474 | where[1] = jump16_disp32[1]; | |
1475 | size_of_jump = 2; | |
1476 | } | |
1477 | else | |
1478 | { | |
1479 | where[0] = jump32_disp32[0]; | |
1480 | size_of_jump = 1; | |
1481 | } | |
1482 | ||
1483 | count -= size_of_jump + 4; | |
1484 | if (!fits_in_imm31 (count)) | |
1485 | { | |
1486 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1487 | _("jump over nop padding out of range")); | |
1488 | return; | |
1489 | } | |
1490 | ||
1491 | md_number_to_chars (where + size_of_jump, count, 4); | |
1492 | where += size_of_jump + 4; | |
76bc74dc | 1493 | } |
ccc9c027 | 1494 | } |
3ae729d5 L |
1495 | |
1496 | /* Generate multiple NOPs. */ | |
1497 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1498 | } |
1499 | ||
c6fb90c8 | 1500 | static INLINE int |
0dfbf9d7 | 1501 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1502 | { |
0dfbf9d7 | 1503 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1504 | { |
1505 | case 3: | |
0dfbf9d7 | 1506 | if (x->array[2]) |
c6fb90c8 | 1507 | return 0; |
1a0670f3 | 1508 | /* Fall through. */ |
c6fb90c8 | 1509 | case 2: |
0dfbf9d7 | 1510 | if (x->array[1]) |
c6fb90c8 | 1511 | return 0; |
1a0670f3 | 1512 | /* Fall through. */ |
c6fb90c8 | 1513 | case 1: |
0dfbf9d7 | 1514 | return !x->array[0]; |
c6fb90c8 L |
1515 | default: |
1516 | abort (); | |
1517 | } | |
40fb9820 L |
1518 | } |
1519 | ||
c6fb90c8 | 1520 | static INLINE void |
0dfbf9d7 | 1521 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1522 | { |
0dfbf9d7 | 1523 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1524 | { |
1525 | case 3: | |
0dfbf9d7 | 1526 | x->array[2] = v; |
1a0670f3 | 1527 | /* Fall through. */ |
c6fb90c8 | 1528 | case 2: |
0dfbf9d7 | 1529 | x->array[1] = v; |
1a0670f3 | 1530 | /* Fall through. */ |
c6fb90c8 | 1531 | case 1: |
0dfbf9d7 | 1532 | x->array[0] = v; |
1a0670f3 | 1533 | /* Fall through. */ |
c6fb90c8 L |
1534 | break; |
1535 | default: | |
1536 | abort (); | |
1537 | } | |
1538 | } | |
40fb9820 | 1539 | |
c6fb90c8 | 1540 | static INLINE int |
0dfbf9d7 L |
1541 | operand_type_equal (const union i386_operand_type *x, |
1542 | const union i386_operand_type *y) | |
c6fb90c8 | 1543 | { |
0dfbf9d7 | 1544 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1545 | { |
1546 | case 3: | |
0dfbf9d7 | 1547 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1548 | return 0; |
1a0670f3 | 1549 | /* Fall through. */ |
c6fb90c8 | 1550 | case 2: |
0dfbf9d7 | 1551 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1552 | return 0; |
1a0670f3 | 1553 | /* Fall through. */ |
c6fb90c8 | 1554 | case 1: |
0dfbf9d7 | 1555 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1556 | break; |
1557 | default: | |
1558 | abort (); | |
1559 | } | |
1560 | } | |
40fb9820 | 1561 | |
0dfbf9d7 L |
1562 | static INLINE int |
1563 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1564 | { | |
1565 | switch (ARRAY_SIZE(x->array)) | |
1566 | { | |
53467f57 IT |
1567 | case 4: |
1568 | if (x->array[3]) | |
1569 | return 0; | |
1570 | /* Fall through. */ | |
0dfbf9d7 L |
1571 | case 3: |
1572 | if (x->array[2]) | |
1573 | return 0; | |
1a0670f3 | 1574 | /* Fall through. */ |
0dfbf9d7 L |
1575 | case 2: |
1576 | if (x->array[1]) | |
1577 | return 0; | |
1a0670f3 | 1578 | /* Fall through. */ |
0dfbf9d7 L |
1579 | case 1: |
1580 | return !x->array[0]; | |
1581 | default: | |
1582 | abort (); | |
1583 | } | |
1584 | } | |
1585 | ||
0dfbf9d7 L |
1586 | static INLINE int |
1587 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1588 | const union i386_cpu_flags *y) | |
1589 | { | |
1590 | switch (ARRAY_SIZE(x->array)) | |
1591 | { | |
53467f57 IT |
1592 | case 4: |
1593 | if (x->array[3] != y->array[3]) | |
1594 | return 0; | |
1595 | /* Fall through. */ | |
0dfbf9d7 L |
1596 | case 3: |
1597 | if (x->array[2] != y->array[2]) | |
1598 | return 0; | |
1a0670f3 | 1599 | /* Fall through. */ |
0dfbf9d7 L |
1600 | case 2: |
1601 | if (x->array[1] != y->array[1]) | |
1602 | return 0; | |
1a0670f3 | 1603 | /* Fall through. */ |
0dfbf9d7 L |
1604 | case 1: |
1605 | return x->array[0] == y->array[0]; | |
1606 | break; | |
1607 | default: | |
1608 | abort (); | |
1609 | } | |
1610 | } | |
c6fb90c8 L |
1611 | |
1612 | static INLINE int | |
1613 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1614 | { | |
1615 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1616 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1617 | } |
1618 | ||
c6fb90c8 L |
1619 | static INLINE i386_cpu_flags |
1620 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1621 | { |
c6fb90c8 L |
1622 | switch (ARRAY_SIZE (x.array)) |
1623 | { | |
53467f57 IT |
1624 | case 4: |
1625 | x.array [3] &= y.array [3]; | |
1626 | /* Fall through. */ | |
c6fb90c8 L |
1627 | case 3: |
1628 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1629 | /* Fall through. */ |
c6fb90c8 L |
1630 | case 2: |
1631 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1632 | /* Fall through. */ |
c6fb90c8 L |
1633 | case 1: |
1634 | x.array [0] &= y.array [0]; | |
1635 | break; | |
1636 | default: | |
1637 | abort (); | |
1638 | } | |
1639 | return x; | |
1640 | } | |
40fb9820 | 1641 | |
c6fb90c8 L |
1642 | static INLINE i386_cpu_flags |
1643 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1644 | { |
c6fb90c8 | 1645 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1646 | { |
53467f57 IT |
1647 | case 4: |
1648 | x.array [3] |= y.array [3]; | |
1649 | /* Fall through. */ | |
c6fb90c8 L |
1650 | case 3: |
1651 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1652 | /* Fall through. */ |
c6fb90c8 L |
1653 | case 2: |
1654 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1655 | /* Fall through. */ |
c6fb90c8 L |
1656 | case 1: |
1657 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1658 | break; |
1659 | default: | |
1660 | abort (); | |
1661 | } | |
40fb9820 L |
1662 | return x; |
1663 | } | |
1664 | ||
309d3373 JB |
1665 | static INLINE i386_cpu_flags |
1666 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1667 | { | |
1668 | switch (ARRAY_SIZE (x.array)) | |
1669 | { | |
53467f57 IT |
1670 | case 4: |
1671 | x.array [3] &= ~y.array [3]; | |
1672 | /* Fall through. */ | |
309d3373 JB |
1673 | case 3: |
1674 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1675 | /* Fall through. */ |
309d3373 JB |
1676 | case 2: |
1677 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1678 | /* Fall through. */ |
309d3373 JB |
1679 | case 1: |
1680 | x.array [0] &= ~y.array [0]; | |
1681 | break; | |
1682 | default: | |
1683 | abort (); | |
1684 | } | |
1685 | return x; | |
1686 | } | |
1687 | ||
c0f3af97 L |
1688 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1689 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1690 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1691 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1692 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1693 | |
a5ff0eb2 | 1694 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1695 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1696 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1697 | #define CPU_FLAGS_PERFECT_MATCH \ |
1698 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1699 | ||
1700 | /* Return CPU flags match bits. */ | |
3629bb00 | 1701 | |
40fb9820 | 1702 | static int |
d3ce72d0 | 1703 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1704 | { |
c0f3af97 L |
1705 | i386_cpu_flags x = t->cpu_flags; |
1706 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1707 | |
1708 | x.bitfield.cpu64 = 0; | |
1709 | x.bitfield.cpuno64 = 0; | |
1710 | ||
0dfbf9d7 | 1711 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1712 | { |
1713 | /* This instruction is available on all archs. */ | |
1714 | match |= CPU_FLAGS_32BIT_MATCH; | |
1715 | } | |
3629bb00 L |
1716 | else |
1717 | { | |
c0f3af97 | 1718 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1719 | i386_cpu_flags cpu = cpu_arch_flags; |
1720 | ||
3629bb00 | 1721 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1722 | if (!cpu_flags_all_zero (&cpu)) |
1723 | { | |
a5ff0eb2 L |
1724 | if (x.bitfield.cpuavx) |
1725 | { | |
ce2f5b3c | 1726 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1727 | if (cpu.bitfield.cpuavx) |
1728 | { | |
1729 | /* Check SSE2AVX. */ | |
1730 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1731 | { | |
1732 | match |= (CPU_FLAGS_ARCH_MATCH | |
1733 | | CPU_FLAGS_AVX_MATCH); | |
1734 | /* Check AES. */ | |
1735 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1736 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1737 | /* Check PCLMUL. */ |
1738 | if (!x.bitfield.cpupclmul | |
1739 | || cpu.bitfield.cpupclmul) | |
1740 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1741 | } |
1742 | } | |
1743 | else | |
1744 | match |= CPU_FLAGS_ARCH_MATCH; | |
1745 | } | |
73b090a9 L |
1746 | else if (x.bitfield.cpuavx512vl) |
1747 | { | |
1748 | /* Match AVX512VL. */ | |
1749 | if (cpu.bitfield.cpuavx512vl) | |
1750 | { | |
1751 | /* Need another match. */ | |
1752 | cpu.bitfield.cpuavx512vl = 0; | |
1753 | if (!cpu_flags_all_zero (&cpu)) | |
1754 | match |= CPU_FLAGS_32BIT_MATCH; | |
1755 | else | |
1756 | match |= CPU_FLAGS_ARCH_MATCH; | |
1757 | } | |
1758 | else | |
1759 | match |= CPU_FLAGS_ARCH_MATCH; | |
1760 | } | |
a5ff0eb2 | 1761 | else |
c0f3af97 L |
1762 | match |= CPU_FLAGS_32BIT_MATCH; |
1763 | } | |
3629bb00 | 1764 | } |
c0f3af97 | 1765 | return match; |
40fb9820 L |
1766 | } |
1767 | ||
c6fb90c8 L |
1768 | static INLINE i386_operand_type |
1769 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1770 | { |
c6fb90c8 L |
1771 | switch (ARRAY_SIZE (x.array)) |
1772 | { | |
1773 | case 3: | |
1774 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1775 | /* Fall through. */ |
c6fb90c8 L |
1776 | case 2: |
1777 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1778 | /* Fall through. */ |
c6fb90c8 L |
1779 | case 1: |
1780 | x.array [0] &= y.array [0]; | |
1781 | break; | |
1782 | default: | |
1783 | abort (); | |
1784 | } | |
1785 | return x; | |
40fb9820 L |
1786 | } |
1787 | ||
73053c1f JB |
1788 | static INLINE i386_operand_type |
1789 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1790 | { | |
1791 | switch (ARRAY_SIZE (x.array)) | |
1792 | { | |
1793 | case 3: | |
1794 | x.array [2] &= ~y.array [2]; | |
1795 | /* Fall through. */ | |
1796 | case 2: | |
1797 | x.array [1] &= ~y.array [1]; | |
1798 | /* Fall through. */ | |
1799 | case 1: | |
1800 | x.array [0] &= ~y.array [0]; | |
1801 | break; | |
1802 | default: | |
1803 | abort (); | |
1804 | } | |
1805 | return x; | |
1806 | } | |
1807 | ||
c6fb90c8 L |
1808 | static INLINE i386_operand_type |
1809 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1810 | { |
c6fb90c8 | 1811 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1812 | { |
c6fb90c8 L |
1813 | case 3: |
1814 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1815 | /* Fall through. */ |
c6fb90c8 L |
1816 | case 2: |
1817 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1818 | /* Fall through. */ |
c6fb90c8 L |
1819 | case 1: |
1820 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1821 | break; |
1822 | default: | |
1823 | abort (); | |
1824 | } | |
c6fb90c8 L |
1825 | return x; |
1826 | } | |
40fb9820 | 1827 | |
c6fb90c8 L |
1828 | static INLINE i386_operand_type |
1829 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1830 | { | |
1831 | switch (ARRAY_SIZE (x.array)) | |
1832 | { | |
1833 | case 3: | |
1834 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1835 | /* Fall through. */ |
c6fb90c8 L |
1836 | case 2: |
1837 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1838 | /* Fall through. */ |
c6fb90c8 L |
1839 | case 1: |
1840 | x.array [0] ^= y.array [0]; | |
1841 | break; | |
1842 | default: | |
1843 | abort (); | |
1844 | } | |
40fb9820 L |
1845 | return x; |
1846 | } | |
1847 | ||
1848 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1849 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1850 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1851 | static const i386_operand_type inoutportreg |
1852 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1853 | static const i386_operand_type reg16_inoutportreg |
1854 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1855 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1856 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1857 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1858 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1859 | static const i386_operand_type anydisp | |
1860 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1861 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1862 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1863 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1864 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1865 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1866 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1867 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1868 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1869 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1870 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1871 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1872 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1873 | |
1874 | enum operand_type | |
1875 | { | |
1876 | reg, | |
40fb9820 L |
1877 | imm, |
1878 | disp, | |
1879 | anymem | |
1880 | }; | |
1881 | ||
c6fb90c8 | 1882 | static INLINE int |
40fb9820 L |
1883 | operand_type_check (i386_operand_type t, enum operand_type c) |
1884 | { | |
1885 | switch (c) | |
1886 | { | |
1887 | case reg: | |
dc821c5f | 1888 | return t.bitfield.reg; |
40fb9820 | 1889 | |
40fb9820 L |
1890 | case imm: |
1891 | return (t.bitfield.imm8 | |
1892 | || t.bitfield.imm8s | |
1893 | || t.bitfield.imm16 | |
1894 | || t.bitfield.imm32 | |
1895 | || t.bitfield.imm32s | |
1896 | || t.bitfield.imm64); | |
1897 | ||
1898 | case disp: | |
1899 | return (t.bitfield.disp8 | |
1900 | || t.bitfield.disp16 | |
1901 | || t.bitfield.disp32 | |
1902 | || t.bitfield.disp32s | |
1903 | || t.bitfield.disp64); | |
1904 | ||
1905 | case anymem: | |
1906 | return (t.bitfield.disp8 | |
1907 | || t.bitfield.disp16 | |
1908 | || t.bitfield.disp32 | |
1909 | || t.bitfield.disp32s | |
1910 | || t.bitfield.disp64 | |
1911 | || t.bitfield.baseindex); | |
1912 | ||
1913 | default: | |
1914 | abort (); | |
1915 | } | |
2cfe26b6 AM |
1916 | |
1917 | return 0; | |
40fb9820 L |
1918 | } |
1919 | ||
ca0d63fe | 1920 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on |
5c07affc L |
1921 | operand J for instruction template T. */ |
1922 | ||
1923 | static INLINE int | |
d3ce72d0 | 1924 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1925 | { |
1926 | return !((i.types[j].bitfield.byte | |
1927 | && !t->operand_types[j].bitfield.byte) | |
1928 | || (i.types[j].bitfield.word | |
1929 | && !t->operand_types[j].bitfield.word) | |
1930 | || (i.types[j].bitfield.dword | |
1931 | && !t->operand_types[j].bitfield.dword) | |
1932 | || (i.types[j].bitfield.qword | |
ca0d63fe JB |
1933 | && !t->operand_types[j].bitfield.qword) |
1934 | || (i.types[j].bitfield.tbyte | |
1935 | && !t->operand_types[j].bitfield.tbyte)); | |
5c07affc L |
1936 | } |
1937 | ||
1b54b8d7 JB |
1938 | /* Return 1 if there is no conflict in SIMD register on |
1939 | operand J for instruction template T. */ | |
1940 | ||
1941 | static INLINE int | |
1942 | match_simd_size (const insn_template *t, unsigned int j) | |
1943 | { | |
1944 | return !((i.types[j].bitfield.xmmword | |
1945 | && !t->operand_types[j].bitfield.xmmword) | |
1946 | || (i.types[j].bitfield.ymmword | |
1947 | && !t->operand_types[j].bitfield.ymmword) | |
1948 | || (i.types[j].bitfield.zmmword | |
1949 | && !t->operand_types[j].bitfield.zmmword)); | |
1950 | } | |
1951 | ||
5c07affc L |
1952 | /* Return 1 if there is no conflict in any size on operand J for |
1953 | instruction template T. */ | |
1954 | ||
1955 | static INLINE int | |
d3ce72d0 | 1956 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1957 | { |
1958 | return (match_reg_size (t, j) | |
1959 | && !((i.types[j].bitfield.unspecified | |
af508cb9 | 1960 | && !i.broadcast |
5c07affc L |
1961 | && !t->operand_types[j].bitfield.unspecified) |
1962 | || (i.types[j].bitfield.fword | |
1963 | && !t->operand_types[j].bitfield.fword) | |
1b54b8d7 JB |
1964 | /* For scalar opcode templates to allow register and memory |
1965 | operands at the same time, some special casing is needed | |
1966 | here. */ | |
1967 | || ((t->operand_types[j].bitfield.regsimd | |
1968 | && !t->opcode_modifier.broadcast | |
1969 | && (t->operand_types[j].bitfield.dword | |
1970 | || t->operand_types[j].bitfield.qword)) | |
1971 | ? (i.types[j].bitfield.xmmword | |
1972 | || i.types[j].bitfield.ymmword | |
1973 | || i.types[j].bitfield.zmmword) | |
1974 | : !match_simd_size(t, j)))); | |
5c07affc L |
1975 | } |
1976 | ||
1977 | /* Return 1 if there is no size conflict on any operands for | |
1978 | instruction template T. */ | |
1979 | ||
1980 | static INLINE int | |
d3ce72d0 | 1981 | operand_size_match (const insn_template *t) |
5c07affc L |
1982 | { |
1983 | unsigned int j; | |
1984 | int match = 1; | |
1985 | ||
1986 | /* Don't check jump instructions. */ | |
1987 | if (t->opcode_modifier.jump | |
1988 | || t->opcode_modifier.jumpbyte | |
1989 | || t->opcode_modifier.jumpdword | |
1990 | || t->opcode_modifier.jumpintersegment) | |
1991 | return match; | |
1992 | ||
1993 | /* Check memory and accumulator operand size. */ | |
1994 | for (j = 0; j < i.operands; j++) | |
1995 | { | |
1b54b8d7 JB |
1996 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
1997 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
1998 | continue; |
1999 | ||
1b54b8d7 | 2000 | if (t->operand_types[j].bitfield.reg |
dc821c5f | 2001 | && !match_reg_size (t, j)) |
5c07affc L |
2002 | { |
2003 | match = 0; | |
2004 | break; | |
2005 | } | |
2006 | ||
1b54b8d7 JB |
2007 | if (t->operand_types[j].bitfield.regsimd |
2008 | && !match_simd_size (t, j)) | |
2009 | { | |
2010 | match = 0; | |
2011 | break; | |
2012 | } | |
2013 | ||
2014 | if (t->operand_types[j].bitfield.acc | |
2015 | && (!match_reg_size (t, j) || !match_simd_size (t, j))) | |
2016 | { | |
2017 | match = 0; | |
2018 | break; | |
2019 | } | |
2020 | ||
5c07affc L |
2021 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) |
2022 | { | |
2023 | match = 0; | |
2024 | break; | |
2025 | } | |
2026 | } | |
2027 | ||
891edac4 | 2028 | if (match) |
5c07affc | 2029 | return match; |
891edac4 L |
2030 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
2031 | { | |
2032 | mismatch: | |
86e026a4 | 2033 | i.error = operand_size_mismatch; |
891edac4 L |
2034 | return 0; |
2035 | } | |
5c07affc L |
2036 | |
2037 | /* Check reverse. */ | |
9c2799c2 | 2038 | gas_assert (i.operands == 2); |
5c07affc L |
2039 | |
2040 | match = 1; | |
2041 | for (j = 0; j < 2; j++) | |
2042 | { | |
dc821c5f JB |
2043 | if ((t->operand_types[j].bitfield.reg |
2044 | || t->operand_types[j].bitfield.acc) | |
5c07affc | 2045 | && !match_reg_size (t, j ? 0 : 1)) |
891edac4 | 2046 | goto mismatch; |
5c07affc L |
2047 | |
2048 | if (i.types[j].bitfield.mem | |
2049 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 2050 | goto mismatch; |
5c07affc L |
2051 | } |
2052 | ||
2053 | return match; | |
2054 | } | |
2055 | ||
c6fb90c8 | 2056 | static INLINE int |
40fb9820 L |
2057 | operand_type_match (i386_operand_type overlap, |
2058 | i386_operand_type given) | |
2059 | { | |
2060 | i386_operand_type temp = overlap; | |
2061 | ||
2062 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2063 | temp.bitfield.unspecified = 0; |
5c07affc L |
2064 | temp.bitfield.byte = 0; |
2065 | temp.bitfield.word = 0; | |
2066 | temp.bitfield.dword = 0; | |
2067 | temp.bitfield.fword = 0; | |
2068 | temp.bitfield.qword = 0; | |
2069 | temp.bitfield.tbyte = 0; | |
2070 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2071 | temp.bitfield.ymmword = 0; |
43234a1e | 2072 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2073 | if (operand_type_all_zero (&temp)) |
891edac4 | 2074 | goto mismatch; |
40fb9820 | 2075 | |
891edac4 L |
2076 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2077 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2078 | return 1; | |
2079 | ||
2080 | mismatch: | |
a65babc9 | 2081 | i.error = operand_type_mismatch; |
891edac4 | 2082 | return 0; |
40fb9820 L |
2083 | } |
2084 | ||
7d5e4556 | 2085 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2086 | unless the expected operand type register overlap is null. |
2087 | Memory operand size of certain SIMD instructions is also being checked | |
2088 | here. */ | |
40fb9820 | 2089 | |
c6fb90c8 | 2090 | static INLINE int |
dc821c5f | 2091 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2092 | i386_operand_type t0, |
40fb9820 L |
2093 | i386_operand_type g1, |
2094 | i386_operand_type t1) | |
2095 | { | |
10c17abd JB |
2096 | if (!g0.bitfield.reg |
2097 | && !g0.bitfield.regsimd | |
2098 | && (!operand_type_check (g0, anymem) | |
2099 | || g0.bitfield.unspecified | |
2100 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2101 | return 1; |
2102 | ||
10c17abd JB |
2103 | if (!g1.bitfield.reg |
2104 | && !g1.bitfield.regsimd | |
2105 | && (!operand_type_check (g1, anymem) | |
2106 | || g1.bitfield.unspecified | |
2107 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2108 | return 1; |
2109 | ||
dc821c5f JB |
2110 | if (g0.bitfield.byte == g1.bitfield.byte |
2111 | && g0.bitfield.word == g1.bitfield.word | |
2112 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2113 | && g0.bitfield.qword == g1.bitfield.qword |
2114 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2115 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2116 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2117 | return 1; |
2118 | ||
dc821c5f JB |
2119 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2120 | && !(t0.bitfield.word & t1.bitfield.word) | |
2121 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2122 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2123 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2124 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2125 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2126 | return 1; |
2127 | ||
a65babc9 | 2128 | i.error = register_type_mismatch; |
891edac4 L |
2129 | |
2130 | return 0; | |
40fb9820 L |
2131 | } |
2132 | ||
4c692bc7 JB |
2133 | static INLINE unsigned int |
2134 | register_number (const reg_entry *r) | |
2135 | { | |
2136 | unsigned int nr = r->reg_num; | |
2137 | ||
2138 | if (r->reg_flags & RegRex) | |
2139 | nr += 8; | |
2140 | ||
200cbe0f L |
2141 | if (r->reg_flags & RegVRex) |
2142 | nr += 16; | |
2143 | ||
4c692bc7 JB |
2144 | return nr; |
2145 | } | |
2146 | ||
252b5132 | 2147 | static INLINE unsigned int |
40fb9820 | 2148 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2149 | { |
b5014f7a | 2150 | if (t.bitfield.disp8) |
40fb9820 L |
2151 | return 1; |
2152 | else if (t.bitfield.disp16 | |
2153 | || t.bitfield.disp32 | |
2154 | || t.bitfield.disp32s) | |
2155 | return 2; | |
2156 | else | |
2157 | return 0; | |
252b5132 RH |
2158 | } |
2159 | ||
2160 | static INLINE int | |
65879393 | 2161 | fits_in_signed_byte (addressT num) |
252b5132 | 2162 | { |
65879393 | 2163 | return num + 0x80 <= 0xff; |
47926f60 | 2164 | } |
252b5132 RH |
2165 | |
2166 | static INLINE int | |
65879393 | 2167 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2168 | { |
65879393 | 2169 | return num <= 0xff; |
47926f60 | 2170 | } |
252b5132 RH |
2171 | |
2172 | static INLINE int | |
65879393 | 2173 | fits_in_unsigned_word (addressT num) |
252b5132 | 2174 | { |
65879393 | 2175 | return num <= 0xffff; |
47926f60 | 2176 | } |
252b5132 RH |
2177 | |
2178 | static INLINE int | |
65879393 | 2179 | fits_in_signed_word (addressT num) |
252b5132 | 2180 | { |
65879393 | 2181 | return num + 0x8000 <= 0xffff; |
47926f60 | 2182 | } |
2a962e6d | 2183 | |
3e73aa7c | 2184 | static INLINE int |
65879393 | 2185 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2186 | { |
2187 | #ifndef BFD64 | |
2188 | return 1; | |
2189 | #else | |
65879393 | 2190 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2191 | #endif |
2192 | } /* fits_in_signed_long() */ | |
2a962e6d | 2193 | |
3e73aa7c | 2194 | static INLINE int |
65879393 | 2195 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2196 | { |
2197 | #ifndef BFD64 | |
2198 | return 1; | |
2199 | #else | |
65879393 | 2200 | return num <= 0xffffffff; |
3e73aa7c JH |
2201 | #endif |
2202 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2203 | |
43234a1e | 2204 | static INLINE int |
b5014f7a | 2205 | fits_in_disp8 (offsetT num) |
43234a1e L |
2206 | { |
2207 | int shift = i.memshift; | |
2208 | unsigned int mask; | |
2209 | ||
2210 | if (shift == -1) | |
2211 | abort (); | |
2212 | ||
2213 | mask = (1 << shift) - 1; | |
2214 | ||
2215 | /* Return 0 if NUM isn't properly aligned. */ | |
2216 | if ((num & mask)) | |
2217 | return 0; | |
2218 | ||
2219 | /* Check if NUM will fit in 8bit after shift. */ | |
2220 | return fits_in_signed_byte (num >> shift); | |
2221 | } | |
2222 | ||
a683cc34 SP |
2223 | static INLINE int |
2224 | fits_in_imm4 (offsetT num) | |
2225 | { | |
2226 | return (num & 0xf) == num; | |
2227 | } | |
2228 | ||
40fb9820 | 2229 | static i386_operand_type |
e3bb37b5 | 2230 | smallest_imm_type (offsetT num) |
252b5132 | 2231 | { |
40fb9820 | 2232 | i386_operand_type t; |
7ab9ffdd | 2233 | |
0dfbf9d7 | 2234 | operand_type_set (&t, 0); |
40fb9820 L |
2235 | t.bitfield.imm64 = 1; |
2236 | ||
2237 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2238 | { |
2239 | /* This code is disabled on the 486 because all the Imm1 forms | |
2240 | in the opcode table are slower on the i486. They're the | |
2241 | versions with the implicitly specified single-position | |
2242 | displacement, which has another syntax if you really want to | |
2243 | use that form. */ | |
40fb9820 L |
2244 | t.bitfield.imm1 = 1; |
2245 | t.bitfield.imm8 = 1; | |
2246 | t.bitfield.imm8s = 1; | |
2247 | t.bitfield.imm16 = 1; | |
2248 | t.bitfield.imm32 = 1; | |
2249 | t.bitfield.imm32s = 1; | |
2250 | } | |
2251 | else if (fits_in_signed_byte (num)) | |
2252 | { | |
2253 | t.bitfield.imm8 = 1; | |
2254 | t.bitfield.imm8s = 1; | |
2255 | t.bitfield.imm16 = 1; | |
2256 | t.bitfield.imm32 = 1; | |
2257 | t.bitfield.imm32s = 1; | |
2258 | } | |
2259 | else if (fits_in_unsigned_byte (num)) | |
2260 | { | |
2261 | t.bitfield.imm8 = 1; | |
2262 | t.bitfield.imm16 = 1; | |
2263 | t.bitfield.imm32 = 1; | |
2264 | t.bitfield.imm32s = 1; | |
2265 | } | |
2266 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2267 | { | |
2268 | t.bitfield.imm16 = 1; | |
2269 | t.bitfield.imm32 = 1; | |
2270 | t.bitfield.imm32s = 1; | |
2271 | } | |
2272 | else if (fits_in_signed_long (num)) | |
2273 | { | |
2274 | t.bitfield.imm32 = 1; | |
2275 | t.bitfield.imm32s = 1; | |
2276 | } | |
2277 | else if (fits_in_unsigned_long (num)) | |
2278 | t.bitfield.imm32 = 1; | |
2279 | ||
2280 | return t; | |
47926f60 | 2281 | } |
252b5132 | 2282 | |
847f7ad4 | 2283 | static offsetT |
e3bb37b5 | 2284 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2285 | { |
508866be | 2286 | addressT mask; |
ba2adb93 | 2287 | |
847f7ad4 AM |
2288 | switch (size) |
2289 | { | |
508866be L |
2290 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2291 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2292 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2293 | #ifdef BFD64 |
2294 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2295 | #endif | |
47926f60 | 2296 | default: abort (); |
847f7ad4 AM |
2297 | } |
2298 | ||
9de868bf L |
2299 | #ifdef BFD64 |
2300 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2301 | if (flag_code != CODE_64BIT | |
2302 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2303 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2304 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2305 | #endif |
ba2adb93 | 2306 | |
47926f60 | 2307 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2308 | { |
2309 | char buf1[40], buf2[40]; | |
2310 | ||
2311 | sprint_value (buf1, val); | |
2312 | sprint_value (buf2, val & mask); | |
2313 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2314 | } | |
2315 | return val & mask; | |
2316 | } | |
2317 | ||
c32fa91d L |
2318 | enum PREFIX_GROUP |
2319 | { | |
2320 | PREFIX_EXIST = 0, | |
2321 | PREFIX_LOCK, | |
2322 | PREFIX_REP, | |
04ef582a | 2323 | PREFIX_DS, |
c32fa91d L |
2324 | PREFIX_OTHER |
2325 | }; | |
2326 | ||
2327 | /* Returns | |
2328 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2329 | same class already exists. | |
2330 | b. PREFIX_LOCK if lock prefix is added. | |
2331 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2332 | d. PREFIX_DS if ds prefix is added. |
2333 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2334 | */ |
2335 | ||
2336 | static enum PREFIX_GROUP | |
e3bb37b5 | 2337 | add_prefix (unsigned int prefix) |
252b5132 | 2338 | { |
c32fa91d | 2339 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2340 | unsigned int q; |
252b5132 | 2341 | |
29b0f896 AM |
2342 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2343 | && flag_code == CODE_64BIT) | |
b1905489 | 2344 | { |
161a04f6 L |
2345 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
2346 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
2347 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 2348 | ret = PREFIX_EXIST; |
b1905489 JB |
2349 | q = REX_PREFIX; |
2350 | } | |
3e73aa7c | 2351 | else |
b1905489 JB |
2352 | { |
2353 | switch (prefix) | |
2354 | { | |
2355 | default: | |
2356 | abort (); | |
2357 | ||
b1905489 | 2358 | case DS_PREFIX_OPCODE: |
04ef582a L |
2359 | ret = PREFIX_DS; |
2360 | /* Fall through. */ | |
2361 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2362 | case ES_PREFIX_OPCODE: |
2363 | case FS_PREFIX_OPCODE: | |
2364 | case GS_PREFIX_OPCODE: | |
2365 | case SS_PREFIX_OPCODE: | |
2366 | q = SEG_PREFIX; | |
2367 | break; | |
2368 | ||
2369 | case REPNE_PREFIX_OPCODE: | |
2370 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2371 | q = REP_PREFIX; |
2372 | ret = PREFIX_REP; | |
2373 | break; | |
2374 | ||
b1905489 | 2375 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2376 | q = LOCK_PREFIX; |
2377 | ret = PREFIX_LOCK; | |
b1905489 JB |
2378 | break; |
2379 | ||
2380 | case FWAIT_OPCODE: | |
2381 | q = WAIT_PREFIX; | |
2382 | break; | |
2383 | ||
2384 | case ADDR_PREFIX_OPCODE: | |
2385 | q = ADDR_PREFIX; | |
2386 | break; | |
2387 | ||
2388 | case DATA_PREFIX_OPCODE: | |
2389 | q = DATA_PREFIX; | |
2390 | break; | |
2391 | } | |
2392 | if (i.prefix[q] != 0) | |
c32fa91d | 2393 | ret = PREFIX_EXIST; |
b1905489 | 2394 | } |
252b5132 | 2395 | |
b1905489 | 2396 | if (ret) |
252b5132 | 2397 | { |
b1905489 JB |
2398 | if (!i.prefix[q]) |
2399 | ++i.prefixes; | |
2400 | i.prefix[q] |= prefix; | |
252b5132 | 2401 | } |
b1905489 JB |
2402 | else |
2403 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2404 | |
252b5132 RH |
2405 | return ret; |
2406 | } | |
2407 | ||
2408 | static void | |
78f12dd3 | 2409 | update_code_flag (int value, int check) |
eecb386c | 2410 | { |
78f12dd3 L |
2411 | PRINTF_LIKE ((*as_error)); |
2412 | ||
1e9cc1c2 | 2413 | flag_code = (enum flag_code) value; |
40fb9820 L |
2414 | if (flag_code == CODE_64BIT) |
2415 | { | |
2416 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2417 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2418 | } |
2419 | else | |
2420 | { | |
2421 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2422 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2423 | } |
2424 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2425 | { |
78f12dd3 L |
2426 | if (check) |
2427 | as_error = as_fatal; | |
2428 | else | |
2429 | as_error = as_bad; | |
2430 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2431 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2432 | } |
40fb9820 | 2433 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2434 | { |
78f12dd3 L |
2435 | if (check) |
2436 | as_error = as_fatal; | |
2437 | else | |
2438 | as_error = as_bad; | |
2439 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2440 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2441 | } |
eecb386c AM |
2442 | stackop_size = '\0'; |
2443 | } | |
2444 | ||
78f12dd3 L |
2445 | static void |
2446 | set_code_flag (int value) | |
2447 | { | |
2448 | update_code_flag (value, 0); | |
2449 | } | |
2450 | ||
eecb386c | 2451 | static void |
e3bb37b5 | 2452 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2453 | { |
1e9cc1c2 | 2454 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2455 | if (flag_code != CODE_16BIT) |
2456 | abort (); | |
2457 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2458 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2459 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2460 | } |
2461 | ||
2462 | static void | |
e3bb37b5 | 2463 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2464 | { |
2465 | /* Find out if register prefixing is specified. */ | |
2466 | int ask_naked_reg = 0; | |
2467 | ||
2468 | SKIP_WHITESPACE (); | |
29b0f896 | 2469 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2470 | { |
d02603dc NC |
2471 | char *string; |
2472 | int e = get_symbol_name (&string); | |
252b5132 | 2473 | |
47926f60 | 2474 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2475 | ask_naked_reg = 1; |
47926f60 | 2476 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2477 | ask_naked_reg = -1; |
2478 | else | |
d0b47220 | 2479 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2480 | (void) restore_line_pointer (e); |
252b5132 RH |
2481 | } |
2482 | demand_empty_rest_of_line (); | |
c3332e24 | 2483 | |
252b5132 RH |
2484 | intel_syntax = syntax_flag; |
2485 | ||
2486 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2487 | allow_naked_reg = (intel_syntax |
2488 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2489 | else |
2490 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2491 | |
ee86248c | 2492 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2493 | |
e4a3b5a4 | 2494 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2495 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2496 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2497 | } |
2498 | ||
1efbbeb4 L |
2499 | static void |
2500 | set_intel_mnemonic (int mnemonic_flag) | |
2501 | { | |
e1d4d893 | 2502 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2503 | } |
2504 | ||
db51cc60 L |
2505 | static void |
2506 | set_allow_index_reg (int flag) | |
2507 | { | |
2508 | allow_index_reg = flag; | |
2509 | } | |
2510 | ||
cb19c032 | 2511 | static void |
7bab8ab5 | 2512 | set_check (int what) |
cb19c032 | 2513 | { |
7bab8ab5 JB |
2514 | enum check_kind *kind; |
2515 | const char *str; | |
2516 | ||
2517 | if (what) | |
2518 | { | |
2519 | kind = &operand_check; | |
2520 | str = "operand"; | |
2521 | } | |
2522 | else | |
2523 | { | |
2524 | kind = &sse_check; | |
2525 | str = "sse"; | |
2526 | } | |
2527 | ||
cb19c032 L |
2528 | SKIP_WHITESPACE (); |
2529 | ||
2530 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2531 | { | |
d02603dc NC |
2532 | char *string; |
2533 | int e = get_symbol_name (&string); | |
cb19c032 L |
2534 | |
2535 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2536 | *kind = check_none; |
cb19c032 | 2537 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2538 | *kind = check_warning; |
cb19c032 | 2539 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2540 | *kind = check_error; |
cb19c032 | 2541 | else |
7bab8ab5 | 2542 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2543 | (void) restore_line_pointer (e); |
cb19c032 L |
2544 | } |
2545 | else | |
7bab8ab5 | 2546 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2547 | |
2548 | demand_empty_rest_of_line (); | |
2549 | } | |
2550 | ||
8a9036a4 L |
2551 | static void |
2552 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2553 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2554 | { |
2555 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2556 | static const char *arch; | |
2557 | ||
2558 | /* Intel LIOM is only supported on ELF. */ | |
2559 | if (!IS_ELF) | |
2560 | return; | |
2561 | ||
2562 | if (!arch) | |
2563 | { | |
2564 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2565 | use default_arch. */ | |
2566 | arch = cpu_arch_name; | |
2567 | if (!arch) | |
2568 | arch = default_arch; | |
2569 | } | |
2570 | ||
81486035 L |
2571 | /* If we are targeting Intel MCU, we must enable it. */ |
2572 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2573 | || new_flag.bitfield.cpuiamcu) | |
2574 | return; | |
2575 | ||
3632d14b | 2576 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2577 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2578 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2579 | return; |
76ba9986 | 2580 | |
7a9068fe L |
2581 | /* If we are targeting Intel K1OM, we must enable it. */ |
2582 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2583 | || new_flag.bitfield.cpuk1om) | |
2584 | return; | |
2585 | ||
8a9036a4 L |
2586 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2587 | #endif | |
2588 | } | |
2589 | ||
e413e4e9 | 2590 | static void |
e3bb37b5 | 2591 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2592 | { |
47926f60 | 2593 | SKIP_WHITESPACE (); |
e413e4e9 | 2594 | |
29b0f896 | 2595 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2596 | { |
d02603dc NC |
2597 | char *string; |
2598 | int e = get_symbol_name (&string); | |
91d6fa6a | 2599 | unsigned int j; |
40fb9820 | 2600 | i386_cpu_flags flags; |
e413e4e9 | 2601 | |
91d6fa6a | 2602 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2603 | { |
91d6fa6a | 2604 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2605 | { |
91d6fa6a | 2606 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2607 | |
5c6af06e JB |
2608 | if (*string != '.') |
2609 | { | |
91d6fa6a | 2610 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2611 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2612 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2613 | if (flag_code == CODE_64BIT) |
2614 | { | |
2615 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2616 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2617 | } | |
2618 | else | |
2619 | { | |
2620 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2621 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2622 | } | |
91d6fa6a NC |
2623 | cpu_arch_isa = cpu_arch[j].type; |
2624 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2625 | if (!cpu_arch_tune_set) |
2626 | { | |
2627 | cpu_arch_tune = cpu_arch_isa; | |
2628 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2629 | } | |
5c6af06e JB |
2630 | break; |
2631 | } | |
40fb9820 | 2632 | |
293f5f65 L |
2633 | flags = cpu_flags_or (cpu_arch_flags, |
2634 | cpu_arch[j].flags); | |
81486035 | 2635 | |
5b64d091 | 2636 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2637 | { |
6305a203 L |
2638 | if (cpu_sub_arch_name) |
2639 | { | |
2640 | char *name = cpu_sub_arch_name; | |
2641 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2642 | cpu_arch[j].name, |
1bf57e9f | 2643 | (const char *) NULL); |
6305a203 L |
2644 | free (name); |
2645 | } | |
2646 | else | |
91d6fa6a | 2647 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2648 | cpu_arch_flags = flags; |
a586129e | 2649 | cpu_arch_isa_flags = flags; |
5c6af06e | 2650 | } |
d02603dc | 2651 | (void) restore_line_pointer (e); |
5c6af06e JB |
2652 | demand_empty_rest_of_line (); |
2653 | return; | |
e413e4e9 AM |
2654 | } |
2655 | } | |
293f5f65 L |
2656 | |
2657 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2658 | { | |
33eaf5de | 2659 | /* Disable an ISA extension. */ |
293f5f65 L |
2660 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2661 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2662 | { | |
2663 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2664 | cpu_noarch[j].flags); | |
2665 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2666 | { | |
2667 | if (cpu_sub_arch_name) | |
2668 | { | |
2669 | char *name = cpu_sub_arch_name; | |
2670 | cpu_sub_arch_name = concat (name, string, | |
2671 | (const char *) NULL); | |
2672 | free (name); | |
2673 | } | |
2674 | else | |
2675 | cpu_sub_arch_name = xstrdup (string); | |
2676 | cpu_arch_flags = flags; | |
2677 | cpu_arch_isa_flags = flags; | |
2678 | } | |
2679 | (void) restore_line_pointer (e); | |
2680 | demand_empty_rest_of_line (); | |
2681 | return; | |
2682 | } | |
2683 | ||
2684 | j = ARRAY_SIZE (cpu_arch); | |
2685 | } | |
2686 | ||
91d6fa6a | 2687 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2688 | as_bad (_("no such architecture: `%s'"), string); |
2689 | ||
2690 | *input_line_pointer = e; | |
2691 | } | |
2692 | else | |
2693 | as_bad (_("missing cpu architecture")); | |
2694 | ||
fddf5b5b AM |
2695 | no_cond_jump_promotion = 0; |
2696 | if (*input_line_pointer == ',' | |
29b0f896 | 2697 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2698 | { |
d02603dc NC |
2699 | char *string; |
2700 | char e; | |
2701 | ||
2702 | ++input_line_pointer; | |
2703 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2704 | |
2705 | if (strcmp (string, "nojumps") == 0) | |
2706 | no_cond_jump_promotion = 1; | |
2707 | else if (strcmp (string, "jumps") == 0) | |
2708 | ; | |
2709 | else | |
2710 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2711 | ||
d02603dc | 2712 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2713 | } |
2714 | ||
e413e4e9 AM |
2715 | demand_empty_rest_of_line (); |
2716 | } | |
2717 | ||
8a9036a4 L |
2718 | enum bfd_architecture |
2719 | i386_arch (void) | |
2720 | { | |
3632d14b | 2721 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2722 | { |
2723 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2724 | || flag_code != CODE_64BIT) | |
2725 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2726 | return bfd_arch_l1om; | |
2727 | } | |
7a9068fe L |
2728 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2729 | { | |
2730 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2731 | || flag_code != CODE_64BIT) | |
2732 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2733 | return bfd_arch_k1om; | |
2734 | } | |
81486035 L |
2735 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2736 | { | |
2737 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2738 | || flag_code == CODE_64BIT) | |
2739 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2740 | return bfd_arch_iamcu; | |
2741 | } | |
8a9036a4 L |
2742 | else |
2743 | return bfd_arch_i386; | |
2744 | } | |
2745 | ||
b9d79e03 | 2746 | unsigned long |
7016a5d5 | 2747 | i386_mach (void) |
b9d79e03 | 2748 | { |
351f65ca | 2749 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2750 | { |
3632d14b | 2751 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2752 | { |
351f65ca L |
2753 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2754 | || default_arch[6] != '\0') | |
8a9036a4 L |
2755 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2756 | return bfd_mach_l1om; | |
2757 | } | |
7a9068fe L |
2758 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2759 | { | |
2760 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2761 | || default_arch[6] != '\0') | |
2762 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2763 | return bfd_mach_k1om; | |
2764 | } | |
351f65ca | 2765 | else if (default_arch[6] == '\0') |
8a9036a4 | 2766 | return bfd_mach_x86_64; |
351f65ca L |
2767 | else |
2768 | return bfd_mach_x64_32; | |
8a9036a4 | 2769 | } |
5197d474 L |
2770 | else if (!strcmp (default_arch, "i386") |
2771 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2772 | { |
2773 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2774 | { | |
2775 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2776 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2777 | return bfd_mach_i386_iamcu; | |
2778 | } | |
2779 | else | |
2780 | return bfd_mach_i386_i386; | |
2781 | } | |
b9d79e03 | 2782 | else |
2b5d6a91 | 2783 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2784 | } |
b9d79e03 | 2785 | \f |
252b5132 | 2786 | void |
7016a5d5 | 2787 | md_begin (void) |
252b5132 RH |
2788 | { |
2789 | const char *hash_err; | |
2790 | ||
86fa6981 L |
2791 | /* Support pseudo prefixes like {disp32}. */ |
2792 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2793 | ||
47926f60 | 2794 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2795 | op_hash = hash_new (); |
2796 | ||
2797 | { | |
d3ce72d0 | 2798 | const insn_template *optab; |
29b0f896 | 2799 | templates *core_optab; |
252b5132 | 2800 | |
47926f60 KH |
2801 | /* Setup for loop. */ |
2802 | optab = i386_optab; | |
add39d23 | 2803 | core_optab = XNEW (templates); |
252b5132 RH |
2804 | core_optab->start = optab; |
2805 | ||
2806 | while (1) | |
2807 | { | |
2808 | ++optab; | |
2809 | if (optab->name == NULL | |
2810 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2811 | { | |
2812 | /* different name --> ship out current template list; | |
47926f60 | 2813 | add to hash table; & begin anew. */ |
252b5132 RH |
2814 | core_optab->end = optab; |
2815 | hash_err = hash_insert (op_hash, | |
2816 | (optab - 1)->name, | |
5a49b8ac | 2817 | (void *) core_optab); |
252b5132 RH |
2818 | if (hash_err) |
2819 | { | |
b37df7c4 | 2820 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2821 | (optab - 1)->name, |
2822 | hash_err); | |
2823 | } | |
2824 | if (optab->name == NULL) | |
2825 | break; | |
add39d23 | 2826 | core_optab = XNEW (templates); |
252b5132 RH |
2827 | core_optab->start = optab; |
2828 | } | |
2829 | } | |
2830 | } | |
2831 | ||
47926f60 | 2832 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2833 | reg_hash = hash_new (); |
2834 | { | |
29b0f896 | 2835 | const reg_entry *regtab; |
c3fe08fa | 2836 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2837 | |
c3fe08fa | 2838 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2839 | { |
5a49b8ac | 2840 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2841 | if (hash_err) |
b37df7c4 | 2842 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2843 | regtab->reg_name, |
2844 | hash_err); | |
252b5132 RH |
2845 | } |
2846 | } | |
2847 | ||
47926f60 | 2848 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2849 | { |
29b0f896 AM |
2850 | int c; |
2851 | char *p; | |
252b5132 RH |
2852 | |
2853 | for (c = 0; c < 256; c++) | |
2854 | { | |
3882b010 | 2855 | if (ISDIGIT (c)) |
252b5132 RH |
2856 | { |
2857 | digit_chars[c] = c; | |
2858 | mnemonic_chars[c] = c; | |
2859 | register_chars[c] = c; | |
2860 | operand_chars[c] = c; | |
2861 | } | |
3882b010 | 2862 | else if (ISLOWER (c)) |
252b5132 RH |
2863 | { |
2864 | mnemonic_chars[c] = c; | |
2865 | register_chars[c] = c; | |
2866 | operand_chars[c] = c; | |
2867 | } | |
3882b010 | 2868 | else if (ISUPPER (c)) |
252b5132 | 2869 | { |
3882b010 | 2870 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2871 | register_chars[c] = mnemonic_chars[c]; |
2872 | operand_chars[c] = c; | |
2873 | } | |
43234a1e | 2874 | else if (c == '{' || c == '}') |
86fa6981 L |
2875 | { |
2876 | mnemonic_chars[c] = c; | |
2877 | operand_chars[c] = c; | |
2878 | } | |
252b5132 | 2879 | |
3882b010 | 2880 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2881 | identifier_chars[c] = c; |
2882 | else if (c >= 128) | |
2883 | { | |
2884 | identifier_chars[c] = c; | |
2885 | operand_chars[c] = c; | |
2886 | } | |
2887 | } | |
2888 | ||
2889 | #ifdef LEX_AT | |
2890 | identifier_chars['@'] = '@'; | |
32137342 NC |
2891 | #endif |
2892 | #ifdef LEX_QM | |
2893 | identifier_chars['?'] = '?'; | |
2894 | operand_chars['?'] = '?'; | |
252b5132 | 2895 | #endif |
252b5132 | 2896 | digit_chars['-'] = '-'; |
c0f3af97 | 2897 | mnemonic_chars['_'] = '_'; |
791fe849 | 2898 | mnemonic_chars['-'] = '-'; |
0003779b | 2899 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2900 | identifier_chars['_'] = '_'; |
2901 | identifier_chars['.'] = '.'; | |
2902 | ||
2903 | for (p = operand_special_chars; *p != '\0'; p++) | |
2904 | operand_chars[(unsigned char) *p] = *p; | |
2905 | } | |
2906 | ||
a4447b93 RH |
2907 | if (flag_code == CODE_64BIT) |
2908 | { | |
ca19b261 KT |
2909 | #if defined (OBJ_COFF) && defined (TE_PE) |
2910 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2911 | ? 32 : 16); | |
2912 | #else | |
a4447b93 | 2913 | x86_dwarf2_return_column = 16; |
ca19b261 | 2914 | #endif |
61ff971f | 2915 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2916 | } |
2917 | else | |
2918 | { | |
2919 | x86_dwarf2_return_column = 8; | |
2920 | x86_cie_data_alignment = -4; | |
2921 | } | |
252b5132 RH |
2922 | } |
2923 | ||
2924 | void | |
e3bb37b5 | 2925 | i386_print_statistics (FILE *file) |
252b5132 RH |
2926 | { |
2927 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2928 | hash_print_statistics (file, "i386 register", reg_hash); | |
2929 | } | |
2930 | \f | |
252b5132 RH |
2931 | #ifdef DEBUG386 |
2932 | ||
ce8a8b2f | 2933 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2934 | static void pte (insn_template *); |
40fb9820 | 2935 | static void pt (i386_operand_type); |
e3bb37b5 L |
2936 | static void pe (expressionS *); |
2937 | static void ps (symbolS *); | |
252b5132 RH |
2938 | |
2939 | static void | |
e3bb37b5 | 2940 | pi (char *line, i386_insn *x) |
252b5132 | 2941 | { |
09137c09 | 2942 | unsigned int j; |
252b5132 RH |
2943 | |
2944 | fprintf (stdout, "%s: template ", line); | |
2945 | pte (&x->tm); | |
09f131f2 JH |
2946 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2947 | x->base_reg ? x->base_reg->reg_name : "none", | |
2948 | x->index_reg ? x->index_reg->reg_name : "none", | |
2949 | x->log2_scale_factor); | |
2950 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2951 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2952 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2953 | x->sib.base, x->sib.index, x->sib.scale); | |
2954 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2955 | (x->rex & REX_W) != 0, |
2956 | (x->rex & REX_R) != 0, | |
2957 | (x->rex & REX_X) != 0, | |
2958 | (x->rex & REX_B) != 0); | |
09137c09 | 2959 | for (j = 0; j < x->operands; j++) |
252b5132 | 2960 | { |
09137c09 SP |
2961 | fprintf (stdout, " #%d: ", j + 1); |
2962 | pt (x->types[j]); | |
252b5132 | 2963 | fprintf (stdout, "\n"); |
dc821c5f | 2964 | if (x->types[j].bitfield.reg |
09137c09 | 2965 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 2966 | || x->types[j].bitfield.regsimd |
09137c09 SP |
2967 | || x->types[j].bitfield.sreg2 |
2968 | || x->types[j].bitfield.sreg3 | |
2969 | || x->types[j].bitfield.control | |
2970 | || x->types[j].bitfield.debug | |
2971 | || x->types[j].bitfield.test) | |
2972 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2973 | if (operand_type_check (x->types[j], imm)) | |
2974 | pe (x->op[j].imms); | |
2975 | if (operand_type_check (x->types[j], disp)) | |
2976 | pe (x->op[j].disps); | |
252b5132 RH |
2977 | } |
2978 | } | |
2979 | ||
2980 | static void | |
d3ce72d0 | 2981 | pte (insn_template *t) |
252b5132 | 2982 | { |
09137c09 | 2983 | unsigned int j; |
252b5132 | 2984 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2985 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2986 | if (t->extension_opcode != None) |
2987 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2988 | if (t->opcode_modifier.d) |
252b5132 | 2989 | fprintf (stdout, "D"); |
40fb9820 | 2990 | if (t->opcode_modifier.w) |
252b5132 RH |
2991 | fprintf (stdout, "W"); |
2992 | fprintf (stdout, "\n"); | |
09137c09 | 2993 | for (j = 0; j < t->operands; j++) |
252b5132 | 2994 | { |
09137c09 SP |
2995 | fprintf (stdout, " #%d type ", j + 1); |
2996 | pt (t->operand_types[j]); | |
252b5132 RH |
2997 | fprintf (stdout, "\n"); |
2998 | } | |
2999 | } | |
3000 | ||
3001 | static void | |
e3bb37b5 | 3002 | pe (expressionS *e) |
252b5132 | 3003 | { |
24eab124 | 3004 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3005 | fprintf (stdout, " add_number %ld (%lx)\n", |
3006 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3007 | if (e->X_add_symbol) |
3008 | { | |
3009 | fprintf (stdout, " add_symbol "); | |
3010 | ps (e->X_add_symbol); | |
3011 | fprintf (stdout, "\n"); | |
3012 | } | |
3013 | if (e->X_op_symbol) | |
3014 | { | |
3015 | fprintf (stdout, " op_symbol "); | |
3016 | ps (e->X_op_symbol); | |
3017 | fprintf (stdout, "\n"); | |
3018 | } | |
3019 | } | |
3020 | ||
3021 | static void | |
e3bb37b5 | 3022 | ps (symbolS *s) |
252b5132 RH |
3023 | { |
3024 | fprintf (stdout, "%s type %s%s", | |
3025 | S_GET_NAME (s), | |
3026 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3027 | segment_name (S_GET_SEGMENT (s))); | |
3028 | } | |
3029 | ||
7b81dfbb | 3030 | static struct type_name |
252b5132 | 3031 | { |
40fb9820 L |
3032 | i386_operand_type mask; |
3033 | const char *name; | |
252b5132 | 3034 | } |
7b81dfbb | 3035 | const type_names[] = |
252b5132 | 3036 | { |
40fb9820 L |
3037 | { OPERAND_TYPE_REG8, "r8" }, |
3038 | { OPERAND_TYPE_REG16, "r16" }, | |
3039 | { OPERAND_TYPE_REG32, "r32" }, | |
3040 | { OPERAND_TYPE_REG64, "r64" }, | |
3041 | { OPERAND_TYPE_IMM8, "i8" }, | |
3042 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3043 | { OPERAND_TYPE_IMM16, "i16" }, | |
3044 | { OPERAND_TYPE_IMM32, "i32" }, | |
3045 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3046 | { OPERAND_TYPE_IMM64, "i64" }, | |
3047 | { OPERAND_TYPE_IMM1, "i1" }, | |
3048 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3049 | { OPERAND_TYPE_DISP8, "d8" }, | |
3050 | { OPERAND_TYPE_DISP16, "d16" }, | |
3051 | { OPERAND_TYPE_DISP32, "d32" }, | |
3052 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3053 | { OPERAND_TYPE_DISP64, "d64" }, | |
3054 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3055 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3056 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3057 | { OPERAND_TYPE_TEST, "test reg" }, | |
3058 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3059 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3060 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3061 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3062 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
3063 | { OPERAND_TYPE_ACC, "Acc" }, | |
3064 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
3065 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3066 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3067 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3068 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3069 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3070 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3071 | }; |
3072 | ||
3073 | static void | |
40fb9820 | 3074 | pt (i386_operand_type t) |
252b5132 | 3075 | { |
40fb9820 | 3076 | unsigned int j; |
c6fb90c8 | 3077 | i386_operand_type a; |
252b5132 | 3078 | |
40fb9820 | 3079 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3080 | { |
3081 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 3082 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
3083 | fprintf (stdout, "%s, ", type_names[j].name); |
3084 | } | |
252b5132 RH |
3085 | fflush (stdout); |
3086 | } | |
3087 | ||
3088 | #endif /* DEBUG386 */ | |
3089 | \f | |
252b5132 | 3090 | static bfd_reloc_code_real_type |
3956db08 | 3091 | reloc (unsigned int size, |
64e74474 AM |
3092 | int pcrel, |
3093 | int sign, | |
3094 | bfd_reloc_code_real_type other) | |
252b5132 | 3095 | { |
47926f60 | 3096 | if (other != NO_RELOC) |
3956db08 | 3097 | { |
91d6fa6a | 3098 | reloc_howto_type *rel; |
3956db08 JB |
3099 | |
3100 | if (size == 8) | |
3101 | switch (other) | |
3102 | { | |
64e74474 AM |
3103 | case BFD_RELOC_X86_64_GOT32: |
3104 | return BFD_RELOC_X86_64_GOT64; | |
3105 | break; | |
553d1284 L |
3106 | case BFD_RELOC_X86_64_GOTPLT64: |
3107 | return BFD_RELOC_X86_64_GOTPLT64; | |
3108 | break; | |
64e74474 AM |
3109 | case BFD_RELOC_X86_64_PLTOFF64: |
3110 | return BFD_RELOC_X86_64_PLTOFF64; | |
3111 | break; | |
3112 | case BFD_RELOC_X86_64_GOTPC32: | |
3113 | other = BFD_RELOC_X86_64_GOTPC64; | |
3114 | break; | |
3115 | case BFD_RELOC_X86_64_GOTPCREL: | |
3116 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3117 | break; | |
3118 | case BFD_RELOC_X86_64_TPOFF32: | |
3119 | other = BFD_RELOC_X86_64_TPOFF64; | |
3120 | break; | |
3121 | case BFD_RELOC_X86_64_DTPOFF32: | |
3122 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3123 | break; | |
3124 | default: | |
3125 | break; | |
3956db08 | 3126 | } |
e05278af | 3127 | |
8ce3d284 | 3128 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3129 | if (other == BFD_RELOC_SIZE32) |
3130 | { | |
3131 | if (size == 8) | |
1ab668bf | 3132 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3133 | if (pcrel) |
1ab668bf AM |
3134 | { |
3135 | as_bad (_("there are no pc-relative size relocations")); | |
3136 | return NO_RELOC; | |
3137 | } | |
8fd4256d | 3138 | } |
8ce3d284 | 3139 | #endif |
8fd4256d | 3140 | |
e05278af | 3141 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3142 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3143 | sign = -1; |
3144 | ||
91d6fa6a NC |
3145 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3146 | if (!rel) | |
3956db08 | 3147 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3148 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3149 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3150 | bfd_get_reloc_size (rel), |
3956db08 | 3151 | size); |
91d6fa6a | 3152 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3153 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3154 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3155 | && !sign) |
91d6fa6a | 3156 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3157 | && sign > 0)) |
3956db08 JB |
3158 | as_bad (_("relocated field and relocation type differ in signedness")); |
3159 | else | |
3160 | return other; | |
3161 | return NO_RELOC; | |
3162 | } | |
252b5132 RH |
3163 | |
3164 | if (pcrel) | |
3165 | { | |
3e73aa7c | 3166 | if (!sign) |
3956db08 | 3167 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3168 | switch (size) |
3169 | { | |
3170 | case 1: return BFD_RELOC_8_PCREL; | |
3171 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3172 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3173 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3174 | } |
3956db08 | 3175 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3176 | } |
3177 | else | |
3178 | { | |
3956db08 | 3179 | if (sign > 0) |
e5cb08ac | 3180 | switch (size) |
3e73aa7c JH |
3181 | { |
3182 | case 4: return BFD_RELOC_X86_64_32S; | |
3183 | } | |
3184 | else | |
3185 | switch (size) | |
3186 | { | |
3187 | case 1: return BFD_RELOC_8; | |
3188 | case 2: return BFD_RELOC_16; | |
3189 | case 4: return BFD_RELOC_32; | |
3190 | case 8: return BFD_RELOC_64; | |
3191 | } | |
3956db08 JB |
3192 | as_bad (_("cannot do %s %u byte relocation"), |
3193 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3194 | } |
3195 | ||
0cc9e1d3 | 3196 | return NO_RELOC; |
252b5132 RH |
3197 | } |
3198 | ||
47926f60 KH |
3199 | /* Here we decide which fixups can be adjusted to make them relative to |
3200 | the beginning of the section instead of the symbol. Basically we need | |
3201 | to make sure that the dynamic relocations are done correctly, so in | |
3202 | some cases we force the original symbol to be used. */ | |
3203 | ||
252b5132 | 3204 | int |
e3bb37b5 | 3205 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3206 | { |
6d249963 | 3207 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3208 | if (!IS_ELF) |
31312f95 AM |
3209 | return 1; |
3210 | ||
a161fe53 AM |
3211 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3212 | mode. */ | |
3213 | if (use_rela_relocations | |
3214 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3215 | && fixP->fx_pcrel) | |
252b5132 | 3216 | return 0; |
31312f95 | 3217 | |
8d01d9a9 AJ |
3218 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3219 | and changed later by validate_fix. */ | |
3220 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3221 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3222 | return 0; | |
3223 | ||
8fd4256d L |
3224 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3225 | for size relocations. */ | |
3226 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3227 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3228 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3229 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3230 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3231 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3232 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3233 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3234 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3235 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3236 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3237 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3238 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3239 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3240 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3241 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3242 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3243 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3244 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3245 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3246 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3247 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3248 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3249 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3250 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3251 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3252 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3253 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3254 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3255 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3256 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3257 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3258 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3259 | return 0; | |
31312f95 | 3260 | #endif |
252b5132 RH |
3261 | return 1; |
3262 | } | |
252b5132 | 3263 | |
b4cac588 | 3264 | static int |
e3bb37b5 | 3265 | intel_float_operand (const char *mnemonic) |
252b5132 | 3266 | { |
9306ca4a JB |
3267 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3268 | operands, hence the code here is free to improperly handle opcodes that | |
3269 | have no operands (for better performance and smaller code). */ | |
3270 | ||
3271 | if (mnemonic[0] != 'f') | |
3272 | return 0; /* non-math */ | |
3273 | ||
3274 | switch (mnemonic[1]) | |
3275 | { | |
3276 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3277 | the fs segment override prefix not currently handled because no | |
3278 | call path can make opcodes without operands get here */ | |
3279 | case 'i': | |
3280 | return 2 /* integer op */; | |
3281 | case 'l': | |
3282 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3283 | return 3; /* fldcw/fldenv */ | |
3284 | break; | |
3285 | case 'n': | |
3286 | if (mnemonic[2] != 'o' /* fnop */) | |
3287 | return 3; /* non-waiting control op */ | |
3288 | break; | |
3289 | case 'r': | |
3290 | if (mnemonic[2] == 's') | |
3291 | return 3; /* frstor/frstpm */ | |
3292 | break; | |
3293 | case 's': | |
3294 | if (mnemonic[2] == 'a') | |
3295 | return 3; /* fsave */ | |
3296 | if (mnemonic[2] == 't') | |
3297 | { | |
3298 | switch (mnemonic[3]) | |
3299 | { | |
3300 | case 'c': /* fstcw */ | |
3301 | case 'd': /* fstdw */ | |
3302 | case 'e': /* fstenv */ | |
3303 | case 's': /* fsts[gw] */ | |
3304 | return 3; | |
3305 | } | |
3306 | } | |
3307 | break; | |
3308 | case 'x': | |
3309 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3310 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3311 | break; | |
3312 | } | |
252b5132 | 3313 | |
9306ca4a | 3314 | return 1; |
252b5132 RH |
3315 | } |
3316 | ||
c0f3af97 L |
3317 | /* Build the VEX prefix. */ |
3318 | ||
3319 | static void | |
d3ce72d0 | 3320 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3321 | { |
3322 | unsigned int register_specifier; | |
3323 | unsigned int implied_prefix; | |
3324 | unsigned int vector_length; | |
3325 | ||
3326 | /* Check register specifier. */ | |
3327 | if (i.vex.register_specifier) | |
43234a1e L |
3328 | { |
3329 | register_specifier = | |
3330 | ~register_number (i.vex.register_specifier) & 0xf; | |
3331 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3332 | } | |
c0f3af97 L |
3333 | else |
3334 | register_specifier = 0xf; | |
3335 | ||
33eaf5de | 3336 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 | 3337 | operand. */ |
86fa6981 L |
3338 | if (i.vec_encoding != vex_encoding_vex3 |
3339 | && i.dir_encoding == dir_encoding_default | |
fa99fab2 | 3340 | && i.operands == i.reg_operands |
7f399153 | 3341 | && i.tm.opcode_modifier.vexopcode == VEX0F |
86fa6981 | 3342 | && i.tm.opcode_modifier.load |
fa99fab2 L |
3343 | && i.rex == REX_B) |
3344 | { | |
3345 | unsigned int xchg = i.operands - 1; | |
3346 | union i386_op temp_op; | |
3347 | i386_operand_type temp_type; | |
3348 | ||
3349 | temp_type = i.types[xchg]; | |
3350 | i.types[xchg] = i.types[0]; | |
3351 | i.types[0] = temp_type; | |
3352 | temp_op = i.op[xchg]; | |
3353 | i.op[xchg] = i.op[0]; | |
3354 | i.op[0] = temp_op; | |
3355 | ||
9c2799c2 | 3356 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3357 | |
3358 | i.rex = REX_R; | |
3359 | xchg = i.rm.regmem; | |
3360 | i.rm.regmem = i.rm.reg; | |
3361 | i.rm.reg = xchg; | |
3362 | ||
3363 | /* Use the next insn. */ | |
3364 | i.tm = t[1]; | |
3365 | } | |
3366 | ||
539f890d L |
3367 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3368 | vector_length = avxscalar; | |
10c17abd JB |
3369 | else if (i.tm.opcode_modifier.vex == VEX256) |
3370 | vector_length = 1; | |
539f890d | 3371 | else |
10c17abd JB |
3372 | { |
3373 | unsigned int op; | |
3374 | ||
3375 | vector_length = 0; | |
3376 | for (op = 0; op < t->operands; ++op) | |
3377 | if (t->operand_types[op].bitfield.xmmword | |
3378 | && t->operand_types[op].bitfield.ymmword | |
3379 | && i.types[op].bitfield.ymmword) | |
3380 | { | |
3381 | vector_length = 1; | |
3382 | break; | |
3383 | } | |
3384 | } | |
c0f3af97 L |
3385 | |
3386 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3387 | { | |
3388 | case 0: | |
3389 | implied_prefix = 0; | |
3390 | break; | |
3391 | case DATA_PREFIX_OPCODE: | |
3392 | implied_prefix = 1; | |
3393 | break; | |
3394 | case REPE_PREFIX_OPCODE: | |
3395 | implied_prefix = 2; | |
3396 | break; | |
3397 | case REPNE_PREFIX_OPCODE: | |
3398 | implied_prefix = 3; | |
3399 | break; | |
3400 | default: | |
3401 | abort (); | |
3402 | } | |
3403 | ||
3404 | /* Use 2-byte VEX prefix if possible. */ | |
86fa6981 L |
3405 | if (i.vec_encoding != vex_encoding_vex3 |
3406 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
04251de0 | 3407 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3408 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3409 | { | |
3410 | /* 2-byte VEX prefix. */ | |
3411 | unsigned int r; | |
3412 | ||
3413 | i.vex.length = 2; | |
3414 | i.vex.bytes[0] = 0xc5; | |
3415 | ||
3416 | /* Check the REX.R bit. */ | |
3417 | r = (i.rex & REX_R) ? 0 : 1; | |
3418 | i.vex.bytes[1] = (r << 7 | |
3419 | | register_specifier << 3 | |
3420 | | vector_length << 2 | |
3421 | | implied_prefix); | |
3422 | } | |
3423 | else | |
3424 | { | |
3425 | /* 3-byte VEX prefix. */ | |
3426 | unsigned int m, w; | |
3427 | ||
f88c9eb0 | 3428 | i.vex.length = 3; |
f88c9eb0 | 3429 | |
7f399153 | 3430 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3431 | { |
7f399153 L |
3432 | case VEX0F: |
3433 | m = 0x1; | |
80de6e00 | 3434 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3435 | break; |
3436 | case VEX0F38: | |
3437 | m = 0x2; | |
80de6e00 | 3438 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3439 | break; |
3440 | case VEX0F3A: | |
3441 | m = 0x3; | |
80de6e00 | 3442 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3443 | break; |
3444 | case XOP08: | |
5dd85c99 SP |
3445 | m = 0x8; |
3446 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3447 | break; |
3448 | case XOP09: | |
f88c9eb0 SP |
3449 | m = 0x9; |
3450 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3451 | break; |
3452 | case XOP0A: | |
f88c9eb0 SP |
3453 | m = 0xa; |
3454 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3455 | break; |
3456 | default: | |
3457 | abort (); | |
f88c9eb0 | 3458 | } |
c0f3af97 | 3459 | |
c0f3af97 L |
3460 | /* The high 3 bits of the second VEX byte are 1's compliment |
3461 | of RXB bits from REX. */ | |
3462 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3463 | ||
3464 | /* Check the REX.W bit. */ | |
3465 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3466 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3467 | w = 1; | |
c0f3af97 L |
3468 | |
3469 | i.vex.bytes[2] = (w << 7 | |
3470 | | register_specifier << 3 | |
3471 | | vector_length << 2 | |
3472 | | implied_prefix); | |
3473 | } | |
3474 | } | |
3475 | ||
43234a1e L |
3476 | /* Build the EVEX prefix. */ |
3477 | ||
3478 | static void | |
3479 | build_evex_prefix (void) | |
3480 | { | |
3481 | unsigned int register_specifier; | |
3482 | unsigned int implied_prefix; | |
3483 | unsigned int m, w; | |
3484 | rex_byte vrex_used = 0; | |
3485 | ||
3486 | /* Check register specifier. */ | |
3487 | if (i.vex.register_specifier) | |
3488 | { | |
3489 | gas_assert ((i.vrex & REX_X) == 0); | |
3490 | ||
3491 | register_specifier = i.vex.register_specifier->reg_num; | |
3492 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3493 | register_specifier += 8; | |
3494 | /* The upper 16 registers are encoded in the fourth byte of the | |
3495 | EVEX prefix. */ | |
3496 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3497 | i.vex.bytes[3] = 0x8; | |
3498 | register_specifier = ~register_specifier & 0xf; | |
3499 | } | |
3500 | else | |
3501 | { | |
3502 | register_specifier = 0xf; | |
3503 | ||
3504 | /* Encode upper 16 vector index register in the fourth byte of | |
3505 | the EVEX prefix. */ | |
3506 | if (!(i.vrex & REX_X)) | |
3507 | i.vex.bytes[3] = 0x8; | |
3508 | else | |
3509 | vrex_used |= REX_X; | |
3510 | } | |
3511 | ||
3512 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3513 | { | |
3514 | case 0: | |
3515 | implied_prefix = 0; | |
3516 | break; | |
3517 | case DATA_PREFIX_OPCODE: | |
3518 | implied_prefix = 1; | |
3519 | break; | |
3520 | case REPE_PREFIX_OPCODE: | |
3521 | implied_prefix = 2; | |
3522 | break; | |
3523 | case REPNE_PREFIX_OPCODE: | |
3524 | implied_prefix = 3; | |
3525 | break; | |
3526 | default: | |
3527 | abort (); | |
3528 | } | |
3529 | ||
3530 | /* 4 byte EVEX prefix. */ | |
3531 | i.vex.length = 4; | |
3532 | i.vex.bytes[0] = 0x62; | |
3533 | ||
3534 | /* mmmm bits. */ | |
3535 | switch (i.tm.opcode_modifier.vexopcode) | |
3536 | { | |
3537 | case VEX0F: | |
3538 | m = 1; | |
3539 | break; | |
3540 | case VEX0F38: | |
3541 | m = 2; | |
3542 | break; | |
3543 | case VEX0F3A: | |
3544 | m = 3; | |
3545 | break; | |
3546 | default: | |
3547 | abort (); | |
3548 | break; | |
3549 | } | |
3550 | ||
3551 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3552 | bits from REX. */ | |
3553 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3554 | ||
3555 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3556 | REX_R bit in VREX. */ | |
3557 | if (!(i.vrex & REX_R)) | |
3558 | i.vex.bytes[1] |= 0x10; | |
3559 | else | |
3560 | vrex_used |= REX_R; | |
3561 | ||
3562 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3563 | { | |
3564 | /* When all operands are registers, the REX_X bit in REX is not | |
3565 | used. We reuse it to encode the upper 16 registers, which is | |
3566 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3567 | as 1's compliment. */ | |
3568 | if ((i.vrex & REX_B)) | |
3569 | { | |
3570 | vrex_used |= REX_B; | |
3571 | i.vex.bytes[1] &= ~0x40; | |
3572 | } | |
3573 | } | |
3574 | ||
3575 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3576 | i.vrex &= ~vrex_used; | |
3577 | gas_assert (i.vrex == 0); | |
3578 | ||
3579 | /* Check the REX.W bit. */ | |
3580 | w = (i.rex & REX_W) ? 1 : 0; | |
3581 | if (i.tm.opcode_modifier.vexw) | |
3582 | { | |
3583 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3584 | w = 1; | |
3585 | } | |
3586 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3587 | else if (!w) | |
3588 | { | |
3589 | if (evexwig == evexw1) | |
3590 | w = 1; | |
3591 | } | |
3592 | ||
3593 | /* Encode the U bit. */ | |
3594 | implied_prefix |= 0x4; | |
3595 | ||
3596 | /* The third byte of the EVEX prefix. */ | |
3597 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3598 | ||
3599 | /* The fourth byte of the EVEX prefix. */ | |
3600 | /* The zeroing-masking bit. */ | |
3601 | if (i.mask && i.mask->zeroing) | |
3602 | i.vex.bytes[3] |= 0x80; | |
3603 | ||
3604 | /* Don't always set the broadcast bit if there is no RC. */ | |
3605 | if (!i.rounding) | |
3606 | { | |
3607 | /* Encode the vector length. */ | |
3608 | unsigned int vec_length; | |
3609 | ||
3610 | switch (i.tm.opcode_modifier.evex) | |
3611 | { | |
3612 | case EVEXLIG: /* LL' is ignored */ | |
3613 | vec_length = evexlig << 5; | |
3614 | break; | |
3615 | case EVEX128: | |
3616 | vec_length = 0 << 5; | |
3617 | break; | |
3618 | case EVEX256: | |
3619 | vec_length = 1 << 5; | |
3620 | break; | |
3621 | case EVEX512: | |
3622 | vec_length = 2 << 5; | |
3623 | break; | |
3624 | default: | |
3625 | abort (); | |
3626 | break; | |
3627 | } | |
3628 | i.vex.bytes[3] |= vec_length; | |
3629 | /* Encode the broadcast bit. */ | |
3630 | if (i.broadcast) | |
3631 | i.vex.bytes[3] |= 0x10; | |
3632 | } | |
3633 | else | |
3634 | { | |
3635 | if (i.rounding->type != saeonly) | |
3636 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3637 | else | |
d3d3c6db | 3638 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3639 | } |
3640 | ||
3641 | if (i.mask && i.mask->mask) | |
3642 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3643 | } | |
3644 | ||
65da13b5 L |
3645 | static void |
3646 | process_immext (void) | |
3647 | { | |
3648 | expressionS *exp; | |
3649 | ||
4c692bc7 JB |
3650 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3651 | && i.operands > 0) | |
65da13b5 | 3652 | { |
4c692bc7 JB |
3653 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3654 | with an opcode suffix which is coded in the same place as an | |
3655 | 8-bit immediate field would be. | |
3656 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3657 | unsigned int x; |
3658 | ||
3659 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3660 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3661 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3662 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3663 | i.tm.name); | |
3664 | ||
3665 | i.operands = 0; | |
65da13b5 L |
3666 | } |
3667 | ||
9916071f AP |
3668 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3669 | { | |
3670 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3671 | suffix which is coded in the same place as an 8-bit immediate | |
3672 | field would be. | |
3673 | Here we check those operands and remove them afterwards. */ | |
3674 | unsigned int x; | |
3675 | ||
3676 | if (i.operands != 3) | |
3677 | abort(); | |
3678 | ||
3679 | for (x = 0; x < 2; x++) | |
3680 | if (register_number (i.op[x].regs) != x) | |
3681 | goto bad_register_operand; | |
3682 | ||
3683 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3684 | if (register_number (i.op[x].regs) | |
3685 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3686 | { | |
3687 | bad_register_operand: | |
3688 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3689 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3690 | i.tm.name); | |
3691 | } | |
3692 | ||
3693 | i.operands = 0; | |
3694 | } | |
3695 | ||
c0f3af97 | 3696 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3697 | which is coded in the same place as an 8-bit immediate field |
3698 | would be. Here we fake an 8-bit immediate operand from the | |
3699 | opcode suffix stored in tm.extension_opcode. | |
3700 | ||
c1e679ec | 3701 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3702 | 3 argument instructions. */ |
65da13b5 | 3703 | |
43234a1e | 3704 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3705 | && (i.operands <= 2 |
43234a1e L |
3706 | || ((i.tm.opcode_modifier.vex |
3707 | || i.tm.opcode_modifier.evex) | |
7ab9ffdd | 3708 | && i.operands <= 4))); |
65da13b5 L |
3709 | |
3710 | exp = &im_expressions[i.imm_operands++]; | |
3711 | i.op[i.operands].imms = exp; | |
3712 | i.types[i.operands] = imm8; | |
3713 | i.operands++; | |
3714 | exp->X_op = O_constant; | |
3715 | exp->X_add_number = i.tm.extension_opcode; | |
3716 | i.tm.extension_opcode = None; | |
3717 | } | |
3718 | ||
42164a71 L |
3719 | |
3720 | static int | |
3721 | check_hle (void) | |
3722 | { | |
3723 | switch (i.tm.opcode_modifier.hleprefixok) | |
3724 | { | |
3725 | default: | |
3726 | abort (); | |
82c2def5 | 3727 | case HLEPrefixNone: |
165de32a L |
3728 | as_bad (_("invalid instruction `%s' after `%s'"), |
3729 | i.tm.name, i.hle_prefix); | |
42164a71 | 3730 | return 0; |
82c2def5 | 3731 | case HLEPrefixLock: |
42164a71 L |
3732 | if (i.prefix[LOCK_PREFIX]) |
3733 | return 1; | |
165de32a | 3734 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3735 | return 0; |
82c2def5 | 3736 | case HLEPrefixAny: |
42164a71 | 3737 | return 1; |
82c2def5 | 3738 | case HLEPrefixRelease: |
42164a71 L |
3739 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3740 | { | |
3741 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3742 | i.tm.name); | |
3743 | return 0; | |
3744 | } | |
3745 | if (i.mem_operands == 0 | |
3746 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3747 | { | |
3748 | as_bad (_("memory destination needed for instruction `%s'" | |
3749 | " after `xrelease'"), i.tm.name); | |
3750 | return 0; | |
3751 | } | |
3752 | return 1; | |
3753 | } | |
3754 | } | |
3755 | ||
b6f8c7c4 L |
3756 | /* Try the shortest encoding by shortening operand size. */ |
3757 | ||
3758 | static void | |
3759 | optimize_encoding (void) | |
3760 | { | |
3761 | int j; | |
3762 | ||
3763 | if (optimize_for_space | |
3764 | && i.reg_operands == 1 | |
3765 | && i.imm_operands == 1 | |
3766 | && !i.types[1].bitfield.byte | |
3767 | && i.op[0].imms->X_op == O_constant | |
3768 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3769 | && ((i.tm.base_opcode == 0xa8 | |
3770 | && i.tm.extension_opcode == None) | |
3771 | || (i.tm.base_opcode == 0xf6 | |
3772 | && i.tm.extension_opcode == 0x0))) | |
3773 | { | |
3774 | /* Optimize: -Os: | |
3775 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3776 | */ | |
3777 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3778 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3779 | { | |
3780 | i.types[1].bitfield.byte = 1; | |
3781 | /* Ignore the suffix. */ | |
3782 | i.suffix = 0; | |
3783 | if (base_regnum >= 4 | |
3784 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3785 | { | |
3786 | /* Handle SP, BP, SI and DI registers. */ | |
3787 | if (i.types[1].bitfield.word) | |
3788 | j = 16; | |
3789 | else if (i.types[1].bitfield.dword) | |
3790 | j = 32; | |
3791 | else | |
3792 | j = 48; | |
3793 | i.op[1].regs -= j; | |
3794 | } | |
3795 | } | |
3796 | } | |
3797 | else if (flag_code == CODE_64BIT | |
3798 | && ((i.reg_operands == 1 | |
3799 | && i.imm_operands == 1 | |
3800 | && i.op[0].imms->X_op == O_constant | |
3801 | && ((i.tm.base_opcode == 0xb0 | |
3802 | && i.tm.extension_opcode == None | |
3803 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3804 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3805 | && (((i.tm.base_opcode == 0x24 | |
3806 | || i.tm.base_opcode == 0xa8) | |
3807 | && i.tm.extension_opcode == None) | |
3808 | || (i.tm.base_opcode == 0x80 | |
3809 | && i.tm.extension_opcode == 0x4) | |
3810 | || ((i.tm.base_opcode == 0xf6 | |
3811 | || i.tm.base_opcode == 0xc6) | |
3812 | && i.tm.extension_opcode == 0x0))))) | |
3813 | || (i.reg_operands == 2 | |
3814 | && i.op[0].regs == i.op[1].regs | |
3815 | && ((i.tm.base_opcode == 0x30 | |
3816 | || i.tm.base_opcode == 0x28) | |
3817 | && i.tm.extension_opcode == None))) | |
3818 | && i.types[1].bitfield.qword) | |
3819 | { | |
3820 | /* Optimize: -O: | |
3821 | andq $imm31, %r64 -> andl $imm31, %r32 | |
3822 | testq $imm31, %r64 -> testl $imm31, %r32 | |
3823 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3824 | subq %r64, %r64 -> subl %r32, %r32 | |
3825 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3826 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3827 | */ | |
3828 | i.tm.opcode_modifier.norex64 = 1; | |
3829 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) | |
3830 | { | |
3831 | /* Handle | |
3832 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3833 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3834 | */ | |
3835 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
3836 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
3837 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
3838 | i.types[0].bitfield.imm32 = 1; | |
3839 | i.types[0].bitfield.imm32s = 0; | |
3840 | i.types[0].bitfield.imm64 = 0; | |
3841 | i.types[1].bitfield.dword = 1; | |
3842 | i.types[1].bitfield.qword = 0; | |
3843 | if (i.tm.base_opcode == 0xc6) | |
3844 | { | |
3845 | /* Handle | |
3846 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3847 | */ | |
3848 | i.tm.base_opcode = 0xb0; | |
3849 | i.tm.extension_opcode = None; | |
3850 | i.tm.opcode_modifier.shortform = 1; | |
3851 | i.tm.opcode_modifier.modrm = 0; | |
3852 | } | |
3853 | } | |
3854 | } | |
3855 | else if (optimize > 1 | |
3856 | && i.reg_operands == 3 | |
3857 | && i.op[0].regs == i.op[1].regs | |
3858 | && !i.types[2].bitfield.xmmword | |
3859 | && (i.tm.opcode_modifier.vex | |
3860 | || (!i.mask | |
3861 | && !i.rounding | |
3862 | && i.tm.opcode_modifier.evex | |
3863 | && cpu_arch_flags.bitfield.cpuavx512vl)) | |
3864 | && ((i.tm.base_opcode == 0x55 | |
3865 | || i.tm.base_opcode == 0x6655 | |
3866 | || i.tm.base_opcode == 0x66df | |
3867 | || i.tm.base_opcode == 0x57 | |
3868 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
3869 | || i.tm.base_opcode == 0x66ef |
3870 | || i.tm.base_opcode == 0x66f8 | |
3871 | || i.tm.base_opcode == 0x66f9 | |
3872 | || i.tm.base_opcode == 0x66fa | |
3873 | || i.tm.base_opcode == 0x66fb) | |
b6f8c7c4 L |
3874 | && i.tm.extension_opcode == None)) |
3875 | { | |
3876 | /* Optimize: -O2: | |
8305403a L |
3877 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
3878 | vpsubq and vpsubw: | |
b6f8c7c4 L |
3879 | EVEX VOP %zmmM, %zmmM, %zmmN |
3880 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3881 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3882 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3883 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3884 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3885 | VEX VOP %ymmM, %ymmM, %ymmN | |
3886 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
3887 | VOP, one of vpandn and vpxor: | |
3888 | VEX VOP %ymmM, %ymmM, %ymmN | |
3889 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
3890 | VOP, one of vpandnd and vpandnq: | |
3891 | EVEX VOP %zmmM, %zmmM, %zmmN | |
3892 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
3893 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3894 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3895 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
3896 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3897 | VOP, one of vpxord and vpxorq: | |
3898 | EVEX VOP %zmmM, %zmmM, %zmmN | |
3899 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
3900 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3901 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3902 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
3903 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3904 | */ | |
3905 | if (i.tm.opcode_modifier.evex) | |
3906 | { | |
3907 | /* If only lower 16 vector registers are used, we can use | |
3908 | VEX encoding. */ | |
3909 | for (j = 0; j < 3; j++) | |
3910 | if (register_number (i.op[j].regs) > 15) | |
3911 | break; | |
3912 | ||
3913 | if (j < 3) | |
3914 | i.tm.opcode_modifier.evex = EVEX128; | |
3915 | else | |
3916 | { | |
3917 | i.tm.opcode_modifier.vex = VEX128; | |
3918 | i.tm.opcode_modifier.vexw = VEXW0; | |
3919 | i.tm.opcode_modifier.evex = 0; | |
3920 | } | |
3921 | } | |
3922 | else | |
3923 | i.tm.opcode_modifier.vex = VEX128; | |
3924 | ||
3925 | if (i.tm.opcode_modifier.vex) | |
3926 | for (j = 0; j < 3; j++) | |
3927 | { | |
3928 | i.types[j].bitfield.xmmword = 1; | |
3929 | i.types[j].bitfield.ymmword = 0; | |
3930 | } | |
3931 | } | |
3932 | } | |
3933 | ||
252b5132 RH |
3934 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3935 | machine dependent instruction. This function is supposed to emit | |
3936 | the frags/bytes it assembles to. */ | |
3937 | ||
3938 | void | |
65da13b5 | 3939 | md_assemble (char *line) |
252b5132 | 3940 | { |
40fb9820 | 3941 | unsigned int j; |
83b16ac6 | 3942 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 3943 | const insn_template *t; |
252b5132 | 3944 | |
47926f60 | 3945 | /* Initialize globals. */ |
252b5132 RH |
3946 | memset (&i, '\0', sizeof (i)); |
3947 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3948 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3949 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3950 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3951 | save_stack_p = save_stack; |
252b5132 RH |
3952 | |
3953 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3954 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3955 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3956 | |
29b0f896 AM |
3957 | line = parse_insn (line, mnemonic); |
3958 | if (line == NULL) | |
3959 | return; | |
83b16ac6 | 3960 | mnem_suffix = i.suffix; |
252b5132 | 3961 | |
29b0f896 | 3962 | line = parse_operands (line, mnemonic); |
ee86248c | 3963 | this_operand = -1; |
8325cc63 JB |
3964 | xfree (i.memop1_string); |
3965 | i.memop1_string = NULL; | |
29b0f896 AM |
3966 | if (line == NULL) |
3967 | return; | |
252b5132 | 3968 | |
29b0f896 AM |
3969 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3970 | operands at hand. */ | |
3971 | ||
3972 | /* All intel opcodes have reversed operands except for "bound" and | |
3973 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3974 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3975 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3976 | if (intel_syntax |
3977 | && i.operands > 1 | |
29b0f896 | 3978 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3979 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3980 | && !(operand_type_check (i.types[0], imm) |
3981 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3982 | swap_operands (); |
3983 | ||
ec56d5c0 JB |
3984 | /* The order of the immediates should be reversed |
3985 | for 2 immediates extrq and insertq instructions */ | |
3986 | if (i.imm_operands == 2 | |
3987 | && (strcmp (mnemonic, "extrq") == 0 | |
3988 | || strcmp (mnemonic, "insertq") == 0)) | |
3989 | swap_2_operands (0, 1); | |
3990 | ||
29b0f896 AM |
3991 | if (i.imm_operands) |
3992 | optimize_imm (); | |
3993 | ||
b300c311 L |
3994 | /* Don't optimize displacement for movabs since it only takes 64bit |
3995 | displacement. */ | |
3996 | if (i.disp_operands | |
a501d77e | 3997 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3998 | && (flag_code != CODE_64BIT |
3999 | || strcmp (mnemonic, "movabs") != 0)) | |
4000 | optimize_disp (); | |
29b0f896 AM |
4001 | |
4002 | /* Next, we find a template that matches the given insn, | |
4003 | making sure the overlap of the given operands types is consistent | |
4004 | with the template operand types. */ | |
252b5132 | 4005 | |
83b16ac6 | 4006 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4007 | return; |
252b5132 | 4008 | |
7bab8ab5 | 4009 | if (sse_check != check_none |
81f8a913 | 4010 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
4011 | && (i.tm.cpu_flags.bitfield.cpusse |
4012 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4013 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4014 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4015 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
4016 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
4017 | { | |
7bab8ab5 | 4018 | (sse_check == check_warning |
daf50ae7 L |
4019 | ? as_warn |
4020 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4021 | } | |
4022 | ||
321fd21e L |
4023 | /* Zap movzx and movsx suffix. The suffix has been set from |
4024 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4025 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4026 | the destination register to choose the suffix for encoding. */ | |
4027 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4028 | { |
321fd21e L |
4029 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4030 | there is no suffix, the default will be byte extension. */ | |
4031 | if (i.reg_operands != 2 | |
4032 | && !i.suffix | |
7ab9ffdd | 4033 | && intel_syntax) |
321fd21e L |
4034 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4035 | ||
4036 | i.suffix = 0; | |
cd61ebfe | 4037 | } |
24eab124 | 4038 | |
40fb9820 | 4039 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4040 | if (!add_prefix (FWAIT_OPCODE)) |
4041 | return; | |
252b5132 | 4042 | |
d5de92cf L |
4043 | /* Check if REP prefix is OK. */ |
4044 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4045 | { | |
4046 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4047 | i.tm.name, i.rep_prefix); | |
4048 | return; | |
4049 | } | |
4050 | ||
c1ba0266 L |
4051 | /* Check for lock without a lockable instruction. Destination operand |
4052 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4053 | if (i.prefix[LOCK_PREFIX] |
4054 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4055 | || i.mem_operands == 0 |
4056 | || (i.tm.base_opcode != 0x86 | |
4057 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
4058 | { |
4059 | as_bad (_("expecting lockable instruction after `lock'")); | |
4060 | return; | |
4061 | } | |
4062 | ||
42164a71 | 4063 | /* Check if HLE prefix is OK. */ |
165de32a | 4064 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4065 | return; |
4066 | ||
7e8b059b L |
4067 | /* Check BND prefix. */ |
4068 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4069 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4070 | ||
04ef582a | 4071 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4072 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4073 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4074 | |
327e8c42 JB |
4075 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4076 | { | |
4077 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4078 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4079 | else if (flag_code != CODE_16BIT | |
4080 | ? i.prefix[ADDR_PREFIX] | |
4081 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4082 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4083 | } | |
7e8b059b L |
4084 | |
4085 | /* Insert BND prefix. */ | |
4086 | if (add_bnd_prefix | |
4087 | && i.tm.opcode_modifier.bndprefixok | |
4088 | && !i.prefix[BND_PREFIX]) | |
4089 | add_prefix (BND_PREFIX_OPCODE); | |
4090 | ||
29b0f896 | 4091 | /* Check string instruction segment overrides. */ |
40fb9820 | 4092 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4093 | { |
4094 | if (!check_string ()) | |
5dd0794d | 4095 | return; |
fc0763e6 | 4096 | i.disp_operands = 0; |
29b0f896 | 4097 | } |
5dd0794d | 4098 | |
b6f8c7c4 L |
4099 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4100 | optimize_encoding (); | |
4101 | ||
29b0f896 AM |
4102 | if (!process_suffix ()) |
4103 | return; | |
e413e4e9 | 4104 | |
bc0844ae L |
4105 | /* Update operand types. */ |
4106 | for (j = 0; j < i.operands; j++) | |
4107 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4108 | ||
29b0f896 AM |
4109 | /* Make still unresolved immediate matches conform to size of immediate |
4110 | given in i.suffix. */ | |
4111 | if (!finalize_imm ()) | |
4112 | return; | |
252b5132 | 4113 | |
40fb9820 | 4114 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4115 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4116 | |
9afe6eb8 L |
4117 | /* We only need to check those implicit registers for instructions |
4118 | with 3 operands or less. */ | |
4119 | if (i.operands <= 3) | |
4120 | for (j = 0; j < i.operands; j++) | |
4121 | if (i.types[j].bitfield.inoutportreg | |
4122 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4123 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4124 | i.reg_operands--; |
40fb9820 | 4125 | |
c0f3af97 L |
4126 | /* ImmExt should be processed after SSE2AVX. */ |
4127 | if (!i.tm.opcode_modifier.sse2avx | |
4128 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4129 | process_immext (); |
252b5132 | 4130 | |
29b0f896 AM |
4131 | /* For insns with operands there are more diddles to do to the opcode. */ |
4132 | if (i.operands) | |
4133 | { | |
4134 | if (!process_operands ()) | |
4135 | return; | |
4136 | } | |
40fb9820 | 4137 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4138 | { |
4139 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4140 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4141 | } | |
252b5132 | 4142 | |
9e5e5283 L |
4143 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) |
4144 | { | |
4145 | if (flag_code == CODE_16BIT) | |
4146 | { | |
4147 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
4148 | i.tm.name); | |
4149 | return; | |
4150 | } | |
c0f3af97 | 4151 | |
9e5e5283 L |
4152 | if (i.tm.opcode_modifier.vex) |
4153 | build_vex_prefix (t); | |
4154 | else | |
4155 | build_evex_prefix (); | |
4156 | } | |
43234a1e | 4157 | |
5dd85c99 SP |
4158 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4159 | instructions may define INT_OPCODE as well, so avoid this corner | |
4160 | case for those instructions that use MODRM. */ | |
4161 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4162 | && !i.tm.opcode_modifier.modrm |
4163 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4164 | { |
4165 | i.tm.base_opcode = INT3_OPCODE; | |
4166 | i.imm_operands = 0; | |
4167 | } | |
252b5132 | 4168 | |
40fb9820 L |
4169 | if ((i.tm.opcode_modifier.jump |
4170 | || i.tm.opcode_modifier.jumpbyte | |
4171 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4172 | && i.op[0].disps->X_op == O_constant) |
4173 | { | |
4174 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4175 | the absolute address given by the constant. Since ix86 jumps and | |
4176 | calls are pc relative, we need to generate a reloc. */ | |
4177 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4178 | i.op[0].disps->X_op = O_symbol; | |
4179 | } | |
252b5132 | 4180 | |
40fb9820 | 4181 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4182 | i.rex |= REX_W; |
252b5132 | 4183 | |
29b0f896 AM |
4184 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4185 | instruction already has a prefix, we need to convert old | |
4186 | registers to new ones. */ | |
773f551c | 4187 | |
dc821c5f | 4188 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 4189 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 4190 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 4191 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
4192 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
4193 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4194 | && i.rex != 0)) |
4195 | { | |
4196 | int x; | |
726c5dcd | 4197 | |
29b0f896 AM |
4198 | i.rex |= REX_OPCODE; |
4199 | for (x = 0; x < 2; x++) | |
4200 | { | |
4201 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 4202 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 4203 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4204 | { |
29b0f896 AM |
4205 | /* In case it is "hi" register, give up. */ |
4206 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4207 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4208 | "instruction requiring REX prefix."), |
a540244d | 4209 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4210 | |
29b0f896 AM |
4211 | /* Otherwise it is equivalent to the extended register. |
4212 | Since the encoding doesn't change this is merely | |
4213 | cosmetic cleanup for debug output. */ | |
4214 | ||
4215 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4216 | } |
29b0f896 AM |
4217 | } |
4218 | } | |
773f551c | 4219 | |
6b6b6807 L |
4220 | if (i.rex == 0 && i.rex_encoding) |
4221 | { | |
4222 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4223 | that uses legacy register. If it is "hi" register, don't add | |
4224 | the REX_OPCODE byte. */ | |
4225 | int x; | |
4226 | for (x = 0; x < 2; x++) | |
4227 | if (i.types[x].bitfield.reg | |
4228 | && i.types[x].bitfield.byte | |
4229 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4230 | && i.op[x].regs->reg_num > 3) | |
4231 | { | |
4232 | i.rex_encoding = FALSE; | |
4233 | break; | |
4234 | } | |
4235 | ||
4236 | if (i.rex_encoding) | |
4237 | i.rex = REX_OPCODE; | |
4238 | } | |
4239 | ||
7ab9ffdd | 4240 | if (i.rex != 0) |
29b0f896 AM |
4241 | add_prefix (REX_OPCODE | i.rex); |
4242 | ||
4243 | /* We are ready to output the insn. */ | |
4244 | output_insn (); | |
4245 | } | |
4246 | ||
4247 | static char * | |
e3bb37b5 | 4248 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4249 | { |
4250 | char *l = line; | |
4251 | char *token_start = l; | |
4252 | char *mnem_p; | |
5c6af06e | 4253 | int supported; |
d3ce72d0 | 4254 | const insn_template *t; |
b6169b20 | 4255 | char *dot_p = NULL; |
29b0f896 | 4256 | |
29b0f896 AM |
4257 | while (1) |
4258 | { | |
4259 | mnem_p = mnemonic; | |
4260 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4261 | { | |
b6169b20 L |
4262 | if (*mnem_p == '.') |
4263 | dot_p = mnem_p; | |
29b0f896 AM |
4264 | mnem_p++; |
4265 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4266 | { |
29b0f896 AM |
4267 | as_bad (_("no such instruction: `%s'"), token_start); |
4268 | return NULL; | |
4269 | } | |
4270 | l++; | |
4271 | } | |
4272 | if (!is_space_char (*l) | |
4273 | && *l != END_OF_INSN | |
e44823cf JB |
4274 | && (intel_syntax |
4275 | || (*l != PREFIX_SEPARATOR | |
4276 | && *l != ','))) | |
29b0f896 AM |
4277 | { |
4278 | as_bad (_("invalid character %s in mnemonic"), | |
4279 | output_invalid (*l)); | |
4280 | return NULL; | |
4281 | } | |
4282 | if (token_start == l) | |
4283 | { | |
e44823cf | 4284 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4285 | as_bad (_("expecting prefix; got nothing")); |
4286 | else | |
4287 | as_bad (_("expecting mnemonic; got nothing")); | |
4288 | return NULL; | |
4289 | } | |
45288df1 | 4290 | |
29b0f896 | 4291 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4292 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4293 | |
29b0f896 AM |
4294 | if (*l != END_OF_INSN |
4295 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4296 | && current_templates | |
40fb9820 | 4297 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4298 | { |
c6fb90c8 | 4299 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4300 | { |
4301 | as_bad ((flag_code != CODE_64BIT | |
4302 | ? _("`%s' is only supported in 64-bit mode") | |
4303 | : _("`%s' is not supported in 64-bit mode")), | |
4304 | current_templates->start->name); | |
4305 | return NULL; | |
4306 | } | |
29b0f896 AM |
4307 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4308 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
4309 | if ((current_templates->start->opcode_modifier.size16 |
4310 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 4311 | && flag_code != CODE_64BIT |
40fb9820 | 4312 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
4313 | ^ (flag_code == CODE_16BIT))) |
4314 | { | |
4315 | as_bad (_("redundant %s prefix"), | |
4316 | current_templates->start->name); | |
4317 | return NULL; | |
45288df1 | 4318 | } |
86fa6981 | 4319 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4320 | { |
86fa6981 L |
4321 | /* Handle pseudo prefixes. */ |
4322 | switch (current_templates->start->base_opcode) | |
4323 | { | |
4324 | case 0x0: | |
4325 | /* {disp8} */ | |
4326 | i.disp_encoding = disp_encoding_8bit; | |
4327 | break; | |
4328 | case 0x1: | |
4329 | /* {disp32} */ | |
4330 | i.disp_encoding = disp_encoding_32bit; | |
4331 | break; | |
4332 | case 0x2: | |
4333 | /* {load} */ | |
4334 | i.dir_encoding = dir_encoding_load; | |
4335 | break; | |
4336 | case 0x3: | |
4337 | /* {store} */ | |
4338 | i.dir_encoding = dir_encoding_store; | |
4339 | break; | |
4340 | case 0x4: | |
4341 | /* {vex2} */ | |
4342 | i.vec_encoding = vex_encoding_vex2; | |
4343 | break; | |
4344 | case 0x5: | |
4345 | /* {vex3} */ | |
4346 | i.vec_encoding = vex_encoding_vex3; | |
4347 | break; | |
4348 | case 0x6: | |
4349 | /* {evex} */ | |
4350 | i.vec_encoding = vex_encoding_evex; | |
4351 | break; | |
6b6b6807 L |
4352 | case 0x7: |
4353 | /* {rex} */ | |
4354 | i.rex_encoding = TRUE; | |
4355 | break; | |
b6f8c7c4 L |
4356 | case 0x8: |
4357 | /* {nooptimize} */ | |
4358 | i.no_optimize = TRUE; | |
4359 | break; | |
86fa6981 L |
4360 | default: |
4361 | abort (); | |
4362 | } | |
4363 | } | |
4364 | else | |
4365 | { | |
4366 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4367 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4368 | { |
4e9ac44a L |
4369 | case PREFIX_EXIST: |
4370 | return NULL; | |
4371 | case PREFIX_DS: | |
d777820b | 4372 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4373 | i.notrack_prefix = current_templates->start->name; |
4374 | break; | |
4375 | case PREFIX_REP: | |
4376 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4377 | i.hle_prefix = current_templates->start->name; | |
4378 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4379 | i.bnd_prefix = current_templates->start->name; | |
4380 | else | |
4381 | i.rep_prefix = current_templates->start->name; | |
4382 | break; | |
4383 | default: | |
4384 | break; | |
86fa6981 | 4385 | } |
29b0f896 AM |
4386 | } |
4387 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4388 | token_start = ++l; | |
4389 | } | |
4390 | else | |
4391 | break; | |
4392 | } | |
45288df1 | 4393 | |
30a55f88 | 4394 | if (!current_templates) |
b6169b20 | 4395 | { |
f8a5c266 L |
4396 | /* Check if we should swap operand or force 32bit displacement in |
4397 | encoding. */ | |
30a55f88 | 4398 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
86fa6981 | 4399 | i.dir_encoding = dir_encoding_store; |
8d63c93e | 4400 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4401 | && dot_p[1] == 'd' |
4402 | && dot_p[2] == '8') | |
4403 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4404 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4405 | && dot_p[1] == 'd' |
4406 | && dot_p[2] == '3' | |
4407 | && dot_p[3] == '2') | |
a501d77e | 4408 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4409 | else |
4410 | goto check_suffix; | |
4411 | mnem_p = dot_p; | |
4412 | *dot_p = '\0'; | |
d3ce72d0 | 4413 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4414 | } |
4415 | ||
29b0f896 AM |
4416 | if (!current_templates) |
4417 | { | |
b6169b20 | 4418 | check_suffix: |
29b0f896 AM |
4419 | /* See if we can get a match by trimming off a suffix. */ |
4420 | switch (mnem_p[-1]) | |
4421 | { | |
4422 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
4423 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
4424 | i.suffix = SHORT_MNEM_SUFFIX; | |
4425 | else | |
1a0670f3 | 4426 | /* Fall through. */ |
29b0f896 AM |
4427 | case BYTE_MNEM_SUFFIX: |
4428 | case QWORD_MNEM_SUFFIX: | |
4429 | i.suffix = mnem_p[-1]; | |
4430 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4431 | current_templates = (const templates *) hash_find (op_hash, |
4432 | mnemonic); | |
29b0f896 AM |
4433 | break; |
4434 | case SHORT_MNEM_SUFFIX: | |
4435 | case LONG_MNEM_SUFFIX: | |
4436 | if (!intel_syntax) | |
4437 | { | |
4438 | i.suffix = mnem_p[-1]; | |
4439 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4440 | current_templates = (const templates *) hash_find (op_hash, |
4441 | mnemonic); | |
29b0f896 AM |
4442 | } |
4443 | break; | |
252b5132 | 4444 | |
29b0f896 AM |
4445 | /* Intel Syntax. */ |
4446 | case 'd': | |
4447 | if (intel_syntax) | |
4448 | { | |
9306ca4a | 4449 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
4450 | i.suffix = SHORT_MNEM_SUFFIX; |
4451 | else | |
4452 | i.suffix = LONG_MNEM_SUFFIX; | |
4453 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4454 | current_templates = (const templates *) hash_find (op_hash, |
4455 | mnemonic); | |
29b0f896 AM |
4456 | } |
4457 | break; | |
4458 | } | |
4459 | if (!current_templates) | |
4460 | { | |
4461 | as_bad (_("no such instruction: `%s'"), token_start); | |
4462 | return NULL; | |
4463 | } | |
4464 | } | |
252b5132 | 4465 | |
40fb9820 L |
4466 | if (current_templates->start->opcode_modifier.jump |
4467 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4468 | { |
4469 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4470 | predict taken and predict not taken respectively. | |
4471 | I'm not sure that branch hints actually do anything on loop | |
4472 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4473 | may work in the future and it doesn't hurt to accept them | |
4474 | now. */ | |
4475 | if (l[0] == ',' && l[1] == 'p') | |
4476 | { | |
4477 | if (l[2] == 't') | |
4478 | { | |
4479 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4480 | return NULL; | |
4481 | l += 3; | |
4482 | } | |
4483 | else if (l[2] == 'n') | |
4484 | { | |
4485 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4486 | return NULL; | |
4487 | l += 3; | |
4488 | } | |
4489 | } | |
4490 | } | |
4491 | /* Any other comma loses. */ | |
4492 | if (*l == ',') | |
4493 | { | |
4494 | as_bad (_("invalid character %s in mnemonic"), | |
4495 | output_invalid (*l)); | |
4496 | return NULL; | |
4497 | } | |
252b5132 | 4498 | |
29b0f896 | 4499 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4500 | supported = 0; |
4501 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4502 | { | |
c0f3af97 L |
4503 | supported |= cpu_flags_match (t); |
4504 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 4505 | goto skip; |
5c6af06e | 4506 | } |
3629bb00 | 4507 | |
c0f3af97 | 4508 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
4509 | { |
4510 | as_bad (flag_code == CODE_64BIT | |
4511 | ? _("`%s' is not supported in 64-bit mode") | |
4512 | : _("`%s' is only supported in 64-bit mode"), | |
4513 | current_templates->start->name); | |
4514 | return NULL; | |
4515 | } | |
c0f3af97 | 4516 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 4517 | { |
3629bb00 | 4518 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 4519 | current_templates->start->name, |
41aacd83 | 4520 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
4521 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
4522 | return NULL; | |
29b0f896 | 4523 | } |
3629bb00 L |
4524 | |
4525 | skip: | |
4526 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 4527 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
4528 | { |
4529 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
4530 | } | |
252b5132 | 4531 | |
29b0f896 AM |
4532 | return l; |
4533 | } | |
252b5132 | 4534 | |
29b0f896 | 4535 | static char * |
e3bb37b5 | 4536 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4537 | { |
4538 | char *token_start; | |
3138f287 | 4539 | |
29b0f896 AM |
4540 | /* 1 if operand is pending after ','. */ |
4541 | unsigned int expecting_operand = 0; | |
252b5132 | 4542 | |
29b0f896 AM |
4543 | /* Non-zero if operand parens not balanced. */ |
4544 | unsigned int paren_not_balanced; | |
4545 | ||
4546 | while (*l != END_OF_INSN) | |
4547 | { | |
4548 | /* Skip optional white space before operand. */ | |
4549 | if (is_space_char (*l)) | |
4550 | ++l; | |
d02603dc | 4551 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4552 | { |
4553 | as_bad (_("invalid character %s before operand %d"), | |
4554 | output_invalid (*l), | |
4555 | i.operands + 1); | |
4556 | return NULL; | |
4557 | } | |
d02603dc | 4558 | token_start = l; /* After white space. */ |
29b0f896 AM |
4559 | paren_not_balanced = 0; |
4560 | while (paren_not_balanced || *l != ',') | |
4561 | { | |
4562 | if (*l == END_OF_INSN) | |
4563 | { | |
4564 | if (paren_not_balanced) | |
4565 | { | |
4566 | if (!intel_syntax) | |
4567 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4568 | i.operands + 1); | |
4569 | else | |
4570 | as_bad (_("unbalanced brackets in operand %d."), | |
4571 | i.operands + 1); | |
4572 | return NULL; | |
4573 | } | |
4574 | else | |
4575 | break; /* we are done */ | |
4576 | } | |
d02603dc | 4577 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4578 | { |
4579 | as_bad (_("invalid character %s in operand %d"), | |
4580 | output_invalid (*l), | |
4581 | i.operands + 1); | |
4582 | return NULL; | |
4583 | } | |
4584 | if (!intel_syntax) | |
4585 | { | |
4586 | if (*l == '(') | |
4587 | ++paren_not_balanced; | |
4588 | if (*l == ')') | |
4589 | --paren_not_balanced; | |
4590 | } | |
4591 | else | |
4592 | { | |
4593 | if (*l == '[') | |
4594 | ++paren_not_balanced; | |
4595 | if (*l == ']') | |
4596 | --paren_not_balanced; | |
4597 | } | |
4598 | l++; | |
4599 | } | |
4600 | if (l != token_start) | |
4601 | { /* Yes, we've read in another operand. */ | |
4602 | unsigned int operand_ok; | |
4603 | this_operand = i.operands++; | |
4604 | if (i.operands > MAX_OPERANDS) | |
4605 | { | |
4606 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4607 | MAX_OPERANDS); | |
4608 | return NULL; | |
4609 | } | |
9d46ce34 | 4610 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4611 | /* Now parse operand adding info to 'i' as we go along. */ |
4612 | END_STRING_AND_SAVE (l); | |
4613 | ||
4614 | if (intel_syntax) | |
4615 | operand_ok = | |
4616 | i386_intel_operand (token_start, | |
4617 | intel_float_operand (mnemonic)); | |
4618 | else | |
a7619375 | 4619 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4620 | |
4621 | RESTORE_END_STRING (l); | |
4622 | if (!operand_ok) | |
4623 | return NULL; | |
4624 | } | |
4625 | else | |
4626 | { | |
4627 | if (expecting_operand) | |
4628 | { | |
4629 | expecting_operand_after_comma: | |
4630 | as_bad (_("expecting operand after ','; got nothing")); | |
4631 | return NULL; | |
4632 | } | |
4633 | if (*l == ',') | |
4634 | { | |
4635 | as_bad (_("expecting operand before ','; got nothing")); | |
4636 | return NULL; | |
4637 | } | |
4638 | } | |
7f3f1ea2 | 4639 | |
29b0f896 AM |
4640 | /* Now *l must be either ',' or END_OF_INSN. */ |
4641 | if (*l == ',') | |
4642 | { | |
4643 | if (*++l == END_OF_INSN) | |
4644 | { | |
4645 | /* Just skip it, if it's \n complain. */ | |
4646 | goto expecting_operand_after_comma; | |
4647 | } | |
4648 | expecting_operand = 1; | |
4649 | } | |
4650 | } | |
4651 | return l; | |
4652 | } | |
7f3f1ea2 | 4653 | |
050dfa73 | 4654 | static void |
4d456e3d | 4655 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4656 | { |
4657 | union i386_op temp_op; | |
40fb9820 | 4658 | i386_operand_type temp_type; |
050dfa73 | 4659 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4660 | |
050dfa73 MM |
4661 | temp_type = i.types[xchg2]; |
4662 | i.types[xchg2] = i.types[xchg1]; | |
4663 | i.types[xchg1] = temp_type; | |
4664 | temp_op = i.op[xchg2]; | |
4665 | i.op[xchg2] = i.op[xchg1]; | |
4666 | i.op[xchg1] = temp_op; | |
4667 | temp_reloc = i.reloc[xchg2]; | |
4668 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4669 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4670 | |
4671 | if (i.mask) | |
4672 | { | |
4673 | if (i.mask->operand == xchg1) | |
4674 | i.mask->operand = xchg2; | |
4675 | else if (i.mask->operand == xchg2) | |
4676 | i.mask->operand = xchg1; | |
4677 | } | |
4678 | if (i.broadcast) | |
4679 | { | |
4680 | if (i.broadcast->operand == xchg1) | |
4681 | i.broadcast->operand = xchg2; | |
4682 | else if (i.broadcast->operand == xchg2) | |
4683 | i.broadcast->operand = xchg1; | |
4684 | } | |
4685 | if (i.rounding) | |
4686 | { | |
4687 | if (i.rounding->operand == xchg1) | |
4688 | i.rounding->operand = xchg2; | |
4689 | else if (i.rounding->operand == xchg2) | |
4690 | i.rounding->operand = xchg1; | |
4691 | } | |
050dfa73 MM |
4692 | } |
4693 | ||
29b0f896 | 4694 | static void |
e3bb37b5 | 4695 | swap_operands (void) |
29b0f896 | 4696 | { |
b7c61d9a | 4697 | switch (i.operands) |
050dfa73 | 4698 | { |
c0f3af97 | 4699 | case 5: |
b7c61d9a | 4700 | case 4: |
4d456e3d | 4701 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4702 | /* Fall through. */ |
b7c61d9a L |
4703 | case 3: |
4704 | case 2: | |
4d456e3d | 4705 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4706 | break; |
4707 | default: | |
4708 | abort (); | |
29b0f896 | 4709 | } |
29b0f896 AM |
4710 | |
4711 | if (i.mem_operands == 2) | |
4712 | { | |
4713 | const seg_entry *temp_seg; | |
4714 | temp_seg = i.seg[0]; | |
4715 | i.seg[0] = i.seg[1]; | |
4716 | i.seg[1] = temp_seg; | |
4717 | } | |
4718 | } | |
252b5132 | 4719 | |
29b0f896 AM |
4720 | /* Try to ensure constant immediates are represented in the smallest |
4721 | opcode possible. */ | |
4722 | static void | |
e3bb37b5 | 4723 | optimize_imm (void) |
29b0f896 AM |
4724 | { |
4725 | char guess_suffix = 0; | |
4726 | int op; | |
252b5132 | 4727 | |
29b0f896 AM |
4728 | if (i.suffix) |
4729 | guess_suffix = i.suffix; | |
4730 | else if (i.reg_operands) | |
4731 | { | |
4732 | /* Figure out a suffix from the last register operand specified. | |
4733 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4734 | but the following works for instructions with immediates. | |
4735 | In any case, we can't set i.suffix yet. */ | |
4736 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4737 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4738 | { |
40fb9820 L |
4739 | guess_suffix = BYTE_MNEM_SUFFIX; |
4740 | break; | |
4741 | } | |
dc821c5f | 4742 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4743 | { |
40fb9820 L |
4744 | guess_suffix = WORD_MNEM_SUFFIX; |
4745 | break; | |
4746 | } | |
dc821c5f | 4747 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4748 | { |
4749 | guess_suffix = LONG_MNEM_SUFFIX; | |
4750 | break; | |
4751 | } | |
dc821c5f | 4752 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4753 | { |
4754 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4755 | break; |
252b5132 | 4756 | } |
29b0f896 AM |
4757 | } |
4758 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4759 | guess_suffix = WORD_MNEM_SUFFIX; | |
4760 | ||
4761 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4762 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4763 | { |
4764 | switch (i.op[op].imms->X_op) | |
252b5132 | 4765 | { |
29b0f896 AM |
4766 | case O_constant: |
4767 | /* If a suffix is given, this operand may be shortened. */ | |
4768 | switch (guess_suffix) | |
252b5132 | 4769 | { |
29b0f896 | 4770 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4771 | i.types[op].bitfield.imm32 = 1; |
4772 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4773 | break; |
4774 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4775 | i.types[op].bitfield.imm16 = 1; |
4776 | i.types[op].bitfield.imm32 = 1; | |
4777 | i.types[op].bitfield.imm32s = 1; | |
4778 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4779 | break; |
4780 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4781 | i.types[op].bitfield.imm8 = 1; |
4782 | i.types[op].bitfield.imm8s = 1; | |
4783 | i.types[op].bitfield.imm16 = 1; | |
4784 | i.types[op].bitfield.imm32 = 1; | |
4785 | i.types[op].bitfield.imm32s = 1; | |
4786 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4787 | break; |
252b5132 | 4788 | } |
252b5132 | 4789 | |
29b0f896 AM |
4790 | /* If this operand is at most 16 bits, convert it |
4791 | to a signed 16 bit number before trying to see | |
4792 | whether it will fit in an even smaller size. | |
4793 | This allows a 16-bit operand such as $0xffe0 to | |
4794 | be recognised as within Imm8S range. */ | |
40fb9820 | 4795 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4796 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4797 | { |
29b0f896 AM |
4798 | i.op[op].imms->X_add_number = |
4799 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4800 | } | |
a28def75 L |
4801 | #ifdef BFD64 |
4802 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4803 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4804 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4805 | == 0)) | |
4806 | { | |
4807 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4808 | ^ ((offsetT) 1 << 31)) | |
4809 | - ((offsetT) 1 << 31)); | |
4810 | } | |
a28def75 | 4811 | #endif |
40fb9820 | 4812 | i.types[op] |
c6fb90c8 L |
4813 | = operand_type_or (i.types[op], |
4814 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4815 | |
29b0f896 AM |
4816 | /* We must avoid matching of Imm32 templates when 64bit |
4817 | only immediate is available. */ | |
4818 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4819 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4820 | break; |
252b5132 | 4821 | |
29b0f896 AM |
4822 | case O_absent: |
4823 | case O_register: | |
4824 | abort (); | |
4825 | ||
4826 | /* Symbols and expressions. */ | |
4827 | default: | |
9cd96992 JB |
4828 | /* Convert symbolic operand to proper sizes for matching, but don't |
4829 | prevent matching a set of insns that only supports sizes other | |
4830 | than those matching the insn suffix. */ | |
4831 | { | |
40fb9820 | 4832 | i386_operand_type mask, allowed; |
d3ce72d0 | 4833 | const insn_template *t; |
9cd96992 | 4834 | |
0dfbf9d7 L |
4835 | operand_type_set (&mask, 0); |
4836 | operand_type_set (&allowed, 0); | |
40fb9820 | 4837 | |
4eed87de AM |
4838 | for (t = current_templates->start; |
4839 | t < current_templates->end; | |
4840 | ++t) | |
c6fb90c8 L |
4841 | allowed = operand_type_or (allowed, |
4842 | t->operand_types[op]); | |
9cd96992 JB |
4843 | switch (guess_suffix) |
4844 | { | |
4845 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4846 | mask.bitfield.imm64 = 1; |
4847 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4848 | break; |
4849 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4850 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4851 | break; |
4852 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4853 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4854 | break; |
4855 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4856 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4857 | break; |
4858 | default: | |
9cd96992 JB |
4859 | break; |
4860 | } | |
c6fb90c8 | 4861 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4862 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4863 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4864 | } |
29b0f896 | 4865 | break; |
252b5132 | 4866 | } |
29b0f896 AM |
4867 | } |
4868 | } | |
47926f60 | 4869 | |
29b0f896 AM |
4870 | /* Try to use the smallest displacement type too. */ |
4871 | static void | |
e3bb37b5 | 4872 | optimize_disp (void) |
29b0f896 AM |
4873 | { |
4874 | int op; | |
3e73aa7c | 4875 | |
29b0f896 | 4876 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4877 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4878 | { |
b300c311 | 4879 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4880 | { |
91d6fa6a | 4881 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4882 | |
40fb9820 | 4883 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4884 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4885 | { |
4886 | /* If this operand is at most 16 bits, convert | |
4887 | to a signed 16 bit number and don't use 64bit | |
4888 | displacement. */ | |
91d6fa6a | 4889 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4890 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4891 | } |
a28def75 L |
4892 | #ifdef BFD64 |
4893 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4894 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4895 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4896 | { |
4897 | /* If this operand is at most 32 bits, convert | |
4898 | to a signed 32 bit number and don't use 64bit | |
4899 | displacement. */ | |
91d6fa6a NC |
4900 | op_disp &= (((offsetT) 2 << 31) - 1); |
4901 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4902 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4903 | } |
a28def75 | 4904 | #endif |
91d6fa6a | 4905 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4906 | { |
40fb9820 L |
4907 | i.types[op].bitfield.disp8 = 0; |
4908 | i.types[op].bitfield.disp16 = 0; | |
4909 | i.types[op].bitfield.disp32 = 0; | |
4910 | i.types[op].bitfield.disp32s = 0; | |
4911 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4912 | i.op[op].disps = 0; |
4913 | i.disp_operands--; | |
4914 | } | |
4915 | else if (flag_code == CODE_64BIT) | |
4916 | { | |
91d6fa6a | 4917 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4918 | { |
40fb9820 L |
4919 | i.types[op].bitfield.disp64 = 0; |
4920 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4921 | } |
0e1147d9 | 4922 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4923 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4924 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4925 | } |
40fb9820 L |
4926 | if ((i.types[op].bitfield.disp32 |
4927 | || i.types[op].bitfield.disp32s | |
4928 | || i.types[op].bitfield.disp16) | |
b5014f7a | 4929 | && fits_in_disp8 (op_disp)) |
40fb9820 | 4930 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4931 | } |
67a4f2b7 AO |
4932 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
4933 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
4934 | { | |
4935 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
4936 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
4937 | i.types[op].bitfield.disp8 = 0; |
4938 | i.types[op].bitfield.disp16 = 0; | |
4939 | i.types[op].bitfield.disp32 = 0; | |
4940 | i.types[op].bitfield.disp32s = 0; | |
4941 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
4942 | } |
4943 | else | |
b300c311 | 4944 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 4945 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 4946 | } |
29b0f896 AM |
4947 | } |
4948 | ||
6c30d220 L |
4949 | /* Check if operands are valid for the instruction. */ |
4950 | ||
4951 | static int | |
4952 | check_VecOperands (const insn_template *t) | |
4953 | { | |
43234a1e L |
4954 | unsigned int op; |
4955 | ||
6c30d220 L |
4956 | /* Without VSIB byte, we can't have a vector register for index. */ |
4957 | if (!t->opcode_modifier.vecsib | |
4958 | && i.index_reg | |
1b54b8d7 JB |
4959 | && (i.index_reg->reg_type.bitfield.xmmword |
4960 | || i.index_reg->reg_type.bitfield.ymmword | |
4961 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
4962 | { |
4963 | i.error = unsupported_vector_index_register; | |
4964 | return 1; | |
4965 | } | |
4966 | ||
ad8ecc81 MZ |
4967 | /* Check if default mask is allowed. */ |
4968 | if (t->opcode_modifier.nodefmask | |
4969 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
4970 | { | |
4971 | i.error = no_default_mask; | |
4972 | return 1; | |
4973 | } | |
4974 | ||
7bab8ab5 JB |
4975 | /* For VSIB byte, we need a vector register for index, and all vector |
4976 | registers must be distinct. */ | |
4977 | if (t->opcode_modifier.vecsib) | |
4978 | { | |
4979 | if (!i.index_reg | |
6c30d220 | 4980 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 4981 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 4982 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 4983 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 4984 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 4985 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
4986 | { |
4987 | i.error = invalid_vsib_address; | |
4988 | return 1; | |
4989 | } | |
4990 | ||
43234a1e L |
4991 | gas_assert (i.reg_operands == 2 || i.mask); |
4992 | if (i.reg_operands == 2 && !i.mask) | |
4993 | { | |
1b54b8d7 JB |
4994 | gas_assert (i.types[0].bitfield.regsimd); |
4995 | gas_assert (i.types[0].bitfield.xmmword | |
4996 | || i.types[0].bitfield.ymmword); | |
4997 | gas_assert (i.types[2].bitfield.regsimd); | |
4998 | gas_assert (i.types[2].bitfield.xmmword | |
4999 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5000 | if (operand_check == check_none) |
5001 | return 0; | |
5002 | if (register_number (i.op[0].regs) | |
5003 | != register_number (i.index_reg) | |
5004 | && register_number (i.op[2].regs) | |
5005 | != register_number (i.index_reg) | |
5006 | && register_number (i.op[0].regs) | |
5007 | != register_number (i.op[2].regs)) | |
5008 | return 0; | |
5009 | if (operand_check == check_error) | |
5010 | { | |
5011 | i.error = invalid_vector_register_set; | |
5012 | return 1; | |
5013 | } | |
5014 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5015 | } | |
8444f82a MZ |
5016 | else if (i.reg_operands == 1 && i.mask) |
5017 | { | |
1b54b8d7 JB |
5018 | if (i.types[1].bitfield.regsimd |
5019 | && (i.types[1].bitfield.xmmword | |
5020 | || i.types[1].bitfield.ymmword | |
5021 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5022 | && (register_number (i.op[1].regs) |
5023 | == register_number (i.index_reg))) | |
5024 | { | |
5025 | if (operand_check == check_error) | |
5026 | { | |
5027 | i.error = invalid_vector_register_set; | |
5028 | return 1; | |
5029 | } | |
5030 | if (operand_check != check_none) | |
5031 | as_warn (_("index and destination registers should be distinct")); | |
5032 | } | |
5033 | } | |
43234a1e | 5034 | } |
7bab8ab5 | 5035 | |
43234a1e L |
5036 | /* Check if broadcast is supported by the instruction and is applied |
5037 | to the memory operand. */ | |
5038 | if (i.broadcast) | |
5039 | { | |
5040 | int broadcasted_opnd_size; | |
5041 | ||
5042 | /* Check if specified broadcast is supported in this instruction, | |
5043 | and it's applied to memory operand of DWORD or QWORD type, | |
5044 | depending on VecESize. */ | |
5045 | if (i.broadcast->type != t->opcode_modifier.broadcast | |
5046 | || !i.types[i.broadcast->operand].bitfield.mem | |
5047 | || (t->opcode_modifier.vecesize == 0 | |
5048 | && !i.types[i.broadcast->operand].bitfield.dword | |
5049 | && !i.types[i.broadcast->operand].bitfield.unspecified) | |
5050 | || (t->opcode_modifier.vecesize == 1 | |
5051 | && !i.types[i.broadcast->operand].bitfield.qword | |
5052 | && !i.types[i.broadcast->operand].bitfield.unspecified)) | |
5053 | goto bad_broadcast; | |
5054 | ||
5055 | broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; | |
5056 | if (i.broadcast->type == BROADCAST_1TO16) | |
5057 | broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ | |
5058 | else if (i.broadcast->type == BROADCAST_1TO8) | |
5059 | broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ | |
b28d1bda IT |
5060 | else if (i.broadcast->type == BROADCAST_1TO4) |
5061 | broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ | |
5062 | else if (i.broadcast->type == BROADCAST_1TO2) | |
5063 | broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ | |
43234a1e L |
5064 | else |
5065 | goto bad_broadcast; | |
5066 | ||
5067 | if ((broadcasted_opnd_size == 256 | |
5068 | && !t->operand_types[i.broadcast->operand].bitfield.ymmword) | |
5069 | || (broadcasted_opnd_size == 512 | |
5070 | && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) | |
5071 | { | |
5072 | bad_broadcast: | |
5073 | i.error = unsupported_broadcast; | |
5074 | return 1; | |
5075 | } | |
5076 | } | |
5077 | /* If broadcast is supported in this instruction, we need to check if | |
5078 | operand of one-element size isn't specified without broadcast. */ | |
5079 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5080 | { | |
5081 | /* Find memory operand. */ | |
5082 | for (op = 0; op < i.operands; op++) | |
5083 | if (operand_type_check (i.types[op], anymem)) | |
5084 | break; | |
5085 | gas_assert (op < i.operands); | |
5086 | /* Check size of the memory operand. */ | |
5087 | if ((t->opcode_modifier.vecesize == 0 | |
5088 | && i.types[op].bitfield.dword) | |
5089 | || (t->opcode_modifier.vecesize == 1 | |
5090 | && i.types[op].bitfield.qword)) | |
5091 | { | |
5092 | i.error = broadcast_needed; | |
5093 | return 1; | |
5094 | } | |
5095 | } | |
5096 | ||
5097 | /* Check if requested masking is supported. */ | |
5098 | if (i.mask | |
5099 | && (!t->opcode_modifier.masking | |
5100 | || (i.mask->zeroing | |
5101 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
5102 | { | |
5103 | i.error = unsupported_masking; | |
5104 | return 1; | |
5105 | } | |
5106 | ||
5107 | /* Check if masking is applied to dest operand. */ | |
5108 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5109 | { | |
5110 | i.error = mask_not_on_destination; | |
5111 | return 1; | |
5112 | } | |
5113 | ||
43234a1e L |
5114 | /* Check RC/SAE. */ |
5115 | if (i.rounding) | |
5116 | { | |
5117 | if ((i.rounding->type != saeonly | |
5118 | && !t->opcode_modifier.staticrounding) | |
5119 | || (i.rounding->type == saeonly | |
5120 | && (t->opcode_modifier.staticrounding | |
5121 | || !t->opcode_modifier.sae))) | |
5122 | { | |
5123 | i.error = unsupported_rc_sae; | |
5124 | return 1; | |
5125 | } | |
5126 | /* If the instruction has several immediate operands and one of | |
5127 | them is rounding, the rounding operand should be the last | |
5128 | immediate operand. */ | |
5129 | if (i.imm_operands > 1 | |
5130 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5131 | { |
43234a1e | 5132 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5133 | return 1; |
5134 | } | |
6c30d220 L |
5135 | } |
5136 | ||
43234a1e | 5137 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5138 | if (t->opcode_modifier.disp8memshift |
5139 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5140 | { |
5141 | if (i.broadcast) | |
5142 | i.memshift = t->opcode_modifier.vecesize ? 3 : 2; | |
5143 | else | |
5144 | i.memshift = t->opcode_modifier.disp8memshift; | |
5145 | ||
5146 | for (op = 0; op < i.operands; op++) | |
5147 | if (operand_type_check (i.types[op], disp) | |
5148 | && i.op[op].disps->X_op == O_constant) | |
5149 | { | |
b5014f7a | 5150 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5151 | { |
b5014f7a JB |
5152 | i.types[op].bitfield.disp8 = 1; |
5153 | return 0; | |
43234a1e | 5154 | } |
b5014f7a | 5155 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5156 | } |
5157 | } | |
b5014f7a JB |
5158 | |
5159 | i.memshift = 0; | |
43234a1e | 5160 | |
6c30d220 L |
5161 | return 0; |
5162 | } | |
5163 | ||
43f3e2ee | 5164 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5165 | operand types. */ |
5166 | ||
5167 | static int | |
5168 | VEX_check_operands (const insn_template *t) | |
5169 | { | |
86fa6981 | 5170 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5171 | { |
86fa6981 L |
5172 | /* This instruction must be encoded with EVEX prefix. */ |
5173 | if (!t->opcode_modifier.evex) | |
5174 | { | |
5175 | i.error = unsupported; | |
5176 | return 1; | |
5177 | } | |
5178 | return 0; | |
43234a1e L |
5179 | } |
5180 | ||
a683cc34 | 5181 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5182 | { |
5183 | /* This instruction template doesn't have VEX prefix. */ | |
5184 | if (i.vec_encoding != vex_encoding_default) | |
5185 | { | |
5186 | i.error = unsupported; | |
5187 | return 1; | |
5188 | } | |
5189 | return 0; | |
5190 | } | |
a683cc34 SP |
5191 | |
5192 | /* Only check VEX_Imm4, which must be the first operand. */ | |
5193 | if (t->operand_types[0].bitfield.vec_imm4) | |
5194 | { | |
5195 | if (i.op[0].imms->X_op != O_constant | |
5196 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5197 | { |
a65babc9 | 5198 | i.error = bad_imm4; |
891edac4 L |
5199 | return 1; |
5200 | } | |
a683cc34 SP |
5201 | |
5202 | /* Turn off Imm8 so that update_imm won't complain. */ | |
5203 | i.types[0] = vec_imm4; | |
5204 | } | |
5205 | ||
5206 | return 0; | |
5207 | } | |
5208 | ||
d3ce72d0 | 5209 | static const insn_template * |
83b16ac6 | 5210 | match_template (char mnem_suffix) |
29b0f896 AM |
5211 | { |
5212 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5213 | const insn_template *t; |
40fb9820 | 5214 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5215 | i386_operand_type overlap4; |
29b0f896 | 5216 | unsigned int found_reverse_match; |
83b16ac6 | 5217 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5218 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5219 | int addr_prefix_disp; |
a5c311ca | 5220 | unsigned int j; |
3629bb00 | 5221 | unsigned int found_cpu_match; |
45664ddb | 5222 | unsigned int check_register; |
5614d22c | 5223 | enum i386_error specific_error = 0; |
29b0f896 | 5224 | |
c0f3af97 L |
5225 | #if MAX_OPERANDS != 5 |
5226 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5227 | #endif |
5228 | ||
29b0f896 | 5229 | found_reverse_match = 0; |
539e75ad | 5230 | addr_prefix_disp = -1; |
40fb9820 L |
5231 | |
5232 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
5233 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
5234 | suffix_check.no_bsuf = 1; | |
5235 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5236 | suffix_check.no_wsuf = 1; | |
5237 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5238 | suffix_check.no_ssuf = 1; | |
5239 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5240 | suffix_check.no_lsuf = 1; | |
5241 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5242 | suffix_check.no_qsuf = 1; | |
5243 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5244 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5245 | |
83b16ac6 JB |
5246 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5247 | if (intel_syntax) | |
5248 | { | |
5249 | switch (mnem_suffix) | |
5250 | { | |
5251 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5252 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5253 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5254 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5255 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5256 | } | |
5257 | } | |
5258 | ||
01559ecc L |
5259 | /* Must have right number of operands. */ |
5260 | i.error = number_of_operands_mismatch; | |
5261 | ||
45aa61fe | 5262 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5263 | { |
539e75ad L |
5264 | addr_prefix_disp = -1; |
5265 | ||
29b0f896 AM |
5266 | if (i.operands != t->operands) |
5267 | continue; | |
5268 | ||
50aecf8c | 5269 | /* Check processor support. */ |
a65babc9 | 5270 | i.error = unsupported; |
c0f3af97 L |
5271 | found_cpu_match = (cpu_flags_match (t) |
5272 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5273 | if (!found_cpu_match) |
5274 | continue; | |
5275 | ||
e1d4d893 | 5276 | /* Check old gcc support. */ |
a65babc9 | 5277 | i.error = old_gcc_only; |
e1d4d893 L |
5278 | if (!old_gcc && t->opcode_modifier.oldgcc) |
5279 | continue; | |
5280 | ||
5281 | /* Check AT&T mnemonic. */ | |
a65babc9 | 5282 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5283 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5284 | continue; |
5285 | ||
e92bae62 | 5286 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5287 | i.error = unsupported_syntax; |
5c07affc | 5288 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5289 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5290 | || (intel64 && t->opcode_modifier.amd64) | |
5291 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5292 | continue; |
5293 | ||
20592a94 | 5294 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5295 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5296 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5297 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5298 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5299 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5300 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5301 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5302 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5303 | continue; |
83b16ac6 JB |
5304 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5305 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5306 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5307 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5308 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5309 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5310 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5311 | continue; | |
29b0f896 | 5312 | |
5c07affc | 5313 | if (!operand_size_match (t)) |
7d5e4556 | 5314 | continue; |
539e75ad | 5315 | |
5c07affc L |
5316 | for (j = 0; j < MAX_OPERANDS; j++) |
5317 | operand_types[j] = t->operand_types[j]; | |
5318 | ||
45aa61fe AM |
5319 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5320 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5321 | && flag_code != CODE_64BIT | |
5322 | && (intel_syntax | |
40fb9820 | 5323 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
5324 | && !intel_float_operand (t->name)) |
5325 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5326 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5327 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5328 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5329 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5330 | && (t->base_opcode != 0x0fc7 |
5331 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5332 | continue; | |
5333 | ||
192dc9c6 JB |
5334 | /* In general, don't allow 32-bit operands on pre-386. */ |
5335 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5336 | && !cpu_arch_flags.bitfield.cpui386 | |
5337 | && (intel_syntax | |
5338 | ? (!t->opcode_modifier.ignoresize | |
5339 | && !intel_float_operand (t->name)) | |
5340 | : intel_float_operand (t->name) != 2) | |
5341 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5342 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5343 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5344 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5345 | continue; |
5346 | ||
29b0f896 | 5347 | /* Do not verify operands when there are none. */ |
50aecf8c | 5348 | else |
29b0f896 | 5349 | { |
c6fb90c8 | 5350 | if (!t->operands) |
2dbab7d5 L |
5351 | /* We've found a match; break out of loop. */ |
5352 | break; | |
29b0f896 | 5353 | } |
252b5132 | 5354 | |
539e75ad L |
5355 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5356 | into Disp32/Disp16/Disp32 operand. */ | |
5357 | if (i.prefix[ADDR_PREFIX] != 0) | |
5358 | { | |
40fb9820 | 5359 | /* There should be only one Disp operand. */ |
539e75ad L |
5360 | switch (flag_code) |
5361 | { | |
5362 | case CODE_16BIT: | |
40fb9820 L |
5363 | for (j = 0; j < MAX_OPERANDS; j++) |
5364 | { | |
5365 | if (operand_types[j].bitfield.disp16) | |
5366 | { | |
5367 | addr_prefix_disp = j; | |
5368 | operand_types[j].bitfield.disp32 = 1; | |
5369 | operand_types[j].bitfield.disp16 = 0; | |
5370 | break; | |
5371 | } | |
5372 | } | |
539e75ad L |
5373 | break; |
5374 | case CODE_32BIT: | |
40fb9820 L |
5375 | for (j = 0; j < MAX_OPERANDS; j++) |
5376 | { | |
5377 | if (operand_types[j].bitfield.disp32) | |
5378 | { | |
5379 | addr_prefix_disp = j; | |
5380 | operand_types[j].bitfield.disp32 = 0; | |
5381 | operand_types[j].bitfield.disp16 = 1; | |
5382 | break; | |
5383 | } | |
5384 | } | |
539e75ad L |
5385 | break; |
5386 | case CODE_64BIT: | |
40fb9820 L |
5387 | for (j = 0; j < MAX_OPERANDS; j++) |
5388 | { | |
5389 | if (operand_types[j].bitfield.disp64) | |
5390 | { | |
5391 | addr_prefix_disp = j; | |
5392 | operand_types[j].bitfield.disp64 = 0; | |
5393 | operand_types[j].bitfield.disp32 = 1; | |
5394 | break; | |
5395 | } | |
5396 | } | |
539e75ad L |
5397 | break; |
5398 | } | |
539e75ad L |
5399 | } |
5400 | ||
02a86693 L |
5401 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5402 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5403 | continue; | |
5404 | ||
56ffb741 L |
5405 | /* We check register size if needed. */ |
5406 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 5407 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5408 | switch (t->operands) |
5409 | { | |
5410 | case 1: | |
40fb9820 | 5411 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5412 | continue; |
5413 | break; | |
5414 | case 2: | |
33eaf5de | 5415 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5416 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5417 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5418 | zero-extend %eax to %rax. */ | |
5419 | if (flag_code == CODE_64BIT | |
5420 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5421 | && operand_type_equal (&i.types [0], &acc32) |
5422 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5423 | continue; |
86fa6981 L |
5424 | /* If we want store form, we reverse direction of operands. */ |
5425 | if (i.dir_encoding == dir_encoding_store | |
5426 | && t->opcode_modifier.d) | |
5427 | goto check_reverse; | |
1a0670f3 | 5428 | /* Fall through. */ |
b6169b20 | 5429 | |
29b0f896 | 5430 | case 3: |
86fa6981 L |
5431 | /* If we want store form, we skip the current load. */ |
5432 | if (i.dir_encoding == dir_encoding_store | |
5433 | && i.mem_operands == 0 | |
5434 | && t->opcode_modifier.load) | |
fa99fab2 | 5435 | continue; |
1a0670f3 | 5436 | /* Fall through. */ |
f48ff2ae | 5437 | case 4: |
c0f3af97 | 5438 | case 5: |
c6fb90c8 | 5439 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5440 | if (!operand_type_match (overlap0, i.types[0]) |
5441 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5442 | || (check_register |
dc821c5f | 5443 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5444 | operand_types[0], |
dc821c5f | 5445 | i.types[1], |
40fb9820 | 5446 | operand_types[1]))) |
29b0f896 AM |
5447 | { |
5448 | /* Check if other direction is valid ... */ | |
40fb9820 | 5449 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
5450 | continue; |
5451 | ||
b6169b20 | 5452 | check_reverse: |
29b0f896 | 5453 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5454 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5455 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5456 | if (!operand_type_match (overlap0, i.types[0]) |
5457 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5458 | || (check_register |
dc821c5f | 5459 | && !operand_type_register_match (i.types[0], |
45664ddb | 5460 | operand_types[1], |
45664ddb L |
5461 | i.types[1], |
5462 | operand_types[0]))) | |
29b0f896 AM |
5463 | { |
5464 | /* Does not match either direction. */ | |
5465 | continue; | |
5466 | } | |
5467 | /* found_reverse_match holds which of D or FloatDR | |
5468 | we've found. */ | |
40fb9820 | 5469 | if (t->opcode_modifier.d) |
8a2ed489 | 5470 | found_reverse_match = Opcode_D; |
40fb9820 | 5471 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
5472 | found_reverse_match = Opcode_FloatD; |
5473 | else | |
5474 | found_reverse_match = 0; | |
40fb9820 | 5475 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5476 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5477 | } |
f48ff2ae | 5478 | else |
29b0f896 | 5479 | { |
f48ff2ae | 5480 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5481 | switch (t->operands) |
5482 | { | |
c0f3af97 L |
5483 | case 5: |
5484 | overlap4 = operand_type_and (i.types[4], | |
5485 | operand_types[4]); | |
1a0670f3 | 5486 | /* Fall through. */ |
d1cbb4db | 5487 | case 4: |
c6fb90c8 L |
5488 | overlap3 = operand_type_and (i.types[3], |
5489 | operand_types[3]); | |
1a0670f3 | 5490 | /* Fall through. */ |
d1cbb4db | 5491 | case 3: |
c6fb90c8 L |
5492 | overlap2 = operand_type_and (i.types[2], |
5493 | operand_types[2]); | |
d1cbb4db L |
5494 | break; |
5495 | } | |
29b0f896 | 5496 | |
f48ff2ae L |
5497 | switch (t->operands) |
5498 | { | |
c0f3af97 L |
5499 | case 5: |
5500 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5501 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5502 | operand_types[3], |
c0f3af97 L |
5503 | i.types[4], |
5504 | operand_types[4])) | |
5505 | continue; | |
1a0670f3 | 5506 | /* Fall through. */ |
f48ff2ae | 5507 | case 4: |
40fb9820 | 5508 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb | 5509 | || (check_register |
dc821c5f | 5510 | && !operand_type_register_match (i.types[2], |
45664ddb | 5511 | operand_types[2], |
45664ddb L |
5512 | i.types[3], |
5513 | operand_types[3]))) | |
f48ff2ae | 5514 | continue; |
1a0670f3 | 5515 | /* Fall through. */ |
f48ff2ae L |
5516 | case 3: |
5517 | /* Here we make use of the fact that there are no | |
5518 | reverse match 3 operand instructions, and all 3 | |
5519 | operand instructions only need to be checked for | |
5520 | register consistency between operands 2 and 3. */ | |
40fb9820 | 5521 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb | 5522 | || (check_register |
dc821c5f | 5523 | && !operand_type_register_match (i.types[1], |
45664ddb | 5524 | operand_types[1], |
45664ddb L |
5525 | i.types[2], |
5526 | operand_types[2]))) | |
f48ff2ae L |
5527 | continue; |
5528 | break; | |
5529 | } | |
29b0f896 | 5530 | } |
f48ff2ae | 5531 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5532 | slip through to break. */ |
5533 | } | |
3629bb00 | 5534 | if (!found_cpu_match) |
29b0f896 AM |
5535 | { |
5536 | found_reverse_match = 0; | |
5537 | continue; | |
5538 | } | |
c0f3af97 | 5539 | |
5614d22c JB |
5540 | /* Check if vector and VEX operands are valid. */ |
5541 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5542 | { | |
5543 | specific_error = i.error; | |
5544 | continue; | |
5545 | } | |
a683cc34 | 5546 | |
29b0f896 AM |
5547 | /* We've found a match; break out of loop. */ |
5548 | break; | |
5549 | } | |
5550 | ||
5551 | if (t == current_templates->end) | |
5552 | { | |
5553 | /* We found no match. */ | |
a65babc9 | 5554 | const char *err_msg; |
5614d22c | 5555 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5556 | { |
5557 | default: | |
5558 | abort (); | |
86e026a4 | 5559 | case operand_size_mismatch: |
a65babc9 L |
5560 | err_msg = _("operand size mismatch"); |
5561 | break; | |
5562 | case operand_type_mismatch: | |
5563 | err_msg = _("operand type mismatch"); | |
5564 | break; | |
5565 | case register_type_mismatch: | |
5566 | err_msg = _("register type mismatch"); | |
5567 | break; | |
5568 | case number_of_operands_mismatch: | |
5569 | err_msg = _("number of operands mismatch"); | |
5570 | break; | |
5571 | case invalid_instruction_suffix: | |
5572 | err_msg = _("invalid instruction suffix"); | |
5573 | break; | |
5574 | case bad_imm4: | |
4a2608e3 | 5575 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
5576 | break; |
5577 | case old_gcc_only: | |
5578 | err_msg = _("only supported with old gcc"); | |
5579 | break; | |
5580 | case unsupported_with_intel_mnemonic: | |
5581 | err_msg = _("unsupported with Intel mnemonic"); | |
5582 | break; | |
5583 | case unsupported_syntax: | |
5584 | err_msg = _("unsupported syntax"); | |
5585 | break; | |
5586 | case unsupported: | |
35262a23 | 5587 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5588 | current_templates->start->name); |
5589 | return NULL; | |
6c30d220 L |
5590 | case invalid_vsib_address: |
5591 | err_msg = _("invalid VSIB address"); | |
5592 | break; | |
7bab8ab5 JB |
5593 | case invalid_vector_register_set: |
5594 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5595 | break; | |
6c30d220 L |
5596 | case unsupported_vector_index_register: |
5597 | err_msg = _("unsupported vector index register"); | |
5598 | break; | |
43234a1e L |
5599 | case unsupported_broadcast: |
5600 | err_msg = _("unsupported broadcast"); | |
5601 | break; | |
5602 | case broadcast_not_on_src_operand: | |
5603 | err_msg = _("broadcast not on source memory operand"); | |
5604 | break; | |
5605 | case broadcast_needed: | |
5606 | err_msg = _("broadcast is needed for operand of such type"); | |
5607 | break; | |
5608 | case unsupported_masking: | |
5609 | err_msg = _("unsupported masking"); | |
5610 | break; | |
5611 | case mask_not_on_destination: | |
5612 | err_msg = _("mask not on destination operand"); | |
5613 | break; | |
5614 | case no_default_mask: | |
5615 | err_msg = _("default mask isn't allowed"); | |
5616 | break; | |
5617 | case unsupported_rc_sae: | |
5618 | err_msg = _("unsupported static rounding/sae"); | |
5619 | break; | |
5620 | case rc_sae_operand_not_last_imm: | |
5621 | if (intel_syntax) | |
5622 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5623 | else | |
5624 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5625 | break; | |
5626 | case invalid_register_operand: | |
5627 | err_msg = _("invalid register operand"); | |
5628 | break; | |
a65babc9 L |
5629 | } |
5630 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5631 | current_templates->start->name); |
fa99fab2 | 5632 | return NULL; |
29b0f896 | 5633 | } |
252b5132 | 5634 | |
29b0f896 AM |
5635 | if (!quiet_warnings) |
5636 | { | |
5637 | if (!intel_syntax | |
40fb9820 L |
5638 | && (i.types[0].bitfield.jumpabsolute |
5639 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5640 | { |
5641 | as_warn (_("indirect %s without `*'"), t->name); | |
5642 | } | |
5643 | ||
40fb9820 L |
5644 | if (t->opcode_modifier.isprefix |
5645 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5646 | { |
5647 | /* Warn them that a data or address size prefix doesn't | |
5648 | affect assembly of the next line of code. */ | |
5649 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5650 | } | |
5651 | } | |
5652 | ||
5653 | /* Copy the template we found. */ | |
5654 | i.tm = *t; | |
539e75ad L |
5655 | |
5656 | if (addr_prefix_disp != -1) | |
5657 | i.tm.operand_types[addr_prefix_disp] | |
5658 | = operand_types[addr_prefix_disp]; | |
5659 | ||
29b0f896 AM |
5660 | if (found_reverse_match) |
5661 | { | |
5662 | /* If we found a reverse match we must alter the opcode | |
5663 | direction bit. found_reverse_match holds bits to change | |
5664 | (different for int & float insns). */ | |
5665 | ||
5666 | i.tm.base_opcode ^= found_reverse_match; | |
5667 | ||
539e75ad L |
5668 | i.tm.operand_types[0] = operand_types[1]; |
5669 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5670 | } |
5671 | ||
fa99fab2 | 5672 | return t; |
29b0f896 AM |
5673 | } |
5674 | ||
5675 | static int | |
e3bb37b5 | 5676 | check_string (void) |
29b0f896 | 5677 | { |
40fb9820 L |
5678 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5679 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5680 | { |
5681 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5682 | { | |
a87af027 | 5683 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5684 | i.tm.name, |
a87af027 JB |
5685 | mem_op + 1, |
5686 | register_prefix); | |
29b0f896 AM |
5687 | return 0; |
5688 | } | |
5689 | /* There's only ever one segment override allowed per instruction. | |
5690 | This instruction possibly has a legal segment override on the | |
5691 | second operand, so copy the segment to where non-string | |
5692 | instructions store it, allowing common code. */ | |
5693 | i.seg[0] = i.seg[1]; | |
5694 | } | |
40fb9820 | 5695 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5696 | { |
5697 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5698 | { | |
a87af027 | 5699 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5700 | i.tm.name, |
a87af027 JB |
5701 | mem_op + 2, |
5702 | register_prefix); | |
29b0f896 AM |
5703 | return 0; |
5704 | } | |
5705 | } | |
5706 | return 1; | |
5707 | } | |
5708 | ||
5709 | static int | |
543613e9 | 5710 | process_suffix (void) |
29b0f896 AM |
5711 | { |
5712 | /* If matched instruction specifies an explicit instruction mnemonic | |
5713 | suffix, use it. */ | |
40fb9820 L |
5714 | if (i.tm.opcode_modifier.size16) |
5715 | i.suffix = WORD_MNEM_SUFFIX; | |
5716 | else if (i.tm.opcode_modifier.size32) | |
5717 | i.suffix = LONG_MNEM_SUFFIX; | |
5718 | else if (i.tm.opcode_modifier.size64) | |
5719 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5720 | else if (i.reg_operands) |
5721 | { | |
5722 | /* If there's no instruction mnemonic suffix we try to invent one | |
5723 | based on register operands. */ | |
5724 | if (!i.suffix) | |
5725 | { | |
5726 | /* We take i.suffix from the last register operand specified, | |
5727 | Destination register type is more significant than source | |
381d071f L |
5728 | register type. crc32 in SSE4.2 prefers source register |
5729 | type. */ | |
5730 | if (i.tm.base_opcode == 0xf20f38f1) | |
5731 | { | |
dc821c5f | 5732 | if (i.types[0].bitfield.reg && i.types[0].bitfield.word) |
40fb9820 | 5733 | i.suffix = WORD_MNEM_SUFFIX; |
dc821c5f | 5734 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword) |
40fb9820 | 5735 | i.suffix = LONG_MNEM_SUFFIX; |
dc821c5f | 5736 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword) |
40fb9820 | 5737 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f | 5738 | } |
9344ff29 | 5739 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5740 | { |
dc821c5f | 5741 | if (i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
20592a94 L |
5742 | i.suffix = BYTE_MNEM_SUFFIX; |
5743 | } | |
381d071f L |
5744 | |
5745 | if (!i.suffix) | |
5746 | { | |
5747 | int op; | |
5748 | ||
20592a94 L |
5749 | if (i.tm.base_opcode == 0xf20f38f1 |
5750 | || i.tm.base_opcode == 0xf20f38f0) | |
5751 | { | |
5752 | /* We have to know the operand size for crc32. */ | |
5753 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5754 | i.tm.name); | |
5755 | return 0; | |
5756 | } | |
5757 | ||
381d071f | 5758 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
5759 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
5760 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 5761 | { |
dc821c5f | 5762 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
40fb9820 L |
5763 | { |
5764 | i.suffix = BYTE_MNEM_SUFFIX; | |
5765 | break; | |
5766 | } | |
dc821c5f | 5767 | if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
40fb9820 L |
5768 | { |
5769 | i.suffix = WORD_MNEM_SUFFIX; | |
5770 | break; | |
5771 | } | |
dc821c5f | 5772 | if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
5773 | { |
5774 | i.suffix = LONG_MNEM_SUFFIX; | |
5775 | break; | |
5776 | } | |
dc821c5f | 5777 | if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
5778 | { |
5779 | i.suffix = QWORD_MNEM_SUFFIX; | |
5780 | break; | |
5781 | } | |
381d071f L |
5782 | } |
5783 | } | |
29b0f896 AM |
5784 | } |
5785 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5786 | { | |
2eb952a4 L |
5787 | if (intel_syntax |
5788 | && i.tm.opcode_modifier.ignoresize | |
5789 | && i.tm.opcode_modifier.no_bsuf) | |
5790 | i.suffix = 0; | |
5791 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5792 | return 0; |
5793 | } | |
5794 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5795 | { | |
2eb952a4 L |
5796 | if (intel_syntax |
5797 | && i.tm.opcode_modifier.ignoresize | |
5798 | && i.tm.opcode_modifier.no_lsuf) | |
5799 | i.suffix = 0; | |
5800 | else if (!check_long_reg ()) | |
29b0f896 AM |
5801 | return 0; |
5802 | } | |
5803 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5804 | { | |
955e1e6a L |
5805 | if (intel_syntax |
5806 | && i.tm.opcode_modifier.ignoresize | |
5807 | && i.tm.opcode_modifier.no_qsuf) | |
5808 | i.suffix = 0; | |
5809 | else if (!check_qword_reg ()) | |
29b0f896 AM |
5810 | return 0; |
5811 | } | |
5812 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5813 | { | |
2eb952a4 L |
5814 | if (intel_syntax |
5815 | && i.tm.opcode_modifier.ignoresize | |
5816 | && i.tm.opcode_modifier.no_wsuf) | |
5817 | i.suffix = 0; | |
5818 | else if (!check_word_reg ()) | |
29b0f896 AM |
5819 | return 0; |
5820 | } | |
c0f3af97 | 5821 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
43234a1e L |
5822 | || i.suffix == YMMWORD_MNEM_SUFFIX |
5823 | || i.suffix == ZMMWORD_MNEM_SUFFIX) | |
582d5edd | 5824 | { |
43234a1e | 5825 | /* Skip if the instruction has x/y/z suffix. match_template |
582d5edd L |
5826 | should check if it is a valid suffix. */ |
5827 | } | |
40fb9820 | 5828 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
5829 | /* Do nothing if the instruction is going to ignore the prefix. */ |
5830 | ; | |
5831 | else | |
5832 | abort (); | |
5833 | } | |
40fb9820 | 5834 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
5835 | && !i.suffix |
5836 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 5837 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
5838 | { |
5839 | i.suffix = stackop_size; | |
5840 | } | |
9306ca4a JB |
5841 | else if (intel_syntax |
5842 | && !i.suffix | |
40fb9820 L |
5843 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
5844 | || i.tm.opcode_modifier.jumpbyte | |
5845 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
5846 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
5847 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
5848 | { |
5849 | switch (flag_code) | |
5850 | { | |
5851 | case CODE_64BIT: | |
40fb9820 | 5852 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
5853 | { |
5854 | i.suffix = QWORD_MNEM_SUFFIX; | |
5855 | break; | |
5856 | } | |
1a0670f3 | 5857 | /* Fall through. */ |
9306ca4a | 5858 | case CODE_32BIT: |
40fb9820 | 5859 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
5860 | i.suffix = LONG_MNEM_SUFFIX; |
5861 | break; | |
5862 | case CODE_16BIT: | |
40fb9820 | 5863 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
5864 | i.suffix = WORD_MNEM_SUFFIX; |
5865 | break; | |
5866 | } | |
5867 | } | |
252b5132 | 5868 | |
9306ca4a | 5869 | if (!i.suffix) |
29b0f896 | 5870 | { |
9306ca4a JB |
5871 | if (!intel_syntax) |
5872 | { | |
40fb9820 | 5873 | if (i.tm.opcode_modifier.w) |
9306ca4a | 5874 | { |
4eed87de AM |
5875 | as_bad (_("no instruction mnemonic suffix given and " |
5876 | "no register operands; can't size instruction")); | |
9306ca4a JB |
5877 | return 0; |
5878 | } | |
5879 | } | |
5880 | else | |
5881 | { | |
40fb9820 | 5882 | unsigned int suffixes; |
7ab9ffdd | 5883 | |
40fb9820 L |
5884 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
5885 | if (!i.tm.opcode_modifier.no_wsuf) | |
5886 | suffixes |= 1 << 1; | |
5887 | if (!i.tm.opcode_modifier.no_lsuf) | |
5888 | suffixes |= 1 << 2; | |
fc4adea1 | 5889 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
5890 | suffixes |= 1 << 3; |
5891 | if (!i.tm.opcode_modifier.no_ssuf) | |
5892 | suffixes |= 1 << 4; | |
c2b9da16 | 5893 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
5894 | suffixes |= 1 << 5; |
5895 | ||
5896 | /* There are more than suffix matches. */ | |
5897 | if (i.tm.opcode_modifier.w | |
9306ca4a | 5898 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
5899 | && !i.tm.opcode_modifier.defaultsize |
5900 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
5901 | { |
5902 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
5903 | return 0; | |
5904 | } | |
5905 | } | |
29b0f896 | 5906 | } |
252b5132 | 5907 | |
9306ca4a JB |
5908 | /* Change the opcode based on the operand size given by i.suffix; |
5909 | We don't need to change things for byte insns. */ | |
5910 | ||
582d5edd L |
5911 | if (i.suffix |
5912 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 | 5913 | && i.suffix != XMMWORD_MNEM_SUFFIX |
43234a1e L |
5914 | && i.suffix != YMMWORD_MNEM_SUFFIX |
5915 | && i.suffix != ZMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
5916 | { |
5917 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 5918 | if (i.tm.opcode_modifier.w) |
29b0f896 | 5919 | { |
40fb9820 | 5920 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
5921 | i.tm.base_opcode |= 8; |
5922 | else | |
5923 | i.tm.base_opcode |= 1; | |
5924 | } | |
0f3f3d8b | 5925 | |
29b0f896 AM |
5926 | /* Now select between word & dword operations via the operand |
5927 | size prefix, except for instructions that will ignore this | |
5928 | prefix anyway. */ | |
ca61edf2 | 5929 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 5930 | { |
ca61edf2 L |
5931 | /* The address size override prefix changes the size of the |
5932 | first operand. */ | |
40fb9820 | 5933 | if ((flag_code == CODE_32BIT |
dc821c5f | 5934 | && i.op->regs[0].reg_type.bitfield.word) |
40fb9820 | 5935 | || (flag_code != CODE_32BIT |
dc821c5f | 5936 | && i.op->regs[0].reg_type.bitfield.dword)) |
cb712a9e L |
5937 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
5938 | return 0; | |
5939 | } | |
5940 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
5941 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
5942 | && !i.tm.opcode_modifier.ignoresize |
5943 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
5944 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
5945 | || (flag_code == CODE_64BIT | |
40fb9820 | 5946 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
5947 | { |
5948 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 5949 | |
40fb9820 | 5950 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 5951 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 5952 | |
29b0f896 AM |
5953 | if (!add_prefix (prefix)) |
5954 | return 0; | |
24eab124 | 5955 | } |
252b5132 | 5956 | |
29b0f896 AM |
5957 | /* Set mode64 for an operand. */ |
5958 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 5959 | && flag_code == CODE_64BIT |
40fb9820 | 5960 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
5961 | { |
5962 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
5963 | need rex64. cmpxchg8b is also a special case. */ |
5964 | if (! (i.operands == 2 | |
5965 | && i.tm.base_opcode == 0x90 | |
5966 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
5967 | && operand_type_equal (&i.types [0], &acc64) |
5968 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
5969 | && ! (i.operands == 1 |
5970 | && i.tm.base_opcode == 0xfc7 | |
5971 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
5972 | && !operand_type_check (i.types [0], reg) |
5973 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 5974 | i.rex |= REX_W; |
46e883c5 | 5975 | } |
3e73aa7c | 5976 | |
29b0f896 AM |
5977 | /* Size floating point instruction. */ |
5978 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 5979 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 5980 | i.tm.base_opcode ^= 4; |
29b0f896 | 5981 | } |
7ecd2f8b | 5982 | |
29b0f896 AM |
5983 | return 1; |
5984 | } | |
3e73aa7c | 5985 | |
29b0f896 | 5986 | static int |
543613e9 | 5987 | check_byte_reg (void) |
29b0f896 AM |
5988 | { |
5989 | int op; | |
543613e9 | 5990 | |
29b0f896 AM |
5991 | for (op = i.operands; --op >= 0;) |
5992 | { | |
dc821c5f JB |
5993 | /* Skip non-register operands. */ |
5994 | if (!i.types[op].bitfield.reg) | |
5995 | continue; | |
5996 | ||
29b0f896 AM |
5997 | /* If this is an eight bit register, it's OK. If it's the 16 or |
5998 | 32 bit version of an eight bit register, we will just use the | |
5999 | low portion, and that's OK too. */ | |
dc821c5f | 6000 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6001 | continue; |
6002 | ||
5a819eb9 JB |
6003 | /* I/O port address operands are OK too. */ |
6004 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6005 | continue; | |
6006 | ||
9344ff29 L |
6007 | /* crc32 doesn't generate this warning. */ |
6008 | if (i.tm.base_opcode == 0xf20f38f0) | |
6009 | continue; | |
6010 | ||
dc821c5f JB |
6011 | if ((i.types[op].bitfield.word |
6012 | || i.types[op].bitfield.dword | |
6013 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6014 | && i.op[op].regs->reg_num < 4 |
6015 | /* Prohibit these changes in 64bit mode, since the lowering | |
6016 | would be more complicated. */ | |
6017 | && flag_code != CODE_64BIT) | |
29b0f896 | 6018 | { |
29b0f896 | 6019 | #if REGISTER_WARNINGS |
5a819eb9 | 6020 | if (!quiet_warnings) |
a540244d L |
6021 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6022 | register_prefix, | |
dc821c5f | 6023 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6024 | ? REGNAM_AL - REGNAM_AX |
6025 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6026 | register_prefix, |
29b0f896 AM |
6027 | i.op[op].regs->reg_name, |
6028 | i.suffix); | |
6029 | #endif | |
6030 | continue; | |
6031 | } | |
6032 | /* Any other register is bad. */ | |
dc821c5f | 6033 | if (i.types[op].bitfield.reg |
40fb9820 | 6034 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6035 | || i.types[op].bitfield.regsimd |
40fb9820 L |
6036 | || i.types[op].bitfield.sreg2 |
6037 | || i.types[op].bitfield.sreg3 | |
6038 | || i.types[op].bitfield.control | |
6039 | || i.types[op].bitfield.debug | |
ca0d63fe | 6040 | || i.types[op].bitfield.test) |
29b0f896 | 6041 | { |
a540244d L |
6042 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6043 | register_prefix, | |
29b0f896 AM |
6044 | i.op[op].regs->reg_name, |
6045 | i.tm.name, | |
6046 | i.suffix); | |
6047 | return 0; | |
6048 | } | |
6049 | } | |
6050 | return 1; | |
6051 | } | |
6052 | ||
6053 | static int | |
e3bb37b5 | 6054 | check_long_reg (void) |
29b0f896 AM |
6055 | { |
6056 | int op; | |
6057 | ||
6058 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6059 | /* Skip non-register operands. */ |
6060 | if (!i.types[op].bitfield.reg) | |
6061 | continue; | |
29b0f896 AM |
6062 | /* Reject eight bit registers, except where the template requires |
6063 | them. (eg. movzb) */ | |
dc821c5f JB |
6064 | else if (i.types[op].bitfield.byte |
6065 | && (i.tm.operand_types[op].bitfield.reg | |
6066 | || i.tm.operand_types[op].bitfield.acc) | |
6067 | && (i.tm.operand_types[op].bitfield.word | |
6068 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6069 | { |
a540244d L |
6070 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6071 | register_prefix, | |
29b0f896 AM |
6072 | i.op[op].regs->reg_name, |
6073 | i.tm.name, | |
6074 | i.suffix); | |
6075 | return 0; | |
6076 | } | |
e4630f71 | 6077 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6078 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6079 | && i.types[op].bitfield.word |
6080 | && (i.tm.operand_types[op].bitfield.reg | |
6081 | || i.tm.operand_types[op].bitfield.acc) | |
6082 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6083 | { |
6084 | /* Prohibit these changes in the 64bit mode, since the | |
6085 | lowering is more complicated. */ | |
6086 | if (flag_code == CODE_64BIT) | |
252b5132 | 6087 | { |
2b5d6a91 | 6088 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6089 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6090 | i.suffix); |
6091 | return 0; | |
252b5132 | 6092 | } |
29b0f896 | 6093 | #if REGISTER_WARNINGS |
cecf1424 JB |
6094 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6095 | register_prefix, | |
6096 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6097 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6098 | #endif |
252b5132 | 6099 | } |
e4630f71 | 6100 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
6101 | else if (i.types[op].bitfield.qword |
6102 | && (i.tm.operand_types[op].bitfield.reg | |
6103 | || i.tm.operand_types[op].bitfield.acc) | |
6104 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6105 | { |
34828aad | 6106 | if (intel_syntax |
ca61edf2 | 6107 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 6108 | && !i.types[0].bitfield.regsimd) |
34828aad | 6109 | { |
ca61edf2 | 6110 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6111 | i.suffix = QWORD_MNEM_SUFFIX; |
6112 | } | |
6113 | else | |
6114 | { | |
2b5d6a91 | 6115 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6116 | register_prefix, i.op[op].regs->reg_name, |
6117 | i.suffix); | |
6118 | return 0; | |
6119 | } | |
29b0f896 AM |
6120 | } |
6121 | return 1; | |
6122 | } | |
252b5132 | 6123 | |
29b0f896 | 6124 | static int |
e3bb37b5 | 6125 | check_qword_reg (void) |
29b0f896 AM |
6126 | { |
6127 | int op; | |
252b5132 | 6128 | |
29b0f896 | 6129 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
6130 | /* Skip non-register operands. */ |
6131 | if (!i.types[op].bitfield.reg) | |
6132 | continue; | |
29b0f896 AM |
6133 | /* Reject eight bit registers, except where the template requires |
6134 | them. (eg. movzb) */ | |
dc821c5f JB |
6135 | else if (i.types[op].bitfield.byte |
6136 | && (i.tm.operand_types[op].bitfield.reg | |
6137 | || i.tm.operand_types[op].bitfield.acc) | |
6138 | && (i.tm.operand_types[op].bitfield.word | |
6139 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6140 | { |
a540244d L |
6141 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6142 | register_prefix, | |
29b0f896 AM |
6143 | i.op[op].regs->reg_name, |
6144 | i.tm.name, | |
6145 | i.suffix); | |
6146 | return 0; | |
6147 | } | |
e4630f71 | 6148 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6149 | else if ((i.types[op].bitfield.word |
6150 | || i.types[op].bitfield.dword) | |
6151 | && (i.tm.operand_types[op].bitfield.reg | |
6152 | || i.tm.operand_types[op].bitfield.acc) | |
6153 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6154 | { |
6155 | /* Prohibit these changes in the 64bit mode, since the | |
6156 | lowering is more complicated. */ | |
34828aad | 6157 | if (intel_syntax |
ca61edf2 | 6158 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 6159 | && !i.types[0].bitfield.regsimd) |
34828aad | 6160 | { |
ca61edf2 | 6161 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6162 | i.suffix = LONG_MNEM_SUFFIX; |
6163 | } | |
6164 | else | |
6165 | { | |
2b5d6a91 | 6166 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6167 | register_prefix, i.op[op].regs->reg_name, |
6168 | i.suffix); | |
6169 | return 0; | |
6170 | } | |
252b5132 | 6171 | } |
29b0f896 AM |
6172 | return 1; |
6173 | } | |
252b5132 | 6174 | |
29b0f896 | 6175 | static int |
e3bb37b5 | 6176 | check_word_reg (void) |
29b0f896 AM |
6177 | { |
6178 | int op; | |
6179 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6180 | /* Skip non-register operands. */ |
6181 | if (!i.types[op].bitfield.reg) | |
6182 | continue; | |
29b0f896 AM |
6183 | /* Reject eight bit registers, except where the template requires |
6184 | them. (eg. movzb) */ | |
dc821c5f JB |
6185 | else if (i.types[op].bitfield.byte |
6186 | && (i.tm.operand_types[op].bitfield.reg | |
6187 | || i.tm.operand_types[op].bitfield.acc) | |
6188 | && (i.tm.operand_types[op].bitfield.word | |
6189 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6190 | { |
a540244d L |
6191 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6192 | register_prefix, | |
29b0f896 AM |
6193 | i.op[op].regs->reg_name, |
6194 | i.tm.name, | |
6195 | i.suffix); | |
6196 | return 0; | |
6197 | } | |
e4630f71 | 6198 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6199 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6200 | && (i.types[op].bitfield.dword |
6201 | || i.types[op].bitfield.qword) | |
6202 | && (i.tm.operand_types[op].bitfield.reg | |
6203 | || i.tm.operand_types[op].bitfield.acc) | |
6204 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6205 | { |
29b0f896 AM |
6206 | /* Prohibit these changes in the 64bit mode, since the |
6207 | lowering is more complicated. */ | |
6208 | if (flag_code == CODE_64BIT) | |
252b5132 | 6209 | { |
2b5d6a91 | 6210 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6211 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6212 | i.suffix); |
6213 | return 0; | |
252b5132 | 6214 | } |
29b0f896 | 6215 | #if REGISTER_WARNINGS |
cecf1424 JB |
6216 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6217 | register_prefix, | |
6218 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6219 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6220 | #endif |
6221 | } | |
6222 | return 1; | |
6223 | } | |
252b5132 | 6224 | |
29b0f896 | 6225 | static int |
40fb9820 | 6226 | update_imm (unsigned int j) |
29b0f896 | 6227 | { |
bc0844ae | 6228 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6229 | if ((overlap.bitfield.imm8 |
6230 | || overlap.bitfield.imm8s | |
6231 | || overlap.bitfield.imm16 | |
6232 | || overlap.bitfield.imm32 | |
6233 | || overlap.bitfield.imm32s | |
6234 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6235 | && !operand_type_equal (&overlap, &imm8) |
6236 | && !operand_type_equal (&overlap, &imm8s) | |
6237 | && !operand_type_equal (&overlap, &imm16) | |
6238 | && !operand_type_equal (&overlap, &imm32) | |
6239 | && !operand_type_equal (&overlap, &imm32s) | |
6240 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6241 | { |
6242 | if (i.suffix) | |
6243 | { | |
40fb9820 L |
6244 | i386_operand_type temp; |
6245 | ||
0dfbf9d7 | 6246 | operand_type_set (&temp, 0); |
7ab9ffdd | 6247 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6248 | { |
6249 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6250 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6251 | } | |
6252 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6253 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6254 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6255 | { | |
6256 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6257 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6258 | } | |
6259 | else | |
6260 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6261 | overlap = temp; | |
29b0f896 | 6262 | } |
0dfbf9d7 L |
6263 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6264 | || operand_type_equal (&overlap, &imm16_32) | |
6265 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6266 | { |
40fb9820 | 6267 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6268 | overlap = imm16; |
40fb9820 | 6269 | else |
65da13b5 | 6270 | overlap = imm32s; |
29b0f896 | 6271 | } |
0dfbf9d7 L |
6272 | if (!operand_type_equal (&overlap, &imm8) |
6273 | && !operand_type_equal (&overlap, &imm8s) | |
6274 | && !operand_type_equal (&overlap, &imm16) | |
6275 | && !operand_type_equal (&overlap, &imm32) | |
6276 | && !operand_type_equal (&overlap, &imm32s) | |
6277 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6278 | { |
4eed87de AM |
6279 | as_bad (_("no instruction mnemonic suffix given; " |
6280 | "can't determine immediate size")); | |
29b0f896 AM |
6281 | return 0; |
6282 | } | |
6283 | } | |
40fb9820 | 6284 | i.types[j] = overlap; |
29b0f896 | 6285 | |
40fb9820 L |
6286 | return 1; |
6287 | } | |
6288 | ||
6289 | static int | |
6290 | finalize_imm (void) | |
6291 | { | |
bc0844ae | 6292 | unsigned int j, n; |
29b0f896 | 6293 | |
bc0844ae L |
6294 | /* Update the first 2 immediate operands. */ |
6295 | n = i.operands > 2 ? 2 : i.operands; | |
6296 | if (n) | |
6297 | { | |
6298 | for (j = 0; j < n; j++) | |
6299 | if (update_imm (j) == 0) | |
6300 | return 0; | |
40fb9820 | 6301 | |
bc0844ae L |
6302 | /* The 3rd operand can't be immediate operand. */ |
6303 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6304 | } | |
29b0f896 AM |
6305 | |
6306 | return 1; | |
6307 | } | |
6308 | ||
6309 | static int | |
e3bb37b5 | 6310 | process_operands (void) |
29b0f896 AM |
6311 | { |
6312 | /* Default segment register this instruction will use for memory | |
6313 | accesses. 0 means unknown. This is only for optimizing out | |
6314 | unnecessary segment overrides. */ | |
6315 | const seg_entry *default_seg = 0; | |
6316 | ||
2426c15f | 6317 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6318 | { |
91d6fa6a NC |
6319 | unsigned int dupl = i.operands; |
6320 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6321 | unsigned int j; |
6322 | ||
c0f3af97 | 6323 | /* The destination must be an xmm register. */ |
9c2799c2 | 6324 | gas_assert (i.reg_operands |
91d6fa6a | 6325 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6326 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6327 | |
1b54b8d7 JB |
6328 | if (i.tm.operand_types[0].bitfield.acc |
6329 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6330 | { |
8cd7925b | 6331 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6332 | { |
6333 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6334 | sources. */ | |
1b54b8d7 JB |
6335 | i.tm.operand_types[0].bitfield.acc = 0; |
6336 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6337 | goto duplicate; |
6338 | } | |
e2ec9d29 | 6339 | else |
c0f3af97 L |
6340 | { |
6341 | /* We remove the first xmm0 and keep the number of | |
6342 | operands unchanged, which in fact duplicates the | |
6343 | destination. */ | |
6344 | for (j = 1; j < i.operands; j++) | |
6345 | { | |
6346 | i.op[j - 1] = i.op[j]; | |
6347 | i.types[j - 1] = i.types[j]; | |
6348 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6349 | } | |
6350 | } | |
6351 | } | |
6352 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6353 | { |
91d6fa6a | 6354 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6355 | && (i.tm.opcode_modifier.vexsources |
6356 | == VEX3SOURCES)); | |
c0f3af97 L |
6357 | |
6358 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6359 | and 3 sources. */ | |
6360 | for (j = i.operands; j > 0; j--) | |
6361 | { | |
6362 | i.op[j] = i.op[j - 1]; | |
6363 | i.types[j] = i.types[j - 1]; | |
6364 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6365 | } | |
6366 | i.op[0].regs | |
6367 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6368 | i.types[0] = regxmm; |
c0f3af97 L |
6369 | i.tm.operand_types[0] = regxmm; |
6370 | ||
6371 | i.operands += 2; | |
6372 | i.reg_operands += 2; | |
6373 | i.tm.operands += 2; | |
6374 | ||
91d6fa6a | 6375 | dupl++; |
c0f3af97 | 6376 | dest++; |
91d6fa6a NC |
6377 | i.op[dupl] = i.op[dest]; |
6378 | i.types[dupl] = i.types[dest]; | |
6379 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6380 | } |
c0f3af97 L |
6381 | else |
6382 | { | |
6383 | duplicate: | |
6384 | i.operands++; | |
6385 | i.reg_operands++; | |
6386 | i.tm.operands++; | |
6387 | ||
91d6fa6a NC |
6388 | i.op[dupl] = i.op[dest]; |
6389 | i.types[dupl] = i.types[dest]; | |
6390 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6391 | } |
6392 | ||
6393 | if (i.tm.opcode_modifier.immext) | |
6394 | process_immext (); | |
6395 | } | |
1b54b8d7 JB |
6396 | else if (i.tm.operand_types[0].bitfield.acc |
6397 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6398 | { |
6399 | unsigned int j; | |
6400 | ||
9fcfb3d7 L |
6401 | for (j = 1; j < i.operands; j++) |
6402 | { | |
6403 | i.op[j - 1] = i.op[j]; | |
6404 | i.types[j - 1] = i.types[j]; | |
6405 | ||
6406 | /* We need to adjust fields in i.tm since they are used by | |
6407 | build_modrm_byte. */ | |
6408 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6409 | } | |
6410 | ||
e2ec9d29 L |
6411 | i.operands--; |
6412 | i.reg_operands--; | |
e2ec9d29 L |
6413 | i.tm.operands--; |
6414 | } | |
920d2ddc IT |
6415 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6416 | { | |
6417 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ | |
10c17abd | 6418 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
920d2ddc IT |
6419 | unsigned int regnum = register_number (i.op[1].regs); |
6420 | unsigned int first_reg_in_group = regnum & ~3; | |
6421 | unsigned int last_reg_in_group = first_reg_in_group + 3; | |
6422 | if (regnum != first_reg_in_group) { | |
6423 | as_warn (_("the second source register `%s%s' implicitly denotes" | |
6424 | " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"), | |
6425 | register_prefix, i.op[1].regs->reg_name, | |
6426 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6427 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6428 | i.tm.name); | |
6429 | } | |
6430 | } | |
e2ec9d29 L |
6431 | else if (i.tm.opcode_modifier.regkludge) |
6432 | { | |
6433 | /* The imul $imm, %reg instruction is converted into | |
6434 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6435 | is converted into xor %reg, %reg. */ | |
6436 | ||
6437 | unsigned int first_reg_op; | |
6438 | ||
6439 | if (operand_type_check (i.types[0], reg)) | |
6440 | first_reg_op = 0; | |
6441 | else | |
6442 | first_reg_op = 1; | |
6443 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6444 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6445 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6446 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6447 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6448 | i.operands++; | |
6449 | i.reg_operands++; | |
29b0f896 AM |
6450 | } |
6451 | ||
40fb9820 | 6452 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6453 | { |
40fb9820 L |
6454 | if (i.types[0].bitfield.sreg2 |
6455 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6456 | { |
4eed87de AM |
6457 | if (i.tm.base_opcode == POP_SEG_SHORT |
6458 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6459 | { |
a87af027 | 6460 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6461 | return 0; |
29b0f896 | 6462 | } |
4eed87de AM |
6463 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6464 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6465 | i.rex |= REX_B; |
4eed87de AM |
6466 | } |
6467 | else | |
6468 | { | |
7ab9ffdd | 6469 | /* The register or float register operand is in operand |
85f10a01 | 6470 | 0 or 1. */ |
40fb9820 | 6471 | unsigned int op; |
7ab9ffdd | 6472 | |
ca0d63fe | 6473 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6474 | || operand_type_check (i.types[0], reg)) |
6475 | op = 0; | |
6476 | else | |
6477 | op = 1; | |
4eed87de AM |
6478 | /* Register goes in low 3 bits of opcode. */ |
6479 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6480 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6481 | i.rex |= REX_B; |
40fb9820 | 6482 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6483 | { |
4eed87de AM |
6484 | /* Warn about some common errors, but press on regardless. |
6485 | The first case can be generated by gcc (<= 2.8.1). */ | |
6486 | if (i.operands == 2) | |
6487 | { | |
6488 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6489 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6490 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6491 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6492 | } |
6493 | else | |
6494 | { | |
6495 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6496 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6497 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6498 | } |
29b0f896 AM |
6499 | } |
6500 | } | |
6501 | } | |
40fb9820 | 6502 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6503 | { |
6504 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6505 | must be put into the modrm byte). Now, we make the modrm and |
6506 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6507 | |
6508 | default_seg = build_modrm_byte (); | |
6509 | } | |
8a2ed489 | 6510 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6511 | { |
6512 | default_seg = &ds; | |
6513 | } | |
40fb9820 | 6514 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6515 | { |
6516 | /* For the string instructions that allow a segment override | |
6517 | on one of their operands, the default segment is ds. */ | |
6518 | default_seg = &ds; | |
6519 | } | |
6520 | ||
75178d9d L |
6521 | if (i.tm.base_opcode == 0x8d /* lea */ |
6522 | && i.seg[0] | |
6523 | && !quiet_warnings) | |
30123838 | 6524 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6525 | |
6526 | /* If a segment was explicitly specified, and the specified segment | |
6527 | is not the default, use an opcode prefix to select it. If we | |
6528 | never figured out what the default segment is, then default_seg | |
6529 | will be zero at this point, and the specified segment prefix will | |
6530 | always be used. */ | |
29b0f896 AM |
6531 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6532 | { | |
6533 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6534 | return 0; | |
6535 | } | |
6536 | return 1; | |
6537 | } | |
6538 | ||
6539 | static const seg_entry * | |
e3bb37b5 | 6540 | build_modrm_byte (void) |
29b0f896 AM |
6541 | { |
6542 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6543 | unsigned int source, dest; |
8cd7925b | 6544 | int vex_3_sources; |
c0f3af97 L |
6545 | |
6546 | /* The first operand of instructions with VEX prefix and 3 sources | |
6547 | must be VEX_Imm4. */ | |
8cd7925b | 6548 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6549 | if (vex_3_sources) |
6550 | { | |
91d6fa6a | 6551 | unsigned int nds, reg_slot; |
4c2c6516 | 6552 | expressionS *exp; |
c0f3af97 | 6553 | |
922d8de8 | 6554 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
6555 | && i.tm.opcode_modifier.immext) |
6556 | { | |
6557 | dest = i.operands - 2; | |
6558 | gas_assert (dest == 3); | |
6559 | } | |
922d8de8 | 6560 | else |
a683cc34 | 6561 | dest = i.operands - 1; |
c0f3af97 | 6562 | nds = dest - 1; |
922d8de8 | 6563 | |
a683cc34 SP |
6564 | /* There are 2 kinds of instructions: |
6565 | 1. 5 operands: 4 register operands or 3 register operands | |
6566 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
43234a1e L |
6567 | VexW0 or VexW1. The destination must be either XMM, YMM or |
6568 | ZMM register. | |
a683cc34 SP |
6569 | 2. 4 operands: 4 register operands or 3 register operands |
6570 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 6571 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
6572 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6573 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
6574 | && (i.tm.opcode_modifier.veximmext | |
6575 | || (i.imm_operands == 1 | |
6576 | && i.types[0].bitfield.vec_imm4 | |
6577 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
6578 | || i.tm.opcode_modifier.vexw == VEXW1) | |
10c17abd | 6579 | && i.tm.operand_types[dest].bitfield.regsimd))); |
a683cc34 SP |
6580 | |
6581 | if (i.imm_operands == 0) | |
6582 | { | |
6583 | /* When there is no immediate operand, generate an 8bit | |
6584 | immediate operand to encode the first operand. */ | |
6585 | exp = &im_expressions[i.imm_operands++]; | |
6586 | i.op[i.operands].imms = exp; | |
6587 | i.types[i.operands] = imm8; | |
6588 | i.operands++; | |
6589 | /* If VexW1 is set, the first operand is the source and | |
6590 | the second operand is encoded in the immediate operand. */ | |
6591 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6592 | { | |
6593 | source = 0; | |
6594 | reg_slot = 1; | |
6595 | } | |
6596 | else | |
6597 | { | |
6598 | source = 1; | |
6599 | reg_slot = 0; | |
6600 | } | |
6601 | ||
6602 | /* FMA swaps REG and NDS. */ | |
6603 | if (i.tm.cpu_flags.bitfield.cpufma) | |
6604 | { | |
6605 | unsigned int tmp; | |
6606 | tmp = reg_slot; | |
6607 | reg_slot = nds; | |
6608 | nds = tmp; | |
6609 | } | |
6610 | ||
10c17abd | 6611 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6612 | exp->X_op = O_constant; |
4c692bc7 | 6613 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
43234a1e L |
6614 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6615 | } | |
922d8de8 | 6616 | else |
a683cc34 SP |
6617 | { |
6618 | unsigned int imm_slot; | |
6619 | ||
6620 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
6621 | { | |
6622 | /* If VexW0 is set, the third operand is the source and | |
6623 | the second operand is encoded in the immediate | |
6624 | operand. */ | |
6625 | source = 2; | |
6626 | reg_slot = 1; | |
6627 | } | |
6628 | else | |
6629 | { | |
6630 | /* VexW1 is set, the second operand is the source and | |
6631 | the third operand is encoded in the immediate | |
6632 | operand. */ | |
6633 | source = 1; | |
6634 | reg_slot = 2; | |
6635 | } | |
6636 | ||
6637 | if (i.tm.opcode_modifier.immext) | |
6638 | { | |
33eaf5de | 6639 | /* When ImmExt is set, the immediate byte is the last |
a683cc34 SP |
6640 | operand. */ |
6641 | imm_slot = i.operands - 1; | |
6642 | source--; | |
6643 | reg_slot--; | |
6644 | } | |
6645 | else | |
6646 | { | |
6647 | imm_slot = 0; | |
6648 | ||
6649 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6650 | i.types[imm_slot].bitfield.imm8 = 1; | |
6651 | } | |
6652 | ||
10c17abd | 6653 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6654 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 6655 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 6656 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
a683cc34 SP |
6657 | } |
6658 | ||
10c17abd | 6659 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 6660 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6661 | } |
6662 | else | |
6663 | source = dest = 0; | |
29b0f896 AM |
6664 | |
6665 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6666 | implicit registers do not count. If there are 3 register |
6667 | operands, it must be a instruction with VexNDS. For a | |
6668 | instruction with VexNDD, the destination register is encoded | |
6669 | in VEX prefix. If there are 4 register operands, it must be | |
6670 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6671 | if (i.mem_operands == 0 |
6672 | && ((i.reg_operands == 2 | |
2426c15f | 6673 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6674 | || (i.reg_operands == 3 |
2426c15f | 6675 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6676 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6677 | { |
cab737b9 L |
6678 | switch (i.operands) |
6679 | { | |
6680 | case 2: | |
6681 | source = 0; | |
6682 | break; | |
6683 | case 3: | |
c81128dc L |
6684 | /* When there are 3 operands, one of them may be immediate, |
6685 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6686 | the first operand must be shift count register (cl) or it |
6687 | is an instruction with VexNDS. */ | |
9c2799c2 | 6688 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6689 | || (i.imm_operands == 0 |
2426c15f | 6690 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6691 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6692 | if (operand_type_check (i.types[0], imm) |
6693 | || i.types[0].bitfield.shiftcount) | |
6694 | source = 1; | |
6695 | else | |
6696 | source = 0; | |
cab737b9 L |
6697 | break; |
6698 | case 4: | |
368d64cc L |
6699 | /* When there are 4 operands, the first two must be 8bit |
6700 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6701 | one. |
6702 | ||
6703 | For instructions with VexNDS, if the first operand | |
6704 | an imm8, the source operand is the 2nd one. If the last | |
6705 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6706 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6707 | && i.types[0].bitfield.imm8 |
6708 | && i.types[1].bitfield.imm8) | |
2426c15f | 6709 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6710 | && i.imm_operands == 1 |
6711 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6712 | || i.types[i.operands - 1].bitfield.imm8 |
6713 | || i.rounding))); | |
9f2670f2 L |
6714 | if (i.imm_operands == 2) |
6715 | source = 2; | |
6716 | else | |
c0f3af97 L |
6717 | { |
6718 | if (i.types[0].bitfield.imm8) | |
6719 | source = 1; | |
6720 | else | |
6721 | source = 0; | |
6722 | } | |
c0f3af97 L |
6723 | break; |
6724 | case 5: | |
43234a1e L |
6725 | if (i.tm.opcode_modifier.evex) |
6726 | { | |
6727 | /* For EVEX instructions, when there are 5 operands, the | |
6728 | first one must be immediate operand. If the second one | |
6729 | is immediate operand, the source operand is the 3th | |
6730 | one. If the last one is immediate operand, the source | |
6731 | operand is the 2nd one. */ | |
6732 | gas_assert (i.imm_operands == 2 | |
6733 | && i.tm.opcode_modifier.sae | |
6734 | && operand_type_check (i.types[0], imm)); | |
6735 | if (operand_type_check (i.types[1], imm)) | |
6736 | source = 2; | |
6737 | else if (operand_type_check (i.types[4], imm)) | |
6738 | source = 1; | |
6739 | else | |
6740 | abort (); | |
6741 | } | |
cab737b9 L |
6742 | break; |
6743 | default: | |
6744 | abort (); | |
6745 | } | |
6746 | ||
c0f3af97 L |
6747 | if (!vex_3_sources) |
6748 | { | |
6749 | dest = source + 1; | |
6750 | ||
43234a1e L |
6751 | /* RC/SAE operand could be between DEST and SRC. That happens |
6752 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6753 | register. */ | |
6754 | if (i.rounding && i.rounding->operand == (int) dest) | |
6755 | dest++; | |
6756 | ||
2426c15f | 6757 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6758 | { |
43234a1e | 6759 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 6760 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
6761 | register. It is encoded in VEX prefix. We need to |
6762 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6763 | |
6764 | i386_operand_type op; | |
6765 | unsigned int vvvv; | |
6766 | ||
6767 | /* Check register-only source operand when two source | |
6768 | operands are swapped. */ | |
6769 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6770 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6771 | { | |
6772 | vvvv = source; | |
6773 | source = dest; | |
6774 | } | |
6775 | else | |
6776 | vvvv = dest; | |
6777 | ||
6778 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6779 | op.bitfield.regmem = 0; |
c0f3af97 | 6780 | if ((dest + 1) >= i.operands |
dc821c5f JB |
6781 | || ((!op.bitfield.reg |
6782 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 6783 | && !op.bitfield.regsimd |
43234a1e | 6784 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 6785 | abort (); |
f12dc422 | 6786 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6787 | dest++; |
6788 | } | |
6789 | } | |
29b0f896 AM |
6790 | |
6791 | i.rm.mode = 3; | |
6792 | /* One of the register operands will be encoded in the i.tm.reg | |
6793 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6794 | fields. If no form of this instruction supports a memory | |
6795 | destination operand, then we assume the source operand may | |
6796 | sometimes be a memory operand and so we need to store the | |
6797 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6798 | if (!i.tm.operand_types[dest].bitfield.regmem |
6799 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6800 | { |
6801 | i.rm.reg = i.op[dest].regs->reg_num; | |
6802 | i.rm.regmem = i.op[source].regs->reg_num; | |
6803 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6804 | i.rex |= REX_R; |
43234a1e L |
6805 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6806 | i.vrex |= REX_R; | |
29b0f896 | 6807 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6808 | i.rex |= REX_B; |
43234a1e L |
6809 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6810 | i.vrex |= REX_B; | |
29b0f896 AM |
6811 | } |
6812 | else | |
6813 | { | |
6814 | i.rm.reg = i.op[source].regs->reg_num; | |
6815 | i.rm.regmem = i.op[dest].regs->reg_num; | |
6816 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6817 | i.rex |= REX_B; |
43234a1e L |
6818 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6819 | i.vrex |= REX_B; | |
29b0f896 | 6820 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6821 | i.rex |= REX_R; |
43234a1e L |
6822 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6823 | i.vrex |= REX_R; | |
29b0f896 | 6824 | } |
161a04f6 | 6825 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 6826 | { |
40fb9820 L |
6827 | if (!i.types[0].bitfield.control |
6828 | && !i.types[1].bitfield.control) | |
c4a530c5 | 6829 | abort (); |
161a04f6 | 6830 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
6831 | add_prefix (LOCK_PREFIX_OPCODE); |
6832 | } | |
29b0f896 AM |
6833 | } |
6834 | else | |
6835 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
6836 | unsigned int mem; |
6837 | ||
29b0f896 AM |
6838 | if (i.mem_operands) |
6839 | { | |
6840 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 6841 | unsigned int op; |
4eed87de | 6842 | |
7ab9ffdd L |
6843 | for (op = 0; op < i.operands; op++) |
6844 | if (operand_type_check (i.types[op], anymem)) | |
6845 | break; | |
7ab9ffdd | 6846 | gas_assert (op < i.operands); |
29b0f896 | 6847 | |
6c30d220 L |
6848 | if (i.tm.opcode_modifier.vecsib) |
6849 | { | |
6850 | if (i.index_reg->reg_num == RegEiz | |
6851 | || i.index_reg->reg_num == RegRiz) | |
6852 | abort (); | |
6853 | ||
6854 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6855 | if (!i.base_reg) | |
6856 | { | |
6857 | i.sib.base = NO_BASE_REGISTER; | |
6858 | i.sib.scale = i.log2_scale_factor; | |
6859 | i.types[op].bitfield.disp8 = 0; | |
6860 | i.types[op].bitfield.disp16 = 0; | |
6861 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6862 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
6863 | { |
6864 | /* Must be 32 bit */ | |
6865 | i.types[op].bitfield.disp32 = 1; | |
6866 | i.types[op].bitfield.disp32s = 0; | |
6867 | } | |
6868 | else | |
6869 | { | |
6870 | i.types[op].bitfield.disp32 = 0; | |
6871 | i.types[op].bitfield.disp32s = 1; | |
6872 | } | |
6873 | } | |
6874 | i.sib.index = i.index_reg->reg_num; | |
6875 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
6876 | i.rex |= REX_X; | |
43234a1e L |
6877 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
6878 | i.vrex |= REX_X; | |
6c30d220 L |
6879 | } |
6880 | ||
29b0f896 AM |
6881 | default_seg = &ds; |
6882 | ||
6883 | if (i.base_reg == 0) | |
6884 | { | |
6885 | i.rm.mode = 0; | |
6886 | if (!i.disp_operands) | |
9bb129e8 | 6887 | fake_zero_displacement = 1; |
29b0f896 AM |
6888 | if (i.index_reg == 0) |
6889 | { | |
73053c1f JB |
6890 | i386_operand_type newdisp; |
6891 | ||
6c30d220 | 6892 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6893 | /* Operand is just <disp> */ |
20f0a1fc | 6894 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
6895 | { |
6896 | /* 64bit mode overwrites the 32bit absolute | |
6897 | addressing by RIP relative addressing and | |
6898 | absolute addressing is encoded by one of the | |
6899 | redundant SIB forms. */ | |
6900 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6901 | i.sib.base = NO_BASE_REGISTER; | |
6902 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 6903 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 6904 | } |
fc225355 L |
6905 | else if ((flag_code == CODE_16BIT) |
6906 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
6907 | { |
6908 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 6909 | newdisp = disp16; |
20f0a1fc NC |
6910 | } |
6911 | else | |
6912 | { | |
6913 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 6914 | newdisp = disp32; |
29b0f896 | 6915 | } |
73053c1f JB |
6916 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
6917 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 6918 | } |
6c30d220 | 6919 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6920 | { |
6c30d220 | 6921 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
6922 | if (i.index_reg->reg_num == RegEiz |
6923 | || i.index_reg->reg_num == RegRiz) | |
6924 | i.sib.index = NO_INDEX_REGISTER; | |
6925 | else | |
6926 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6927 | i.sib.base = NO_BASE_REGISTER; |
6928 | i.sib.scale = i.log2_scale_factor; | |
6929 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
6930 | i.types[op].bitfield.disp8 = 0; |
6931 | i.types[op].bitfield.disp16 = 0; | |
6932 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6933 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
6934 | { |
6935 | /* Must be 32 bit */ | |
6936 | i.types[op].bitfield.disp32 = 1; | |
6937 | i.types[op].bitfield.disp32s = 0; | |
6938 | } | |
29b0f896 | 6939 | else |
40fb9820 L |
6940 | { |
6941 | i.types[op].bitfield.disp32 = 0; | |
6942 | i.types[op].bitfield.disp32s = 1; | |
6943 | } | |
29b0f896 | 6944 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6945 | i.rex |= REX_X; |
29b0f896 AM |
6946 | } |
6947 | } | |
6948 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
6949 | else if (i.base_reg->reg_num == RegRip || |
6950 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 6951 | { |
6c30d220 | 6952 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6953 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
6954 | i.types[op].bitfield.disp8 = 0; |
6955 | i.types[op].bitfield.disp16 = 0; | |
6956 | i.types[op].bitfield.disp32 = 0; | |
6957 | i.types[op].bitfield.disp32s = 1; | |
6958 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 6959 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
6960 | if (! i.disp_operands) |
6961 | fake_zero_displacement = 1; | |
29b0f896 | 6962 | } |
dc821c5f | 6963 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 6964 | { |
6c30d220 | 6965 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6966 | switch (i.base_reg->reg_num) |
6967 | { | |
6968 | case 3: /* (%bx) */ | |
6969 | if (i.index_reg == 0) | |
6970 | i.rm.regmem = 7; | |
6971 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
6972 | i.rm.regmem = i.index_reg->reg_num - 6; | |
6973 | break; | |
6974 | case 5: /* (%bp) */ | |
6975 | default_seg = &ss; | |
6976 | if (i.index_reg == 0) | |
6977 | { | |
6978 | i.rm.regmem = 6; | |
40fb9820 | 6979 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
6980 | { |
6981 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 6982 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 6983 | fake_zero_displacement = 1; |
29b0f896 AM |
6984 | } |
6985 | } | |
6986 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
6987 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
6988 | break; | |
6989 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
6990 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
6991 | } | |
6992 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6993 | } | |
6994 | else /* i.base_reg and 32/64 bit mode */ | |
6995 | { | |
6996 | if (flag_code == CODE_64BIT | |
40fb9820 L |
6997 | && operand_type_check (i.types[op], disp)) |
6998 | { | |
73053c1f JB |
6999 | i.types[op].bitfield.disp16 = 0; |
7000 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7001 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7002 | { |
7003 | i.types[op].bitfield.disp32 = 0; | |
7004 | i.types[op].bitfield.disp32s = 1; | |
7005 | } | |
40fb9820 | 7006 | else |
73053c1f JB |
7007 | { |
7008 | i.types[op].bitfield.disp32 = 1; | |
7009 | i.types[op].bitfield.disp32s = 0; | |
7010 | } | |
40fb9820 | 7011 | } |
20f0a1fc | 7012 | |
6c30d220 L |
7013 | if (!i.tm.opcode_modifier.vecsib) |
7014 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7015 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7016 | i.rex |= REX_B; |
29b0f896 AM |
7017 | i.sib.base = i.base_reg->reg_num; |
7018 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7019 | complications. */ | |
848930b2 JB |
7020 | if (!(i.base_reg->reg_flags & RegRex) |
7021 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7022 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7023 | default_seg = &ss; |
848930b2 | 7024 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7025 | { |
848930b2 | 7026 | fake_zero_displacement = 1; |
b5014f7a | 7027 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7028 | } |
7029 | i.sib.scale = i.log2_scale_factor; | |
7030 | if (i.index_reg == 0) | |
7031 | { | |
6c30d220 | 7032 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7033 | /* <disp>(%esp) becomes two byte modrm with no index |
7034 | register. We've already stored the code for esp | |
7035 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7036 | Any base register besides %esp will not use the | |
7037 | extra modrm byte. */ | |
7038 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7039 | } |
6c30d220 | 7040 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7041 | { |
db51cc60 L |
7042 | if (i.index_reg->reg_num == RegEiz |
7043 | || i.index_reg->reg_num == RegRiz) | |
7044 | i.sib.index = NO_INDEX_REGISTER; | |
7045 | else | |
7046 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7047 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7048 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7049 | i.rex |= REX_X; |
29b0f896 | 7050 | } |
67a4f2b7 AO |
7051 | |
7052 | if (i.disp_operands | |
7053 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7054 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7055 | i.rm.mode = 0; | |
7056 | else | |
a501d77e L |
7057 | { |
7058 | if (!fake_zero_displacement | |
7059 | && !i.disp_operands | |
7060 | && i.disp_encoding) | |
7061 | { | |
7062 | fake_zero_displacement = 1; | |
7063 | if (i.disp_encoding == disp_encoding_8bit) | |
7064 | i.types[op].bitfield.disp8 = 1; | |
7065 | else | |
7066 | i.types[op].bitfield.disp32 = 1; | |
7067 | } | |
7068 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7069 | } | |
29b0f896 | 7070 | } |
252b5132 | 7071 | |
29b0f896 AM |
7072 | if (fake_zero_displacement) |
7073 | { | |
7074 | /* Fakes a zero displacement assuming that i.types[op] | |
7075 | holds the correct displacement size. */ | |
7076 | expressionS *exp; | |
7077 | ||
9c2799c2 | 7078 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7079 | exp = &disp_expressions[i.disp_operands++]; |
7080 | i.op[op].disps = exp; | |
7081 | exp->X_op = O_constant; | |
7082 | exp->X_add_number = 0; | |
7083 | exp->X_add_symbol = (symbolS *) 0; | |
7084 | exp->X_op_symbol = (symbolS *) 0; | |
7085 | } | |
c0f3af97 L |
7086 | |
7087 | mem = op; | |
29b0f896 | 7088 | } |
c0f3af97 L |
7089 | else |
7090 | mem = ~0; | |
252b5132 | 7091 | |
8c43a48b | 7092 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7093 | { |
7094 | if (operand_type_check (i.types[0], imm)) | |
7095 | i.vex.register_specifier = NULL; | |
7096 | else | |
7097 | { | |
7098 | /* VEX.vvvv encodes one of the sources when the first | |
7099 | operand is not an immediate. */ | |
1ef99a7b | 7100 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7101 | i.vex.register_specifier = i.op[0].regs; |
7102 | else | |
7103 | i.vex.register_specifier = i.op[1].regs; | |
7104 | } | |
7105 | ||
7106 | /* Destination is a XMM register encoded in the ModRM.reg | |
7107 | and VEX.R bit. */ | |
7108 | i.rm.reg = i.op[2].regs->reg_num; | |
7109 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7110 | i.rex |= REX_R; | |
7111 | ||
7112 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7113 | if (!i.mem_operands) | |
7114 | { | |
7115 | i.rm.mode = 3; | |
7116 | ||
1ef99a7b | 7117 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7118 | i.rm.regmem = i.op[1].regs->reg_num; |
7119 | else | |
7120 | i.rm.regmem = i.op[0].regs->reg_num; | |
7121 | ||
7122 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7123 | i.rex |= REX_B; | |
7124 | } | |
7125 | } | |
2426c15f | 7126 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7127 | { |
7128 | i.vex.register_specifier = i.op[2].regs; | |
7129 | if (!i.mem_operands) | |
7130 | { | |
7131 | i.rm.mode = 3; | |
7132 | i.rm.regmem = i.op[1].regs->reg_num; | |
7133 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7134 | i.rex |= REX_B; | |
7135 | } | |
7136 | } | |
29b0f896 AM |
7137 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7138 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7139 | careful to make sure that segment/control/debug/test/MMX | |
7140 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7141 | else if (i.reg_operands) |
29b0f896 | 7142 | { |
99018f42 | 7143 | unsigned int op; |
7ab9ffdd L |
7144 | unsigned int vex_reg = ~0; |
7145 | ||
7146 | for (op = 0; op < i.operands; op++) | |
dc821c5f | 7147 | if (i.types[op].bitfield.reg |
7ab9ffdd | 7148 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 7149 | || i.types[op].bitfield.regsimd |
7e8b059b | 7150 | || i.types[op].bitfield.regbnd |
43234a1e | 7151 | || i.types[op].bitfield.regmask |
7ab9ffdd L |
7152 | || i.types[op].bitfield.sreg2 |
7153 | || i.types[op].bitfield.sreg3 | |
7154 | || i.types[op].bitfield.control | |
7155 | || i.types[op].bitfield.debug | |
7156 | || i.types[op].bitfield.test) | |
7157 | break; | |
c0209578 | 7158 | |
7ab9ffdd L |
7159 | if (vex_3_sources) |
7160 | op = dest; | |
2426c15f | 7161 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7162 | { |
7163 | /* For instructions with VexNDS, the register-only | |
7164 | source operand is encoded in VEX prefix. */ | |
7165 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7166 | |
7ab9ffdd | 7167 | if (op > mem) |
c0f3af97 | 7168 | { |
7ab9ffdd L |
7169 | vex_reg = op++; |
7170 | gas_assert (op < i.operands); | |
c0f3af97 L |
7171 | } |
7172 | else | |
c0f3af97 | 7173 | { |
f12dc422 L |
7174 | /* Check register-only source operand when two source |
7175 | operands are swapped. */ | |
7176 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7177 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7178 | { | |
7179 | vex_reg = op; | |
7180 | op += 2; | |
7181 | gas_assert (mem == (vex_reg + 1) | |
7182 | && op < i.operands); | |
7183 | } | |
7184 | else | |
7185 | { | |
7186 | vex_reg = op + 1; | |
7187 | gas_assert (vex_reg < i.operands); | |
7188 | } | |
c0f3af97 | 7189 | } |
7ab9ffdd | 7190 | } |
2426c15f | 7191 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7192 | { |
f12dc422 | 7193 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7194 | is encoded in VEX prefix. */ |
f12dc422 L |
7195 | if (i.mem_operands == 0) |
7196 | { | |
7197 | /* There is no memory operand. */ | |
7198 | gas_assert ((op + 2) == i.operands); | |
7199 | vex_reg = op + 1; | |
7200 | } | |
7201 | else | |
8d63c93e | 7202 | { |
f12dc422 L |
7203 | /* There are only 2 operands. */ |
7204 | gas_assert (op < 2 && i.operands == 2); | |
7205 | vex_reg = 1; | |
7206 | } | |
7ab9ffdd L |
7207 | } |
7208 | else | |
7209 | gas_assert (op < i.operands); | |
99018f42 | 7210 | |
7ab9ffdd L |
7211 | if (vex_reg != (unsigned int) ~0) |
7212 | { | |
f12dc422 | 7213 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7214 | |
dc821c5f JB |
7215 | if ((!type->bitfield.reg |
7216 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 7217 | && !type->bitfield.regsimd |
43234a1e | 7218 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7219 | abort (); |
f88c9eb0 | 7220 | |
7ab9ffdd L |
7221 | i.vex.register_specifier = i.op[vex_reg].regs; |
7222 | } | |
7223 | ||
1b9f0c97 L |
7224 | /* Don't set OP operand twice. */ |
7225 | if (vex_reg != op) | |
7ab9ffdd | 7226 | { |
1b9f0c97 L |
7227 | /* If there is an extension opcode to put here, the |
7228 | register number must be put into the regmem field. */ | |
7229 | if (i.tm.extension_opcode != None) | |
7230 | { | |
7231 | i.rm.regmem = i.op[op].regs->reg_num; | |
7232 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7233 | i.rex |= REX_B; | |
43234a1e L |
7234 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7235 | i.vrex |= REX_B; | |
1b9f0c97 L |
7236 | } |
7237 | else | |
7238 | { | |
7239 | i.rm.reg = i.op[op].regs->reg_num; | |
7240 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7241 | i.rex |= REX_R; | |
43234a1e L |
7242 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7243 | i.vrex |= REX_R; | |
1b9f0c97 | 7244 | } |
7ab9ffdd | 7245 | } |
252b5132 | 7246 | |
29b0f896 AM |
7247 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7248 | must set it to 3 to indicate this is a register operand | |
7249 | in the regmem field. */ | |
7250 | if (!i.mem_operands) | |
7251 | i.rm.mode = 3; | |
7252 | } | |
252b5132 | 7253 | |
29b0f896 | 7254 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7255 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7256 | i.rm.reg = i.tm.extension_opcode; |
7257 | } | |
7258 | return default_seg; | |
7259 | } | |
252b5132 | 7260 | |
29b0f896 | 7261 | static void |
e3bb37b5 | 7262 | output_branch (void) |
29b0f896 AM |
7263 | { |
7264 | char *p; | |
f8a5c266 | 7265 | int size; |
29b0f896 AM |
7266 | int code16; |
7267 | int prefix; | |
7268 | relax_substateT subtype; | |
7269 | symbolS *sym; | |
7270 | offsetT off; | |
7271 | ||
f8a5c266 | 7272 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7273 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7274 | |
7275 | prefix = 0; | |
7276 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7277 | { |
29b0f896 AM |
7278 | prefix = 1; |
7279 | i.prefixes -= 1; | |
7280 | code16 ^= CODE16; | |
252b5132 | 7281 | } |
29b0f896 AM |
7282 | /* Pentium4 branch hints. */ |
7283 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7284 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7285 | { |
29b0f896 AM |
7286 | prefix++; |
7287 | i.prefixes--; | |
7288 | } | |
7289 | if (i.prefix[REX_PREFIX] != 0) | |
7290 | { | |
7291 | prefix++; | |
7292 | i.prefixes--; | |
2f66722d AM |
7293 | } |
7294 | ||
7e8b059b L |
7295 | /* BND prefixed jump. */ |
7296 | if (i.prefix[BND_PREFIX] != 0) | |
7297 | { | |
7298 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7299 | i.prefixes -= 1; | |
7300 | } | |
7301 | ||
29b0f896 AM |
7302 | if (i.prefixes != 0 && !intel_syntax) |
7303 | as_warn (_("skipping prefixes on this instruction")); | |
7304 | ||
7305 | /* It's always a symbol; End frag & setup for relax. | |
7306 | Make sure there is enough room in this frag for the largest | |
7307 | instruction we may generate in md_convert_frag. This is 2 | |
7308 | bytes for the opcode and room for the prefix and largest | |
7309 | displacement. */ | |
7310 | frag_grow (prefix + 2 + 4); | |
7311 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7312 | p = frag_more (prefix + 1); | |
7313 | if (i.prefix[DATA_PREFIX] != 0) | |
7314 | *p++ = DATA_PREFIX_OPCODE; | |
7315 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7316 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7317 | *p++ = i.prefix[SEG_PREFIX]; | |
7318 | if (i.prefix[REX_PREFIX] != 0) | |
7319 | *p++ = i.prefix[REX_PREFIX]; | |
7320 | *p = i.tm.base_opcode; | |
7321 | ||
7322 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7323 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7324 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7325 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7326 | else |
f8a5c266 | 7327 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7328 | subtype |= code16; |
3e73aa7c | 7329 | |
29b0f896 AM |
7330 | sym = i.op[0].disps->X_add_symbol; |
7331 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7332 | |
29b0f896 AM |
7333 | if (i.op[0].disps->X_op != O_constant |
7334 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7335 | { |
29b0f896 AM |
7336 | /* Handle complex expressions. */ |
7337 | sym = make_expr_symbol (i.op[0].disps); | |
7338 | off = 0; | |
7339 | } | |
3e73aa7c | 7340 | |
29b0f896 AM |
7341 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7342 | Pass reloc in fr_var. */ | |
d258b828 | 7343 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7344 | } |
3e73aa7c | 7345 | |
bd7ab16b L |
7346 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7347 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7348 | symbol S. */ | |
7349 | ||
7350 | static bfd_boolean | |
7351 | need_plt32_p (symbolS *s) | |
7352 | { | |
7353 | /* PLT32 relocation is ELF only. */ | |
7354 | if (!IS_ELF) | |
7355 | return FALSE; | |
7356 | ||
7357 | /* Since there is no need to prepare for PLT branch on x86-64, we | |
7358 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7359 | be used as a marker for 32-bit PC-relative branches. */ | |
7360 | if (!object_64bit) | |
7361 | return FALSE; | |
7362 | ||
7363 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7364 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7365 | return TRUE; | |
7366 | ||
7367 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7368 | if (! S_IS_EXTERNAL (s)) | |
7369 | return FALSE; | |
7370 | ||
7371 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7372 | non-default visibilities are treated as normal global symbol | |
7373 | so that PLT32 relocation can be used as a marker for 32-bit | |
7374 | PC-relative branches. It is useful for linker relaxation. */ | |
7375 | return TRUE; | |
7376 | } | |
7377 | #endif | |
7378 | ||
29b0f896 | 7379 | static void |
e3bb37b5 | 7380 | output_jump (void) |
29b0f896 AM |
7381 | { |
7382 | char *p; | |
7383 | int size; | |
3e02c1cc | 7384 | fixS *fixP; |
bd7ab16b | 7385 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7386 | |
40fb9820 | 7387 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7388 | { |
7389 | /* This is a loop or jecxz type instruction. */ | |
7390 | size = 1; | |
7391 | if (i.prefix[ADDR_PREFIX] != 0) | |
7392 | { | |
7393 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7394 | i.prefixes -= 1; | |
7395 | } | |
7396 | /* Pentium4 branch hints. */ | |
7397 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7398 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7399 | { | |
7400 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7401 | i.prefixes--; | |
3e73aa7c JH |
7402 | } |
7403 | } | |
29b0f896 AM |
7404 | else |
7405 | { | |
7406 | int code16; | |
3e73aa7c | 7407 | |
29b0f896 AM |
7408 | code16 = 0; |
7409 | if (flag_code == CODE_16BIT) | |
7410 | code16 = CODE16; | |
3e73aa7c | 7411 | |
29b0f896 AM |
7412 | if (i.prefix[DATA_PREFIX] != 0) |
7413 | { | |
7414 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7415 | i.prefixes -= 1; | |
7416 | code16 ^= CODE16; | |
7417 | } | |
252b5132 | 7418 | |
29b0f896 AM |
7419 | size = 4; |
7420 | if (code16) | |
7421 | size = 2; | |
7422 | } | |
9fcc94b6 | 7423 | |
29b0f896 AM |
7424 | if (i.prefix[REX_PREFIX] != 0) |
7425 | { | |
7426 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7427 | i.prefixes -= 1; | |
7428 | } | |
252b5132 | 7429 | |
7e8b059b L |
7430 | /* BND prefixed jump. */ |
7431 | if (i.prefix[BND_PREFIX] != 0) | |
7432 | { | |
7433 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7434 | i.prefixes -= 1; | |
7435 | } | |
7436 | ||
29b0f896 AM |
7437 | if (i.prefixes != 0 && !intel_syntax) |
7438 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7439 | |
42164a71 L |
7440 | p = frag_more (i.tm.opcode_length + size); |
7441 | switch (i.tm.opcode_length) | |
7442 | { | |
7443 | case 2: | |
7444 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7445 | /* Fall through. */ |
42164a71 L |
7446 | case 1: |
7447 | *p++ = i.tm.base_opcode; | |
7448 | break; | |
7449 | default: | |
7450 | abort (); | |
7451 | } | |
e0890092 | 7452 | |
bd7ab16b L |
7453 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7454 | if (size == 4 | |
7455 | && jump_reloc == NO_RELOC | |
7456 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7457 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7458 | #endif | |
7459 | ||
7460 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7461 | ||
3e02c1cc | 7462 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7463 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7464 | |
7465 | /* All jumps handled here are signed, but don't use a signed limit | |
7466 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7467 | 4G and 64k respectively. */ | |
7468 | if (size == 1) | |
7469 | fixP->fx_signed = 1; | |
29b0f896 | 7470 | } |
e0890092 | 7471 | |
29b0f896 | 7472 | static void |
e3bb37b5 | 7473 | output_interseg_jump (void) |
29b0f896 AM |
7474 | { |
7475 | char *p; | |
7476 | int size; | |
7477 | int prefix; | |
7478 | int code16; | |
252b5132 | 7479 | |
29b0f896 AM |
7480 | code16 = 0; |
7481 | if (flag_code == CODE_16BIT) | |
7482 | code16 = CODE16; | |
a217f122 | 7483 | |
29b0f896 AM |
7484 | prefix = 0; |
7485 | if (i.prefix[DATA_PREFIX] != 0) | |
7486 | { | |
7487 | prefix = 1; | |
7488 | i.prefixes -= 1; | |
7489 | code16 ^= CODE16; | |
7490 | } | |
7491 | if (i.prefix[REX_PREFIX] != 0) | |
7492 | { | |
7493 | prefix++; | |
7494 | i.prefixes -= 1; | |
7495 | } | |
252b5132 | 7496 | |
29b0f896 AM |
7497 | size = 4; |
7498 | if (code16) | |
7499 | size = 2; | |
252b5132 | 7500 | |
29b0f896 AM |
7501 | if (i.prefixes != 0 && !intel_syntax) |
7502 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7503 | |
29b0f896 AM |
7504 | /* 1 opcode; 2 segment; offset */ |
7505 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7506 | |
29b0f896 AM |
7507 | if (i.prefix[DATA_PREFIX] != 0) |
7508 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7509 | |
29b0f896 AM |
7510 | if (i.prefix[REX_PREFIX] != 0) |
7511 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7512 | |
29b0f896 AM |
7513 | *p++ = i.tm.base_opcode; |
7514 | if (i.op[1].imms->X_op == O_constant) | |
7515 | { | |
7516 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7517 | |
29b0f896 AM |
7518 | if (size == 2 |
7519 | && !fits_in_unsigned_word (n) | |
7520 | && !fits_in_signed_word (n)) | |
7521 | { | |
7522 | as_bad (_("16-bit jump out of range")); | |
7523 | return; | |
7524 | } | |
7525 | md_number_to_chars (p, n, size); | |
7526 | } | |
7527 | else | |
7528 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7529 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7530 | if (i.op[0].imms->X_op != O_constant) |
7531 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7532 | i.tm.name); | |
7533 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7534 | } | |
a217f122 | 7535 | |
29b0f896 | 7536 | static void |
e3bb37b5 | 7537 | output_insn (void) |
29b0f896 | 7538 | { |
2bbd9c25 JJ |
7539 | fragS *insn_start_frag; |
7540 | offsetT insn_start_off; | |
7541 | ||
29b0f896 AM |
7542 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7543 | We can't do this after the insn has been output as the current | |
7544 | frag may have been closed off. eg. by frag_var. */ | |
7545 | dwarf2_emit_insn (0); | |
7546 | ||
2bbd9c25 JJ |
7547 | insn_start_frag = frag_now; |
7548 | insn_start_off = frag_now_fix (); | |
7549 | ||
29b0f896 | 7550 | /* Output jumps. */ |
40fb9820 | 7551 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7552 | output_branch (); |
40fb9820 L |
7553 | else if (i.tm.opcode_modifier.jumpbyte |
7554 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7555 | output_jump (); |
40fb9820 | 7556 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7557 | output_interseg_jump (); |
7558 | else | |
7559 | { | |
7560 | /* Output normal instructions here. */ | |
7561 | char *p; | |
7562 | unsigned char *q; | |
47465058 | 7563 | unsigned int j; |
331d2d0d | 7564 | unsigned int prefix; |
4dffcebc | 7565 | |
e4e00185 AS |
7566 | if (avoid_fence |
7567 | && i.tm.base_opcode == 0xfae | |
7568 | && i.operands == 1 | |
7569 | && i.imm_operands == 1 | |
7570 | && (i.op[0].imms->X_add_number == 0xe8 | |
7571 | || i.op[0].imms->X_add_number == 0xf0 | |
7572 | || i.op[0].imms->X_add_number == 0xf8)) | |
7573 | { | |
7574 | /* Encode lfence, mfence, and sfence as | |
7575 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7576 | offsetT val = 0x240483f0ULL; | |
7577 | p = frag_more (5); | |
7578 | md_number_to_chars (p, val, 5); | |
7579 | return; | |
7580 | } | |
7581 | ||
d022bddd IT |
7582 | /* Some processors fail on LOCK prefix. This options makes |
7583 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7584 | if (omit_lock_prefix) | |
7585 | { | |
7586 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7587 | return; | |
7588 | i.prefix[LOCK_PREFIX] = 0; | |
7589 | } | |
7590 | ||
43234a1e L |
7591 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7592 | don't need the explicit prefix. */ | |
7593 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7594 | { |
c0f3af97 | 7595 | switch (i.tm.opcode_length) |
bc4bd9ab | 7596 | { |
c0f3af97 L |
7597 | case 3: |
7598 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7599 | { |
c0f3af97 L |
7600 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
7601 | goto check_prefix; | |
7602 | } | |
7603 | break; | |
7604 | case 2: | |
7605 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7606 | { | |
7607 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
7608 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
7609 | { | |
4dffcebc | 7610 | check_prefix: |
c0f3af97 | 7611 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 7612 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
7613 | != REPE_PREFIX_OPCODE)) |
7614 | add_prefix (prefix); | |
7615 | } | |
7616 | else | |
4dffcebc L |
7617 | add_prefix (prefix); |
7618 | } | |
c0f3af97 L |
7619 | break; |
7620 | case 1: | |
7621 | break; | |
390c91cf L |
7622 | case 0: |
7623 | /* Check for pseudo prefixes. */ | |
7624 | as_bad_where (insn_start_frag->fr_file, | |
7625 | insn_start_frag->fr_line, | |
7626 | _("pseudo prefix without instruction")); | |
7627 | return; | |
c0f3af97 L |
7628 | default: |
7629 | abort (); | |
bc4bd9ab | 7630 | } |
c0f3af97 | 7631 | |
6d19a37a | 7632 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7633 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7634 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7635 | perform IE->LE optimization. */ | |
7636 | if (x86_elf_abi == X86_64_X32_ABI | |
7637 | && i.operands == 2 | |
7638 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7639 | && i.prefix[REX_PREFIX] == 0) | |
7640 | add_prefix (REX_OPCODE); | |
6d19a37a | 7641 | #endif |
cf61b747 | 7642 | |
c0f3af97 L |
7643 | /* The prefix bytes. */ |
7644 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7645 | if (*q) | |
7646 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7647 | } |
ae5c1c7b | 7648 | else |
c0f3af97 L |
7649 | { |
7650 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7651 | if (*q) | |
7652 | switch (j) | |
7653 | { | |
7654 | case REX_PREFIX: | |
7655 | /* REX byte is encoded in VEX prefix. */ | |
7656 | break; | |
7657 | case SEG_PREFIX: | |
7658 | case ADDR_PREFIX: | |
7659 | FRAG_APPEND_1_CHAR (*q); | |
7660 | break; | |
7661 | default: | |
7662 | /* There should be no other prefixes for instructions | |
7663 | with VEX prefix. */ | |
7664 | abort (); | |
7665 | } | |
7666 | ||
43234a1e L |
7667 | /* For EVEX instructions i.vrex should become 0 after |
7668 | build_evex_prefix. For VEX instructions upper 16 registers | |
7669 | aren't available, so VREX should be 0. */ | |
7670 | if (i.vrex) | |
7671 | abort (); | |
c0f3af97 L |
7672 | /* Now the VEX prefix. */ |
7673 | p = frag_more (i.vex.length); | |
7674 | for (j = 0; j < i.vex.length; j++) | |
7675 | p[j] = i.vex.bytes[j]; | |
7676 | } | |
252b5132 | 7677 | |
29b0f896 | 7678 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7679 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7680 | { |
7681 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7682 | } | |
7683 | else | |
7684 | { | |
4dffcebc | 7685 | switch (i.tm.opcode_length) |
331d2d0d | 7686 | { |
43234a1e L |
7687 | case 4: |
7688 | p = frag_more (4); | |
7689 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7690 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7691 | break; | |
4dffcebc | 7692 | case 3: |
331d2d0d L |
7693 | p = frag_more (3); |
7694 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7695 | break; |
7696 | case 2: | |
7697 | p = frag_more (2); | |
7698 | break; | |
7699 | default: | |
7700 | abort (); | |
7701 | break; | |
331d2d0d | 7702 | } |
0f10071e | 7703 | |
29b0f896 AM |
7704 | /* Put out high byte first: can't use md_number_to_chars! */ |
7705 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7706 | *p = i.tm.base_opcode & 0xff; | |
7707 | } | |
3e73aa7c | 7708 | |
29b0f896 | 7709 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7710 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7711 | { |
4a3523fa L |
7712 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7713 | | i.rm.reg << 3 | |
7714 | | i.rm.mode << 6)); | |
29b0f896 AM |
7715 | /* If i.rm.regmem == ESP (4) |
7716 | && i.rm.mode != (Register mode) | |
7717 | && not 16 bit | |
7718 | ==> need second modrm byte. */ | |
7719 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7720 | && i.rm.mode != 3 | |
dc821c5f | 7721 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
7722 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7723 | | i.sib.index << 3 | |
7724 | | i.sib.scale << 6)); | |
29b0f896 | 7725 | } |
3e73aa7c | 7726 | |
29b0f896 | 7727 | if (i.disp_operands) |
2bbd9c25 | 7728 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7729 | |
29b0f896 | 7730 | if (i.imm_operands) |
2bbd9c25 | 7731 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7732 | } |
252b5132 | 7733 | |
29b0f896 AM |
7734 | #ifdef DEBUG386 |
7735 | if (flag_debug) | |
7736 | { | |
7b81dfbb | 7737 | pi ("" /*line*/, &i); |
29b0f896 AM |
7738 | } |
7739 | #endif /* DEBUG386 */ | |
7740 | } | |
252b5132 | 7741 | |
e205caa7 L |
7742 | /* Return the size of the displacement operand N. */ |
7743 | ||
7744 | static int | |
7745 | disp_size (unsigned int n) | |
7746 | { | |
7747 | int size = 4; | |
43234a1e | 7748 | |
b5014f7a | 7749 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
7750 | size = 8; |
7751 | else if (i.types[n].bitfield.disp8) | |
7752 | size = 1; | |
7753 | else if (i.types[n].bitfield.disp16) | |
7754 | size = 2; | |
e205caa7 L |
7755 | return size; |
7756 | } | |
7757 | ||
7758 | /* Return the size of the immediate operand N. */ | |
7759 | ||
7760 | static int | |
7761 | imm_size (unsigned int n) | |
7762 | { | |
7763 | int size = 4; | |
40fb9820 L |
7764 | if (i.types[n].bitfield.imm64) |
7765 | size = 8; | |
7766 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7767 | size = 1; | |
7768 | else if (i.types[n].bitfield.imm16) | |
7769 | size = 2; | |
e205caa7 L |
7770 | return size; |
7771 | } | |
7772 | ||
29b0f896 | 7773 | static void |
64e74474 | 7774 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7775 | { |
7776 | char *p; | |
7777 | unsigned int n; | |
252b5132 | 7778 | |
29b0f896 AM |
7779 | for (n = 0; n < i.operands; n++) |
7780 | { | |
b5014f7a | 7781 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
7782 | { |
7783 | if (i.op[n].disps->X_op == O_constant) | |
7784 | { | |
e205caa7 | 7785 | int size = disp_size (n); |
43234a1e | 7786 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7787 | |
b5014f7a | 7788 | val = offset_in_range (val >> i.memshift, size); |
29b0f896 AM |
7789 | p = frag_more (size); |
7790 | md_number_to_chars (p, val, size); | |
7791 | } | |
7792 | else | |
7793 | { | |
f86103b7 | 7794 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7795 | int size = disp_size (n); |
40fb9820 | 7796 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7797 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7798 | fixS *fixP; |
29b0f896 | 7799 | |
e205caa7 | 7800 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7801 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7802 | |
29b0f896 AM |
7803 | /* The PC relative address is computed relative |
7804 | to the instruction boundary, so in case immediate | |
7805 | fields follows, we need to adjust the value. */ | |
7806 | if (pcrel && i.imm_operands) | |
7807 | { | |
29b0f896 | 7808 | unsigned int n1; |
e205caa7 | 7809 | int sz = 0; |
252b5132 | 7810 | |
29b0f896 | 7811 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7812 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7813 | { |
e205caa7 L |
7814 | /* Only one immediate is allowed for PC |
7815 | relative address. */ | |
9c2799c2 | 7816 | gas_assert (sz == 0); |
e205caa7 L |
7817 | sz = imm_size (n1); |
7818 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7819 | } |
29b0f896 | 7820 | /* We should find the immediate. */ |
9c2799c2 | 7821 | gas_assert (sz != 0); |
29b0f896 | 7822 | } |
520dc8e8 | 7823 | |
29b0f896 | 7824 | p = frag_more (size); |
d258b828 | 7825 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 7826 | if (GOT_symbol |
2bbd9c25 | 7827 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 7828 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7829 | || reloc_type == BFD_RELOC_X86_64_32S |
7830 | || (reloc_type == BFD_RELOC_64 | |
7831 | && object_64bit)) | |
d6ab8113 JB |
7832 | && (i.op[n].disps->X_op == O_symbol |
7833 | || (i.op[n].disps->X_op == O_add | |
7834 | && ((symbol_get_value_expression | |
7835 | (i.op[n].disps->X_op_symbol)->X_op) | |
7836 | == O_subtract)))) | |
7837 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
7838 | { |
7839 | offsetT add; | |
7840 | ||
7841 | if (insn_start_frag == frag_now) | |
7842 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7843 | else | |
7844 | { | |
7845 | fragS *fr; | |
7846 | ||
7847 | add = insn_start_frag->fr_fix - insn_start_off; | |
7848 | for (fr = insn_start_frag->fr_next; | |
7849 | fr && fr != frag_now; fr = fr->fr_next) | |
7850 | add += fr->fr_fix; | |
7851 | add += p - frag_now->fr_literal; | |
7852 | } | |
7853 | ||
4fa24527 | 7854 | if (!object_64bit) |
7b81dfbb AJ |
7855 | { |
7856 | reloc_type = BFD_RELOC_386_GOTPC; | |
7857 | i.op[n].imms->X_add_number += add; | |
7858 | } | |
7859 | else if (reloc_type == BFD_RELOC_64) | |
7860 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 7861 | else |
7b81dfbb AJ |
7862 | /* Don't do the adjustment for x86-64, as there |
7863 | the pcrel addressing is relative to the _next_ | |
7864 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 7865 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 7866 | } |
02a86693 L |
7867 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
7868 | size, i.op[n].disps, pcrel, | |
7869 | reloc_type); | |
7870 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
7871 | "test %reg, mem" and "binop mem, %reg" where binop | |
7872 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
7873 | instructions. Always generate R_386_GOT32X for |
7874 | "sym*GOT" operand in 32-bit mode. */ | |
7875 | if ((generate_relax_relocations | |
7876 | || (!object_64bit | |
7877 | && i.rm.mode == 0 | |
7878 | && i.rm.regmem == 5)) | |
7879 | && (i.rm.mode == 2 | |
7880 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
7881 | && ((i.operands == 1 |
7882 | && i.tm.base_opcode == 0xff | |
7883 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
7884 | || (i.operands == 2 | |
7885 | && (i.tm.base_opcode == 0x8b | |
7886 | || i.tm.base_opcode == 0x85 | |
7887 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
7888 | { | |
7889 | if (object_64bit) | |
7890 | { | |
7891 | fixP->fx_tcbit = i.rex != 0; | |
7892 | if (i.base_reg | |
7893 | && (i.base_reg->reg_num == RegRip | |
7894 | || i.base_reg->reg_num == RegEip)) | |
7895 | fixP->fx_tcbit2 = 1; | |
7896 | } | |
7897 | else | |
7898 | fixP->fx_tcbit2 = 1; | |
7899 | } | |
29b0f896 AM |
7900 | } |
7901 | } | |
7902 | } | |
7903 | } | |
252b5132 | 7904 | |
29b0f896 | 7905 | static void |
64e74474 | 7906 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7907 | { |
7908 | char *p; | |
7909 | unsigned int n; | |
252b5132 | 7910 | |
29b0f896 AM |
7911 | for (n = 0; n < i.operands; n++) |
7912 | { | |
43234a1e L |
7913 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
7914 | if (i.rounding && (int) n == i.rounding->operand) | |
7915 | continue; | |
7916 | ||
40fb9820 | 7917 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
7918 | { |
7919 | if (i.op[n].imms->X_op == O_constant) | |
7920 | { | |
e205caa7 | 7921 | int size = imm_size (n); |
29b0f896 | 7922 | offsetT val; |
b4cac588 | 7923 | |
29b0f896 AM |
7924 | val = offset_in_range (i.op[n].imms->X_add_number, |
7925 | size); | |
7926 | p = frag_more (size); | |
7927 | md_number_to_chars (p, val, size); | |
7928 | } | |
7929 | else | |
7930 | { | |
7931 | /* Not absolute_section. | |
7932 | Need a 32-bit fixup (don't support 8bit | |
7933 | non-absolute imms). Try to support other | |
7934 | sizes ... */ | |
f86103b7 | 7935 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
7936 | int size = imm_size (n); |
7937 | int sign; | |
29b0f896 | 7938 | |
40fb9820 | 7939 | if (i.types[n].bitfield.imm32s |
a7d61044 | 7940 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 7941 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 7942 | sign = 1; |
e205caa7 L |
7943 | else |
7944 | sign = 0; | |
520dc8e8 | 7945 | |
29b0f896 | 7946 | p = frag_more (size); |
d258b828 | 7947 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 7948 | |
2bbd9c25 JJ |
7949 | /* This is tough to explain. We end up with this one if we |
7950 | * have operands that look like | |
7951 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
7952 | * obtain the absolute address of the GOT, and it is strongly | |
7953 | * preferable from a performance point of view to avoid using | |
7954 | * a runtime relocation for this. The actual sequence of | |
7955 | * instructions often look something like: | |
7956 | * | |
7957 | * call .L66 | |
7958 | * .L66: | |
7959 | * popl %ebx | |
7960 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
7961 | * | |
7962 | * The call and pop essentially return the absolute address | |
7963 | * of the label .L66 and store it in %ebx. The linker itself | |
7964 | * will ultimately change the first operand of the addl so | |
7965 | * that %ebx points to the GOT, but to keep things simple, the | |
7966 | * .o file must have this operand set so that it generates not | |
7967 | * the absolute address of .L66, but the absolute address of | |
7968 | * itself. This allows the linker itself simply treat a GOTPC | |
7969 | * relocation as asking for a pcrel offset to the GOT to be | |
7970 | * added in, and the addend of the relocation is stored in the | |
7971 | * operand field for the instruction itself. | |
7972 | * | |
7973 | * Our job here is to fix the operand so that it would add | |
7974 | * the correct offset so that %ebx would point to itself. The | |
7975 | * thing that is tricky is that .-.L66 will point to the | |
7976 | * beginning of the instruction, so we need to further modify | |
7977 | * the operand so that it will point to itself. There are | |
7978 | * other cases where you have something like: | |
7979 | * | |
7980 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
7981 | * | |
7982 | * and here no correction would be required. Internally in | |
7983 | * the assembler we treat operands of this form as not being | |
7984 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
7985 | * whether it would simplify matters to do it this way. Who | |
7986 | * knows. In earlier versions of the PIC patches, the | |
7987 | * pcrel_adjust field was used to store the correction, but | |
7988 | * since the expression is not pcrel, I felt it would be | |
7989 | * confusing to do it this way. */ | |
7990 | ||
d6ab8113 | 7991 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7992 | || reloc_type == BFD_RELOC_X86_64_32S |
7993 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
7994 | && GOT_symbol |
7995 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
7996 | && (i.op[n].imms->X_op == O_symbol | |
7997 | || (i.op[n].imms->X_op == O_add | |
7998 | && ((symbol_get_value_expression | |
7999 | (i.op[n].imms->X_op_symbol)->X_op) | |
8000 | == O_subtract)))) | |
8001 | { | |
2bbd9c25 JJ |
8002 | offsetT add; |
8003 | ||
8004 | if (insn_start_frag == frag_now) | |
8005 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8006 | else | |
8007 | { | |
8008 | fragS *fr; | |
8009 | ||
8010 | add = insn_start_frag->fr_fix - insn_start_off; | |
8011 | for (fr = insn_start_frag->fr_next; | |
8012 | fr && fr != frag_now; fr = fr->fr_next) | |
8013 | add += fr->fr_fix; | |
8014 | add += p - frag_now->fr_literal; | |
8015 | } | |
8016 | ||
4fa24527 | 8017 | if (!object_64bit) |
d6ab8113 | 8018 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8019 | else if (size == 4) |
d6ab8113 | 8020 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8021 | else if (size == 8) |
8022 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 8023 | i.op[n].imms->X_add_number += add; |
29b0f896 | 8024 | } |
29b0f896 AM |
8025 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8026 | i.op[n].imms, 0, reloc_type); | |
8027 | } | |
8028 | } | |
8029 | } | |
252b5132 RH |
8030 | } |
8031 | \f | |
d182319b JB |
8032 | /* x86_cons_fix_new is called via the expression parsing code when a |
8033 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8034 | static int cons_sign = -1; |
8035 | ||
8036 | void | |
e3bb37b5 | 8037 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8038 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8039 | { |
d258b828 | 8040 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8041 | |
8042 | #ifdef TE_PE | |
8043 | if (exp->X_op == O_secrel) | |
8044 | { | |
8045 | exp->X_op = O_symbol; | |
8046 | r = BFD_RELOC_32_SECREL; | |
8047 | } | |
8048 | #endif | |
8049 | ||
8050 | fix_new_exp (frag, off, len, exp, 0, r); | |
8051 | } | |
8052 | ||
357d1bd8 L |
8053 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8054 | purpose of the `.dc.a' internal pseudo-op. */ | |
8055 | ||
8056 | int | |
8057 | x86_address_bytes (void) | |
8058 | { | |
8059 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8060 | return 4; | |
8061 | return stdoutput->arch_info->bits_per_address / 8; | |
8062 | } | |
8063 | ||
d382c579 TG |
8064 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8065 | || defined (LEX_AT) | |
d258b828 | 8066 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8067 | #else |
f3c180ae AM |
8068 | /* Parse operands of the form |
8069 | <symbol>@GOTOFF+<nnn> | |
8070 | and similar .plt or .got references. | |
8071 | ||
8072 | If we find one, set up the correct relocation in RELOC and copy the | |
8073 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8074 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8075 | is non-null set it to the length of the string we removed from the | |
8076 | input line. Otherwise return NULL. */ | |
8077 | static char * | |
91d6fa6a | 8078 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8079 | int *adjust, |
d258b828 | 8080 | i386_operand_type *types) |
f3c180ae | 8081 | { |
7b81dfbb AJ |
8082 | /* Some of the relocations depend on the size of what field is to |
8083 | be relocated. But in our callers i386_immediate and i386_displacement | |
8084 | we don't yet know the operand size (this will be set by insn | |
8085 | matching). Hence we record the word32 relocation here, | |
8086 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8087 | static const struct { |
8088 | const char *str; | |
cff8d58a | 8089 | int len; |
4fa24527 | 8090 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8091 | const i386_operand_type types64; |
f3c180ae | 8092 | } gotrel[] = { |
8ce3d284 | 8093 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8094 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8095 | BFD_RELOC_SIZE32 }, | |
8096 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8097 | #endif |
cff8d58a L |
8098 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8099 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8100 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8101 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8102 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8103 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8104 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8105 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8106 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8107 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8108 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8109 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8110 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8111 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8112 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8113 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8114 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8115 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8116 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8117 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8118 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8119 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8120 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8121 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8122 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8123 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8124 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8125 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8126 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8127 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8128 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8129 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8130 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8131 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8132 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8133 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8134 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8135 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8136 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8137 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8138 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8139 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8140 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8141 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8142 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8143 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8144 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8145 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8146 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8147 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8148 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8149 | }; |
8150 | char *cp; | |
8151 | unsigned int j; | |
8152 | ||
d382c579 | 8153 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8154 | if (!IS_ELF) |
8155 | return NULL; | |
d382c579 | 8156 | #endif |
718ddfc0 | 8157 | |
f3c180ae | 8158 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8159 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8160 | return NULL; |
8161 | ||
47465058 | 8162 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8163 | { |
cff8d58a | 8164 | int len = gotrel[j].len; |
28f81592 | 8165 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8166 | { |
4fa24527 | 8167 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8168 | { |
28f81592 AM |
8169 | int first, second; |
8170 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8171 | |
91d6fa6a | 8172 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8173 | |
3956db08 JB |
8174 | if (types) |
8175 | { | |
8176 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8177 | { |
8178 | types->bitfield.imm32 = 1; | |
8179 | types->bitfield.disp32 = 1; | |
8180 | } | |
3956db08 JB |
8181 | else |
8182 | *types = gotrel[j].types64; | |
8183 | } | |
8184 | ||
8fd4256d | 8185 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8186 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8187 | ||
28f81592 | 8188 | /* The length of the first part of our input line. */ |
f3c180ae | 8189 | first = cp - input_line_pointer; |
28f81592 AM |
8190 | |
8191 | /* The second part goes from after the reloc token until | |
67c11a9b | 8192 | (and including) an end_of_line char or comma. */ |
28f81592 | 8193 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8194 | cp = past_reloc; |
8195 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8196 | ++cp; | |
8197 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8198 | |
8199 | /* Allocate and copy string. The trailing NUL shouldn't | |
8200 | be necessary, but be safe. */ | |
add39d23 | 8201 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8202 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8203 | if (second != 0 && *past_reloc != ' ') |
8204 | /* Replace the relocation token with ' ', so that | |
8205 | errors like foo@GOTOFF1 will be detected. */ | |
8206 | tmpbuf[first++] = ' '; | |
af89796a L |
8207 | else |
8208 | /* Increment length by 1 if the relocation token is | |
8209 | removed. */ | |
8210 | len++; | |
8211 | if (adjust) | |
8212 | *adjust = len; | |
0787a12d AM |
8213 | memcpy (tmpbuf + first, past_reloc, second); |
8214 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8215 | return tmpbuf; |
8216 | } | |
8217 | ||
4fa24527 JB |
8218 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8219 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8220 | return NULL; |
8221 | } | |
8222 | } | |
8223 | ||
8224 | /* Might be a symbol version string. Don't as_bad here. */ | |
8225 | return NULL; | |
8226 | } | |
4e4f7c87 | 8227 | #endif |
f3c180ae | 8228 | |
a988325c NC |
8229 | #ifdef TE_PE |
8230 | #ifdef lex_got | |
8231 | #undef lex_got | |
8232 | #endif | |
8233 | /* Parse operands of the form | |
8234 | <symbol>@SECREL32+<nnn> | |
8235 | ||
8236 | If we find one, set up the correct relocation in RELOC and copy the | |
8237 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8238 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8239 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8240 | input line. Otherwise return NULL. |
8241 | ||
a988325c NC |
8242 | This function is copied from the ELF version above adjusted for PE targets. */ |
8243 | ||
8244 | static char * | |
8245 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8246 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8247 | i386_operand_type *types) |
a988325c NC |
8248 | { |
8249 | static const struct | |
8250 | { | |
8251 | const char *str; | |
8252 | int len; | |
8253 | const enum bfd_reloc_code_real rel[2]; | |
8254 | const i386_operand_type types64; | |
8255 | } | |
8256 | gotrel[] = | |
8257 | { | |
8258 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8259 | BFD_RELOC_32_SECREL }, | |
8260 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8261 | }; | |
8262 | ||
8263 | char *cp; | |
8264 | unsigned j; | |
8265 | ||
8266 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8267 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8268 | return NULL; | |
8269 | ||
8270 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8271 | { | |
8272 | int len = gotrel[j].len; | |
8273 | ||
8274 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8275 | { | |
8276 | if (gotrel[j].rel[object_64bit] != 0) | |
8277 | { | |
8278 | int first, second; | |
8279 | char *tmpbuf, *past_reloc; | |
8280 | ||
8281 | *rel = gotrel[j].rel[object_64bit]; | |
8282 | if (adjust) | |
8283 | *adjust = len; | |
8284 | ||
8285 | if (types) | |
8286 | { | |
8287 | if (flag_code != CODE_64BIT) | |
8288 | { | |
8289 | types->bitfield.imm32 = 1; | |
8290 | types->bitfield.disp32 = 1; | |
8291 | } | |
8292 | else | |
8293 | *types = gotrel[j].types64; | |
8294 | } | |
8295 | ||
8296 | /* The length of the first part of our input line. */ | |
8297 | first = cp - input_line_pointer; | |
8298 | ||
8299 | /* The second part goes from after the reloc token until | |
8300 | (and including) an end_of_line char or comma. */ | |
8301 | past_reloc = cp + 1 + len; | |
8302 | cp = past_reloc; | |
8303 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8304 | ++cp; | |
8305 | second = cp + 1 - past_reloc; | |
8306 | ||
8307 | /* Allocate and copy string. The trailing NUL shouldn't | |
8308 | be necessary, but be safe. */ | |
add39d23 | 8309 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8310 | memcpy (tmpbuf, input_line_pointer, first); |
8311 | if (second != 0 && *past_reloc != ' ') | |
8312 | /* Replace the relocation token with ' ', so that | |
8313 | errors like foo@SECLREL321 will be detected. */ | |
8314 | tmpbuf[first++] = ' '; | |
8315 | memcpy (tmpbuf + first, past_reloc, second); | |
8316 | tmpbuf[first + second] = '\0'; | |
8317 | return tmpbuf; | |
8318 | } | |
8319 | ||
8320 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8321 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8322 | return NULL; | |
8323 | } | |
8324 | } | |
8325 | ||
8326 | /* Might be a symbol version string. Don't as_bad here. */ | |
8327 | return NULL; | |
8328 | } | |
8329 | ||
8330 | #endif /* TE_PE */ | |
8331 | ||
62ebcb5c | 8332 | bfd_reloc_code_real_type |
e3bb37b5 | 8333 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8334 | { |
62ebcb5c AM |
8335 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8336 | ||
ee86248c JB |
8337 | intel_syntax = -intel_syntax; |
8338 | ||
3c7b9c2c | 8339 | exp->X_md = 0; |
4fa24527 | 8340 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8341 | { |
8342 | /* Handle @GOTOFF and the like in an expression. */ | |
8343 | char *save; | |
8344 | char *gotfree_input_line; | |
4a57f2cf | 8345 | int adjust = 0; |
f3c180ae AM |
8346 | |
8347 | save = input_line_pointer; | |
d258b828 | 8348 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8349 | if (gotfree_input_line) |
8350 | input_line_pointer = gotfree_input_line; | |
8351 | ||
8352 | expression (exp); | |
8353 | ||
8354 | if (gotfree_input_line) | |
8355 | { | |
8356 | /* expression () has merrily parsed up to the end of line, | |
8357 | or a comma - in the wrong buffer. Transfer how far | |
8358 | input_line_pointer has moved to the right buffer. */ | |
8359 | input_line_pointer = (save | |
8360 | + (input_line_pointer - gotfree_input_line) | |
8361 | + adjust); | |
8362 | free (gotfree_input_line); | |
3992d3b7 AM |
8363 | if (exp->X_op == O_constant |
8364 | || exp->X_op == O_absent | |
8365 | || exp->X_op == O_illegal | |
0398aac5 | 8366 | || exp->X_op == O_register |
3992d3b7 AM |
8367 | || exp->X_op == O_big) |
8368 | { | |
8369 | char c = *input_line_pointer; | |
8370 | *input_line_pointer = 0; | |
8371 | as_bad (_("missing or invalid expression `%s'"), save); | |
8372 | *input_line_pointer = c; | |
8373 | } | |
f3c180ae AM |
8374 | } |
8375 | } | |
8376 | else | |
8377 | expression (exp); | |
ee86248c JB |
8378 | |
8379 | intel_syntax = -intel_syntax; | |
8380 | ||
8381 | if (intel_syntax) | |
8382 | i386_intel_simplify (exp); | |
62ebcb5c AM |
8383 | |
8384 | return got_reloc; | |
f3c180ae | 8385 | } |
f3c180ae | 8386 | |
9f32dd5b L |
8387 | static void |
8388 | signed_cons (int size) | |
6482c264 | 8389 | { |
d182319b JB |
8390 | if (flag_code == CODE_64BIT) |
8391 | cons_sign = 1; | |
8392 | cons (size); | |
8393 | cons_sign = -1; | |
6482c264 NC |
8394 | } |
8395 | ||
d182319b | 8396 | #ifdef TE_PE |
6482c264 | 8397 | static void |
7016a5d5 | 8398 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
8399 | { |
8400 | expressionS exp; | |
8401 | ||
8402 | do | |
8403 | { | |
8404 | expression (&exp); | |
8405 | if (exp.X_op == O_symbol) | |
8406 | exp.X_op = O_secrel; | |
8407 | ||
8408 | emit_expr (&exp, 4); | |
8409 | } | |
8410 | while (*input_line_pointer++ == ','); | |
8411 | ||
8412 | input_line_pointer--; | |
8413 | demand_empty_rest_of_line (); | |
8414 | } | |
6482c264 NC |
8415 | #endif |
8416 | ||
43234a1e L |
8417 | /* Handle Vector operations. */ |
8418 | ||
8419 | static char * | |
8420 | check_VecOperations (char *op_string, char *op_end) | |
8421 | { | |
8422 | const reg_entry *mask; | |
8423 | const char *saved; | |
8424 | char *end_op; | |
8425 | ||
8426 | while (*op_string | |
8427 | && (op_end == NULL || op_string < op_end)) | |
8428 | { | |
8429 | saved = op_string; | |
8430 | if (*op_string == '{') | |
8431 | { | |
8432 | op_string++; | |
8433 | ||
8434 | /* Check broadcasts. */ | |
8435 | if (strncmp (op_string, "1to", 3) == 0) | |
8436 | { | |
8437 | int bcst_type; | |
8438 | ||
8439 | if (i.broadcast) | |
8440 | goto duplicated_vec_op; | |
8441 | ||
8442 | op_string += 3; | |
8443 | if (*op_string == '8') | |
8444 | bcst_type = BROADCAST_1TO8; | |
b28d1bda IT |
8445 | else if (*op_string == '4') |
8446 | bcst_type = BROADCAST_1TO4; | |
8447 | else if (*op_string == '2') | |
8448 | bcst_type = BROADCAST_1TO2; | |
43234a1e L |
8449 | else if (*op_string == '1' |
8450 | && *(op_string+1) == '6') | |
8451 | { | |
8452 | bcst_type = BROADCAST_1TO16; | |
8453 | op_string++; | |
8454 | } | |
8455 | else | |
8456 | { | |
8457 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
8458 | return NULL; | |
8459 | } | |
8460 | op_string++; | |
8461 | ||
8462 | broadcast_op.type = bcst_type; | |
8463 | broadcast_op.operand = this_operand; | |
8464 | i.broadcast = &broadcast_op; | |
8465 | } | |
8466 | /* Check masking operation. */ | |
8467 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
8468 | { | |
8469 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 8470 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 8471 | { |
6d2cd6b2 JB |
8472 | as_bad (_("`%s%s' can't be used for write mask"), |
8473 | register_prefix, mask->reg_name); | |
43234a1e L |
8474 | return NULL; |
8475 | } | |
8476 | ||
8477 | if (!i.mask) | |
8478 | { | |
8479 | mask_op.mask = mask; | |
8480 | mask_op.zeroing = 0; | |
8481 | mask_op.operand = this_operand; | |
8482 | i.mask = &mask_op; | |
8483 | } | |
8484 | else | |
8485 | { | |
8486 | if (i.mask->mask) | |
8487 | goto duplicated_vec_op; | |
8488 | ||
8489 | i.mask->mask = mask; | |
8490 | ||
8491 | /* Only "{z}" is allowed here. No need to check | |
8492 | zeroing mask explicitly. */ | |
8493 | if (i.mask->operand != this_operand) | |
8494 | { | |
8495 | as_bad (_("invalid write mask `%s'"), saved); | |
8496 | return NULL; | |
8497 | } | |
8498 | } | |
8499 | ||
8500 | op_string = end_op; | |
8501 | } | |
8502 | /* Check zeroing-flag for masking operation. */ | |
8503 | else if (*op_string == 'z') | |
8504 | { | |
8505 | if (!i.mask) | |
8506 | { | |
8507 | mask_op.mask = NULL; | |
8508 | mask_op.zeroing = 1; | |
8509 | mask_op.operand = this_operand; | |
8510 | i.mask = &mask_op; | |
8511 | } | |
8512 | else | |
8513 | { | |
8514 | if (i.mask->zeroing) | |
8515 | { | |
8516 | duplicated_vec_op: | |
8517 | as_bad (_("duplicated `%s'"), saved); | |
8518 | return NULL; | |
8519 | } | |
8520 | ||
8521 | i.mask->zeroing = 1; | |
8522 | ||
8523 | /* Only "{%k}" is allowed here. No need to check mask | |
8524 | register explicitly. */ | |
8525 | if (i.mask->operand != this_operand) | |
8526 | { | |
8527 | as_bad (_("invalid zeroing-masking `%s'"), | |
8528 | saved); | |
8529 | return NULL; | |
8530 | } | |
8531 | } | |
8532 | ||
8533 | op_string++; | |
8534 | } | |
8535 | else | |
8536 | goto unknown_vec_op; | |
8537 | ||
8538 | if (*op_string != '}') | |
8539 | { | |
8540 | as_bad (_("missing `}' in `%s'"), saved); | |
8541 | return NULL; | |
8542 | } | |
8543 | op_string++; | |
8544 | continue; | |
8545 | } | |
8546 | unknown_vec_op: | |
8547 | /* We don't know this one. */ | |
8548 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8549 | return NULL; | |
8550 | } | |
8551 | ||
6d2cd6b2 JB |
8552 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
8553 | { | |
8554 | as_bad (_("zeroing-masking only allowed with write mask")); | |
8555 | return NULL; | |
8556 | } | |
8557 | ||
43234a1e L |
8558 | return op_string; |
8559 | } | |
8560 | ||
252b5132 | 8561 | static int |
70e41ade | 8562 | i386_immediate (char *imm_start) |
252b5132 RH |
8563 | { |
8564 | char *save_input_line_pointer; | |
f3c180ae | 8565 | char *gotfree_input_line; |
252b5132 | 8566 | segT exp_seg = 0; |
47926f60 | 8567 | expressionS *exp; |
40fb9820 L |
8568 | i386_operand_type types; |
8569 | ||
0dfbf9d7 | 8570 | operand_type_set (&types, ~0); |
252b5132 RH |
8571 | |
8572 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8573 | { | |
31b2323c L |
8574 | as_bad (_("at most %d immediate operands are allowed"), |
8575 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8576 | return 0; |
8577 | } | |
8578 | ||
8579 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8580 | i.op[this_operand].imms = exp; |
252b5132 RH |
8581 | |
8582 | if (is_space_char (*imm_start)) | |
8583 | ++imm_start; | |
8584 | ||
8585 | save_input_line_pointer = input_line_pointer; | |
8586 | input_line_pointer = imm_start; | |
8587 | ||
d258b828 | 8588 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8589 | if (gotfree_input_line) |
8590 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8591 | |
8592 | exp_seg = expression (exp); | |
8593 | ||
83183c0c | 8594 | SKIP_WHITESPACE (); |
43234a1e L |
8595 | |
8596 | /* Handle vector operations. */ | |
8597 | if (*input_line_pointer == '{') | |
8598 | { | |
8599 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8600 | NULL); | |
8601 | if (input_line_pointer == NULL) | |
8602 | return 0; | |
8603 | } | |
8604 | ||
252b5132 | 8605 | if (*input_line_pointer) |
f3c180ae | 8606 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8607 | |
8608 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8609 | if (gotfree_input_line) |
ee86248c JB |
8610 | { |
8611 | free (gotfree_input_line); | |
8612 | ||
8613 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8614 | exp->X_op = O_illegal; | |
8615 | } | |
8616 | ||
8617 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8618 | } | |
252b5132 | 8619 | |
ee86248c JB |
8620 | static int |
8621 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8622 | i386_operand_type types, const char *imm_start) | |
8623 | { | |
8624 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8625 | { |
313c53d1 L |
8626 | if (imm_start) |
8627 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8628 | imm_start); | |
3992d3b7 | 8629 | return 0; |
252b5132 | 8630 | } |
3e73aa7c | 8631 | else if (exp->X_op == O_constant) |
252b5132 | 8632 | { |
47926f60 | 8633 | /* Size it properly later. */ |
40fb9820 | 8634 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8635 | /* If not 64bit, sign extend val. */ |
8636 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8637 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8638 | exp->X_add_number | |
8639 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8640 | } |
4c63da97 | 8641 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8642 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8643 | && exp_seg != absolute_section |
47926f60 | 8644 | && exp_seg != text_section |
24eab124 AM |
8645 | && exp_seg != data_section |
8646 | && exp_seg != bss_section | |
8647 | && exp_seg != undefined_section | |
f86103b7 | 8648 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8649 | { |
d0b47220 | 8650 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8651 | return 0; |
8652 | } | |
8653 | #endif | |
a841bdf5 | 8654 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8655 | { |
313c53d1 L |
8656 | if (imm_start) |
8657 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8658 | return 0; |
8659 | } | |
252b5132 RH |
8660 | else |
8661 | { | |
8662 | /* This is an address. The size of the address will be | |
24eab124 | 8663 | determined later, depending on destination register, |
3e73aa7c | 8664 | suffix, or the default for the section. */ |
40fb9820 L |
8665 | i.types[this_operand].bitfield.imm8 = 1; |
8666 | i.types[this_operand].bitfield.imm16 = 1; | |
8667 | i.types[this_operand].bitfield.imm32 = 1; | |
8668 | i.types[this_operand].bitfield.imm32s = 1; | |
8669 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8670 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8671 | types); | |
252b5132 RH |
8672 | } |
8673 | ||
8674 | return 1; | |
8675 | } | |
8676 | ||
551c1ca1 | 8677 | static char * |
e3bb37b5 | 8678 | i386_scale (char *scale) |
252b5132 | 8679 | { |
551c1ca1 AM |
8680 | offsetT val; |
8681 | char *save = input_line_pointer; | |
252b5132 | 8682 | |
551c1ca1 AM |
8683 | input_line_pointer = scale; |
8684 | val = get_absolute_expression (); | |
8685 | ||
8686 | switch (val) | |
252b5132 | 8687 | { |
551c1ca1 | 8688 | case 1: |
252b5132 RH |
8689 | i.log2_scale_factor = 0; |
8690 | break; | |
551c1ca1 | 8691 | case 2: |
252b5132 RH |
8692 | i.log2_scale_factor = 1; |
8693 | break; | |
551c1ca1 | 8694 | case 4: |
252b5132 RH |
8695 | i.log2_scale_factor = 2; |
8696 | break; | |
551c1ca1 | 8697 | case 8: |
252b5132 RH |
8698 | i.log2_scale_factor = 3; |
8699 | break; | |
8700 | default: | |
a724f0f4 JB |
8701 | { |
8702 | char sep = *input_line_pointer; | |
8703 | ||
8704 | *input_line_pointer = '\0'; | |
8705 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8706 | scale); | |
8707 | *input_line_pointer = sep; | |
8708 | input_line_pointer = save; | |
8709 | return NULL; | |
8710 | } | |
252b5132 | 8711 | } |
29b0f896 | 8712 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8713 | { |
8714 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8715 | 1 << i.log2_scale_factor); |
252b5132 | 8716 | i.log2_scale_factor = 0; |
252b5132 | 8717 | } |
551c1ca1 AM |
8718 | scale = input_line_pointer; |
8719 | input_line_pointer = save; | |
8720 | return scale; | |
252b5132 RH |
8721 | } |
8722 | ||
252b5132 | 8723 | static int |
e3bb37b5 | 8724 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8725 | { |
29b0f896 | 8726 | expressionS *exp; |
252b5132 RH |
8727 | segT exp_seg = 0; |
8728 | char *save_input_line_pointer; | |
f3c180ae | 8729 | char *gotfree_input_line; |
40fb9820 L |
8730 | int override; |
8731 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8732 | int ret; |
252b5132 | 8733 | |
31b2323c L |
8734 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8735 | { | |
8736 | as_bad (_("at most %d displacement operands are allowed"), | |
8737 | MAX_MEMORY_OPERANDS); | |
8738 | return 0; | |
8739 | } | |
8740 | ||
0dfbf9d7 | 8741 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8742 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8743 | || (!current_templates->start->opcode_modifier.jump | |
8744 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8745 | { |
40fb9820 | 8746 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8747 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8748 | if (flag_code == CODE_64BIT) |
8749 | { | |
8750 | if (!override) | |
8751 | { | |
8752 | bigdisp.bitfield.disp32s = 1; | |
8753 | bigdisp.bitfield.disp64 = 1; | |
8754 | } | |
8755 | } | |
8756 | else if ((flag_code == CODE_16BIT) ^ override) | |
8757 | { | |
8758 | bigdisp.bitfield.disp32 = 0; | |
8759 | bigdisp.bitfield.disp16 = 1; | |
8760 | } | |
e05278af JB |
8761 | } |
8762 | else | |
8763 | { | |
8764 | /* For PC-relative branches, the width of the displacement | |
8765 | is dependent upon data size, not address size. */ | |
e05278af | 8766 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8767 | if (flag_code == CODE_64BIT) |
8768 | { | |
8769 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8770 | bigdisp.bitfield.disp16 = 1; | |
8771 | else | |
8772 | { | |
8773 | bigdisp.bitfield.disp32 = 1; | |
8774 | bigdisp.bitfield.disp32s = 1; | |
8775 | } | |
8776 | } | |
8777 | else | |
e05278af JB |
8778 | { |
8779 | if (!override) | |
8780 | override = (i.suffix == (flag_code != CODE_16BIT | |
8781 | ? WORD_MNEM_SUFFIX | |
8782 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8783 | bigdisp.bitfield.disp32 = 1; |
8784 | if ((flag_code == CODE_16BIT) ^ override) | |
8785 | { | |
8786 | bigdisp.bitfield.disp32 = 0; | |
8787 | bigdisp.bitfield.disp16 = 1; | |
8788 | } | |
e05278af | 8789 | } |
e05278af | 8790 | } |
c6fb90c8 L |
8791 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8792 | bigdisp); | |
252b5132 RH |
8793 | |
8794 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8795 | i.op[this_operand].disps = exp; |
252b5132 RH |
8796 | i.disp_operands++; |
8797 | save_input_line_pointer = input_line_pointer; | |
8798 | input_line_pointer = disp_start; | |
8799 | END_STRING_AND_SAVE (disp_end); | |
8800 | ||
8801 | #ifndef GCC_ASM_O_HACK | |
8802 | #define GCC_ASM_O_HACK 0 | |
8803 | #endif | |
8804 | #if GCC_ASM_O_HACK | |
8805 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8806 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8807 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8808 | { |
8809 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8810 | constraint within gcc asm statements. |
8811 | For instance: | |
8812 | ||
8813 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
8814 | __asm__ __volatile__ ( \ | |
8815 | "movw %w2,%0\n\t" \ | |
8816 | "movw %w1,2+%0\n\t" \ | |
8817 | "rorl $16,%1\n\t" \ | |
8818 | "movb %b1,4+%0\n\t" \ | |
8819 | "movb %4,5+%0\n\t" \ | |
8820 | "movb $0,6+%0\n\t" \ | |
8821 | "movb %h1,7+%0\n\t" \ | |
8822 | "rorl $16,%1" \ | |
8823 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
8824 | ||
8825 | This works great except that the output assembler ends | |
8826 | up looking a bit weird if it turns out that there is | |
8827 | no offset. You end up producing code that looks like: | |
8828 | ||
8829 | #APP | |
8830 | movw $235,(%eax) | |
8831 | movw %dx,2+(%eax) | |
8832 | rorl $16,%edx | |
8833 | movb %dl,4+(%eax) | |
8834 | movb $137,5+(%eax) | |
8835 | movb $0,6+(%eax) | |
8836 | movb %dh,7+(%eax) | |
8837 | rorl $16,%edx | |
8838 | #NO_APP | |
8839 | ||
47926f60 | 8840 | So here we provide the missing zero. */ |
24eab124 AM |
8841 | |
8842 | *displacement_string_end = '0'; | |
252b5132 RH |
8843 | } |
8844 | #endif | |
d258b828 | 8845 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8846 | if (gotfree_input_line) |
8847 | input_line_pointer = gotfree_input_line; | |
252b5132 | 8848 | |
24eab124 | 8849 | exp_seg = expression (exp); |
252b5132 | 8850 | |
636c26b0 AM |
8851 | SKIP_WHITESPACE (); |
8852 | if (*input_line_pointer) | |
8853 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
8854 | #if GCC_ASM_O_HACK | |
8855 | RESTORE_END_STRING (disp_end + 1); | |
8856 | #endif | |
636c26b0 | 8857 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 8858 | if (gotfree_input_line) |
ee86248c JB |
8859 | { |
8860 | free (gotfree_input_line); | |
8861 | ||
8862 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8863 | exp->X_op = O_illegal; | |
8864 | } | |
8865 | ||
8866 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
8867 | ||
8868 | RESTORE_END_STRING (disp_end); | |
8869 | ||
8870 | return ret; | |
8871 | } | |
8872 | ||
8873 | static int | |
8874 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8875 | i386_operand_type types, const char *disp_start) | |
8876 | { | |
8877 | i386_operand_type bigdisp; | |
8878 | int ret = 1; | |
636c26b0 | 8879 | |
24eab124 AM |
8880 | /* We do this to make sure that the section symbol is in |
8881 | the symbol table. We will ultimately change the relocation | |
47926f60 | 8882 | to be relative to the beginning of the section. */ |
1ae12ab7 | 8883 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
8884 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
8885 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 8886 | { |
636c26b0 | 8887 | if (exp->X_op != O_symbol) |
3992d3b7 | 8888 | goto inv_disp; |
636c26b0 | 8889 | |
e5cb08ac | 8890 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
8891 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
8892 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 8893 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
8894 | exp->X_op = O_subtract; |
8895 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 8896 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 8897 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
8898 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
8899 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 8900 | else |
29b0f896 | 8901 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 8902 | } |
252b5132 | 8903 | |
3992d3b7 AM |
8904 | else if (exp->X_op == O_absent |
8905 | || exp->X_op == O_illegal | |
ee86248c | 8906 | || exp->X_op == O_big) |
2daf4fd8 | 8907 | { |
3992d3b7 AM |
8908 | inv_disp: |
8909 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 8910 | disp_start); |
3992d3b7 | 8911 | ret = 0; |
2daf4fd8 AM |
8912 | } |
8913 | ||
0e1147d9 L |
8914 | else if (flag_code == CODE_64BIT |
8915 | && !i.prefix[ADDR_PREFIX] | |
8916 | && exp->X_op == O_constant) | |
8917 | { | |
8918 | /* Since displacement is signed extended to 64bit, don't allow | |
8919 | disp32 and turn off disp32s if they are out of range. */ | |
8920 | i.types[this_operand].bitfield.disp32 = 0; | |
8921 | if (!fits_in_signed_long (exp->X_add_number)) | |
8922 | { | |
8923 | i.types[this_operand].bitfield.disp32s = 0; | |
8924 | if (i.types[this_operand].bitfield.baseindex) | |
8925 | { | |
8926 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
8927 | (long) exp->X_add_number); | |
8928 | ret = 0; | |
8929 | } | |
8930 | } | |
8931 | } | |
8932 | ||
4c63da97 | 8933 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
8934 | else if (exp->X_op != O_constant |
8935 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
8936 | && exp_seg != absolute_section | |
8937 | && exp_seg != text_section | |
8938 | && exp_seg != data_section | |
8939 | && exp_seg != bss_section | |
8940 | && exp_seg != undefined_section | |
8941 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 8942 | { |
d0b47220 | 8943 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 8944 | ret = 0; |
24eab124 | 8945 | } |
252b5132 | 8946 | #endif |
3956db08 | 8947 | |
40fb9820 L |
8948 | /* Check if this is a displacement only operand. */ |
8949 | bigdisp = i.types[this_operand]; | |
8950 | bigdisp.bitfield.disp8 = 0; | |
8951 | bigdisp.bitfield.disp16 = 0; | |
8952 | bigdisp.bitfield.disp32 = 0; | |
8953 | bigdisp.bitfield.disp32s = 0; | |
8954 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 8955 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
8956 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8957 | types); | |
3956db08 | 8958 | |
3992d3b7 | 8959 | return ret; |
252b5132 RH |
8960 | } |
8961 | ||
2abc2bec JB |
8962 | /* Return the active addressing mode, taking address override and |
8963 | registers forming the address into consideration. Update the | |
8964 | address override prefix if necessary. */ | |
47926f60 | 8965 | |
2abc2bec JB |
8966 | static enum flag_code |
8967 | i386_addressing_mode (void) | |
252b5132 | 8968 | { |
be05d201 L |
8969 | enum flag_code addr_mode; |
8970 | ||
8971 | if (i.prefix[ADDR_PREFIX]) | |
8972 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
8973 | else | |
8974 | { | |
8975 | addr_mode = flag_code; | |
8976 | ||
24eab124 | 8977 | #if INFER_ADDR_PREFIX |
be05d201 L |
8978 | if (i.mem_operands == 0) |
8979 | { | |
8980 | /* Infer address prefix from the first memory operand. */ | |
8981 | const reg_entry *addr_reg = i.base_reg; | |
8982 | ||
8983 | if (addr_reg == NULL) | |
8984 | addr_reg = i.index_reg; | |
eecb386c | 8985 | |
be05d201 L |
8986 | if (addr_reg) |
8987 | { | |
8988 | if (addr_reg->reg_num == RegEip | |
8989 | || addr_reg->reg_num == RegEiz | |
dc821c5f | 8990 | || addr_reg->reg_type.bitfield.dword) |
be05d201 L |
8991 | addr_mode = CODE_32BIT; |
8992 | else if (flag_code != CODE_64BIT | |
dc821c5f | 8993 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
8994 | addr_mode = CODE_16BIT; |
8995 | ||
8996 | if (addr_mode != flag_code) | |
8997 | { | |
8998 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
8999 | i.prefixes += 1; | |
9000 | /* Change the size of any displacement too. At most one | |
9001 | of Disp16 or Disp32 is set. | |
9002 | FIXME. There doesn't seem to be any real need for | |
9003 | separate Disp16 and Disp32 flags. The same goes for | |
9004 | Imm16 and Imm32. Removing them would probably clean | |
9005 | up the code quite a lot. */ | |
9006 | if (flag_code != CODE_64BIT | |
9007 | && (i.types[this_operand].bitfield.disp16 | |
9008 | || i.types[this_operand].bitfield.disp32)) | |
9009 | i.types[this_operand] | |
9010 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9011 | } | |
9012 | } | |
9013 | } | |
24eab124 | 9014 | #endif |
be05d201 L |
9015 | } |
9016 | ||
2abc2bec JB |
9017 | return addr_mode; |
9018 | } | |
9019 | ||
9020 | /* Make sure the memory operand we've been dealt is valid. | |
9021 | Return 1 on success, 0 on a failure. */ | |
9022 | ||
9023 | static int | |
9024 | i386_index_check (const char *operand_string) | |
9025 | { | |
9026 | const char *kind = "base/index"; | |
9027 | enum flag_code addr_mode = i386_addressing_mode (); | |
9028 | ||
fc0763e6 JB |
9029 | if (current_templates->start->opcode_modifier.isstring |
9030 | && !current_templates->start->opcode_modifier.immext | |
9031 | && (current_templates->end[-1].opcode_modifier.isstring | |
9032 | || i.mem_operands)) | |
9033 | { | |
9034 | /* Memory operands of string insns are special in that they only allow | |
9035 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9036 | const reg_entry *expected_reg; |
9037 | static const char *di_si[][2] = | |
9038 | { | |
9039 | { "esi", "edi" }, | |
9040 | { "si", "di" }, | |
9041 | { "rsi", "rdi" } | |
9042 | }; | |
9043 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9044 | |
9045 | kind = "string address"; | |
9046 | ||
8325cc63 | 9047 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9048 | { |
9049 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9050 | ||
9051 | if (!type.bitfield.baseindex | |
9052 | || ((!i.mem_operands != !intel_syntax) | |
9053 | && current_templates->end[-1].operand_types[1] | |
9054 | .bitfield.baseindex)) | |
9055 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9056 | expected_reg = hash_find (reg_hash, |
9057 | di_si[addr_mode][type.bitfield.esseg]); | |
9058 | ||
fc0763e6 JB |
9059 | } |
9060 | else | |
be05d201 | 9061 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9062 | |
be05d201 L |
9063 | if (i.base_reg != expected_reg |
9064 | || i.index_reg | |
fc0763e6 | 9065 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9066 | { |
be05d201 L |
9067 | /* The second memory operand must have the same size as |
9068 | the first one. */ | |
9069 | if (i.mem_operands | |
9070 | && i.base_reg | |
9071 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9072 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9073 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9074 | ? i.base_reg->reg_type.bitfield.dword |
9075 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9076 | goto bad_address; |
9077 | ||
fc0763e6 JB |
9078 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9079 | operand_string, | |
9080 | intel_syntax ? '[' : '(', | |
9081 | register_prefix, | |
be05d201 | 9082 | expected_reg->reg_name, |
fc0763e6 | 9083 | intel_syntax ? ']' : ')'); |
be05d201 | 9084 | return 1; |
fc0763e6 | 9085 | } |
be05d201 L |
9086 | else |
9087 | return 1; | |
9088 | ||
9089 | bad_address: | |
9090 | as_bad (_("`%s' is not a valid %s expression"), | |
9091 | operand_string, kind); | |
9092 | return 0; | |
3e73aa7c JH |
9093 | } |
9094 | else | |
9095 | { | |
be05d201 L |
9096 | if (addr_mode != CODE_16BIT) |
9097 | { | |
9098 | /* 32-bit/64-bit checks. */ | |
9099 | if ((i.base_reg | |
9100 | && (addr_mode == CODE_64BIT | |
dc821c5f JB |
9101 | ? !i.base_reg->reg_type.bitfield.qword |
9102 | : !i.base_reg->reg_type.bitfield.dword) | |
be05d201 L |
9103 | && (i.index_reg |
9104 | || (i.base_reg->reg_num | |
9105 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
9106 | || (i.index_reg | |
1b54b8d7 JB |
9107 | && !i.index_reg->reg_type.bitfield.xmmword |
9108 | && !i.index_reg->reg_type.bitfield.ymmword | |
9109 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9110 | && ((addr_mode == CODE_64BIT |
dc821c5f | 9111 | ? !(i.index_reg->reg_type.bitfield.qword |
be05d201 | 9112 | || i.index_reg->reg_num == RegRiz) |
dc821c5f | 9113 | : !(i.index_reg->reg_type.bitfield.dword |
be05d201 L |
9114 | || i.index_reg->reg_num == RegEiz)) |
9115 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
9116 | goto bad_address; | |
8178be5b JB |
9117 | |
9118 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9119 | if (current_templates->start->base_opcode == 0xf30f1b | |
9120 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9121 | { | |
9122 | /* They cannot use RIP-relative addressing. */ | |
9123 | if (i.base_reg && i.base_reg->reg_num == RegRip) | |
9124 | { | |
9125 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9126 | return 0; | |
9127 | } | |
9128 | ||
9129 | /* bndldx and bndstx ignore their scale factor. */ | |
9130 | if (current_templates->start->base_opcode != 0xf30f1b | |
9131 | && i.log2_scale_factor) | |
9132 | as_warn (_("register scaling is being ignored here")); | |
9133 | } | |
be05d201 L |
9134 | } |
9135 | else | |
3e73aa7c | 9136 | { |
be05d201 | 9137 | /* 16-bit checks. */ |
3e73aa7c | 9138 | if ((i.base_reg |
dc821c5f | 9139 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9140 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9141 | || (i.index_reg |
dc821c5f | 9142 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9143 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9144 | || !(i.base_reg |
9145 | && i.base_reg->reg_num < 6 | |
9146 | && i.index_reg->reg_num >= 6 | |
9147 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9148 | goto bad_address; |
3e73aa7c JH |
9149 | } |
9150 | } | |
be05d201 | 9151 | return 1; |
24eab124 | 9152 | } |
252b5132 | 9153 | |
43234a1e L |
9154 | /* Handle vector immediates. */ |
9155 | ||
9156 | static int | |
9157 | RC_SAE_immediate (const char *imm_start) | |
9158 | { | |
9159 | unsigned int match_found, j; | |
9160 | const char *pstr = imm_start; | |
9161 | expressionS *exp; | |
9162 | ||
9163 | if (*pstr != '{') | |
9164 | return 0; | |
9165 | ||
9166 | pstr++; | |
9167 | match_found = 0; | |
9168 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9169 | { | |
9170 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9171 | { | |
9172 | if (!i.rounding) | |
9173 | { | |
9174 | rc_op.type = RC_NamesTable[j].type; | |
9175 | rc_op.operand = this_operand; | |
9176 | i.rounding = &rc_op; | |
9177 | } | |
9178 | else | |
9179 | { | |
9180 | as_bad (_("duplicated `%s'"), imm_start); | |
9181 | return 0; | |
9182 | } | |
9183 | pstr += RC_NamesTable[j].len; | |
9184 | match_found = 1; | |
9185 | break; | |
9186 | } | |
9187 | } | |
9188 | if (!match_found) | |
9189 | return 0; | |
9190 | ||
9191 | if (*pstr++ != '}') | |
9192 | { | |
9193 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9194 | return 0; | |
9195 | } | |
9196 | /* RC/SAE immediate string should contain nothing more. */; | |
9197 | if (*pstr != 0) | |
9198 | { | |
9199 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9200 | return 0; | |
9201 | } | |
9202 | ||
9203 | exp = &im_expressions[i.imm_operands++]; | |
9204 | i.op[this_operand].imms = exp; | |
9205 | ||
9206 | exp->X_op = O_constant; | |
9207 | exp->X_add_number = 0; | |
9208 | exp->X_add_symbol = (symbolS *) 0; | |
9209 | exp->X_op_symbol = (symbolS *) 0; | |
9210 | ||
9211 | i.types[this_operand].bitfield.imm8 = 1; | |
9212 | return 1; | |
9213 | } | |
9214 | ||
8325cc63 JB |
9215 | /* Only string instructions can have a second memory operand, so |
9216 | reduce current_templates to just those if it contains any. */ | |
9217 | static int | |
9218 | maybe_adjust_templates (void) | |
9219 | { | |
9220 | const insn_template *t; | |
9221 | ||
9222 | gas_assert (i.mem_operands == 1); | |
9223 | ||
9224 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9225 | if (t->opcode_modifier.isstring) | |
9226 | break; | |
9227 | ||
9228 | if (t < current_templates->end) | |
9229 | { | |
9230 | static templates aux_templates; | |
9231 | bfd_boolean recheck; | |
9232 | ||
9233 | aux_templates.start = t; | |
9234 | for (; t < current_templates->end; ++t) | |
9235 | if (!t->opcode_modifier.isstring) | |
9236 | break; | |
9237 | aux_templates.end = t; | |
9238 | ||
9239 | /* Determine whether to re-check the first memory operand. */ | |
9240 | recheck = (aux_templates.start != current_templates->start | |
9241 | || t != current_templates->end); | |
9242 | ||
9243 | current_templates = &aux_templates; | |
9244 | ||
9245 | if (recheck) | |
9246 | { | |
9247 | i.mem_operands = 0; | |
9248 | if (i.memop1_string != NULL | |
9249 | && i386_index_check (i.memop1_string) == 0) | |
9250 | return 0; | |
9251 | i.mem_operands = 1; | |
9252 | } | |
9253 | } | |
9254 | ||
9255 | return 1; | |
9256 | } | |
9257 | ||
fc0763e6 | 9258 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9259 | on error. */ |
252b5132 | 9260 | |
252b5132 | 9261 | static int |
a7619375 | 9262 | i386_att_operand (char *operand_string) |
252b5132 | 9263 | { |
af6bdddf AM |
9264 | const reg_entry *r; |
9265 | char *end_op; | |
24eab124 | 9266 | char *op_string = operand_string; |
252b5132 | 9267 | |
24eab124 | 9268 | if (is_space_char (*op_string)) |
252b5132 RH |
9269 | ++op_string; |
9270 | ||
24eab124 | 9271 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9272 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9273 | if (*op_string == ABSOLUTE_PREFIX) |
9274 | { | |
9275 | ++op_string; | |
9276 | if (is_space_char (*op_string)) | |
9277 | ++op_string; | |
40fb9820 | 9278 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9279 | } |
252b5132 | 9280 | |
47926f60 | 9281 | /* Check if operand is a register. */ |
4d1bb795 | 9282 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9283 | { |
40fb9820 L |
9284 | i386_operand_type temp; |
9285 | ||
24eab124 AM |
9286 | /* Check for a segment override by searching for ':' after a |
9287 | segment register. */ | |
9288 | op_string = end_op; | |
9289 | if (is_space_char (*op_string)) | |
9290 | ++op_string; | |
40fb9820 L |
9291 | if (*op_string == ':' |
9292 | && (r->reg_type.bitfield.sreg2 | |
9293 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9294 | { |
9295 | switch (r->reg_num) | |
9296 | { | |
9297 | case 0: | |
9298 | i.seg[i.mem_operands] = &es; | |
9299 | break; | |
9300 | case 1: | |
9301 | i.seg[i.mem_operands] = &cs; | |
9302 | break; | |
9303 | case 2: | |
9304 | i.seg[i.mem_operands] = &ss; | |
9305 | break; | |
9306 | case 3: | |
9307 | i.seg[i.mem_operands] = &ds; | |
9308 | break; | |
9309 | case 4: | |
9310 | i.seg[i.mem_operands] = &fs; | |
9311 | break; | |
9312 | case 5: | |
9313 | i.seg[i.mem_operands] = &gs; | |
9314 | break; | |
9315 | } | |
252b5132 | 9316 | |
24eab124 | 9317 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
9318 | ++op_string; |
9319 | if (is_space_char (*op_string)) | |
24eab124 | 9320 | ++op_string; |
252b5132 | 9321 | |
24eab124 AM |
9322 | if (!is_digit_char (*op_string) |
9323 | && !is_identifier_char (*op_string) | |
9324 | && *op_string != '(' | |
9325 | && *op_string != ABSOLUTE_PREFIX) | |
9326 | { | |
9327 | as_bad (_("bad memory operand `%s'"), op_string); | |
9328 | return 0; | |
9329 | } | |
47926f60 | 9330 | /* Handle case of %es:*foo. */ |
24eab124 AM |
9331 | if (*op_string == ABSOLUTE_PREFIX) |
9332 | { | |
9333 | ++op_string; | |
9334 | if (is_space_char (*op_string)) | |
9335 | ++op_string; | |
40fb9820 | 9336 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
9337 | } |
9338 | goto do_memory_reference; | |
9339 | } | |
43234a1e L |
9340 | |
9341 | /* Handle vector operations. */ | |
9342 | if (*op_string == '{') | |
9343 | { | |
9344 | op_string = check_VecOperations (op_string, NULL); | |
9345 | if (op_string == NULL) | |
9346 | return 0; | |
9347 | } | |
9348 | ||
24eab124 AM |
9349 | if (*op_string) |
9350 | { | |
d0b47220 | 9351 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9352 | return 0; |
9353 | } | |
40fb9820 L |
9354 | temp = r->reg_type; |
9355 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9356 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9357 | temp); | |
7d5e4556 | 9358 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 9359 | i.op[this_operand].regs = r; |
24eab124 AM |
9360 | i.reg_operands++; |
9361 | } | |
af6bdddf AM |
9362 | else if (*op_string == REGISTER_PREFIX) |
9363 | { | |
9364 | as_bad (_("bad register name `%s'"), op_string); | |
9365 | return 0; | |
9366 | } | |
24eab124 | 9367 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 9368 | { |
24eab124 | 9369 | ++op_string; |
40fb9820 | 9370 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 9371 | { |
d0b47220 | 9372 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
9373 | return 0; |
9374 | } | |
9375 | if (!i386_immediate (op_string)) | |
9376 | return 0; | |
9377 | } | |
43234a1e L |
9378 | else if (RC_SAE_immediate (operand_string)) |
9379 | { | |
9380 | /* If it is a RC or SAE immediate, do nothing. */ | |
9381 | ; | |
9382 | } | |
24eab124 AM |
9383 | else if (is_digit_char (*op_string) |
9384 | || is_identifier_char (*op_string) | |
d02603dc | 9385 | || *op_string == '"' |
e5cb08ac | 9386 | || *op_string == '(') |
24eab124 | 9387 | { |
47926f60 | 9388 | /* This is a memory reference of some sort. */ |
af6bdddf | 9389 | char *base_string; |
252b5132 | 9390 | |
47926f60 | 9391 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
9392 | char *displacement_string_start; |
9393 | char *displacement_string_end; | |
43234a1e | 9394 | char *vop_start; |
252b5132 | 9395 | |
24eab124 | 9396 | do_memory_reference: |
8325cc63 JB |
9397 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
9398 | return 0; | |
24eab124 | 9399 | if ((i.mem_operands == 1 |
40fb9820 | 9400 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
9401 | || i.mem_operands == 2) |
9402 | { | |
9403 | as_bad (_("too many memory references for `%s'"), | |
9404 | current_templates->start->name); | |
9405 | return 0; | |
9406 | } | |
252b5132 | 9407 | |
24eab124 AM |
9408 | /* Check for base index form. We detect the base index form by |
9409 | looking for an ')' at the end of the operand, searching | |
9410 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
9411 | after the '('. */ | |
af6bdddf | 9412 | base_string = op_string + strlen (op_string); |
c3332e24 | 9413 | |
43234a1e L |
9414 | /* Handle vector operations. */ |
9415 | vop_start = strchr (op_string, '{'); | |
9416 | if (vop_start && vop_start < base_string) | |
9417 | { | |
9418 | if (check_VecOperations (vop_start, base_string) == NULL) | |
9419 | return 0; | |
9420 | base_string = vop_start; | |
9421 | } | |
9422 | ||
af6bdddf AM |
9423 | --base_string; |
9424 | if (is_space_char (*base_string)) | |
9425 | --base_string; | |
252b5132 | 9426 | |
47926f60 | 9427 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
9428 | displacement_string_start = op_string; |
9429 | displacement_string_end = base_string + 1; | |
252b5132 | 9430 | |
24eab124 AM |
9431 | if (*base_string == ')') |
9432 | { | |
af6bdddf | 9433 | char *temp_string; |
24eab124 AM |
9434 | unsigned int parens_balanced = 1; |
9435 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 9436 | equal, so this loop will not be infinite. */ |
24eab124 AM |
9437 | do |
9438 | { | |
9439 | base_string--; | |
9440 | if (*base_string == ')') | |
9441 | parens_balanced++; | |
9442 | if (*base_string == '(') | |
9443 | parens_balanced--; | |
9444 | } | |
9445 | while (parens_balanced); | |
c3332e24 | 9446 | |
af6bdddf | 9447 | temp_string = base_string; |
c3332e24 | 9448 | |
24eab124 | 9449 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
9450 | ++base_string; |
9451 | if (is_space_char (*base_string)) | |
24eab124 | 9452 | ++base_string; |
252b5132 | 9453 | |
af6bdddf | 9454 | if (*base_string == ',' |
4eed87de AM |
9455 | || ((i.base_reg = parse_register (base_string, &end_op)) |
9456 | != NULL)) | |
252b5132 | 9457 | { |
af6bdddf | 9458 | displacement_string_end = temp_string; |
252b5132 | 9459 | |
40fb9820 | 9460 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 9461 | |
af6bdddf | 9462 | if (i.base_reg) |
24eab124 | 9463 | { |
24eab124 AM |
9464 | base_string = end_op; |
9465 | if (is_space_char (*base_string)) | |
9466 | ++base_string; | |
af6bdddf AM |
9467 | } |
9468 | ||
9469 | /* There may be an index reg or scale factor here. */ | |
9470 | if (*base_string == ',') | |
9471 | { | |
9472 | ++base_string; | |
9473 | if (is_space_char (*base_string)) | |
9474 | ++base_string; | |
9475 | ||
4eed87de AM |
9476 | if ((i.index_reg = parse_register (base_string, &end_op)) |
9477 | != NULL) | |
24eab124 | 9478 | { |
af6bdddf | 9479 | base_string = end_op; |
24eab124 AM |
9480 | if (is_space_char (*base_string)) |
9481 | ++base_string; | |
af6bdddf AM |
9482 | if (*base_string == ',') |
9483 | { | |
9484 | ++base_string; | |
9485 | if (is_space_char (*base_string)) | |
9486 | ++base_string; | |
9487 | } | |
e5cb08ac | 9488 | else if (*base_string != ')') |
af6bdddf | 9489 | { |
4eed87de AM |
9490 | as_bad (_("expecting `,' or `)' " |
9491 | "after index register in `%s'"), | |
af6bdddf AM |
9492 | operand_string); |
9493 | return 0; | |
9494 | } | |
24eab124 | 9495 | } |
af6bdddf | 9496 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 9497 | { |
f76bf5e0 L |
9498 | end_op = strchr (base_string, ','); |
9499 | if (end_op) | |
9500 | *end_op = '\0'; | |
af6bdddf | 9501 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
9502 | return 0; |
9503 | } | |
252b5132 | 9504 | |
47926f60 | 9505 | /* Check for scale factor. */ |
551c1ca1 | 9506 | if (*base_string != ')') |
af6bdddf | 9507 | { |
551c1ca1 AM |
9508 | char *end_scale = i386_scale (base_string); |
9509 | ||
9510 | if (!end_scale) | |
af6bdddf | 9511 | return 0; |
24eab124 | 9512 | |
551c1ca1 | 9513 | base_string = end_scale; |
af6bdddf AM |
9514 | if (is_space_char (*base_string)) |
9515 | ++base_string; | |
9516 | if (*base_string != ')') | |
9517 | { | |
4eed87de AM |
9518 | as_bad (_("expecting `)' " |
9519 | "after scale factor in `%s'"), | |
af6bdddf AM |
9520 | operand_string); |
9521 | return 0; | |
9522 | } | |
9523 | } | |
9524 | else if (!i.index_reg) | |
24eab124 | 9525 | { |
4eed87de AM |
9526 | as_bad (_("expecting index register or scale factor " |
9527 | "after `,'; got '%c'"), | |
af6bdddf | 9528 | *base_string); |
24eab124 AM |
9529 | return 0; |
9530 | } | |
9531 | } | |
af6bdddf | 9532 | else if (*base_string != ')') |
24eab124 | 9533 | { |
4eed87de AM |
9534 | as_bad (_("expecting `,' or `)' " |
9535 | "after base register in `%s'"), | |
af6bdddf | 9536 | operand_string); |
24eab124 AM |
9537 | return 0; |
9538 | } | |
c3332e24 | 9539 | } |
af6bdddf | 9540 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 9541 | { |
f76bf5e0 L |
9542 | end_op = strchr (base_string, ','); |
9543 | if (end_op) | |
9544 | *end_op = '\0'; | |
af6bdddf | 9545 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9546 | return 0; |
c3332e24 | 9547 | } |
24eab124 AM |
9548 | } |
9549 | ||
9550 | /* If there's an expression beginning the operand, parse it, | |
9551 | assuming displacement_string_start and | |
9552 | displacement_string_end are meaningful. */ | |
9553 | if (displacement_string_start != displacement_string_end) | |
9554 | { | |
9555 | if (!i386_displacement (displacement_string_start, | |
9556 | displacement_string_end)) | |
9557 | return 0; | |
9558 | } | |
9559 | ||
9560 | /* Special case for (%dx) while doing input/output op. */ | |
9561 | if (i.base_reg | |
0dfbf9d7 L |
9562 | && operand_type_equal (&i.base_reg->reg_type, |
9563 | ®16_inoutportreg) | |
24eab124 AM |
9564 | && i.index_reg == 0 |
9565 | && i.log2_scale_factor == 0 | |
9566 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9567 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9568 | { |
65da13b5 | 9569 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
9570 | return 1; |
9571 | } | |
9572 | ||
eecb386c AM |
9573 | if (i386_index_check (operand_string) == 0) |
9574 | return 0; | |
5c07affc | 9575 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9576 | if (i.mem_operands == 0) |
9577 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9578 | i.mem_operands++; |
9579 | } | |
9580 | else | |
ce8a8b2f AM |
9581 | { |
9582 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9583 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9584 | output_invalid (*op_string), | |
9585 | this_operand + 1, | |
9586 | op_string); | |
9587 | return 0; | |
9588 | } | |
47926f60 | 9589 | return 1; /* Normal return. */ |
252b5132 RH |
9590 | } |
9591 | \f | |
fa94de6b RM |
9592 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9593 | that an rs_machine_dependent frag may reach. */ | |
9594 | ||
9595 | unsigned int | |
9596 | i386_frag_max_var (fragS *frag) | |
9597 | { | |
9598 | /* The only relaxable frags are for jumps. | |
9599 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9600 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9601 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9602 | } | |
9603 | ||
b084df0b L |
9604 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9605 | static int | |
8dcea932 | 9606 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9607 | { |
9608 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9609 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9610 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9611 | return 0; | |
9612 | ||
9613 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9614 | /* Symbol may be weak or local. */ | |
9615 | return !S_IS_WEAK (fr_symbol); | |
9616 | ||
8dcea932 L |
9617 | /* Global symbols with non-default visibility can't be preempted. */ |
9618 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9619 | return 1; | |
9620 | ||
9621 | if (fr_var != NO_RELOC) | |
9622 | switch ((enum bfd_reloc_code_real) fr_var) | |
9623 | { | |
9624 | case BFD_RELOC_386_PLT32: | |
9625 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 9626 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
9627 | return 0; |
9628 | default: | |
9629 | abort (); | |
9630 | } | |
9631 | ||
b084df0b L |
9632 | /* Global symbols with default visibility in a shared library may be |
9633 | preempted by another definition. */ | |
8dcea932 | 9634 | return !shared; |
b084df0b L |
9635 | } |
9636 | #endif | |
9637 | ||
ee7fcc42 AM |
9638 | /* md_estimate_size_before_relax() |
9639 | ||
9640 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9641 | assembler uses these frags to handle variable size jump | |
9642 | instructions. | |
9643 | ||
9644 | Any symbol that is now undefined will not become defined. | |
9645 | Return the correct fr_subtype in the frag. | |
9646 | Return the initial "guess for variable size of frag" to caller. | |
9647 | The guess is actually the growth beyond the fixed part. Whatever | |
9648 | we do to grow the fixed or variable part contributes to our | |
9649 | returned value. */ | |
9650 | ||
252b5132 | 9651 | int |
7016a5d5 | 9652 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9653 | { |
252b5132 | 9654 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9655 | check for un-relaxable symbols. On an ELF system, we can't relax |
9656 | an externally visible symbol, because it may be overridden by a | |
9657 | shared library. */ | |
9658 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9659 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9660 | || (IS_ELF |
8dcea932 L |
9661 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9662 | fragP->fr_var)) | |
fbeb56a4 DK |
9663 | #endif |
9664 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9665 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9666 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9667 | #endif |
9668 | ) | |
252b5132 | 9669 | { |
b98ef147 AM |
9670 | /* Symbol is undefined in this segment, or we need to keep a |
9671 | reloc so that weak symbols can be overridden. */ | |
9672 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9673 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9674 | unsigned char *opcode; |
9675 | int old_fr_fix; | |
f6af82bd | 9676 | |
ee7fcc42 | 9677 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9678 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9679 | else if (size == 2) |
f6af82bd | 9680 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
9681 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9682 | else if (need_plt32_p (fragP->fr_symbol)) | |
9683 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
9684 | #endif | |
f6af82bd AM |
9685 | else |
9686 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9687 | |
ee7fcc42 AM |
9688 | old_fr_fix = fragP->fr_fix; |
9689 | opcode = (unsigned char *) fragP->fr_opcode; | |
9690 | ||
fddf5b5b | 9691 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9692 | { |
fddf5b5b AM |
9693 | case UNCOND_JUMP: |
9694 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9695 | opcode[0] = 0xe9; |
252b5132 | 9696 | fragP->fr_fix += size; |
062cd5e7 AS |
9697 | fix_new (fragP, old_fr_fix, size, |
9698 | fragP->fr_symbol, | |
9699 | fragP->fr_offset, 1, | |
9700 | reloc_type); | |
252b5132 RH |
9701 | break; |
9702 | ||
fddf5b5b | 9703 | case COND_JUMP86: |
412167cb AM |
9704 | if (size == 2 |
9705 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9706 | { |
9707 | /* Negate the condition, and branch past an | |
9708 | unconditional jump. */ | |
9709 | opcode[0] ^= 1; | |
9710 | opcode[1] = 3; | |
9711 | /* Insert an unconditional jump. */ | |
9712 | opcode[2] = 0xe9; | |
9713 | /* We added two extra opcode bytes, and have a two byte | |
9714 | offset. */ | |
9715 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9716 | fix_new (fragP, old_fr_fix + 2, 2, |
9717 | fragP->fr_symbol, | |
9718 | fragP->fr_offset, 1, | |
9719 | reloc_type); | |
fddf5b5b AM |
9720 | break; |
9721 | } | |
9722 | /* Fall through. */ | |
9723 | ||
9724 | case COND_JUMP: | |
412167cb AM |
9725 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9726 | { | |
3e02c1cc AM |
9727 | fixS *fixP; |
9728 | ||
412167cb | 9729 | fragP->fr_fix += 1; |
3e02c1cc AM |
9730 | fixP = fix_new (fragP, old_fr_fix, 1, |
9731 | fragP->fr_symbol, | |
9732 | fragP->fr_offset, 1, | |
9733 | BFD_RELOC_8_PCREL); | |
9734 | fixP->fx_signed = 1; | |
412167cb AM |
9735 | break; |
9736 | } | |
93c2a809 | 9737 | |
24eab124 | 9738 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9739 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9740 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9741 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9742 | /* We've added an opcode byte. */ |
9743 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9744 | fix_new (fragP, old_fr_fix + 1, size, |
9745 | fragP->fr_symbol, | |
9746 | fragP->fr_offset, 1, | |
9747 | reloc_type); | |
252b5132 | 9748 | break; |
fddf5b5b AM |
9749 | |
9750 | default: | |
9751 | BAD_CASE (fragP->fr_subtype); | |
9752 | break; | |
252b5132 RH |
9753 | } |
9754 | frag_wane (fragP); | |
ee7fcc42 | 9755 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9756 | } |
93c2a809 | 9757 | |
93c2a809 AM |
9758 | /* Guess size depending on current relax state. Initially the relax |
9759 | state will correspond to a short jump and we return 1, because | |
9760 | the variable part of the frag (the branch offset) is one byte | |
9761 | long. However, we can relax a section more than once and in that | |
9762 | case we must either set fr_subtype back to the unrelaxed state, | |
9763 | or return the value for the appropriate branch. */ | |
9764 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9765 | } |
9766 | ||
47926f60 KH |
9767 | /* Called after relax() is finished. |
9768 | ||
9769 | In: Address of frag. | |
9770 | fr_type == rs_machine_dependent. | |
9771 | fr_subtype is what the address relaxed to. | |
9772 | ||
9773 | Out: Any fixSs and constants are set up. | |
9774 | Caller will turn frag into a ".space 0". */ | |
9775 | ||
252b5132 | 9776 | void |
7016a5d5 TG |
9777 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9778 | fragS *fragP) | |
252b5132 | 9779 | { |
29b0f896 | 9780 | unsigned char *opcode; |
252b5132 | 9781 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9782 | offsetT target_address; |
9783 | offsetT opcode_address; | |
252b5132 | 9784 | unsigned int extension = 0; |
847f7ad4 | 9785 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9786 | |
9787 | opcode = (unsigned char *) fragP->fr_opcode; | |
9788 | ||
47926f60 | 9789 | /* Address we want to reach in file space. */ |
252b5132 | 9790 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9791 | |
47926f60 | 9792 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9793 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9794 | ||
47926f60 | 9795 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9796 | displacement_from_opcode_start = target_address - opcode_address; |
9797 | ||
fddf5b5b | 9798 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9799 | { |
47926f60 KH |
9800 | /* Don't have to change opcode. */ |
9801 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9802 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9803 | } |
9804 | else | |
9805 | { | |
9806 | if (no_cond_jump_promotion | |
9807 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9808 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9809 | _("long jump required")); | |
252b5132 | 9810 | |
fddf5b5b AM |
9811 | switch (fragP->fr_subtype) |
9812 | { | |
9813 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
9814 | extension = 4; /* 1 opcode + 4 displacement */ | |
9815 | opcode[0] = 0xe9; | |
9816 | where_to_put_displacement = &opcode[1]; | |
9817 | break; | |
252b5132 | 9818 | |
fddf5b5b AM |
9819 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
9820 | extension = 2; /* 1 opcode + 2 displacement */ | |
9821 | opcode[0] = 0xe9; | |
9822 | where_to_put_displacement = &opcode[1]; | |
9823 | break; | |
252b5132 | 9824 | |
fddf5b5b AM |
9825 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
9826 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
9827 | extension = 5; /* 2 opcode + 4 displacement */ | |
9828 | opcode[1] = opcode[0] + 0x10; | |
9829 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9830 | where_to_put_displacement = &opcode[2]; | |
9831 | break; | |
252b5132 | 9832 | |
fddf5b5b AM |
9833 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
9834 | extension = 3; /* 2 opcode + 2 displacement */ | |
9835 | opcode[1] = opcode[0] + 0x10; | |
9836 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9837 | where_to_put_displacement = &opcode[2]; | |
9838 | break; | |
252b5132 | 9839 | |
fddf5b5b AM |
9840 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
9841 | extension = 4; | |
9842 | opcode[0] ^= 1; | |
9843 | opcode[1] = 3; | |
9844 | opcode[2] = 0xe9; | |
9845 | where_to_put_displacement = &opcode[3]; | |
9846 | break; | |
9847 | ||
9848 | default: | |
9849 | BAD_CASE (fragP->fr_subtype); | |
9850 | break; | |
9851 | } | |
252b5132 | 9852 | } |
fddf5b5b | 9853 | |
7b81dfbb AJ |
9854 | /* If size if less then four we are sure that the operand fits, |
9855 | but if it's 4, then it could be that the displacement is larger | |
9856 | then -/+ 2GB. */ | |
9857 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
9858 | && object_64bit | |
9859 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
9860 | + ((addressT) 1 << 31)) |
9861 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
9862 | { |
9863 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9864 | _("jump target out of range")); | |
9865 | /* Make us emit 0. */ | |
9866 | displacement_from_opcode_start = extension; | |
9867 | } | |
47926f60 | 9868 | /* Now put displacement after opcode. */ |
252b5132 RH |
9869 | md_number_to_chars ((char *) where_to_put_displacement, |
9870 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 9871 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
9872 | fragP->fr_fix += extension; |
9873 | } | |
9874 | \f | |
7016a5d5 | 9875 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
9876 | by our caller that we have all the info we need to fix it up. |
9877 | ||
7016a5d5 TG |
9878 | Parameter valP is the pointer to the value of the bits. |
9879 | ||
252b5132 RH |
9880 | On the 386, immediates, displacements, and data pointers are all in |
9881 | the same (little-endian) format, so we don't need to care about which | |
9882 | we are handling. */ | |
9883 | ||
94f592af | 9884 | void |
7016a5d5 | 9885 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 9886 | { |
94f592af | 9887 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 9888 | valueT value = *valP; |
252b5132 | 9889 | |
f86103b7 | 9890 | #if !defined (TE_Mach) |
93382f6d AM |
9891 | if (fixP->fx_pcrel) |
9892 | { | |
9893 | switch (fixP->fx_r_type) | |
9894 | { | |
5865bb77 ILT |
9895 | default: |
9896 | break; | |
9897 | ||
d6ab8113 JB |
9898 | case BFD_RELOC_64: |
9899 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
9900 | break; | |
93382f6d | 9901 | case BFD_RELOC_32: |
ae8887b5 | 9902 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
9903 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
9904 | break; | |
9905 | case BFD_RELOC_16: | |
9906 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
9907 | break; | |
9908 | case BFD_RELOC_8: | |
9909 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
9910 | break; | |
9911 | } | |
9912 | } | |
252b5132 | 9913 | |
a161fe53 | 9914 | if (fixP->fx_addsy != NULL |
31312f95 | 9915 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 9916 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 9917 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 9918 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 9919 | && !use_rela_relocations) |
252b5132 | 9920 | { |
31312f95 AM |
9921 | /* This is a hack. There should be a better way to handle this. |
9922 | This covers for the fact that bfd_install_relocation will | |
9923 | subtract the current location (for partial_inplace, PC relative | |
9924 | relocations); see more below. */ | |
252b5132 | 9925 | #ifndef OBJ_AOUT |
718ddfc0 | 9926 | if (IS_ELF |
252b5132 RH |
9927 | #ifdef TE_PE |
9928 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
9929 | #endif | |
9930 | ) | |
9931 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9932 | #endif | |
9933 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 9934 | if (IS_ELF) |
252b5132 | 9935 | { |
6539b54b | 9936 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 9937 | |
6539b54b | 9938 | if ((sym_seg == seg |
2f66722d | 9939 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 9940 | && sym_seg != absolute_section)) |
af65af87 | 9941 | && !generic_force_reloc (fixP)) |
2f66722d AM |
9942 | { |
9943 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
9944 | bfd_install_relocation subtracts them out again. I think |
9945 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
9946 | it. FIXME. */ |
9947 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9948 | } | |
252b5132 RH |
9949 | } |
9950 | #endif | |
9951 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
9952 | /* For some reason, the PE format does not store a |
9953 | section address offset for a PC relative symbol. */ | |
9954 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 9955 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
9956 | value += md_pcrel_from (fixP); |
9957 | #endif | |
9958 | } | |
fbeb56a4 | 9959 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
9960 | if (fixP->fx_addsy != NULL |
9961 | && S_IS_WEAK (fixP->fx_addsy) | |
9962 | /* PR 16858: Do not modify weak function references. */ | |
9963 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 9964 | { |
296a8689 NC |
9965 | #if !defined (TE_PEP) |
9966 | /* For x86 PE weak function symbols are neither PC-relative | |
9967 | nor do they set S_IS_FUNCTION. So the only reliable way | |
9968 | to detect them is to check the flags of their containing | |
9969 | section. */ | |
9970 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
9971 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
9972 | ; | |
9973 | else | |
9974 | #endif | |
fbeb56a4 DK |
9975 | value -= S_GET_VALUE (fixP->fx_addsy); |
9976 | } | |
9977 | #endif | |
252b5132 RH |
9978 | |
9979 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 9980 | and we must not disappoint it. */ |
252b5132 | 9981 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9982 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
9983 | switch (fixP->fx_r_type) |
9984 | { | |
9985 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 9986 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
9987 | /* Make the jump instruction point to the address of the operand. At |
9988 | runtime we merely add the offset to the actual PLT entry. */ | |
9989 | value = -4; | |
9990 | break; | |
31312f95 | 9991 | |
13ae64f3 JJ |
9992 | case BFD_RELOC_386_TLS_GD: |
9993 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 9994 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
9995 | case BFD_RELOC_386_TLS_IE: |
9996 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 9997 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
9998 | case BFD_RELOC_X86_64_TLSGD: |
9999 | case BFD_RELOC_X86_64_TLSLD: | |
10000 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10001 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10002 | value = 0; /* Fully resolved at runtime. No addend. */ |
10003 | /* Fallthrough */ | |
10004 | case BFD_RELOC_386_TLS_LE: | |
10005 | case BFD_RELOC_386_TLS_LDO_32: | |
10006 | case BFD_RELOC_386_TLS_LE_32: | |
10007 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10008 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10009 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10010 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10011 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10012 | break; | |
10013 | ||
67a4f2b7 AO |
10014 | case BFD_RELOC_386_TLS_DESC_CALL: |
10015 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10016 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10017 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10018 | fixP->fx_done = 0; | |
10019 | return; | |
10020 | ||
47926f60 KH |
10021 | case BFD_RELOC_VTABLE_INHERIT: |
10022 | case BFD_RELOC_VTABLE_ENTRY: | |
10023 | fixP->fx_done = 0; | |
94f592af | 10024 | return; |
47926f60 KH |
10025 | |
10026 | default: | |
10027 | break; | |
10028 | } | |
10029 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10030 | *valP = value; |
f86103b7 | 10031 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10032 | |
3e73aa7c | 10033 | /* Are we finished with this relocation now? */ |
c6682705 | 10034 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10035 | fixP->fx_done = 1; |
fbeb56a4 DK |
10036 | #if defined (OBJ_COFF) && defined (TE_PE) |
10037 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10038 | { | |
10039 | fixP->fx_done = 0; | |
10040 | /* Remember value for tc_gen_reloc. */ | |
10041 | fixP->fx_addnumber = value; | |
10042 | /* Clear out the frag for now. */ | |
10043 | value = 0; | |
10044 | } | |
10045 | #endif | |
3e73aa7c JH |
10046 | else if (use_rela_relocations) |
10047 | { | |
10048 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10049 | /* Remember value for tc_gen_reloc. */ |
10050 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10051 | value = 0; |
10052 | } | |
f86103b7 | 10053 | |
94f592af | 10054 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10055 | } |
252b5132 | 10056 | \f |
6d4af3c2 | 10057 | const char * |
499ac353 | 10058 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10059 | { |
499ac353 NC |
10060 | /* This outputs the LITTLENUMs in REVERSE order; |
10061 | in accord with the bigendian 386. */ | |
10062 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10063 | } |
10064 | \f | |
2d545b82 | 10065 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10066 | |
252b5132 | 10067 | static char * |
e3bb37b5 | 10068 | output_invalid (int c) |
252b5132 | 10069 | { |
3882b010 | 10070 | if (ISPRINT (c)) |
f9f21a03 L |
10071 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10072 | "'%c'", c); | |
252b5132 | 10073 | else |
f9f21a03 | 10074 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10075 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10076 | return output_invalid_buf; |
10077 | } | |
10078 | ||
af6bdddf | 10079 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10080 | |
10081 | static const reg_entry * | |
4d1bb795 | 10082 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10083 | { |
af6bdddf AM |
10084 | char *s = reg_string; |
10085 | char *p; | |
252b5132 RH |
10086 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10087 | const reg_entry *r; | |
10088 | ||
10089 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10090 | if (*s == REGISTER_PREFIX) | |
10091 | ++s; | |
10092 | ||
10093 | if (is_space_char (*s)) | |
10094 | ++s; | |
10095 | ||
10096 | p = reg_name_given; | |
af6bdddf | 10097 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10098 | { |
10099 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10100 | return (const reg_entry *) NULL; |
10101 | s++; | |
252b5132 RH |
10102 | } |
10103 | ||
6588847e DN |
10104 | /* For naked regs, make sure that we are not dealing with an identifier. |
10105 | This prevents confusing an identifier like `eax_var' with register | |
10106 | `eax'. */ | |
10107 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10108 | return (const reg_entry *) NULL; | |
10109 | ||
af6bdddf | 10110 | *end_op = s; |
252b5132 RH |
10111 | |
10112 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10113 | ||
5f47d35b | 10114 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10115 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10116 | { |
5f47d35b AM |
10117 | if (is_space_char (*s)) |
10118 | ++s; | |
10119 | if (*s == '(') | |
10120 | { | |
af6bdddf | 10121 | ++s; |
5f47d35b AM |
10122 | if (is_space_char (*s)) |
10123 | ++s; | |
10124 | if (*s >= '0' && *s <= '7') | |
10125 | { | |
db557034 | 10126 | int fpr = *s - '0'; |
af6bdddf | 10127 | ++s; |
5f47d35b AM |
10128 | if (is_space_char (*s)) |
10129 | ++s; | |
10130 | if (*s == ')') | |
10131 | { | |
10132 | *end_op = s + 1; | |
1e9cc1c2 | 10133 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10134 | know (r); |
10135 | return r + fpr; | |
5f47d35b | 10136 | } |
5f47d35b | 10137 | } |
47926f60 | 10138 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10139 | return (const reg_entry *) NULL; |
10140 | } | |
10141 | } | |
10142 | ||
a60de03c JB |
10143 | if (r == NULL || allow_pseudo_reg) |
10144 | return r; | |
10145 | ||
0dfbf9d7 | 10146 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10147 | return (const reg_entry *) NULL; |
10148 | ||
dc821c5f | 10149 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
10150 | || r->reg_type.bitfield.sreg3 |
10151 | || r->reg_type.bitfield.control | |
10152 | || r->reg_type.bitfield.debug | |
10153 | || r->reg_type.bitfield.test) | |
10154 | && !cpu_arch_flags.bitfield.cpui386) | |
10155 | return (const reg_entry *) NULL; | |
10156 | ||
ca0d63fe | 10157 | if (r->reg_type.bitfield.tbyte |
309d3373 JB |
10158 | && !cpu_arch_flags.bitfield.cpu8087 |
10159 | && !cpu_arch_flags.bitfield.cpu287 | |
10160 | && !cpu_arch_flags.bitfield.cpu387) | |
10161 | return (const reg_entry *) NULL; | |
10162 | ||
1848e567 | 10163 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) |
192dc9c6 JB |
10164 | return (const reg_entry *) NULL; |
10165 | ||
1b54b8d7 | 10166 | if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm) |
192dc9c6 JB |
10167 | return (const reg_entry *) NULL; |
10168 | ||
1b54b8d7 | 10169 | if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm) |
40f12533 L |
10170 | return (const reg_entry *) NULL; |
10171 | ||
1b54b8d7 | 10172 | if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm) |
1848e567 L |
10173 | return (const reg_entry *) NULL; |
10174 | ||
10175 | if (r->reg_type.bitfield.regmask | |
10176 | && !cpu_arch_flags.bitfield.cpuregmask) | |
43234a1e L |
10177 | return (const reg_entry *) NULL; |
10178 | ||
db51cc60 | 10179 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 10180 | if (!allow_index_reg |
db51cc60 L |
10181 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
10182 | return (const reg_entry *) NULL; | |
10183 | ||
43234a1e L |
10184 | /* Upper 16 vector register is only available with VREX in 64bit |
10185 | mode. */ | |
10186 | if ((r->reg_flags & RegVRex)) | |
10187 | { | |
86fa6981 L |
10188 | if (i.vec_encoding == vex_encoding_default) |
10189 | i.vec_encoding = vex_encoding_evex; | |
10190 | ||
43234a1e | 10191 | if (!cpu_arch_flags.bitfield.cpuvrex |
86fa6981 | 10192 | || i.vec_encoding != vex_encoding_evex |
43234a1e L |
10193 | || flag_code != CODE_64BIT) |
10194 | return (const reg_entry *) NULL; | |
43234a1e L |
10195 | } |
10196 | ||
a60de03c | 10197 | if (((r->reg_flags & (RegRex64 | RegRex)) |
dc821c5f | 10198 | || r->reg_type.bitfield.qword) |
40fb9820 | 10199 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 10200 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 10201 | && flag_code != CODE_64BIT) |
20f0a1fc | 10202 | return (const reg_entry *) NULL; |
1ae00879 | 10203 | |
b7240065 JB |
10204 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
10205 | return (const reg_entry *) NULL; | |
10206 | ||
252b5132 RH |
10207 | return r; |
10208 | } | |
4d1bb795 JB |
10209 | |
10210 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10211 | ||
10212 | static const reg_entry * | |
10213 | parse_register (char *reg_string, char **end_op) | |
10214 | { | |
10215 | const reg_entry *r; | |
10216 | ||
10217 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10218 | r = parse_real_register (reg_string, end_op); | |
10219 | else | |
10220 | r = NULL; | |
10221 | if (!r) | |
10222 | { | |
10223 | char *save = input_line_pointer; | |
10224 | char c; | |
10225 | symbolS *symbolP; | |
10226 | ||
10227 | input_line_pointer = reg_string; | |
d02603dc | 10228 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10229 | symbolP = symbol_find (reg_string); |
10230 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10231 | { | |
10232 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10233 | ||
0398aac5 | 10234 | know (e->X_op == O_register); |
4eed87de | 10235 | know (e->X_add_number >= 0 |
c3fe08fa | 10236 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10237 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10238 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10239 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10240 | *end_op = input_line_pointer; |
10241 | } | |
10242 | *input_line_pointer = c; | |
10243 | input_line_pointer = save; | |
10244 | } | |
10245 | return r; | |
10246 | } | |
10247 | ||
10248 | int | |
10249 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10250 | { | |
10251 | const reg_entry *r; | |
10252 | char *end = input_line_pointer; | |
10253 | ||
10254 | *end = *nextcharP; | |
10255 | r = parse_register (name, &input_line_pointer); | |
10256 | if (r && end <= input_line_pointer) | |
10257 | { | |
10258 | *nextcharP = *input_line_pointer; | |
10259 | *input_line_pointer = 0; | |
10260 | e->X_op = O_register; | |
10261 | e->X_add_number = r - i386_regtab; | |
10262 | return 1; | |
10263 | } | |
10264 | input_line_pointer = end; | |
10265 | *end = 0; | |
ee86248c | 10266 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10267 | } |
10268 | ||
10269 | void | |
10270 | md_operand (expressionS *e) | |
10271 | { | |
ee86248c JB |
10272 | char *end; |
10273 | const reg_entry *r; | |
4d1bb795 | 10274 | |
ee86248c JB |
10275 | switch (*input_line_pointer) |
10276 | { | |
10277 | case REGISTER_PREFIX: | |
10278 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10279 | if (r) |
10280 | { | |
10281 | e->X_op = O_register; | |
10282 | e->X_add_number = r - i386_regtab; | |
10283 | input_line_pointer = end; | |
10284 | } | |
ee86248c JB |
10285 | break; |
10286 | ||
10287 | case '[': | |
9c2799c2 | 10288 | gas_assert (intel_syntax); |
ee86248c JB |
10289 | end = input_line_pointer++; |
10290 | expression (e); | |
10291 | if (*input_line_pointer == ']') | |
10292 | { | |
10293 | ++input_line_pointer; | |
10294 | e->X_op_symbol = make_expr_symbol (e); | |
10295 | e->X_add_symbol = NULL; | |
10296 | e->X_add_number = 0; | |
10297 | e->X_op = O_index; | |
10298 | } | |
10299 | else | |
10300 | { | |
10301 | e->X_op = O_absent; | |
10302 | input_line_pointer = end; | |
10303 | } | |
10304 | break; | |
4d1bb795 JB |
10305 | } |
10306 | } | |
10307 | ||
252b5132 | 10308 | \f |
4cc782b5 | 10309 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 10310 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 10311 | #else |
b6f8c7c4 | 10312 | const char *md_shortopts = "qnO::"; |
252b5132 | 10313 | #endif |
6e0b89ee | 10314 | |
3e73aa7c | 10315 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10316 | #define OPTION_64 (OPTION_MD_BASE + 1) |
10317 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
10318 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
10319 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
10320 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
10321 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
10322 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
10323 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
10324 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 10325 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 10326 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
10327 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
10328 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
10329 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 10330 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
10331 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
10332 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 10333 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 10334 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 10335 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 10336 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
10337 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
10338 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 10339 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
0cb4071e | 10340 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) |
b3b91714 | 10341 | |
99ad8390 NC |
10342 | struct option md_longopts[] = |
10343 | { | |
3e73aa7c | 10344 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 10345 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10346 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 10347 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
10348 | #endif |
10349 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 10350 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 10351 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 10352 | #endif |
b3b91714 | 10353 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
10354 | {"march", required_argument, NULL, OPTION_MARCH}, |
10355 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
10356 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
10357 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
10358 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
10359 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
10360 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 10361 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 10362 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 10363 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 10364 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 10365 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
10366 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
10367 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
10368 | # if defined (TE_PE) || defined (TE_PEP) |
10369 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
10370 | #endif | |
d1982f93 | 10371 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 10372 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 10373 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 10374 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
10375 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
10376 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
10377 | {NULL, no_argument, NULL, 0} |
10378 | }; | |
10379 | size_t md_longopts_size = sizeof (md_longopts); | |
10380 | ||
10381 | int | |
17b9d67d | 10382 | md_parse_option (int c, const char *arg) |
252b5132 | 10383 | { |
91d6fa6a | 10384 | unsigned int j; |
293f5f65 | 10385 | char *arch, *next, *saved; |
9103f4f4 | 10386 | |
252b5132 RH |
10387 | switch (c) |
10388 | { | |
12b55ccc L |
10389 | case 'n': |
10390 | optimize_align_code = 0; | |
10391 | break; | |
10392 | ||
a38cf1db AM |
10393 | case 'q': |
10394 | quiet_warnings = 1; | |
252b5132 RH |
10395 | break; |
10396 | ||
10397 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
10398 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
10399 | should be emitted or not. FIXME: Not implemented. */ | |
10400 | case 'Q': | |
252b5132 RH |
10401 | break; |
10402 | ||
10403 | /* -V: SVR4 argument to print version ID. */ | |
10404 | case 'V': | |
10405 | print_version_id (); | |
10406 | break; | |
10407 | ||
a38cf1db AM |
10408 | /* -k: Ignore for FreeBSD compatibility. */ |
10409 | case 'k': | |
252b5132 | 10410 | break; |
4cc782b5 ILT |
10411 | |
10412 | case 's': | |
10413 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 10414 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 10415 | break; |
8dcea932 L |
10416 | |
10417 | case OPTION_MSHARED: | |
10418 | shared = 1; | |
10419 | break; | |
99ad8390 | 10420 | #endif |
321098a5 | 10421 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10422 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
10423 | case OPTION_64: |
10424 | { | |
10425 | const char **list, **l; | |
10426 | ||
3e73aa7c JH |
10427 | list = bfd_target_list (); |
10428 | for (l = list; *l != NULL; l++) | |
8620418b | 10429 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
10430 | || strcmp (*l, "coff-x86-64") == 0 |
10431 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
10432 | || strcmp (*l, "pei-x86-64") == 0 |
10433 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
10434 | { |
10435 | default_arch = "x86_64"; | |
10436 | break; | |
10437 | } | |
3e73aa7c | 10438 | if (*l == NULL) |
2b5d6a91 | 10439 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
10440 | free (list); |
10441 | } | |
10442 | break; | |
10443 | #endif | |
252b5132 | 10444 | |
351f65ca | 10445 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 10446 | case OPTION_X32: |
351f65ca L |
10447 | if (IS_ELF) |
10448 | { | |
10449 | const char **list, **l; | |
10450 | ||
10451 | list = bfd_target_list (); | |
10452 | for (l = list; *l != NULL; l++) | |
10453 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
10454 | { | |
10455 | default_arch = "x86_64:32"; | |
10456 | break; | |
10457 | } | |
10458 | if (*l == NULL) | |
2b5d6a91 | 10459 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
10460 | free (list); |
10461 | } | |
10462 | else | |
10463 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
10464 | break; | |
10465 | #endif | |
10466 | ||
6e0b89ee AM |
10467 | case OPTION_32: |
10468 | default_arch = "i386"; | |
10469 | break; | |
10470 | ||
b3b91714 AM |
10471 | case OPTION_DIVIDE: |
10472 | #ifdef SVR4_COMMENT_CHARS | |
10473 | { | |
10474 | char *n, *t; | |
10475 | const char *s; | |
10476 | ||
add39d23 | 10477 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
10478 | t = n; |
10479 | for (s = i386_comment_chars; *s != '\0'; s++) | |
10480 | if (*s != '/') | |
10481 | *t++ = *s; | |
10482 | *t = '\0'; | |
10483 | i386_comment_chars = n; | |
10484 | } | |
10485 | #endif | |
10486 | break; | |
10487 | ||
9103f4f4 | 10488 | case OPTION_MARCH: |
293f5f65 L |
10489 | saved = xstrdup (arg); |
10490 | arch = saved; | |
10491 | /* Allow -march=+nosse. */ | |
10492 | if (*arch == '+') | |
10493 | arch++; | |
6305a203 | 10494 | do |
9103f4f4 | 10495 | { |
6305a203 | 10496 | if (*arch == '.') |
2b5d6a91 | 10497 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10498 | next = strchr (arch, '+'); |
10499 | if (next) | |
10500 | *next++ = '\0'; | |
91d6fa6a | 10501 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10502 | { |
91d6fa6a | 10503 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 10504 | { |
6305a203 | 10505 | /* Processor. */ |
1ded5609 JB |
10506 | if (! cpu_arch[j].flags.bitfield.cpui386) |
10507 | continue; | |
10508 | ||
91d6fa6a | 10509 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 10510 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
10511 | cpu_arch_flags = cpu_arch[j].flags; |
10512 | cpu_arch_isa = cpu_arch[j].type; | |
10513 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
10514 | if (!cpu_arch_tune_set) |
10515 | { | |
10516 | cpu_arch_tune = cpu_arch_isa; | |
10517 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10518 | } | |
10519 | break; | |
10520 | } | |
91d6fa6a NC |
10521 | else if (*cpu_arch [j].name == '.' |
10522 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 10523 | { |
33eaf5de | 10524 | /* ISA extension. */ |
6305a203 | 10525 | i386_cpu_flags flags; |
309d3373 | 10526 | |
293f5f65 L |
10527 | flags = cpu_flags_or (cpu_arch_flags, |
10528 | cpu_arch[j].flags); | |
81486035 | 10529 | |
5b64d091 | 10530 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
10531 | { |
10532 | if (cpu_sub_arch_name) | |
10533 | { | |
10534 | char *name = cpu_sub_arch_name; | |
10535 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 10536 | cpu_arch[j].name, |
1bf57e9f | 10537 | (const char *) NULL); |
6305a203 L |
10538 | free (name); |
10539 | } | |
10540 | else | |
91d6fa6a | 10541 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 10542 | cpu_arch_flags = flags; |
a586129e | 10543 | cpu_arch_isa_flags = flags; |
6305a203 L |
10544 | } |
10545 | break; | |
ccc9c027 | 10546 | } |
9103f4f4 | 10547 | } |
6305a203 | 10548 | |
293f5f65 L |
10549 | if (j >= ARRAY_SIZE (cpu_arch)) |
10550 | { | |
33eaf5de | 10551 | /* Disable an ISA extension. */ |
293f5f65 L |
10552 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
10553 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10554 | { | |
10555 | i386_cpu_flags flags; | |
10556 | ||
10557 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10558 | cpu_noarch[j].flags); | |
10559 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10560 | { | |
10561 | if (cpu_sub_arch_name) | |
10562 | { | |
10563 | char *name = cpu_sub_arch_name; | |
10564 | cpu_sub_arch_name = concat (arch, | |
10565 | (const char *) NULL); | |
10566 | free (name); | |
10567 | } | |
10568 | else | |
10569 | cpu_sub_arch_name = xstrdup (arch); | |
10570 | cpu_arch_flags = flags; | |
10571 | cpu_arch_isa_flags = flags; | |
10572 | } | |
10573 | break; | |
10574 | } | |
10575 | ||
10576 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10577 | j = ARRAY_SIZE (cpu_arch); | |
10578 | } | |
10579 | ||
91d6fa6a | 10580 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10581 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10582 | |
10583 | arch = next; | |
9103f4f4 | 10584 | } |
293f5f65 L |
10585 | while (next != NULL); |
10586 | free (saved); | |
9103f4f4 L |
10587 | break; |
10588 | ||
10589 | case OPTION_MTUNE: | |
10590 | if (*arg == '.') | |
2b5d6a91 | 10591 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10592 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10593 | { |
91d6fa6a | 10594 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10595 | { |
ccc9c027 | 10596 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10597 | cpu_arch_tune = cpu_arch [j].type; |
10598 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10599 | break; |
10600 | } | |
10601 | } | |
91d6fa6a | 10602 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10603 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10604 | break; |
10605 | ||
1efbbeb4 L |
10606 | case OPTION_MMNEMONIC: |
10607 | if (strcasecmp (arg, "att") == 0) | |
10608 | intel_mnemonic = 0; | |
10609 | else if (strcasecmp (arg, "intel") == 0) | |
10610 | intel_mnemonic = 1; | |
10611 | else | |
2b5d6a91 | 10612 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10613 | break; |
10614 | ||
10615 | case OPTION_MSYNTAX: | |
10616 | if (strcasecmp (arg, "att") == 0) | |
10617 | intel_syntax = 0; | |
10618 | else if (strcasecmp (arg, "intel") == 0) | |
10619 | intel_syntax = 1; | |
10620 | else | |
2b5d6a91 | 10621 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10622 | break; |
10623 | ||
10624 | case OPTION_MINDEX_REG: | |
10625 | allow_index_reg = 1; | |
10626 | break; | |
10627 | ||
10628 | case OPTION_MNAKED_REG: | |
10629 | allow_naked_reg = 1; | |
10630 | break; | |
10631 | ||
10632 | case OPTION_MOLD_GCC: | |
10633 | old_gcc = 1; | |
1efbbeb4 L |
10634 | break; |
10635 | ||
c0f3af97 L |
10636 | case OPTION_MSSE2AVX: |
10637 | sse2avx = 1; | |
10638 | break; | |
10639 | ||
daf50ae7 L |
10640 | case OPTION_MSSE_CHECK: |
10641 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10642 | sse_check = check_error; |
daf50ae7 | 10643 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10644 | sse_check = check_warning; |
daf50ae7 | 10645 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10646 | sse_check = check_none; |
daf50ae7 | 10647 | else |
2b5d6a91 | 10648 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10649 | break; |
10650 | ||
7bab8ab5 JB |
10651 | case OPTION_MOPERAND_CHECK: |
10652 | if (strcasecmp (arg, "error") == 0) | |
10653 | operand_check = check_error; | |
10654 | else if (strcasecmp (arg, "warning") == 0) | |
10655 | operand_check = check_warning; | |
10656 | else if (strcasecmp (arg, "none") == 0) | |
10657 | operand_check = check_none; | |
10658 | else | |
10659 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10660 | break; | |
10661 | ||
539f890d L |
10662 | case OPTION_MAVXSCALAR: |
10663 | if (strcasecmp (arg, "128") == 0) | |
10664 | avxscalar = vex128; | |
10665 | else if (strcasecmp (arg, "256") == 0) | |
10666 | avxscalar = vex256; | |
10667 | else | |
2b5d6a91 | 10668 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10669 | break; |
10670 | ||
7e8b059b L |
10671 | case OPTION_MADD_BND_PREFIX: |
10672 | add_bnd_prefix = 1; | |
10673 | break; | |
10674 | ||
43234a1e L |
10675 | case OPTION_MEVEXLIG: |
10676 | if (strcmp (arg, "128") == 0) | |
10677 | evexlig = evexl128; | |
10678 | else if (strcmp (arg, "256") == 0) | |
10679 | evexlig = evexl256; | |
10680 | else if (strcmp (arg, "512") == 0) | |
10681 | evexlig = evexl512; | |
10682 | else | |
10683 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10684 | break; | |
10685 | ||
d3d3c6db IT |
10686 | case OPTION_MEVEXRCIG: |
10687 | if (strcmp (arg, "rne") == 0) | |
10688 | evexrcig = rne; | |
10689 | else if (strcmp (arg, "rd") == 0) | |
10690 | evexrcig = rd; | |
10691 | else if (strcmp (arg, "ru") == 0) | |
10692 | evexrcig = ru; | |
10693 | else if (strcmp (arg, "rz") == 0) | |
10694 | evexrcig = rz; | |
10695 | else | |
10696 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10697 | break; | |
10698 | ||
43234a1e L |
10699 | case OPTION_MEVEXWIG: |
10700 | if (strcmp (arg, "0") == 0) | |
10701 | evexwig = evexw0; | |
10702 | else if (strcmp (arg, "1") == 0) | |
10703 | evexwig = evexw1; | |
10704 | else | |
10705 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10706 | break; | |
10707 | ||
167ad85b TG |
10708 | # if defined (TE_PE) || defined (TE_PEP) |
10709 | case OPTION_MBIG_OBJ: | |
10710 | use_big_obj = 1; | |
10711 | break; | |
10712 | #endif | |
10713 | ||
d1982f93 | 10714 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10715 | if (strcasecmp (arg, "yes") == 0) |
10716 | omit_lock_prefix = 1; | |
10717 | else if (strcasecmp (arg, "no") == 0) | |
10718 | omit_lock_prefix = 0; | |
10719 | else | |
10720 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10721 | break; | |
10722 | ||
e4e00185 AS |
10723 | case OPTION_MFENCE_AS_LOCK_ADD: |
10724 | if (strcasecmp (arg, "yes") == 0) | |
10725 | avoid_fence = 1; | |
10726 | else if (strcasecmp (arg, "no") == 0) | |
10727 | avoid_fence = 0; | |
10728 | else | |
10729 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10730 | break; | |
10731 | ||
0cb4071e L |
10732 | case OPTION_MRELAX_RELOCATIONS: |
10733 | if (strcasecmp (arg, "yes") == 0) | |
10734 | generate_relax_relocations = 1; | |
10735 | else if (strcasecmp (arg, "no") == 0) | |
10736 | generate_relax_relocations = 0; | |
10737 | else | |
10738 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10739 | break; | |
10740 | ||
5db04b09 | 10741 | case OPTION_MAMD64: |
e89c5eaa | 10742 | intel64 = 0; |
5db04b09 L |
10743 | break; |
10744 | ||
10745 | case OPTION_MINTEL64: | |
e89c5eaa | 10746 | intel64 = 1; |
5db04b09 L |
10747 | break; |
10748 | ||
b6f8c7c4 L |
10749 | case 'O': |
10750 | if (arg == NULL) | |
10751 | { | |
10752 | optimize = 1; | |
10753 | /* Turn off -Os. */ | |
10754 | optimize_for_space = 0; | |
10755 | } | |
10756 | else if (*arg == 's') | |
10757 | { | |
10758 | optimize_for_space = 1; | |
10759 | /* Turn on all encoding optimizations. */ | |
10760 | optimize = -1; | |
10761 | } | |
10762 | else | |
10763 | { | |
10764 | optimize = atoi (arg); | |
10765 | /* Turn off -Os. */ | |
10766 | optimize_for_space = 0; | |
10767 | } | |
10768 | break; | |
10769 | ||
252b5132 RH |
10770 | default: |
10771 | return 0; | |
10772 | } | |
10773 | return 1; | |
10774 | } | |
10775 | ||
8a2c8fef L |
10776 | #define MESSAGE_TEMPLATE \ |
10777 | " " | |
10778 | ||
293f5f65 L |
10779 | static char * |
10780 | output_message (FILE *stream, char *p, char *message, char *start, | |
10781 | int *left_p, const char *name, int len) | |
10782 | { | |
10783 | int size = sizeof (MESSAGE_TEMPLATE); | |
10784 | int left = *left_p; | |
10785 | ||
10786 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10787 | left -= len + 2; | |
10788 | ||
10789 | /* Check if there is any room. */ | |
10790 | if (left >= 0) | |
10791 | { | |
10792 | if (p != start) | |
10793 | { | |
10794 | *p++ = ','; | |
10795 | *p++ = ' '; | |
10796 | } | |
10797 | p = mempcpy (p, name, len); | |
10798 | } | |
10799 | else | |
10800 | { | |
10801 | /* Output the current message now and start a new one. */ | |
10802 | *p++ = ','; | |
10803 | *p = '\0'; | |
10804 | fprintf (stream, "%s\n", message); | |
10805 | p = start; | |
10806 | left = size - (start - message) - len - 2; | |
10807 | ||
10808 | gas_assert (left >= 0); | |
10809 | ||
10810 | p = mempcpy (p, name, len); | |
10811 | } | |
10812 | ||
10813 | *left_p = left; | |
10814 | return p; | |
10815 | } | |
10816 | ||
8a2c8fef | 10817 | static void |
1ded5609 | 10818 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
10819 | { |
10820 | static char message[] = MESSAGE_TEMPLATE; | |
10821 | char *start = message + 27; | |
10822 | char *p; | |
10823 | int size = sizeof (MESSAGE_TEMPLATE); | |
10824 | int left; | |
10825 | const char *name; | |
10826 | int len; | |
10827 | unsigned int j; | |
10828 | ||
10829 | p = start; | |
10830 | left = size - (start - message); | |
10831 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
10832 | { | |
10833 | /* Should it be skipped? */ | |
10834 | if (cpu_arch [j].skip) | |
10835 | continue; | |
10836 | ||
10837 | name = cpu_arch [j].name; | |
10838 | len = cpu_arch [j].len; | |
10839 | if (*name == '.') | |
10840 | { | |
10841 | /* It is an extension. Skip if we aren't asked to show it. */ | |
10842 | if (ext) | |
10843 | { | |
10844 | name++; | |
10845 | len--; | |
10846 | } | |
10847 | else | |
10848 | continue; | |
10849 | } | |
10850 | else if (ext) | |
10851 | { | |
10852 | /* It is an processor. Skip if we show only extension. */ | |
10853 | continue; | |
10854 | } | |
1ded5609 JB |
10855 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
10856 | { | |
10857 | /* It is an impossible processor - skip. */ | |
10858 | continue; | |
10859 | } | |
8a2c8fef | 10860 | |
293f5f65 | 10861 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
10862 | } |
10863 | ||
293f5f65 L |
10864 | /* Display disabled extensions. */ |
10865 | if (ext) | |
10866 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10867 | { | |
10868 | name = cpu_noarch [j].name; | |
10869 | len = cpu_noarch [j].len; | |
10870 | p = output_message (stream, p, message, start, &left, name, | |
10871 | len); | |
10872 | } | |
10873 | ||
8a2c8fef L |
10874 | *p = '\0'; |
10875 | fprintf (stream, "%s\n", message); | |
10876 | } | |
10877 | ||
252b5132 | 10878 | void |
8a2c8fef | 10879 | md_show_usage (FILE *stream) |
252b5132 | 10880 | { |
4cc782b5 ILT |
10881 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10882 | fprintf (stream, _("\ | |
a38cf1db AM |
10883 | -Q ignored\n\ |
10884 | -V print assembler version number\n\ | |
b3b91714 AM |
10885 | -k ignored\n")); |
10886 | #endif | |
10887 | fprintf (stream, _("\ | |
12b55ccc | 10888 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
10889 | -q quieten some warnings\n")); |
10890 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10891 | fprintf (stream, _("\ | |
a38cf1db | 10892 | -s ignored\n")); |
b3b91714 | 10893 | #endif |
321098a5 L |
10894 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
10895 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 10896 | fprintf (stream, _("\ |
570561f7 | 10897 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 10898 | #endif |
b3b91714 AM |
10899 | #ifdef SVR4_COMMENT_CHARS |
10900 | fprintf (stream, _("\ | |
10901 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
10902 | #else |
10903 | fprintf (stream, _("\ | |
b3b91714 | 10904 | --divide ignored\n")); |
4cc782b5 | 10905 | #endif |
9103f4f4 | 10906 | fprintf (stream, _("\ |
6305a203 | 10907 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 10908 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 10909 | show_arch (stream, 0, 1); |
8a2c8fef L |
10910 | fprintf (stream, _("\ |
10911 | EXTENSION is combination of:\n")); | |
1ded5609 | 10912 | show_arch (stream, 1, 0); |
6305a203 | 10913 | fprintf (stream, _("\ |
8a2c8fef | 10914 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 10915 | show_arch (stream, 0, 0); |
ba104c83 | 10916 | fprintf (stream, _("\ |
c0f3af97 L |
10917 | -msse2avx encode SSE instructions with VEX prefix\n")); |
10918 | fprintf (stream, _("\ | |
daf50ae7 L |
10919 | -msse-check=[none|error|warning]\n\ |
10920 | check SSE instructions\n")); | |
10921 | fprintf (stream, _("\ | |
7bab8ab5 JB |
10922 | -moperand-check=[none|error|warning]\n\ |
10923 | check operand combinations for validity\n")); | |
10924 | fprintf (stream, _("\ | |
539f890d L |
10925 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
10926 | length\n")); | |
10927 | fprintf (stream, _("\ | |
43234a1e L |
10928 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
10929 | length\n")); | |
10930 | fprintf (stream, _("\ | |
10931 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
10932 | for EVEX.W bit ignored instructions\n")); | |
10933 | fprintf (stream, _("\ | |
d3d3c6db IT |
10934 | -mevexrcig=[rne|rd|ru|rz]\n\ |
10935 | encode EVEX instructions with specific EVEX.RC value\n\ | |
10936 | for SAE-only ignored instructions\n")); | |
10937 | fprintf (stream, _("\ | |
ba104c83 L |
10938 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
10939 | fprintf (stream, _("\ | |
10940 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
10941 | fprintf (stream, _("\ | |
10942 | -mindex-reg support pseudo index registers\n")); | |
10943 | fprintf (stream, _("\ | |
10944 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
10945 | fprintf (stream, _("\ | |
10946 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
7e8b059b L |
10947 | fprintf (stream, _("\ |
10948 | -madd-bnd-prefix add BND prefix for all valid branches\n")); | |
8dcea932 L |
10949 | fprintf (stream, _("\ |
10950 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
10951 | # if defined (TE_PE) || defined (TE_PEP) |
10952 | fprintf (stream, _("\ | |
10953 | -mbig-obj generate big object files\n")); | |
10954 | #endif | |
d022bddd IT |
10955 | fprintf (stream, _("\ |
10956 | -momit-lock-prefix=[no|yes]\n\ | |
10957 | strip all lock prefixes\n")); | |
5db04b09 | 10958 | fprintf (stream, _("\ |
e4e00185 AS |
10959 | -mfence-as-lock-add=[no|yes]\n\ |
10960 | encode lfence, mfence and sfence as\n\ | |
10961 | lock addl $0x0, (%%{re}sp)\n")); | |
10962 | fprintf (stream, _("\ | |
0cb4071e L |
10963 | -mrelax-relocations=[no|yes]\n\ |
10964 | generate relax relocations\n")); | |
10965 | fprintf (stream, _("\ | |
5db04b09 L |
10966 | -mamd64 accept only AMD64 ISA\n")); |
10967 | fprintf (stream, _("\ | |
10968 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
10969 | } |
10970 | ||
3e73aa7c | 10971 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 10972 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 10973 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
10974 | |
10975 | /* Pick the target format to use. */ | |
10976 | ||
47926f60 | 10977 | const char * |
e3bb37b5 | 10978 | i386_target_format (void) |
252b5132 | 10979 | { |
351f65ca L |
10980 | if (!strncmp (default_arch, "x86_64", 6)) |
10981 | { | |
10982 | update_code_flag (CODE_64BIT, 1); | |
10983 | if (default_arch[6] == '\0') | |
7f56bc95 | 10984 | x86_elf_abi = X86_64_ABI; |
351f65ca | 10985 | else |
7f56bc95 | 10986 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 10987 | } |
3e73aa7c | 10988 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 10989 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
10990 | else if (!strcmp (default_arch, "iamcu")) |
10991 | { | |
10992 | update_code_flag (CODE_32BIT, 1); | |
10993 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
10994 | { | |
10995 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
10996 | cpu_arch_name = "iamcu"; | |
10997 | cpu_sub_arch_name = NULL; | |
10998 | cpu_arch_flags = iamcu_flags; | |
10999 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11000 | cpu_arch_isa_flags = iamcu_flags; | |
11001 | if (!cpu_arch_tune_set) | |
11002 | { | |
11003 | cpu_arch_tune = cpu_arch_isa; | |
11004 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11005 | } | |
11006 | } | |
8d471ec1 | 11007 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11008 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11009 | cpu_arch_name); | |
11010 | } | |
3e73aa7c | 11011 | else |
2b5d6a91 | 11012 | as_fatal (_("unknown architecture")); |
89507696 JB |
11013 | |
11014 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11015 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11016 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11017 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11018 | ||
252b5132 RH |
11019 | switch (OUTPUT_FLAVOR) |
11020 | { | |
9384f2ff | 11021 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11022 | case bfd_target_aout_flavour: |
47926f60 | 11023 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11024 | #endif |
9384f2ff AM |
11025 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11026 | # if defined (TE_PE) || defined (TE_PEP) | |
11027 | case bfd_target_coff_flavour: | |
167ad85b TG |
11028 | if (flag_code == CODE_64BIT) |
11029 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11030 | else | |
11031 | return "pe-i386"; | |
9384f2ff | 11032 | # elif defined (TE_GO32) |
0561d57c JK |
11033 | case bfd_target_coff_flavour: |
11034 | return "coff-go32"; | |
9384f2ff | 11035 | # else |
252b5132 RH |
11036 | case bfd_target_coff_flavour: |
11037 | return "coff-i386"; | |
9384f2ff | 11038 | # endif |
4c63da97 | 11039 | #endif |
3e73aa7c | 11040 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11041 | case bfd_target_elf_flavour: |
3e73aa7c | 11042 | { |
351f65ca L |
11043 | const char *format; |
11044 | ||
11045 | switch (x86_elf_abi) | |
4fa24527 | 11046 | { |
351f65ca L |
11047 | default: |
11048 | format = ELF_TARGET_FORMAT; | |
11049 | break; | |
7f56bc95 | 11050 | case X86_64_ABI: |
351f65ca | 11051 | use_rela_relocations = 1; |
4fa24527 | 11052 | object_64bit = 1; |
351f65ca L |
11053 | format = ELF_TARGET_FORMAT64; |
11054 | break; | |
7f56bc95 | 11055 | case X86_64_X32_ABI: |
4fa24527 | 11056 | use_rela_relocations = 1; |
351f65ca | 11057 | object_64bit = 1; |
862be3fb | 11058 | disallow_64bit_reloc = 1; |
351f65ca L |
11059 | format = ELF_TARGET_FORMAT32; |
11060 | break; | |
4fa24527 | 11061 | } |
3632d14b | 11062 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11063 | { |
7f56bc95 | 11064 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11065 | as_fatal (_("Intel L1OM is 64bit only")); |
11066 | return ELF_TARGET_L1OM_FORMAT; | |
11067 | } | |
b49f93f6 | 11068 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11069 | { |
11070 | if (x86_elf_abi != X86_64_ABI) | |
11071 | as_fatal (_("Intel K1OM is 64bit only")); | |
11072 | return ELF_TARGET_K1OM_FORMAT; | |
11073 | } | |
81486035 L |
11074 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11075 | { | |
11076 | if (x86_elf_abi != I386_ABI) | |
11077 | as_fatal (_("Intel MCU is 32bit only")); | |
11078 | return ELF_TARGET_IAMCU_FORMAT; | |
11079 | } | |
8a9036a4 | 11080 | else |
351f65ca | 11081 | return format; |
3e73aa7c | 11082 | } |
e57f8c65 TG |
11083 | #endif |
11084 | #if defined (OBJ_MACH_O) | |
11085 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11086 | if (flag_code == CODE_64BIT) |
11087 | { | |
11088 | use_rela_relocations = 1; | |
11089 | object_64bit = 1; | |
11090 | return "mach-o-x86-64"; | |
11091 | } | |
11092 | else | |
11093 | return "mach-o-i386"; | |
4c63da97 | 11094 | #endif |
252b5132 RH |
11095 | default: |
11096 | abort (); | |
11097 | return NULL; | |
11098 | } | |
11099 | } | |
11100 | ||
47926f60 | 11101 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11102 | \f |
252b5132 | 11103 | symbolS * |
7016a5d5 | 11104 | md_undefined_symbol (char *name) |
252b5132 | 11105 | { |
18dc2407 ILT |
11106 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11107 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11108 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11109 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11110 | { |
11111 | if (!GOT_symbol) | |
11112 | { | |
11113 | if (symbol_find (name)) | |
11114 | as_bad (_("GOT already in symbol table")); | |
11115 | GOT_symbol = symbol_new (name, undefined_section, | |
11116 | (valueT) 0, &zero_address_frag); | |
11117 | }; | |
11118 | return GOT_symbol; | |
11119 | } | |
252b5132 RH |
11120 | return 0; |
11121 | } | |
11122 | ||
11123 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11124 | |
252b5132 | 11125 | valueT |
7016a5d5 | 11126 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11127 | { |
4c63da97 AM |
11128 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11129 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11130 | { | |
11131 | /* For a.out, force the section size to be aligned. If we don't do | |
11132 | this, BFD will align it for us, but it will not write out the | |
11133 | final bytes of the section. This may be a bug in BFD, but it is | |
11134 | easier to fix it here since that is how the other a.out targets | |
11135 | work. */ | |
11136 | int align; | |
11137 | ||
11138 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 11139 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11140 | } |
252b5132 RH |
11141 | #endif |
11142 | ||
11143 | return size; | |
11144 | } | |
11145 | ||
11146 | /* On the i386, PC-relative offsets are relative to the start of the | |
11147 | next instruction. That is, the address of the offset, plus its | |
11148 | size, since the offset is always the last part of the insn. */ | |
11149 | ||
11150 | long | |
e3bb37b5 | 11151 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11152 | { |
11153 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11154 | } | |
11155 | ||
11156 | #ifndef I386COFF | |
11157 | ||
11158 | static void | |
e3bb37b5 | 11159 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11160 | { |
29b0f896 | 11161 | int temp; |
252b5132 | 11162 | |
8a75718c JB |
11163 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11164 | if (IS_ELF) | |
11165 | obj_elf_section_change_hook (); | |
11166 | #endif | |
252b5132 RH |
11167 | temp = get_absolute_expression (); |
11168 | subseg_set (bss_section, (subsegT) temp); | |
11169 | demand_empty_rest_of_line (); | |
11170 | } | |
11171 | ||
11172 | #endif | |
11173 | ||
252b5132 | 11174 | void |
e3bb37b5 | 11175 | i386_validate_fix (fixS *fixp) |
252b5132 | 11176 | { |
02a86693 | 11177 | if (fixp->fx_subsy) |
252b5132 | 11178 | { |
02a86693 | 11179 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11180 | { |
02a86693 L |
11181 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11182 | { | |
11183 | if (!object_64bit) | |
11184 | abort (); | |
11185 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11186 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11187 | fixp->fx_r_type = (fixp->fx_tcbit |
11188 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11189 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11190 | else |
11191 | #endif | |
11192 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11193 | } | |
d6ab8113 | 11194 | else |
02a86693 L |
11195 | { |
11196 | if (!object_64bit) | |
11197 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11198 | else | |
11199 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11200 | } | |
11201 | fixp->fx_subsy = 0; | |
23df1078 | 11202 | } |
252b5132 | 11203 | } |
02a86693 L |
11204 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11205 | else if (!object_64bit) | |
11206 | { | |
11207 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11208 | && fixp->fx_tcbit2) | |
11209 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11210 | } | |
11211 | #endif | |
252b5132 RH |
11212 | } |
11213 | ||
252b5132 | 11214 | arelent * |
7016a5d5 | 11215 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11216 | { |
11217 | arelent *rel; | |
11218 | bfd_reloc_code_real_type code; | |
11219 | ||
11220 | switch (fixp->fx_r_type) | |
11221 | { | |
8ce3d284 | 11222 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11223 | case BFD_RELOC_SIZE32: |
11224 | case BFD_RELOC_SIZE64: | |
11225 | if (S_IS_DEFINED (fixp->fx_addsy) | |
11226 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
11227 | { | |
11228 | /* Resolve size relocation against local symbol to size of | |
11229 | the symbol plus addend. */ | |
11230 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
11231 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
11232 | && !fits_in_unsigned_long (value)) | |
11233 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11234 | _("symbol size computation overflow")); | |
11235 | fixp->fx_addsy = NULL; | |
11236 | fixp->fx_subsy = NULL; | |
11237 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
11238 | return NULL; | |
11239 | } | |
8ce3d284 | 11240 | #endif |
1a0670f3 | 11241 | /* Fall through. */ |
8fd4256d | 11242 | |
3e73aa7c JH |
11243 | case BFD_RELOC_X86_64_PLT32: |
11244 | case BFD_RELOC_X86_64_GOT32: | |
11245 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11246 | case BFD_RELOC_X86_64_GOTPCRELX: |
11247 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
11248 | case BFD_RELOC_386_PLT32: |
11249 | case BFD_RELOC_386_GOT32: | |
02a86693 | 11250 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
11251 | case BFD_RELOC_386_GOTOFF: |
11252 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
11253 | case BFD_RELOC_386_TLS_GD: |
11254 | case BFD_RELOC_386_TLS_LDM: | |
11255 | case BFD_RELOC_386_TLS_LDO_32: | |
11256 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11257 | case BFD_RELOC_386_TLS_IE: |
11258 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11259 | case BFD_RELOC_386_TLS_LE_32: |
11260 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11261 | case BFD_RELOC_386_TLS_GOTDESC: |
11262 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11263 | case BFD_RELOC_X86_64_TLSGD: |
11264 | case BFD_RELOC_X86_64_TLSLD: | |
11265 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11266 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11267 | case BFD_RELOC_X86_64_GOTTPOFF: |
11268 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
11269 | case BFD_RELOC_X86_64_TPOFF64: |
11270 | case BFD_RELOC_X86_64_GOTOFF64: | |
11271 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
11272 | case BFD_RELOC_X86_64_GOT64: |
11273 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11274 | case BFD_RELOC_X86_64_GOTPC64: | |
11275 | case BFD_RELOC_X86_64_GOTPLT64: | |
11276 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
11277 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11278 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
11279 | case BFD_RELOC_RVA: |
11280 | case BFD_RELOC_VTABLE_ENTRY: | |
11281 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
11282 | #ifdef TE_PE |
11283 | case BFD_RELOC_32_SECREL: | |
11284 | #endif | |
252b5132 RH |
11285 | code = fixp->fx_r_type; |
11286 | break; | |
dbbaec26 L |
11287 | case BFD_RELOC_X86_64_32S: |
11288 | if (!fixp->fx_pcrel) | |
11289 | { | |
11290 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
11291 | code = fixp->fx_r_type; | |
11292 | break; | |
11293 | } | |
1a0670f3 | 11294 | /* Fall through. */ |
252b5132 | 11295 | default: |
93382f6d | 11296 | if (fixp->fx_pcrel) |
252b5132 | 11297 | { |
93382f6d AM |
11298 | switch (fixp->fx_size) |
11299 | { | |
11300 | default: | |
b091f402 AM |
11301 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11302 | _("can not do %d byte pc-relative relocation"), | |
11303 | fixp->fx_size); | |
93382f6d AM |
11304 | code = BFD_RELOC_32_PCREL; |
11305 | break; | |
11306 | case 1: code = BFD_RELOC_8_PCREL; break; | |
11307 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 11308 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
11309 | #ifdef BFD64 |
11310 | case 8: code = BFD_RELOC_64_PCREL; break; | |
11311 | #endif | |
93382f6d AM |
11312 | } |
11313 | } | |
11314 | else | |
11315 | { | |
11316 | switch (fixp->fx_size) | |
11317 | { | |
11318 | default: | |
b091f402 AM |
11319 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11320 | _("can not do %d byte relocation"), | |
11321 | fixp->fx_size); | |
93382f6d AM |
11322 | code = BFD_RELOC_32; |
11323 | break; | |
11324 | case 1: code = BFD_RELOC_8; break; | |
11325 | case 2: code = BFD_RELOC_16; break; | |
11326 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 11327 | #ifdef BFD64 |
3e73aa7c | 11328 | case 8: code = BFD_RELOC_64; break; |
937149dd | 11329 | #endif |
93382f6d | 11330 | } |
252b5132 RH |
11331 | } |
11332 | break; | |
11333 | } | |
252b5132 | 11334 | |
d182319b JB |
11335 | if ((code == BFD_RELOC_32 |
11336 | || code == BFD_RELOC_32_PCREL | |
11337 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
11338 | && GOT_symbol |
11339 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 11340 | { |
4fa24527 | 11341 | if (!object_64bit) |
d6ab8113 JB |
11342 | code = BFD_RELOC_386_GOTPC; |
11343 | else | |
11344 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 11345 | } |
7b81dfbb AJ |
11346 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
11347 | && GOT_symbol | |
11348 | && fixp->fx_addsy == GOT_symbol) | |
11349 | { | |
11350 | code = BFD_RELOC_X86_64_GOTPC64; | |
11351 | } | |
252b5132 | 11352 | |
add39d23 TS |
11353 | rel = XNEW (arelent); |
11354 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 11355 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
11356 | |
11357 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 11358 | |
3e73aa7c JH |
11359 | if (!use_rela_relocations) |
11360 | { | |
11361 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
11362 | vtable entry to be used in the relocation's section offset. */ | |
11363 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11364 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
11365 | #if defined (OBJ_COFF) && defined (TE_PE) |
11366 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
11367 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
11368 | else | |
11369 | #endif | |
c6682705 | 11370 | rel->addend = 0; |
3e73aa7c JH |
11371 | } |
11372 | /* Use the rela in 64bit mode. */ | |
252b5132 | 11373 | else |
3e73aa7c | 11374 | { |
862be3fb L |
11375 | if (disallow_64bit_reloc) |
11376 | switch (code) | |
11377 | { | |
862be3fb L |
11378 | case BFD_RELOC_X86_64_DTPOFF64: |
11379 | case BFD_RELOC_X86_64_TPOFF64: | |
11380 | case BFD_RELOC_64_PCREL: | |
11381 | case BFD_RELOC_X86_64_GOTOFF64: | |
11382 | case BFD_RELOC_X86_64_GOT64: | |
11383 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11384 | case BFD_RELOC_X86_64_GOTPC64: | |
11385 | case BFD_RELOC_X86_64_GOTPLT64: | |
11386 | case BFD_RELOC_X86_64_PLTOFF64: | |
11387 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11388 | _("cannot represent relocation type %s in x32 mode"), | |
11389 | bfd_get_reloc_code_name (code)); | |
11390 | break; | |
11391 | default: | |
11392 | break; | |
11393 | } | |
11394 | ||
062cd5e7 AS |
11395 | if (!fixp->fx_pcrel) |
11396 | rel->addend = fixp->fx_offset; | |
11397 | else | |
11398 | switch (code) | |
11399 | { | |
11400 | case BFD_RELOC_X86_64_PLT32: | |
11401 | case BFD_RELOC_X86_64_GOT32: | |
11402 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11403 | case BFD_RELOC_X86_64_GOTPCRELX: |
11404 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
11405 | case BFD_RELOC_X86_64_TLSGD: |
11406 | case BFD_RELOC_X86_64_TLSLD: | |
11407 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
11408 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11409 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
11410 | rel->addend = fixp->fx_offset - fixp->fx_size; |
11411 | break; | |
11412 | default: | |
11413 | rel->addend = (section->vma | |
11414 | - fixp->fx_size | |
11415 | + fixp->fx_addnumber | |
11416 | + md_pcrel_from (fixp)); | |
11417 | break; | |
11418 | } | |
3e73aa7c JH |
11419 | } |
11420 | ||
252b5132 RH |
11421 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
11422 | if (rel->howto == NULL) | |
11423 | { | |
11424 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 11425 | _("cannot represent relocation type %s"), |
252b5132 RH |
11426 | bfd_get_reloc_code_name (code)); |
11427 | /* Set howto to a garbage value so that we can keep going. */ | |
11428 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 11429 | gas_assert (rel->howto != NULL); |
252b5132 RH |
11430 | } |
11431 | ||
11432 | return rel; | |
11433 | } | |
11434 | ||
ee86248c | 11435 | #include "tc-i386-intel.c" |
54cfded0 | 11436 | |
a60de03c JB |
11437 | void |
11438 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 11439 | { |
a60de03c JB |
11440 | int saved_naked_reg; |
11441 | char saved_register_dot; | |
54cfded0 | 11442 | |
a60de03c JB |
11443 | saved_naked_reg = allow_naked_reg; |
11444 | allow_naked_reg = 1; | |
11445 | saved_register_dot = register_chars['.']; | |
11446 | register_chars['.'] = '.'; | |
11447 | allow_pseudo_reg = 1; | |
11448 | expression_and_evaluate (exp); | |
11449 | allow_pseudo_reg = 0; | |
11450 | register_chars['.'] = saved_register_dot; | |
11451 | allow_naked_reg = saved_naked_reg; | |
11452 | ||
e96d56a1 | 11453 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 11454 | { |
a60de03c JB |
11455 | if ((addressT) exp->X_add_number < i386_regtab_size) |
11456 | { | |
11457 | exp->X_op = O_constant; | |
11458 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
11459 | .dw2_regnum[flag_code >> 1]; | |
11460 | } | |
11461 | else | |
11462 | exp->X_op = O_illegal; | |
54cfded0 | 11463 | } |
54cfded0 AM |
11464 | } |
11465 | ||
11466 | void | |
11467 | tc_x86_frame_initial_instructions (void) | |
11468 | { | |
a60de03c JB |
11469 | static unsigned int sp_regno[2]; |
11470 | ||
11471 | if (!sp_regno[flag_code >> 1]) | |
11472 | { | |
11473 | char *saved_input = input_line_pointer; | |
11474 | char sp[][4] = {"esp", "rsp"}; | |
11475 | expressionS exp; | |
a4447b93 | 11476 | |
a60de03c JB |
11477 | input_line_pointer = sp[flag_code >> 1]; |
11478 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 11479 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
11480 | sp_regno[flag_code >> 1] = exp.X_add_number; |
11481 | input_line_pointer = saved_input; | |
11482 | } | |
a4447b93 | 11483 | |
61ff971f L |
11484 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
11485 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 11486 | } |
d2b2c203 | 11487 | |
d7921315 L |
11488 | int |
11489 | x86_dwarf2_addr_size (void) | |
11490 | { | |
11491 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
11492 | if (x86_elf_abi == X86_64_X32_ABI) | |
11493 | return 4; | |
11494 | #endif | |
11495 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
11496 | } | |
11497 | ||
d2b2c203 DJ |
11498 | int |
11499 | i386_elf_section_type (const char *str, size_t len) | |
11500 | { | |
11501 | if (flag_code == CODE_64BIT | |
11502 | && len == sizeof ("unwind") - 1 | |
11503 | && strncmp (str, "unwind", 6) == 0) | |
11504 | return SHT_X86_64_UNWIND; | |
11505 | ||
11506 | return -1; | |
11507 | } | |
bb41ade5 | 11508 | |
ad5fec3b EB |
11509 | #ifdef TE_SOLARIS |
11510 | void | |
11511 | i386_solaris_fix_up_eh_frame (segT sec) | |
11512 | { | |
11513 | if (flag_code == CODE_64BIT) | |
11514 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
11515 | } | |
11516 | #endif | |
11517 | ||
bb41ade5 AM |
11518 | #ifdef TE_PE |
11519 | void | |
11520 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
11521 | { | |
91d6fa6a | 11522 | expressionS exp; |
bb41ade5 | 11523 | |
91d6fa6a NC |
11524 | exp.X_op = O_secrel; |
11525 | exp.X_add_symbol = symbol; | |
11526 | exp.X_add_number = 0; | |
11527 | emit_expr (&exp, size); | |
bb41ade5 AM |
11528 | } |
11529 | #endif | |
3b22753a L |
11530 | |
11531 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11532 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
11533 | ||
01e1a5bc | 11534 | bfd_vma |
6d4af3c2 | 11535 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
11536 | { |
11537 | if (flag_code == CODE_64BIT) | |
11538 | { | |
11539 | if (letter == 'l') | |
11540 | return SHF_X86_64_LARGE; | |
11541 | ||
8f3bae45 | 11542 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 11543 | } |
3b22753a | 11544 | else |
8f3bae45 | 11545 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
11546 | return -1; |
11547 | } | |
11548 | ||
01e1a5bc | 11549 | bfd_vma |
3b22753a L |
11550 | x86_64_section_word (char *str, size_t len) |
11551 | { | |
8620418b | 11552 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
11553 | return SHF_X86_64_LARGE; |
11554 | ||
11555 | return -1; | |
11556 | } | |
11557 | ||
11558 | static void | |
11559 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
11560 | { | |
11561 | if (flag_code != CODE_64BIT) | |
11562 | { | |
11563 | s_comm_internal (0, elf_common_parse); | |
11564 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
11565 | } | |
11566 | else | |
11567 | { | |
11568 | static segT lbss_section; | |
11569 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
11570 | asection *saved_bss_section = bss_section; | |
11571 | ||
11572 | if (lbss_section == NULL) | |
11573 | { | |
11574 | flagword applicable; | |
11575 | segT seg = now_seg; | |
11576 | subsegT subseg = now_subseg; | |
11577 | ||
11578 | /* The .lbss section is for local .largecomm symbols. */ | |
11579 | lbss_section = subseg_new (".lbss", 0); | |
11580 | applicable = bfd_applicable_section_flags (stdoutput); | |
11581 | bfd_set_section_flags (stdoutput, lbss_section, | |
11582 | applicable & SEC_ALLOC); | |
11583 | seg_info (lbss_section)->bss = 1; | |
11584 | ||
11585 | subseg_set (seg, subseg); | |
11586 | } | |
11587 | ||
11588 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11589 | bss_section = lbss_section; | |
11590 | ||
11591 | s_comm_internal (0, elf_common_parse); | |
11592 | ||
11593 | elf_com_section_ptr = saved_com_section_ptr; | |
11594 | bss_section = saved_bss_section; | |
11595 | } | |
11596 | } | |
11597 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |