]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - gas/config/tc-i386.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* bfd-in.h (BFD_HOST_LONG_LONG): Delete.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
1efbbeb4 61static void set_intel_mnemonic (int);
db51cc60 62static void set_allow_index_reg (int);
e3bb37b5 63static void set_cpu_arch (int);
6482c264 64#ifdef TE_PE
e3bb37b5 65static void pe_directive_secrel (int);
6482c264 66#endif
e3bb37b5
L		 67static void signed_cons (int);
68static char *output_invalid (int c);
a7619375 69static int i386_att_operand (char *);
e3bb37b5
L		 70static int i386_intel_operand (char *, int);
71static const reg_entry *parse_register (char *, char **);
72static char *parse_insn (char *, char *);
73static char *parse_operands (char *, const char *);
74static void swap_operands (void);
4d456e3d 75static void swap_2_operands (int, int);
e3bb37b5
L		 76static void optimize_imm (void);
77static void optimize_disp (void);
78static int match_template (void);
79static int check_string (void);
80static int process_suffix (void);
81static int check_byte_reg (void);
82static int check_long_reg (void);
83static int check_qword_reg (void);
84static int check_word_reg (void);
85static int finalize_imm (void);
85f10a01 86static void process_drex (void);
e3bb37b5
L		 87static int process_operands (void);
88static const seg_entry *build_modrm_byte (void);
89static void output_insn (void);
90static void output_imm (fragS *, offsetT);
91static void output_disp (fragS *, offsetT);
29b0f896 92#ifndef I386COFF
e3bb37b5 93static void s_bss (int);
252b5132 94#endif
17d4e2a2
L		 95#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96static void handle_large_common (int small ATTRIBUTE_UNUSED);
97#endif
252b5132 98
a847613f 99static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 100
252b5132 101/* 'md_assemble ()' gathers together information and puts it into a
47926f60 102 i386_insn. */
252b5132 103
520dc8e8
AM		 104union i386_op
105 {
106 expressionS *disps;
107 expressionS *imms;
108 const reg_entry *regs;
109 };
110
252b5132
RH		 111struct _i386_insn
112 {
47926f60 113 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 114 template tm;
115
7d5e4556
L		 116 /* SUFFIX holds the instruction size suffix for byte, word, dword
117 or qword, if given. */
252b5132
RH		 118 char suffix;
119
47926f60 120 /* OPERANDS gives the number of given operands. */
252b5132
RH		 121 unsigned int operands;
122
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
47926f60 125 operands. */
252b5132
RH		 126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
127
128 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 129 use OP[i] for the corresponding operand. */
40fb9820 130 i386_operand_type types[MAX_OPERANDS];
252b5132 131
520dc8e8
AM		 132 /* Displacement expression, immediate expression, or register for each
133 operand. */
134 union i386_op op[MAX_OPERANDS];
252b5132 135
3e73aa7c
JH		 136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138#define Operand_PCrel 1
139
252b5132 140 /* Relocation type for operand */
f86103b7 141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 142
252b5132
RH		 143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
148
149 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 150 explicit segment overrides are given. */
ce8a8b2f 151 const seg_entry *seg[2];
252b5132
RH		 152
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
157
158 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
252b5132
RH		 161
162 modrm_byte rm;
3e73aa7c 163 rex_byte rex;
252b5132 164 sib_byte sib;
85f10a01 165 drex_byte drex;
252b5132
RH		 166 };
167
168typedef struct _i386_insn i386_insn;
169
170/* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
32137342 172const char extra_symbol_chars[] = "*%-(["
252b5132 173#ifdef LEX_AT
32137342
NC		 174 "@"
175#endif
176#ifdef LEX_QM
177 "?"
252b5132 178#endif
32137342 179 ;
252b5132 180
29b0f896
AM		 181#if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 183 && !defined (TE_GNU) \
29b0f896 184 && !defined (TE_LINUX) \
32137342 185 && !defined (TE_NETWARE) \
29b0f896
AM		 186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
252b5132 188/* This array holds the chars that always start a comment. If the
b3b91714
AM		 189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191const char *i386_comment_chars = "#/";
192#define SVR4_COMMENT_CHARS 1
252b5132 193#define PREFIX_SEPARATOR '\\'
252b5132 194
b3b91714
AM		 195#else
196const char *i386_comment_chars = "#";
197#define PREFIX_SEPARATOR '/'
198#endif
199
252b5132
RH		 200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
b3b91714 208const char line_comment_chars[] = "#/";
252b5132 209
63a0b638 210const char line_separator_chars[] = ";";
252b5132 211
ce8a8b2f
AM		 212/* Chars that can be used to separate mant from exp in floating point
213 nums. */
252b5132
RH		 214const char EXP_CHARS[] = "eE";
215
ce8a8b2f
AM		 216/* Chars that mean this number is a floating point constant
217 As in 0f12.456
218 or 0d1.2345e12. */
252b5132
RH		 219const char FLT_CHARS[] = "fFdDxX";
220
ce8a8b2f 221/* Tables for lexical analysis. */
252b5132
RH		 222static char mnemonic_chars[256];
223static char register_chars[256];
224static char operand_chars[256];
225static char identifier_chars[256];
226static char digit_chars[256];
227
ce8a8b2f 228/* Lexical macros. */
252b5132
RH		 229#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230#define is_operand_char(x) (operand_chars[(unsigned char) x])
231#define is_register_char(x) (register_chars[(unsigned char) x])
232#define is_space_char(x) ((x) == ' ')
233#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234#define is_digit_char(x) (digit_chars[(unsigned char) x])
235
0234cb7c 236/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 237static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
238
239/* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
47926f60 242 assembler instruction). */
252b5132 243static char save_stack[32];
ce8a8b2f 244static char *save_stack_p;
252b5132
RH		 245#define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247#define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
249
47926f60 250/* The instruction we're assembling. */
252b5132
RH		 251static i386_insn i;
252
253/* Possible templates for current insn. */
254static const templates *current_templates;
255
31b2323c
L		 256/* Per instruction expressionS buffers: max displacements & immediates. */
257static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 259
47926f60
KH		 260/* Current operand we are working on. */
261static int this_operand;
252b5132 262
3e73aa7c
JH		 263/* We support four different modes. FLAG_CODE variable is used to distinguish
264 these. */
265
266enum flag_code {
267 CODE_32BIT,
268 CODE_16BIT,
269 CODE_64BIT };
270
271static enum flag_code flag_code;
4fa24527 272static unsigned int object_64bit;
3e73aa7c
JH		 273static int use_rela_relocations = 0;
274
275/* The names used to print error messages. */
b77a7acd 276static const char *flag_code_names[] =
3e73aa7c
JH		 277 {
278 "32",
279 "16",
280 "64"
281 };
252b5132 282
47926f60
KH		 283/* 1 for intel syntax,
284 0 if att syntax. */
285static int intel_syntax = 0;
252b5132 286
1efbbeb4
L		 287/* 1 for intel mnemonic,
288 0 if att mnemonic. */
289static int intel_mnemonic = !SYSV386_COMPAT;
290
5209009a 291/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 292static int old_gcc = OLDGCC_COMPAT;
293
47926f60
KH		 294/* 1 if register prefix % not required. */
295static int allow_naked_reg = 0;
252b5132 296
ba104c83 297/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 298static int allow_index_reg = 0;
299
2ca3ace5
L		 300/* Register prefix used for error message. */
301static const char *register_prefix = "%";
302
47926f60
KH		 303/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306static char stackop_size = '\0';
eecb386c 307
12b55ccc
L		 308/* Non-zero to optimize code alignment. */
309int optimize_align_code = 1;
310
47926f60
KH		 311/* Non-zero to quieten some warnings. */
312static int quiet_warnings = 0;
a38cf1db 313
47926f60
KH		 314/* CPU name. */
315static const char *cpu_arch_name = NULL;
5c6af06e 316static const char *cpu_sub_arch_name = NULL;
a38cf1db 317
47926f60 318/* CPU feature flags. */
40fb9820
L		 319static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
320
ccc9c027
L		 321/* If we have selected a cpu we are generating instructions for. */
322static int cpu_arch_tune_set = 0;
323
9103f4f4
L		 324/* Cpu we are generating instructions for. */
325static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
326
327/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 328static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 329
ccc9c027
L		 330/* CPU instruction set architecture used. */
331static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
332
9103f4f4 333/* CPU feature flags of instruction set architecture used. */
40fb9820 334static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 335
fddf5b5b
AM		 336/* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338static unsigned int no_cond_jump_promotion = 0;
339
29b0f896 340/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 341static symbolS *GOT_symbol;
29b0f896 342
a4447b93
RH		 343/* The dwarf2 return column, adjusted for 32 or 64 bit. */
344unsigned int x86_dwarf2_return_column;
345
346/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347int x86_cie_data_alignment;
348
252b5132 349/* Interface to relax_segment.
fddf5b5b
AM		 350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
252b5132 353
47926f60 354/* Types. */
93c2a809
AM		 355#define UNCOND_JUMP 0
356#define COND_JUMP 1
357#define COND_JUMP86 2
fddf5b5b 358
47926f60 359/* Sizes. */
252b5132
RH		 360#define CODE16 1
361#define SMALL 0
29b0f896 362#define SMALL16 (SMALL | CODE16)
252b5132 363#define BIG 2
29b0f896 364#define BIG16 (BIG | CODE16)
252b5132
RH		 365
366#ifndef INLINE
367#ifdef __GNUC__
368#define INLINE __inline__
369#else
370#define INLINE
371#endif
372#endif
373
fddf5b5b
AM		 374#define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376#define TYPE_FROM_RELAX_STATE(s) \
377 ((s) >> 2)
378#define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 380
381/* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
388
389const relax_typeS md_relax_table[] =
390{
24eab124
AM		 391 /* The fields are:
392 1) most positive reach of this state,
393 2) most negative reach of this state,
93c2a809 394 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 395 4) which index into the table to try if we can't fit into this one. */
252b5132 396
fddf5b5b 397 /* UNCOND_JUMP states. */
93c2a809
AM		 398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
252b5132 402 {0, 0, 4, 0},
93c2a809
AM		 403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 405 {0, 0, 2, 0},
406
93c2a809
AM		 407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
fddf5b5b 413 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 414 1 extra opcode byte, 2 displacement bytes. */
415 {0, 0, 3, 0},
416
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
422 {0, 0, 5, 0},
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
425 {0, 0, 4, 0}
252b5132
RH		 426};
427
9103f4f4
L		 428static const arch_entry cpu_arch[] =
429{
430 {"generic32", PROCESSOR_GENERIC32,
40fb9820 431 CPU_GENERIC32_FLAGS },
9103f4f4 432 {"generic64", PROCESSOR_GENERIC64,
40fb9820 433 CPU_GENERIC64_FLAGS },
9103f4f4 434 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 435 CPU_NONE_FLAGS },
9103f4f4 436 {"i186", PROCESSOR_UNKNOWN,
40fb9820 437 CPU_I186_FLAGS },
9103f4f4 438 {"i286", PROCESSOR_UNKNOWN,
40fb9820 439 CPU_I286_FLAGS },
76bc74dc 440 {"i386", PROCESSOR_I386,
40fb9820 441 CPU_I386_FLAGS },
9103f4f4 442 {"i486", PROCESSOR_I486,
40fb9820 443 CPU_I486_FLAGS },
9103f4f4 444 {"i586", PROCESSOR_PENTIUM,
40fb9820 445 CPU_I586_FLAGS },
9103f4f4 446 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 447 CPU_I686_FLAGS },
9103f4f4 448 {"pentium", PROCESSOR_PENTIUM,
40fb9820 449 CPU_I586_FLAGS },
9103f4f4 450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 451 CPU_I686_FLAGS },
9103f4f4 452 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 453 CPU_P2_FLAGS },
9103f4f4 454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 455 CPU_P3_FLAGS },
9103f4f4 456 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 457 CPU_P4_FLAGS },
9103f4f4 458 {"prescott", PROCESSOR_NOCONA,
40fb9820 459 CPU_CORE_FLAGS },
9103f4f4 460 {"nocona", PROCESSOR_NOCONA,
40fb9820 461 CPU_NOCONA_FLAGS },
ef05d495 462 {"yonah", PROCESSOR_CORE,
40fb9820 463 CPU_CORE_FLAGS },
ef05d495 464 {"core", PROCESSOR_CORE,
40fb9820 465 CPU_CORE_FLAGS },
ef05d495 466 {"merom", PROCESSOR_CORE2,
40fb9820 467 CPU_CORE2_FLAGS },
ef05d495 468 {"core2", PROCESSOR_CORE2,
40fb9820 469 CPU_CORE2_FLAGS },
9103f4f4 470 {"k6", PROCESSOR_K6,
40fb9820 471 CPU_K6_FLAGS },
9103f4f4 472 {"k6_2", PROCESSOR_K6,
40fb9820 473 CPU_K6_2_FLAGS },
9103f4f4 474 {"athlon", PROCESSOR_ATHLON,
40fb9820 475 CPU_ATHLON_FLAGS },
9103f4f4 476 {"sledgehammer", PROCESSOR_K8,
40fb9820 477 CPU_K8_FLAGS },
9103f4f4 478 {"opteron", PROCESSOR_K8,
40fb9820 479 CPU_K8_FLAGS },
9103f4f4 480 {"k8", PROCESSOR_K8,
40fb9820 481 CPU_K8_FLAGS },
050dfa73 482 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 483 CPU_AMDFAM10_FLAGS },
9103f4f4 484 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 485 CPU_MMX_FLAGS },
9103f4f4 486 {".sse", PROCESSOR_UNKNOWN,
40fb9820 487 CPU_SSE_FLAGS },
9103f4f4 488 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 489 CPU_SSE2_FLAGS },
9103f4f4 490 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 491 CPU_SSE3_FLAGS },
ef05d495 492 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 493 CPU_SSSE3_FLAGS },
42903f7f 494 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 495 CPU_SSE4_1_FLAGS },
381d071f 496 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 497 CPU_SSE4_2_FLAGS },
381d071f 498 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 499 CPU_SSE4_2_FLAGS },
9103f4f4 500 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 501 CPU_3DNOW_FLAGS },
9103f4f4 502 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 503 CPU_3DNOWA_FLAGS },
9103f4f4 504 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 505 CPU_PADLOCK_FLAGS },
9103f4f4 506 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 507 CPU_SVME_FLAGS },
9103f4f4 508 {".svme", PROCESSOR_UNKNOWN,
40fb9820 509 CPU_SVME_FLAGS },
050dfa73 510 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 511 CPU_SSE4A_FLAGS },
050dfa73 512 {".abm", PROCESSOR_UNKNOWN,
40fb9820 513 CPU_ABM_FLAGS },
85f10a01
MM		 514 {".sse5", PROCESSOR_UNKNOWN,
515 CPU_SSE5_FLAGS },
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
07a53e5c 548#else
e3bb37b5 549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 552#endif
6482c264
NC		 553#ifdef TE_PE
554 {"secrel32", pe_directive_secrel, 0},
555#endif
29b0f896
AM		 556 {0, 0, 0}
557};
558
559/* For interface with expression (). */
560extern char *input_line_pointer;
561
562/* Hash table for instruction mnemonic lookup. */
563static struct hash_control *op_hash;
564
565/* Hash table for register lookup. */
566static struct hash_control *reg_hash;
567\f
252b5132 568void
e3bb37b5 569i386_align_code (fragS *fragP, int count)
252b5132 570{
ce8a8b2f
AM		 571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
252b5132
RH		 574 static const char f32_1[] =
575 {0x90}; /* nop */
576 static const char f32_2[] =
ccc9c027 577 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
583 {0x90, /* nop */
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
590 {0x90, /* nop */
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
615 {0x90, /* nop */
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 634 };
635 static const char *const f16_patt[] = {
76bc74dc 636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
76bc74dc
L		 743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 745 return;
3e73aa7c 746
ccc9c027
L		 747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
4eed87de 749
76bc74dc
L		 750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 757
76bc74dc
L		 758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
760 be used.
ccc9c027
L		 761
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
764
765 if (flag_code == CODE_16BIT)
766 {
ccc9c027 767 if (count > 8)
33fef721 768 {
76bc74dc
L		 769 memcpy (fragP->fr_literal + fragP->fr_fix,
770 jump_31, count);
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 773 }
76bc74dc
L		 774 else
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
252b5132 777 }
33fef721 778 else
ccc9c027
L		 779 {
780 const char *const *patt = NULL;
781
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
783 {
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
786 {
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
40fb9820 790 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 791 patt = alt_long_patt;
ccc9c027
L		 792 else
793 patt = f32_patt;
794 break;
ccc9c027
L		 795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
ef05d495 798 case PROCESSOR_CORE:
76bc74dc
L		 799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
802 break;
ccc9c027
L		 803 case PROCESSOR_K6:
804 case PROCESSOR_ATHLON:
805 case PROCESSOR_K8:
4eed87de 806 case PROCESSOR_AMDFAM10:
ccc9c027
L		 807 patt = alt_short_patt;
808 break;
76bc74dc 809 case PROCESSOR_I386:
ccc9c027
L		 810 case PROCESSOR_I486:
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
813 patt = f32_patt;
814 break;
4eed87de 815 }
ccc9c027
L		 816 }
817 else
818 {
819 switch (cpu_arch_tune)
820 {
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
824 abort ();
825 break;
826
76bc74dc 827 case PROCESSOR_I386:
ccc9c027
L		 828 case PROCESSOR_I486:
829 case PROCESSOR_PENTIUM:
ccc9c027
L		 830 case PROCESSOR_K6:
831 case PROCESSOR_ATHLON:
832 case PROCESSOR_K8:
4eed87de 833 case PROCESSOR_AMDFAM10:
ccc9c027
L		 834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
836 for Cpu686. */
40fb9820 837 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 838 patt = alt_short_patt;
839 else
840 patt = f32_patt;
841 break;
76bc74dc
L		 842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
845 case PROCESSOR_CORE:
ef05d495 846 case PROCESSOR_CORE2:
40fb9820 847 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 848 patt = alt_long_patt;
849 else
850 patt = f32_patt;
851 break;
852 case PROCESSOR_GENERIC64:
76bc74dc 853 patt = alt_long_patt;
ccc9c027 854 break;
4eed87de 855 }
ccc9c027
L		 856 }
857
76bc74dc
L		 858 if (patt == f32_patt)
859 {
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
862 its offset. */
863 if (count < 15)
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
866 else
867 {
868 memcpy (fragP->fr_literal + fragP->fr_fix,
869 jump_31, count);
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
872 }
873 }
874 else
875 {
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
879 int padding = count;
880 while (padding > 15)
881 {
882 padding -= 15;
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
884 patt [14], 15);
885 }
886
887 if (padding)
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
890 }
ccc9c027 891 }
33fef721 892 fragP->fr_var = count;
252b5132
RH		 893}
894
c6fb90c8
L		 895static INLINE int
896uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 897{
c6fb90c8
L		 898 switch (size)
899 {
900 case 3:
901 if (x[2])
902 return 0;
903 case 2:
904 if (x[1])
905 return 0;
906 case 1:
907 return !x[0];
908 default:
909 abort ();
910 }
40fb9820
L		 911}
912
c6fb90c8
L		 913static INLINE void
914uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 915{
c6fb90c8
L		 916 switch (size)
917 {
918 case 3:
919 x[2] = v;
920 case 2:
921 x[1] = v;
922 case 1:
923 x[0] = v;
924 break;
925 default:
926 abort ();
927 }
928}
40fb9820 929
c6fb90c8
L		 930static INLINE int
931uints_equal (const unsigned int *x, const unsigned int *y,
932 unsigned int size)
933{
934 switch (size)
935 {
936 case 3:
937 if (x[2] != y [2])
938 return 0;
939 case 2:
940 if (x[1] != y [1])
941 return 0;
942 case 1:
943 return x[0] == y [0];
944 break;
945 default:
946 abort ();
947 }
948}
40fb9820 949
c6fb90c8
L		 950#define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952#define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954#define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956#define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
958
959static INLINE int
960cpu_flags_check_cpu64 (i386_cpu_flags f)
961{
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 964}
965
c6fb90c8
L		 966static INLINE i386_cpu_flags
967cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 968{
c6fb90c8
L		 969 switch (ARRAY_SIZE (x.array))
970 {
971 case 3:
972 x.array [2] &= y.array [2];
973 case 2:
974 x.array [1] &= y.array [1];
975 case 1:
976 x.array [0] &= y.array [0];
977 break;
978 default:
979 abort ();
980 }
981 return x;
982}
40fb9820 983
c6fb90c8
L		 984static INLINE i386_cpu_flags
985cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 986{
c6fb90c8 987 switch (ARRAY_SIZE (x.array))
40fb9820 988 {
c6fb90c8
L		 989 case 3:
990 x.array [2] |= y.array [2];
991 case 2:
992 x.array [1] |= y.array [1];
993 case 1:
994 x.array [0] |= y.array [0];
40fb9820
L		 995 break;
996 default:
997 abort ();
998 }
40fb9820
L		 999 return x;
1000}
1001
3629bb00
L		 1002/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1004
40fb9820
L		 1005static int
1006cpu_flags_match (i386_cpu_flags x)
1007{
3629bb00 1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1009
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1012
3629bb00
L		 1013 if (UINTS_ALL_ZERO (x))
1014 overlap |= 1;
1015 else
1016 {
1017 i386_cpu_flags cpu = cpu_arch_flags;
1018
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1023 }
1024 return overlap;
40fb9820
L		 1025}
1026
c6fb90c8
L		 1027static INLINE i386_operand_type
1028operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1029{
c6fb90c8
L		 1030 switch (ARRAY_SIZE (x.array))
1031 {
1032 case 3:
1033 x.array [2] &= y.array [2];
1034 case 2:
1035 x.array [1] &= y.array [1];
1036 case 1:
1037 x.array [0] &= y.array [0];
1038 break;
1039 default:
1040 abort ();
1041 }
1042 return x;
40fb9820
L		 1043}
1044
c6fb90c8
L		 1045static INLINE i386_operand_type
1046operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1047{
c6fb90c8 1048 switch (ARRAY_SIZE (x.array))
40fb9820 1049 {
c6fb90c8
L		 1050 case 3:
1051 x.array [2] |= y.array [2];
1052 case 2:
1053 x.array [1] |= y.array [1];
1054 case 1:
1055 x.array [0] |= y.array [0];
40fb9820
L		 1056 break;
1057 default:
1058 abort ();
1059 }
c6fb90c8
L		 1060 return x;
1061}
40fb9820 1062
c6fb90c8
L		 1063static INLINE i386_operand_type
1064operand_type_xor (i386_operand_type x, i386_operand_type y)
1065{
1066 switch (ARRAY_SIZE (x.array))
1067 {
1068 case 3:
1069 x.array [2] ^= y.array [2];
1070 case 2:
1071 x.array [1] ^= y.array [1];
1072 case 1:
1073 x.array [0] ^= y.array [0];
1074 break;
1075 default:
1076 abort ();
1077 }
40fb9820
L		 1078 return x;
1079}
1080
1081static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1092static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1102
1103enum operand_type
1104{
1105 reg,
40fb9820
L		 1106 imm,
1107 disp,
1108 anymem
1109};
1110
c6fb90c8 1111static INLINE int
40fb9820
L		 1112operand_type_check (i386_operand_type t, enum operand_type c)
1113{
1114 switch (c)
1115 {
1116 case reg:
1117 return (t.bitfield.reg8
1118 || t.bitfield.reg16
1119 || t.bitfield.reg32
1120 || t.bitfield.reg64);
1121
40fb9820
L		 1122 case imm:
1123 return (t.bitfield.imm8
1124 || t.bitfield.imm8s
1125 || t.bitfield.imm16
1126 || t.bitfield.imm32
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1129
1130 case disp:
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1136
1137 case anymem:
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1144
1145 default:
1146 abort ();
1147 }
1148}
1149
c6fb90c8 1150static INLINE int
40fb9820
L		 1151operand_type_match (i386_operand_type overlap,
1152 i386_operand_type given)
1153{
1154 i386_operand_type temp = overlap;
1155
1156 temp.bitfield.jumpabsolute = 0;
7d5e4556 1157 temp.bitfield.unspecified = 0;
c6fb90c8 1158 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1159 return 0;
1160
1161 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1162 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1163}
1164
7d5e4556 1165/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1166 unless the expected operand type register overlap is null.
1167 Note that Acc in a template matches every size of reg. */
1168
c6fb90c8 1169static INLINE int
40fb9820
L		 1170operand_type_register_match (i386_operand_type m0,
1171 i386_operand_type g0,
1172 i386_operand_type t0,
1173 i386_operand_type m1,
1174 i386_operand_type g1,
1175 i386_operand_type t1)
1176{
1177 if (!operand_type_check (g0, reg))
1178 return 1;
1179
1180 if (!operand_type_check (g1, reg))
1181 return 1;
1182
1183 if (g0.bitfield.reg8 == g1.bitfield.reg8
1184 && g0.bitfield.reg16 == g1.bitfield.reg16
1185 && g0.bitfield.reg32 == g1.bitfield.reg32
1186 && g0.bitfield.reg64 == g1.bitfield.reg64)
1187 return 1;
1188
1189 if (m0.bitfield.acc)
1190 {
1191 t0.bitfield.reg8 = 1;
1192 t0.bitfield.reg16 = 1;
1193 t0.bitfield.reg32 = 1;
1194 t0.bitfield.reg64 = 1;
1195 }
1196
1197 if (m1.bitfield.acc)
1198 {
1199 t1.bitfield.reg8 = 1;
1200 t1.bitfield.reg16 = 1;
1201 t1.bitfield.reg32 = 1;
1202 t1.bitfield.reg64 = 1;
1203 }
1204
1205 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1206 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1207 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1208 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1209}
1210
252b5132 1211static INLINE unsigned int
40fb9820 1212mode_from_disp_size (i386_operand_type t)
252b5132 1213{
40fb9820
L		 1214 if (t.bitfield.disp8)
1215 return 1;
1216 else if (t.bitfield.disp16
1217 || t.bitfield.disp32
1218 || t.bitfield.disp32s)
1219 return 2;
1220 else
1221 return 0;
252b5132
RH		 1222}
1223
1224static INLINE int
e3bb37b5 1225fits_in_signed_byte (offsetT num)
252b5132
RH		 1226{
1227 return (num >= -128) && (num <= 127);
47926f60 1228}
252b5132
RH		 1229
1230static INLINE int
e3bb37b5 1231fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1232{
1233 return (num & 0xff) == num;
47926f60 1234}
252b5132
RH		 1235
1236static INLINE int
e3bb37b5 1237fits_in_unsigned_word (offsetT num)
252b5132
RH		 1238{
1239 return (num & 0xffff) == num;
47926f60 1240}
252b5132
RH		 1241
1242static INLINE int
e3bb37b5 1243fits_in_signed_word (offsetT num)
252b5132
RH		 1244{
1245 return (-32768 <= num) && (num <= 32767);
47926f60 1246}
2a962e6d 1247
3e73aa7c 1248static INLINE int
e3bb37b5 1249fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1250{
1251#ifndef BFD64
1252 return 1;
1253#else
1254 return (!(((offsetT) -1 << 31) & num)
1255 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1256#endif
1257} /* fits_in_signed_long() */
2a962e6d 1258
3e73aa7c 1259static INLINE int
e3bb37b5 1260fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1261{
1262#ifndef BFD64
1263 return 1;
1264#else
1265 return (num & (((offsetT) 2 << 31) - 1)) == num;
1266#endif
1267} /* fits_in_unsigned_long() */
252b5132 1268
40fb9820 1269static i386_operand_type
e3bb37b5 1270smallest_imm_type (offsetT num)
252b5132 1271{
40fb9820
L		 1272 i386_operand_type t;
1273
c6fb90c8 1274 UINTS_CLEAR (t);
40fb9820
L		 1275 t.bitfield.imm64 = 1;
1276
1277 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1278 {
1279 /* This code is disabled on the 486 because all the Imm1 forms
1280 in the opcode table are slower on the i486. They're the
1281 versions with the implicitly specified single-position
1282 displacement, which has another syntax if you really want to
1283 use that form. */
40fb9820
L		 1284 t.bitfield.imm1 = 1;
1285 t.bitfield.imm8 = 1;
1286 t.bitfield.imm8s = 1;
1287 t.bitfield.imm16 = 1;
1288 t.bitfield.imm32 = 1;
1289 t.bitfield.imm32s = 1;
1290 }
1291 else if (fits_in_signed_byte (num))
1292 {
1293 t.bitfield.imm8 = 1;
1294 t.bitfield.imm8s = 1;
1295 t.bitfield.imm16 = 1;
1296 t.bitfield.imm32 = 1;
1297 t.bitfield.imm32s = 1;
1298 }
1299 else if (fits_in_unsigned_byte (num))
1300 {
1301 t.bitfield.imm8 = 1;
1302 t.bitfield.imm16 = 1;
1303 t.bitfield.imm32 = 1;
1304 t.bitfield.imm32s = 1;
1305 }
1306 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1307 {
1308 t.bitfield.imm16 = 1;
1309 t.bitfield.imm32 = 1;
1310 t.bitfield.imm32s = 1;
1311 }
1312 else if (fits_in_signed_long (num))
1313 {
1314 t.bitfield.imm32 = 1;
1315 t.bitfield.imm32s = 1;
1316 }
1317 else if (fits_in_unsigned_long (num))
1318 t.bitfield.imm32 = 1;
1319
1320 return t;
47926f60 1321}
252b5132 1322
847f7ad4 1323static offsetT
e3bb37b5 1324offset_in_range (offsetT val, int size)
847f7ad4 1325{
508866be 1326 addressT mask;
ba2adb93 1327
847f7ad4
AM		 1328 switch (size)
1329 {
508866be
L		 1330 case 1: mask = ((addressT) 1 << 8) - 1; break;
1331 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1332 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1333#ifdef BFD64
1334 case 8: mask = ((addressT) 2 << 63) - 1; break;
1335#endif
47926f60 1336 default: abort ();
847f7ad4
AM		 1337 }
1338
ba2adb93 1339 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1340 if (!use_rela_relocations)
1341 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1342 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1343
47926f60 1344 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1345 {
1346 char buf1[40], buf2[40];
1347
1348 sprint_value (buf1, val);
1349 sprint_value (buf2, val & mask);
1350 as_warn (_("%s shortened to %s"), buf1, buf2);
1351 }
1352 return val & mask;
1353}
1354
252b5132
RH		 1355/* Returns 0 if attempting to add a prefix where one from the same
1356 class already exists, 1 if non rep/repne added, 2 if rep/repne
1357 added. */
1358static int
e3bb37b5 1359add_prefix (unsigned int prefix)
252b5132
RH		 1360{
1361 int ret = 1;
b1905489 1362 unsigned int q;
252b5132 1363
29b0f896
AM		 1364 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1365 && flag_code == CODE_64BIT)
b1905489 1366 {
161a04f6
L		 1367 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1368 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1369 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1370 ret = 0;
1371 q = REX_PREFIX;
1372 }
3e73aa7c 1373 else
b1905489
JB		 1374 {
1375 switch (prefix)
1376 {
1377 default:
1378 abort ();
1379
1380 case CS_PREFIX_OPCODE:
1381 case DS_PREFIX_OPCODE:
1382 case ES_PREFIX_OPCODE:
1383 case FS_PREFIX_OPCODE:
1384 case GS_PREFIX_OPCODE:
1385 case SS_PREFIX_OPCODE:
1386 q = SEG_PREFIX;
1387 break;
1388
1389 case REPNE_PREFIX_OPCODE:
1390 case REPE_PREFIX_OPCODE:
1391 ret = 2;
1392 /* fall thru */
1393 case LOCK_PREFIX_OPCODE:
1394 q = LOCKREP_PREFIX;
1395 break;
1396
1397 case FWAIT_OPCODE:
1398 q = WAIT_PREFIX;
1399 break;
1400
1401 case ADDR_PREFIX_OPCODE:
1402 q = ADDR_PREFIX;
1403 break;
1404
1405 case DATA_PREFIX_OPCODE:
1406 q = DATA_PREFIX;
1407 break;
1408 }
1409 if (i.prefix[q] != 0)
1410 ret = 0;
1411 }
252b5132 1412
b1905489 1413 if (ret)
252b5132 1414 {
b1905489
JB		 1415 if (!i.prefix[q])
1416 ++i.prefixes;
1417 i.prefix[q] |= prefix;
252b5132 1418 }
b1905489
JB		 1419 else
1420 as_bad (_("same type of prefix used twice"));
252b5132 1421
252b5132
RH		 1422 return ret;
1423}
1424
1425static void
e3bb37b5 1426set_code_flag (int value)
eecb386c 1427{
3e73aa7c 1428 flag_code = value;
40fb9820
L		 1429 if (flag_code == CODE_64BIT)
1430 {
1431 cpu_arch_flags.bitfield.cpu64 = 1;
1432 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1433 }
1434 else
1435 {
1436 cpu_arch_flags.bitfield.cpu64 = 0;
1437 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1438 }
1439 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1440 {
1441 as_bad (_("64bit mode not supported on this CPU."));
1442 }
40fb9820 1443 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1444 {
1445 as_bad (_("32bit mode not supported on this CPU."));
1446 }
eecb386c
AM		 1447 stackop_size = '\0';
1448}
1449
1450static void
e3bb37b5 1451set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1452{
3e73aa7c 1453 flag_code = new_code_flag;
40fb9820
L		 1454 if (flag_code != CODE_16BIT)
1455 abort ();
1456 cpu_arch_flags.bitfield.cpu64 = 0;
1457 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1458 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1459}
1460
1461static void
e3bb37b5 1462set_intel_syntax (int syntax_flag)
252b5132
RH		 1463{
1464 /* Find out if register prefixing is specified. */
1465 int ask_naked_reg = 0;
1466
1467 SKIP_WHITESPACE ();
29b0f896 1468 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1469 {
1470 char *string = input_line_pointer;
1471 int e = get_symbol_end ();
1472
47926f60 1473 if (strcmp (string, "prefix") == 0)
252b5132 1474 ask_naked_reg = 1;
47926f60 1475 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1476 ask_naked_reg = -1;
1477 else
d0b47220 1478 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1479 *input_line_pointer = e;
1480 }
1481 demand_empty_rest_of_line ();
c3332e24 1482
252b5132
RH		 1483 intel_syntax = syntax_flag;
1484
1485 if (ask_naked_reg == 0)
f86103b7
AM		 1486 allow_naked_reg = (intel_syntax
1487 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1488 else
1489 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1490
e4a3b5a4 1491 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1492 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1493 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1494}
1495
1efbbeb4
L		 1496static void
1497set_intel_mnemonic (int mnemonic_flag)
1498{
e1d4d893 1499 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1500}
1501
db51cc60
L		 1502static void
1503set_allow_index_reg (int flag)
1504{
1505 allow_index_reg = flag;
1506}
1507
e413e4e9 1508static void
e3bb37b5 1509set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1510{
47926f60 1511 SKIP_WHITESPACE ();
e413e4e9 1512
29b0f896 1513 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1514 {
1515 char *string = input_line_pointer;
1516 int e = get_symbol_end ();
9103f4f4 1517 unsigned int i;
40fb9820 1518 i386_cpu_flags flags;
e413e4e9 1519
9103f4f4 1520 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1521 {
1522 if (strcmp (string, cpu_arch[i].name) == 0)
1523 {
5c6af06e
JB		 1524 if (*string != '.')
1525 {
1526 cpu_arch_name = cpu_arch[i].name;
1527 cpu_sub_arch_name = NULL;
40fb9820
L		 1528 cpu_arch_flags = cpu_arch[i].flags;
1529 if (flag_code == CODE_64BIT)
1530 {
1531 cpu_arch_flags.bitfield.cpu64 = 1;
1532 cpu_arch_flags.bitfield.cpuno64 = 0;
1533 }
1534 else
1535 {
1536 cpu_arch_flags.bitfield.cpu64 = 0;
1537 cpu_arch_flags.bitfield.cpuno64 = 1;
1538 }
ccc9c027 1539 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1540 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1541 if (!cpu_arch_tune_set)
1542 {
1543 cpu_arch_tune = cpu_arch_isa;
1544 cpu_arch_tune_flags = cpu_arch_isa_flags;
1545 }
5c6af06e
JB		 1546 break;
1547 }
40fb9820 1548
c6fb90c8
L		 1549 flags = cpu_flags_or (cpu_arch_flags,
1550 cpu_arch[i].flags);
1551 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1552 {
1553 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820 1554 cpu_arch_flags = flags;
5c6af06e
JB		 1555 }
1556 *input_line_pointer = e;
1557 demand_empty_rest_of_line ();
1558 return;
e413e4e9
AM		 1559 }
1560 }
9103f4f4 1561 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1562 as_bad (_("no such architecture: `%s'"), string);
1563
1564 *input_line_pointer = e;
1565 }
1566 else
1567 as_bad (_("missing cpu architecture"));
1568
fddf5b5b
AM		 1569 no_cond_jump_promotion = 0;
1570 if (*input_line_pointer == ','
29b0f896 1571 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1572 {
1573 char *string = ++input_line_pointer;
1574 int e = get_symbol_end ();
1575
1576 if (strcmp (string, "nojumps") == 0)
1577 no_cond_jump_promotion = 1;
1578 else if (strcmp (string, "jumps") == 0)
1579 ;
1580 else
1581 as_bad (_("no such architecture modifier: `%s'"), string);
1582
1583 *input_line_pointer = e;
1584 }
1585
e413e4e9
AM		 1586 demand_empty_rest_of_line ();
1587}
1588
b9d79e03
JH		 1589unsigned long
1590i386_mach ()
1591{
1592 if (!strcmp (default_arch, "x86_64"))
1593 return bfd_mach_x86_64;
1594 else if (!strcmp (default_arch, "i386"))
1595 return bfd_mach_i386_i386;
1596 else
1597 as_fatal (_("Unknown architecture"));
1598}
b9d79e03 1599\f
252b5132
RH		 1600void
1601md_begin ()
1602{
1603 const char *hash_err;
1604
47926f60 1605 /* Initialize op_hash hash table. */
252b5132
RH		 1606 op_hash = hash_new ();
1607
1608 {
29b0f896
AM		 1609 const template *optab;
1610 templates *core_optab;
252b5132 1611
47926f60
KH		 1612 /* Setup for loop. */
1613 optab = i386_optab;
252b5132
RH		 1614 core_optab = (templates *) xmalloc (sizeof (templates));
1615 core_optab->start = optab;
1616
1617 while (1)
1618 {
1619 ++optab;
1620 if (optab->name == NULL
1621 || strcmp (optab->name, (optab - 1)->name) != 0)
1622 {
1623 /* different name --> ship out current template list;
47926f60 1624 add to hash table; & begin anew. */
252b5132
RH		 1625 core_optab->end = optab;
1626 hash_err = hash_insert (op_hash,
1627 (optab - 1)->name,
1628 (PTR) core_optab);
1629 if (hash_err)
1630 {
252b5132
RH		 1631 as_fatal (_("Internal Error: Can't hash %s: %s"),
1632 (optab - 1)->name,
1633 hash_err);
1634 }
1635 if (optab->name == NULL)
1636 break;
1637 core_optab = (templates *) xmalloc (sizeof (templates));
1638 core_optab->start = optab;
1639 }
1640 }
1641 }
1642
47926f60 1643 /* Initialize reg_hash hash table. */
252b5132
RH		 1644 reg_hash = hash_new ();
1645 {
29b0f896 1646 const reg_entry *regtab;
c3fe08fa 1647 unsigned int regtab_size = i386_regtab_size;
252b5132 1648
c3fe08fa 1649 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1650 {
1651 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1652 if (hash_err)
3e73aa7c
JH		 1653 as_fatal (_("Internal Error: Can't hash %s: %s"),
1654 regtab->reg_name,
1655 hash_err);
252b5132
RH		 1656 }
1657 }
1658
47926f60 1659 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1660 {
29b0f896
AM		 1661 int c;
1662 char *p;
252b5132
RH		 1663
1664 for (c = 0; c < 256; c++)
1665 {
3882b010 1666 if (ISDIGIT (c))
252b5132
RH		 1667 {
1668 digit_chars[c] = c;
1669 mnemonic_chars[c] = c;
1670 register_chars[c] = c;
1671 operand_chars[c] = c;
1672 }
3882b010 1673 else if (ISLOWER (c))
252b5132
RH		 1674 {
1675 mnemonic_chars[c] = c;
1676 register_chars[c] = c;
1677 operand_chars[c] = c;
1678 }
3882b010 1679 else if (ISUPPER (c))
252b5132 1680 {
3882b010 1681 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1682 register_chars[c] = mnemonic_chars[c];
1683 operand_chars[c] = c;
1684 }
1685
3882b010 1686 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1687 identifier_chars[c] = c;
1688 else if (c >= 128)
1689 {
1690 identifier_chars[c] = c;
1691 operand_chars[c] = c;
1692 }
1693 }
1694
1695#ifdef LEX_AT
1696 identifier_chars['@'] = '@';
32137342
NC		 1697#endif
1698#ifdef LEX_QM
1699 identifier_chars['?'] = '?';
1700 operand_chars['?'] = '?';
252b5132 1701#endif
252b5132 1702 digit_chars['-'] = '-';
791fe849 1703 mnemonic_chars['-'] = '-';
0003779b 1704 mnemonic_chars['.'] = '.';
252b5132
RH		 1705 identifier_chars['_'] = '_';
1706 identifier_chars['.'] = '.';
1707
1708 for (p = operand_special_chars; *p != '\0'; p++)
1709 operand_chars[(unsigned char) *p] = *p;
1710 }
1711
1712#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1713 if (IS_ELF)
252b5132
RH		 1714 {
1715 record_alignment (text_section, 2);
1716 record_alignment (data_section, 2);
1717 record_alignment (bss_section, 2);
1718 }
1719#endif
a4447b93
RH		 1720
1721 if (flag_code == CODE_64BIT)
1722 {
1723 x86_dwarf2_return_column = 16;
1724 x86_cie_data_alignment = -8;
1725 }
1726 else
1727 {
1728 x86_dwarf2_return_column = 8;
1729 x86_cie_data_alignment = -4;
1730 }
252b5132
RH		 1731}
1732
1733void
e3bb37b5 1734i386_print_statistics (FILE *file)
252b5132
RH		 1735{
1736 hash_print_statistics (file, "i386 opcode", op_hash);
1737 hash_print_statistics (file, "i386 register", reg_hash);
1738}
1739\f
252b5132
RH		 1740#ifdef DEBUG386
1741
ce8a8b2f 1742/* Debugging routines for md_assemble. */
e3bb37b5 1743static void pte (template *);
40fb9820 1744static void pt (i386_operand_type);
e3bb37b5
L		 1745static void pe (expressionS *);
1746static void ps (symbolS *);
252b5132
RH		 1747
1748static void
e3bb37b5 1749pi (char *line, i386_insn *x)
252b5132 1750{
09f131f2 1751 unsigned int i;
252b5132
RH		 1752
1753 fprintf (stdout, "%s: template ", line);
1754 pte (&x->tm);
09f131f2
JH		 1755 fprintf (stdout, " address: base %s index %s scale %x\n",
1756 x->base_reg ? x->base_reg->reg_name : "none",
1757 x->index_reg ? x->index_reg->reg_name : "none",
1758 x->log2_scale_factor);
1759 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1760 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1761 fprintf (stdout, " sib: base %x index %x scale %x\n",
1762 x->sib.base, x->sib.index, x->sib.scale);
1763 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1764 (x->rex & REX_W) != 0,
1765 (x->rex & REX_R) != 0,
1766 (x->rex & REX_X) != 0,
1767 (x->rex & REX_B) != 0);
85f10a01
MM		 1768 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1769 x->drex.reg, x->drex.rex);
252b5132
RH		 1770 for (i = 0; i < x->operands; i++)
1771 {
1772 fprintf (stdout, " #%d: ", i + 1);
1773 pt (x->types[i]);
1774 fprintf (stdout, "\n");
40fb9820
L		 1775 if (x->types[i].bitfield.reg8
1776 || x->types[i].bitfield.reg16
1777 || x->types[i].bitfield.reg32
1778 || x->types[i].bitfield.reg64
1779 || x->types[i].bitfield.regmmx
1780 || x->types[i].bitfield.regxmm
1781 || x->types[i].bitfield.sreg2
1782 || x->types[i].bitfield.sreg3
1783 || x->types[i].bitfield.control
1784 || x->types[i].bitfield.debug
1785 || x->types[i].bitfield.test)
520dc8e8 1786 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1787 if (operand_type_check (x->types[i], imm))
520dc8e8 1788 pe (x->op[i].imms);
40fb9820 1789 if (operand_type_check (x->types[i], disp))
520dc8e8 1790 pe (x->op[i].disps);
252b5132
RH		 1791 }
1792}
1793
1794static void
e3bb37b5 1795pte (template *t)
252b5132 1796{
09f131f2 1797 unsigned int i;
252b5132 1798 fprintf (stdout, " %d operands ", t->operands);
47926f60 1799 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1800 if (t->extension_opcode != None)
1801 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1802 if (t->opcode_modifier.d)
252b5132 1803 fprintf (stdout, "D");
40fb9820 1804 if (t->opcode_modifier.w)
252b5132
RH		 1805 fprintf (stdout, "W");
1806 fprintf (stdout, "\n");
1807 for (i = 0; i < t->operands; i++)
1808 {
1809 fprintf (stdout, " #%d type ", i + 1);
1810 pt (t->operand_types[i]);
1811 fprintf (stdout, "\n");
1812 }
1813}
1814
1815static void
e3bb37b5 1816pe (expressionS *e)
252b5132 1817{
24eab124 1818 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1819 fprintf (stdout, " add_number %ld (%lx)\n",
1820 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1821 if (e->X_add_symbol)
1822 {
1823 fprintf (stdout, " add_symbol ");
1824 ps (e->X_add_symbol);
1825 fprintf (stdout, "\n");
1826 }
1827 if (e->X_op_symbol)
1828 {
1829 fprintf (stdout, " op_symbol ");
1830 ps (e->X_op_symbol);
1831 fprintf (stdout, "\n");
1832 }
1833}
1834
1835static void
e3bb37b5 1836ps (symbolS *s)
252b5132
RH		 1837{
1838 fprintf (stdout, "%s type %s%s",
1839 S_GET_NAME (s),
1840 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1841 segment_name (S_GET_SEGMENT (s)));
1842}
1843
7b81dfbb 1844static struct type_name
252b5132 1845 {
40fb9820
L		 1846 i386_operand_type mask;
1847 const char *name;
252b5132 1848 }
7b81dfbb 1849const type_names[] =
252b5132 1850{
40fb9820
L		 1851 { OPERAND_TYPE_REG8, "r8" },
1852 { OPERAND_TYPE_REG16, "r16" },
1853 { OPERAND_TYPE_REG32, "r32" },
1854 { OPERAND_TYPE_REG64, "r64" },
1855 { OPERAND_TYPE_IMM8, "i8" },
1856 { OPERAND_TYPE_IMM8, "i8s" },
1857 { OPERAND_TYPE_IMM16, "i16" },
1858 { OPERAND_TYPE_IMM32, "i32" },
1859 { OPERAND_TYPE_IMM32S, "i32s" },
1860 { OPERAND_TYPE_IMM64, "i64" },
1861 { OPERAND_TYPE_IMM1, "i1" },
1862 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1863 { OPERAND_TYPE_DISP8, "d8" },
1864 { OPERAND_TYPE_DISP16, "d16" },
1865 { OPERAND_TYPE_DISP32, "d32" },
1866 { OPERAND_TYPE_DISP32S, "d32s" },
1867 { OPERAND_TYPE_DISP64, "d64" },
1868 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1869 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1870 { OPERAND_TYPE_CONTROL, "control reg" },
1871 { OPERAND_TYPE_TEST, "test reg" },
1872 { OPERAND_TYPE_DEBUG, "debug reg" },
1873 { OPERAND_TYPE_FLOATREG, "FReg" },
1874 { OPERAND_TYPE_FLOATACC, "FAcc" },
1875 { OPERAND_TYPE_SREG2, "SReg2" },
1876 { OPERAND_TYPE_SREG3, "SReg3" },
1877 { OPERAND_TYPE_ACC, "Acc" },
1878 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1879 { OPERAND_TYPE_REGMMX, "rMMX" },
1880 { OPERAND_TYPE_REGXMM, "rXMM" },
1881 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1882};
1883
1884static void
40fb9820 1885pt (i386_operand_type t)
252b5132 1886{
40fb9820 1887 unsigned int j;
c6fb90c8 1888 i386_operand_type a;
252b5132 1889
40fb9820 1890 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1891 {
1892 a = operand_type_and (t, type_names[j].mask);
1893 if (!UINTS_ALL_ZERO (a))
1894 fprintf (stdout, "%s, ", type_names[j].name);
1895 }
252b5132
RH		 1896 fflush (stdout);
1897}
1898
1899#endif /* DEBUG386 */
1900\f
252b5132 1901static bfd_reloc_code_real_type
3956db08 1902reloc (unsigned int size,
64e74474
AM		 1903 int pcrel,
1904 int sign,
1905 bfd_reloc_code_real_type other)
252b5132 1906{
47926f60 1907 if (other != NO_RELOC)
3956db08
JB		 1908 {
1909 reloc_howto_type *reloc;
1910
1911 if (size == 8)
1912 switch (other)
1913 {
64e74474
AM		 1914 case BFD_RELOC_X86_64_GOT32:
1915 return BFD_RELOC_X86_64_GOT64;
1916 break;
1917 case BFD_RELOC_X86_64_PLTOFF64:
1918 return BFD_RELOC_X86_64_PLTOFF64;
1919 break;
1920 case BFD_RELOC_X86_64_GOTPC32:
1921 other = BFD_RELOC_X86_64_GOTPC64;
1922 break;
1923 case BFD_RELOC_X86_64_GOTPCREL:
1924 other = BFD_RELOC_X86_64_GOTPCREL64;
1925 break;
1926 case BFD_RELOC_X86_64_TPOFF32:
1927 other = BFD_RELOC_X86_64_TPOFF64;
1928 break;
1929 case BFD_RELOC_X86_64_DTPOFF32:
1930 other = BFD_RELOC_X86_64_DTPOFF64;
1931 break;
1932 default:
1933 break;
3956db08 1934 }
e05278af
JB		 1935
1936 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1937 if (size == 4 && flag_code != CODE_64BIT)
1938 sign = -1;
1939
3956db08
JB		 1940 reloc = bfd_reloc_type_lookup (stdoutput, other);
1941 if (!reloc)
1942 as_bad (_("unknown relocation (%u)"), other);
1943 else if (size != bfd_get_reloc_size (reloc))
1944 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1945 bfd_get_reloc_size (reloc),
1946 size);
1947 else if (pcrel && !reloc->pc_relative)
1948 as_bad (_("non-pc-relative relocation for pc-relative field"));
1949 else if ((reloc->complain_on_overflow == complain_overflow_signed
1950 && !sign)
1951 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1952 && sign > 0))
3956db08
JB		 1953 as_bad (_("relocated field and relocation type differ in signedness"));
1954 else
1955 return other;
1956 return NO_RELOC;
1957 }
252b5132
RH		 1958
1959 if (pcrel)
1960 {
3e73aa7c 1961 if (!sign)
3956db08 1962 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1963 switch (size)
1964 {
1965 case 1: return BFD_RELOC_8_PCREL;
1966 case 2: return BFD_RELOC_16_PCREL;
1967 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1968 case 8: return BFD_RELOC_64_PCREL;
252b5132 1969 }
3956db08 1970 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1971 }
1972 else
1973 {
3956db08 1974 if (sign > 0)
e5cb08ac 1975 switch (size)
3e73aa7c
JH		 1976 {
1977 case 4: return BFD_RELOC_X86_64_32S;
1978 }
1979 else
1980 switch (size)
1981 {
1982 case 1: return BFD_RELOC_8;
1983 case 2: return BFD_RELOC_16;
1984 case 4: return BFD_RELOC_32;
1985 case 8: return BFD_RELOC_64;
1986 }
3956db08
JB		 1987 as_bad (_("cannot do %s %u byte relocation"),
1988 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1989 }
1990
bfb32b52 1991 abort ();
252b5132
RH		 1992 return BFD_RELOC_NONE;
1993}
1994
47926f60
KH		 1995/* Here we decide which fixups can be adjusted to make them relative to
1996 the beginning of the section instead of the symbol. Basically we need
1997 to make sure that the dynamic relocations are done correctly, so in
1998 some cases we force the original symbol to be used. */
1999
252b5132 2000int
e3bb37b5 2001tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2002{
6d249963 2003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2004 if (!IS_ELF)
31312f95
AM		 2005 return 1;
2006
a161fe53
AM		 2007 /* Don't adjust pc-relative references to merge sections in 64-bit
2008 mode. */
2009 if (use_rela_relocations
2010 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2011 && fixP->fx_pcrel)
252b5132 2012 return 0;
31312f95 2013
8d01d9a9
AJ		 2014 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2015 and changed later by validate_fix. */
2016 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2017 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2018 return 0;
2019
ce8a8b2f 2020 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2021 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2022 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2023 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2024 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2026 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2028 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2029 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2034 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2036 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2038 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2040 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2041 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2043 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2046 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2047 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2048 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2049 return 0;
31312f95 2050#endif
252b5132
RH		 2051 return 1;
2052}
252b5132 2053
b4cac588 2054static int
e3bb37b5 2055intel_float_operand (const char *mnemonic)
252b5132 2056{
9306ca4a
JB		 2057 /* Note that the value returned is meaningful only for opcodes with (memory)
2058 operands, hence the code here is free to improperly handle opcodes that
2059 have no operands (for better performance and smaller code). */
2060
2061 if (mnemonic[0] != 'f')
2062 return 0; /* non-math */
2063
2064 switch (mnemonic[1])
2065 {
2066 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2067 the fs segment override prefix not currently handled because no
2068 call path can make opcodes without operands get here */
2069 case 'i':
2070 return 2 /* integer op */;
2071 case 'l':
2072 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2073 return 3; /* fldcw/fldenv */
2074 break;
2075 case 'n':
2076 if (mnemonic[2] != 'o' /* fnop */)
2077 return 3; /* non-waiting control op */
2078 break;
2079 case 'r':
2080 if (mnemonic[2] == 's')
2081 return 3; /* frstor/frstpm */
2082 break;
2083 case 's':
2084 if (mnemonic[2] == 'a')
2085 return 3; /* fsave */
2086 if (mnemonic[2] == 't')
2087 {
2088 switch (mnemonic[3])
2089 {
2090 case 'c': /* fstcw */
2091 case 'd': /* fstdw */
2092 case 'e': /* fstenv */
2093 case 's': /* fsts[gw] */
2094 return 3;
2095 }
2096 }
2097 break;
2098 case 'x':
2099 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2100 return 0; /* fxsave/fxrstor are not really math ops */
2101 break;
2102 }
252b5132 2103
9306ca4a 2104 return 1;
252b5132
RH		 2105}
2106
2107/* This is the guts of the machine-dependent assembler. LINE points to a
2108 machine dependent instruction. This function is supposed to emit
2109 the frags/bytes it assembles to. */
2110
2111void
2112md_assemble (line)
2113 char *line;
2114{
40fb9820 2115 unsigned int j;
252b5132
RH		 2116 char mnemonic[MAX_MNEM_SIZE];
2117
47926f60 2118 /* Initialize globals. */
252b5132
RH		 2119 memset (&i, '\0', sizeof (i));
2120 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2121 i.reloc[j] = NO_RELOC;
252b5132
RH		 2122 memset (disp_expressions, '\0', sizeof (disp_expressions));
2123 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2124 save_stack_p = save_stack;
252b5132
RH		 2125
2126 /* First parse an instruction mnemonic & call i386_operand for the operands.
2127 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2128 start of a (possibly prefixed) mnemonic. */
252b5132 2129
29b0f896
AM		 2130 line = parse_insn (line, mnemonic);
2131 if (line == NULL)
2132 return;
252b5132 2133
29b0f896
AM		 2134 line = parse_operands (line, mnemonic);
2135 if (line == NULL)
2136 return;
252b5132 2137
29b0f896
AM		 2138 /* Now we've parsed the mnemonic into a set of templates, and have the
2139 operands at hand. */
2140
2141 /* All intel opcodes have reversed operands except for "bound" and
2142 "enter". We also don't reverse intersegment "jmp" and "call"
2143 instructions with 2 immediate operands so that the immediate segment
050dfa73 2144 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2145 if (intel_syntax
2146 && i.operands > 1
29b0f896 2147 && (strcmp (mnemonic, "bound") != 0)
30123838 2148 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2149 && !(operand_type_check (i.types[0], imm)
2150 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2151 swap_operands ();
2152
ec56d5c0
JB		 2153 /* The order of the immediates should be reversed
2154 for 2 immediates extrq and insertq instructions */
2155 if (i.imm_operands == 2
2156 && (strcmp (mnemonic, "extrq") == 0
2157 || strcmp (mnemonic, "insertq") == 0))
2158 swap_2_operands (0, 1);
2159
29b0f896
AM		 2160 if (i.imm_operands)
2161 optimize_imm ();
2162
b300c311
L		 2163 /* Don't optimize displacement for movabs since it only takes 64bit
2164 displacement. */
2165 if (i.disp_operands
2166 && (flag_code != CODE_64BIT
2167 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2168 optimize_disp ();
2169
2170 /* Next, we find a template that matches the given insn,
2171 making sure the overlap of the given operands types is consistent
2172 with the template operand types. */
252b5132 2173
29b0f896
AM		 2174 if (!match_template ())
2175 return;
252b5132 2176
cd61ebfe
AM		 2177 if (intel_syntax)
2178 {
cd61ebfe
AM		 2179 /* Zap movzx and movsx suffix. The suffix may have been set from
2180 "word ptr" or "byte ptr" on the source operand, but we'll use
2181 the suffix later to choose the destination register. */
2182 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2183 {
2184 if (i.reg_operands < 2
2185 && !i.suffix
40fb9820
L		 2186 && (!i.tm.opcode_modifier.no_bsuf
2187 || !i.tm.opcode_modifier.no_wsuf
2188 || !i.tm.opcode_modifier.no_lsuf
2189 || !i.tm.opcode_modifier.no_ssuf
7ce189b3 2190 || !i.tm.opcode_modifier.no_ldsuf
40fb9820 2191 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2192 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2193
2194 i.suffix = 0;
2195 }
cd61ebfe 2196 }
24eab124 2197
40fb9820 2198 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2199 if (!add_prefix (FWAIT_OPCODE))
2200 return;
252b5132 2201
29b0f896 2202 /* Check string instruction segment overrides. */
40fb9820 2203 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2204 {
2205 if (!check_string ())
5dd0794d 2206 return;
29b0f896 2207 }
5dd0794d 2208
29b0f896
AM		 2209 if (!process_suffix ())
2210 return;
e413e4e9 2211
29b0f896
AM		 2212 /* Make still unresolved immediate matches conform to size of immediate
2213 given in i.suffix. */
2214 if (!finalize_imm ())
2215 return;
252b5132 2216
40fb9820 2217 if (i.types[0].bitfield.imm1)
29b0f896 2218 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2219
40fb9820 2220 for (j = 0; j < 3; j++)
c6fb90c8
L		 2221 if (i.types[j].bitfield.inoutportreg
2222 || i.types[j].bitfield.shiftcount
2223 || i.types[j].bitfield.acc
2224 || i.types[j].bitfield.floatacc)
40fb9820
L		 2225 i.reg_operands--;
2226
2227 if (i.tm.opcode_modifier.immext)
29b0f896 2228 {
02fc3089
L		 2229 expressionS *exp;
2230
40fb9820 2231 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2232 {
b7d9ef37 2233 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2234 operands with an opcode suffix which is coded in the same
2235 place as an 8-bit immediate field would be. Here we check
2236 those operands and remove them afterwards. */
2237 unsigned int x;
2238
a4622f40 2239 for (x = 0; x < i.operands; x++)
ca164297 2240 if (i.op[x].regs->reg_num != x)
a540244d
L		 2241 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2242 register_prefix,
2243 i.op[x].regs->reg_name,
2244 x + 1,
2245 i.tm.name);
ca164297
L		 2246 i.operands = 0;
2247 }
2248
29b0f896
AM		 2249 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2250 opcode suffix which is coded in the same place as an 8-bit
2251 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2252 operand from the opcode suffix stored in tm.extension_opcode.
2253 SSE5 also uses this encoding, for some of its 3 argument
2254 instructions. */
252b5132 2255
85f10a01
MM		 2256 assert (i.imm_operands == 0
2257 && (i.operands <= 2
2258 || (i.tm.cpu_flags.bitfield.cpusse5
2259 && i.operands <= 3)));
252b5132 2260
29b0f896
AM		 2261 exp = &im_expressions[i.imm_operands++];
2262 i.op[i.operands].imms = exp;
c6fb90c8 2263 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2264 i.types[i.operands].bitfield.imm8 = 1;
2265 i.operands++;
29b0f896
AM		 2266 exp->X_op = O_constant;
2267 exp->X_add_number = i.tm.extension_opcode;
2268 i.tm.extension_opcode = None;
2269 }
252b5132 2270
29b0f896
AM		 2271 /* For insns with operands there are more diddles to do to the opcode. */
2272 if (i.operands)
2273 {
2274 if (!process_operands ())
2275 return;
2276 }
40fb9820 2277 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2278 {
2279 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2280 as_warn (_("translating to `%sp'"), i.tm.name);
2281 }
252b5132 2282
29b0f896
AM		 2283 /* Handle conversion of 'int $3' --> special int3 insn. */
2284 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2285 {
2286 i.tm.base_opcode = INT3_OPCODE;
2287 i.imm_operands = 0;
2288 }
252b5132 2289
40fb9820
L		 2290 if ((i.tm.opcode_modifier.jump
2291 || i.tm.opcode_modifier.jumpbyte
2292 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2293 && i.op[0].disps->X_op == O_constant)
2294 {
2295 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2296 the absolute address given by the constant. Since ix86 jumps and
2297 calls are pc relative, we need to generate a reloc. */
2298 i.op[0].disps->X_add_symbol = &abs_symbol;
2299 i.op[0].disps->X_op = O_symbol;
2300 }
252b5132 2301
40fb9820 2302 if (i.tm.opcode_modifier.rex64)
161a04f6 2303 i.rex |= REX_W;
252b5132 2304
29b0f896
AM		 2305 /* For 8 bit registers we need an empty rex prefix. Also if the
2306 instruction already has a prefix, we need to convert old
2307 registers to new ones. */
773f551c 2308
40fb9820 2309 if ((i.types[0].bitfield.reg8
29b0f896 2310 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2311 || (i.types[1].bitfield.reg8
29b0f896 2312 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2313 || ((i.types[0].bitfield.reg8
2314 || i.types[1].bitfield.reg8)
29b0f896
AM		 2315 && i.rex != 0))
2316 {
2317 int x;
726c5dcd 2318
29b0f896
AM		 2319 i.rex |= REX_OPCODE;
2320 for (x = 0; x < 2; x++)
2321 {
2322 /* Look for 8 bit operand that uses old registers. */
40fb9820 2323 if (i.types[x].bitfield.reg8
29b0f896 2324 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2325 {
29b0f896
AM		 2326 /* In case it is "hi" register, give up. */
2327 if (i.op[x].regs->reg_num > 3)
a540244d 2328 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2329 "instruction requiring REX prefix."),
a540244d 2330 register_prefix, i.op[x].regs->reg_name);
773f551c 2331
29b0f896
AM		 2332 /* Otherwise it is equivalent to the extended register.
2333 Since the encoding doesn't change this is merely
2334 cosmetic cleanup for debug output. */
2335
2336 i.op[x].regs = i.op[x].regs + 8;
773f551c 2337 }
29b0f896
AM		 2338 }
2339 }
773f551c 2340
85f10a01
MM		 2341 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2342 REX prefix. */
2343 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2344 {
2345 i.drex.rex = i.rex;
2346 i.rex = 0;
2347 }
2348 else if (i.rex != 0)
29b0f896
AM		 2349 add_prefix (REX_OPCODE | i.rex);
2350
2351 /* We are ready to output the insn. */
2352 output_insn ();
2353}
2354
2355static char *
e3bb37b5 2356parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2357{
2358 char *l = line;
2359 char *token_start = l;
2360 char *mnem_p;
5c6af06e
JB		 2361 int supported;
2362 const template *t;
29b0f896
AM		 2363
2364 /* Non-zero if we found a prefix only acceptable with string insns. */
2365 const char *expecting_string_instruction = NULL;
45288df1 2366
29b0f896
AM		 2367 while (1)
2368 {
2369 mnem_p = mnemonic;
2370 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2371 {
2372 mnem_p++;
2373 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2374 {
29b0f896
AM		 2375 as_bad (_("no such instruction: `%s'"), token_start);
2376 return NULL;
2377 }
2378 l++;
2379 }
2380 if (!is_space_char (*l)
2381 && *l != END_OF_INSN
e44823cf
JB		 2382 && (intel_syntax
2383 || (*l != PREFIX_SEPARATOR
2384 && *l != ',')))
29b0f896
AM		 2385 {
2386 as_bad (_("invalid character %s in mnemonic"),
2387 output_invalid (*l));
2388 return NULL;
2389 }
2390 if (token_start == l)
2391 {
e44823cf 2392 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2393 as_bad (_("expecting prefix; got nothing"));
2394 else
2395 as_bad (_("expecting mnemonic; got nothing"));
2396 return NULL;
2397 }
45288df1 2398
29b0f896
AM		 2399 /* Look up instruction (or prefix) via hash table. */
2400 current_templates = hash_find (op_hash, mnemonic);
47926f60 2401
29b0f896
AM		 2402 if (*l != END_OF_INSN
2403 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2404 && current_templates
40fb9820 2405 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2406 {
c6fb90c8 2407 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2408 {
2409 as_bad ((flag_code != CODE_64BIT
2410 ? _("`%s' is only supported in 64-bit mode")
2411 : _("`%s' is not supported in 64-bit mode")),
2412 current_templates->start->name);
2413 return NULL;
2414 }
29b0f896
AM		 2415 /* If we are in 16-bit mode, do not allow addr16 or data16.
2416 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2417 if ((current_templates->start->opcode_modifier.size16
2418 || current_templates->start->opcode_modifier.size32)
29b0f896 2419 && flag_code != CODE_64BIT
40fb9820 2420 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2421 ^ (flag_code == CODE_16BIT)))
2422 {
2423 as_bad (_("redundant %s prefix"),
2424 current_templates->start->name);
2425 return NULL;
45288df1 2426 }
29b0f896
AM		 2427 /* Add prefix, checking for repeated prefixes. */
2428 switch (add_prefix (current_templates->start->base_opcode))
2429 {
2430 case 0:
2431 return NULL;
2432 case 2:
2433 expecting_string_instruction = current_templates->start->name;
2434 break;
2435 }
2436 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2437 token_start = ++l;
2438 }
2439 else
2440 break;
2441 }
45288df1 2442
29b0f896
AM		 2443 if (!current_templates)
2444 {
2445 /* See if we can get a match by trimming off a suffix. */
2446 switch (mnem_p[-1])
2447 {
2448 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2449 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2450 i.suffix = SHORT_MNEM_SUFFIX;
2451 else
29b0f896
AM		 2452 case BYTE_MNEM_SUFFIX:
2453 case QWORD_MNEM_SUFFIX:
2454 i.suffix = mnem_p[-1];
2455 mnem_p[-1] = '\0';
2456 current_templates = hash_find (op_hash, mnemonic);
2457 break;
2458 case SHORT_MNEM_SUFFIX:
2459 case LONG_MNEM_SUFFIX:
2460 if (!intel_syntax)
2461 {
2462 i.suffix = mnem_p[-1];
2463 mnem_p[-1] = '\0';
2464 current_templates = hash_find (op_hash, mnemonic);
2465 }
2466 break;
252b5132 2467
29b0f896
AM		 2468 /* Intel Syntax. */
2469 case 'd':
2470 if (intel_syntax)
2471 {
9306ca4a 2472 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2473 i.suffix = SHORT_MNEM_SUFFIX;
2474 else
2475 i.suffix = LONG_MNEM_SUFFIX;
2476 mnem_p[-1] = '\0';
2477 current_templates = hash_find (op_hash, mnemonic);
2478 }
2479 break;
2480 }
2481 if (!current_templates)
2482 {
2483 as_bad (_("no such instruction: `%s'"), token_start);
2484 return NULL;
2485 }
2486 }
252b5132 2487
40fb9820
L		 2488 if (current_templates->start->opcode_modifier.jump
2489 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2490 {
2491 /* Check for a branch hint. We allow ",pt" and ",pn" for
2492 predict taken and predict not taken respectively.
2493 I'm not sure that branch hints actually do anything on loop
2494 and jcxz insns (JumpByte) for current Pentium4 chips. They
2495 may work in the future and it doesn't hurt to accept them
2496 now. */
2497 if (l[0] == ',' && l[1] == 'p')
2498 {
2499 if (l[2] == 't')
2500 {
2501 if (!add_prefix (DS_PREFIX_OPCODE))
2502 return NULL;
2503 l += 3;
2504 }
2505 else if (l[2] == 'n')
2506 {
2507 if (!add_prefix (CS_PREFIX_OPCODE))
2508 return NULL;
2509 l += 3;
2510 }
2511 }
2512 }
2513 /* Any other comma loses. */
2514 if (*l == ',')
2515 {
2516 as_bad (_("invalid character %s in mnemonic"),
2517 output_invalid (*l));
2518 return NULL;
2519 }
252b5132 2520
29b0f896 2521 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2522 supported = 0;
2523 for (t = current_templates->start; t < current_templates->end; ++t)
2524 {
3629bb00
L		 2525 supported |= cpu_flags_match (t->cpu_flags);
2526 if (supported == 3)
2527 goto skip;
5c6af06e 2528 }
3629bb00 2529
5c6af06e
JB		 2530 if (!(supported & 2))
2531 {
2532 as_bad (flag_code == CODE_64BIT
2533 ? _("`%s' is not supported in 64-bit mode")
2534 : _("`%s' is only supported in 64-bit mode"),
2535 current_templates->start->name);
2536 return NULL;
2537 }
2538 if (!(supported & 1))
29b0f896 2539 {
3629bb00
L		 2540 as_bad (_("`%s' is not supported on `%s%s'"),
2541 current_templates->start->name, cpu_arch_name,
2542 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2543 return NULL;
29b0f896 2544 }
3629bb00
L		 2545
2546skip:
2547 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2548 && (flag_code != CODE_16BIT))
29b0f896
AM		 2549 {
2550 as_warn (_("use .code16 to ensure correct addressing mode"));
2551 }
252b5132 2552
29b0f896 2553 /* Check for rep/repne without a string instruction. */
f41bbced 2554 if (expecting_string_instruction)
29b0f896 2555 {
f41bbced
JB		 2556 static templates override;
2557
2558 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2559 if (t->opcode_modifier.isstring)
f41bbced
JB		 2560 break;
2561 if (t >= current_templates->end)
2562 {
2563 as_bad (_("expecting string instruction after `%s'"),
64e74474 2564 expecting_string_instruction);
f41bbced
JB		 2565 return NULL;
2566 }
2567 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2568 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2569 break;
2570 override.end = t;
2571 current_templates = &override;
29b0f896 2572 }
252b5132 2573
29b0f896
AM		 2574 return l;
2575}
252b5132 2576
29b0f896 2577static char *
e3bb37b5 2578parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2579{
2580 char *token_start;
3138f287 2581
29b0f896
AM		 2582 /* 1 if operand is pending after ','. */
2583 unsigned int expecting_operand = 0;
252b5132 2584
29b0f896
AM		 2585 /* Non-zero if operand parens not balanced. */
2586 unsigned int paren_not_balanced;
2587
2588 while (*l != END_OF_INSN)
2589 {
2590 /* Skip optional white space before operand. */
2591 if (is_space_char (*l))
2592 ++l;
2593 if (!is_operand_char (*l) && *l != END_OF_INSN)
2594 {
2595 as_bad (_("invalid character %s before operand %d"),
2596 output_invalid (*l),
2597 i.operands + 1);
2598 return NULL;
2599 }
2600 token_start = l; /* after white space */
2601 paren_not_balanced = 0;
2602 while (paren_not_balanced || *l != ',')
2603 {
2604 if (*l == END_OF_INSN)
2605 {
2606 if (paren_not_balanced)
2607 {
2608 if (!intel_syntax)
2609 as_bad (_("unbalanced parenthesis in operand %d."),
2610 i.operands + 1);
2611 else
2612 as_bad (_("unbalanced brackets in operand %d."),
2613 i.operands + 1);
2614 return NULL;
2615 }
2616 else
2617 break; /* we are done */
2618 }
2619 else if (!is_operand_char (*l) && !is_space_char (*l))
2620 {
2621 as_bad (_("invalid character %s in operand %d"),
2622 output_invalid (*l),
2623 i.operands + 1);
2624 return NULL;
2625 }
2626 if (!intel_syntax)
2627 {
2628 if (*l == '(')
2629 ++paren_not_balanced;
2630 if (*l == ')')
2631 --paren_not_balanced;
2632 }
2633 else
2634 {
2635 if (*l == '[')
2636 ++paren_not_balanced;
2637 if (*l == ']')
2638 --paren_not_balanced;
2639 }
2640 l++;
2641 }
2642 if (l != token_start)
2643 { /* Yes, we've read in another operand. */
2644 unsigned int operand_ok;
2645 this_operand = i.operands++;
7d5e4556 2646 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2647 if (i.operands > MAX_OPERANDS)
2648 {
2649 as_bad (_("spurious operands; (%d operands/instruction max)"),
2650 MAX_OPERANDS);
2651 return NULL;
2652 }
2653 /* Now parse operand adding info to 'i' as we go along. */
2654 END_STRING_AND_SAVE (l);
2655
2656 if (intel_syntax)
2657 operand_ok =
2658 i386_intel_operand (token_start,
2659 intel_float_operand (mnemonic));
2660 else
a7619375 2661 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2662
2663 RESTORE_END_STRING (l);
2664 if (!operand_ok)
2665 return NULL;
2666 }
2667 else
2668 {
2669 if (expecting_operand)
2670 {
2671 expecting_operand_after_comma:
2672 as_bad (_("expecting operand after ','; got nothing"));
2673 return NULL;
2674 }
2675 if (*l == ',')
2676 {
2677 as_bad (_("expecting operand before ','; got nothing"));
2678 return NULL;
2679 }
2680 }
7f3f1ea2 2681
29b0f896
AM		 2682 /* Now *l must be either ',' or END_OF_INSN. */
2683 if (*l == ',')
2684 {
2685 if (*++l == END_OF_INSN)
2686 {
2687 /* Just skip it, if it's \n complain. */
2688 goto expecting_operand_after_comma;
2689 }
2690 expecting_operand = 1;
2691 }
2692 }
2693 return l;
2694}
7f3f1ea2 2695
050dfa73 2696static void
4d456e3d 2697swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2698{
2699 union i386_op temp_op;
40fb9820 2700 i386_operand_type temp_type;
050dfa73 2701 enum bfd_reloc_code_real temp_reloc;
4eed87de 2702
050dfa73
MM		 2703 temp_type = i.types[xchg2];
2704 i.types[xchg2] = i.types[xchg1];
2705 i.types[xchg1] = temp_type;
2706 temp_op = i.op[xchg2];
2707 i.op[xchg2] = i.op[xchg1];
2708 i.op[xchg1] = temp_op;
2709 temp_reloc = i.reloc[xchg2];
2710 i.reloc[xchg2] = i.reloc[xchg1];
2711 i.reloc[xchg1] = temp_reloc;
2712}
2713
29b0f896 2714static void
e3bb37b5 2715swap_operands (void)
29b0f896 2716{
b7c61d9a 2717 switch (i.operands)
050dfa73 2718 {
b7c61d9a 2719 case 4:
4d456e3d 2720 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2721 case 3:
2722 case 2:
4d456e3d 2723 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2724 break;
2725 default:
2726 abort ();
29b0f896 2727 }
29b0f896
AM		 2728
2729 if (i.mem_operands == 2)
2730 {
2731 const seg_entry *temp_seg;
2732 temp_seg = i.seg[0];
2733 i.seg[0] = i.seg[1];
2734 i.seg[1] = temp_seg;
2735 }
2736}
252b5132 2737
29b0f896
AM		 2738/* Try to ensure constant immediates are represented in the smallest
2739 opcode possible. */
2740static void
e3bb37b5 2741optimize_imm (void)
29b0f896
AM		 2742{
2743 char guess_suffix = 0;
2744 int op;
252b5132 2745
29b0f896
AM		 2746 if (i.suffix)
2747 guess_suffix = i.suffix;
2748 else if (i.reg_operands)
2749 {
2750 /* Figure out a suffix from the last register operand specified.
2751 We can't do this properly yet, ie. excluding InOutPortReg,
2752 but the following works for instructions with immediates.
2753 In any case, we can't set i.suffix yet. */
2754 for (op = i.operands; --op >= 0;)
40fb9820
L		 2755 if (i.types[op].bitfield.reg8)
2756 {
2757 guess_suffix = BYTE_MNEM_SUFFIX;
2758 break;
2759 }
2760 else if (i.types[op].bitfield.reg16)
252b5132 2761 {
40fb9820
L		 2762 guess_suffix = WORD_MNEM_SUFFIX;
2763 break;
2764 }
2765 else if (i.types[op].bitfield.reg32)
2766 {
2767 guess_suffix = LONG_MNEM_SUFFIX;
2768 break;
2769 }
2770 else if (i.types[op].bitfield.reg64)
2771 {
2772 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2773 break;
252b5132 2774 }
29b0f896
AM		 2775 }
2776 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2777 guess_suffix = WORD_MNEM_SUFFIX;
2778
2779 for (op = i.operands; --op >= 0;)
40fb9820 2780 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2781 {
2782 switch (i.op[op].imms->X_op)
252b5132 2783 {
29b0f896
AM		 2784 case O_constant:
2785 /* If a suffix is given, this operand may be shortened. */
2786 switch (guess_suffix)
252b5132 2787 {
29b0f896 2788 case LONG_MNEM_SUFFIX:
40fb9820
L		 2789 i.types[op].bitfield.imm32 = 1;
2790 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2791 break;
2792 case WORD_MNEM_SUFFIX:
40fb9820
L		 2793 i.types[op].bitfield.imm16 = 1;
2794 i.types[op].bitfield.imm32 = 1;
2795 i.types[op].bitfield.imm32s = 1;
2796 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2797 break;
2798 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2799 i.types[op].bitfield.imm8 = 1;
2800 i.types[op].bitfield.imm8s = 1;
2801 i.types[op].bitfield.imm16 = 1;
2802 i.types[op].bitfield.imm32 = 1;
2803 i.types[op].bitfield.imm32s = 1;
2804 i.types[op].bitfield.imm64 = 1;
29b0f896 2805 break;
252b5132 2806 }
252b5132 2807
29b0f896
AM		 2808 /* If this operand is at most 16 bits, convert it
2809 to a signed 16 bit number before trying to see
2810 whether it will fit in an even smaller size.
2811 This allows a 16-bit operand such as $0xffe0 to
2812 be recognised as within Imm8S range. */
40fb9820 2813 if ((i.types[op].bitfield.imm16)
29b0f896 2814 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2815 {
29b0f896
AM		 2816 i.op[op].imms->X_add_number =
2817 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2818 }
40fb9820 2819 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2820 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2821 == 0))
2822 {
2823 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2824 ^ ((offsetT) 1 << 31))
2825 - ((offsetT) 1 << 31));
2826 }
40fb9820 2827 i.types[op]
c6fb90c8
L		 2828 = operand_type_or (i.types[op],
2829 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2830
29b0f896
AM		 2831 /* We must avoid matching of Imm32 templates when 64bit
2832 only immediate is available. */
2833 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2834 i.types[op].bitfield.imm32 = 0;
29b0f896 2835 break;
252b5132 2836
29b0f896
AM		 2837 case O_absent:
2838 case O_register:
2839 abort ();
2840
2841 /* Symbols and expressions. */
2842 default:
9cd96992
JB		 2843 /* Convert symbolic operand to proper sizes for matching, but don't
2844 prevent matching a set of insns that only supports sizes other
2845 than those matching the insn suffix. */
2846 {
40fb9820 2847 i386_operand_type mask, allowed;
9cd96992
JB		 2848 const template *t;
2849
c6fb90c8
L		 2850 UINTS_CLEAR (mask);
2851 UINTS_CLEAR (allowed);
40fb9820 2852
4eed87de
AM		 2853 for (t = current_templates->start;
2854 t < current_templates->end;
2855 ++t)
c6fb90c8
L		 2856 allowed = operand_type_or (allowed,
2857 t->operand_types[op]);
9cd96992
JB		 2858 switch (guess_suffix)
2859 {
2860 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2861 mask.bitfield.imm64 = 1;
2862 mask.bitfield.imm32s = 1;
9cd96992
JB		 2863 break;
2864 case LONG_MNEM_SUFFIX:
40fb9820 2865 mask.bitfield.imm32 = 1;
9cd96992
JB		 2866 break;
2867 case WORD_MNEM_SUFFIX:
40fb9820 2868 mask.bitfield.imm16 = 1;
9cd96992
JB		 2869 break;
2870 case BYTE_MNEM_SUFFIX:
40fb9820 2871 mask.bitfield.imm8 = 1;
9cd96992
JB		 2872 break;
2873 default:
9cd96992
JB		 2874 break;
2875 }
c6fb90c8
L		 2876 allowed = operand_type_and (mask, allowed);
2877 if (!UINTS_ALL_ZERO (allowed))
2878 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2879 }
29b0f896 2880 break;
252b5132 2881 }
29b0f896
AM		 2882 }
2883}
47926f60 2884
29b0f896
AM		 2885/* Try to use the smallest displacement type too. */
2886static void
e3bb37b5 2887optimize_disp (void)
29b0f896
AM		 2888{
2889 int op;
3e73aa7c 2890
29b0f896 2891 for (op = i.operands; --op >= 0;)
40fb9820 2892 if (operand_type_check (i.types[op], disp))
252b5132 2893 {
b300c311 2894 if (i.op[op].disps->X_op == O_constant)
252b5132 2895 {
b300c311 2896 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2897
40fb9820 2898 if (i.types[op].bitfield.disp16
b300c311
L		 2899 && (disp & ~(offsetT) 0xffff) == 0)
2900 {
2901 /* If this operand is at most 16 bits, convert
2902 to a signed 16 bit number and don't use 64bit
2903 displacement. */
2904 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2905 i.types[op].bitfield.disp64 = 0;
b300c311 2906 }
40fb9820 2907 if (i.types[op].bitfield.disp32
b300c311
L		 2908 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2909 {
2910 /* If this operand is at most 32 bits, convert
2911 to a signed 32 bit number and don't use 64bit
2912 displacement. */
2913 disp &= (((offsetT) 2 << 31) - 1);
2914 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2915 i.types[op].bitfield.disp64 = 0;
b300c311 2916 }
40fb9820 2917 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2918 {
40fb9820
L		 2919 i.types[op].bitfield.disp8 = 0;
2920 i.types[op].bitfield.disp16 = 0;
2921 i.types[op].bitfield.disp32 = 0;
2922 i.types[op].bitfield.disp32s = 0;
2923 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2924 i.op[op].disps = 0;
2925 i.disp_operands--;
2926 }
2927 else if (flag_code == CODE_64BIT)
2928 {
2929 if (fits_in_signed_long (disp))
28a9d8f5 2930 {
40fb9820
L		 2931 i.types[op].bitfield.disp64 = 0;
2932 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2933 }
b300c311 2934 if (fits_in_unsigned_long (disp))
40fb9820 2935 i.types[op].bitfield.disp32 = 1;
b300c311 2936 }
40fb9820
L		 2937 if ((i.types[op].bitfield.disp32
2938 || i.types[op].bitfield.disp32s
2939 || i.types[op].bitfield.disp16)
b300c311 2940 && fits_in_signed_byte (disp))
40fb9820 2941 i.types[op].bitfield.disp8 = 1;
252b5132 2942 }
67a4f2b7
AO		 2943 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2944 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2945 {
2946 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2947 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2948 i.types[op].bitfield.disp8 = 0;
2949 i.types[op].bitfield.disp16 = 0;
2950 i.types[op].bitfield.disp32 = 0;
2951 i.types[op].bitfield.disp32s = 0;
2952 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2953 }
2954 else
b300c311 2955 /* We only support 64bit displacement on constants. */
40fb9820 2956 i.types[op].bitfield.disp64 = 0;
252b5132 2957 }
29b0f896
AM		 2958}
2959
2960static int
e3bb37b5 2961match_template (void)
29b0f896
AM		 2962{
2963 /* Points to template once we've found it. */
2964 const template *t;
40fb9820 2965 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2966 unsigned int found_reverse_match;
40fb9820
L		 2967 i386_opcode_modifier suffix_check;
2968 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2969 int addr_prefix_disp;
a5c311ca 2970 unsigned int j;
3629bb00 2971 unsigned int found_cpu_match;
45664ddb 2972 unsigned int check_register;
7d5e4556 2973 unsigned int size_match;
29b0f896 2974
f48ff2ae
L		 2975#if MAX_OPERANDS != 4
2976# error "MAX_OPERANDS must be 4."
2977#endif
2978
29b0f896 2979 found_reverse_match = 0;
539e75ad 2980 addr_prefix_disp = -1;
40fb9820
L		 2981
2982 memset (&suffix_check, 0, sizeof (suffix_check));
2983 if (i.suffix == BYTE_MNEM_SUFFIX)
2984 suffix_check.no_bsuf = 1;
2985 else if (i.suffix == WORD_MNEM_SUFFIX)
2986 suffix_check.no_wsuf = 1;
2987 else if (i.suffix == SHORT_MNEM_SUFFIX)
2988 suffix_check.no_ssuf = 1;
2989 else if (i.suffix == LONG_MNEM_SUFFIX)
2990 suffix_check.no_lsuf = 1;
2991 else if (i.suffix == QWORD_MNEM_SUFFIX)
2992 suffix_check.no_qsuf = 1;
2993 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 2994 suffix_check.no_ldsuf = 1;
29b0f896 2995
45aa61fe 2996 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2997 {
539e75ad
L		 2998 addr_prefix_disp = -1;
2999
29b0f896
AM		 3000 /* Must have right number of operands. */
3001 if (i.operands != t->operands)
3002 continue;
3003
50aecf8c
L		 3004 /* Check processor support. */
3005 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3006 if (!found_cpu_match)
3007 continue;
3008
e1d4d893
L		 3009 /* Check old gcc support. */
3010 if (!old_gcc && t->opcode_modifier.oldgcc)
3011 continue;
3012
3013 /* Check AT&T mnemonic. */
3014 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3015 continue;
3016
e1d4d893
L		 3017 /* Check Intel syntax. */
3018 if (intel_syntax && t->opcode_modifier.attsyntax)
1efbbeb4
L		 3019 continue;
3020
20592a94 3021 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3022 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3023 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3024 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3025 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3026 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3027 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3028 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3029 continue;
3030
7d5e4556 3031 size_match = 1;
a5c311ca 3032 for (j = 0; j < MAX_OPERANDS; j++)
7d5e4556
L		 3033 {
3034 operand_types[j] = t->operand_types[j];
3035
3036 /* Check memory and accumulator operand size. We check
3037 operand_types for accumulator, and both operand_types
3038 and i.types for memory. */
3039 if (j < i.operands
3040 && !operand_types[j].bitfield.anysize
3041 && ((operand_types[j].bitfield.acc
3042 && ((i.types[j].bitfield.byte
3043 && !operand_types[j].bitfield.byte)
3044 || (i.types[j].bitfield.word
3045 && !operand_types[j].bitfield.word)
3046 || (i.types[j].bitfield.dword
3047 && !operand_types[j].bitfield.dword)
3048 || (i.types[j].bitfield.qword
3049 && !operand_types[j].bitfield.qword)))
3050 || (operand_types[j].bitfield.baseindex
3051 && i.types[j].bitfield.baseindex
3052 && ((i.types[j].bitfield.unspecified
3053 && !operand_types[j].bitfield.unspecified)
3054 || (i.types[j].bitfield.byte
3055 && !operand_types[j].bitfield.byte)
3056 || (i.types[j].bitfield.word
3057 && !operand_types[j].bitfield.word)
3058 || (i.types[j].bitfield.dword
3059 && !operand_types[j].bitfield.dword)
3060 || (i.types[j].bitfield.fword
3061 && !operand_types[j].bitfield.fword)
3062 || (i.types[j].bitfield.qword
3063 && !operand_types[j].bitfield.qword)
3064 || (i.types[j].bitfield.tbyte
3065 && !operand_types[j].bitfield.tbyte)
3066 || (i.types[j].bitfield.xmmword
3067 && !operand_types[j].bitfield.xmmword)))))
3068 {
3069 size_match = 0;
3070 break;
3071 }
3072 }
3073
3074 if (!size_match)
3075 continue;
539e75ad 3076
45aa61fe
AM		 3077 /* In general, don't allow 64-bit operands in 32-bit mode. */
3078 if (i.suffix == QWORD_MNEM_SUFFIX
3079 && flag_code != CODE_64BIT
3080 && (intel_syntax
40fb9820 3081 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3082 && !intel_float_operand (t->name))
3083 : intel_float_operand (t->name) != 2)
40fb9820
L		 3084 && ((!operand_types[0].bitfield.regmmx
3085 && !operand_types[0].bitfield.regxmm)
3086 || (!operand_types[t->operands > 1].bitfield.regmmx
3087 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3088 && (t->base_opcode != 0x0fc7
3089 || t->extension_opcode != 1 /* cmpxchg8b */))
3090 continue;
3091
29b0f896 3092 /* Do not verify operands when there are none. */
50aecf8c 3093 else
29b0f896 3094 {
c6fb90c8 3095 if (!t->operands)
2dbab7d5
L		 3096 /* We've found a match; break out of loop. */
3097 break;
29b0f896 3098 }
252b5132 3099
539e75ad
L		 3100 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3101 into Disp32/Disp16/Disp32 operand. */
3102 if (i.prefix[ADDR_PREFIX] != 0)
3103 {
40fb9820 3104 /* There should be only one Disp operand. */
539e75ad
L		 3105 switch (flag_code)
3106 {
3107 case CODE_16BIT:
40fb9820
L		 3108 for (j = 0; j < MAX_OPERANDS; j++)
3109 {
3110 if (operand_types[j].bitfield.disp16)
3111 {
3112 addr_prefix_disp = j;
3113 operand_types[j].bitfield.disp32 = 1;
3114 operand_types[j].bitfield.disp16 = 0;
3115 break;
3116 }
3117 }
539e75ad
L		 3118 break;
3119 case CODE_32BIT:
40fb9820
L		 3120 for (j = 0; j < MAX_OPERANDS; j++)
3121 {
3122 if (operand_types[j].bitfield.disp32)
3123 {
3124 addr_prefix_disp = j;
3125 operand_types[j].bitfield.disp32 = 0;
3126 operand_types[j].bitfield.disp16 = 1;
3127 break;
3128 }
3129 }
539e75ad
L		 3130 break;
3131 case CODE_64BIT:
40fb9820
L		 3132 for (j = 0; j < MAX_OPERANDS; j++)
3133 {
3134 if (operand_types[j].bitfield.disp64)
3135 {
3136 addr_prefix_disp = j;
3137 operand_types[j].bitfield.disp64 = 0;
3138 operand_types[j].bitfield.disp32 = 1;
3139 break;
3140 }
3141 }
539e75ad
L		 3142 break;
3143 }
539e75ad
L		 3144 }
3145
45664ddb
L		 3146 /* We check register size only if size of operands can be
3147 encoded the canonical way. */
3148 check_register = t->opcode_modifier.w;
c6fb90c8 3149 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3150 switch (t->operands)
3151 {
3152 case 1:
40fb9820 3153 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3154 continue;
3155 break;
3156 case 2:
8b38ad71
L		 3157 /* xchg %eax, %eax is a special case. It is an aliase for nop
3158 only in 32bit mode and we can use opcode 0x90. In 64bit
3159 mode, we can't use 0x90 for xchg %eax, %eax since it should
3160 zero-extend %eax to %rax. */
3161 if (flag_code == CODE_64BIT
3162 && t->base_opcode == 0x90
c6fb90c8
L		 3163 && UINTS_EQUAL (i.types [0], acc32)
3164 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3165 continue;
29b0f896 3166 case 3:
f48ff2ae 3167 case 4:
c6fb90c8 3168 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3169 if (!operand_type_match (overlap0, i.types[0])
3170 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3171 || (check_register
3172 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3173 operand_types[0],
3174 overlap1, i.types[1],
3175 operand_types[1])))
29b0f896
AM		 3176 {
3177 /* Check if other direction is valid ... */
40fb9820 3178 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3179 continue;
3180
3181 /* Try reversing direction of operands. */
c6fb90c8
L		 3182 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3183 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3184 if (!operand_type_match (overlap0, i.types[0])
3185 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3186 || (check_register
3187 && !operand_type_register_match (overlap0,
3188 i.types[0],
3189 operand_types[1],
3190 overlap1,
3191 i.types[1],
3192 operand_types[0])))
29b0f896
AM		 3193 {
3194 /* Does not match either direction. */
3195 continue;
3196 }
3197 /* found_reverse_match holds which of D or FloatDR
3198 we've found. */
40fb9820 3199 if (t->opcode_modifier.d)
8a2ed489 3200 found_reverse_match = Opcode_D;
40fb9820 3201 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3202 found_reverse_match = Opcode_FloatD;
3203 else
3204 found_reverse_match = 0;
40fb9820 3205 if (t->opcode_modifier.floatr)
8a2ed489 3206 found_reverse_match |= Opcode_FloatR;
29b0f896 3207 }
f48ff2ae 3208 else
29b0f896 3209 {
f48ff2ae 3210 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3211 switch (t->operands)
3212 {
3213 case 4:
c6fb90c8
L		 3214 overlap3 = operand_type_and (i.types[3],
3215 operand_types[3]);
d1cbb4db 3216 case 3:
c6fb90c8
L		 3217 overlap2 = operand_type_and (i.types[2],
3218 operand_types[2]);
d1cbb4db
L		 3219 break;
3220 }
29b0f896 3221
f48ff2ae
L		 3222 switch (t->operands)
3223 {
3224 case 4:
40fb9820 3225 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3226 || (check_register
3227 && !operand_type_register_match (overlap2,
3228 i.types[2],
3229 operand_types[2],
3230 overlap3,
3231 i.types[3],
3232 operand_types[3])))
f48ff2ae
L		 3233 continue;
3234 case 3:
3235 /* Here we make use of the fact that there are no
3236 reverse match 3 operand instructions, and all 3
3237 operand instructions only need to be checked for
3238 register consistency between operands 2 and 3. */
40fb9820 3239 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3240 || (check_register
3241 && !operand_type_register_match (overlap1,
3242 i.types[1],
3243 operand_types[1],
3244 overlap2,
3245 i.types[2],
3246 operand_types[2])))
f48ff2ae
L		 3247 continue;
3248 break;
3249 }
29b0f896 3250 }
f48ff2ae 3251 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3252 slip through to break. */
3253 }
3629bb00 3254 if (!found_cpu_match)
29b0f896
AM		 3255 {
3256 found_reverse_match = 0;
3257 continue;
3258 }
3259 /* We've found a match; break out of loop. */
3260 break;
3261 }
3262
3263 if (t == current_templates->end)
3264 {
3265 /* We found no match. */
3266 as_bad (_("suffix or operands invalid for `%s'"),
3267 current_templates->start->name);
3268 return 0;
3269 }
252b5132 3270
29b0f896
AM		 3271 if (!quiet_warnings)
3272 {
3273 if (!intel_syntax
40fb9820
L		 3274 && (i.types[0].bitfield.jumpabsolute
3275 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3276 {
3277 as_warn (_("indirect %s without `*'"), t->name);
3278 }
3279
40fb9820
L		 3280 if (t->opcode_modifier.isprefix
3281 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3282 {
3283 /* Warn them that a data or address size prefix doesn't
3284 affect assembly of the next line of code. */
3285 as_warn (_("stand-alone `%s' prefix"), t->name);
3286 }
3287 }
3288
3289 /* Copy the template we found. */
3290 i.tm = *t;
539e75ad
L		 3291
3292 if (addr_prefix_disp != -1)
3293 i.tm.operand_types[addr_prefix_disp]
3294 = operand_types[addr_prefix_disp];
3295
29b0f896
AM		 3296 if (found_reverse_match)
3297 {
3298 /* If we found a reverse match we must alter the opcode
3299 direction bit. found_reverse_match holds bits to change
3300 (different for int & float insns). */
3301
3302 i.tm.base_opcode ^= found_reverse_match;
3303
539e75ad
L		 3304 i.tm.operand_types[0] = operand_types[1];
3305 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3306 }
3307
3308 return 1;
3309}
3310
3311static int
e3bb37b5 3312check_string (void)
29b0f896 3313{
40fb9820
L		 3314 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3315 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3316 {
3317 if (i.seg[0] != NULL && i.seg[0] != &es)
3318 {
3319 as_bad (_("`%s' operand %d must use `%%es' segment"),
3320 i.tm.name,
3321 mem_op + 1);
3322 return 0;
3323 }
3324 /* There's only ever one segment override allowed per instruction.
3325 This instruction possibly has a legal segment override on the
3326 second operand, so copy the segment to where non-string
3327 instructions store it, allowing common code. */
3328 i.seg[0] = i.seg[1];
3329 }
40fb9820 3330 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3331 {
3332 if (i.seg[1] != NULL && i.seg[1] != &es)
3333 {
3334 as_bad (_("`%s' operand %d must use `%%es' segment"),
3335 i.tm.name,
3336 mem_op + 2);
3337 return 0;
3338 }
3339 }
3340 return 1;
3341}
3342
3343static int
543613e9 3344process_suffix (void)
29b0f896
AM		 3345{
3346 /* If matched instruction specifies an explicit instruction mnemonic
3347 suffix, use it. */
40fb9820
L		 3348 if (i.tm.opcode_modifier.size16)
3349 i.suffix = WORD_MNEM_SUFFIX;
3350 else if (i.tm.opcode_modifier.size32)
3351 i.suffix = LONG_MNEM_SUFFIX;
3352 else if (i.tm.opcode_modifier.size64)
3353 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3354 else if (i.reg_operands)
3355 {
3356 /* If there's no instruction mnemonic suffix we try to invent one
3357 based on register operands. */
3358 if (!i.suffix)
3359 {
3360 /* We take i.suffix from the last register operand specified,
3361 Destination register type is more significant than source
381d071f
L		 3362 register type. crc32 in SSE4.2 prefers source register
3363 type. */
3364 if (i.tm.base_opcode == 0xf20f38f1)
3365 {
40fb9820
L		 3366 if (i.types[0].bitfield.reg16)
3367 i.suffix = WORD_MNEM_SUFFIX;
3368 else if (i.types[0].bitfield.reg32)
3369 i.suffix = LONG_MNEM_SUFFIX;
3370 else if (i.types[0].bitfield.reg64)
3371 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3372 }
9344ff29 3373 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3374 {
40fb9820 3375 if (i.types[0].bitfield.reg8)
20592a94
L		 3376 i.suffix = BYTE_MNEM_SUFFIX;
3377 }
381d071f
L		 3378
3379 if (!i.suffix)
3380 {
3381 int op;
3382
20592a94
L		 3383 if (i.tm.base_opcode == 0xf20f38f1
3384 || i.tm.base_opcode == 0xf20f38f0)
3385 {
3386 /* We have to know the operand size for crc32. */
3387 as_bad (_("ambiguous memory operand size for `%s`"),
3388 i.tm.name);
3389 return 0;
3390 }
3391
381d071f 3392 for (op = i.operands; --op >= 0;)
40fb9820 3393 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3394 {
40fb9820
L		 3395 if (i.types[op].bitfield.reg8)
3396 {
3397 i.suffix = BYTE_MNEM_SUFFIX;
3398 break;
3399 }
3400 else if (i.types[op].bitfield.reg16)
3401 {
3402 i.suffix = WORD_MNEM_SUFFIX;
3403 break;
3404 }
3405 else if (i.types[op].bitfield.reg32)
3406 {
3407 i.suffix = LONG_MNEM_SUFFIX;
3408 break;
3409 }
3410 else if (i.types[op].bitfield.reg64)
3411 {
3412 i.suffix = QWORD_MNEM_SUFFIX;
3413 break;
3414 }
381d071f
L		 3415 }
3416 }
29b0f896
AM		 3417 }
3418 else if (i.suffix == BYTE_MNEM_SUFFIX)
3419 {
3420 if (!check_byte_reg ())
3421 return 0;
3422 }
3423 else if (i.suffix == LONG_MNEM_SUFFIX)
3424 {
3425 if (!check_long_reg ())
3426 return 0;
3427 }
3428 else if (i.suffix == QWORD_MNEM_SUFFIX)
3429 {
955e1e6a
L		 3430 if (intel_syntax
3431 && i.tm.opcode_modifier.ignoresize
3432 && i.tm.opcode_modifier.no_qsuf)
3433 i.suffix = 0;
3434 else if (!check_qword_reg ())
29b0f896
AM		 3435 return 0;
3436 }
3437 else if (i.suffix == WORD_MNEM_SUFFIX)
3438 {
3439 if (!check_word_reg ())
3440 return 0;
3441 }
582d5edd
L		 3442 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3443 {
3444 /* Skip if the instruction has x suffix. match_template
3445 should check if it is a valid suffix. */
3446 }
40fb9820 3447 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3448 /* Do nothing if the instruction is going to ignore the prefix. */
3449 ;
3450 else
3451 abort ();
3452 }
40fb9820 3453 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3454 && !i.suffix
3455 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3456 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3457 {
3458 i.suffix = stackop_size;
3459 }
9306ca4a
JB		 3460 else if (intel_syntax
3461 && !i.suffix
40fb9820
L		 3462 && (i.tm.operand_types[0].bitfield.jumpabsolute
3463 || i.tm.opcode_modifier.jumpbyte
3464 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3465 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3466 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3467 {
3468 switch (flag_code)
3469 {
3470 case CODE_64BIT:
40fb9820 3471 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3472 {
3473 i.suffix = QWORD_MNEM_SUFFIX;
3474 break;
3475 }
3476 case CODE_32BIT:
40fb9820 3477 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3478 i.suffix = LONG_MNEM_SUFFIX;
3479 break;
3480 case CODE_16BIT:
40fb9820 3481 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3482 i.suffix = WORD_MNEM_SUFFIX;
3483 break;
3484 }
3485 }
252b5132 3486
9306ca4a 3487 if (!i.suffix)
29b0f896 3488 {
9306ca4a
JB		 3489 if (!intel_syntax)
3490 {
40fb9820 3491 if (i.tm.opcode_modifier.w)
9306ca4a 3492 {
4eed87de
AM		 3493 as_bad (_("no instruction mnemonic suffix given and "
3494 "no register operands; can't size instruction"));
9306ca4a
JB		 3495 return 0;
3496 }
3497 }
3498 else
3499 {
40fb9820
L		 3500 unsigned int suffixes;
3501
3502 suffixes = !i.tm.opcode_modifier.no_bsuf;
3503 if (!i.tm.opcode_modifier.no_wsuf)
3504 suffixes |= 1 << 1;
3505 if (!i.tm.opcode_modifier.no_lsuf)
3506 suffixes |= 1 << 2;
fc4adea1 3507 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3508 suffixes |= 1 << 3;
3509 if (!i.tm.opcode_modifier.no_ssuf)
3510 suffixes |= 1 << 4;
3511 if (!i.tm.opcode_modifier.no_qsuf)
3512 suffixes |= 1 << 5;
3513
3514 /* There are more than suffix matches. */
3515 if (i.tm.opcode_modifier.w
9306ca4a 3516 || ((suffixes & (suffixes - 1))
40fb9820
L		 3517 && !i.tm.opcode_modifier.defaultsize
3518 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3519 {
3520 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3521 return 0;
3522 }
3523 }
29b0f896 3524 }
252b5132 3525
9306ca4a
JB		 3526 /* Change the opcode based on the operand size given by i.suffix;
3527 We don't need to change things for byte insns. */
3528
582d5edd
L		 3529 if (i.suffix
3530 && i.suffix != BYTE_MNEM_SUFFIX
3531 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3532 {
3533 /* It's not a byte, select word/dword operation. */
40fb9820 3534 if (i.tm.opcode_modifier.w)
29b0f896 3535 {
40fb9820 3536 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3537 i.tm.base_opcode |= 8;
3538 else
3539 i.tm.base_opcode |= 1;
3540 }
0f3f3d8b 3541
29b0f896
AM		 3542 /* Now select between word & dword operations via the operand
3543 size prefix, except for instructions that will ignore this
3544 prefix anyway. */
ca61edf2 3545 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3546 {
ca61edf2
L		 3547 /* The address size override prefix changes the size of the
3548 first operand. */
40fb9820
L		 3549 if ((flag_code == CODE_32BIT
3550 && i.op->regs[0].reg_type.bitfield.reg16)
3551 || (flag_code != CODE_32BIT
3552 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3553 if (!add_prefix (ADDR_PREFIX_OPCODE))
3554 return 0;
3555 }
3556 else if (i.suffix != QWORD_MNEM_SUFFIX
3557 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3558 && !i.tm.opcode_modifier.ignoresize
3559 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3560 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3561 || (flag_code == CODE_64BIT
40fb9820 3562 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3563 {
3564 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3565
40fb9820 3566 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3567 prefix = ADDR_PREFIX_OPCODE;
252b5132 3568
29b0f896
AM		 3569 if (!add_prefix (prefix))
3570 return 0;
24eab124 3571 }
252b5132 3572
29b0f896
AM		 3573 /* Set mode64 for an operand. */
3574 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3575 && flag_code == CODE_64BIT
40fb9820 3576 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3577 {
3578 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3579 need rex64. cmpxchg8b is also a special case. */
3580 if (! (i.operands == 2
3581 && i.tm.base_opcode == 0x90
3582 && i.tm.extension_opcode == None
c6fb90c8
L		 3583 && UINTS_EQUAL (i.types [0], acc64)
3584 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3585 && ! (i.operands == 1
3586 && i.tm.base_opcode == 0xfc7
3587 && i.tm.extension_opcode == 1
40fb9820
L		 3588 && !operand_type_check (i.types [0], reg)
3589 && operand_type_check (i.types [0], anymem)))
f6bee062 3590 i.rex |= REX_W;
46e883c5 3591 }
3e73aa7c 3592
29b0f896
AM		 3593 /* Size floating point instruction. */
3594 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3595 if (i.tm.opcode_modifier.floatmf)
543613e9 3596 i.tm.base_opcode ^= 4;
29b0f896 3597 }
7ecd2f8b 3598
29b0f896
AM		 3599 return 1;
3600}
3e73aa7c 3601
29b0f896 3602static int
543613e9 3603check_byte_reg (void)
29b0f896
AM		 3604{
3605 int op;
543613e9 3606
29b0f896
AM		 3607 for (op = i.operands; --op >= 0;)
3608 {
3609 /* If this is an eight bit register, it's OK. If it's the 16 or
3610 32 bit version of an eight bit register, we will just use the
3611 low portion, and that's OK too. */
40fb9820 3612 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3613 continue;
3614
ca61edf2
L		 3615 /* Don't generate this warning if not needed. */
3616 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3617 continue;
3618
9344ff29
L		 3619 /* crc32 doesn't generate this warning. */
3620 if (i.tm.base_opcode == 0xf20f38f0)
3621 continue;
3622
40fb9820
L		 3623 if ((i.types[op].bitfield.reg16
3624 || i.types[op].bitfield.reg32
3625 || i.types[op].bitfield.reg64)
3626 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3627 {
3628 /* Prohibit these changes in the 64bit mode, since the
3629 lowering is more complicated. */
3630 if (flag_code == CODE_64BIT
40fb9820 3631 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3632 {
2ca3ace5
L		 3633 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3634 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3635 i.suffix);
3636 return 0;
3637 }
3638#if REGISTER_WARNINGS
3639 if (!quiet_warnings
40fb9820 3640 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3641 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3642 register_prefix,
40fb9820 3643 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3644 ? REGNAM_AL - REGNAM_AX
3645 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3646 register_prefix,
29b0f896
AM		 3647 i.op[op].regs->reg_name,
3648 i.suffix);
3649#endif
3650 continue;
3651 }
3652 /* Any other register is bad. */
40fb9820
L		 3653 if (i.types[op].bitfield.reg16
3654 || i.types[op].bitfield.reg32
3655 || i.types[op].bitfield.reg64
3656 || i.types[op].bitfield.regmmx
3657 || i.types[op].bitfield.regxmm
3658 || i.types[op].bitfield.sreg2
3659 || i.types[op].bitfield.sreg3
3660 || i.types[op].bitfield.control
3661 || i.types[op].bitfield.debug
3662 || i.types[op].bitfield.test
3663 || i.types[op].bitfield.floatreg
3664 || i.types[op].bitfield.floatacc)
29b0f896 3665 {
a540244d
L		 3666 as_bad (_("`%s%s' not allowed with `%s%c'"),
3667 register_prefix,
29b0f896
AM		 3668 i.op[op].regs->reg_name,
3669 i.tm.name,
3670 i.suffix);
3671 return 0;
3672 }
3673 }
3674 return 1;
3675}
3676
3677static int
e3bb37b5 3678check_long_reg (void)
29b0f896
AM		 3679{
3680 int op;
3681
3682 for (op = i.operands; --op >= 0;)
3683 /* Reject eight bit registers, except where the template requires
3684 them. (eg. movzb) */
40fb9820
L		 3685 if (i.types[op].bitfield.reg8
3686 && (i.tm.operand_types[op].bitfield.reg16
3687 || i.tm.operand_types[op].bitfield.reg32
3688 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3689 {
a540244d
L		 3690 as_bad (_("`%s%s' not allowed with `%s%c'"),
3691 register_prefix,
29b0f896
AM		 3692 i.op[op].regs->reg_name,
3693 i.tm.name,
3694 i.suffix);
3695 return 0;
3696 }
3697 /* Warn if the e prefix on a general reg is missing. */
3698 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3699 && i.types[op].bitfield.reg16
3700 && (i.tm.operand_types[op].bitfield.reg32
3701 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3702 {
3703 /* Prohibit these changes in the 64bit mode, since the
3704 lowering is more complicated. */
3705 if (flag_code == CODE_64BIT)
252b5132 3706 {
2ca3ace5
L		 3707 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3708 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3709 i.suffix);
3710 return 0;
252b5132 3711 }
29b0f896
AM		 3712#if REGISTER_WARNINGS
3713 else
a540244d
L		 3714 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3715 register_prefix,
29b0f896 3716 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3717 register_prefix,
29b0f896
AM		 3718 i.op[op].regs->reg_name,
3719 i.suffix);
3720#endif
252b5132 3721 }
29b0f896 3722 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3723 else if (i.types[op].bitfield.reg64
3724 && (i.tm.operand_types[op].bitfield.reg32
3725 || i.tm.operand_types[op].bitfield.acc))
252b5132 3726 {
34828aad 3727 if (intel_syntax
ca61edf2 3728 && i.tm.opcode_modifier.toqword
40fb9820 3729 && !i.types[0].bitfield.regxmm)
34828aad 3730 {
ca61edf2 3731 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3732 i.suffix = QWORD_MNEM_SUFFIX;
3733 }
3734 else
3735 {
3736 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3737 register_prefix, i.op[op].regs->reg_name,
3738 i.suffix);
3739 return 0;
3740 }
29b0f896
AM		 3741 }
3742 return 1;
3743}
252b5132 3744
29b0f896 3745static int
e3bb37b5 3746check_qword_reg (void)
29b0f896
AM		 3747{
3748 int op;
252b5132 3749
29b0f896
AM		 3750 for (op = i.operands; --op >= 0; )
3751 /* Reject eight bit registers, except where the template requires
3752 them. (eg. movzb) */
40fb9820
L		 3753 if (i.types[op].bitfield.reg8
3754 && (i.tm.operand_types[op].bitfield.reg16
3755 || i.tm.operand_types[op].bitfield.reg32
3756 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3757 {
a540244d
L		 3758 as_bad (_("`%s%s' not allowed with `%s%c'"),
3759 register_prefix,
29b0f896
AM		 3760 i.op[op].regs->reg_name,
3761 i.tm.name,
3762 i.suffix);
3763 return 0;
3764 }
3765 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3766 else if ((i.types[op].bitfield.reg16
3767 || i.types[op].bitfield.reg32)
3768 && (i.tm.operand_types[op].bitfield.reg32
3769 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3770 {
3771 /* Prohibit these changes in the 64bit mode, since the
3772 lowering is more complicated. */
34828aad 3773 if (intel_syntax
ca61edf2 3774 && i.tm.opcode_modifier.todword
40fb9820 3775 && !i.types[0].bitfield.regxmm)
34828aad 3776 {
ca61edf2 3777 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3778 i.suffix = LONG_MNEM_SUFFIX;
3779 }
3780 else
3781 {
3782 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3783 register_prefix, i.op[op].regs->reg_name,
3784 i.suffix);
3785 return 0;
3786 }
252b5132 3787 }
29b0f896
AM		 3788 return 1;
3789}
252b5132 3790
29b0f896 3791static int
e3bb37b5 3792check_word_reg (void)
29b0f896
AM		 3793{
3794 int op;
3795 for (op = i.operands; --op >= 0;)
3796 /* Reject eight bit registers, except where the template requires
3797 them. (eg. movzb) */
40fb9820
L		 3798 if (i.types[op].bitfield.reg8
3799 && (i.tm.operand_types[op].bitfield.reg16
3800 || i.tm.operand_types[op].bitfield.reg32
3801 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3802 {
a540244d
L		 3803 as_bad (_("`%s%s' not allowed with `%s%c'"),
3804 register_prefix,
29b0f896
AM		 3805 i.op[op].regs->reg_name,
3806 i.tm.name,
3807 i.suffix);
3808 return 0;
3809 }
3810 /* Warn if the e prefix on a general reg is present. */
3811 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3812 && i.types[op].bitfield.reg32
3813 && (i.tm.operand_types[op].bitfield.reg16
3814 || i.tm.operand_types[op].bitfield.acc))
252b5132 3815 {
29b0f896
AM		 3816 /* Prohibit these changes in the 64bit mode, since the
3817 lowering is more complicated. */
3818 if (flag_code == CODE_64BIT)
252b5132 3819 {
2ca3ace5
L		 3820 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3821 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3822 i.suffix);
3823 return 0;
252b5132 3824 }
29b0f896
AM		 3825 else
3826#if REGISTER_WARNINGS
a540244d
L		 3827 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3828 register_prefix,
29b0f896 3829 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3830 register_prefix,
29b0f896
AM		 3831 i.op[op].regs->reg_name,
3832 i.suffix);
3833#endif
3834 }
3835 return 1;
3836}
252b5132 3837
29b0f896 3838static int
40fb9820 3839update_imm (unsigned int j)
29b0f896 3840{
40fb9820
L		 3841 i386_operand_type overlap;
3842
c6fb90c8 3843 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3844 if ((overlap.bitfield.imm8
3845 || overlap.bitfield.imm8s
3846 || overlap.bitfield.imm16
3847 || overlap.bitfield.imm32
3848 || overlap.bitfield.imm32s
3849 || overlap.bitfield.imm64)
c6fb90c8
L		 3850 && !UINTS_EQUAL (overlap, imm8)
3851 && !UINTS_EQUAL (overlap, imm8s)
3852 && !UINTS_EQUAL (overlap, imm16)
3853 && !UINTS_EQUAL (overlap, imm32)
3854 && !UINTS_EQUAL (overlap, imm32s)
3855 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3856 {
3857 if (i.suffix)
3858 {
40fb9820
L		 3859 i386_operand_type temp;
3860
c6fb90c8 3861 UINTS_CLEAR (temp);
40fb9820
L		 3862 if (i.suffix == BYTE_MNEM_SUFFIX)
3863 {
3864 temp.bitfield.imm8 = overlap.bitfield.imm8;
3865 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3866 }
3867 else if (i.suffix == WORD_MNEM_SUFFIX)
3868 temp.bitfield.imm16 = overlap.bitfield.imm16;
3869 else if (i.suffix == QWORD_MNEM_SUFFIX)
3870 {
3871 temp.bitfield.imm64 = overlap.bitfield.imm64;
3872 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3873 }
3874 else
3875 temp.bitfield.imm32 = overlap.bitfield.imm32;
3876 overlap = temp;
29b0f896 3877 }
c6fb90c8
L		 3878 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3879 || UINTS_EQUAL (overlap, imm16_32)
3880 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3881 {
c6fb90c8 3882 UINTS_CLEAR (overlap);
40fb9820
L		 3883 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3884 overlap.bitfield.imm16 = 1;
3885 else
3886 overlap.bitfield.imm32s = 1;
29b0f896 3887 }
c6fb90c8
L		 3888 if (!UINTS_EQUAL (overlap, imm8)
3889 && !UINTS_EQUAL (overlap, imm8s)
3890 && !UINTS_EQUAL (overlap, imm16)
3891 && !UINTS_EQUAL (overlap, imm32)
3892 && !UINTS_EQUAL (overlap, imm32s)
3893 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3894 {
4eed87de
AM		 3895 as_bad (_("no instruction mnemonic suffix given; "
3896 "can't determine immediate size"));
29b0f896
AM		 3897 return 0;
3898 }
3899 }
40fb9820 3900 i.types[j] = overlap;
29b0f896 3901
40fb9820
L		 3902 return 1;
3903}
3904
3905static int
3906finalize_imm (void)
3907{
3908 unsigned int j;
29b0f896 3909
40fb9820
L		 3910 for (j = 0; j < 2; j++)
3911 if (update_imm (j) == 0)
3912 return 0;
3913
c6fb90c8 3914 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3915 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3916
3917 return 1;
3918}
3919
85f10a01
MM		 3920static void
3921process_drex (void)
3922{
5dd15031
JJ		 3923 i.drex.modrm_reg = 0;
3924 i.drex.modrm_regmem = 0;
85f10a01
MM		 3925
3926 /* SSE5 4 operand instructions must have the destination the same as
3927 one of the inputs. Figure out the destination register and cache
3928 it away in the drex field, and remember which fields to use for
3929 the modrm byte. */
3930 if (i.tm.opcode_modifier.drex
3931 && i.tm.opcode_modifier.drexv
3932 && i.operands == 4)
3933 {
3934 i.tm.extension_opcode = None;
3935
3936 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3937 if (i.types[0].bitfield.regxmm != 0
3938 && i.types[1].bitfield.regxmm != 0
3939 && i.types[2].bitfield.regxmm != 0
3940 && i.types[3].bitfield.regxmm != 0
3941 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3942 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3943 {
3944 /* Clear the arguments that are stored in drex. */
3945 UINTS_CLEAR (i.types[0]);
3946 UINTS_CLEAR (i.types[3]);
3947 i.reg_operands -= 2;
3948
3949 /* There are two different ways to encode a 4 operand
3950 instruction with all registers that uses OC1 set to
3951 0 or 1. Favor setting OC1 to 0 since this mimics the
3952 actions of other SSE5 assemblers. Use modrm encoding 2
3953 for register/register. Include the high order bit that
3954 is normally stored in the REX byte in the register
3955 field. */
3956 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3957 i.drex.modrm_reg = 2;
3958 i.drex.modrm_regmem = 1;
3959 i.drex.reg = (i.op[3].regs->reg_num
3960 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3961 }
3962
3963 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3964 else if (i.types[0].bitfield.regxmm != 0
3965 && i.types[1].bitfield.regxmm != 0
3966 && (i.types[2].bitfield.regxmm
3967 || operand_type_check (i.types[2], anymem))
3968 && i.types[3].bitfield.regxmm != 0
3969 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3970 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3971 {
3972 /* clear the arguments that are stored in drex */
3973 UINTS_CLEAR (i.types[0]);
3974 UINTS_CLEAR (i.types[3]);
3975 i.reg_operands -= 2;
3976
3977 /* Specify the modrm encoding for memory addressing. Include
3978 the high order bit that is normally stored in the REX byte
3979 in the register field. */
3980 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3981 i.drex.modrm_reg = 1;
3982 i.drex.modrm_regmem = 2;
3983 i.drex.reg = (i.op[3].regs->reg_num
3984 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3985 }
3986
3987 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3988 else if (i.types[0].bitfield.regxmm != 0
3989 && operand_type_check (i.types[1], anymem) != 0
3990 && i.types[2].bitfield.regxmm != 0
3991 && i.types[3].bitfield.regxmm != 0
3992 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3993 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3994 {
3995 /* Clear the arguments that are stored in drex. */
3996 UINTS_CLEAR (i.types[0]);
3997 UINTS_CLEAR (i.types[3]);
3998 i.reg_operands -= 2;
3999
4000 /* Specify the modrm encoding for memory addressing. Include
4001 the high order bit that is normally stored in the REX byte
4002 in the register field. */
4003 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4004 i.drex.modrm_reg = 2;
4005 i.drex.modrm_regmem = 1;
4006 i.drex.reg = (i.op[3].regs->reg_num
4007 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4008 }
4009
4010 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4011 else if (i.types[0].bitfield.regxmm != 0
4012 && i.types[1].bitfield.regxmm != 0
4013 && i.types[2].bitfield.regxmm != 0
4014 && i.types[3].bitfield.regxmm != 0
4015 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4016 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4017 {
4018 /* clear the arguments that are stored in drex */
4019 UINTS_CLEAR (i.types[2]);
4020 UINTS_CLEAR (i.types[3]);
4021 i.reg_operands -= 2;
4022
4023 /* There are two different ways to encode a 4 operand
4024 instruction with all registers that uses OC1 set to
4025 0 or 1. Favor setting OC1 to 0 since this mimics the
4026 actions of other SSE5 assemblers. Use modrm encoding
4027 2 for register/register. Include the high order bit that
4028 is normally stored in the REX byte in the register
4029 field. */
4030 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4031 i.drex.modrm_reg = 1;
4032 i.drex.modrm_regmem = 0;
4033
4034 /* Remember the register, including the upper bits */
4035 i.drex.reg = (i.op[3].regs->reg_num
4036 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4037 }
4038
4039 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4040 else if (i.types[0].bitfield.regxmm != 0
4041 && (i.types[1].bitfield.regxmm
4042 || operand_type_check (i.types[1], anymem))
4043 && i.types[2].bitfield.regxmm != 0
4044 && i.types[3].bitfield.regxmm != 0
4045 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4046 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4047 {
4048 /* Clear the arguments that are stored in drex. */
4049 UINTS_CLEAR (i.types[2]);
4050 UINTS_CLEAR (i.types[3]);
4051 i.reg_operands -= 2;
4052
4053 /* Specify the modrm encoding and remember the register
4054 including the bits normally stored in the REX byte. */
4055 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4056 i.drex.modrm_reg = 0;
4057 i.drex.modrm_regmem = 1;
4058 i.drex.reg = (i.op[3].regs->reg_num
4059 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4060 }
4061
4062 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4063 else if (operand_type_check (i.types[0], anymem) != 0
4064 && i.types[1].bitfield.regxmm != 0
4065 && i.types[2].bitfield.regxmm != 0
4066 && i.types[3].bitfield.regxmm != 0
4067 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4068 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4069 {
4070 /* clear the arguments that are stored in drex */
4071 UINTS_CLEAR (i.types[2]);
4072 UINTS_CLEAR (i.types[3]);
4073 i.reg_operands -= 2;
4074
4075 /* Specify the modrm encoding and remember the register
4076 including the bits normally stored in the REX byte. */
4077 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4078 i.drex.modrm_reg = 1;
4079 i.drex.modrm_regmem = 0;
4080 i.drex.reg = (i.op[3].regs->reg_num
4081 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4082 }
4083
4084 else
4085 as_bad (_("Incorrect operands for the '%s' instruction"),
4086 i.tm.name);
4087 }
4088
4089 /* SSE5 instructions with the DREX byte where the only memory operand
4090 is in the 2nd argument, and the first and last xmm register must
4091 match, and is encoded in the DREX byte. */
4092 else if (i.tm.opcode_modifier.drex
4093 && !i.tm.opcode_modifier.drexv
4094 && i.operands == 4)
4095 {
4096 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4097 if (i.types[0].bitfield.regxmm != 0
4098 && (i.types[1].bitfield.regxmm
4099 || operand_type_check(i.types[1], anymem))
4100 && i.types[2].bitfield.regxmm != 0
4101 && i.types[3].bitfield.regxmm != 0
4102 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4103 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4104 {
4105 /* clear the arguments that are stored in drex */
4106 UINTS_CLEAR (i.types[0]);
4107 UINTS_CLEAR (i.types[3]);
4108 i.reg_operands -= 2;
4109
4110 /* Specify the modrm encoding and remember the register
4111 including the high bit normally stored in the REX
4112 byte. */
4113 i.drex.modrm_reg = 2;
4114 i.drex.modrm_regmem = 1;
4115 i.drex.reg = (i.op[3].regs->reg_num
4116 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4117 }
4118
4119 else
4120 as_bad (_("Incorrect operands for the '%s' instruction"),
4121 i.tm.name);
4122 }
4123
4124 /* SSE5 3 operand instructions that the result is a register, being
4125 either operand can be a memory operand, using OC0 to note which
4126 one is the memory. */
4127 else if (i.tm.opcode_modifier.drex
4128 && i.tm.opcode_modifier.drexv
4129 && i.operands == 3)
4130 {
4131 i.tm.extension_opcode = None;
4132
4133 /* Case 1: 3 operand insn, src1 = register. */
4134 if (i.types[0].bitfield.regxmm != 0
4135 && i.types[1].bitfield.regxmm != 0
4136 && i.types[2].bitfield.regxmm != 0)
4137 {
4138 /* Clear the arguments that are stored in drex. */
4139 UINTS_CLEAR (i.types[2]);
4140 i.reg_operands--;
4141
4142 /* Specify the modrm encoding and remember the register
4143 including the high bit normally stored in the REX byte. */
4144 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4145 i.drex.modrm_reg = 1;
4146 i.drex.modrm_regmem = 0;
4147 i.drex.reg = (i.op[2].regs->reg_num
4148 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4149 }
4150
4151 /* Case 2: 3 operand insn, src1 = memory. */
4152 else if (operand_type_check (i.types[0], anymem) != 0
4153 && i.types[1].bitfield.regxmm != 0
4154 && i.types[2].bitfield.regxmm != 0)
4155 {
4156 /* Clear the arguments that are stored in drex. */
4157 UINTS_CLEAR (i.types[2]);
4158 i.reg_operands--;
4159
4160 /* Specify the modrm encoding and remember the register
4161 including the high bit normally stored in the REX
4162 byte. */
4163 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4164 i.drex.modrm_reg = 1;
4165 i.drex.modrm_regmem = 0;
4166 i.drex.reg = (i.op[2].regs->reg_num
4167 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4168 }
4169
4170 /* Case 3: 3 operand insn, src2 = memory. */
4171 else if (i.types[0].bitfield.regxmm != 0
4172 && operand_type_check (i.types[1], anymem) != 0
4173 && i.types[2].bitfield.regxmm != 0)
4174 {
4175 /* Clear the arguments that are stored in drex. */
4176 UINTS_CLEAR (i.types[2]);
4177 i.reg_operands--;
4178
4179 /* Specify the modrm encoding and remember the register
4180 including the high bit normally stored in the REX byte. */
4181 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4182 i.drex.modrm_reg = 0;
4183 i.drex.modrm_regmem = 1;
4184 i.drex.reg = (i.op[2].regs->reg_num
4185 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4186 }
4187
4188 else
4189 as_bad (_("Incorrect operands for the '%s' instruction"),
4190 i.tm.name);
4191 }
4192
4193 /* SSE5 4 operand instructions that are the comparison instructions
4194 where the first operand is the immediate value of the comparison
4195 to be done. */
4196 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4197 {
4198 /* Case 1: 4 operand insn, src1 = reg/memory. */
4199 if (operand_type_check (i.types[0], imm) != 0
4200 && (i.types[1].bitfield.regxmm
4201 || operand_type_check (i.types[1], anymem))
4202 && i.types[2].bitfield.regxmm != 0
4203 && i.types[3].bitfield.regxmm != 0)
4204 {
4205 /* clear the arguments that are stored in drex */
4206 UINTS_CLEAR (i.types[3]);
4207 i.reg_operands--;
4208
4209 /* Specify the modrm encoding and remember the register
4210 including the high bit normally stored in the REX byte. */
4211 i.drex.modrm_reg = 2;
4212 i.drex.modrm_regmem = 1;
4213 i.drex.reg = (i.op[3].regs->reg_num
4214 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4215 }
4216
4217 /* Case 2: 3 operand insn with ImmExt that places the
4218 opcode_extension as an immediate argument. This is used for
4219 all of the varients of comparison that supplies the appropriate
4220 value as part of the instruction. */
4221 else if ((i.types[0].bitfield.regxmm
4222 || operand_type_check (i.types[0], anymem))
4223 && i.types[1].bitfield.regxmm != 0
4224 && i.types[2].bitfield.regxmm != 0
4225 && operand_type_check (i.types[3], imm) != 0)
4226 {
4227 /* clear the arguments that are stored in drex */
4228 UINTS_CLEAR (i.types[2]);
4229 i.reg_operands--;
4230
4231 /* Specify the modrm encoding and remember the register
4232 including the high bit normally stored in the REX byte. */
4233 i.drex.modrm_reg = 1;
4234 i.drex.modrm_regmem = 0;
4235 i.drex.reg = (i.op[2].regs->reg_num
4236 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4237 }
4238
4239 else
4240 as_bad (_("Incorrect operands for the '%s' instruction"),
4241 i.tm.name);
4242 }
4243
4244 else if (i.tm.opcode_modifier.drex
4245 || i.tm.opcode_modifier.drexv
4246 || i.tm.opcode_modifier.drexc)
4247 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4248}
4249
29b0f896 4250static int
e3bb37b5 4251process_operands (void)
29b0f896
AM		 4252{
4253 /* Default segment register this instruction will use for memory
4254 accesses. 0 means unknown. This is only for optimizing out
4255 unnecessary segment overrides. */
4256 const seg_entry *default_seg = 0;
4257
85f10a01
MM		 4258 /* Handle all of the DREX munging that SSE5 needs. */
4259 if (i.tm.opcode_modifier.drex
4260 || i.tm.opcode_modifier.drexv
4261 || i.tm.opcode_modifier.drexc)
4262 process_drex ();
4263
e2ec9d29 4264 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4265 {
9fcfb3d7
L		 4266 unsigned int j;
4267
e2ec9d29
L		 4268 /* The first operand is implicit and must be xmm0. */
4269 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4270 if (i.op[0].regs->reg_num != 0)
4271 {
4272 if (intel_syntax)
4273 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4274 i.tm.name, register_prefix);
4275 else
4276 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4277 i.tm.name, register_prefix);
4278 return 0;
4279 }
9fcfb3d7
L		 4280
4281 for (j = 1; j < i.operands; j++)
4282 {
4283 i.op[j - 1] = i.op[j];
4284 i.types[j - 1] = i.types[j];
4285
4286 /* We need to adjust fields in i.tm since they are used by
4287 build_modrm_byte. */
4288 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4289 }
4290
e2ec9d29
L		 4291 i.operands--;
4292 i.reg_operands--;
e2ec9d29
L		 4293 i.tm.operands--;
4294 }
4295 else if (i.tm.opcode_modifier.regkludge)
4296 {
4297 /* The imul $imm, %reg instruction is converted into
4298 imul $imm, %reg, %reg, and the clr %reg instruction
4299 is converted into xor %reg, %reg. */
4300
4301 unsigned int first_reg_op;
4302
4303 if (operand_type_check (i.types[0], reg))
4304 first_reg_op = 0;
4305 else
4306 first_reg_op = 1;
4307 /* Pretend we saw the extra register operand. */
4308 assert (i.reg_operands == 1
4309 && i.op[first_reg_op + 1].regs == 0);
4310 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4311 i.types[first_reg_op + 1] = i.types[first_reg_op];
4312 i.operands++;
4313 i.reg_operands++;
29b0f896
AM		 4314 }
4315
40fb9820 4316 if (i.tm.opcode_modifier.shortform)
29b0f896 4317 {
40fb9820
L		 4318 if (i.types[0].bitfield.sreg2
4319 || i.types[0].bitfield.sreg3)
29b0f896 4320 {
4eed87de
AM		 4321 if (i.tm.base_opcode == POP_SEG_SHORT
4322 && i.op[0].regs->reg_num == 1)
29b0f896 4323 {
4eed87de
AM		 4324 as_bad (_("you can't `pop %%cs'"));
4325 return 0;
29b0f896 4326 }
4eed87de
AM		 4327 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4328 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4329 i.rex |= REX_B;
4eed87de
AM		 4330 }
4331 else
4332 {
85f10a01
MM		 4333 /* The register or float register operand is in operand
4334 0 or 1. */
40fb9820
L		 4335 unsigned int op;
4336
4337 if (i.types[0].bitfield.floatreg
4338 || operand_type_check (i.types[0], reg))
4339 op = 0;
4340 else
4341 op = 1;
4eed87de
AM		 4342 /* Register goes in low 3 bits of opcode. */
4343 i.tm.base_opcode |= i.op[op].regs->reg_num;
4344 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4345 i.rex |= REX_B;
40fb9820 4346 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4347 {
4eed87de
AM		 4348 /* Warn about some common errors, but press on regardless.
4349 The first case can be generated by gcc (<= 2.8.1). */
4350 if (i.operands == 2)
4351 {
4352 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4353 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4354 register_prefix, i.op[1].regs->reg_name,
4355 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4356 }
4357 else
4358 {
4359 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4360 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4361 register_prefix, i.op[0].regs->reg_name);
4eed87de 4362 }
29b0f896
AM		 4363 }
4364 }
4365 }
40fb9820 4366 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4367 {
4368 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4369 must be put into the modrm byte). Now, we make the modrm and
4370 index base bytes based on all the info we've collected. */
29b0f896
AM		 4371
4372 default_seg = build_modrm_byte ();
4373 }
8a2ed489 4374 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4375 {
4376 default_seg = &ds;
4377 }
40fb9820 4378 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4379 {
4380 /* For the string instructions that allow a segment override
4381 on one of their operands, the default segment is ds. */
4382 default_seg = &ds;
4383 }
4384
75178d9d
L		 4385 if (i.tm.base_opcode == 0x8d /* lea */
4386 && i.seg[0]
4387 && !quiet_warnings)
30123838 4388 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4389
4390 /* If a segment was explicitly specified, and the specified segment
4391 is not the default, use an opcode prefix to select it. If we
4392 never figured out what the default segment is, then default_seg
4393 will be zero at this point, and the specified segment prefix will
4394 always be used. */
29b0f896
AM		 4395 if ((i.seg[0]) && (i.seg[0] != default_seg))
4396 {
4397 if (!add_prefix (i.seg[0]->seg_prefix))
4398 return 0;
4399 }
4400 return 1;
4401}
4402
4403static const seg_entry *
e3bb37b5 4404build_modrm_byte (void)
29b0f896
AM		 4405{
4406 const seg_entry *default_seg = 0;
4407
85f10a01
MM		 4408 /* SSE5 4 operand instructions are encoded in such a way that one of
4409 the inputs must match the destination register. Process_drex hides
4410 the 3rd argument in the drex field, so that by the time we get
4411 here, it looks to GAS as if this is a 2 operand instruction. */
4412 if ((i.tm.opcode_modifier.drex
4413 || i.tm.opcode_modifier.drexv
b5016f89 4414 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4415 && i.reg_operands == 2)
4416 {
4417 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4418 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4419
4420 i.rm.reg = reg->reg_num;
4421 i.rm.regmem = regmem->reg_num;
4422 i.rm.mode = 3;
4423 if ((reg->reg_flags & RegRex) != 0)
4424 i.rex |= REX_R;
4425 if ((regmem->reg_flags & RegRex) != 0)
4426 i.rex |= REX_B;
4427 }
4428
29b0f896
AM		 4429 /* i.reg_operands MUST be the number of real register operands;
4430 implicit registers do not count. */
85f10a01 4431 else if (i.reg_operands == 2)
29b0f896
AM		 4432 {
4433 unsigned int source, dest;
cab737b9
L		 4434
4435 switch (i.operands)
4436 {
4437 case 2:
4438 source = 0;
4439 break;
4440 case 3:
c81128dc
L		 4441 /* When there are 3 operands, one of them may be immediate,
4442 which may be the first or the last operand. Otherwise,
4443 the first operand must be shift count register (cl). */
4444 assert (i.imm_operands == 1
4445 || (i.imm_operands == 0
40fb9820
L		 4446 && i.types[0].bitfield.shiftcount));
4447 if (operand_type_check (i.types[0], imm)
4448 || i.types[0].bitfield.shiftcount)
4449 source = 1;
4450 else
4451 source = 0;
cab737b9
L		 4452 break;
4453 case 4:
368d64cc
L		 4454 /* When there are 4 operands, the first two must be 8bit
4455 immediate operands. The source operand will be the 3rd
4456 one. */
cab737b9 4457 assert (i.imm_operands == 2
368d64cc
L		 4458 && i.types[0].bitfield.imm8
4459 && i.types[1].bitfield.imm8);
cab737b9
L		 4460 source = 2;
4461 break;
4462 default:
4463 abort ();
4464 }
4465
29b0f896
AM		 4466 dest = source + 1;
4467
4468 i.rm.mode = 3;
4469 /* One of the register operands will be encoded in the i.tm.reg
4470 field, the other in the combined i.tm.mode and i.tm.regmem
4471 fields. If no form of this instruction supports a memory
4472 destination operand, then we assume the source operand may
4473 sometimes be a memory operand and so we need to store the
4474 destination in the i.rm.reg field. */
40fb9820
L		 4475 if (!i.tm.operand_types[dest].bitfield.regmem
4476 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4477 {
4478 i.rm.reg = i.op[dest].regs->reg_num;
4479 i.rm.regmem = i.op[source].regs->reg_num;
4480 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4481 i.rex |= REX_R;
29b0f896 4482 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4483 i.rex |= REX_B;
29b0f896
AM		 4484 }
4485 else
4486 {
4487 i.rm.reg = i.op[source].regs->reg_num;
4488 i.rm.regmem = i.op[dest].regs->reg_num;
4489 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4490 i.rex |= REX_B;
29b0f896 4491 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4492 i.rex |= REX_R;
29b0f896 4493 }
161a04f6 4494 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4495 {
40fb9820
L		 4496 if (!i.types[0].bitfield.control
4497 && !i.types[1].bitfield.control)
c4a530c5 4498 abort ();
161a04f6 4499 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4500 add_prefix (LOCK_PREFIX_OPCODE);
4501 }
29b0f896
AM		 4502 }
4503 else
4504 { /* If it's not 2 reg operands... */
4505 if (i.mem_operands)
4506 {
4507 unsigned int fake_zero_displacement = 0;
99018f42 4508 unsigned int op;
4eed87de 4509
85f10a01
MM		 4510 /* This has been precalculated for SSE5 instructions
4511 that have a DREX field earlier in process_drex. */
b5016f89
L		 4512 if (i.tm.opcode_modifier.drex
4513 || i.tm.opcode_modifier.drexv
4514 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4515 op = i.drex.modrm_regmem;
4516 else
4517 {
c0209578
L		 4518 for (op = 0; op < i.operands; op++)
4519 if (operand_type_check (i.types[op], anymem))
4520 break;
4521 assert (op < i.operands);
85f10a01 4522 }
29b0f896
AM		 4523
4524 default_seg = &ds;
4525
4526 if (i.base_reg == 0)
4527 {
4528 i.rm.mode = 0;
4529 if (!i.disp_operands)
4530 fake_zero_displacement = 1;
4531 if (i.index_reg == 0)
4532 {
4533 /* Operand is just <disp> */
20f0a1fc 4534 if (flag_code == CODE_64BIT)
29b0f896
AM		 4535 {
4536 /* 64bit mode overwrites the 32bit absolute
4537 addressing by RIP relative addressing and
4538 absolute addressing is encoded by one of the
4539 redundant SIB forms. */
4540 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4541 i.sib.base = NO_BASE_REGISTER;
4542 i.sib.index = NO_INDEX_REGISTER;
fc225355 4543 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4544 ? disp32s : disp32);
20f0a1fc 4545 }
fc225355
L		 4546 else if ((flag_code == CODE_16BIT)
4547 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4548 {
4549 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4550 i.types[op] = disp16;
20f0a1fc
NC		 4551 }
4552 else
4553 {
4554 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4555 i.types[op] = disp32;
29b0f896
AM		 4556 }
4557 }
4558 else /* !i.base_reg && i.index_reg */
4559 {
db51cc60
L		 4560 if (i.index_reg->reg_num == RegEiz
4561 || i.index_reg->reg_num == RegRiz)
4562 i.sib.index = NO_INDEX_REGISTER;
4563 else
4564 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4565 i.sib.base = NO_BASE_REGISTER;
4566 i.sib.scale = i.log2_scale_factor;
4567 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4568 i.types[op].bitfield.disp8 = 0;
4569 i.types[op].bitfield.disp16 = 0;
4570 i.types[op].bitfield.disp64 = 0;
29b0f896 4571 if (flag_code != CODE_64BIT)
40fb9820
L		 4572 {
4573 /* Must be 32 bit */
4574 i.types[op].bitfield.disp32 = 1;
4575 i.types[op].bitfield.disp32s = 0;
4576 }
29b0f896 4577 else
40fb9820
L		 4578 {
4579 i.types[op].bitfield.disp32 = 0;
4580 i.types[op].bitfield.disp32s = 1;
4581 }
29b0f896 4582 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4583 i.rex |= REX_X;
29b0f896
AM		 4584 }
4585 }
4586 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4587 else if (i.base_reg->reg_num == RegRip ||
4588 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4589 {
4590 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4591 i.types[op].bitfield.disp8 = 0;
4592 i.types[op].bitfield.disp16 = 0;
4593 i.types[op].bitfield.disp32 = 0;
4594 i.types[op].bitfield.disp32s = 1;
4595 i.types[op].bitfield.disp64 = 0;
71903a11 4596 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4597 if (! i.disp_operands)
4598 fake_zero_displacement = 1;
29b0f896 4599 }
40fb9820 4600 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4601 {
4602 switch (i.base_reg->reg_num)
4603 {
4604 case 3: /* (%bx) */
4605 if (i.index_reg == 0)
4606 i.rm.regmem = 7;
4607 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4608 i.rm.regmem = i.index_reg->reg_num - 6;
4609 break;
4610 case 5: /* (%bp) */
4611 default_seg = &ss;
4612 if (i.index_reg == 0)
4613 {
4614 i.rm.regmem = 6;
40fb9820 4615 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4616 {
4617 /* fake (%bp) into 0(%bp) */
40fb9820 4618 i.types[op].bitfield.disp8 = 1;
252b5132 4619 fake_zero_displacement = 1;
29b0f896
AM		 4620 }
4621 }
4622 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4623 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4624 break;
4625 default: /* (%si) -> 4 or (%di) -> 5 */
4626 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4627 }
4628 i.rm.mode = mode_from_disp_size (i.types[op]);
4629 }
4630 else /* i.base_reg and 32/64 bit mode */
4631 {
4632 if (flag_code == CODE_64BIT
40fb9820
L		 4633 && operand_type_check (i.types[op], disp))
4634 {
4635 i386_operand_type temp;
c6fb90c8 4636 UINTS_CLEAR (temp);
40fb9820
L		 4637 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4638 i.types[op] = temp;
4639 if (i.prefix[ADDR_PREFIX] == 0)
4640 i.types[op].bitfield.disp32s = 1;
4641 else
4642 i.types[op].bitfield.disp32 = 1;
4643 }
20f0a1fc 4644
29b0f896
AM		 4645 i.rm.regmem = i.base_reg->reg_num;
4646 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4647 i.rex |= REX_B;
29b0f896
AM		 4648 i.sib.base = i.base_reg->reg_num;
4649 /* x86-64 ignores REX prefix bit here to avoid decoder
4650 complications. */
4651 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4652 {
4653 default_seg = &ss;
4654 if (i.disp_operands == 0)
4655 {
4656 fake_zero_displacement = 1;
40fb9820 4657 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4658 }
4659 }
4660 else if (i.base_reg->reg_num == ESP_REG_NUM)
4661 {
4662 default_seg = &ss;
4663 }
4664 i.sib.scale = i.log2_scale_factor;
4665 if (i.index_reg == 0)
4666 {
4667 /* <disp>(%esp) becomes two byte modrm with no index
4668 register. We've already stored the code for esp
4669 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4670 Any base register besides %esp will not use the
4671 extra modrm byte. */
4672 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4673 }
4674 else
4675 {
db51cc60
L		 4676 if (i.index_reg->reg_num == RegEiz
4677 || i.index_reg->reg_num == RegRiz)
4678 i.sib.index = NO_INDEX_REGISTER;
4679 else
4680 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4681 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4682 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4683 i.rex |= REX_X;
29b0f896 4684 }
67a4f2b7
AO		 4685
4686 if (i.disp_operands
4687 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4688 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4689 i.rm.mode = 0;
4690 else
4691 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4692 }
252b5132 4693
29b0f896
AM		 4694 if (fake_zero_displacement)
4695 {
4696 /* Fakes a zero displacement assuming that i.types[op]
4697 holds the correct displacement size. */
4698 expressionS *exp;
4699
4700 assert (i.op[op].disps == 0);
4701 exp = &disp_expressions[i.disp_operands++];
4702 i.op[op].disps = exp;
4703 exp->X_op = O_constant;
4704 exp->X_add_number = 0;
4705 exp->X_add_symbol = (symbolS *) 0;
4706 exp->X_op_symbol = (symbolS *) 0;
4707 }
4708 }
252b5132 4709
29b0f896
AM		 4710 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4711 (if any) based on i.tm.extension_opcode. Again, we must be
4712 careful to make sure that segment/control/debug/test/MMX
4713 registers are coded into the i.rm.reg field. */
4714 if (i.reg_operands)
4715 {
99018f42
L		 4716 unsigned int op;
4717
85f10a01
MM		 4718 /* This has been precalculated for SSE5 instructions
4719 that have a DREX field earlier in process_drex. */
b5016f89
L		 4720 if (i.tm.opcode_modifier.drex
4721 || i.tm.opcode_modifier.drexv
4722 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4723 {
4724 op = i.drex.modrm_reg;
4725 i.rm.reg = i.op[op].regs->reg_num;
4726 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4727 i.rex |= REX_R;
4728 }
4729 else
4730 {
c0209578
L		 4731 for (op = 0; op < i.operands; op++)
4732 if (i.types[op].bitfield.reg8
4733 || i.types[op].bitfield.reg16
4734 || i.types[op].bitfield.reg32
4735 || i.types[op].bitfield.reg64
4736 || i.types[op].bitfield.regmmx
4737 || i.types[op].bitfield.regxmm
4738 || i.types[op].bitfield.sreg2
4739 || i.types[op].bitfield.sreg3
4740 || i.types[op].bitfield.control
4741 || i.types[op].bitfield.debug
4742 || i.types[op].bitfield.test)
4743 break;
4744
4745 assert (op < i.operands);
99018f42 4746
85f10a01
MM		 4747 /* If there is an extension opcode to put here, the
4748 register number must be put into the regmem field. */
c0209578
L		 4749 if (i.tm.extension_opcode != None)
4750 {
4751 i.rm.regmem = i.op[op].regs->reg_num;
4752 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4753 i.rex |= REX_B;
4754 }
4755 else
4756 {
4757 i.rm.reg = i.op[op].regs->reg_num;
4758 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4759 i.rex |= REX_R;
4760 }
85f10a01 4761 }
252b5132 4762
29b0f896
AM		 4763 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4764 must set it to 3 to indicate this is a register operand
4765 in the regmem field. */
4766 if (!i.mem_operands)
4767 i.rm.mode = 3;
4768 }
252b5132 4769
29b0f896 4770 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4771 if (i.tm.extension_opcode != None
4772 && !(i.tm.opcode_modifier.drex
4773 || i.tm.opcode_modifier.drexv
4774 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4775 i.rm.reg = i.tm.extension_opcode;
4776 }
4777 return default_seg;
4778}
252b5132 4779
29b0f896 4780static void
e3bb37b5 4781output_branch (void)
29b0f896
AM		 4782{
4783 char *p;
4784 int code16;
4785 int prefix;
4786 relax_substateT subtype;
4787 symbolS *sym;
4788 offsetT off;
4789
4790 code16 = 0;
4791 if (flag_code == CODE_16BIT)
4792 code16 = CODE16;
4793
4794 prefix = 0;
4795 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4796 {
29b0f896
AM		 4797 prefix = 1;
4798 i.prefixes -= 1;
4799 code16 ^= CODE16;
252b5132 4800 }
29b0f896
AM		 4801 /* Pentium4 branch hints. */
4802 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4803 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4804 {
29b0f896
AM		 4805 prefix++;
4806 i.prefixes--;
4807 }
4808 if (i.prefix[REX_PREFIX] != 0)
4809 {
4810 prefix++;
4811 i.prefixes--;
2f66722d
AM		 4812 }
4813
29b0f896
AM		 4814 if (i.prefixes != 0 && !intel_syntax)
4815 as_warn (_("skipping prefixes on this instruction"));
4816
4817 /* It's always a symbol; End frag & setup for relax.
4818 Make sure there is enough room in this frag for the largest
4819 instruction we may generate in md_convert_frag. This is 2
4820 bytes for the opcode and room for the prefix and largest
4821 displacement. */
4822 frag_grow (prefix + 2 + 4);
4823 /* Prefix and 1 opcode byte go in fr_fix. */
4824 p = frag_more (prefix + 1);
4825 if (i.prefix[DATA_PREFIX] != 0)
4826 *p++ = DATA_PREFIX_OPCODE;
4827 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4828 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4829 *p++ = i.prefix[SEG_PREFIX];
4830 if (i.prefix[REX_PREFIX] != 0)
4831 *p++ = i.prefix[REX_PREFIX];
4832 *p = i.tm.base_opcode;
4833
4834 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4835 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4836 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4837 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4838 else
4839 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4840 subtype |= code16;
3e73aa7c 4841
29b0f896
AM		 4842 sym = i.op[0].disps->X_add_symbol;
4843 off = i.op[0].disps->X_add_number;
3e73aa7c 4844
29b0f896
AM		 4845 if (i.op[0].disps->X_op != O_constant
4846 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4847 {
29b0f896
AM		 4848 /* Handle complex expressions. */
4849 sym = make_expr_symbol (i.op[0].disps);
4850 off = 0;
4851 }
3e73aa7c 4852
29b0f896
AM		 4853 /* 1 possible extra opcode + 4 byte displacement go in var part.
4854 Pass reloc in fr_var. */
4855 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4856}
3e73aa7c 4857
29b0f896 4858static void
e3bb37b5 4859output_jump (void)
29b0f896
AM		 4860{
4861 char *p;
4862 int size;
3e02c1cc 4863 fixS *fixP;
29b0f896 4864
40fb9820 4865 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4866 {
4867 /* This is a loop or jecxz type instruction. */
4868 size = 1;
4869 if (i.prefix[ADDR_PREFIX] != 0)
4870 {
4871 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4872 i.prefixes -= 1;
4873 }
4874 /* Pentium4 branch hints. */
4875 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4876 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4877 {
4878 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4879 i.prefixes--;
3e73aa7c
JH		 4880 }
4881 }
29b0f896
AM		 4882 else
4883 {
4884 int code16;
3e73aa7c 4885
29b0f896
AM		 4886 code16 = 0;
4887 if (flag_code == CODE_16BIT)
4888 code16 = CODE16;
3e73aa7c 4889
29b0f896
AM		 4890 if (i.prefix[DATA_PREFIX] != 0)
4891 {
4892 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4893 i.prefixes -= 1;
4894 code16 ^= CODE16;
4895 }
252b5132 4896
29b0f896
AM		 4897 size = 4;
4898 if (code16)
4899 size = 2;
4900 }
9fcc94b6 4901
29b0f896
AM		 4902 if (i.prefix[REX_PREFIX] != 0)
4903 {
4904 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4905 i.prefixes -= 1;
4906 }
252b5132 4907
29b0f896
AM		 4908 if (i.prefixes != 0 && !intel_syntax)
4909 as_warn (_("skipping prefixes on this instruction"));
e0890092 4910
29b0f896
AM		 4911 p = frag_more (1 + size);
4912 *p++ = i.tm.base_opcode;
e0890092 4913
3e02c1cc
AM		 4914 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4915 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4916
4917 /* All jumps handled here are signed, but don't use a signed limit
4918 check for 32 and 16 bit jumps as we want to allow wrap around at
4919 4G and 64k respectively. */
4920 if (size == 1)
4921 fixP->fx_signed = 1;
29b0f896 4922}
e0890092 4923
29b0f896 4924static void
e3bb37b5 4925output_interseg_jump (void)
29b0f896
AM		 4926{
4927 char *p;
4928 int size;
4929 int prefix;
4930 int code16;
252b5132 4931
29b0f896
AM		 4932 code16 = 0;
4933 if (flag_code == CODE_16BIT)
4934 code16 = CODE16;
a217f122 4935
29b0f896
AM		 4936 prefix = 0;
4937 if (i.prefix[DATA_PREFIX] != 0)
4938 {
4939 prefix = 1;
4940 i.prefixes -= 1;
4941 code16 ^= CODE16;
4942 }
4943 if (i.prefix[REX_PREFIX] != 0)
4944 {
4945 prefix++;
4946 i.prefixes -= 1;
4947 }
252b5132 4948
29b0f896
AM		 4949 size = 4;
4950 if (code16)
4951 size = 2;
252b5132 4952
29b0f896
AM		 4953 if (i.prefixes != 0 && !intel_syntax)
4954 as_warn (_("skipping prefixes on this instruction"));
252b5132 4955
29b0f896
AM		 4956 /* 1 opcode; 2 segment; offset */
4957 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4958
29b0f896
AM		 4959 if (i.prefix[DATA_PREFIX] != 0)
4960 *p++ = DATA_PREFIX_OPCODE;
252b5132 4961
29b0f896
AM		 4962 if (i.prefix[REX_PREFIX] != 0)
4963 *p++ = i.prefix[REX_PREFIX];
252b5132 4964
29b0f896
AM		 4965 *p++ = i.tm.base_opcode;
4966 if (i.op[1].imms->X_op == O_constant)
4967 {
4968 offsetT n = i.op[1].imms->X_add_number;
252b5132 4969
29b0f896
AM		 4970 if (size == 2
4971 && !fits_in_unsigned_word (n)
4972 && !fits_in_signed_word (n))
4973 {
4974 as_bad (_("16-bit jump out of range"));
4975 return;
4976 }
4977 md_number_to_chars (p, n, size);
4978 }
4979 else
4980 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4981 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4982 if (i.op[0].imms->X_op != O_constant)
4983 as_bad (_("can't handle non absolute segment in `%s'"),
4984 i.tm.name);
4985 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4986}
a217f122 4987
29b0f896 4988static void
e3bb37b5 4989output_insn (void)
29b0f896 4990{
2bbd9c25
JJ		 4991 fragS *insn_start_frag;
4992 offsetT insn_start_off;
4993
29b0f896
AM		 4994 /* Tie dwarf2 debug info to the address at the start of the insn.
4995 We can't do this after the insn has been output as the current
4996 frag may have been closed off. eg. by frag_var. */
4997 dwarf2_emit_insn (0);
4998
2bbd9c25
JJ		 4999 insn_start_frag = frag_now;
5000 insn_start_off = frag_now_fix ();
5001
29b0f896 5002 /* Output jumps. */
40fb9820 5003 if (i.tm.opcode_modifier.jump)
29b0f896 5004 output_branch ();
40fb9820
L		 5005 else if (i.tm.opcode_modifier.jumpbyte
5006 || i.tm.opcode_modifier.jumpdword)
29b0f896 5007 output_jump ();
40fb9820 5008 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5009 output_interseg_jump ();
5010 else
5011 {
5012 /* Output normal instructions here. */
5013 char *p;
5014 unsigned char *q;
47465058 5015 unsigned int j;
331d2d0d 5016 unsigned int prefix;
4dffcebc
L		 5017
5018 switch (i.tm.opcode_length)
bc4bd9ab 5019 {
4dffcebc 5020 case 3:
331d2d0d
L		 5021 if (i.tm.base_opcode & 0xff000000)
5022 {
5023 prefix = (i.tm.base_opcode >> 24) & 0xff;
5024 goto check_prefix;
5025 }
4dffcebc
L		 5026 break;
5027 case 2:
5028 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5029 {
4dffcebc
L		 5030 prefix = (i.tm.base_opcode >> 16) & 0xff;
5031 if (i.tm.cpu_flags.bitfield.cpupadlock)
5032 {
5033check_prefix:
5034 if (prefix != REPE_PREFIX_OPCODE
5035 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5036 add_prefix (prefix);
5037 }
5038 else
bc4bd9ab
MK		 5039 add_prefix (prefix);
5040 }
4dffcebc
L		 5041 break;
5042 case 1:
5043 break;
5044 default:
5045 abort ();
0f10071e 5046 }
252b5132 5047
29b0f896 5048 /* The prefix bytes. */
47465058
L		 5049 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5050 if (*q)
5051 FRAG_APPEND_1_CHAR (*q);
252b5132 5052
29b0f896 5053 /* Now the opcode; be careful about word order here! */
4dffcebc 5054 if (i.tm.opcode_length == 1)
29b0f896
AM		 5055 {
5056 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5057 }
5058 else
5059 {
4dffcebc 5060 switch (i.tm.opcode_length)
331d2d0d 5061 {
4dffcebc 5062 case 3:
331d2d0d
L		 5063 p = frag_more (3);
5064 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5065 break;
5066 case 2:
5067 p = frag_more (2);
5068 break;
5069 default:
5070 abort ();
5071 break;
331d2d0d 5072 }
0f10071e 5073
29b0f896
AM		 5074 /* Put out high byte first: can't use md_number_to_chars! */
5075 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5076 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5077
5078 /* On SSE5, encode the OC1 bit in the DREX field if this
5079 encoding has multiple formats. */
5080 if (i.tm.opcode_modifier.drex
5081 && i.tm.opcode_modifier.drexv
5082 && DREX_OC1 (i.tm.extension_opcode))
5083 *p |= DREX_OC1_MASK;
29b0f896 5084 }
3e73aa7c 5085
29b0f896 5086 /* Now the modrm byte and sib byte (if present). */
40fb9820 5087 if (i.tm.opcode_modifier.modrm)
29b0f896 5088 {
4a3523fa
L		 5089 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5090 | i.rm.reg << 3
5091 | i.rm.mode << 6));
29b0f896
AM		 5092 /* If i.rm.regmem == ESP (4)
5093 && i.rm.mode != (Register mode)
5094 && not 16 bit
5095 ==> need second modrm byte. */
5096 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5097 && i.rm.mode != 3
40fb9820 5098 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5099 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5100 | i.sib.index << 3
5101 | i.sib.scale << 6));
29b0f896 5102 }
3e73aa7c 5103
85f10a01
MM		 5104 /* Write the DREX byte if needed. */
5105 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5106 {
5107 p = frag_more (1);
5108 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5109
5110 /* Encode the OC0 bit if this encoding has multiple
5111 formats. */
5112 if ((i.tm.opcode_modifier.drex
5113 || i.tm.opcode_modifier.drexv)
5114 && DREX_OC0 (i.tm.extension_opcode))
5115 *p |= DREX_OC0_MASK;
5116 }
5117
29b0f896 5118 if (i.disp_operands)
2bbd9c25 5119 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5120
29b0f896 5121 if (i.imm_operands)
2bbd9c25 5122 output_imm (insn_start_frag, insn_start_off);
29b0f896 5123 }
252b5132 5124
29b0f896
AM		 5125#ifdef DEBUG386
5126 if (flag_debug)
5127 {
7b81dfbb 5128 pi ("" /*line*/, &i);
29b0f896
AM		 5129 }
5130#endif /* DEBUG386 */
5131}
252b5132 5132
e205caa7
L		 5133/* Return the size of the displacement operand N. */
5134
5135static int
5136disp_size (unsigned int n)
5137{
5138 int size = 4;
40fb9820
L		 5139 if (i.types[n].bitfield.disp64)
5140 size = 8;
5141 else if (i.types[n].bitfield.disp8)
5142 size = 1;
5143 else if (i.types[n].bitfield.disp16)
5144 size = 2;
e205caa7
L		 5145 return size;
5146}
5147
5148/* Return the size of the immediate operand N. */
5149
5150static int
5151imm_size (unsigned int n)
5152{
5153 int size = 4;
40fb9820
L		 5154 if (i.types[n].bitfield.imm64)
5155 size = 8;
5156 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5157 size = 1;
5158 else if (i.types[n].bitfield.imm16)
5159 size = 2;
e205caa7
L		 5160 return size;
5161}
5162
29b0f896 5163static void
64e74474 5164output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5165{
5166 char *p;
5167 unsigned int n;
252b5132 5168
29b0f896
AM		 5169 for (n = 0; n < i.operands; n++)
5170 {
40fb9820 5171 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5172 {
5173 if (i.op[n].disps->X_op == O_constant)
5174 {
e205caa7 5175 int size = disp_size (n);
29b0f896 5176 offsetT val;
252b5132 5177
29b0f896
AM		 5178 val = offset_in_range (i.op[n].disps->X_add_number,
5179 size);
5180 p = frag_more (size);
5181 md_number_to_chars (p, val, size);
5182 }
5183 else
5184 {
f86103b7 5185 enum bfd_reloc_code_real reloc_type;
e205caa7 5186 int size = disp_size (n);
40fb9820 5187 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5188 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5189
e205caa7 5190 /* We can't have 8 bit displacement here. */
40fb9820 5191 assert (!i.types[n].bitfield.disp8);
e205caa7 5192
29b0f896
AM		 5193 /* The PC relative address is computed relative
5194 to the instruction boundary, so in case immediate
5195 fields follows, we need to adjust the value. */
5196 if (pcrel && i.imm_operands)
5197 {
29b0f896 5198 unsigned int n1;
e205caa7 5199 int sz = 0;
252b5132 5200
29b0f896 5201 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5202 if (operand_type_check (i.types[n1], imm))
252b5132 5203 {
e205caa7
L		 5204 /* Only one immediate is allowed for PC
5205 relative address. */
5206 assert (sz == 0);
5207 sz = imm_size (n1);
5208 i.op[n].disps->X_add_number -= sz;
252b5132 5209 }
29b0f896 5210 /* We should find the immediate. */
e205caa7 5211 assert (sz != 0);
29b0f896 5212 }
520dc8e8 5213
29b0f896 5214 p = frag_more (size);
2bbd9c25 5215 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5216 if (GOT_symbol
2bbd9c25 5217 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5218 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5219 || reloc_type == BFD_RELOC_X86_64_32S
5220 || (reloc_type == BFD_RELOC_64
5221 && object_64bit))
d6ab8113
JB		 5222 && (i.op[n].disps->X_op == O_symbol
5223 || (i.op[n].disps->X_op == O_add
5224 && ((symbol_get_value_expression
5225 (i.op[n].disps->X_op_symbol)->X_op)
5226 == O_subtract))))
5227 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5228 {
5229 offsetT add;
5230
5231 if (insn_start_frag == frag_now)
5232 add = (p - frag_now->fr_literal) - insn_start_off;
5233 else
5234 {
5235 fragS *fr;
5236
5237 add = insn_start_frag->fr_fix - insn_start_off;
5238 for (fr = insn_start_frag->fr_next;
5239 fr && fr != frag_now; fr = fr->fr_next)
5240 add += fr->fr_fix;
5241 add += p - frag_now->fr_literal;
5242 }
5243
4fa24527 5244 if (!object_64bit)
7b81dfbb
AJ		 5245 {
5246 reloc_type = BFD_RELOC_386_GOTPC;
5247 i.op[n].imms->X_add_number += add;
5248 }
5249 else if (reloc_type == BFD_RELOC_64)
5250 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5251 else
7b81dfbb
AJ		 5252 /* Don't do the adjustment for x86-64, as there
5253 the pcrel addressing is relative to the _next_
5254 insn, and that is taken care of in other code. */
d6ab8113 5255 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5256 }
062cd5e7 5257 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5258 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5259 }
5260 }
5261 }
5262}
252b5132 5263
29b0f896 5264static void
64e74474 5265output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5266{
5267 char *p;
5268 unsigned int n;
252b5132 5269
29b0f896
AM		 5270 for (n = 0; n < i.operands; n++)
5271 {
40fb9820 5272 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5273 {
5274 if (i.op[n].imms->X_op == O_constant)
5275 {
e205caa7 5276 int size = imm_size (n);
29b0f896 5277 offsetT val;
b4cac588 5278
29b0f896
AM		 5279 val = offset_in_range (i.op[n].imms->X_add_number,
5280 size);
5281 p = frag_more (size);
5282 md_number_to_chars (p, val, size);
5283 }
5284 else
5285 {
5286 /* Not absolute_section.
5287 Need a 32-bit fixup (don't support 8bit
5288 non-absolute imms). Try to support other
5289 sizes ... */
f86103b7 5290 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5291 int size = imm_size (n);
5292 int sign;
29b0f896 5293
40fb9820 5294 if (i.types[n].bitfield.imm32s
a7d61044 5295 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5296 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5297 sign = 1;
e205caa7
L		 5298 else
5299 sign = 0;
520dc8e8 5300
29b0f896
AM		 5301 p = frag_more (size);
5302 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5303
2bbd9c25
JJ		 5304 /* This is tough to explain. We end up with this one if we
5305 * have operands that look like
5306 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5307 * obtain the absolute address of the GOT, and it is strongly
5308 * preferable from a performance point of view to avoid using
5309 * a runtime relocation for this. The actual sequence of
5310 * instructions often look something like:
5311 *
5312 * call .L66
5313 * .L66:
5314 * popl %ebx
5315 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5316 *
5317 * The call and pop essentially return the absolute address
5318 * of the label .L66 and store it in %ebx. The linker itself
5319 * will ultimately change the first operand of the addl so
5320 * that %ebx points to the GOT, but to keep things simple, the
5321 * .o file must have this operand set so that it generates not
5322 * the absolute address of .L66, but the absolute address of
5323 * itself. This allows the linker itself simply treat a GOTPC
5324 * relocation as asking for a pcrel offset to the GOT to be
5325 * added in, and the addend of the relocation is stored in the
5326 * operand field for the instruction itself.
5327 *
5328 * Our job here is to fix the operand so that it would add
5329 * the correct offset so that %ebx would point to itself. The
5330 * thing that is tricky is that .-.L66 will point to the
5331 * beginning of the instruction, so we need to further modify
5332 * the operand so that it will point to itself. There are
5333 * other cases where you have something like:
5334 *
5335 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5336 *
5337 * and here no correction would be required. Internally in
5338 * the assembler we treat operands of this form as not being
5339 * pcrel since the '.' is explicitly mentioned, and I wonder
5340 * whether it would simplify matters to do it this way. Who
5341 * knows. In earlier versions of the PIC patches, the
5342 * pcrel_adjust field was used to store the correction, but
5343 * since the expression is not pcrel, I felt it would be
5344 * confusing to do it this way. */
5345
d6ab8113 5346 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5347 || reloc_type == BFD_RELOC_X86_64_32S
5348 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5349 && GOT_symbol
5350 && GOT_symbol == i.op[n].imms->X_add_symbol
5351 && (i.op[n].imms->X_op == O_symbol
5352 || (i.op[n].imms->X_op == O_add
5353 && ((symbol_get_value_expression
5354 (i.op[n].imms->X_op_symbol)->X_op)
5355 == O_subtract))))
5356 {
2bbd9c25
JJ		 5357 offsetT add;
5358
5359 if (insn_start_frag == frag_now)
5360 add = (p - frag_now->fr_literal) - insn_start_off;
5361 else
5362 {
5363 fragS *fr;
5364
5365 add = insn_start_frag->fr_fix - insn_start_off;
5366 for (fr = insn_start_frag->fr_next;
5367 fr && fr != frag_now; fr = fr->fr_next)
5368 add += fr->fr_fix;
5369 add += p - frag_now->fr_literal;
5370 }
5371
4fa24527 5372 if (!object_64bit)
d6ab8113 5373 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5374 else if (size == 4)
d6ab8113 5375 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5376 else if (size == 8)
5377 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5378 i.op[n].imms->X_add_number += add;
29b0f896 5379 }
29b0f896
AM		 5380 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5381 i.op[n].imms, 0, reloc_type);
5382 }
5383 }
5384 }
252b5132
RH		 5385}
5386\f
d182319b
JB		 5387/* x86_cons_fix_new is called via the expression parsing code when a
5388 reloc is needed. We use this hook to get the correct .got reloc. */
5389static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5390static int cons_sign = -1;
5391
5392void
e3bb37b5 5393x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5394 expressionS *exp)
d182319b
JB		 5395{
5396 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5397
5398 got_reloc = NO_RELOC;
5399
5400#ifdef TE_PE
5401 if (exp->X_op == O_secrel)
5402 {
5403 exp->X_op = O_symbol;
5404 r = BFD_RELOC_32_SECREL;
5405 }
5406#endif
5407
5408 fix_new_exp (frag, off, len, exp, 0, r);
5409}
5410
718ddfc0
JB		 5411#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5412# define lex_got(reloc, adjust, types) NULL
5413#else
f3c180ae
AM		 5414/* Parse operands of the form
5415 <symbol>@GOTOFF+<nnn>
5416 and similar .plt or .got references.
5417
5418 If we find one, set up the correct relocation in RELOC and copy the
5419 input string, minus the `@GOTOFF' into a malloc'd buffer for
5420 parsing by the calling routine. Return this buffer, and if ADJUST
5421 is non-null set it to the length of the string we removed from the
5422 input line. Otherwise return NULL. */
5423static char *
3956db08 5424lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5425 int *adjust,
40fb9820 5426 i386_operand_type *types)
f3c180ae 5427{
7b81dfbb
AJ		 5428 /* Some of the relocations depend on the size of what field is to
5429 be relocated. But in our callers i386_immediate and i386_displacement
5430 we don't yet know the operand size (this will be set by insn
5431 matching). Hence we record the word32 relocation here,
5432 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5433 static const struct {
5434 const char *str;
4fa24527 5435 const enum bfd_reloc_code_real rel[2];
40fb9820 5436 const i386_operand_type types64;
f3c180ae 5437 } gotrel[] = {
4eed87de
AM		 5438 { "PLTOFF", { 0,
5439 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5440 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5441 { "PLT", { BFD_RELOC_386_PLT32,
5442 BFD_RELOC_X86_64_PLT32 },
40fb9820 5443 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5444 { "GOTPLT", { 0,
5445 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5446 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5447 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5448 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5449 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5450 { "GOTPCREL", { 0,
5451 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5452 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5453 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5454 BFD_RELOC_X86_64_TLSGD },
40fb9820 5455 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5456 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5457 0 },
40fb9820 5458 OPERAND_TYPE_NONE },
4eed87de
AM		 5459 { "TLSLD", { 0,
5460 BFD_RELOC_X86_64_TLSLD },
40fb9820 5461 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5462 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5463 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5464 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5465 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5466 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5467 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5468 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5469 0 },
40fb9820 5470 OPERAND_TYPE_NONE },
4eed87de
AM		 5471 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5472 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5473
5474 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5475 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5476 0 },
40fb9820 5477 OPERAND_TYPE_NONE },
4eed87de
AM		 5478 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5479 0 },
40fb9820 5480 OPERAND_TYPE_NONE },
4eed87de
AM		 5481 { "GOT", { BFD_RELOC_386_GOT32,
5482 BFD_RELOC_X86_64_GOT32 },
40fb9820 5483 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5484 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5485 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5486 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5487 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5488 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5489 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5490 };
5491 char *cp;
5492 unsigned int j;
5493
718ddfc0
JB		 5494 if (!IS_ELF)
5495 return NULL;
5496
f3c180ae 5497 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5498 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5499 return NULL;
5500
47465058 5501 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5502 {
5503 int len;
5504
5505 len = strlen (gotrel[j].str);
28f81592 5506 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5507 {
4fa24527 5508 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5509 {
28f81592
AM		 5510 int first, second;
5511 char *tmpbuf, *past_reloc;
f3c180ae 5512
4fa24527 5513 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5514 if (adjust)
5515 *adjust = len;
f3c180ae 5516
3956db08
JB		 5517 if (types)
5518 {
5519 if (flag_code != CODE_64BIT)
40fb9820
L		 5520 {
5521 types->bitfield.imm32 = 1;
5522 types->bitfield.disp32 = 1;
5523 }
3956db08
JB		 5524 else
5525 *types = gotrel[j].types64;
5526 }
5527
f3c180ae
AM		 5528 if (GOT_symbol == NULL)
5529 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5530
28f81592 5531 /* The length of the first part of our input line. */
f3c180ae 5532 first = cp - input_line_pointer;
28f81592
AM		 5533
5534 /* The second part goes from after the reloc token until
67c11a9b 5535 (and including) an end_of_line char or comma. */
28f81592 5536 past_reloc = cp + 1 + len;
67c11a9b
AM		 5537 cp = past_reloc;
5538 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5539 ++cp;
5540 second = cp + 1 - past_reloc;
28f81592
AM		 5541
5542 /* Allocate and copy string. The trailing NUL shouldn't
5543 be necessary, but be safe. */
5544 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5545 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5546 if (second != 0 && *past_reloc != ' ')
5547 /* Replace the relocation token with ' ', so that
5548 errors like foo@GOTOFF1 will be detected. */
5549 tmpbuf[first++] = ' ';
5550 memcpy (tmpbuf + first, past_reloc, second);
5551 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5552 return tmpbuf;
5553 }
5554
4fa24527
JB		 5555 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5556 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5557 return NULL;
5558 }
5559 }
5560
5561 /* Might be a symbol version string. Don't as_bad here. */
5562 return NULL;
5563}
5564
f3c180ae 5565void
e3bb37b5 5566x86_cons (expressionS *exp, int size)
f3c180ae 5567{
4fa24527 5568 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5569 {
5570 /* Handle @GOTOFF and the like in an expression. */
5571 char *save;
5572 char *gotfree_input_line;
5573 int adjust;
5574
5575 save = input_line_pointer;
3956db08 5576 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5577 if (gotfree_input_line)
5578 input_line_pointer = gotfree_input_line;
5579
5580 expression (exp);
5581
5582 if (gotfree_input_line)
5583 {
5584 /* expression () has merrily parsed up to the end of line,
5585 or a comma - in the wrong buffer. Transfer how far
5586 input_line_pointer has moved to the right buffer. */
5587 input_line_pointer = (save
5588 + (input_line_pointer - gotfree_input_line)
5589 + adjust);
5590 free (gotfree_input_line);
3992d3b7
AM		 5591 if (exp->X_op == O_constant
5592 || exp->X_op == O_absent
5593 || exp->X_op == O_illegal
5594 || exp->X_op == O_register
5595 || exp->X_op == O_big)
5596 {
5597 char c = *input_line_pointer;
5598 *input_line_pointer = 0;
5599 as_bad (_("missing or invalid expression `%s'"), save);
5600 *input_line_pointer = c;
5601 }
f3c180ae
AM		 5602 }
5603 }
5604 else
5605 expression (exp);
5606}
5607#endif
5608
d182319b 5609static void signed_cons (int size)
6482c264 5610{
d182319b
JB		 5611 if (flag_code == CODE_64BIT)
5612 cons_sign = 1;
5613 cons (size);
5614 cons_sign = -1;
6482c264
NC		 5615}
5616
d182319b 5617#ifdef TE_PE
6482c264
NC		 5618static void
5619pe_directive_secrel (dummy)
5620 int dummy ATTRIBUTE_UNUSED;
5621{
5622 expressionS exp;
5623
5624 do
5625 {
5626 expression (&exp);
5627 if (exp.X_op == O_symbol)
5628 exp.X_op = O_secrel;
5629
5630 emit_expr (&exp, 4);
5631 }
5632 while (*input_line_pointer++ == ',');
5633
5634 input_line_pointer--;
5635 demand_empty_rest_of_line ();
5636}
6482c264
NC		 5637#endif
5638
252b5132 5639static int
70e41ade 5640i386_immediate (char *imm_start)
252b5132
RH		 5641{
5642 char *save_input_line_pointer;
f3c180ae 5643 char *gotfree_input_line;
252b5132 5644 segT exp_seg = 0;
47926f60 5645 expressionS *exp;
40fb9820
L		 5646 i386_operand_type types;
5647
c6fb90c8 5648 UINTS_SET (types, ~0);
252b5132
RH		 5649
5650 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5651 {
31b2323c
L		 5652 as_bad (_("at most %d immediate operands are allowed"),
5653 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5654 return 0;
5655 }
5656
5657 exp = &im_expressions[i.imm_operands++];
520dc8e8 5658 i.op[this_operand].imms = exp;
252b5132
RH		 5659
5660 if (is_space_char (*imm_start))
5661 ++imm_start;
5662
5663 save_input_line_pointer = input_line_pointer;
5664 input_line_pointer = imm_start;
5665
3956db08 5666 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5667 if (gotfree_input_line)
5668 input_line_pointer = gotfree_input_line;
252b5132
RH		 5669
5670 exp_seg = expression (exp);
5671
83183c0c 5672 SKIP_WHITESPACE ();
252b5132 5673 if (*input_line_pointer)
f3c180ae 5674 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5675
5676 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5677 if (gotfree_input_line)
5678 free (gotfree_input_line);
252b5132 5679
3992d3b7
AM		 5680 if (exp->X_op == O_absent
5681 || exp->X_op == O_illegal
5682 || exp->X_op == O_big
5683 || (gotfree_input_line
5684 && (exp->X_op == O_constant
5685 || exp->X_op == O_register)))
252b5132 5686 {
3992d3b7 5687 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5688 imm_start);
3992d3b7 5689 return 0;
252b5132 5690 }
3e73aa7c 5691 else if (exp->X_op == O_constant)
252b5132 5692 {
47926f60 5693 /* Size it properly later. */
40fb9820 5694 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5695 /* If BFD64, sign extend val. */
4eed87de
AM		 5696 if (!use_rela_relocations
5697 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5698 exp->X_add_number
5699 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5700 }
4c63da97 5701#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5702 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5703 && exp_seg != absolute_section
47926f60 5704 && exp_seg != text_section
24eab124
AM		 5705 && exp_seg != data_section
5706 && exp_seg != bss_section
5707 && exp_seg != undefined_section
f86103b7 5708 && !bfd_is_com_section (exp_seg))
252b5132 5709 {
d0b47220 5710 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5711 return 0;
5712 }
5713#endif
bb8f5920
L		 5714 else if (!intel_syntax && exp->X_op == O_register)
5715 {
5716 as_bad (_("illegal immediate register operand %s"), imm_start);
5717 return 0;
5718 }
252b5132
RH		 5719 else
5720 {
5721 /* This is an address. The size of the address will be
24eab124 5722 determined later, depending on destination register,
3e73aa7c 5723 suffix, or the default for the section. */
40fb9820
L		 5724 i.types[this_operand].bitfield.imm8 = 1;
5725 i.types[this_operand].bitfield.imm16 = 1;
5726 i.types[this_operand].bitfield.imm32 = 1;
5727 i.types[this_operand].bitfield.imm32s = 1;
5728 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5729 i.types[this_operand] = operand_type_and (i.types[this_operand],
5730 types);
252b5132
RH		 5731 }
5732
5733 return 1;
5734}
5735
551c1ca1 5736static char *
e3bb37b5 5737i386_scale (char *scale)
252b5132 5738{
551c1ca1
AM		 5739 offsetT val;
5740 char *save = input_line_pointer;
252b5132 5741
551c1ca1
AM		 5742 input_line_pointer = scale;
5743 val = get_absolute_expression ();
5744
5745 switch (val)
252b5132 5746 {
551c1ca1 5747 case 1:
252b5132
RH		 5748 i.log2_scale_factor = 0;
5749 break;
551c1ca1 5750 case 2:
252b5132
RH		 5751 i.log2_scale_factor = 1;
5752 break;
551c1ca1 5753 case 4:
252b5132
RH		 5754 i.log2_scale_factor = 2;
5755 break;
551c1ca1 5756 case 8:
252b5132
RH		 5757 i.log2_scale_factor = 3;
5758 break;
5759 default:
a724f0f4
JB		 5760 {
5761 char sep = *input_line_pointer;
5762
5763 *input_line_pointer = '\0';
5764 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5765 scale);
5766 *input_line_pointer = sep;
5767 input_line_pointer = save;
5768 return NULL;
5769 }
252b5132 5770 }
29b0f896 5771 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5772 {
5773 as_warn (_("scale factor of %d without an index register"),
24eab124 5774 1 << i.log2_scale_factor);
252b5132 5775 i.log2_scale_factor = 0;
252b5132 5776 }
551c1ca1
AM		 5777 scale = input_line_pointer;
5778 input_line_pointer = save;
5779 return scale;
252b5132
RH		 5780}
5781
252b5132 5782static int
e3bb37b5 5783i386_displacement (char *disp_start, char *disp_end)
252b5132 5784{
29b0f896 5785 expressionS *exp;
252b5132
RH		 5786 segT exp_seg = 0;
5787 char *save_input_line_pointer;
f3c180ae 5788 char *gotfree_input_line;
40fb9820
L		 5789 int override;
5790 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5791 int ret;
252b5132 5792
31b2323c
L		 5793 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5794 {
5795 as_bad (_("at most %d displacement operands are allowed"),
5796 MAX_MEMORY_OPERANDS);
5797 return 0;
5798 }
5799
c6fb90c8 5800 UINTS_CLEAR (bigdisp);
40fb9820
L		 5801 if ((i.types[this_operand].bitfield.jumpabsolute)
5802 || (!current_templates->start->opcode_modifier.jump
5803 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5804 {
40fb9820 5805 bigdisp.bitfield.disp32 = 1;
e05278af 5806 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5807 if (flag_code == CODE_64BIT)
5808 {
5809 if (!override)
5810 {
5811 bigdisp.bitfield.disp32s = 1;
5812 bigdisp.bitfield.disp64 = 1;
5813 }
5814 }
5815 else if ((flag_code == CODE_16BIT) ^ override)
5816 {
5817 bigdisp.bitfield.disp32 = 0;
5818 bigdisp.bitfield.disp16 = 1;
5819 }
e05278af
JB		 5820 }
5821 else
5822 {
5823 /* For PC-relative branches, the width of the displacement
5824 is dependent upon data size, not address size. */
e05278af 5825 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5826 if (flag_code == CODE_64BIT)
5827 {
5828 if (override || i.suffix == WORD_MNEM_SUFFIX)
5829 bigdisp.bitfield.disp16 = 1;
5830 else
5831 {
5832 bigdisp.bitfield.disp32 = 1;
5833 bigdisp.bitfield.disp32s = 1;
5834 }
5835 }
5836 else
e05278af
JB		 5837 {
5838 if (!override)
5839 override = (i.suffix == (flag_code != CODE_16BIT
5840 ? WORD_MNEM_SUFFIX
5841 : LONG_MNEM_SUFFIX));
40fb9820
L		 5842 bigdisp.bitfield.disp32 = 1;
5843 if ((flag_code == CODE_16BIT) ^ override)
5844 {
5845 bigdisp.bitfield.disp32 = 0;
5846 bigdisp.bitfield.disp16 = 1;
5847 }
e05278af 5848 }
e05278af 5849 }
c6fb90c8
L		 5850 i.types[this_operand] = operand_type_or (i.types[this_operand],
5851 bigdisp);
252b5132
RH		 5852
5853 exp = &disp_expressions[i.disp_operands];
520dc8e8 5854 i.op[this_operand].disps = exp;
252b5132
RH		 5855 i.disp_operands++;
5856 save_input_line_pointer = input_line_pointer;
5857 input_line_pointer = disp_start;
5858 END_STRING_AND_SAVE (disp_end);
5859
5860#ifndef GCC_ASM_O_HACK
5861#define GCC_ASM_O_HACK 0
5862#endif
5863#if GCC_ASM_O_HACK
5864 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5865 if (i.types[this_operand].bitfield.baseIndex
24eab124 5866 && displacement_string_end[-1] == '+')
252b5132
RH		 5867 {
5868 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5869 constraint within gcc asm statements.
5870 For instance:
5871
5872 #define _set_tssldt_desc(n,addr,limit,type) \
5873 __asm__ __volatile__ ( \
5874 "movw %w2,%0\n\t" \
5875 "movw %w1,2+%0\n\t" \
5876 "rorl $16,%1\n\t" \
5877 "movb %b1,4+%0\n\t" \
5878 "movb %4,5+%0\n\t" \
5879 "movb $0,6+%0\n\t" \
5880 "movb %h1,7+%0\n\t" \
5881 "rorl $16,%1" \
5882 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5883
5884 This works great except that the output assembler ends
5885 up looking a bit weird if it turns out that there is
5886 no offset. You end up producing code that looks like:
5887
5888 #APP
5889 movw $235,(%eax)
5890 movw %dx,2+(%eax)
5891 rorl $16,%edx
5892 movb %dl,4+(%eax)
5893 movb $137,5+(%eax)
5894 movb $0,6+(%eax)
5895 movb %dh,7+(%eax)
5896 rorl $16,%edx
5897 #NO_APP
5898
47926f60 5899 So here we provide the missing zero. */
24eab124
AM		 5900
5901 *displacement_string_end = '0';
252b5132
RH		 5902 }
5903#endif
3956db08 5904 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5905 if (gotfree_input_line)
5906 input_line_pointer = gotfree_input_line;
252b5132 5907
24eab124 5908 exp_seg = expression (exp);
252b5132 5909
636c26b0
AM		 5910 SKIP_WHITESPACE ();
5911 if (*input_line_pointer)
5912 as_bad (_("junk `%s' after expression"), input_line_pointer);
5913#if GCC_ASM_O_HACK
5914 RESTORE_END_STRING (disp_end + 1);
5915#endif
636c26b0 5916 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5917 if (gotfree_input_line)
5918 free (gotfree_input_line);
3992d3b7 5919 ret = 1;
636c26b0 5920
24eab124
AM		 5921 /* We do this to make sure that the section symbol is in
5922 the symbol table. We will ultimately change the relocation
47926f60 5923 to be relative to the beginning of the section. */
1ae12ab7 5924 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5925 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5926 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5927 {
636c26b0 5928 if (exp->X_op != O_symbol)
3992d3b7 5929 goto inv_disp;
636c26b0 5930
e5cb08ac 5931 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5932 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5933 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5934 exp->X_op = O_subtract;
5935 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5936 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5937 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5938 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5939 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5940 else
29b0f896 5941 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5942 }
252b5132 5943
3992d3b7
AM		 5944 else if (exp->X_op == O_absent
5945 || exp->X_op == O_illegal
5946 || exp->X_op == O_big
5947 || (gotfree_input_line
5948 && (exp->X_op == O_constant
5949 || exp->X_op == O_register)))
2daf4fd8 5950 {
3992d3b7
AM		 5951 inv_disp:
5952 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5953 disp_start);
3992d3b7 5954 ret = 0;
2daf4fd8
AM		 5955 }
5956
4c63da97 5957#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5958 else if (exp->X_op != O_constant
5959 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5960 && exp_seg != absolute_section
5961 && exp_seg != text_section
5962 && exp_seg != data_section
5963 && exp_seg != bss_section
5964 && exp_seg != undefined_section
5965 && !bfd_is_com_section (exp_seg))
24eab124 5966 {
d0b47220 5967 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5968 ret = 0;
24eab124 5969 }
252b5132 5970#endif
3956db08 5971
3992d3b7
AM		 5972 RESTORE_END_STRING (disp_end);
5973
40fb9820
L		 5974 /* Check if this is a displacement only operand. */
5975 bigdisp = i.types[this_operand];
5976 bigdisp.bitfield.disp8 = 0;
5977 bigdisp.bitfield.disp16 = 0;
5978 bigdisp.bitfield.disp32 = 0;
5979 bigdisp.bitfield.disp32s = 0;
5980 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5981 if (UINTS_ALL_ZERO (bigdisp))
5982 i.types[this_operand] = operand_type_and (i.types[this_operand],
5983 types);
3956db08 5984
3992d3b7 5985 return ret;
252b5132
RH		 5986}
5987
eecb386c 5988/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5989 Return 1 on success, 0 on a failure. */
5990
252b5132 5991static int
e3bb37b5 5992i386_index_check (const char *operand_string)
252b5132 5993{
3e73aa7c 5994 int ok;
24eab124 5995#if INFER_ADDR_PREFIX
eecb386c
AM		 5996 int fudged = 0;
5997
24eab124
AM		 5998 tryprefix:
5999#endif
3e73aa7c 6000 ok = 1;
75178d9d 6001 if (flag_code == CODE_64BIT)
64e74474 6002 {
64e74474 6003 if ((i.base_reg
40fb9820
L		 6004 && ((i.prefix[ADDR_PREFIX] == 0
6005 && !i.base_reg->reg_type.bitfield.reg64)
6006 || (i.prefix[ADDR_PREFIX]
6007 && !i.base_reg->reg_type.bitfield.reg32))
6008 && (i.index_reg
9a04903e
JB		 6009 || i.base_reg->reg_num !=
6010 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6011 || (i.index_reg
40fb9820
L		 6012 && (!i.index_reg->reg_type.bitfield.baseindex
6013 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6014 && i.index_reg->reg_num != RegRiz
6015 && !i.index_reg->reg_type.bitfield.reg64
6016 )
40fb9820 6017 || (i.prefix[ADDR_PREFIX]
db51cc60 6018 && i.index_reg->reg_num != RegEiz
40fb9820 6019 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6020 ok = 0;
3e73aa7c
JH		 6021 }
6022 else
6023 {
6024 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6025 {
6026 /* 16bit checks. */
6027 if ((i.base_reg
40fb9820
L		 6028 && (!i.base_reg->reg_type.bitfield.reg16
6029 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6030 || (i.index_reg
40fb9820
L		 6031 && (!i.index_reg->reg_type.bitfield.reg16
6032 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6033 || !(i.base_reg
6034 && i.base_reg->reg_num < 6
6035 && i.index_reg->reg_num >= 6
6036 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6037 ok = 0;
6038 }
6039 else
e5cb08ac 6040 {
3e73aa7c
JH		 6041 /* 32bit checks. */
6042 if ((i.base_reg
40fb9820 6043 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6044 || (i.index_reg
db51cc60
L		 6045 && ((!i.index_reg->reg_type.bitfield.reg32
6046 && i.index_reg->reg_num != RegEiz)
40fb9820 6047 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6048 ok = 0;
3e73aa7c
JH		 6049 }
6050 }
6051 if (!ok)
24eab124
AM		 6052 {
6053#if INFER_ADDR_PREFIX
20f0a1fc 6054 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6055 {
6056 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6057 i.prefixes += 1;
b23bac36
AM		 6058 /* Change the size of any displacement too. At most one of
6059 Disp16 or Disp32 is set.
6060 FIXME. There doesn't seem to be any real need for separate
6061 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6062 Removing them would probably clean up the code quite a lot. */
4eed87de 6063 if (flag_code != CODE_64BIT
40fb9820
L		 6064 && (i.types[this_operand].bitfield.disp16
6065 || i.types[this_operand].bitfield.disp32))
6066 i.types[this_operand]
c6fb90c8 6067 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6068 fudged = 1;
24eab124
AM		 6069 goto tryprefix;
6070 }
eecb386c
AM		 6071 if (fudged)
6072 as_bad (_("`%s' is not a valid base/index expression"),
6073 operand_string);
6074 else
c388dee8 6075#endif
eecb386c
AM		 6076 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6077 operand_string,
3e73aa7c 6078 flag_code_names[flag_code]);
24eab124 6079 }
20f0a1fc 6080 return ok;
24eab124 6081}
252b5132 6082
252b5132 6083/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6084 on error. */
252b5132 6085
252b5132 6086static int
a7619375 6087i386_att_operand (char *operand_string)
252b5132 6088{
af6bdddf
AM		 6089 const reg_entry *r;
6090 char *end_op;
24eab124 6091 char *op_string = operand_string;
252b5132 6092
24eab124 6093 if (is_space_char (*op_string))
252b5132
RH		 6094 ++op_string;
6095
24eab124 6096 /* We check for an absolute prefix (differentiating,
47926f60 6097 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6098 if (*op_string == ABSOLUTE_PREFIX)
6099 {
6100 ++op_string;
6101 if (is_space_char (*op_string))
6102 ++op_string;
40fb9820 6103 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6104 }
252b5132 6105
47926f60 6106 /* Check if operand is a register. */
4d1bb795 6107 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6108 {
40fb9820
L		 6109 i386_operand_type temp;
6110
24eab124
AM		 6111 /* Check for a segment override by searching for ':' after a
6112 segment register. */
6113 op_string = end_op;
6114 if (is_space_char (*op_string))
6115 ++op_string;
40fb9820
L		 6116 if (*op_string == ':'
6117 && (r->reg_type.bitfield.sreg2
6118 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6119 {
6120 switch (r->reg_num)
6121 {
6122 case 0:
6123 i.seg[i.mem_operands] = &es;
6124 break;
6125 case 1:
6126 i.seg[i.mem_operands] = &cs;
6127 break;
6128 case 2:
6129 i.seg[i.mem_operands] = &ss;
6130 break;
6131 case 3:
6132 i.seg[i.mem_operands] = &ds;
6133 break;
6134 case 4:
6135 i.seg[i.mem_operands] = &fs;
6136 break;
6137 case 5:
6138 i.seg[i.mem_operands] = &gs;
6139 break;
6140 }
252b5132 6141
24eab124 6142 /* Skip the ':' and whitespace. */
252b5132
RH		 6143 ++op_string;
6144 if (is_space_char (*op_string))
24eab124 6145 ++op_string;
252b5132 6146
24eab124
AM		 6147 if (!is_digit_char (*op_string)
6148 && !is_identifier_char (*op_string)
6149 && *op_string != '('
6150 && *op_string != ABSOLUTE_PREFIX)
6151 {
6152 as_bad (_("bad memory operand `%s'"), op_string);
6153 return 0;
6154 }
47926f60 6155 /* Handle case of %es:*foo. */
24eab124
AM		 6156 if (*op_string == ABSOLUTE_PREFIX)
6157 {
6158 ++op_string;
6159 if (is_space_char (*op_string))
6160 ++op_string;
40fb9820 6161 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6162 }
6163 goto do_memory_reference;
6164 }
6165 if (*op_string)
6166 {
d0b47220 6167 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6168 return 0;
6169 }
40fb9820
L		 6170 temp = r->reg_type;
6171 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6172 i.types[this_operand] = operand_type_or (i.types[this_operand],
6173 temp);
7d5e4556 6174 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6175 i.op[this_operand].regs = r;
24eab124
AM		 6176 i.reg_operands++;
6177 }
af6bdddf
AM		 6178 else if (*op_string == REGISTER_PREFIX)
6179 {
6180 as_bad (_("bad register name `%s'"), op_string);
6181 return 0;
6182 }
24eab124 6183 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6184 {
24eab124 6185 ++op_string;
40fb9820 6186 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6187 {
d0b47220 6188 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6189 return 0;
6190 }
6191 if (!i386_immediate (op_string))
6192 return 0;
6193 }
6194 else if (is_digit_char (*op_string)
6195 || is_identifier_char (*op_string)
e5cb08ac 6196 || *op_string == '(')
24eab124 6197 {
47926f60 6198 /* This is a memory reference of some sort. */
af6bdddf 6199 char *base_string;
252b5132 6200
47926f60 6201 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6202 char *displacement_string_start;
6203 char *displacement_string_end;
252b5132 6204
24eab124 6205 do_memory_reference:
24eab124 6206 if ((i.mem_operands == 1
40fb9820 6207 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6208 || i.mem_operands == 2)
6209 {
6210 as_bad (_("too many memory references for `%s'"),
6211 current_templates->start->name);
6212 return 0;
6213 }
252b5132 6214
24eab124
AM		 6215 /* Check for base index form. We detect the base index form by
6216 looking for an ')' at the end of the operand, searching
6217 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6218 after the '('. */
af6bdddf 6219 base_string = op_string + strlen (op_string);
c3332e24 6220
af6bdddf
AM		 6221 --base_string;
6222 if (is_space_char (*base_string))
6223 --base_string;
252b5132 6224
47926f60 6225 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6226 displacement_string_start = op_string;
6227 displacement_string_end = base_string + 1;
252b5132 6228
24eab124
AM		 6229 if (*base_string == ')')
6230 {
af6bdddf 6231 char *temp_string;
24eab124
AM		 6232 unsigned int parens_balanced = 1;
6233 /* We've already checked that the number of left & right ()'s are
47926f60 6234 equal, so this loop will not be infinite. */
24eab124
AM		 6235 do
6236 {
6237 base_string--;
6238 if (*base_string == ')')
6239 parens_balanced++;
6240 if (*base_string == '(')
6241 parens_balanced--;
6242 }
6243 while (parens_balanced);
c3332e24 6244
af6bdddf 6245 temp_string = base_string;
c3332e24 6246
24eab124 6247 /* Skip past '(' and whitespace. */
252b5132
RH		 6248 ++base_string;
6249 if (is_space_char (*base_string))
24eab124 6250 ++base_string;
252b5132 6251
af6bdddf 6252 if (*base_string == ','
4eed87de
AM		 6253 || ((i.base_reg = parse_register (base_string, &end_op))
6254 != NULL))
252b5132 6255 {
af6bdddf 6256 displacement_string_end = temp_string;
252b5132 6257
40fb9820 6258 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6259
af6bdddf 6260 if (i.base_reg)
24eab124 6261 {
24eab124
AM		 6262 base_string = end_op;
6263 if (is_space_char (*base_string))
6264 ++base_string;
af6bdddf
AM		 6265 }
6266
6267 /* There may be an index reg or scale factor here. */
6268 if (*base_string == ',')
6269 {
6270 ++base_string;
6271 if (is_space_char (*base_string))
6272 ++base_string;
6273
4eed87de
AM		 6274 if ((i.index_reg = parse_register (base_string, &end_op))
6275 != NULL)
24eab124 6276 {
af6bdddf 6277 base_string = end_op;
24eab124
AM		 6278 if (is_space_char (*base_string))
6279 ++base_string;
af6bdddf
AM		 6280 if (*base_string == ',')
6281 {
6282 ++base_string;
6283 if (is_space_char (*base_string))
6284 ++base_string;
6285 }
e5cb08ac 6286 else if (*base_string != ')')
af6bdddf 6287 {
4eed87de
AM		 6288 as_bad (_("expecting `,' or `)' "
6289 "after index register in `%s'"),
af6bdddf
AM		 6290 operand_string);
6291 return 0;
6292 }
24eab124 6293 }
af6bdddf 6294 else if (*base_string == REGISTER_PREFIX)
24eab124 6295 {
af6bdddf 6296 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6297 return 0;
6298 }
252b5132 6299
47926f60 6300 /* Check for scale factor. */
551c1ca1 6301 if (*base_string != ')')
af6bdddf 6302 {
551c1ca1
AM		 6303 char *end_scale = i386_scale (base_string);
6304
6305 if (!end_scale)
af6bdddf 6306 return 0;
24eab124 6307
551c1ca1 6308 base_string = end_scale;
af6bdddf
AM		 6309 if (is_space_char (*base_string))
6310 ++base_string;
6311 if (*base_string != ')')
6312 {
4eed87de
AM		 6313 as_bad (_("expecting `)' "
6314 "after scale factor in `%s'"),
af6bdddf
AM		 6315 operand_string);
6316 return 0;
6317 }
6318 }
6319 else if (!i.index_reg)
24eab124 6320 {
4eed87de
AM		 6321 as_bad (_("expecting index register or scale factor "
6322 "after `,'; got '%c'"),
af6bdddf 6323 *base_string);
24eab124
AM		 6324 return 0;
6325 }
6326 }
af6bdddf 6327 else if (*base_string != ')')
24eab124 6328 {
4eed87de
AM		 6329 as_bad (_("expecting `,' or `)' "
6330 "after base register in `%s'"),
af6bdddf 6331 operand_string);
24eab124
AM		 6332 return 0;
6333 }
c3332e24 6334 }
af6bdddf 6335 else if (*base_string == REGISTER_PREFIX)
c3332e24 6336 {
af6bdddf 6337 as_bad (_("bad register name `%s'"), base_string);
24eab124 6338 return 0;
c3332e24 6339 }
24eab124
AM		 6340 }
6341
6342 /* If there's an expression beginning the operand, parse it,
6343 assuming displacement_string_start and
6344 displacement_string_end are meaningful. */
6345 if (displacement_string_start != displacement_string_end)
6346 {
6347 if (!i386_displacement (displacement_string_start,
6348 displacement_string_end))
6349 return 0;
6350 }
6351
6352 /* Special case for (%dx) while doing input/output op. */
6353 if (i.base_reg
c6fb90c8 6354 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6355 && i.index_reg == 0
6356 && i.log2_scale_factor == 0
6357 && i.seg[i.mem_operands] == 0
40fb9820 6358 && !operand_type_check (i.types[this_operand], disp))
24eab124 6359 {
c6fb90c8 6360 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6361 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6362 return 1;
6363 }
6364
eecb386c
AM		 6365 if (i386_index_check (operand_string) == 0)
6366 return 0;
24eab124
AM		 6367 i.mem_operands++;
6368 }
6369 else
ce8a8b2f
AM		 6370 {
6371 /* It's not a memory operand; argh! */
24eab124
AM		 6372 as_bad (_("invalid char %s beginning operand %d `%s'"),
6373 output_invalid (*op_string),
6374 this_operand + 1,
6375 op_string);
6376 return 0;
6377 }
47926f60 6378 return 1; /* Normal return. */
252b5132
RH		 6379}
6380\f
ee7fcc42
AM		 6381/* md_estimate_size_before_relax()
6382
6383 Called just before relax() for rs_machine_dependent frags. The x86
6384 assembler uses these frags to handle variable size jump
6385 instructions.
6386
6387 Any symbol that is now undefined will not become defined.
6388 Return the correct fr_subtype in the frag.
6389 Return the initial "guess for variable size of frag" to caller.
6390 The guess is actually the growth beyond the fixed part. Whatever
6391 we do to grow the fixed or variable part contributes to our
6392 returned value. */
6393
252b5132
RH		 6394int
6395md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6396 fragS *fragP;
6397 segT segment;
252b5132 6398{
252b5132 6399 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6400 check for un-relaxable symbols. On an ELF system, we can't relax
6401 an externally visible symbol, because it may be overridden by a
6402 shared library. */
6403 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6404#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6405 || (IS_ELF
31312f95
AM		 6406 && (S_IS_EXTERNAL (fragP->fr_symbol)
6407 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6408#endif
6409 )
252b5132 6410 {
b98ef147
AM		 6411 /* Symbol is undefined in this segment, or we need to keep a
6412 reloc so that weak symbols can be overridden. */
6413 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6414 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6415 unsigned char *opcode;
6416 int old_fr_fix;
f6af82bd 6417
ee7fcc42
AM		 6418 if (fragP->fr_var != NO_RELOC)
6419 reloc_type = fragP->fr_var;
b98ef147 6420 else if (size == 2)
f6af82bd
AM		 6421 reloc_type = BFD_RELOC_16_PCREL;
6422 else
6423 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6424
ee7fcc42
AM		 6425 old_fr_fix = fragP->fr_fix;
6426 opcode = (unsigned char *) fragP->fr_opcode;
6427
fddf5b5b 6428 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6429 {
fddf5b5b
AM		 6430 case UNCOND_JUMP:
6431 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6432 opcode[0] = 0xe9;
252b5132 6433 fragP->fr_fix += size;
062cd5e7
AS		 6434 fix_new (fragP, old_fr_fix, size,
6435 fragP->fr_symbol,
6436 fragP->fr_offset, 1,
6437 reloc_type);
252b5132
RH		 6438 break;
6439
fddf5b5b 6440 case COND_JUMP86:
412167cb
AM		 6441 if (size == 2
6442 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6443 {
6444 /* Negate the condition, and branch past an
6445 unconditional jump. */
6446 opcode[0] ^= 1;
6447 opcode[1] = 3;
6448 /* Insert an unconditional jump. */
6449 opcode[2] = 0xe9;
6450 /* We added two extra opcode bytes, and have a two byte
6451 offset. */
6452 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6453 fix_new (fragP, old_fr_fix + 2, 2,
6454 fragP->fr_symbol,
6455 fragP->fr_offset, 1,
6456 reloc_type);
fddf5b5b
AM		 6457 break;
6458 }
6459 /* Fall through. */
6460
6461 case COND_JUMP:
412167cb
AM		 6462 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6463 {
3e02c1cc
AM		 6464 fixS *fixP;
6465
412167cb 6466 fragP->fr_fix += 1;
3e02c1cc
AM		 6467 fixP = fix_new (fragP, old_fr_fix, 1,
6468 fragP->fr_symbol,
6469 fragP->fr_offset, 1,
6470 BFD_RELOC_8_PCREL);
6471 fixP->fx_signed = 1;
412167cb
AM		 6472 break;
6473 }
93c2a809 6474
24eab124 6475 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6476 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6477 opcode[1] = opcode[0] + 0x10;
f6af82bd 6478 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6479 /* We've added an opcode byte. */
6480 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6481 fix_new (fragP, old_fr_fix + 1, size,
6482 fragP->fr_symbol,
6483 fragP->fr_offset, 1,
6484 reloc_type);
252b5132 6485 break;
fddf5b5b
AM		 6486
6487 default:
6488 BAD_CASE (fragP->fr_subtype);
6489 break;
252b5132
RH		 6490 }
6491 frag_wane (fragP);
ee7fcc42 6492 return fragP->fr_fix - old_fr_fix;
252b5132 6493 }
93c2a809 6494
93c2a809
AM		 6495 /* Guess size depending on current relax state. Initially the relax
6496 state will correspond to a short jump and we return 1, because
6497 the variable part of the frag (the branch offset) is one byte
6498 long. However, we can relax a section more than once and in that
6499 case we must either set fr_subtype back to the unrelaxed state,
6500 or return the value for the appropriate branch. */
6501 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6502}
6503
47926f60
KH		 6504/* Called after relax() is finished.
6505
6506 In: Address of frag.
6507 fr_type == rs_machine_dependent.
6508 fr_subtype is what the address relaxed to.
6509
6510 Out: Any fixSs and constants are set up.
6511 Caller will turn frag into a ".space 0". */
6512
252b5132
RH		 6513void
6514md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6515 bfd *abfd ATTRIBUTE_UNUSED;
6516 segT sec ATTRIBUTE_UNUSED;
29b0f896 6517 fragS *fragP;
252b5132 6518{
29b0f896 6519 unsigned char *opcode;
252b5132 6520 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6521 offsetT target_address;
6522 offsetT opcode_address;
252b5132 6523 unsigned int extension = 0;
847f7ad4 6524 offsetT displacement_from_opcode_start;
252b5132
RH		 6525
6526 opcode = (unsigned char *) fragP->fr_opcode;
6527
47926f60 6528 /* Address we want to reach in file space. */
252b5132 6529 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6530
47926f60 6531 /* Address opcode resides at in file space. */
252b5132
RH		 6532 opcode_address = fragP->fr_address + fragP->fr_fix;
6533
47926f60 6534 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6535 displacement_from_opcode_start = target_address - opcode_address;
6536
fddf5b5b 6537 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6538 {
47926f60
KH		 6539 /* Don't have to change opcode. */
6540 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6541 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6542 }
6543 else
6544 {
6545 if (no_cond_jump_promotion
6546 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6547 as_warn_where (fragP->fr_file, fragP->fr_line,
6548 _("long jump required"));
252b5132 6549
fddf5b5b
AM		 6550 switch (fragP->fr_subtype)
6551 {
6552 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6553 extension = 4; /* 1 opcode + 4 displacement */
6554 opcode[0] = 0xe9;
6555 where_to_put_displacement = &opcode[1];
6556 break;
252b5132 6557
fddf5b5b
AM		 6558 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6559 extension = 2; /* 1 opcode + 2 displacement */
6560 opcode[0] = 0xe9;
6561 where_to_put_displacement = &opcode[1];
6562 break;
252b5132 6563
fddf5b5b
AM		 6564 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6565 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6566 extension = 5; /* 2 opcode + 4 displacement */
6567 opcode[1] = opcode[0] + 0x10;
6568 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6569 where_to_put_displacement = &opcode[2];
6570 break;
252b5132 6571
fddf5b5b
AM		 6572 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6573 extension = 3; /* 2 opcode + 2 displacement */
6574 opcode[1] = opcode[0] + 0x10;
6575 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6576 where_to_put_displacement = &opcode[2];
6577 break;
252b5132 6578
fddf5b5b
AM		 6579 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6580 extension = 4;
6581 opcode[0] ^= 1;
6582 opcode[1] = 3;
6583 opcode[2] = 0xe9;
6584 where_to_put_displacement = &opcode[3];
6585 break;
6586
6587 default:
6588 BAD_CASE (fragP->fr_subtype);
6589 break;
6590 }
252b5132 6591 }
fddf5b5b 6592
7b81dfbb
AJ		 6593 /* If size if less then four we are sure that the operand fits,
6594 but if it's 4, then it could be that the displacement is larger
6595 then -/+ 2GB. */
6596 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6597 && object_64bit
6598 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6599 + ((addressT) 1 << 31))
6600 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6601 {
6602 as_bad_where (fragP->fr_file, fragP->fr_line,
6603 _("jump target out of range"));
6604 /* Make us emit 0. */
6605 displacement_from_opcode_start = extension;
6606 }
47926f60 6607 /* Now put displacement after opcode. */
252b5132
RH		 6608 md_number_to_chars ((char *) where_to_put_displacement,
6609 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6610 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6611 fragP->fr_fix += extension;
6612}
6613\f
252b5132
RH		 6614/* Apply a fixup (fixS) to segment data, once it has been determined
6615 by our caller that we have all the info we need to fix it up.
6616
6617 On the 386, immediates, displacements, and data pointers are all in
6618 the same (little-endian) format, so we don't need to care about which
6619 we are handling. */
6620
94f592af 6621void
55cf6793 6622md_apply_fix (fixP, valP, seg)
47926f60
KH		 6623 /* The fix we're to put in. */
6624 fixS *fixP;
47926f60 6625 /* Pointer to the value of the bits. */
c6682705 6626 valueT *valP;
47926f60
KH		 6627 /* Segment fix is from. */
6628 segT seg ATTRIBUTE_UNUSED;
252b5132 6629{
94f592af 6630 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6631 valueT value = *valP;
252b5132 6632
f86103b7 6633#if !defined (TE_Mach)
93382f6d
AM		 6634 if (fixP->fx_pcrel)
6635 {
6636 switch (fixP->fx_r_type)
6637 {
5865bb77
ILT		 6638 default:
6639 break;
6640
d6ab8113
JB		 6641 case BFD_RELOC_64:
6642 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6643 break;
93382f6d 6644 case BFD_RELOC_32:
ae8887b5 6645 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6646 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6647 break;
6648 case BFD_RELOC_16:
6649 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6650 break;
6651 case BFD_RELOC_8:
6652 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6653 break;
6654 }
6655 }
252b5132 6656
a161fe53 6657 if (fixP->fx_addsy != NULL
31312f95 6658 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6659 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6660 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6661 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6662 && !use_rela_relocations)
252b5132 6663 {
31312f95
AM		 6664 /* This is a hack. There should be a better way to handle this.
6665 This covers for the fact that bfd_install_relocation will
6666 subtract the current location (for partial_inplace, PC relative
6667 relocations); see more below. */
252b5132 6668#ifndef OBJ_AOUT
718ddfc0 6669 if (IS_ELF
252b5132
RH		 6670#ifdef TE_PE
6671 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6672#endif
6673 )
6674 value += fixP->fx_where + fixP->fx_frag->fr_address;
6675#endif
6676#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6677 if (IS_ELF)
252b5132 6678 {
6539b54b 6679 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6680
6539b54b 6681 if ((sym_seg == seg
2f66722d 6682 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6683 && sym_seg != absolute_section))
ae6063d4 6684 && !generic_force_reloc (fixP))
2f66722d
AM		 6685 {
6686 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6687 bfd_install_relocation subtracts them out again. I think
6688 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6689 it. FIXME. */
6690 value += fixP->fx_where + fixP->fx_frag->fr_address;
6691 }
252b5132
RH		 6692 }
6693#endif
6694#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6695 /* For some reason, the PE format does not store a
6696 section address offset for a PC relative symbol. */
6697 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6698 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6699 value += md_pcrel_from (fixP);
6700#endif
6701 }
6702
6703 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6704 and we must not disappoint it. */
252b5132 6705#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6706 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6707 switch (fixP->fx_r_type)
6708 {
6709 case BFD_RELOC_386_PLT32:
3e73aa7c 6710 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6711 /* Make the jump instruction point to the address of the operand. At
6712 runtime we merely add the offset to the actual PLT entry. */
6713 value = -4;
6714 break;
31312f95 6715
13ae64f3
JJ		 6716 case BFD_RELOC_386_TLS_GD:
6717 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6718 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6719 case BFD_RELOC_386_TLS_IE:
6720 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6721 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6722 case BFD_RELOC_X86_64_TLSGD:
6723 case BFD_RELOC_X86_64_TLSLD:
6724 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6725 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6726 value = 0; /* Fully resolved at runtime. No addend. */
6727 /* Fallthrough */
6728 case BFD_RELOC_386_TLS_LE:
6729 case BFD_RELOC_386_TLS_LDO_32:
6730 case BFD_RELOC_386_TLS_LE_32:
6731 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6732 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6733 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6734 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6735 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6736 break;
6737
67a4f2b7
AO		 6738 case BFD_RELOC_386_TLS_DESC_CALL:
6739 case BFD_RELOC_X86_64_TLSDESC_CALL:
6740 value = 0; /* Fully resolved at runtime. No addend. */
6741 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6742 fixP->fx_done = 0;
6743 return;
6744
00f7efb6
JJ		 6745 case BFD_RELOC_386_GOT32:
6746 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6747 value = 0; /* Fully resolved at runtime. No addend. */
6748 break;
47926f60
KH		 6749
6750 case BFD_RELOC_VTABLE_INHERIT:
6751 case BFD_RELOC_VTABLE_ENTRY:
6752 fixP->fx_done = 0;
94f592af 6753 return;
47926f60
KH		 6754
6755 default:
6756 break;
6757 }
6758#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6759 *valP = value;
f86103b7 6760#endif /* !defined (TE_Mach) */
3e73aa7c 6761
3e73aa7c 6762 /* Are we finished with this relocation now? */
c6682705 6763 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6764 fixP->fx_done = 1;
6765 else if (use_rela_relocations)
6766 {
6767 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6768 /* Remember value for tc_gen_reloc. */
6769 fixP->fx_addnumber = value;
3e73aa7c
JH		 6770 value = 0;
6771 }
f86103b7 6772
94f592af 6773 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6774}
252b5132 6775\f
252b5132 6776char *
499ac353 6777md_atof (int type, char *litP, int *sizeP)
252b5132 6778{
499ac353
NC		 6779 /* This outputs the LITTLENUMs in REVERSE order;
6780 in accord with the bigendian 386. */
6781 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6782}
6783\f
2d545b82 6784static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6785
252b5132 6786static char *
e3bb37b5 6787output_invalid (int c)
252b5132 6788{
3882b010 6789 if (ISPRINT (c))
f9f21a03
L		 6790 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6791 "'%c'", c);
252b5132 6792 else
f9f21a03 6793 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6794 "(0x%x)", (unsigned char) c);
252b5132
RH		 6795 return output_invalid_buf;
6796}
6797
af6bdddf 6798/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6799
6800static const reg_entry *
4d1bb795 6801parse_real_register (char *reg_string, char **end_op)
252b5132 6802{
af6bdddf
AM		 6803 char *s = reg_string;
6804 char *p;
252b5132
RH		 6805 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6806 const reg_entry *r;
6807
6808 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6809 if (*s == REGISTER_PREFIX)
6810 ++s;
6811
6812 if (is_space_char (*s))
6813 ++s;
6814
6815 p = reg_name_given;
af6bdddf 6816 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6817 {
6818 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6819 return (const reg_entry *) NULL;
6820 s++;
252b5132
RH		 6821 }
6822
6588847e
DN		 6823 /* For naked regs, make sure that we are not dealing with an identifier.
6824 This prevents confusing an identifier like `eax_var' with register
6825 `eax'. */
6826 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6827 return (const reg_entry *) NULL;
6828
af6bdddf 6829 *end_op = s;
252b5132
RH		 6830
6831 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6832
5f47d35b 6833 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6834 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6835 {
5f47d35b
AM		 6836 if (is_space_char (*s))
6837 ++s;
6838 if (*s == '(')
6839 {
af6bdddf 6840 ++s;
5f47d35b
AM		 6841 if (is_space_char (*s))
6842 ++s;
6843 if (*s >= '0' && *s <= '7')
6844 {
db557034 6845 int fpr = *s - '0';
af6bdddf 6846 ++s;
5f47d35b
AM		 6847 if (is_space_char (*s))
6848 ++s;
6849 if (*s == ')')
6850 {
6851 *end_op = s + 1;
db557034
AM		 6852 r = hash_find (reg_hash, "st(0)");
6853 know (r);
6854 return r + fpr;
5f47d35b 6855 }
5f47d35b 6856 }
47926f60 6857 /* We have "%st(" then garbage. */
5f47d35b
AM		 6858 return (const reg_entry *) NULL;
6859 }
6860 }
6861
db51cc60
L		 6862 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6863 if (r != NULL
6864 && !allow_index_reg
6865 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6866 return (const reg_entry *) NULL;
6867
1ae00879 6868 if (r != NULL
d946b91f 6869 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6870 || r->reg_type.bitfield.reg64)
6871 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6872 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6873 && flag_code != CODE_64BIT)
20f0a1fc 6874 return (const reg_entry *) NULL;
1ae00879 6875
252b5132
RH		 6876 return r;
6877}
4d1bb795
JB		 6878
6879/* REG_STRING starts *before* REGISTER_PREFIX. */
6880
6881static const reg_entry *
6882parse_register (char *reg_string, char **end_op)
6883{
6884 const reg_entry *r;
6885
6886 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6887 r = parse_real_register (reg_string, end_op);
6888 else
6889 r = NULL;
6890 if (!r)
6891 {
6892 char *save = input_line_pointer;
6893 char c;
6894 symbolS *symbolP;
6895
6896 input_line_pointer = reg_string;
6897 c = get_symbol_end ();
6898 symbolP = symbol_find (reg_string);
6899 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6900 {
6901 const expressionS *e = symbol_get_value_expression (symbolP);
6902
6903 know (e->X_op == O_register);
4eed87de 6904 know (e->X_add_number >= 0
c3fe08fa 6905 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6906 r = i386_regtab + e->X_add_number;
6907 *end_op = input_line_pointer;
6908 }
6909 *input_line_pointer = c;
6910 input_line_pointer = save;
6911 }
6912 return r;
6913}
6914
6915int
6916i386_parse_name (char *name, expressionS *e, char *nextcharP)
6917{
6918 const reg_entry *r;
6919 char *end = input_line_pointer;
6920
6921 *end = *nextcharP;
6922 r = parse_register (name, &input_line_pointer);
6923 if (r && end <= input_line_pointer)
6924 {
6925 *nextcharP = *input_line_pointer;
6926 *input_line_pointer = 0;
6927 e->X_op = O_register;
6928 e->X_add_number = r - i386_regtab;
6929 return 1;
6930 }
6931 input_line_pointer = end;
6932 *end = 0;
6933 return 0;
6934}
6935
6936void
6937md_operand (expressionS *e)
6938{
6939 if (*input_line_pointer == REGISTER_PREFIX)
6940 {
6941 char *end;
6942 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6943
6944 if (r)
6945 {
6946 e->X_op = O_register;
6947 e->X_add_number = r - i386_regtab;
6948 input_line_pointer = end;
6949 }
6950 }
6951}
6952
252b5132 6953\f
4cc782b5 6954#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6955const char *md_shortopts = "kVQ:sqn";
252b5132 6956#else
12b55ccc 6957const char *md_shortopts = "qn";
252b5132 6958#endif
6e0b89ee 6959
3e73aa7c 6960#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6961#define OPTION_64 (OPTION_MD_BASE + 1)
6962#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6963#define OPTION_MARCH (OPTION_MD_BASE + 3)
6964#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 6965#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6966#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6967#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6968#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6969#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 6970
99ad8390
NC		 6971struct option md_longopts[] =
6972{
3e73aa7c 6973 {"32", no_argument, NULL, OPTION_32},
99ad8390 6974#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6975 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6976#endif
b3b91714 6977 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6978 {"march", required_argument, NULL, OPTION_MARCH},
6979 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 6980 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
6981 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
6982 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
6983 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
6984 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 6985 {NULL, no_argument, NULL, 0}
6986};
6987size_t md_longopts_size = sizeof (md_longopts);
6988
6989int
9103f4f4 6990md_parse_option (int c, char *arg)
252b5132 6991{
9103f4f4
L		 6992 unsigned int i;
6993
252b5132
RH		 6994 switch (c)
6995 {
12b55ccc
L		 6996 case 'n':
6997 optimize_align_code = 0;
6998 break;
6999
a38cf1db
AM		 7000 case 'q':
7001 quiet_warnings = 1;
252b5132
RH		 7002 break;
7003
7004#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7005 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7006 should be emitted or not. FIXME: Not implemented. */
7007 case 'Q':
252b5132
RH		 7008 break;
7009
7010 /* -V: SVR4 argument to print version ID. */
7011 case 'V':
7012 print_version_id ();
7013 break;
7014
a38cf1db
AM		 7015 /* -k: Ignore for FreeBSD compatibility. */
7016 case 'k':
252b5132 7017 break;
4cc782b5
ILT		 7018
7019 case 's':
7020 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7021 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7022 break;
99ad8390
NC		 7023#endif
7024#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7025 case OPTION_64:
7026 {
7027 const char **list, **l;
7028
3e73aa7c
JH		 7029 list = bfd_target_list ();
7030 for (l = list; *l != NULL; l++)
8620418b 7031 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7032 || strcmp (*l, "coff-x86-64") == 0
7033 || strcmp (*l, "pe-x86-64") == 0
7034 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7035 {
7036 default_arch = "x86_64";
7037 break;
7038 }
3e73aa7c 7039 if (*l == NULL)
6e0b89ee 7040 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7041 free (list);
7042 }
7043 break;
7044#endif
252b5132 7045
6e0b89ee
AM		 7046 case OPTION_32:
7047 default_arch = "i386";
7048 break;
7049
b3b91714
AM		 7050 case OPTION_DIVIDE:
7051#ifdef SVR4_COMMENT_CHARS
7052 {
7053 char *n, *t;
7054 const char *s;
7055
7056 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7057 t = n;
7058 for (s = i386_comment_chars; *s != '\0'; s++)
7059 if (*s != '/')
7060 *t++ = *s;
7061 *t = '\0';
7062 i386_comment_chars = n;
7063 }
7064#endif
7065 break;
7066
9103f4f4
L		 7067 case OPTION_MARCH:
7068 if (*arg == '.')
7069 as_fatal (_("Invalid -march= option: `%s'"), arg);
7070 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7071 {
7072 if (strcmp (arg, cpu_arch [i].name) == 0)
7073 {
ccc9c027 7074 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7075 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7076 if (!cpu_arch_tune_set)
7077 {
7078 cpu_arch_tune = cpu_arch_isa;
7079 cpu_arch_tune_flags = cpu_arch_isa_flags;
7080 }
9103f4f4
L		 7081 break;
7082 }
7083 }
7084 if (i >= ARRAY_SIZE (cpu_arch))
7085 as_fatal (_("Invalid -march= option: `%s'"), arg);
7086 break;
7087
7088 case OPTION_MTUNE:
7089 if (*arg == '.')
7090 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7091 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7092 {
7093 if (strcmp (arg, cpu_arch [i].name) == 0)
7094 {
ccc9c027 7095 cpu_arch_tune_set = 1;
9103f4f4
L		 7096 cpu_arch_tune = cpu_arch [i].type;
7097 cpu_arch_tune_flags = cpu_arch[i].flags;
7098 break;
7099 }
7100 }
7101 if (i >= ARRAY_SIZE (cpu_arch))
7102 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7103 break;
7104
1efbbeb4
L		 7105 case OPTION_MMNEMONIC:
7106 if (strcasecmp (arg, "att") == 0)
7107 intel_mnemonic = 0;
7108 else if (strcasecmp (arg, "intel") == 0)
7109 intel_mnemonic = 1;
7110 else
7111 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7112 break;
7113
7114 case OPTION_MSYNTAX:
7115 if (strcasecmp (arg, "att") == 0)
7116 intel_syntax = 0;
7117 else if (strcasecmp (arg, "intel") == 0)
7118 intel_syntax = 1;
7119 else
7120 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7121 break;
7122
7123 case OPTION_MINDEX_REG:
7124 allow_index_reg = 1;
7125 break;
7126
7127 case OPTION_MNAKED_REG:
7128 allow_naked_reg = 1;
7129 break;
7130
7131 case OPTION_MOLD_GCC:
7132 old_gcc = 1;
1efbbeb4
L		 7133 break;
7134
252b5132
RH		 7135 default:
7136 return 0;
7137 }
7138 return 1;
7139}
7140
7141void
7142md_show_usage (stream)
7143 FILE *stream;
7144{
4cc782b5
ILT		 7145#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7146 fprintf (stream, _("\
a38cf1db
AM		 7147 -Q ignored\n\
7148 -V print assembler version number\n\
b3b91714
AM		 7149 -k ignored\n"));
7150#endif
7151 fprintf (stream, _("\
12b55ccc 7152 -n Do not optimize code alignment\n\
b3b91714
AM		 7153 -q quieten some warnings\n"));
7154#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7155 fprintf (stream, _("\
a38cf1db 7156 -s ignored\n"));
b3b91714 7157#endif
751d281c
L		 7158#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7159 fprintf (stream, _("\
7160 --32/--64 generate 32bit/64bit code\n"));
7161#endif
b3b91714
AM		 7162#ifdef SVR4_COMMENT_CHARS
7163 fprintf (stream, _("\
7164 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7165#else
7166 fprintf (stream, _("\
b3b91714 7167 --divide ignored\n"));
4cc782b5 7168#endif
9103f4f4
L		 7169 fprintf (stream, _("\
7170 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7171 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7172 core, core2, k6, athlon, k8, generic32, generic64\n"));
ba104c83
L		 7173 fprintf (stream, _("\
7174 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7175 fprintf (stream, _("\
7176 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7177 fprintf (stream, _("\
7178 -mindex-reg support pseudo index registers\n"));
7179 fprintf (stream, _("\
7180 -mnaked-reg don't require `%%' prefix for registers\n"));
7181 fprintf (stream, _("\
7182 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7183}
7184
3e73aa7c 7185#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7186 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7187
7188/* Pick the target format to use. */
7189
47926f60 7190const char *
e3bb37b5 7191i386_target_format (void)
252b5132 7192{
3e73aa7c 7193 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7194 {
7195 set_code_flag (CODE_64BIT);
c6fb90c8 7196 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7197 {
7198 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7199 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7200 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7201 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7202 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7203 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7204 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7205 cpu_arch_isa_flags.bitfield.cpummx= 1;
7206 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7207 cpu_arch_isa_flags.bitfield.cpusse = 1;
7208 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7209 }
c6fb90c8 7210 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7211 {
7212 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7213 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7214 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7215 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7216 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7217 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7218 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7219 cpu_arch_tune_flags.bitfield.cpummx= 1;
7220 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7221 cpu_arch_tune_flags.bitfield.cpusse = 1;
7222 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7223 }
9103f4f4 7224 }
3e73aa7c 7225 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7226 {
7227 set_code_flag (CODE_32BIT);
c6fb90c8 7228 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7229 {
7230 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7231 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7232 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7233 }
c6fb90c8 7234 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7235 {
7236 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7237 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7238 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7239 }
9103f4f4 7240 }
3e73aa7c
JH		 7241 else
7242 as_fatal (_("Unknown architecture"));
252b5132
RH		 7243 switch (OUTPUT_FLAVOR)
7244 {
872ce6ff
L		 7245#ifdef TE_PEP
7246 case bfd_target_coff_flavour:
7247 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7248 break;
7249#endif
4c63da97
AM		 7250#ifdef OBJ_MAYBE_AOUT
7251 case bfd_target_aout_flavour:
47926f60 7252 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7253#endif
7254#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7255 case bfd_target_coff_flavour:
7256 return "coff-i386";
4c63da97 7257#endif
3e73aa7c 7258#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7259 case bfd_target_elf_flavour:
3e73aa7c 7260 {
e5cb08ac 7261 if (flag_code == CODE_64BIT)
4fa24527
JB		 7262 {
7263 object_64bit = 1;
7264 use_rela_relocations = 1;
7265 }
9d7cbccd 7266 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7267 }
4c63da97 7268#endif
252b5132
RH		 7269 default:
7270 abort ();
7271 return NULL;
7272 }
7273}
7274
47926f60 7275#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7276
7277#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7278void
7279i386_elf_emit_arch_note (void)
a847613f 7280{
718ddfc0 7281 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7282 {
7283 char *p;
7284 asection *seg = now_seg;
7285 subsegT subseg = now_subseg;
7286 Elf_Internal_Note i_note;
7287 Elf_External_Note e_note;
7288 asection *note_secp;
7289 int len;
7290
7291 /* Create the .note section. */
7292 note_secp = subseg_new (".note", 0);
7293 bfd_set_section_flags (stdoutput,
7294 note_secp,
7295 SEC_HAS_CONTENTS | SEC_READONLY);
7296
7297 /* Process the arch string. */
7298 len = strlen (cpu_arch_name);
7299
7300 i_note.namesz = len + 1;
7301 i_note.descsz = 0;
7302 i_note.type = NT_ARCH;
7303 p = frag_more (sizeof (e_note.namesz));
7304 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7305 p = frag_more (sizeof (e_note.descsz));
7306 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7307 p = frag_more (sizeof (e_note.type));
7308 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7309 p = frag_more (len + 1);
7310 strcpy (p, cpu_arch_name);
7311
7312 frag_align (2, 0, 0);
7313
7314 subseg_set (seg, subseg);
7315 }
7316}
7317#endif
252b5132 7318\f
252b5132
RH		 7319symbolS *
7320md_undefined_symbol (name)
7321 char *name;
7322{
18dc2407
ILT		 7323 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7324 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7325 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7326 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7327 {
7328 if (!GOT_symbol)
7329 {
7330 if (symbol_find (name))
7331 as_bad (_("GOT already in symbol table"));
7332 GOT_symbol = symbol_new (name, undefined_section,
7333 (valueT) 0, &zero_address_frag);
7334 };
7335 return GOT_symbol;
7336 }
252b5132
RH		 7337 return 0;
7338}
7339
7340/* Round up a section size to the appropriate boundary. */
47926f60 7341
252b5132
RH		 7342valueT
7343md_section_align (segment, size)
ab9da554 7344 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7345 valueT size;
7346{
4c63da97
AM		 7347#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7348 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7349 {
7350 /* For a.out, force the section size to be aligned. If we don't do
7351 this, BFD will align it for us, but it will not write out the
7352 final bytes of the section. This may be a bug in BFD, but it is
7353 easier to fix it here since that is how the other a.out targets
7354 work. */
7355 int align;
7356
7357 align = bfd_get_section_alignment (stdoutput, segment);
7358 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7359 }
252b5132
RH		 7360#endif
7361
7362 return size;
7363}
7364
7365/* On the i386, PC-relative offsets are relative to the start of the
7366 next instruction. That is, the address of the offset, plus its
7367 size, since the offset is always the last part of the insn. */
7368
7369long
e3bb37b5 7370md_pcrel_from (fixS *fixP)
252b5132
RH		 7371{
7372 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7373}
7374
7375#ifndef I386COFF
7376
7377static void
e3bb37b5 7378s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7379{
29b0f896 7380 int temp;
252b5132 7381
8a75718c
JB		 7382#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7383 if (IS_ELF)
7384 obj_elf_section_change_hook ();
7385#endif
252b5132
RH		 7386 temp = get_absolute_expression ();
7387 subseg_set (bss_section, (subsegT) temp);
7388 demand_empty_rest_of_line ();
7389}
7390
7391#endif
7392
252b5132 7393void
e3bb37b5 7394i386_validate_fix (fixS *fixp)
252b5132
RH		 7395{
7396 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7397 {
23df1078
JH		 7398 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7399 {
4fa24527 7400 if (!object_64bit)
23df1078
JH		 7401 abort ();
7402 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7403 }
7404 else
7405 {
4fa24527 7406 if (!object_64bit)
d6ab8113
JB		 7407 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7408 else
7409 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7410 }
252b5132
RH		 7411 fixp->fx_subsy = 0;
7412 }
7413}
7414
252b5132
RH		 7415arelent *
7416tc_gen_reloc (section, fixp)
ab9da554 7417 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7418 fixS *fixp;
7419{
7420 arelent *rel;
7421 bfd_reloc_code_real_type code;
7422
7423 switch (fixp->fx_r_type)
7424 {
3e73aa7c
JH		 7425 case BFD_RELOC_X86_64_PLT32:
7426 case BFD_RELOC_X86_64_GOT32:
7427 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7428 case BFD_RELOC_386_PLT32:
7429 case BFD_RELOC_386_GOT32:
7430 case BFD_RELOC_386_GOTOFF:
7431 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7432 case BFD_RELOC_386_TLS_GD:
7433 case BFD_RELOC_386_TLS_LDM:
7434 case BFD_RELOC_386_TLS_LDO_32:
7435 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7436 case BFD_RELOC_386_TLS_IE:
7437 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7438 case BFD_RELOC_386_TLS_LE_32:
7439 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7440 case BFD_RELOC_386_TLS_GOTDESC:
7441 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7442 case BFD_RELOC_X86_64_TLSGD:
7443 case BFD_RELOC_X86_64_TLSLD:
7444 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7445 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7446 case BFD_RELOC_X86_64_GOTTPOFF:
7447 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7448 case BFD_RELOC_X86_64_TPOFF64:
7449 case BFD_RELOC_X86_64_GOTOFF64:
7450 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7451 case BFD_RELOC_X86_64_GOT64:
7452 case BFD_RELOC_X86_64_GOTPCREL64:
7453 case BFD_RELOC_X86_64_GOTPC64:
7454 case BFD_RELOC_X86_64_GOTPLT64:
7455 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7456 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7457 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7458 case BFD_RELOC_RVA:
7459 case BFD_RELOC_VTABLE_ENTRY:
7460 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7461#ifdef TE_PE
7462 case BFD_RELOC_32_SECREL:
7463#endif
252b5132
RH		 7464 code = fixp->fx_r_type;
7465 break;
dbbaec26
L		 7466 case BFD_RELOC_X86_64_32S:
7467 if (!fixp->fx_pcrel)
7468 {
7469 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7470 code = fixp->fx_r_type;
7471 break;
7472 }
252b5132 7473 default:
93382f6d 7474 if (fixp->fx_pcrel)
252b5132 7475 {
93382f6d
AM		 7476 switch (fixp->fx_size)
7477 {
7478 default:
b091f402
AM		 7479 as_bad_where (fixp->fx_file, fixp->fx_line,
7480 _("can not do %d byte pc-relative relocation"),
7481 fixp->fx_size);
93382f6d
AM		 7482 code = BFD_RELOC_32_PCREL;
7483 break;
7484 case 1: code = BFD_RELOC_8_PCREL; break;
7485 case 2: code = BFD_RELOC_16_PCREL; break;
7486 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7487#ifdef BFD64
7488 case 8: code = BFD_RELOC_64_PCREL; break;
7489#endif
93382f6d
AM		 7490 }
7491 }
7492 else
7493 {
7494 switch (fixp->fx_size)
7495 {
7496 default:
b091f402
AM		 7497 as_bad_where (fixp->fx_file, fixp->fx_line,
7498 _("can not do %d byte relocation"),
7499 fixp->fx_size);
93382f6d
AM		 7500 code = BFD_RELOC_32;
7501 break;
7502 case 1: code = BFD_RELOC_8; break;
7503 case 2: code = BFD_RELOC_16; break;
7504 case 4: code = BFD_RELOC_32; break;
937149dd 7505#ifdef BFD64
3e73aa7c 7506 case 8: code = BFD_RELOC_64; break;
937149dd 7507#endif
93382f6d 7508 }
252b5132
RH		 7509 }
7510 break;
7511 }
252b5132 7512
d182319b
JB		 7513 if ((code == BFD_RELOC_32
7514 || code == BFD_RELOC_32_PCREL
7515 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7516 && GOT_symbol
7517 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7518 {
4fa24527 7519 if (!object_64bit)
d6ab8113
JB		 7520 code = BFD_RELOC_386_GOTPC;
7521 else
7522 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7523 }
7b81dfbb
AJ		 7524 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7525 && GOT_symbol
7526 && fixp->fx_addsy == GOT_symbol)
7527 {
7528 code = BFD_RELOC_X86_64_GOTPC64;
7529 }
252b5132
RH		 7530
7531 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7532 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7533 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7534
7535 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7536
3e73aa7c
JH		 7537 if (!use_rela_relocations)
7538 {
7539 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7540 vtable entry to be used in the relocation's section offset. */
7541 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7542 rel->address = fixp->fx_offset;
252b5132 7543
c6682705 7544 rel->addend = 0;
3e73aa7c
JH		 7545 }
7546 /* Use the rela in 64bit mode. */
252b5132 7547 else
3e73aa7c 7548 {
062cd5e7
AS		 7549 if (!fixp->fx_pcrel)
7550 rel->addend = fixp->fx_offset;
7551 else
7552 switch (code)
7553 {
7554 case BFD_RELOC_X86_64_PLT32:
7555 case BFD_RELOC_X86_64_GOT32:
7556 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7557 case BFD_RELOC_X86_64_TLSGD:
7558 case BFD_RELOC_X86_64_TLSLD:
7559 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7560 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7561 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7562 rel->addend = fixp->fx_offset - fixp->fx_size;
7563 break;
7564 default:
7565 rel->addend = (section->vma
7566 - fixp->fx_size
7567 + fixp->fx_addnumber
7568 + md_pcrel_from (fixp));
7569 break;
7570 }
3e73aa7c
JH		 7571 }
7572
252b5132
RH		 7573 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7574 if (rel->howto == NULL)
7575 {
7576 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7577 _("cannot represent relocation type %s"),
252b5132
RH		 7578 bfd_get_reloc_code_name (code));
7579 /* Set howto to a garbage value so that we can keep going. */
7580 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7581 assert (rel->howto != NULL);
7582 }
7583
7584 return rel;
7585}
7586
64a0c779
DN		 7587\f
7588/* Parse operands using Intel syntax. This implements a recursive descent
7589 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7590 Programmer's Guide.
7591
7592 FIXME: We do not recognize the full operand grammar defined in the MASM
7593 documentation. In particular, all the structure/union and
7594 high-level macro operands are missing.
7595
7596 Uppercase words are terminals, lower case words are non-terminals.
7597 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7598 bars '|' denote choices. Most grammar productions are implemented in
7599 functions called 'intel_<production>'.
7600
7601 Initial production is 'expr'.
7602
9306ca4a 7603 addOp + | -
64a0c779
DN		 7604
7605 alpha [a-zA-Z]
7606
9306ca4a
JB		 7607 binOp & | AND | \| | OR | ^ | XOR
7608
64a0c779
DN		 7609 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7610
7611 constant digits [[ radixOverride ]]
7612
9306ca4a 7613 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7614
7615 digits decdigit
b77a7acd
AJ		 7616 | digits decdigit
7617 | digits hexdigit
64a0c779
DN		 7618
7619 decdigit [0-9]
7620
9306ca4a
JB		 7621 e04 e04 addOp e05
7622 | e05
7623
7624 e05 e05 binOp e06
b77a7acd 7625 | e06
64a0c779
DN		 7626
7627 e06 e06 mulOp e09
b77a7acd 7628 | e09
64a0c779
DN		 7629
7630 e09 OFFSET e10
a724f0f4
JB		 7631 | SHORT e10
7632 | + e10
7633 | - e10
9306ca4a
JB		 7634 | ~ e10
7635 | NOT e10
64a0c779
DN		 7636 | e09 PTR e10
7637 | e09 : e10
7638 | e10
7639
7640 e10 e10 [ expr ]
b77a7acd 7641 | e11
64a0c779
DN		 7642
7643 e11 ( expr )
b77a7acd 7644 | [ expr ]
64a0c779
DN		 7645 | constant
7646 | dataType
7647 | id
7648 | $
7649 | register
7650
a724f0f4 7651 => expr expr cmpOp e04
9306ca4a 7652 | e04
64a0c779
DN		 7653
7654 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7655 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7656
7657 hexdigit a | b | c | d | e | f
b77a7acd 7658 | A | B | C | D | E | F
64a0c779
DN		 7659
7660 id alpha
b77a7acd 7661 | id alpha
64a0c779
DN		 7662 | id decdigit
7663
9306ca4a 7664 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7665
7666 quote " | '
7667
7668 register specialRegister
b77a7acd 7669 | gpRegister
64a0c779
DN		 7670 | byteRegister
7671
7672 segmentRegister CS | DS | ES | FS | GS | SS
7673
9306ca4a 7674 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7675 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7676 | TR3 | TR4 | TR5 | TR6 | TR7
7677
64a0c779
DN		 7678 We simplify the grammar in obvious places (e.g., register parsing is
7679 done by calling parse_register) and eliminate immediate left recursion
7680 to implement a recursive-descent parser.
7681
a724f0f4
JB		 7682 expr e04 expr'
7683
7684 expr' cmpOp e04 expr'
7685 | Empty
9306ca4a
JB		 7686
7687 e04 e05 e04'
7688
7689 e04' addOp e05 e04'
7690 | Empty
64a0c779
DN		 7691
7692 e05 e06 e05'
7693
9306ca4a 7694 e05' binOp e06 e05'
b77a7acd 7695 | Empty
64a0c779
DN		 7696
7697 e06 e09 e06'
7698
7699 e06' mulOp e09 e06'
b77a7acd 7700 | Empty
64a0c779
DN		 7701
7702 e09 OFFSET e10 e09'
a724f0f4
JB		 7703 | SHORT e10'
7704 | + e10'
7705 | - e10'
7706 | ~ e10'
7707 | NOT e10'
b77a7acd 7708 | e10 e09'
64a0c779
DN		 7709
7710 e09' PTR e10 e09'
b77a7acd 7711 | : e10 e09'
64a0c779
DN		 7712 | Empty
7713
7714 e10 e11 e10'
7715
7716 e10' [ expr ] e10'
b77a7acd 7717 | Empty
64a0c779
DN		 7718
7719 e11 ( expr )
b77a7acd 7720 | [ expr ]
64a0c779
DN		 7721 | BYTE
7722 | WORD
7723 | DWORD
9306ca4a 7724 | FWORD
64a0c779 7725 | QWORD
9306ca4a
JB		 7726 | TBYTE
7727 | OWORD
7728 | XMMWORD
64a0c779
DN		 7729 | .
7730 | $
7731 | register
7732 | id
7733 | constant */
7734
7735/* Parsing structure for the intel syntax parser. Used to implement the
7736 semantic actions for the operand grammar. */
7737struct intel_parser_s
7738 {
7739 char *op_string; /* The string being parsed. */
7740 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7741 int op_modifier; /* Operand modifier. */
64a0c779 7742 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7743 int in_offset; /* >=1 if parsing operand of offset. */
7744 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7745 const reg_entry *reg; /* Last register reference found. */
7746 char *disp; /* Displacement string being built. */
a724f0f4 7747 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7748 };
7749
7750static struct intel_parser_s intel_parser;
7751
7752/* Token structure for parsing intel syntax. */
7753struct intel_token
7754 {
7755 int code; /* Token code. */
7756 const reg_entry *reg; /* Register entry for register tokens. */
7757 char *str; /* String representation. */
7758 };
7759
7760static struct intel_token cur_token, prev_token;
7761
50705ef4
AM		 7762/* Token codes for the intel parser. Since T_SHORT is already used
7763 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7764#define T_NIL -1
7765#define T_CONST 1
7766#define T_REG 2
7767#define T_BYTE 3
7768#define T_WORD 4
9306ca4a
JB		 7769#define T_DWORD 5
7770#define T_FWORD 6
7771#define T_QWORD 7
7772#define T_TBYTE 8
7773#define T_XMMWORD 9
50705ef4 7774#undef T_SHORT
9306ca4a
JB		 7775#define T_SHORT 10
7776#define T_OFFSET 11
7777#define T_PTR 12
7778#define T_ID 13
7779#define T_SHL 14
7780#define T_SHR 15
64a0c779
DN		 7781
7782/* Prototypes for intel parser functions. */
e3bb37b5
L		 7783static int intel_match_token (int);
7784static void intel_putback_token (void);
7785static void intel_get_token (void);
7786static int intel_expr (void);
7787static int intel_e04 (void);
7788static int intel_e05 (void);
7789static int intel_e06 (void);
7790static int intel_e09 (void);
7791static int intel_e10 (void);
7792static int intel_e11 (void);
64a0c779 7793
64a0c779 7794static int
e3bb37b5 7795i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7796{
7797 int ret;
7798 char *p;
7799
a724f0f4
JB		 7800 p = intel_parser.op_string = xstrdup (operand_string);
7801 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7802
7803 for (;;)
64a0c779 7804 {
a724f0f4
JB		 7805 /* Initialize token holders. */
7806 cur_token.code = prev_token.code = T_NIL;
7807 cur_token.reg = prev_token.reg = NULL;
7808 cur_token.str = prev_token.str = NULL;
7809
7810 /* Initialize parser structure. */
7811 intel_parser.got_a_float = got_a_float;
7812 intel_parser.op_modifier = 0;
7813 intel_parser.is_mem = 0;
7814 intel_parser.in_offset = 0;
7815 intel_parser.in_bracket = 0;
7816 intel_parser.reg = NULL;
7817 intel_parser.disp[0] = '\0';
7818 intel_parser.next_operand = NULL;
7819
7820 /* Read the first token and start the parser. */
7821 intel_get_token ();
7822 ret = intel_expr ();
7823
7824 if (!ret)
7825 break;
7826
9306ca4a
JB		 7827 if (cur_token.code != T_NIL)
7828 {
7829 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7830 current_templates->start->name, cur_token.str);
7831 ret = 0;
7832 }
64a0c779
DN		 7833 /* If we found a memory reference, hand it over to i386_displacement
7834 to fill in the rest of the operand fields. */
9306ca4a 7835 else if (intel_parser.is_mem)
64a0c779
DN		 7836 {
7837 if ((i.mem_operands == 1
40fb9820 7838 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7839 || i.mem_operands == 2)
7840 {
7841 as_bad (_("too many memory references for '%s'"),
7842 current_templates->start->name);
7843 ret = 0;
7844 }
7845 else
7846 {
7847 char *s = intel_parser.disp;
7848 i.mem_operands++;
7849
a724f0f4
JB		 7850 if (!quiet_warnings && intel_parser.is_mem < 0)
7851 /* See the comments in intel_bracket_expr. */
7852 as_warn (_("Treating `%s' as memory reference"), operand_string);
7853
64a0c779
DN		 7854 /* Add the displacement expression. */
7855 if (*s != '\0')
a4622f40
AM		 7856 ret = i386_displacement (s, s + strlen (s));
7857 if (ret)
a724f0f4
JB		 7858 {
7859 /* Swap base and index in 16-bit memory operands like
7860 [si+bx]. Since i386_index_check is also used in AT&T
7861 mode we have to do that here. */
7862 if (i.base_reg
7863 && i.index_reg
40fb9820
L		 7864 && i.base_reg->reg_type.bitfield.reg16
7865 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7866 && i.base_reg->reg_num >= 6
7867 && i.index_reg->reg_num < 6)
7868 {
7869 const reg_entry *base = i.index_reg;
7870
7871 i.index_reg = i.base_reg;
7872 i.base_reg = base;
7873 }
7874 ret = i386_index_check (operand_string);
7875 }
64a0c779
DN		 7876 }
7877 }
7878
7879 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7880 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7881 || intel_parser.reg == NULL)
7882 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7883
7884 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7885 ret = 0;
a724f0f4
JB		 7886 if (!ret || !intel_parser.next_operand)
7887 break;
7888 intel_parser.op_string = intel_parser.next_operand;
7889 this_operand = i.operands++;
7d5e4556 7890 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 7891 }
7892
7893 free (p);
7894 free (intel_parser.disp);
7895
7896 return ret;
7897}
7898
a724f0f4
JB		 7899#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7900
7901/* expr e04 expr'
7902
7903 expr' cmpOp e04 expr'
7904 | Empty */
64a0c779 7905static int
e3bb37b5 7906intel_expr (void)
64a0c779 7907{
a724f0f4
JB		 7908 /* XXX Implement the comparison operators. */
7909 return intel_e04 ();
9306ca4a
JB		 7910}
7911
a724f0f4 7912/* e04 e05 e04'
9306ca4a 7913
a724f0f4 7914 e04' addOp e05 e04'
9306ca4a
JB		 7915 | Empty */
7916static int
e3bb37b5 7917intel_e04 (void)
9306ca4a 7918{
a724f0f4 7919 int nregs = -1;
9306ca4a 7920
a724f0f4 7921 for (;;)
9306ca4a 7922 {
a724f0f4
JB		 7923 if (!intel_e05())
7924 return 0;
9306ca4a 7925
a724f0f4
JB		 7926 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7927 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7928
a724f0f4
JB		 7929 if (cur_token.code == '+')
7930 nregs = -1;
7931 else if (cur_token.code == '-')
7932 nregs = NUM_ADDRESS_REGS;
7933 else
7934 return 1;
64a0c779 7935
a724f0f4
JB		 7936 strcat (intel_parser.disp, cur_token.str);
7937 intel_match_token (cur_token.code);
7938 }
64a0c779
DN		 7939}
7940
64a0c779
DN		 7941/* e05 e06 e05'
7942
9306ca4a 7943 e05' binOp e06 e05'
64a0c779
DN		 7944 | Empty */
7945static int
e3bb37b5 7946intel_e05 (void)
64a0c779 7947{
a724f0f4 7948 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7949
a724f0f4 7950 for (;;)
64a0c779 7951 {
a724f0f4
JB		 7952 if (!intel_e06())
7953 return 0;
7954
4eed87de
AM		 7955 if (cur_token.code == '&'
7956 || cur_token.code == '|'
7957 || cur_token.code == '^')
a724f0f4
JB		 7958 {
7959 char str[2];
7960
7961 str[0] = cur_token.code;
7962 str[1] = 0;
7963 strcat (intel_parser.disp, str);
7964 }
7965 else
7966 break;
9306ca4a 7967
64a0c779
DN		 7968 intel_match_token (cur_token.code);
7969
a724f0f4
JB		 7970 if (nregs < 0)
7971 nregs = ~nregs;
64a0c779 7972 }
a724f0f4
JB		 7973 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7974 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7975 return 1;
4a1805b1 7976}
64a0c779
DN		 7977
7978/* e06 e09 e06'
7979
7980 e06' mulOp e09 e06'
b77a7acd 7981 | Empty */
64a0c779 7982static int
e3bb37b5 7983intel_e06 (void)
64a0c779 7984{
a724f0f4 7985 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7986
a724f0f4 7987 for (;;)
64a0c779 7988 {
a724f0f4
JB		 7989 if (!intel_e09())
7990 return 0;
9306ca4a 7991
4eed87de
AM		 7992 if (cur_token.code == '*'
7993 || cur_token.code == '/'
7994 || cur_token.code == '%')
a724f0f4
JB		 7995 {
7996 char str[2];
9306ca4a 7997
a724f0f4
JB		 7998 str[0] = cur_token.code;
7999 str[1] = 0;
8000 strcat (intel_parser.disp, str);
8001 }
8002 else if (cur_token.code == T_SHL)
8003 strcat (intel_parser.disp, "<<");
8004 else if (cur_token.code == T_SHR)
8005 strcat (intel_parser.disp, ">>");
8006 else
8007 break;
9306ca4a 8008
64e74474 8009 intel_match_token (cur_token.code);
64a0c779 8010
a724f0f4
JB		 8011 if (nregs < 0)
8012 nregs = ~nregs;
64a0c779 8013 }
a724f0f4
JB		 8014 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8015 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8016 return 1;
64a0c779
DN		 8017}
8018
a724f0f4
JB		 8019/* e09 OFFSET e09
8020 | SHORT e09
8021 | + e09
8022 | - e09
8023 | ~ e09
8024 | NOT e09
9306ca4a
JB		 8025 | e10 e09'
8026
64a0c779 8027 e09' PTR e10 e09'
b77a7acd 8028 | : e10 e09'
64a0c779
DN		 8029 | Empty */
8030static int
e3bb37b5 8031intel_e09 (void)
64a0c779 8032{
a724f0f4
JB		 8033 int nregs = ~NUM_ADDRESS_REGS;
8034 int in_offset = 0;
8035
8036 for (;;)
64a0c779 8037 {
a724f0f4
JB		 8038 /* Don't consume constants here. */
8039 if (cur_token.code == '+' || cur_token.code == '-')
8040 {
8041 /* Need to look one token ahead - if the next token
8042 is a constant, the current token is its sign. */
8043 int next_code;
8044
8045 intel_match_token (cur_token.code);
8046 next_code = cur_token.code;
8047 intel_putback_token ();
8048 if (next_code == T_CONST)
8049 break;
8050 }
8051
8052 /* e09 OFFSET e09 */
8053 if (cur_token.code == T_OFFSET)
8054 {
8055 if (!in_offset++)
8056 ++intel_parser.in_offset;
8057 }
8058
8059 /* e09 SHORT e09 */
8060 else if (cur_token.code == T_SHORT)
8061 intel_parser.op_modifier |= 1 << T_SHORT;
8062
8063 /* e09 + e09 */
8064 else if (cur_token.code == '+')
8065 strcat (intel_parser.disp, "+");
8066
8067 /* e09 - e09
8068 | ~ e09
8069 | NOT e09 */
8070 else if (cur_token.code == '-' || cur_token.code == '~')
8071 {
8072 char str[2];
64a0c779 8073
a724f0f4
JB		 8074 if (nregs < 0)
8075 nregs = ~nregs;
8076 str[0] = cur_token.code;
8077 str[1] = 0;
8078 strcat (intel_parser.disp, str);
8079 }
8080
8081 /* e09 e10 e09' */
8082 else
8083 break;
8084
8085 intel_match_token (cur_token.code);
64a0c779
DN		 8086 }
8087
a724f0f4 8088 for (;;)
9306ca4a 8089 {
a724f0f4
JB		 8090 if (!intel_e10 ())
8091 return 0;
9306ca4a 8092
a724f0f4
JB		 8093 /* e09' PTR e10 e09' */
8094 if (cur_token.code == T_PTR)
8095 {
8096 char suffix;
9306ca4a 8097
a724f0f4 8098 if (prev_token.code == T_BYTE)
7d5e4556
L		 8099 {
8100 suffix = BYTE_MNEM_SUFFIX;
8101 i.types[this_operand].bitfield.byte = 1;
8102 }
9306ca4a 8103
a724f0f4
JB		 8104 else if (prev_token.code == T_WORD)
8105 {
8106 if (current_templates->start->name[0] == 'l'
8107 && current_templates->start->name[2] == 's'
8108 && current_templates->start->name[3] == 0)
8109 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8110 else if (intel_parser.got_a_float == 2) /* "fi..." */
8111 suffix = SHORT_MNEM_SUFFIX;
8112 else
8113 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8114 i.types[this_operand].bitfield.word = 1;
a724f0f4 8115 }
64a0c779 8116
a724f0f4
JB		 8117 else if (prev_token.code == T_DWORD)
8118 {
8119 if (current_templates->start->name[0] == 'l'
8120 && current_templates->start->name[2] == 's'
8121 && current_templates->start->name[3] == 0)
8122 suffix = WORD_MNEM_SUFFIX;
8123 else if (flag_code == CODE_16BIT
40fb9820
L		 8124 && (current_templates->start->opcode_modifier.jump
8125 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8126 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8127 else if (intel_parser.got_a_float == 1) /* "f..." */
8128 suffix = SHORT_MNEM_SUFFIX;
8129 else
8130 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8131 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8132 }
9306ca4a 8133
a724f0f4
JB		 8134 else if (prev_token.code == T_FWORD)
8135 {
8136 if (current_templates->start->name[0] == 'l'
8137 && current_templates->start->name[2] == 's'
8138 && current_templates->start->name[3] == 0)
8139 suffix = LONG_MNEM_SUFFIX;
8140 else if (!intel_parser.got_a_float)
8141 {
8142 if (flag_code == CODE_16BIT)
8143 add_prefix (DATA_PREFIX_OPCODE);
8144 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8145 }
8146 else
8147 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8148 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8149 }
64a0c779 8150
a724f0f4
JB		 8151 else if (prev_token.code == T_QWORD)
8152 {
8153 if (intel_parser.got_a_float == 1) /* "f..." */
8154 suffix = LONG_MNEM_SUFFIX;
8155 else
7d5e4556
L		 8156 suffix = QWORD_MNEM_SUFFIX;
8157 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8158 }
64a0c779 8159
a724f0f4
JB		 8160 else if (prev_token.code == T_TBYTE)
8161 {
8162 if (intel_parser.got_a_float == 1)
8163 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8164 else
8165 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8166 }
9306ca4a 8167
a724f0f4 8168 else if (prev_token.code == T_XMMWORD)
9306ca4a 8169 {
582d5edd 8170 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8171 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8172 }
64a0c779 8173
f16b83df 8174 else
a724f0f4
JB		 8175 {
8176 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8177 return 0;
8178 }
8179
7d5e4556
L		 8180 i.types[this_operand].bitfield.unspecified = 0;
8181
435acd52
JB		 8182 /* Operands for jump/call using 'ptr' notation denote absolute
8183 addresses. */
40fb9820
L		 8184 if (current_templates->start->opcode_modifier.jump
8185 || current_templates->start->opcode_modifier.jumpdword)
8186 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8187
a724f0f4
JB		 8188 if (current_templates->start->base_opcode == 0x8d /* lea */)
8189 ;
8190 else if (!i.suffix)
8191 i.suffix = suffix;
8192 else if (i.suffix != suffix)
8193 {
8194 as_bad (_("Conflicting operand modifiers"));
8195 return 0;
8196 }
64a0c779 8197
9306ca4a
JB		 8198 }
8199
a724f0f4
JB		 8200 /* e09' : e10 e09' */
8201 else if (cur_token.code == ':')
9306ca4a 8202 {
a724f0f4
JB		 8203 if (prev_token.code != T_REG)
8204 {
8205 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8206 segment/group identifier (which we don't have), using comma
8207 as the operand separator there is even less consistent, since
8208 there all branches only have a single operand. */
8209 if (this_operand != 0
8210 || intel_parser.in_offset
8211 || intel_parser.in_bracket
40fb9820
L		 8212 || (!current_templates->start->opcode_modifier.jump
8213 && !current_templates->start->opcode_modifier.jumpdword
8214 && !current_templates->start->opcode_modifier.jumpintersegment
8215 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8216 return intel_match_token (T_NIL);
8217 /* Remember the start of the 2nd operand and terminate 1st
8218 operand here.
8219 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8220 another expression), but it gets at least the simplest case
8221 (a plain number or symbol on the left side) right. */
8222 intel_parser.next_operand = intel_parser.op_string;
8223 *--intel_parser.op_string = '\0';
8224 return intel_match_token (':');
8225 }
9306ca4a 8226 }
64a0c779 8227
a724f0f4 8228 /* e09' Empty */
64a0c779 8229 else
a724f0f4 8230 break;
64a0c779 8231
a724f0f4
JB		 8232 intel_match_token (cur_token.code);
8233
8234 }
8235
8236 if (in_offset)
8237 {
8238 --intel_parser.in_offset;
8239 if (nregs < 0)
8240 nregs = ~nregs;
8241 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8242 {
a724f0f4 8243 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8244 return 0;
8245 }
a724f0f4
JB		 8246 intel_parser.op_modifier |= 1 << T_OFFSET;
8247 }
9306ca4a 8248
a724f0f4
JB		 8249 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8250 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8251 return 1;
8252}
64a0c779 8253
a724f0f4 8254static int
e3bb37b5 8255intel_bracket_expr (void)
a724f0f4
JB		 8256{
8257 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8258 const char *start = intel_parser.op_string;
8259 int len;
8260
8261 if (i.op[this_operand].regs)
8262 return intel_match_token (T_NIL);
8263
8264 intel_match_token ('[');
8265
8266 /* Mark as a memory operand only if it's not already known to be an
8267 offset expression. If it's an offset expression, we need to keep
8268 the brace in. */
8269 if (!intel_parser.in_offset)
8270 {
8271 ++intel_parser.in_bracket;
435acd52
JB		 8272
8273 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8274 if (current_templates->start->opcode_modifier.jump
8275 || current_templates->start->opcode_modifier.jumpdword)
8276 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8277
a724f0f4
JB		 8278 /* Unfortunately gas always diverged from MASM in a respect that can't
8279 be easily fixed without risking to break code sequences likely to be
8280 encountered (the testsuite even check for this): MASM doesn't consider
8281 an expression inside brackets unconditionally as a memory reference.
8282 When that is e.g. a constant, an offset expression, or the sum of the
8283 two, this is still taken as a constant load. gas, however, always
8284 treated these as memory references. As a compromise, we'll try to make
8285 offset expressions inside brackets work the MASM way (since that's
8286 less likely to be found in real world code), but make constants alone
8287 continue to work the traditional gas way. In either case, issue a
8288 warning. */
8289 intel_parser.op_modifier &= ~was_offset;
64a0c779 8290 }
a724f0f4 8291 else
64e74474 8292 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8293
8294 /* Add a '+' to the displacement string if necessary. */
8295 if (*intel_parser.disp != '\0'
8296 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8297 strcat (intel_parser.disp, "+");
64a0c779 8298
a724f0f4
JB		 8299 if (intel_expr ()
8300 && (len = intel_parser.op_string - start - 1,
8301 intel_match_token (']')))
64a0c779 8302 {
a724f0f4
JB		 8303 /* Preserve brackets when the operand is an offset expression. */
8304 if (intel_parser.in_offset)
8305 strcat (intel_parser.disp, "]");
8306 else
8307 {
8308 --intel_parser.in_bracket;
8309 if (i.base_reg || i.index_reg)
8310 intel_parser.is_mem = 1;
8311 if (!intel_parser.is_mem)
8312 {
8313 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8314 /* Defer the warning until all of the operand was parsed. */
8315 intel_parser.is_mem = -1;
8316 else if (!quiet_warnings)
4eed87de
AM		 8317 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8318 len, start, len, start);
a724f0f4
JB		 8319 }
8320 }
8321 intel_parser.op_modifier |= was_offset;
64a0c779 8322
a724f0f4 8323 return 1;
64a0c779 8324 }
a724f0f4 8325 return 0;
64a0c779
DN		 8326}
8327
8328/* e10 e11 e10'
8329
8330 e10' [ expr ] e10'
b77a7acd 8331 | Empty */
64a0c779 8332static int
e3bb37b5 8333intel_e10 (void)
64a0c779 8334{
a724f0f4
JB		 8335 if (!intel_e11 ())
8336 return 0;
64a0c779 8337
a724f0f4 8338 while (cur_token.code == '[')
64a0c779 8339 {
a724f0f4 8340 if (!intel_bracket_expr ())
21d6c4af 8341 return 0;
64a0c779
DN		 8342 }
8343
a724f0f4 8344 return 1;
64a0c779
DN		 8345}
8346
64a0c779 8347/* e11 ( expr )
b77a7acd 8348 | [ expr ]
64a0c779
DN		 8349 | BYTE
8350 | WORD
8351 | DWORD
9306ca4a 8352 | FWORD
64a0c779 8353 | QWORD
9306ca4a
JB		 8354 | TBYTE
8355 | OWORD
8356 | XMMWORD
4a1805b1 8357 | $
64a0c779
DN		 8358 | .
8359 | register
8360 | id
8361 | constant */
8362static int
e3bb37b5 8363intel_e11 (void)
64a0c779 8364{
a724f0f4 8365 switch (cur_token.code)
64a0c779 8366 {
a724f0f4
JB		 8367 /* e11 ( expr ) */
8368 case '(':
64a0c779
DN		 8369 intel_match_token ('(');
8370 strcat (intel_parser.disp, "(");
8371
8372 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8373 {
8374 strcat (intel_parser.disp, ")");
8375 return 1;
8376 }
a724f0f4 8377 return 0;
4a1805b1 8378
a724f0f4
JB		 8379 /* e11 [ expr ] */
8380 case '[':
a724f0f4 8381 return intel_bracket_expr ();
64a0c779 8382
a724f0f4
JB		 8383 /* e11 $
8384 | . */
8385 case '.':
64a0c779
DN		 8386 strcat (intel_parser.disp, cur_token.str);
8387 intel_match_token (cur_token.code);
21d6c4af
DN		 8388
8389 /* Mark as a memory operand only if it's not already known to be an
8390 offset expression. */
a724f0f4 8391 if (!intel_parser.in_offset)
21d6c4af 8392 intel_parser.is_mem = 1;
64a0c779
DN		 8393
8394 return 1;
64a0c779 8395
a724f0f4
JB		 8396 /* e11 register */
8397 case T_REG:
8398 {
8399 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8400
a724f0f4 8401 intel_match_token (T_REG);
64a0c779 8402
a724f0f4
JB		 8403 /* Check for segment change. */
8404 if (cur_token.code == ':')
8405 {
40fb9820
L		 8406 if (!reg->reg_type.bitfield.sreg2
8407 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8408 {
4eed87de
AM		 8409 as_bad (_("`%s' is not a valid segment register"),
8410 reg->reg_name);
a724f0f4
JB		 8411 return 0;
8412 }
8413 else if (i.seg[i.mem_operands])
8414 as_warn (_("Extra segment override ignored"));
8415 else
8416 {
8417 if (!intel_parser.in_offset)
8418 intel_parser.is_mem = 1;
8419 switch (reg->reg_num)
8420 {
8421 case 0:
8422 i.seg[i.mem_operands] = &es;
8423 break;
8424 case 1:
8425 i.seg[i.mem_operands] = &cs;
8426 break;
8427 case 2:
8428 i.seg[i.mem_operands] = &ss;
8429 break;
8430 case 3:
8431 i.seg[i.mem_operands] = &ds;
8432 break;
8433 case 4:
8434 i.seg[i.mem_operands] = &fs;
8435 break;
8436 case 5:
8437 i.seg[i.mem_operands] = &gs;
8438 break;
8439 }
8440 }
8441 }
64a0c779 8442
a724f0f4
JB		 8443 /* Not a segment register. Check for register scaling. */
8444 else if (cur_token.code == '*')
8445 {
8446 if (!intel_parser.in_bracket)
8447 {
8448 as_bad (_("Register scaling only allowed in memory operands"));
8449 return 0;
8450 }
64a0c779 8451
40fb9820 8452 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8453 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8454 else if (i.index_reg)
8455 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8456
a724f0f4
JB		 8457 /* What follows must be a valid scale. */
8458 intel_match_token ('*');
8459 i.index_reg = reg;
40fb9820 8460 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8461
a724f0f4
JB		 8462 /* Set the scale after setting the register (otherwise,
8463 i386_scale will complain) */
8464 if (cur_token.code == '+' || cur_token.code == '-')
8465 {
8466 char *str, sign = cur_token.code;
8467 intel_match_token (cur_token.code);
8468 if (cur_token.code != T_CONST)
8469 {
8470 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8471 cur_token.str);
8472 return 0;
8473 }
8474 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8475 strcpy (str + 1, cur_token.str);
8476 *str = sign;
8477 if (!i386_scale (str))
8478 return 0;
8479 free (str);
8480 }
8481 else if (!i386_scale (cur_token.str))
64a0c779 8482 return 0;
a724f0f4
JB		 8483 intel_match_token (cur_token.code);
8484 }
64a0c779 8485
a724f0f4
JB		 8486 /* No scaling. If this is a memory operand, the register is either a
8487 base register (first occurrence) or an index register (second
8488 occurrence). */
7b0441f6 8489 else if (intel_parser.in_bracket)
a724f0f4 8490 {
64a0c779 8491
a724f0f4
JB		 8492 if (!i.base_reg)
8493 i.base_reg = reg;
8494 else if (!i.index_reg)
8495 i.index_reg = reg;
8496 else
8497 {
8498 as_bad (_("Too many register references in memory operand"));
8499 return 0;
8500 }
64a0c779 8501
40fb9820 8502 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8503 }
4a1805b1 8504
4d1bb795
JB		 8505 /* It's neither base nor index. */
8506 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8507 {
40fb9820
L		 8508 i386_operand_type temp = reg->reg_type;
8509 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8510 i.types[this_operand] = operand_type_or (i.types[this_operand],
8511 temp);
7d5e4556 8512 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8513 i.op[this_operand].regs = reg;
8514 i.reg_operands++;
8515 }
8516 else
8517 {
8518 as_bad (_("Invalid use of register"));
8519 return 0;
8520 }
64a0c779 8521
a724f0f4
JB		 8522 /* Since registers are not part of the displacement string (except
8523 when we're parsing offset operands), we may need to remove any
8524 preceding '+' from the displacement string. */
8525 if (*intel_parser.disp != '\0'
8526 && !intel_parser.in_offset)
8527 {
8528 char *s = intel_parser.disp;
8529 s += strlen (s) - 1;
8530 if (*s == '+')
8531 *s = '\0';
8532 }
4a1805b1 8533
a724f0f4
JB		 8534 return 1;
8535 }
8536
8537 /* e11 BYTE
8538 | WORD
8539 | DWORD
8540 | FWORD
8541 | QWORD
8542 | TBYTE
8543 | OWORD
8544 | XMMWORD */
8545 case T_BYTE:
8546 case T_WORD:
8547 case T_DWORD:
8548 case T_FWORD:
8549 case T_QWORD:
8550 case T_TBYTE:
8551 case T_XMMWORD:
8552 intel_match_token (cur_token.code);
64a0c779 8553
a724f0f4
JB		 8554 if (cur_token.code == T_PTR)
8555 return 1;
8556
8557 /* It must have been an identifier. */
8558 intel_putback_token ();
8559 cur_token.code = T_ID;
8560 /* FALLTHRU */
8561
8562 /* e11 id
8563 | constant */
8564 case T_ID:
8565 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8566 {
8567 symbolS *symbolP;
8568
a724f0f4
JB		 8569 /* The identifier represents a memory reference only if it's not
8570 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8571 symbolP = symbol_find(cur_token.str);
8572 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8573 intel_parser.is_mem = 1;
8574 }
a724f0f4 8575 /* FALLTHRU */
64a0c779 8576
a724f0f4
JB		 8577 case T_CONST:
8578 case '-':
8579 case '+':
8580 {
8581 char *save_str, sign = 0;
64a0c779 8582
a724f0f4
JB		 8583 /* Allow constants that start with `+' or `-'. */
8584 if (cur_token.code == '-' || cur_token.code == '+')
8585 {
8586 sign = cur_token.code;
8587 intel_match_token (cur_token.code);
8588 if (cur_token.code != T_CONST)
8589 {
8590 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8591 cur_token.str);
8592 return 0;
8593 }
8594 }
64a0c779 8595
a724f0f4
JB		 8596 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8597 strcpy (save_str + !!sign, cur_token.str);
8598 if (sign)
8599 *save_str = sign;
64a0c779 8600
a724f0f4
JB		 8601 /* Get the next token to check for register scaling. */
8602 intel_match_token (cur_token.code);
64a0c779 8603
4eed87de
AM		 8604 /* Check if this constant is a scaling factor for an
8605 index register. */
a724f0f4
JB		 8606 if (cur_token.code == '*')
8607 {
8608 if (intel_match_token ('*') && cur_token.code == T_REG)
8609 {
8610 const reg_entry *reg = cur_token.reg;
8611
8612 if (!intel_parser.in_bracket)
8613 {
4eed87de
AM		 8614 as_bad (_("Register scaling only allowed "
8615 "in memory operands"));
a724f0f4
JB		 8616 return 0;
8617 }
8618
4eed87de
AM		 8619 /* Disallow things like [1*si].
8620 sp and esp are invalid as index. */
40fb9820 8621 if (reg->reg_type.bitfield.reg16)
4eed87de 8622 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8623 else if (i.index_reg)
4eed87de 8624 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8625
8626 /* The constant is followed by `* reg', so it must be
8627 a valid scale. */
8628 i.index_reg = reg;
40fb9820 8629 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8630
8631 /* Set the scale after setting the register (otherwise,
8632 i386_scale will complain) */
8633 if (!i386_scale (save_str))
64a0c779 8634 return 0;
a724f0f4
JB		 8635 intel_match_token (T_REG);
8636
8637 /* Since registers are not part of the displacement
8638 string, we may need to remove any preceding '+' from
8639 the displacement string. */
8640 if (*intel_parser.disp != '\0')
8641 {
8642 char *s = intel_parser.disp;
8643 s += strlen (s) - 1;
8644 if (*s == '+')
8645 *s = '\0';
8646 }
8647
8648 free (save_str);
8649
8650 return 1;
8651 }
64a0c779 8652
a724f0f4
JB		 8653 /* The constant was not used for register scaling. Since we have
8654 already consumed the token following `*' we now need to put it
8655 back in the stream. */
64a0c779 8656 intel_putback_token ();
a724f0f4 8657 }
64a0c779 8658
a724f0f4
JB		 8659 /* Add the constant to the displacement string. */
8660 strcat (intel_parser.disp, save_str);
8661 free (save_str);
64a0c779 8662
a724f0f4
JB		 8663 return 1;
8664 }
64a0c779
DN		 8665 }
8666
64a0c779
DN		 8667 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8668 return 0;
8669}
8670
64a0c779
DN		 8671/* Match the given token against cur_token. If they match, read the next
8672 token from the operand string. */
8673static int
e3bb37b5 8674intel_match_token (int code)
64a0c779
DN		 8675{
8676 if (cur_token.code == code)
8677 {
8678 intel_get_token ();
8679 return 1;
8680 }
8681 else
8682 {
0477af35 8683 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8684 return 0;
8685 }
8686}
8687
64a0c779
DN		 8688/* Read a new token from intel_parser.op_string and store it in cur_token. */
8689static void
e3bb37b5 8690intel_get_token (void)
64a0c779
DN		 8691{
8692 char *end_op;
8693 const reg_entry *reg;
8694 struct intel_token new_token;
8695
8696 new_token.code = T_NIL;
8697 new_token.reg = NULL;
8698 new_token.str = NULL;
8699
4a1805b1 8700 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8701 cur_token to prev_token. */
8702 if (prev_token.str)
8703 free (prev_token.str);
8704
8705 prev_token = cur_token;
8706
8707 /* Skip whitespace. */
8708 while (is_space_char (*intel_parser.op_string))
8709 intel_parser.op_string++;
8710
8711 /* Return an empty token if we find nothing else on the line. */
8712 if (*intel_parser.op_string == '\0')
8713 {
8714 cur_token = new_token;
8715 return;
8716 }
8717
8718 /* The new token cannot be larger than the remainder of the operand
8719 string. */
a724f0f4 8720 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8721 new_token.str[0] = '\0';
8722
8723 if (strchr ("0123456789", *intel_parser.op_string))
8724 {
8725 char *p = new_token.str;
8726 char *q = intel_parser.op_string;
8727 new_token.code = T_CONST;
8728
8729 /* Allow any kind of identifier char to encompass floating point and
8730 hexadecimal numbers. */
8731 while (is_identifier_char (*q))
8732 *p++ = *q++;
8733 *p = '\0';
8734
8735 /* Recognize special symbol names [0-9][bf]. */
8736 if (strlen (intel_parser.op_string) == 2
4a1805b1 8737 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8738 || intel_parser.op_string[1] == 'f'))
8739 new_token.code = T_ID;
8740 }
8741
4d1bb795 8742 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8743 {
4d1bb795
JB		 8744 size_t len = end_op - intel_parser.op_string;
8745
64a0c779
DN		 8746 new_token.code = T_REG;
8747 new_token.reg = reg;
8748
4d1bb795
JB		 8749 memcpy (new_token.str, intel_parser.op_string, len);
8750 new_token.str[len] = '\0';
64a0c779
DN		 8751 }
8752
8753 else if (is_identifier_char (*intel_parser.op_string))
8754 {
8755 char *p = new_token.str;
8756 char *q = intel_parser.op_string;
8757
8758 /* A '.' or '$' followed by an identifier char is an identifier.
8759 Otherwise, it's operator '.' followed by an expression. */
8760 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8761 {
9306ca4a
JB		 8762 new_token.code = '.';
8763 new_token.str[0] = '.';
64a0c779
DN		 8764 new_token.str[1] = '\0';
8765 }
8766 else
8767 {
8768 while (is_identifier_char (*q) || *q == '@')
8769 *p++ = *q++;
8770 *p = '\0';
8771
9306ca4a
JB		 8772 if (strcasecmp (new_token.str, "NOT") == 0)
8773 new_token.code = '~';
8774
8775 else if (strcasecmp (new_token.str, "MOD") == 0)
8776 new_token.code = '%';
8777
8778 else if (strcasecmp (new_token.str, "AND") == 0)
8779 new_token.code = '&';
8780
8781 else if (strcasecmp (new_token.str, "OR") == 0)
8782 new_token.code = '|';
8783
8784 else if (strcasecmp (new_token.str, "XOR") == 0)
8785 new_token.code = '^';
8786
8787 else if (strcasecmp (new_token.str, "SHL") == 0)
8788 new_token.code = T_SHL;
8789
8790 else if (strcasecmp (new_token.str, "SHR") == 0)
8791 new_token.code = T_SHR;
8792
8793 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8794 new_token.code = T_BYTE;
8795
8796 else if (strcasecmp (new_token.str, "WORD") == 0)
8797 new_token.code = T_WORD;
8798
8799 else if (strcasecmp (new_token.str, "DWORD") == 0)
8800 new_token.code = T_DWORD;
8801
9306ca4a
JB		 8802 else if (strcasecmp (new_token.str, "FWORD") == 0)
8803 new_token.code = T_FWORD;
8804
64a0c779
DN		 8805 else if (strcasecmp (new_token.str, "QWORD") == 0)
8806 new_token.code = T_QWORD;
8807
9306ca4a
JB		 8808 else if (strcasecmp (new_token.str, "TBYTE") == 0
8809 /* XXX remove (gcc still uses it) */
8810 || strcasecmp (new_token.str, "XWORD") == 0)
8811 new_token.code = T_TBYTE;
8812
8813 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8814 || strcasecmp (new_token.str, "OWORD") == 0)
8815 new_token.code = T_XMMWORD;
64a0c779
DN		 8816
8817 else if (strcasecmp (new_token.str, "PTR") == 0)
8818 new_token.code = T_PTR;
8819
8820 else if (strcasecmp (new_token.str, "SHORT") == 0)
8821 new_token.code = T_SHORT;
8822
8823 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8824 {
8825 new_token.code = T_OFFSET;
8826
8827 /* ??? This is not mentioned in the MASM grammar but gcc
8828 makes use of it with -mintel-syntax. OFFSET may be
8829 followed by FLAT: */
8830 if (strncasecmp (q, " FLAT:", 6) == 0)
8831 strcat (new_token.str, " FLAT:");
8832 }
8833
8834 /* ??? This is not mentioned in the MASM grammar. */
8835 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8836 {
8837 new_token.code = T_OFFSET;
8838 if (*q == ':')
8839 strcat (new_token.str, ":");
8840 else
8841 as_bad (_("`:' expected"));
8842 }
64a0c779
DN		 8843
8844 else
8845 new_token.code = T_ID;
8846 }
8847 }
8848
9306ca4a
JB		 8849 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8850 {
8851 new_token.code = *intel_parser.op_string;
8852 new_token.str[0] = *intel_parser.op_string;
8853 new_token.str[1] = '\0';
8854 }
8855
8856 else if (strchr ("<>", *intel_parser.op_string)
8857 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8858 {
8859 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8860 new_token.str[0] = *intel_parser.op_string;
8861 new_token.str[1] = *intel_parser.op_string;
8862 new_token.str[2] = '\0';
8863 }
8864
64a0c779 8865 else
0477af35 8866 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8867
8868 intel_parser.op_string += strlen (new_token.str);
8869 cur_token = new_token;
8870}
8871
64a0c779
DN		 8872/* Put cur_token back into the token stream and make cur_token point to
8873 prev_token. */
8874static void
e3bb37b5 8875intel_putback_token (void)
64a0c779 8876{
a724f0f4
JB		 8877 if (cur_token.code != T_NIL)
8878 {
8879 intel_parser.op_string -= strlen (cur_token.str);
8880 free (cur_token.str);
8881 }
64a0c779 8882 cur_token = prev_token;
4a1805b1 8883
64a0c779
DN		 8884 /* Forget prev_token. */
8885 prev_token.code = T_NIL;
8886 prev_token.reg = NULL;
8887 prev_token.str = NULL;
8888}
54cfded0 8889
a4447b93 8890int
1df69f4f 8891tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8892{
8893 unsigned int regnum;
8894 unsigned int regnames_count;
089dfecd 8895 static const char *const regnames_32[] =
54cfded0 8896 {
a4447b93
RH		 8897 "eax", "ecx", "edx", "ebx",
8898 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8899 "eip", "eflags", NULL,
8900 "st0", "st1", "st2", "st3",
8901 "st4", "st5", "st6", "st7",
8902 NULL, NULL,
8903 "xmm0", "xmm1", "xmm2", "xmm3",
8904 "xmm4", "xmm5", "xmm6", "xmm7",
8905 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8906 "mm4", "mm5", "mm6", "mm7",
8907 "fcw", "fsw", "mxcsr",
8908 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8909 "tr", "ldtr"
54cfded0 8910 };
089dfecd 8911 static const char *const regnames_64[] =
54cfded0 8912 {
089dfecd
JB		 8913 "rax", "rdx", "rcx", "rbx",
8914 "rsi", "rdi", "rbp", "rsp",
8915 "r8", "r9", "r10", "r11",
54cfded0 8916 "r12", "r13", "r14", "r15",
089dfecd
JB		 8917 "rip",
8918 "xmm0", "xmm1", "xmm2", "xmm3",
8919 "xmm4", "xmm5", "xmm6", "xmm7",
8920 "xmm8", "xmm9", "xmm10", "xmm11",
8921 "xmm12", "xmm13", "xmm14", "xmm15",
8922 "st0", "st1", "st2", "st3",
8923 "st4", "st5", "st6", "st7",
8924 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8925 "mm4", "mm5", "mm6", "mm7",
8926 "rflags",
8927 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8928 "fs.base", "gs.base", NULL, NULL,
8929 "tr", "ldtr",
8930 "mxcsr", "fcw", "fsw"
54cfded0 8931 };
089dfecd 8932 const char *const *regnames;
54cfded0
AM		 8933
8934 if (flag_code == CODE_64BIT)
8935 {
8936 regnames = regnames_64;
0cea6190 8937 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8938 }
8939 else
8940 {
8941 regnames = regnames_32;
0cea6190 8942 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8943 }
8944
8945 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8946 if (regnames[regnum] != NULL
8947 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8948 return regnum;
8949
54cfded0
AM		 8950 return -1;
8951}
8952
8953void
8954tc_x86_frame_initial_instructions (void)
8955{
a4447b93
RH		 8956 static unsigned int sp_regno;
8957
8958 if (!sp_regno)
8959 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8960 ? "rsp" : "esp");
8961
8962 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8963 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8964}
d2b2c203
DJ		 8965
8966int
8967i386_elf_section_type (const char *str, size_t len)
8968{
8969 if (flag_code == CODE_64BIT
8970 && len == sizeof ("unwind") - 1
8971 && strncmp (str, "unwind", 6) == 0)
8972 return SHT_X86_64_UNWIND;
8973
8974 return -1;
8975}
bb41ade5
AM		 8976
8977#ifdef TE_PE
8978void
8979tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8980{
8981 expressionS expr;
8982
8983 expr.X_op = O_secrel;
8984 expr.X_add_symbol = symbol;
8985 expr.X_add_number = 0;
8986 emit_expr (&expr, size);
8987}
8988#endif
3b22753a
L		 8989
8990#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8991/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8992
8993int
8994x86_64_section_letter (int letter, char **ptr_msg)
8995{
8996 if (flag_code == CODE_64BIT)
8997 {
8998 if (letter == 'l')
8999 return SHF_X86_64_LARGE;
9000
9001 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9002 }
3b22753a 9003 else
64e74474 9004 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9005 return -1;
9006}
9007
9008int
9009x86_64_section_word (char *str, size_t len)
9010{
8620418b 9011 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9012 return SHF_X86_64_LARGE;
9013
9014 return -1;
9015}
9016
9017static void
9018handle_large_common (int small ATTRIBUTE_UNUSED)
9019{
9020 if (flag_code != CODE_64BIT)
9021 {
9022 s_comm_internal (0, elf_common_parse);
9023 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9024 }
9025 else
9026 {
9027 static segT lbss_section;
9028 asection *saved_com_section_ptr = elf_com_section_ptr;
9029 asection *saved_bss_section = bss_section;
9030
9031 if (lbss_section == NULL)
9032 {
9033 flagword applicable;
9034 segT seg = now_seg;
9035 subsegT subseg = now_subseg;
9036
9037 /* The .lbss section is for local .largecomm symbols. */
9038 lbss_section = subseg_new (".lbss", 0);
9039 applicable = bfd_applicable_section_flags (stdoutput);
9040 bfd_set_section_flags (stdoutput, lbss_section,
9041 applicable & SEC_ALLOC);
9042 seg_info (lbss_section)->bss = 1;
9043
9044 subseg_set (seg, subseg);
9045 }
9046
9047 elf_com_section_ptr = &_bfd_elf_large_com_section;
9048 bss_section = lbss_section;
9049
9050 s_comm_internal (0, elf_common_parse);
9051
9052 elf_com_section_ptr = saved_com_section_ptr;
9053 bss_section = saved_bss_section;
9054 }
9055}
9056#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
A mirror of the official binutils-gdb repository