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[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
86fa6981
L		 357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
891edac4 364
a501d77e
L		 365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
f8a5c266 372
86fa6981
L		 373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
d5de92cf
L		 382 /* REP prefix. */
383 const char *rep_prefix;
384
165de32a
L		 385 /* HLE prefix. */
386 const char *hle_prefix;
42164a71 387
7e8b059b
L		 388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
04ef582a
L		 391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
891edac4 394 /* Error message. */
a65babc9 395 enum i386_error error;
252b5132
RH		 396 };
397
398typedef struct _i386_insn i386_insn;
399
43234a1e
L		 400/* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402struct RC_name
403{
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407};
408
409static const struct RC_name RC_NamesTable[] =
410{
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416};
417
252b5132
RH		 418/* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 420const char extra_symbol_chars[] = "*%-([{}"
252b5132 421#ifdef LEX_AT
32137342
NC		 422 "@"
423#endif
424#ifdef LEX_QM
425 "?"
252b5132 426#endif
32137342 427 ;
252b5132 428
29b0f896
AM		 429#if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 431 && !defined (TE_GNU) \
29b0f896 432 && !defined (TE_LINUX) \
8d63c93e
RM		 433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
5209009a 563/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 564static int old_gcc = OLDGCC_COMPAT;
565
a60de03c
JB		 566/* 1 if pseudo registers are permitted. */
567static int allow_pseudo_reg = 0;
568
47926f60
KH		 569/* 1 if register prefix % not required. */
570static int allow_naked_reg = 0;
252b5132 571
33eaf5de 572/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575static int add_bnd_prefix = 0;
576
ba104c83 577/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 578static int allow_index_reg = 0;
579
d022bddd
IT		 580/* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582static int omit_lock_prefix = 0;
583
e4e00185
AS		 584/* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586static int avoid_fence = 0;
587
0cb4071e
L		 588/* 1 if the assembler should generate relax relocations. */
589
590static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
7bab8ab5 593static enum check_kind
daf50ae7 594 {
7bab8ab5
JB		 595 check_none = 0,
596 check_warning,
597 check_error
daf50ae7 598 }
7bab8ab5 599sse_check, operand_check = check_warning;
daf50ae7 600
2ca3ace5
L		 601/* Register prefix used for error message. */
602static const char *register_prefix = "%";
603
47926f60
KH		 604/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607static char stackop_size = '\0';
eecb386c 608
12b55ccc
L		 609/* Non-zero to optimize code alignment. */
610int optimize_align_code = 1;
611
47926f60
KH		 612/* Non-zero to quieten some warnings. */
613static int quiet_warnings = 0;
a38cf1db 614
47926f60
KH		 615/* CPU name. */
616static const char *cpu_arch_name = NULL;
6305a203 617static char *cpu_sub_arch_name = NULL;
a38cf1db 618
47926f60 619/* CPU feature flags. */
40fb9820
L		 620static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
ccc9c027
L		 622/* If we have selected a cpu we are generating instructions for. */
623static int cpu_arch_tune_set = 0;
624
9103f4f4 625/* Cpu we are generating instructions for. */
fbf3f584 626enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 627
628/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 629static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 630
ccc9c027 631/* CPU instruction set architecture used. */
fbf3f584 632enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 633
9103f4f4 634/* CPU feature flags of instruction set architecture used. */
fbf3f584 635i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 636
fddf5b5b
AM		 637/* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639static unsigned int no_cond_jump_promotion = 0;
640
c0f3af97
L		 641/* Encode SSE instructions with VEX prefix. */
642static unsigned int sse2avx;
643
539f890d
L		 644/* Encode scalar AVX instructions with specific vector length. */
645static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
43234a1e
L		 651/* Encode scalar EVEX LIG instructions with specific vector length. */
652static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659/* Encode EVEX WIG instructions with specific evex.w. */
660static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
d3d3c6db
IT		 666/* Value to encode in EVEX RC bits, for SAE-only instructions. */
667static enum rc_type evexrcig = rne;
668
29b0f896 669/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 670static symbolS *GOT_symbol;
29b0f896 671
a4447b93
RH		 672/* The dwarf2 return column, adjusted for 32 or 64 bit. */
673unsigned int x86_dwarf2_return_column;
674
675/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676int x86_cie_data_alignment;
677
252b5132 678/* Interface to relax_segment.
fddf5b5b
AM		 679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
252b5132 682
47926f60 683/* Types. */
93c2a809
AM		 684#define UNCOND_JUMP 0
685#define COND_JUMP 1
686#define COND_JUMP86 2
fddf5b5b 687
47926f60 688/* Sizes. */
252b5132
RH		 689#define CODE16 1
690#define SMALL 0
29b0f896 691#define SMALL16 (SMALL | CODE16)
252b5132 692#define BIG 2
29b0f896 693#define BIG16 (BIG | CODE16)
252b5132
RH		 694
695#ifndef INLINE
696#ifdef __GNUC__
697#define INLINE __inline__
698#else
699#define INLINE
700#endif
701#endif
702
fddf5b5b
AM		 703#define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705#define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707#define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 709
710/* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718const relax_typeS md_relax_table[] =
719{
24eab124
AM		 720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
93c2a809 723 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 724 4) which index into the table to try if we can't fit into this one. */
252b5132 725
fddf5b5b 726 /* UNCOND_JUMP states. */
93c2a809
AM		 727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
252b5132 731 {0, 0, 4, 0},
93c2a809
AM		 732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 734 {0, 0, 2, 0},
735
93c2a809
AM		 736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
fddf5b5b 742 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
252b5132
RH		 755};
756
9103f4f4
L		 757static const arch_entry cpu_arch[] =
758{
89507696
JB		 759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
8a2c8fef 761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 762 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 764 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 766 CPU_NONE_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 768 CPU_I186_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 770 CPU_I286_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 772 CPU_I386_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 774 CPU_I486_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 776 CPU_I586_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 778 CPU_I686_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 780 CPU_I586_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 782 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 784 CPU_P2_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 786 CPU_P3_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 788 CPU_P4_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 790 CPU_CORE_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 792 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 794 CPU_CORE_FLAGS, 1 },
8a2c8fef 795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 796 CPU_CORE_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 798 CPU_CORE2_FLAGS, 1 },
8a2c8fef 799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 800 CPU_CORE2_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 802 CPU_COREI7_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 804 CPU_L1OM_FLAGS, 0 },
7a9068fe 805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 806 CPU_K1OM_FLAGS, 0 },
81486035 807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 808 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 810 CPU_K6_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 812 CPU_K6_2_FLAGS, 0 },
8a2c8fef 813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 814 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 816 CPU_K8_FLAGS, 1 },
8a2c8fef 817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 818 CPU_K8_FLAGS, 0 },
8a2c8fef 819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 820 CPU_K8_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 822 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 824 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 826 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 828 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 830 CPU_BDVER4_FLAGS, 0 },
029f3522 831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 832 CPU_ZNVER1_FLAGS, 0 },
7b458c12 833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 834 CPU_BTVER1_FLAGS, 0 },
7b458c12 835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 836 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_8087_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_287_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_387_FLAGS, 0 },
1848e567
L		 843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_MMX_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_SSE_FLAGS, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_SSE2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_SSE3_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX_FLAGS, 0 },
6c30d220 863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX2_FLAGS, 0 },
43234a1e 865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_AVX512F_FLAGS, 0 },
43234a1e 867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_AVX512CD_FLAGS, 0 },
43234a1e 869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_AVX512ER_FLAGS, 0 },
43234a1e 871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_VMX_FLAGS, 0 },
8729a6f6 881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_SMX_FLAGS, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_AES_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_F16C_FLAGS, 0 },
6c30d220 905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_BMI2_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_FMA_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_FMA4_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_XOP_FLAGS, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_LWP_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_MOVBE_FLAGS, 0 },
60aa667e 917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_CX16_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_EPT_FLAGS, 0 },
6c30d220 921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_LZCNT_FLAGS, 0 },
42164a71 923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_HLE_FLAGS, 0 },
42164a71 925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_RTM_FLAGS, 0 },
6c30d220 927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_CLFLUSH_FLAGS, 0 },
22109423 931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_NOP_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_SVME_FLAGS, 1 },
8a2c8fef 945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_SVME_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_ABM_FLAGS, 0 },
87973e9f 951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_BMI_FLAGS, 0 },
2a2a0f38 953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_TBM_FLAGS, 0 },
e2e1fcde 955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_ADX_FLAGS, 0 },
e2e1fcde 957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_PRFCHW_FLAGS, 0 },
5c111e37 961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SMAP_FLAGS, 0 },
7e8b059b 963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_MPX_FLAGS, 0 },
a0046408 965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_SHA_FLAGS, 0 },
963f3586 967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_SE1_FLAGS, 0 },
c5e7287a 973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
986 CPU_AVX512_VBMI2_FLAGS, 0 },
029f3522 987 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_CLZERO_FLAGS, 0 },
9916071f 989 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_MWAITX_FLAGS, 0 },
8eab4136 991 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_OSPKE_FLAGS, 0 },
8bc52696 993 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 994 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 995 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
996 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 997 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
998 CPU_CET_FLAGS, 0 },
48521003
IT		 999 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1000 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1001 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1002 CPU_VAES_FLAGS, 0 },
293f5f65
L		 1003};
1004
1005static const noarch_entry cpu_noarch[] =
1006{
1007 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1008 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1009 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1010 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1011 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1012 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1013 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1014 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1015 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1016 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1017 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1018 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1019 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1020 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1021 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1022 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1023 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1024 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1025 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1026 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1030 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1031 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1032 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1033 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
e413e4e9
AM		 1034};
1035
704209c0 1036#ifdef I386COFF
a6c24e68
NC		 1037/* Like s_lcomm_internal in gas/read.c but the alignment string
1038 is allowed to be optional. */
1039
1040static symbolS *
1041pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1042{
1043 addressT align = 0;
1044
1045 SKIP_WHITESPACE ();
1046
7ab9ffdd 1047 if (needs_align
a6c24e68
NC		 1048 && *input_line_pointer == ',')
1049 {
1050 align = parse_align (needs_align - 1);
7ab9ffdd 1051
a6c24e68
NC		 1052 if (align == (addressT) -1)
1053 return NULL;
1054 }
1055 else
1056 {
1057 if (size >= 8)
1058 align = 3;
1059 else if (size >= 4)
1060 align = 2;
1061 else if (size >= 2)
1062 align = 1;
1063 else
1064 align = 0;
1065 }
1066
1067 bss_alloc (symbolP, size, align);
1068 return symbolP;
1069}
1070
704209c0 1071static void
a6c24e68
NC		 1072pe_lcomm (int needs_align)
1073{
1074 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1075}
704209c0 1076#endif
a6c24e68 1077
29b0f896
AM		 1078const pseudo_typeS md_pseudo_table[] =
1079{
1080#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1081 {"align", s_align_bytes, 0},
1082#else
1083 {"align", s_align_ptwo, 0},
1084#endif
1085 {"arch", set_cpu_arch, 0},
1086#ifndef I386COFF
1087 {"bss", s_bss, 0},
a6c24e68
NC		 1088#else
1089 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1090#endif
1091 {"ffloat", float_cons, 'f'},
1092 {"dfloat", float_cons, 'd'},
1093 {"tfloat", float_cons, 'x'},
1094 {"value", cons, 2},
d182319b 1095 {"slong", signed_cons, 4},
29b0f896
AM		 1096 {"noopt", s_ignore, 0},
1097 {"optim", s_ignore, 0},
1098 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1099 {"code16", set_code_flag, CODE_16BIT},
1100 {"code32", set_code_flag, CODE_32BIT},
1101 {"code64", set_code_flag, CODE_64BIT},
1102 {"intel_syntax", set_intel_syntax, 1},
1103 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1104 {"intel_mnemonic", set_intel_mnemonic, 1},
1105 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1106 {"allow_index_reg", set_allow_index_reg, 1},
1107 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1108 {"sse_check", set_check, 0},
1109 {"operand_check", set_check, 1},
3b22753a
L		 1110#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1111 {"largecomm", handle_large_common, 0},
07a53e5c 1112#else
e3bb37b5 1113 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1114 {"loc", dwarf2_directive_loc, 0},
1115 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1116#endif
6482c264
NC		 1117#ifdef TE_PE
1118 {"secrel32", pe_directive_secrel, 0},
1119#endif
29b0f896
AM		 1120 {0, 0, 0}
1121};
1122
1123/* For interface with expression (). */
1124extern char *input_line_pointer;
1125
1126/* Hash table for instruction mnemonic lookup. */
1127static struct hash_control *op_hash;
1128
1129/* Hash table for register lookup. */
1130static struct hash_control *reg_hash;
1131\f
252b5132 1132void
e3bb37b5 1133i386_align_code (fragS *fragP, int count)
252b5132 1134{
ce8a8b2f
AM		 1135 /* Various efficient no-op patterns for aligning code labels.
1136 Note: Don't try to assemble the instructions in the comments.
1137 0L and 0w are not legal. */
bad6e36d 1138 static const unsigned char f32_1[] =
252b5132 1139 {0x90}; /* nop */
bad6e36d 1140 static const unsigned char f32_2[] =
ccc9c027 1141 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1142 static const unsigned char f32_3[] =
252b5132 1143 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1144 static const unsigned char f32_4[] =
252b5132 1145 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1146 static const unsigned char f32_5[] =
252b5132
RH		 1147 {0x90, /* nop */
1148 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1149 static const unsigned char f32_6[] =
252b5132 1150 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1151 static const unsigned char f32_7[] =
252b5132 1152 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1153 static const unsigned char f32_8[] =
252b5132
RH		 1154 {0x90, /* nop */
1155 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1156 static const unsigned char f32_9[] =
252b5132
RH		 1157 {0x89,0xf6, /* movl %esi,%esi */
1158 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1159 static const unsigned char f32_10[] =
252b5132
RH		 1160 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1161 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1162 static const unsigned char f32_11[] =
252b5132
RH		 1163 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1164 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1165 static const unsigned char f32_12[] =
252b5132
RH		 1166 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1167 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1168 static const unsigned char f32_13[] =
252b5132
RH		 1169 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1170 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1171 static const unsigned char f32_14[] =
252b5132
RH		 1172 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1173 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1174 static const unsigned char f16_3[] =
c3332e24 1175 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1176 static const unsigned char f16_4[] =
252b5132 1177 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1178 static const unsigned char f16_5[] =
252b5132
RH		 1179 {0x90, /* nop */
1180 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1181 static const unsigned char f16_6[] =
252b5132
RH		 1182 {0x89,0xf6, /* mov %si,%si */
1183 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1184 static const unsigned char f16_7[] =
252b5132
RH		 1185 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1186 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1187 static const unsigned char f16_8[] =
252b5132
RH		 1188 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1189 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1190 static const unsigned char jump_31[] =
76bc74dc
L		 1191 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1192 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1193 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1194 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1195 static const unsigned char *const f32_patt[] = {
252b5132 1196 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1197 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1198 };
bad6e36d 1199 static const unsigned char *const f16_patt[] = {
76bc74dc 1200 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1201 };
ccc9c027 1202 /* nopl (%[re]ax) */
bad6e36d 1203 static const unsigned char alt_3[] =
ccc9c027
L		 1204 {0x0f,0x1f,0x00};
1205 /* nopl 0(%[re]ax) */
bad6e36d 1206 static const unsigned char alt_4[] =
ccc9c027
L		 1207 {0x0f,0x1f,0x40,0x00};
1208 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1209 static const unsigned char alt_5[] =
ccc9c027
L		 1210 {0x0f,0x1f,0x44,0x00,0x00};
1211 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1212 static const unsigned char alt_6[] =
ccc9c027
L		 1213 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1214 /* nopl 0L(%[re]ax) */
bad6e36d 1215 static const unsigned char alt_7[] =
ccc9c027
L		 1216 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1217 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1218 static const unsigned char alt_8[] =
ccc9c027
L		 1219 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1220 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1221 static const unsigned char alt_9[] =
ccc9c027
L		 1222 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1223 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1224 static const unsigned char alt_10[] =
ccc9c027 1225 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1226 static const unsigned char *const alt_patt[] = {
ccc9c027 1227 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1228 alt_9, alt_10
ccc9c027 1229 };
252b5132 1230
76bc74dc
L		 1231 /* Only align for at least a positive non-zero boundary. */
1232 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1233 return;
3e73aa7c 1234
ccc9c027
L		 1235 /* We need to decide which NOP sequence to use for 32bit and
1236 64bit. When -mtune= is used:
4eed87de 1237
76bc74dc
L		 1238 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1239 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1240 2. For the rest, alt_patt will be used.
1241
1242 When -mtune= isn't used, alt_patt will be used if
22109423 1243 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1244 be used.
ccc9c027
L		 1245
1246 When -march= or .arch is used, we can't use anything beyond
1247 cpu_arch_isa_flags. */
1248
1249 if (flag_code == CODE_16BIT)
1250 {
ccc9c027 1251 if (count > 8)
33fef721 1252 {
76bc74dc
L		 1253 memcpy (fragP->fr_literal + fragP->fr_fix,
1254 jump_31, count);
1255 /* Adjust jump offset. */
1256 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1257 }
76bc74dc
L		 1258 else
1259 memcpy (fragP->fr_literal + fragP->fr_fix,
1260 f16_patt[count - 1], count);
252b5132 1261 }
33fef721 1262 else
ccc9c027 1263 {
bad6e36d 1264 const unsigned char *const *patt = NULL;
ccc9c027 1265
fbf3f584 1266 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1267 {
1268 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1269 switch (cpu_arch_tune)
1270 {
1271 case PROCESSOR_UNKNOWN:
1272 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1273 optimize with nops. */
1274 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1275 patt = alt_patt;
ccc9c027
L		 1276 else
1277 patt = f32_patt;
1278 break;
ccc9c027
L		 1279 case PROCESSOR_PENTIUM4:
1280 case PROCESSOR_NOCONA:
ef05d495 1281 case PROCESSOR_CORE:
76bc74dc 1282 case PROCESSOR_CORE2:
bd5295b2 1283 case PROCESSOR_COREI7:
3632d14b 1284 case PROCESSOR_L1OM:
7a9068fe 1285 case PROCESSOR_K1OM:
76bc74dc 1286 case PROCESSOR_GENERIC64:
ccc9c027
L		 1287 case PROCESSOR_K6:
1288 case PROCESSOR_ATHLON:
1289 case PROCESSOR_K8:
4eed87de 1290 case PROCESSOR_AMDFAM10:
8aedb9fe 1291 case PROCESSOR_BD:
029f3522 1292 case PROCESSOR_ZNVER:
7b458c12 1293 case PROCESSOR_BT:
80b8656c 1294 patt = alt_patt;
ccc9c027 1295 break;
76bc74dc 1296 case PROCESSOR_I386:
ccc9c027
L		 1297 case PROCESSOR_I486:
1298 case PROCESSOR_PENTIUM:
2dde1948 1299 case PROCESSOR_PENTIUMPRO:
81486035 1300 case PROCESSOR_IAMCU:
ccc9c027
L		 1301 case PROCESSOR_GENERIC32:
1302 patt = f32_patt;
1303 break;
4eed87de 1304 }
ccc9c027
L		 1305 }
1306 else
1307 {
fbf3f584 1308 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1309 {
1310 case PROCESSOR_UNKNOWN:
e6a14101 1311 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1312 PROCESSOR_UNKNOWN. */
1313 abort ();
1314 break;
1315
76bc74dc 1316 case PROCESSOR_I386:
ccc9c027
L		 1317 case PROCESSOR_I486:
1318 case PROCESSOR_PENTIUM:
81486035 1319 case PROCESSOR_IAMCU:
ccc9c027
L		 1320 case PROCESSOR_K6:
1321 case PROCESSOR_ATHLON:
1322 case PROCESSOR_K8:
4eed87de 1323 case PROCESSOR_AMDFAM10:
8aedb9fe 1324 case PROCESSOR_BD:
029f3522 1325 case PROCESSOR_ZNVER:
7b458c12 1326 case PROCESSOR_BT:
ccc9c027
L		 1327 case PROCESSOR_GENERIC32:
1328 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1329 with nops. */
1330 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1331 patt = alt_patt;
ccc9c027
L		 1332 else
1333 patt = f32_patt;
1334 break;
76bc74dc
L		 1335 case PROCESSOR_PENTIUMPRO:
1336 case PROCESSOR_PENTIUM4:
1337 case PROCESSOR_NOCONA:
1338 case PROCESSOR_CORE:
ef05d495 1339 case PROCESSOR_CORE2:
bd5295b2 1340 case PROCESSOR_COREI7:
3632d14b 1341 case PROCESSOR_L1OM:
7a9068fe 1342 case PROCESSOR_K1OM:
22109423 1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1344 patt = alt_patt;
ccc9c027
L		 1345 else
1346 patt = f32_patt;
1347 break;
1348 case PROCESSOR_GENERIC64:
80b8656c 1349 patt = alt_patt;
ccc9c027 1350 break;
4eed87de 1351 }
ccc9c027
L		 1352 }
1353
76bc74dc
L		 1354 if (patt == f32_patt)
1355 {
1356 /* If the padding is less than 15 bytes, we use the normal
1357 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1358 its offset. */
1359 int limit;
76ba9986 1360
711eedef
L		 1361 /* For 64bit, the limit is 3 bytes. */
1362 if (flag_code == CODE_64BIT
1363 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1364 limit = 3;
1365 else
1366 limit = 15;
1367 if (count < limit)
76bc74dc
L		 1368 memcpy (fragP->fr_literal + fragP->fr_fix,
1369 patt[count - 1], count);
1370 else
1371 {
1372 memcpy (fragP->fr_literal + fragP->fr_fix,
1373 jump_31, count);
1374 /* Adjust jump offset. */
1375 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1376 }
1377 }
1378 else
1379 {
80b8656c
L		 1380 /* Maximum length of an instruction is 10 byte. If the
1381 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1382 we have to break it into smaller pieces. */
1383 int padding = count;
80b8656c 1384 while (padding > 10)
76bc74dc 1385 {
80b8656c 1386 padding -= 10;
76bc74dc 1387 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1388 patt [9], 10);
76bc74dc
L		 1389 }
1390
1391 if (padding)
1392 memcpy (fragP->fr_literal + fragP->fr_fix,
1393 patt [padding - 1], padding);
1394 }
ccc9c027 1395 }
33fef721 1396 fragP->fr_var = count;
252b5132
RH		 1397}
1398
c6fb90c8 1399static INLINE int
0dfbf9d7 1400operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1401{
0dfbf9d7 1402 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1403 {
1404 case 3:
0dfbf9d7 1405 if (x->array[2])
c6fb90c8 1406 return 0;
1a0670f3 1407 /* Fall through. */
c6fb90c8 1408 case 2:
0dfbf9d7 1409 if (x->array[1])
c6fb90c8 1410 return 0;
1a0670f3 1411 /* Fall through. */
c6fb90c8 1412 case 1:
0dfbf9d7 1413 return !x->array[0];
c6fb90c8
L		 1414 default:
1415 abort ();
1416 }
40fb9820
L		 1417}
1418
c6fb90c8 1419static INLINE void
0dfbf9d7 1420operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1421{
0dfbf9d7 1422 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1423 {
1424 case 3:
0dfbf9d7 1425 x->array[2] = v;
1a0670f3 1426 /* Fall through. */
c6fb90c8 1427 case 2:
0dfbf9d7 1428 x->array[1] = v;
1a0670f3 1429 /* Fall through. */
c6fb90c8 1430 case 1:
0dfbf9d7 1431 x->array[0] = v;
1a0670f3 1432 /* Fall through. */
c6fb90c8
L		 1433 break;
1434 default:
1435 abort ();
1436 }
1437}
40fb9820 1438
c6fb90c8 1439static INLINE int
0dfbf9d7
L		 1440operand_type_equal (const union i386_operand_type *x,
1441 const union i386_operand_type *y)
c6fb90c8 1442{
0dfbf9d7 1443 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1444 {
1445 case 3:
0dfbf9d7 1446 if (x->array[2] != y->array[2])
c6fb90c8 1447 return 0;
1a0670f3 1448 /* Fall through. */
c6fb90c8 1449 case 2:
0dfbf9d7 1450 if (x->array[1] != y->array[1])
c6fb90c8 1451 return 0;
1a0670f3 1452 /* Fall through. */
c6fb90c8 1453 case 1:
0dfbf9d7 1454 return x->array[0] == y->array[0];
c6fb90c8
L		 1455 break;
1456 default:
1457 abort ();
1458 }
1459}
40fb9820 1460
0dfbf9d7
L		 1461static INLINE int
1462cpu_flags_all_zero (const union i386_cpu_flags *x)
1463{
1464 switch (ARRAY_SIZE(x->array))
1465 {
53467f57
IT		 1466 case 4:
1467 if (x->array[3])
1468 return 0;
1469 /* Fall through. */
0dfbf9d7
L		 1470 case 3:
1471 if (x->array[2])
1472 return 0;
1a0670f3 1473 /* Fall through. */
0dfbf9d7
L		 1474 case 2:
1475 if (x->array[1])
1476 return 0;
1a0670f3 1477 /* Fall through. */
0dfbf9d7
L		 1478 case 1:
1479 return !x->array[0];
1480 default:
1481 abort ();
1482 }
1483}
1484
0dfbf9d7
L		 1485static INLINE int
1486cpu_flags_equal (const union i386_cpu_flags *x,
1487 const union i386_cpu_flags *y)
1488{
1489 switch (ARRAY_SIZE(x->array))
1490 {
53467f57
IT		 1491 case 4:
1492 if (x->array[3] != y->array[3])
1493 return 0;
1494 /* Fall through. */
0dfbf9d7
L		 1495 case 3:
1496 if (x->array[2] != y->array[2])
1497 return 0;
1a0670f3 1498 /* Fall through. */
0dfbf9d7
L		 1499 case 2:
1500 if (x->array[1] != y->array[1])
1501 return 0;
1a0670f3 1502 /* Fall through. */
0dfbf9d7
L		 1503 case 1:
1504 return x->array[0] == y->array[0];
1505 break;
1506 default:
1507 abort ();
1508 }
1509}
c6fb90c8
L		 1510
1511static INLINE int
1512cpu_flags_check_cpu64 (i386_cpu_flags f)
1513{
1514 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1515 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1516}
1517
c6fb90c8
L		 1518static INLINE i386_cpu_flags
1519cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1520{
c6fb90c8
L		 1521 switch (ARRAY_SIZE (x.array))
1522 {
53467f57
IT		 1523 case 4:
1524 x.array [3] &= y.array [3];
1525 /* Fall through. */
c6fb90c8
L		 1526 case 3:
1527 x.array [2] &= y.array [2];
1a0670f3 1528 /* Fall through. */
c6fb90c8
L		 1529 case 2:
1530 x.array [1] &= y.array [1];
1a0670f3 1531 /* Fall through. */
c6fb90c8
L		 1532 case 1:
1533 x.array [0] &= y.array [0];
1534 break;
1535 default:
1536 abort ();
1537 }
1538 return x;
1539}
40fb9820 1540
c6fb90c8
L		 1541static INLINE i386_cpu_flags
1542cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1543{
c6fb90c8 1544 switch (ARRAY_SIZE (x.array))
40fb9820 1545 {
53467f57
IT		 1546 case 4:
1547 x.array [3] |= y.array [3];
1548 /* Fall through. */
c6fb90c8
L		 1549 case 3:
1550 x.array [2] |= y.array [2];
1a0670f3 1551 /* Fall through. */
c6fb90c8
L		 1552 case 2:
1553 x.array [1] |= y.array [1];
1a0670f3 1554 /* Fall through. */
c6fb90c8
L		 1555 case 1:
1556 x.array [0] |= y.array [0];
40fb9820
L		 1557 break;
1558 default:
1559 abort ();
1560 }
40fb9820
L		 1561 return x;
1562}
1563
309d3373
JB		 1564static INLINE i386_cpu_flags
1565cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1566{
1567 switch (ARRAY_SIZE (x.array))
1568 {
53467f57
IT		 1569 case 4:
1570 x.array [3] &= ~y.array [3];
1571 /* Fall through. */
309d3373
JB		 1572 case 3:
1573 x.array [2] &= ~y.array [2];
1a0670f3 1574 /* Fall through. */
309d3373
JB		 1575 case 2:
1576 x.array [1] &= ~y.array [1];
1a0670f3 1577 /* Fall through. */
309d3373
JB		 1578 case 1:
1579 x.array [0] &= ~y.array [0];
1580 break;
1581 default:
1582 abort ();
1583 }
1584 return x;
1585}
1586
c0f3af97
L		 1587#define CPU_FLAGS_ARCH_MATCH 0x1
1588#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1589#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1590#define CPU_FLAGS_PCLMUL_MATCH 0x8
1591#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1592
a5ff0eb2 1593#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1594 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1595 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1596#define CPU_FLAGS_PERFECT_MATCH \
1597 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1598
1599/* Return CPU flags match bits. */
3629bb00 1600
40fb9820 1601static int
d3ce72d0 1602cpu_flags_match (const insn_template *t)
40fb9820 1603{
c0f3af97
L		 1604 i386_cpu_flags x = t->cpu_flags;
1605 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1606
1607 x.bitfield.cpu64 = 0;
1608 x.bitfield.cpuno64 = 0;
1609
0dfbf9d7 1610 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1611 {
1612 /* This instruction is available on all archs. */
1613 match |= CPU_FLAGS_32BIT_MATCH;
1614 }
3629bb00
L		 1615 else
1616 {
c0f3af97 1617 /* This instruction is available only on some archs. */
3629bb00
L		 1618 i386_cpu_flags cpu = cpu_arch_flags;
1619
3629bb00 1620 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1621 if (!cpu_flags_all_zero (&cpu))
1622 {
a5ff0eb2
L		 1623 if (x.bitfield.cpuavx)
1624 {
ce2f5b3c 1625 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1626 if (cpu.bitfield.cpuavx)
1627 {
1628 /* Check SSE2AVX. */
1629 if (!t->opcode_modifier.sse2avx|| sse2avx)
1630 {
1631 match |= (CPU_FLAGS_ARCH_MATCH
1632 | CPU_FLAGS_AVX_MATCH);
1633 /* Check AES. */
1634 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1635 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1636 /* Check PCLMUL. */
1637 if (!x.bitfield.cpupclmul
1638 || cpu.bitfield.cpupclmul)
1639 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1640 }
1641 }
1642 else
1643 match |= CPU_FLAGS_ARCH_MATCH;
1644 }
73b090a9
L		 1645 else if (x.bitfield.cpuavx512vl)
1646 {
1647 /* Match AVX512VL. */
1648 if (cpu.bitfield.cpuavx512vl)
1649 {
1650 /* Need another match. */
1651 cpu.bitfield.cpuavx512vl = 0;
1652 if (!cpu_flags_all_zero (&cpu))
1653 match |= CPU_FLAGS_32BIT_MATCH;
1654 else
1655 match |= CPU_FLAGS_ARCH_MATCH;
1656 }
1657 else
1658 match |= CPU_FLAGS_ARCH_MATCH;
1659 }
a5ff0eb2 1660 else
c0f3af97
L		 1661 match |= CPU_FLAGS_32BIT_MATCH;
1662 }
3629bb00 1663 }
c0f3af97 1664 return match;
40fb9820
L		 1665}
1666
c6fb90c8
L		 1667static INLINE i386_operand_type
1668operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1669{
c6fb90c8
L		 1670 switch (ARRAY_SIZE (x.array))
1671 {
1672 case 3:
1673 x.array [2] &= y.array [2];
1a0670f3 1674 /* Fall through. */
c6fb90c8
L		 1675 case 2:
1676 x.array [1] &= y.array [1];
1a0670f3 1677 /* Fall through. */
c6fb90c8
L		 1678 case 1:
1679 x.array [0] &= y.array [0];
1680 break;
1681 default:
1682 abort ();
1683 }
1684 return x;
40fb9820
L		 1685}
1686
c6fb90c8
L		 1687static INLINE i386_operand_type
1688operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1689{
c6fb90c8 1690 switch (ARRAY_SIZE (x.array))
40fb9820 1691 {
c6fb90c8
L		 1692 case 3:
1693 x.array [2] |= y.array [2];
1a0670f3 1694 /* Fall through. */
c6fb90c8
L		 1695 case 2:
1696 x.array [1] |= y.array [1];
1a0670f3 1697 /* Fall through. */
c6fb90c8
L		 1698 case 1:
1699 x.array [0] |= y.array [0];
40fb9820
L		 1700 break;
1701 default:
1702 abort ();
1703 }
c6fb90c8
L		 1704 return x;
1705}
40fb9820 1706
c6fb90c8
L		 1707static INLINE i386_operand_type
1708operand_type_xor (i386_operand_type x, i386_operand_type y)
1709{
1710 switch (ARRAY_SIZE (x.array))
1711 {
1712 case 3:
1713 x.array [2] ^= y.array [2];
1a0670f3 1714 /* Fall through. */
c6fb90c8
L		 1715 case 2:
1716 x.array [1] ^= y.array [1];
1a0670f3 1717 /* Fall through. */
c6fb90c8
L		 1718 case 1:
1719 x.array [0] ^= y.array [0];
1720 break;
1721 default:
1722 abort ();
1723 }
40fb9820
L		 1724 return x;
1725}
1726
1727static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1728static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1729static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1730static const i386_operand_type inoutportreg
1731 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1732static const i386_operand_type reg16_inoutportreg
1733 = OPERAND_TYPE_REG16_INOUTPORTREG;
1734static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1735static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1736static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1737static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1738static const i386_operand_type anydisp
1739 = OPERAND_TYPE_ANYDISP;
40fb9820 1740static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1741static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1742static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1743static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1744static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1745static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1746static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1747static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1748static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1749static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1750static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1751static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1752static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1753static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1754
1755enum operand_type
1756{
1757 reg,
40fb9820
L		 1758 imm,
1759 disp,
1760 anymem
1761};
1762
c6fb90c8 1763static INLINE int
40fb9820
L		 1764operand_type_check (i386_operand_type t, enum operand_type c)
1765{
1766 switch (c)
1767 {
1768 case reg:
1769 return (t.bitfield.reg8
1770 || t.bitfield.reg16
1771 || t.bitfield.reg32
1772 || t.bitfield.reg64);
1773
40fb9820
L		 1774 case imm:
1775 return (t.bitfield.imm8
1776 || t.bitfield.imm8s
1777 || t.bitfield.imm16
1778 || t.bitfield.imm32
1779 || t.bitfield.imm32s
1780 || t.bitfield.imm64);
1781
1782 case disp:
1783 return (t.bitfield.disp8
1784 || t.bitfield.disp16
1785 || t.bitfield.disp32
1786 || t.bitfield.disp32s
1787 || t.bitfield.disp64);
1788
1789 case anymem:
1790 return (t.bitfield.disp8
1791 || t.bitfield.disp16
1792 || t.bitfield.disp32
1793 || t.bitfield.disp32s
1794 || t.bitfield.disp64
1795 || t.bitfield.baseindex);
1796
1797 default:
1798 abort ();
1799 }
2cfe26b6
AM		 1800
1801 return 0;
40fb9820
L		 1802}
1803
5c07affc
L		 1804/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1805 operand J for instruction template T. */
1806
1807static INLINE int
d3ce72d0 1808match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1809{
1810 return !((i.types[j].bitfield.byte
1811 && !t->operand_types[j].bitfield.byte)
1812 || (i.types[j].bitfield.word
1813 && !t->operand_types[j].bitfield.word)
1814 || (i.types[j].bitfield.dword
1815 && !t->operand_types[j].bitfield.dword)
1816 || (i.types[j].bitfield.qword
1817 && !t->operand_types[j].bitfield.qword));
1818}
1819
1820/* Return 1 if there is no conflict in any size on operand J for
1821 instruction template T. */
1822
1823static INLINE int
d3ce72d0 1824match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1825{
1826 return (match_reg_size (t, j)
1827 && !((i.types[j].bitfield.unspecified
af508cb9 1828 && !i.broadcast
5c07affc
L		 1829 && !t->operand_types[j].bitfield.unspecified)
1830 || (i.types[j].bitfield.fword
1831 && !t->operand_types[j].bitfield.fword)
1832 || (i.types[j].bitfield.tbyte
1833 && !t->operand_types[j].bitfield.tbyte)
1834 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1835 && !t->operand_types[j].bitfield.xmmword)
1836 || (i.types[j].bitfield.ymmword
43234a1e
L		 1837 && !t->operand_types[j].bitfield.ymmword)
1838 || (i.types[j].bitfield.zmmword
1839 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1840}
1841
1842/* Return 1 if there is no size conflict on any operands for
1843 instruction template T. */
1844
1845static INLINE int
d3ce72d0 1846operand_size_match (const insn_template *t)
5c07affc
L		 1847{
1848 unsigned int j;
1849 int match = 1;
1850
1851 /* Don't check jump instructions. */
1852 if (t->opcode_modifier.jump
1853 || t->opcode_modifier.jumpbyte
1854 || t->opcode_modifier.jumpdword
1855 || t->opcode_modifier.jumpintersegment)
1856 return match;
1857
1858 /* Check memory and accumulator operand size. */
1859 for (j = 0; j < i.operands; j++)
1860 {
1861 if (t->operand_types[j].bitfield.anysize)
1862 continue;
1863
1864 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1865 {
1866 match = 0;
1867 break;
1868 }
1869
1870 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1871 {
1872 match = 0;
1873 break;
1874 }
1875 }
1876
891edac4 1877 if (match)
5c07affc 1878 return match;
891edac4
L		 1879 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1880 {
1881mismatch:
86e026a4 1882 i.error = operand_size_mismatch;
891edac4
L		 1883 return 0;
1884 }
5c07affc
L		 1885
1886 /* Check reverse. */
9c2799c2 1887 gas_assert (i.operands == 2);
5c07affc
L		 1888
1889 match = 1;
1890 for (j = 0; j < 2; j++)
1891 {
1892 if (t->operand_types[j].bitfield.acc
1893 && !match_reg_size (t, j ? 0 : 1))
891edac4 1894 goto mismatch;
5c07affc
L		 1895
1896 if (i.types[j].bitfield.mem
1897 && !match_mem_size (t, j ? 0 : 1))
891edac4 1898 goto mismatch;
5c07affc
L		 1899 }
1900
1901 return match;
1902}
1903
c6fb90c8 1904static INLINE int
40fb9820
L		 1905operand_type_match (i386_operand_type overlap,
1906 i386_operand_type given)
1907{
1908 i386_operand_type temp = overlap;
1909
1910 temp.bitfield.jumpabsolute = 0;
7d5e4556 1911 temp.bitfield.unspecified = 0;
5c07affc
L		 1912 temp.bitfield.byte = 0;
1913 temp.bitfield.word = 0;
1914 temp.bitfield.dword = 0;
1915 temp.bitfield.fword = 0;
1916 temp.bitfield.qword = 0;
1917 temp.bitfield.tbyte = 0;
1918 temp.bitfield.xmmword = 0;
c0f3af97 1919 temp.bitfield.ymmword = 0;
43234a1e 1920 temp.bitfield.zmmword = 0;
0dfbf9d7 1921 if (operand_type_all_zero (&temp))
891edac4 1922 goto mismatch;
40fb9820 1923
891edac4
L		 1924 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1925 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1926 return 1;
1927
1928mismatch:
a65babc9 1929 i.error = operand_type_mismatch;
891edac4 1930 return 0;
40fb9820
L		 1931}
1932
7d5e4556 1933/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1934 unless the expected operand type register overlap is null.
1935 Note that Acc in a template matches every size of reg. */
1936
c6fb90c8 1937static INLINE int
40fb9820
L		 1938operand_type_register_match (i386_operand_type m0,
1939 i386_operand_type g0,
1940 i386_operand_type t0,
1941 i386_operand_type m1,
1942 i386_operand_type g1,
1943 i386_operand_type t1)
1944{
1945 if (!operand_type_check (g0, reg))
1946 return 1;
1947
1948 if (!operand_type_check (g1, reg))
1949 return 1;
1950
1951 if (g0.bitfield.reg8 == g1.bitfield.reg8
1952 && g0.bitfield.reg16 == g1.bitfield.reg16
1953 && g0.bitfield.reg32 == g1.bitfield.reg32
1954 && g0.bitfield.reg64 == g1.bitfield.reg64)
1955 return 1;
1956
1957 if (m0.bitfield.acc)
1958 {
1959 t0.bitfield.reg8 = 1;
1960 t0.bitfield.reg16 = 1;
1961 t0.bitfield.reg32 = 1;
1962 t0.bitfield.reg64 = 1;
1963 }
1964
1965 if (m1.bitfield.acc)
1966 {
1967 t1.bitfield.reg8 = 1;
1968 t1.bitfield.reg16 = 1;
1969 t1.bitfield.reg32 = 1;
1970 t1.bitfield.reg64 = 1;
1971 }
1972
891edac4
L		 1973 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1974 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1975 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1976 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1977 return 1;
1978
a65babc9 1979 i.error = register_type_mismatch;
891edac4
L		 1980
1981 return 0;
40fb9820
L		 1982}
1983
4c692bc7
JB		 1984static INLINE unsigned int
1985register_number (const reg_entry *r)
1986{
1987 unsigned int nr = r->reg_num;
1988
1989 if (r->reg_flags & RegRex)
1990 nr += 8;
1991
200cbe0f
L		 1992 if (r->reg_flags & RegVRex)
1993 nr += 16;
1994
4c692bc7
JB		 1995 return nr;
1996}
1997
252b5132 1998static INLINE unsigned int
40fb9820 1999mode_from_disp_size (i386_operand_type t)
252b5132 2000{
43234a1e 2001 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 2002 return 1;
2003 else if (t.bitfield.disp16
2004 || t.bitfield.disp32
2005 || t.bitfield.disp32s)
2006 return 2;
2007 else
2008 return 0;
252b5132
RH		 2009}
2010
2011static INLINE int
65879393 2012fits_in_signed_byte (addressT num)
252b5132 2013{
65879393 2014 return num + 0x80 <= 0xff;
47926f60 2015}
252b5132
RH		 2016
2017static INLINE int
65879393 2018fits_in_unsigned_byte (addressT num)
252b5132 2019{
65879393 2020 return num <= 0xff;
47926f60 2021}
252b5132
RH		 2022
2023static INLINE int
65879393 2024fits_in_unsigned_word (addressT num)
252b5132 2025{
65879393 2026 return num <= 0xffff;
47926f60 2027}
252b5132
RH		 2028
2029static INLINE int
65879393 2030fits_in_signed_word (addressT num)
252b5132 2031{
65879393 2032 return num + 0x8000 <= 0xffff;
47926f60 2033}
2a962e6d 2034
3e73aa7c 2035static INLINE int
65879393 2036fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2037{
2038#ifndef BFD64
2039 return 1;
2040#else
65879393 2041 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2042#endif
2043} /* fits_in_signed_long() */
2a962e6d 2044
3e73aa7c 2045static INLINE int
65879393 2046fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2047{
2048#ifndef BFD64
2049 return 1;
2050#else
65879393 2051 return num <= 0xffffffff;
3e73aa7c
JH		 2052#endif
2053} /* fits_in_unsigned_long() */
252b5132 2054
43234a1e
L		 2055static INLINE int
2056fits_in_vec_disp8 (offsetT num)
2057{
2058 int shift = i.memshift;
2059 unsigned int mask;
2060
2061 if (shift == -1)
2062 abort ();
2063
2064 mask = (1 << shift) - 1;
2065
2066 /* Return 0 if NUM isn't properly aligned. */
2067 if ((num & mask))
2068 return 0;
2069
2070 /* Check if NUM will fit in 8bit after shift. */
2071 return fits_in_signed_byte (num >> shift);
2072}
2073
a683cc34
SP		 2074static INLINE int
2075fits_in_imm4 (offsetT num)
2076{
2077 return (num & 0xf) == num;
2078}
2079
40fb9820 2080static i386_operand_type
e3bb37b5 2081smallest_imm_type (offsetT num)
252b5132 2082{
40fb9820 2083 i386_operand_type t;
7ab9ffdd 2084
0dfbf9d7 2085 operand_type_set (&t, 0);
40fb9820
L		 2086 t.bitfield.imm64 = 1;
2087
2088 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2089 {
2090 /* This code is disabled on the 486 because all the Imm1 forms
2091 in the opcode table are slower on the i486. They're the
2092 versions with the implicitly specified single-position
2093 displacement, which has another syntax if you really want to
2094 use that form. */
40fb9820
L		 2095 t.bitfield.imm1 = 1;
2096 t.bitfield.imm8 = 1;
2097 t.bitfield.imm8s = 1;
2098 t.bitfield.imm16 = 1;
2099 t.bitfield.imm32 = 1;
2100 t.bitfield.imm32s = 1;
2101 }
2102 else if (fits_in_signed_byte (num))
2103 {
2104 t.bitfield.imm8 = 1;
2105 t.bitfield.imm8s = 1;
2106 t.bitfield.imm16 = 1;
2107 t.bitfield.imm32 = 1;
2108 t.bitfield.imm32s = 1;
2109 }
2110 else if (fits_in_unsigned_byte (num))
2111 {
2112 t.bitfield.imm8 = 1;
2113 t.bitfield.imm16 = 1;
2114 t.bitfield.imm32 = 1;
2115 t.bitfield.imm32s = 1;
2116 }
2117 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2118 {
2119 t.bitfield.imm16 = 1;
2120 t.bitfield.imm32 = 1;
2121 t.bitfield.imm32s = 1;
2122 }
2123 else if (fits_in_signed_long (num))
2124 {
2125 t.bitfield.imm32 = 1;
2126 t.bitfield.imm32s = 1;
2127 }
2128 else if (fits_in_unsigned_long (num))
2129 t.bitfield.imm32 = 1;
2130
2131 return t;
47926f60 2132}
252b5132 2133
847f7ad4 2134static offsetT
e3bb37b5 2135offset_in_range (offsetT val, int size)
847f7ad4 2136{
508866be 2137 addressT mask;
ba2adb93 2138
847f7ad4
AM		 2139 switch (size)
2140 {
508866be
L		 2141 case 1: mask = ((addressT) 1 << 8) - 1; break;
2142 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2143 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2144#ifdef BFD64
2145 case 8: mask = ((addressT) 2 << 63) - 1; break;
2146#endif
47926f60 2147 default: abort ();
847f7ad4
AM		 2148 }
2149
9de868bf
L		 2150#ifdef BFD64
2151 /* If BFD64, sign extend val for 32bit address mode. */
2152 if (flag_code != CODE_64BIT
2153 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2154 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2155 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2156#endif
ba2adb93 2157
47926f60 2158 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2159 {
2160 char buf1[40], buf2[40];
2161
2162 sprint_value (buf1, val);
2163 sprint_value (buf2, val & mask);
2164 as_warn (_("%s shortened to %s"), buf1, buf2);
2165 }
2166 return val & mask;
2167}
2168
c32fa91d
L		 2169enum PREFIX_GROUP
2170{
2171 PREFIX_EXIST = 0,
2172 PREFIX_LOCK,
2173 PREFIX_REP,
04ef582a 2174 PREFIX_DS,
c32fa91d
L		 2175 PREFIX_OTHER
2176};
2177
2178/* Returns
2179 a. PREFIX_EXIST if attempting to add a prefix where one from the
2180 same class already exists.
2181 b. PREFIX_LOCK if lock prefix is added.
2182 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2183 d. PREFIX_DS if ds prefix is added.
2184 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2185 */
2186
2187static enum PREFIX_GROUP
e3bb37b5 2188add_prefix (unsigned int prefix)
252b5132 2189{
c32fa91d 2190 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2191 unsigned int q;
252b5132 2192
29b0f896
AM		 2193 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2194 && flag_code == CODE_64BIT)
b1905489 2195 {
161a04f6
L		 2196 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2197 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2198 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2199 ret = PREFIX_EXIST;
b1905489
JB		 2200 q = REX_PREFIX;
2201 }
3e73aa7c 2202 else
b1905489
JB		 2203 {
2204 switch (prefix)
2205 {
2206 default:
2207 abort ();
2208
b1905489 2209 case DS_PREFIX_OPCODE:
04ef582a
L		 2210 ret = PREFIX_DS;
2211 /* Fall through. */
2212 case CS_PREFIX_OPCODE:
b1905489
JB		 2213 case ES_PREFIX_OPCODE:
2214 case FS_PREFIX_OPCODE:
2215 case GS_PREFIX_OPCODE:
2216 case SS_PREFIX_OPCODE:
2217 q = SEG_PREFIX;
2218 break;
2219
2220 case REPNE_PREFIX_OPCODE:
2221 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2222 q = REP_PREFIX;
2223 ret = PREFIX_REP;
2224 break;
2225
b1905489 2226 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2227 q = LOCK_PREFIX;
2228 ret = PREFIX_LOCK;
b1905489
JB		 2229 break;
2230
2231 case FWAIT_OPCODE:
2232 q = WAIT_PREFIX;
2233 break;
2234
2235 case ADDR_PREFIX_OPCODE:
2236 q = ADDR_PREFIX;
2237 break;
2238
2239 case DATA_PREFIX_OPCODE:
2240 q = DATA_PREFIX;
2241 break;
2242 }
2243 if (i.prefix[q] != 0)
c32fa91d 2244 ret = PREFIX_EXIST;
b1905489 2245 }
252b5132 2246
b1905489 2247 if (ret)
252b5132 2248 {
b1905489
JB		 2249 if (!i.prefix[q])
2250 ++i.prefixes;
2251 i.prefix[q] |= prefix;
252b5132 2252 }
b1905489
JB		 2253 else
2254 as_bad (_("same type of prefix used twice"));
252b5132 2255
252b5132
RH		 2256 return ret;
2257}
2258
2259static void
78f12dd3 2260update_code_flag (int value, int check)
eecb386c 2261{
78f12dd3
L		 2262 PRINTF_LIKE ((*as_error));
2263
1e9cc1c2 2264 flag_code = (enum flag_code) value;
40fb9820
L		 2265 if (flag_code == CODE_64BIT)
2266 {
2267 cpu_arch_flags.bitfield.cpu64 = 1;
2268 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2269 }
2270 else
2271 {
2272 cpu_arch_flags.bitfield.cpu64 = 0;
2273 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2274 }
2275 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2276 {
78f12dd3
L		 2277 if (check)
2278 as_error = as_fatal;
2279 else
2280 as_error = as_bad;
2281 (*as_error) (_("64bit mode not supported on `%s'."),
2282 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2283 }
40fb9820 2284 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2285 {
78f12dd3
L		 2286 if (check)
2287 as_error = as_fatal;
2288 else
2289 as_error = as_bad;
2290 (*as_error) (_("32bit mode not supported on `%s'."),
2291 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2292 }
eecb386c
AM		 2293 stackop_size = '\0';
2294}
2295
78f12dd3
L		 2296static void
2297set_code_flag (int value)
2298{
2299 update_code_flag (value, 0);
2300}
2301
eecb386c 2302static void
e3bb37b5 2303set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2304{
1e9cc1c2 2305 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2306 if (flag_code != CODE_16BIT)
2307 abort ();
2308 cpu_arch_flags.bitfield.cpu64 = 0;
2309 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2310 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2311}
2312
2313static void
e3bb37b5 2314set_intel_syntax (int syntax_flag)
252b5132
RH		 2315{
2316 /* Find out if register prefixing is specified. */
2317 int ask_naked_reg = 0;
2318
2319 SKIP_WHITESPACE ();
29b0f896 2320 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2321 {
d02603dc
NC		 2322 char *string;
2323 int e = get_symbol_name (&string);
252b5132 2324
47926f60 2325 if (strcmp (string, "prefix") == 0)
252b5132 2326 ask_naked_reg = 1;
47926f60 2327 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2328 ask_naked_reg = -1;
2329 else
d0b47220 2330 as_bad (_("bad argument to syntax directive."));
d02603dc 2331 (void) restore_line_pointer (e);
252b5132
RH		 2332 }
2333 demand_empty_rest_of_line ();
c3332e24 2334
252b5132
RH		 2335 intel_syntax = syntax_flag;
2336
2337 if (ask_naked_reg == 0)
f86103b7
AM		 2338 allow_naked_reg = (intel_syntax
2339 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2340 else
2341 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2342
ee86248c 2343 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2344
e4a3b5a4 2345 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2346 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2347 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2348}
2349
1efbbeb4
L		 2350static void
2351set_intel_mnemonic (int mnemonic_flag)
2352{
e1d4d893 2353 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2354}
2355
db51cc60
L		 2356static void
2357set_allow_index_reg (int flag)
2358{
2359 allow_index_reg = flag;
2360}
2361
cb19c032 2362static void
7bab8ab5 2363set_check (int what)
cb19c032 2364{
7bab8ab5
JB		 2365 enum check_kind *kind;
2366 const char *str;
2367
2368 if (what)
2369 {
2370 kind = &operand_check;
2371 str = "operand";
2372 }
2373 else
2374 {
2375 kind = &sse_check;
2376 str = "sse";
2377 }
2378
cb19c032
L		 2379 SKIP_WHITESPACE ();
2380
2381 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2382 {
d02603dc
NC		 2383 char *string;
2384 int e = get_symbol_name (&string);
cb19c032
L		 2385
2386 if (strcmp (string, "none") == 0)
7bab8ab5 2387 *kind = check_none;
cb19c032 2388 else if (strcmp (string, "warning") == 0)
7bab8ab5 2389 *kind = check_warning;
cb19c032 2390 else if (strcmp (string, "error") == 0)
7bab8ab5 2391 *kind = check_error;
cb19c032 2392 else
7bab8ab5 2393 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2394 (void) restore_line_pointer (e);
cb19c032
L		 2395 }
2396 else
7bab8ab5 2397 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2398
2399 demand_empty_rest_of_line ();
2400}
2401
8a9036a4
L		 2402static void
2403check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2404 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2405{
2406#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2407 static const char *arch;
2408
2409 /* Intel LIOM is only supported on ELF. */
2410 if (!IS_ELF)
2411 return;
2412
2413 if (!arch)
2414 {
2415 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2416 use default_arch. */
2417 arch = cpu_arch_name;
2418 if (!arch)
2419 arch = default_arch;
2420 }
2421
81486035
L		 2422 /* If we are targeting Intel MCU, we must enable it. */
2423 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2424 || new_flag.bitfield.cpuiamcu)
2425 return;
2426
3632d14b 2427 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2428 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2429 || new_flag.bitfield.cpul1om)
8a9036a4 2430 return;
76ba9986 2431
7a9068fe
L		 2432 /* If we are targeting Intel K1OM, we must enable it. */
2433 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2434 || new_flag.bitfield.cpuk1om)
2435 return;
2436
8a9036a4
L		 2437 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2438#endif
2439}
2440
e413e4e9 2441static void
e3bb37b5 2442set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2443{
47926f60 2444 SKIP_WHITESPACE ();
e413e4e9 2445
29b0f896 2446 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2447 {
d02603dc
NC		 2448 char *string;
2449 int e = get_symbol_name (&string);
91d6fa6a 2450 unsigned int j;
40fb9820 2451 i386_cpu_flags flags;
e413e4e9 2452
91d6fa6a 2453 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2454 {
91d6fa6a 2455 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2456 {
91d6fa6a 2457 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2458
5c6af06e
JB		 2459 if (*string != '.')
2460 {
91d6fa6a 2461 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2462 cpu_sub_arch_name = NULL;
91d6fa6a 2463 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2464 if (flag_code == CODE_64BIT)
2465 {
2466 cpu_arch_flags.bitfield.cpu64 = 1;
2467 cpu_arch_flags.bitfield.cpuno64 = 0;
2468 }
2469 else
2470 {
2471 cpu_arch_flags.bitfield.cpu64 = 0;
2472 cpu_arch_flags.bitfield.cpuno64 = 1;
2473 }
91d6fa6a
NC		 2474 cpu_arch_isa = cpu_arch[j].type;
2475 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2476 if (!cpu_arch_tune_set)
2477 {
2478 cpu_arch_tune = cpu_arch_isa;
2479 cpu_arch_tune_flags = cpu_arch_isa_flags;
2480 }
5c6af06e
JB		 2481 break;
2482 }
40fb9820 2483
293f5f65
L		 2484 flags = cpu_flags_or (cpu_arch_flags,
2485 cpu_arch[j].flags);
81486035 2486
5b64d091 2487 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2488 {
6305a203
L		 2489 if (cpu_sub_arch_name)
2490 {
2491 char *name = cpu_sub_arch_name;
2492 cpu_sub_arch_name = concat (name,
91d6fa6a 2493 cpu_arch[j].name,
1bf57e9f 2494 (const char *) NULL);
6305a203
L		 2495 free (name);
2496 }
2497 else
91d6fa6a 2498 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2499 cpu_arch_flags = flags;
a586129e 2500 cpu_arch_isa_flags = flags;
5c6af06e 2501 }
d02603dc 2502 (void) restore_line_pointer (e);
5c6af06e
JB		 2503 demand_empty_rest_of_line ();
2504 return;
e413e4e9
AM		 2505 }
2506 }
293f5f65
L		 2507
2508 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2509 {
33eaf5de 2510 /* Disable an ISA extension. */
293f5f65
L		 2511 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2512 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2513 {
2514 flags = cpu_flags_and_not (cpu_arch_flags,
2515 cpu_noarch[j].flags);
2516 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2517 {
2518 if (cpu_sub_arch_name)
2519 {
2520 char *name = cpu_sub_arch_name;
2521 cpu_sub_arch_name = concat (name, string,
2522 (const char *) NULL);
2523 free (name);
2524 }
2525 else
2526 cpu_sub_arch_name = xstrdup (string);
2527 cpu_arch_flags = flags;
2528 cpu_arch_isa_flags = flags;
2529 }
2530 (void) restore_line_pointer (e);
2531 demand_empty_rest_of_line ();
2532 return;
2533 }
2534
2535 j = ARRAY_SIZE (cpu_arch);
2536 }
2537
91d6fa6a 2538 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2539 as_bad (_("no such architecture: `%s'"), string);
2540
2541 *input_line_pointer = e;
2542 }
2543 else
2544 as_bad (_("missing cpu architecture"));
2545
fddf5b5b
AM		 2546 no_cond_jump_promotion = 0;
2547 if (*input_line_pointer == ','
29b0f896 2548 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2549 {
d02603dc
NC		 2550 char *string;
2551 char e;
2552
2553 ++input_line_pointer;
2554 e = get_symbol_name (&string);
fddf5b5b
AM		 2555
2556 if (strcmp (string, "nojumps") == 0)
2557 no_cond_jump_promotion = 1;
2558 else if (strcmp (string, "jumps") == 0)
2559 ;
2560 else
2561 as_bad (_("no such architecture modifier: `%s'"), string);
2562
d02603dc 2563 (void) restore_line_pointer (e);
fddf5b5b
AM		 2564 }
2565
e413e4e9
AM		 2566 demand_empty_rest_of_line ();
2567}
2568
8a9036a4
L		 2569enum bfd_architecture
2570i386_arch (void)
2571{
3632d14b 2572 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2573 {
2574 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2575 || flag_code != CODE_64BIT)
2576 as_fatal (_("Intel L1OM is 64bit ELF only"));
2577 return bfd_arch_l1om;
2578 }
7a9068fe
L		 2579 else if (cpu_arch_isa == PROCESSOR_K1OM)
2580 {
2581 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2582 || flag_code != CODE_64BIT)
2583 as_fatal (_("Intel K1OM is 64bit ELF only"));
2584 return bfd_arch_k1om;
2585 }
81486035
L		 2586 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2587 {
2588 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2589 || flag_code == CODE_64BIT)
2590 as_fatal (_("Intel MCU is 32bit ELF only"));
2591 return bfd_arch_iamcu;
2592 }
8a9036a4
L		 2593 else
2594 return bfd_arch_i386;
2595}
2596
b9d79e03 2597unsigned long
7016a5d5 2598i386_mach (void)
b9d79e03 2599{
351f65ca 2600 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2601 {
3632d14b 2602 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2603 {
351f65ca
L		 2604 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2605 || default_arch[6] != '\0')
8a9036a4
L		 2606 as_fatal (_("Intel L1OM is 64bit ELF only"));
2607 return bfd_mach_l1om;
2608 }
7a9068fe
L		 2609 else if (cpu_arch_isa == PROCESSOR_K1OM)
2610 {
2611 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2612 || default_arch[6] != '\0')
2613 as_fatal (_("Intel K1OM is 64bit ELF only"));
2614 return bfd_mach_k1om;
2615 }
351f65ca 2616 else if (default_arch[6] == '\0')
8a9036a4 2617 return bfd_mach_x86_64;
351f65ca
L		 2618 else
2619 return bfd_mach_x64_32;
8a9036a4 2620 }
5197d474
L		 2621 else if (!strcmp (default_arch, "i386")
2622 || !strcmp (default_arch, "iamcu"))
81486035
L		 2623 {
2624 if (cpu_arch_isa == PROCESSOR_IAMCU)
2625 {
2626 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2627 as_fatal (_("Intel MCU is 32bit ELF only"));
2628 return bfd_mach_i386_iamcu;
2629 }
2630 else
2631 return bfd_mach_i386_i386;
2632 }
b9d79e03 2633 else
2b5d6a91 2634 as_fatal (_("unknown architecture"));
b9d79e03 2635}
b9d79e03 2636\f
252b5132 2637void
7016a5d5 2638md_begin (void)
252b5132
RH		 2639{
2640 const char *hash_err;
2641
86fa6981
L		 2642 /* Support pseudo prefixes like {disp32}. */
2643 lex_type ['{'] = LEX_BEGIN_NAME;
2644
47926f60 2645 /* Initialize op_hash hash table. */
252b5132
RH		 2646 op_hash = hash_new ();
2647
2648 {
d3ce72d0 2649 const insn_template *optab;
29b0f896 2650 templates *core_optab;
252b5132 2651
47926f60
KH		 2652 /* Setup for loop. */
2653 optab = i386_optab;
add39d23 2654 core_optab = XNEW (templates);
252b5132
RH		 2655 core_optab->start = optab;
2656
2657 while (1)
2658 {
2659 ++optab;
2660 if (optab->name == NULL
2661 || strcmp (optab->name, (optab - 1)->name) != 0)
2662 {
2663 /* different name --> ship out current template list;
47926f60 2664 add to hash table; & begin anew. */
252b5132
RH		 2665 core_optab->end = optab;
2666 hash_err = hash_insert (op_hash,
2667 (optab - 1)->name,
5a49b8ac 2668 (void *) core_optab);
252b5132
RH		 2669 if (hash_err)
2670 {
b37df7c4 2671 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2672 (optab - 1)->name,
2673 hash_err);
2674 }
2675 if (optab->name == NULL)
2676 break;
add39d23 2677 core_optab = XNEW (templates);
252b5132
RH		 2678 core_optab->start = optab;
2679 }
2680 }
2681 }
2682
47926f60 2683 /* Initialize reg_hash hash table. */
252b5132
RH		 2684 reg_hash = hash_new ();
2685 {
29b0f896 2686 const reg_entry *regtab;
c3fe08fa 2687 unsigned int regtab_size = i386_regtab_size;
252b5132 2688
c3fe08fa 2689 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2690 {
5a49b8ac 2691 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2692 if (hash_err)
b37df7c4 2693 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2694 regtab->reg_name,
2695 hash_err);
252b5132
RH		 2696 }
2697 }
2698
47926f60 2699 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2700 {
29b0f896
AM		 2701 int c;
2702 char *p;
252b5132
RH		 2703
2704 for (c = 0; c < 256; c++)
2705 {
3882b010 2706 if (ISDIGIT (c))
252b5132
RH		 2707 {
2708 digit_chars[c] = c;
2709 mnemonic_chars[c] = c;
2710 register_chars[c] = c;
2711 operand_chars[c] = c;
2712 }
3882b010 2713 else if (ISLOWER (c))
252b5132
RH		 2714 {
2715 mnemonic_chars[c] = c;
2716 register_chars[c] = c;
2717 operand_chars[c] = c;
2718 }
3882b010 2719 else if (ISUPPER (c))
252b5132 2720 {
3882b010 2721 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2722 register_chars[c] = mnemonic_chars[c];
2723 operand_chars[c] = c;
2724 }
43234a1e 2725 else if (c == '{' || c == '}')
86fa6981
L		 2726 {
2727 mnemonic_chars[c] = c;
2728 operand_chars[c] = c;
2729 }
252b5132 2730
3882b010 2731 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2732 identifier_chars[c] = c;
2733 else if (c >= 128)
2734 {
2735 identifier_chars[c] = c;
2736 operand_chars[c] = c;
2737 }
2738 }
2739
2740#ifdef LEX_AT
2741 identifier_chars['@'] = '@';
32137342
NC		 2742#endif
2743#ifdef LEX_QM
2744 identifier_chars['?'] = '?';
2745 operand_chars['?'] = '?';
252b5132 2746#endif
252b5132 2747 digit_chars['-'] = '-';
c0f3af97 2748 mnemonic_chars['_'] = '_';
791fe849 2749 mnemonic_chars['-'] = '-';
0003779b 2750 mnemonic_chars['.'] = '.';
252b5132
RH		 2751 identifier_chars['_'] = '_';
2752 identifier_chars['.'] = '.';
2753
2754 for (p = operand_special_chars; *p != '\0'; p++)
2755 operand_chars[(unsigned char) *p] = *p;
2756 }
2757
a4447b93
RH		 2758 if (flag_code == CODE_64BIT)
2759 {
ca19b261
KT		 2760#if defined (OBJ_COFF) && defined (TE_PE)
2761 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2762 ? 32 : 16);
2763#else
a4447b93 2764 x86_dwarf2_return_column = 16;
ca19b261 2765#endif
61ff971f 2766 x86_cie_data_alignment = -8;
a4447b93
RH		 2767 }
2768 else
2769 {
2770 x86_dwarf2_return_column = 8;
2771 x86_cie_data_alignment = -4;
2772 }
252b5132
RH		 2773}
2774
2775void
e3bb37b5 2776i386_print_statistics (FILE *file)
252b5132
RH		 2777{
2778 hash_print_statistics (file, "i386 opcode", op_hash);
2779 hash_print_statistics (file, "i386 register", reg_hash);
2780}
2781\f
252b5132
RH		 2782#ifdef DEBUG386
2783
ce8a8b2f 2784/* Debugging routines for md_assemble. */
d3ce72d0 2785static void pte (insn_template *);
40fb9820 2786static void pt (i386_operand_type);
e3bb37b5
L		 2787static void pe (expressionS *);
2788static void ps (symbolS *);
252b5132
RH		 2789
2790static void
e3bb37b5 2791pi (char *line, i386_insn *x)
252b5132 2792{
09137c09 2793 unsigned int j;
252b5132
RH		 2794
2795 fprintf (stdout, "%s: template ", line);
2796 pte (&x->tm);
09f131f2
JH		 2797 fprintf (stdout, " address: base %s index %s scale %x\n",
2798 x->base_reg ? x->base_reg->reg_name : "none",
2799 x->index_reg ? x->index_reg->reg_name : "none",
2800 x->log2_scale_factor);
2801 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2802 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2803 fprintf (stdout, " sib: base %x index %x scale %x\n",
2804 x->sib.base, x->sib.index, x->sib.scale);
2805 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2806 (x->rex & REX_W) != 0,
2807 (x->rex & REX_R) != 0,
2808 (x->rex & REX_X) != 0,
2809 (x->rex & REX_B) != 0);
09137c09 2810 for (j = 0; j < x->operands; j++)
252b5132 2811 {
09137c09
SP		 2812 fprintf (stdout, " #%d: ", j + 1);
2813 pt (x->types[j]);
252b5132 2814 fprintf (stdout, "\n");
09137c09
SP		 2815 if (x->types[j].bitfield.reg8
2816 || x->types[j].bitfield.reg16
2817 || x->types[j].bitfield.reg32
2818 || x->types[j].bitfield.reg64
2819 || x->types[j].bitfield.regmmx
2820 || x->types[j].bitfield.regxmm
2821 || x->types[j].bitfield.regymm
43234a1e 2822 || x->types[j].bitfield.regzmm
09137c09
SP		 2823 || x->types[j].bitfield.sreg2
2824 || x->types[j].bitfield.sreg3
2825 || x->types[j].bitfield.control
2826 || x->types[j].bitfield.debug
2827 || x->types[j].bitfield.test)
2828 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2829 if (operand_type_check (x->types[j], imm))
2830 pe (x->op[j].imms);
2831 if (operand_type_check (x->types[j], disp))
2832 pe (x->op[j].disps);
252b5132
RH		 2833 }
2834}
2835
2836static void
d3ce72d0 2837pte (insn_template *t)
252b5132 2838{
09137c09 2839 unsigned int j;
252b5132 2840 fprintf (stdout, " %d operands ", t->operands);
47926f60 2841 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2842 if (t->extension_opcode != None)
2843 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2844 if (t->opcode_modifier.d)
252b5132 2845 fprintf (stdout, "D");
40fb9820 2846 if (t->opcode_modifier.w)
252b5132
RH		 2847 fprintf (stdout, "W");
2848 fprintf (stdout, "\n");
09137c09 2849 for (j = 0; j < t->operands; j++)
252b5132 2850 {
09137c09
SP		 2851 fprintf (stdout, " #%d type ", j + 1);
2852 pt (t->operand_types[j]);
252b5132
RH		 2853 fprintf (stdout, "\n");
2854 }
2855}
2856
2857static void
e3bb37b5 2858pe (expressionS *e)
252b5132 2859{
24eab124 2860 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2861 fprintf (stdout, " add_number %ld (%lx)\n",
2862 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2863 if (e->X_add_symbol)
2864 {
2865 fprintf (stdout, " add_symbol ");
2866 ps (e->X_add_symbol);
2867 fprintf (stdout, "\n");
2868 }
2869 if (e->X_op_symbol)
2870 {
2871 fprintf (stdout, " op_symbol ");
2872 ps (e->X_op_symbol);
2873 fprintf (stdout, "\n");
2874 }
2875}
2876
2877static void
e3bb37b5 2878ps (symbolS *s)
252b5132
RH		 2879{
2880 fprintf (stdout, "%s type %s%s",
2881 S_GET_NAME (s),
2882 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2883 segment_name (S_GET_SEGMENT (s)));
2884}
2885
7b81dfbb 2886static struct type_name
252b5132 2887 {
40fb9820
L		 2888 i386_operand_type mask;
2889 const char *name;
252b5132 2890 }
7b81dfbb 2891const type_names[] =
252b5132 2892{
40fb9820
L		 2893 { OPERAND_TYPE_REG8, "r8" },
2894 { OPERAND_TYPE_REG16, "r16" },
2895 { OPERAND_TYPE_REG32, "r32" },
2896 { OPERAND_TYPE_REG64, "r64" },
2897 { OPERAND_TYPE_IMM8, "i8" },
2898 { OPERAND_TYPE_IMM8, "i8s" },
2899 { OPERAND_TYPE_IMM16, "i16" },
2900 { OPERAND_TYPE_IMM32, "i32" },
2901 { OPERAND_TYPE_IMM32S, "i32s" },
2902 { OPERAND_TYPE_IMM64, "i64" },
2903 { OPERAND_TYPE_IMM1, "i1" },
2904 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2905 { OPERAND_TYPE_DISP8, "d8" },
2906 { OPERAND_TYPE_DISP16, "d16" },
2907 { OPERAND_TYPE_DISP32, "d32" },
2908 { OPERAND_TYPE_DISP32S, "d32s" },
2909 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2910 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2911 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2912 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2913 { OPERAND_TYPE_CONTROL, "control reg" },
2914 { OPERAND_TYPE_TEST, "test reg" },
2915 { OPERAND_TYPE_DEBUG, "debug reg" },
2916 { OPERAND_TYPE_FLOATREG, "FReg" },
2917 { OPERAND_TYPE_FLOATACC, "FAcc" },
2918 { OPERAND_TYPE_SREG2, "SReg2" },
2919 { OPERAND_TYPE_SREG3, "SReg3" },
2920 { OPERAND_TYPE_ACC, "Acc" },
2921 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2922 { OPERAND_TYPE_REGMMX, "rMMX" },
2923 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2924 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2925 { OPERAND_TYPE_REGZMM, "rZMM" },
2926 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2927 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2928};
2929
2930static void
40fb9820 2931pt (i386_operand_type t)
252b5132 2932{
40fb9820 2933 unsigned int j;
c6fb90c8 2934 i386_operand_type a;
252b5132 2935
40fb9820 2936 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2937 {
2938 a = operand_type_and (t, type_names[j].mask);
0349dc08 2939 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2940 fprintf (stdout, "%s, ", type_names[j].name);
2941 }
252b5132
RH		 2942 fflush (stdout);
2943}
2944
2945#endif /* DEBUG386 */
2946\f
252b5132 2947static bfd_reloc_code_real_type
3956db08 2948reloc (unsigned int size,
64e74474
AM		 2949 int pcrel,
2950 int sign,
2951 bfd_reloc_code_real_type other)
252b5132 2952{
47926f60 2953 if (other != NO_RELOC)
3956db08 2954 {
91d6fa6a 2955 reloc_howto_type *rel;
3956db08
JB		 2956
2957 if (size == 8)
2958 switch (other)
2959 {
64e74474
AM		 2960 case BFD_RELOC_X86_64_GOT32:
2961 return BFD_RELOC_X86_64_GOT64;
2962 break;
553d1284
L		 2963 case BFD_RELOC_X86_64_GOTPLT64:
2964 return BFD_RELOC_X86_64_GOTPLT64;
2965 break;
64e74474
AM		 2966 case BFD_RELOC_X86_64_PLTOFF64:
2967 return BFD_RELOC_X86_64_PLTOFF64;
2968 break;
2969 case BFD_RELOC_X86_64_GOTPC32:
2970 other = BFD_RELOC_X86_64_GOTPC64;
2971 break;
2972 case BFD_RELOC_X86_64_GOTPCREL:
2973 other = BFD_RELOC_X86_64_GOTPCREL64;
2974 break;
2975 case BFD_RELOC_X86_64_TPOFF32:
2976 other = BFD_RELOC_X86_64_TPOFF64;
2977 break;
2978 case BFD_RELOC_X86_64_DTPOFF32:
2979 other = BFD_RELOC_X86_64_DTPOFF64;
2980 break;
2981 default:
2982 break;
3956db08 2983 }
e05278af 2984
8ce3d284 2985#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2986 if (other == BFD_RELOC_SIZE32)
2987 {
2988 if (size == 8)
1ab668bf 2989 other = BFD_RELOC_SIZE64;
8fd4256d 2990 if (pcrel)
1ab668bf
AM		 2991 {
2992 as_bad (_("there are no pc-relative size relocations"));
2993 return NO_RELOC;
2994 }
8fd4256d 2995 }
8ce3d284 2996#endif
8fd4256d 2997
e05278af 2998 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2999 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3000 sign = -1;
3001
91d6fa6a
NC		 3002 rel = bfd_reloc_type_lookup (stdoutput, other);
3003 if (!rel)
3956db08 3004 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3005 else if (size != bfd_get_reloc_size (rel))
3956db08 3006 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3007 bfd_get_reloc_size (rel),
3956db08 3008 size);
91d6fa6a 3009 else if (pcrel && !rel->pc_relative)
3956db08 3010 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3011 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3012 && !sign)
91d6fa6a 3013 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3014 && sign > 0))
3956db08
JB		 3015 as_bad (_("relocated field and relocation type differ in signedness"));
3016 else
3017 return other;
3018 return NO_RELOC;
3019 }
252b5132
RH		 3020
3021 if (pcrel)
3022 {
3e73aa7c 3023 if (!sign)
3956db08 3024 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3025 switch (size)
3026 {
3027 case 1: return BFD_RELOC_8_PCREL;
3028 case 2: return BFD_RELOC_16_PCREL;
d258b828 3029 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3030 case 8: return BFD_RELOC_64_PCREL;
252b5132 3031 }
3956db08 3032 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3033 }
3034 else
3035 {
3956db08 3036 if (sign > 0)
e5cb08ac 3037 switch (size)
3e73aa7c
JH		 3038 {
3039 case 4: return BFD_RELOC_X86_64_32S;
3040 }
3041 else
3042 switch (size)
3043 {
3044 case 1: return BFD_RELOC_8;
3045 case 2: return BFD_RELOC_16;
3046 case 4: return BFD_RELOC_32;
3047 case 8: return BFD_RELOC_64;
3048 }
3956db08
JB		 3049 as_bad (_("cannot do %s %u byte relocation"),
3050 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3051 }
3052
0cc9e1d3 3053 return NO_RELOC;
252b5132
RH		 3054}
3055
47926f60
KH		 3056/* Here we decide which fixups can be adjusted to make them relative to
3057 the beginning of the section instead of the symbol. Basically we need
3058 to make sure that the dynamic relocations are done correctly, so in
3059 some cases we force the original symbol to be used. */
3060
252b5132 3061int
e3bb37b5 3062tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3063{
6d249963 3064#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3065 if (!IS_ELF)
31312f95
AM		 3066 return 1;
3067
a161fe53
AM		 3068 /* Don't adjust pc-relative references to merge sections in 64-bit
3069 mode. */
3070 if (use_rela_relocations
3071 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3072 && fixP->fx_pcrel)
252b5132 3073 return 0;
31312f95 3074
8d01d9a9
AJ		 3075 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3076 and changed later by validate_fix. */
3077 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3078 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3079 return 0;
3080
8fd4256d
L		 3081 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3082 for size relocations. */
3083 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3084 || fixP->fx_r_type == BFD_RELOC_SIZE64
3085 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3086 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3087 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3088 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3089 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3090 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3091 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3092 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3093 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3094 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3095 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3096 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3097 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3098 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3099 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3100 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3101 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3102 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3103 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3104 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3105 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3106 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3107 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3108 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3109 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3110 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3111 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3112 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3113 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3114 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3115 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3116 return 0;
31312f95 3117#endif
252b5132
RH		 3118 return 1;
3119}
252b5132 3120
b4cac588 3121static int
e3bb37b5 3122intel_float_operand (const char *mnemonic)
252b5132 3123{
9306ca4a
JB		 3124 /* Note that the value returned is meaningful only for opcodes with (memory)
3125 operands, hence the code here is free to improperly handle opcodes that
3126 have no operands (for better performance and smaller code). */
3127
3128 if (mnemonic[0] != 'f')
3129 return 0; /* non-math */
3130
3131 switch (mnemonic[1])
3132 {
3133 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3134 the fs segment override prefix not currently handled because no
3135 call path can make opcodes without operands get here */
3136 case 'i':
3137 return 2 /* integer op */;
3138 case 'l':
3139 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3140 return 3; /* fldcw/fldenv */
3141 break;
3142 case 'n':
3143 if (mnemonic[2] != 'o' /* fnop */)
3144 return 3; /* non-waiting control op */
3145 break;
3146 case 'r':
3147 if (mnemonic[2] == 's')
3148 return 3; /* frstor/frstpm */
3149 break;
3150 case 's':
3151 if (mnemonic[2] == 'a')
3152 return 3; /* fsave */
3153 if (mnemonic[2] == 't')
3154 {
3155 switch (mnemonic[3])
3156 {
3157 case 'c': /* fstcw */
3158 case 'd': /* fstdw */
3159 case 'e': /* fstenv */
3160 case 's': /* fsts[gw] */
3161 return 3;
3162 }
3163 }
3164 break;
3165 case 'x':
3166 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3167 return 0; /* fxsave/fxrstor are not really math ops */
3168 break;
3169 }
252b5132 3170
9306ca4a 3171 return 1;
252b5132
RH		 3172}
3173
c0f3af97
L		 3174/* Build the VEX prefix. */
3175
3176static void
d3ce72d0 3177build_vex_prefix (const insn_template *t)
c0f3af97
L		 3178{
3179 unsigned int register_specifier;
3180 unsigned int implied_prefix;
3181 unsigned int vector_length;
3182
3183 /* Check register specifier. */
3184 if (i.vex.register_specifier)
43234a1e
L		 3185 {
3186 register_specifier =
3187 ~register_number (i.vex.register_specifier) & 0xf;
3188 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3189 }
c0f3af97
L		 3190 else
3191 register_specifier = 0xf;
3192
33eaf5de 3193 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3194 operand. */
86fa6981
L		 3195 if (i.vec_encoding != vex_encoding_vex3
3196 && i.dir_encoding == dir_encoding_default
fa99fab2 3197 && i.operands == i.reg_operands
7f399153 3198 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3199 && i.tm.opcode_modifier.load
fa99fab2
L		 3200 && i.rex == REX_B)
3201 {
3202 unsigned int xchg = i.operands - 1;
3203 union i386_op temp_op;
3204 i386_operand_type temp_type;
3205
3206 temp_type = i.types[xchg];
3207 i.types[xchg] = i.types[0];
3208 i.types[0] = temp_type;
3209 temp_op = i.op[xchg];
3210 i.op[xchg] = i.op[0];
3211 i.op[0] = temp_op;
3212
9c2799c2 3213 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3214
3215 i.rex = REX_R;
3216 xchg = i.rm.regmem;
3217 i.rm.regmem = i.rm.reg;
3218 i.rm.reg = xchg;
3219
3220 /* Use the next insn. */
3221 i.tm = t[1];
3222 }
3223
539f890d
L		 3224 if (i.tm.opcode_modifier.vex == VEXScalar)
3225 vector_length = avxscalar;
3226 else
3227 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3228
3229 switch ((i.tm.base_opcode >> 8) & 0xff)
3230 {
3231 case 0:
3232 implied_prefix = 0;
3233 break;
3234 case DATA_PREFIX_OPCODE:
3235 implied_prefix = 1;
3236 break;
3237 case REPE_PREFIX_OPCODE:
3238 implied_prefix = 2;
3239 break;
3240 case REPNE_PREFIX_OPCODE:
3241 implied_prefix = 3;
3242 break;
3243 default:
3244 abort ();
3245 }
3246
3247 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3248 if (i.vec_encoding != vex_encoding_vex3
3249 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3250 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3251 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3252 {
3253 /* 2-byte VEX prefix. */
3254 unsigned int r;
3255
3256 i.vex.length = 2;
3257 i.vex.bytes[0] = 0xc5;
3258
3259 /* Check the REX.R bit. */
3260 r = (i.rex & REX_R) ? 0 : 1;
3261 i.vex.bytes[1] = (r << 7
3262 | register_specifier << 3
3263 | vector_length << 2
3264 | implied_prefix);
3265 }
3266 else
3267 {
3268 /* 3-byte VEX prefix. */
3269 unsigned int m, w;
3270
f88c9eb0 3271 i.vex.length = 3;
f88c9eb0 3272
7f399153 3273 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3274 {
7f399153
L		 3275 case VEX0F:
3276 m = 0x1;
80de6e00 3277 i.vex.bytes[0] = 0xc4;
7f399153
L		 3278 break;
3279 case VEX0F38:
3280 m = 0x2;
80de6e00 3281 i.vex.bytes[0] = 0xc4;
7f399153
L		 3282 break;
3283 case VEX0F3A:
3284 m = 0x3;
80de6e00 3285 i.vex.bytes[0] = 0xc4;
7f399153
L		 3286 break;
3287 case XOP08:
5dd85c99
SP		 3288 m = 0x8;
3289 i.vex.bytes[0] = 0x8f;
7f399153
L		 3290 break;
3291 case XOP09:
f88c9eb0
SP		 3292 m = 0x9;
3293 i.vex.bytes[0] = 0x8f;
7f399153
L		 3294 break;
3295 case XOP0A:
f88c9eb0
SP		 3296 m = 0xa;
3297 i.vex.bytes[0] = 0x8f;
7f399153
L		 3298 break;
3299 default:
3300 abort ();
f88c9eb0 3301 }
c0f3af97 3302
c0f3af97
L		 3303 /* The high 3 bits of the second VEX byte are 1's compliment
3304 of RXB bits from REX. */
3305 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3306
3307 /* Check the REX.W bit. */
3308 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3309 if (i.tm.opcode_modifier.vexw == VEXW1)
3310 w = 1;
c0f3af97
L		 3311
3312 i.vex.bytes[2] = (w << 7
3313 | register_specifier << 3
3314 | vector_length << 2
3315 | implied_prefix);
3316 }
3317}
3318
43234a1e
L		 3319/* Build the EVEX prefix. */
3320
3321static void
3322build_evex_prefix (void)
3323{
3324 unsigned int register_specifier;
3325 unsigned int implied_prefix;
3326 unsigned int m, w;
3327 rex_byte vrex_used = 0;
3328
3329 /* Check register specifier. */
3330 if (i.vex.register_specifier)
3331 {
3332 gas_assert ((i.vrex & REX_X) == 0);
3333
3334 register_specifier = i.vex.register_specifier->reg_num;
3335 if ((i.vex.register_specifier->reg_flags & RegRex))
3336 register_specifier += 8;
3337 /* The upper 16 registers are encoded in the fourth byte of the
3338 EVEX prefix. */
3339 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3340 i.vex.bytes[3] = 0x8;
3341 register_specifier = ~register_specifier & 0xf;
3342 }
3343 else
3344 {
3345 register_specifier = 0xf;
3346
3347 /* Encode upper 16 vector index register in the fourth byte of
3348 the EVEX prefix. */
3349 if (!(i.vrex & REX_X))
3350 i.vex.bytes[3] = 0x8;
3351 else
3352 vrex_used |= REX_X;
3353 }
3354
3355 switch ((i.tm.base_opcode >> 8) & 0xff)
3356 {
3357 case 0:
3358 implied_prefix = 0;
3359 break;
3360 case DATA_PREFIX_OPCODE:
3361 implied_prefix = 1;
3362 break;
3363 case REPE_PREFIX_OPCODE:
3364 implied_prefix = 2;
3365 break;
3366 case REPNE_PREFIX_OPCODE:
3367 implied_prefix = 3;
3368 break;
3369 default:
3370 abort ();
3371 }
3372
3373 /* 4 byte EVEX prefix. */
3374 i.vex.length = 4;
3375 i.vex.bytes[0] = 0x62;
3376
3377 /* mmmm bits. */
3378 switch (i.tm.opcode_modifier.vexopcode)
3379 {
3380 case VEX0F:
3381 m = 1;
3382 break;
3383 case VEX0F38:
3384 m = 2;
3385 break;
3386 case VEX0F3A:
3387 m = 3;
3388 break;
3389 default:
3390 abort ();
3391 break;
3392 }
3393
3394 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3395 bits from REX. */
3396 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3397
3398 /* The fifth bit of the second EVEX byte is 1's compliment of the
3399 REX_R bit in VREX. */
3400 if (!(i.vrex & REX_R))
3401 i.vex.bytes[1] |= 0x10;
3402 else
3403 vrex_used |= REX_R;
3404
3405 if ((i.reg_operands + i.imm_operands) == i.operands)
3406 {
3407 /* When all operands are registers, the REX_X bit in REX is not
3408 used. We reuse it to encode the upper 16 registers, which is
3409 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3410 as 1's compliment. */
3411 if ((i.vrex & REX_B))
3412 {
3413 vrex_used |= REX_B;
3414 i.vex.bytes[1] &= ~0x40;
3415 }
3416 }
3417
3418 /* EVEX instructions shouldn't need the REX prefix. */
3419 i.vrex &= ~vrex_used;
3420 gas_assert (i.vrex == 0);
3421
3422 /* Check the REX.W bit. */
3423 w = (i.rex & REX_W) ? 1 : 0;
3424 if (i.tm.opcode_modifier.vexw)
3425 {
3426 if (i.tm.opcode_modifier.vexw == VEXW1)
3427 w = 1;
3428 }
3429 /* If w is not set it means we are dealing with WIG instruction. */
3430 else if (!w)
3431 {
3432 if (evexwig == evexw1)
3433 w = 1;
3434 }
3435
3436 /* Encode the U bit. */
3437 implied_prefix |= 0x4;
3438
3439 /* The third byte of the EVEX prefix. */
3440 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3441
3442 /* The fourth byte of the EVEX prefix. */
3443 /* The zeroing-masking bit. */
3444 if (i.mask && i.mask->zeroing)
3445 i.vex.bytes[3] |= 0x80;
3446
3447 /* Don't always set the broadcast bit if there is no RC. */
3448 if (!i.rounding)
3449 {
3450 /* Encode the vector length. */
3451 unsigned int vec_length;
3452
3453 switch (i.tm.opcode_modifier.evex)
3454 {
3455 case EVEXLIG: /* LL' is ignored */
3456 vec_length = evexlig << 5;
3457 break;
3458 case EVEX128:
3459 vec_length = 0 << 5;
3460 break;
3461 case EVEX256:
3462 vec_length = 1 << 5;
3463 break;
3464 case EVEX512:
3465 vec_length = 2 << 5;
3466 break;
3467 default:
3468 abort ();
3469 break;
3470 }
3471 i.vex.bytes[3] |= vec_length;
3472 /* Encode the broadcast bit. */
3473 if (i.broadcast)
3474 i.vex.bytes[3] |= 0x10;
3475 }
3476 else
3477 {
3478 if (i.rounding->type != saeonly)
3479 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3480 else
d3d3c6db 3481 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3482 }
3483
3484 if (i.mask && i.mask->mask)
3485 i.vex.bytes[3] |= i.mask->mask->reg_num;
3486}
3487
65da13b5
L		 3488static void
3489process_immext (void)
3490{
3491 expressionS *exp;
3492
4c692bc7
JB		 3493 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3494 && i.operands > 0)
65da13b5 3495 {
4c692bc7
JB		 3496 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3497 with an opcode suffix which is coded in the same place as an
3498 8-bit immediate field would be.
3499 Here we check those operands and remove them afterwards. */
65da13b5
L		 3500 unsigned int x;
3501
3502 for (x = 0; x < i.operands; x++)
4c692bc7 3503 if (register_number (i.op[x].regs) != x)
65da13b5 3504 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3505 register_prefix, i.op[x].regs->reg_name, x + 1,
3506 i.tm.name);
3507
3508 i.operands = 0;
65da13b5
L		 3509 }
3510
9916071f
AP		 3511 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3512 {
3513 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3514 suffix which is coded in the same place as an 8-bit immediate
3515 field would be.
3516 Here we check those operands and remove them afterwards. */
3517 unsigned int x;
3518
3519 if (i.operands != 3)
3520 abort();
3521
3522 for (x = 0; x < 2; x++)
3523 if (register_number (i.op[x].regs) != x)
3524 goto bad_register_operand;
3525
3526 /* Check for third operand for mwaitx/monitorx insn. */
3527 if (register_number (i.op[x].regs)
3528 != (x + (i.tm.extension_opcode == 0xfb)))
3529 {
3530bad_register_operand:
3531 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3532 register_prefix, i.op[x].regs->reg_name, x+1,
3533 i.tm.name);
3534 }
3535
3536 i.operands = 0;
3537 }
3538
c0f3af97 3539 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3540 which is coded in the same place as an 8-bit immediate field
3541 would be. Here we fake an 8-bit immediate operand from the
3542 opcode suffix stored in tm.extension_opcode.
3543
c1e679ec 3544 AVX instructions also use this encoding, for some of
c0f3af97 3545 3 argument instructions. */
65da13b5 3546
43234a1e 3547 gas_assert (i.imm_operands <= 1
7ab9ffdd 3548 && (i.operands <= 2
43234a1e
L		 3549 || ((i.tm.opcode_modifier.vex
3550 || i.tm.opcode_modifier.evex)
7ab9ffdd 3551 && i.operands <= 4)));
65da13b5
L		 3552
3553 exp = &im_expressions[i.imm_operands++];
3554 i.op[i.operands].imms = exp;
3555 i.types[i.operands] = imm8;
3556 i.operands++;
3557 exp->X_op = O_constant;
3558 exp->X_add_number = i.tm.extension_opcode;
3559 i.tm.extension_opcode = None;
3560}
3561
42164a71
L		 3562
3563static int
3564check_hle (void)
3565{
3566 switch (i.tm.opcode_modifier.hleprefixok)
3567 {
3568 default:
3569 abort ();
82c2def5 3570 case HLEPrefixNone:
165de32a
L		 3571 as_bad (_("invalid instruction `%s' after `%s'"),
3572 i.tm.name, i.hle_prefix);
42164a71 3573 return 0;
82c2def5 3574 case HLEPrefixLock:
42164a71
L		 3575 if (i.prefix[LOCK_PREFIX])
3576 return 1;
165de32a 3577 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3578 return 0;
82c2def5 3579 case HLEPrefixAny:
42164a71 3580 return 1;
82c2def5 3581 case HLEPrefixRelease:
42164a71
L		 3582 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3583 {
3584 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3585 i.tm.name);
3586 return 0;
3587 }
3588 if (i.mem_operands == 0
3589 || !operand_type_check (i.types[i.operands - 1], anymem))
3590 {
3591 as_bad (_("memory destination needed for instruction `%s'"
3592 " after `xrelease'"), i.tm.name);
3593 return 0;
3594 }
3595 return 1;
3596 }
3597}
3598
252b5132
RH		 3599/* This is the guts of the machine-dependent assembler. LINE points to a
3600 machine dependent instruction. This function is supposed to emit
3601 the frags/bytes it assembles to. */
3602
3603void
65da13b5 3604md_assemble (char *line)
252b5132 3605{
40fb9820 3606 unsigned int j;
83b16ac6 3607 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3608 const insn_template *t;
252b5132 3609
47926f60 3610 /* Initialize globals. */
252b5132
RH		 3611 memset (&i, '\0', sizeof (i));
3612 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3613 i.reloc[j] = NO_RELOC;
252b5132
RH		 3614 memset (disp_expressions, '\0', sizeof (disp_expressions));
3615 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3616 save_stack_p = save_stack;
252b5132
RH		 3617
3618 /* First parse an instruction mnemonic & call i386_operand for the operands.
3619 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3620 start of a (possibly prefixed) mnemonic. */
252b5132 3621
29b0f896
AM		 3622 line = parse_insn (line, mnemonic);
3623 if (line == NULL)
3624 return;
83b16ac6 3625 mnem_suffix = i.suffix;
252b5132 3626
29b0f896 3627 line = parse_operands (line, mnemonic);
ee86248c 3628 this_operand = -1;
8325cc63
JB		 3629 xfree (i.memop1_string);
3630 i.memop1_string = NULL;
29b0f896
AM		 3631 if (line == NULL)
3632 return;
252b5132 3633
29b0f896
AM		 3634 /* Now we've parsed the mnemonic into a set of templates, and have the
3635 operands at hand. */
3636
3637 /* All intel opcodes have reversed operands except for "bound" and
3638 "enter". We also don't reverse intersegment "jmp" and "call"
3639 instructions with 2 immediate operands so that the immediate segment
050dfa73 3640 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3641 if (intel_syntax
3642 && i.operands > 1
29b0f896 3643 && (strcmp (mnemonic, "bound") != 0)
30123838 3644 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3645 && !(operand_type_check (i.types[0], imm)
3646 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3647 swap_operands ();
3648
ec56d5c0
JB		 3649 /* The order of the immediates should be reversed
3650 for 2 immediates extrq and insertq instructions */
3651 if (i.imm_operands == 2
3652 && (strcmp (mnemonic, "extrq") == 0
3653 || strcmp (mnemonic, "insertq") == 0))
3654 swap_2_operands (0, 1);
3655
29b0f896
AM		 3656 if (i.imm_operands)
3657 optimize_imm ();
3658
b300c311
L		 3659 /* Don't optimize displacement for movabs since it only takes 64bit
3660 displacement. */
3661 if (i.disp_operands
a501d77e 3662 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3663 && (flag_code != CODE_64BIT
3664 || strcmp (mnemonic, "movabs") != 0))
3665 optimize_disp ();
29b0f896
AM		 3666
3667 /* Next, we find a template that matches the given insn,
3668 making sure the overlap of the given operands types is consistent
3669 with the template operand types. */
252b5132 3670
83b16ac6 3671 if (!(t = match_template (mnem_suffix)))
29b0f896 3672 return;
252b5132 3673
7bab8ab5 3674 if (sse_check != check_none
81f8a913 3675 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3676 && (i.tm.cpu_flags.bitfield.cpusse
3677 || i.tm.cpu_flags.bitfield.cpusse2
3678 || i.tm.cpu_flags.bitfield.cpusse3
3679 || i.tm.cpu_flags.bitfield.cpussse3
3680 || i.tm.cpu_flags.bitfield.cpusse4_1
3681 || i.tm.cpu_flags.bitfield.cpusse4_2))
3682 {
7bab8ab5 3683 (sse_check == check_warning
daf50ae7
L		 3684 ? as_warn
3685 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3686 }
3687
321fd21e
L		 3688 /* Zap movzx and movsx suffix. The suffix has been set from
3689 "word ptr" or "byte ptr" on the source operand in Intel syntax
3690 or extracted from mnemonic in AT&T syntax. But we'll use
3691 the destination register to choose the suffix for encoding. */
3692 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3693 {
321fd21e
L		 3694 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3695 there is no suffix, the default will be byte extension. */
3696 if (i.reg_operands != 2
3697 && !i.suffix
7ab9ffdd 3698 && intel_syntax)
321fd21e
L		 3699 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3700
3701 i.suffix = 0;
cd61ebfe 3702 }
24eab124 3703
40fb9820 3704 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3705 if (!add_prefix (FWAIT_OPCODE))
3706 return;
252b5132 3707
d5de92cf
L		 3708 /* Check if REP prefix is OK. */
3709 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3710 {
3711 as_bad (_("invalid instruction `%s' after `%s'"),
3712 i.tm.name, i.rep_prefix);
3713 return;
3714 }
3715
c1ba0266
L		 3716 /* Check for lock without a lockable instruction. Destination operand
3717 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3718 if (i.prefix[LOCK_PREFIX]
3719 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3720 || i.mem_operands == 0
3721 || (i.tm.base_opcode != 0x86
3722 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3723 {
3724 as_bad (_("expecting lockable instruction after `lock'"));
3725 return;
3726 }
3727
42164a71 3728 /* Check if HLE prefix is OK. */
165de32a 3729 if (i.hle_prefix && !check_hle ())
42164a71
L		 3730 return;
3731
7e8b059b
L		 3732 /* Check BND prefix. */
3733 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3734 as_bad (_("expecting valid branch instruction after `bnd'"));
3735
04ef582a 3736 /* Check NOTRACK prefix. */
9fef80d6
L		 3737 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3738 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3739
327e8c42
JB		 3740 if (i.tm.cpu_flags.bitfield.cpumpx)
3741 {
3742 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3743 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3744 else if (flag_code != CODE_16BIT
3745 ? i.prefix[ADDR_PREFIX]
3746 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3747 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3748 }
7e8b059b
L		 3749
3750 /* Insert BND prefix. */
3751 if (add_bnd_prefix
3752 && i.tm.opcode_modifier.bndprefixok
3753 && !i.prefix[BND_PREFIX])
3754 add_prefix (BND_PREFIX_OPCODE);
3755
29b0f896 3756 /* Check string instruction segment overrides. */
40fb9820 3757 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3758 {
3759 if (!check_string ())
5dd0794d 3760 return;
fc0763e6 3761 i.disp_operands = 0;
29b0f896 3762 }
5dd0794d 3763
29b0f896
AM		 3764 if (!process_suffix ())
3765 return;
e413e4e9 3766
bc0844ae
L		 3767 /* Update operand types. */
3768 for (j = 0; j < i.operands; j++)
3769 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3770
29b0f896
AM		 3771 /* Make still unresolved immediate matches conform to size of immediate
3772 given in i.suffix. */
3773 if (!finalize_imm ())
3774 return;
252b5132 3775
40fb9820 3776 if (i.types[0].bitfield.imm1)
29b0f896 3777 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3778
9afe6eb8
L		 3779 /* We only need to check those implicit registers for instructions
3780 with 3 operands or less. */
3781 if (i.operands <= 3)
3782 for (j = 0; j < i.operands; j++)
3783 if (i.types[j].bitfield.inoutportreg
3784 || i.types[j].bitfield.shiftcount
3785 || i.types[j].bitfield.acc
3786 || i.types[j].bitfield.floatacc)
3787 i.reg_operands--;
40fb9820 3788
c0f3af97
L		 3789 /* ImmExt should be processed after SSE2AVX. */
3790 if (!i.tm.opcode_modifier.sse2avx
3791 && i.tm.opcode_modifier.immext)
65da13b5 3792 process_immext ();
252b5132 3793
29b0f896
AM		 3794 /* For insns with operands there are more diddles to do to the opcode. */
3795 if (i.operands)
3796 {
3797 if (!process_operands ())
3798 return;
3799 }
40fb9820 3800 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3801 {
3802 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3803 as_warn (_("translating to `%sp'"), i.tm.name);
3804 }
252b5132 3805
9e5e5283
L		 3806 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3807 {
3808 if (flag_code == CODE_16BIT)
3809 {
3810 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3811 i.tm.name);
3812 return;
3813 }
c0f3af97 3814
9e5e5283
L		 3815 if (i.tm.opcode_modifier.vex)
3816 build_vex_prefix (t);
3817 else
3818 build_evex_prefix ();
3819 }
43234a1e 3820
5dd85c99
SP		 3821 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3822 instructions may define INT_OPCODE as well, so avoid this corner
3823 case for those instructions that use MODRM. */
3824 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3825 && !i.tm.opcode_modifier.modrm
3826 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3827 {
3828 i.tm.base_opcode = INT3_OPCODE;
3829 i.imm_operands = 0;
3830 }
252b5132 3831
40fb9820
L		 3832 if ((i.tm.opcode_modifier.jump
3833 || i.tm.opcode_modifier.jumpbyte
3834 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3835 && i.op[0].disps->X_op == O_constant)
3836 {
3837 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3838 the absolute address given by the constant. Since ix86 jumps and
3839 calls are pc relative, we need to generate a reloc. */
3840 i.op[0].disps->X_add_symbol = &abs_symbol;
3841 i.op[0].disps->X_op = O_symbol;
3842 }
252b5132 3843
40fb9820 3844 if (i.tm.opcode_modifier.rex64)
161a04f6 3845 i.rex |= REX_W;
252b5132 3846
29b0f896
AM		 3847 /* For 8 bit registers we need an empty rex prefix. Also if the
3848 instruction already has a prefix, we need to convert old
3849 registers to new ones. */
773f551c 3850
40fb9820 3851 if ((i.types[0].bitfield.reg8
29b0f896 3852 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3853 || (i.types[1].bitfield.reg8
29b0f896 3854 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3855 || ((i.types[0].bitfield.reg8
3856 || i.types[1].bitfield.reg8)
29b0f896
AM		 3857 && i.rex != 0))
3858 {
3859 int x;
726c5dcd 3860
29b0f896
AM		 3861 i.rex |= REX_OPCODE;
3862 for (x = 0; x < 2; x++)
3863 {
3864 /* Look for 8 bit operand that uses old registers. */
40fb9820 3865 if (i.types[x].bitfield.reg8
29b0f896 3866 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3867 {
29b0f896
AM		 3868 /* In case it is "hi" register, give up. */
3869 if (i.op[x].regs->reg_num > 3)
a540244d 3870 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3871 "instruction requiring REX prefix."),
a540244d 3872 register_prefix, i.op[x].regs->reg_name);
773f551c 3873
29b0f896
AM		 3874 /* Otherwise it is equivalent to the extended register.
3875 Since the encoding doesn't change this is merely
3876 cosmetic cleanup for debug output. */
3877
3878 i.op[x].regs = i.op[x].regs + 8;
773f551c 3879 }
29b0f896
AM		 3880 }
3881 }
773f551c 3882
7ab9ffdd 3883 if (i.rex != 0)
29b0f896
AM		 3884 add_prefix (REX_OPCODE | i.rex);
3885
3886 /* We are ready to output the insn. */
3887 output_insn ();
3888}
3889
3890static char *
e3bb37b5 3891parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3892{
3893 char *l = line;
3894 char *token_start = l;
3895 char *mnem_p;
5c6af06e 3896 int supported;
d3ce72d0 3897 const insn_template *t;
b6169b20 3898 char *dot_p = NULL;
29b0f896 3899
29b0f896
AM		 3900 while (1)
3901 {
3902 mnem_p = mnemonic;
3903 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3904 {
b6169b20
L		 3905 if (*mnem_p == '.')
3906 dot_p = mnem_p;
29b0f896
AM		 3907 mnem_p++;
3908 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3909 {
29b0f896
AM		 3910 as_bad (_("no such instruction: `%s'"), token_start);
3911 return NULL;
3912 }
3913 l++;
3914 }
3915 if (!is_space_char (*l)
3916 && *l != END_OF_INSN
e44823cf
JB		 3917 && (intel_syntax
3918 || (*l != PREFIX_SEPARATOR
3919 && *l != ',')))
29b0f896
AM		 3920 {
3921 as_bad (_("invalid character %s in mnemonic"),
3922 output_invalid (*l));
3923 return NULL;
3924 }
3925 if (token_start == l)
3926 {
e44823cf 3927 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3928 as_bad (_("expecting prefix; got nothing"));
3929 else
3930 as_bad (_("expecting mnemonic; got nothing"));
3931 return NULL;
3932 }
45288df1 3933
29b0f896 3934 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3935 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3936
29b0f896
AM		 3937 if (*l != END_OF_INSN
3938 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3939 && current_templates
40fb9820 3940 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3941 {
c6fb90c8 3942 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3943 {
3944 as_bad ((flag_code != CODE_64BIT
3945 ? _("`%s' is only supported in 64-bit mode")
3946 : _("`%s' is not supported in 64-bit mode")),
3947 current_templates->start->name);
3948 return NULL;
3949 }
29b0f896
AM		 3950 /* If we are in 16-bit mode, do not allow addr16 or data16.
3951 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3952 if ((current_templates->start->opcode_modifier.size16
3953 || current_templates->start->opcode_modifier.size32)
29b0f896 3954 && flag_code != CODE_64BIT
40fb9820 3955 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3956 ^ (flag_code == CODE_16BIT)))
3957 {
3958 as_bad (_("redundant %s prefix"),
3959 current_templates->start->name);
3960 return NULL;
45288df1 3961 }
86fa6981 3962 if (current_templates->start->opcode_length == 0)
29b0f896 3963 {
86fa6981
L		 3964 /* Handle pseudo prefixes. */
3965 switch (current_templates->start->base_opcode)
3966 {
3967 case 0x0:
3968 /* {disp8} */
3969 i.disp_encoding = disp_encoding_8bit;
3970 break;
3971 case 0x1:
3972 /* {disp32} */
3973 i.disp_encoding = disp_encoding_32bit;
3974 break;
3975 case 0x2:
3976 /* {load} */
3977 i.dir_encoding = dir_encoding_load;
3978 break;
3979 case 0x3:
3980 /* {store} */
3981 i.dir_encoding = dir_encoding_store;
3982 break;
3983 case 0x4:
3984 /* {vex2} */
3985 i.vec_encoding = vex_encoding_vex2;
3986 break;
3987 case 0x5:
3988 /* {vex3} */
3989 i.vec_encoding = vex_encoding_vex3;
3990 break;
3991 case 0x6:
3992 /* {evex} */
3993 i.vec_encoding = vex_encoding_evex;
3994 break;
3995 default:
3996 abort ();
3997 }
3998 }
3999 else
4000 {
4001 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4002 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4003 {
4e9ac44a
L		 4004 case PREFIX_EXIST:
4005 return NULL;
4006 case PREFIX_DS:
4007 if (current_templates->start->cpu_flags.bitfield.cpucet)
4008 i.notrack_prefix = current_templates->start->name;
4009 break;
4010 case PREFIX_REP:
4011 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4012 i.hle_prefix = current_templates->start->name;
4013 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4014 i.bnd_prefix = current_templates->start->name;
4015 else
4016 i.rep_prefix = current_templates->start->name;
4017 break;
4018 default:
4019 break;
86fa6981 4020 }
29b0f896
AM		 4021 }
4022 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4023 token_start = ++l;
4024 }
4025 else
4026 break;
4027 }
45288df1 4028
30a55f88 4029 if (!current_templates)
b6169b20 4030 {
f8a5c266
L		 4031 /* Check if we should swap operand or force 32bit displacement in
4032 encoding. */
30a55f88 4033 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4034 i.dir_encoding = dir_encoding_store;
8d63c93e 4035 else if (mnem_p - 3 == dot_p
a501d77e
L		 4036 && dot_p[1] == 'd'
4037 && dot_p[2] == '8')
4038 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4039 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4040 && dot_p[1] == 'd'
4041 && dot_p[2] == '3'
4042 && dot_p[3] == '2')
a501d77e 4043 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4044 else
4045 goto check_suffix;
4046 mnem_p = dot_p;
4047 *dot_p = '\0';
d3ce72d0 4048 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4049 }
4050
29b0f896
AM		 4051 if (!current_templates)
4052 {
b6169b20 4053check_suffix:
29b0f896
AM		 4054 /* See if we can get a match by trimming off a suffix. */
4055 switch (mnem_p[-1])
4056 {
4057 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4058 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4059 i.suffix = SHORT_MNEM_SUFFIX;
4060 else
1a0670f3 4061 /* Fall through. */
29b0f896
AM		 4062 case BYTE_MNEM_SUFFIX:
4063 case QWORD_MNEM_SUFFIX:
4064 i.suffix = mnem_p[-1];
4065 mnem_p[-1] = '\0';
d3ce72d0
NC		 4066 current_templates = (const templates *) hash_find (op_hash,
4067 mnemonic);
29b0f896
AM		 4068 break;
4069 case SHORT_MNEM_SUFFIX:
4070 case LONG_MNEM_SUFFIX:
4071 if (!intel_syntax)
4072 {
4073 i.suffix = mnem_p[-1];
4074 mnem_p[-1] = '\0';
d3ce72d0
NC		 4075 current_templates = (const templates *) hash_find (op_hash,
4076 mnemonic);
29b0f896
AM		 4077 }
4078 break;
252b5132 4079
29b0f896
AM		 4080 /* Intel Syntax. */
4081 case 'd':
4082 if (intel_syntax)
4083 {
9306ca4a 4084 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4085 i.suffix = SHORT_MNEM_SUFFIX;
4086 else
4087 i.suffix = LONG_MNEM_SUFFIX;
4088 mnem_p[-1] = '\0';
d3ce72d0
NC		 4089 current_templates = (const templates *) hash_find (op_hash,
4090 mnemonic);
29b0f896
AM		 4091 }
4092 break;
4093 }
4094 if (!current_templates)
4095 {
4096 as_bad (_("no such instruction: `%s'"), token_start);
4097 return NULL;
4098 }
4099 }
252b5132 4100
40fb9820
L		 4101 if (current_templates->start->opcode_modifier.jump
4102 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4103 {
4104 /* Check for a branch hint. We allow ",pt" and ",pn" for
4105 predict taken and predict not taken respectively.
4106 I'm not sure that branch hints actually do anything on loop
4107 and jcxz insns (JumpByte) for current Pentium4 chips. They
4108 may work in the future and it doesn't hurt to accept them
4109 now. */
4110 if (l[0] == ',' && l[1] == 'p')
4111 {
4112 if (l[2] == 't')
4113 {
4114 if (!add_prefix (DS_PREFIX_OPCODE))
4115 return NULL;
4116 l += 3;
4117 }
4118 else if (l[2] == 'n')
4119 {
4120 if (!add_prefix (CS_PREFIX_OPCODE))
4121 return NULL;
4122 l += 3;
4123 }
4124 }
4125 }
4126 /* Any other comma loses. */
4127 if (*l == ',')
4128 {
4129 as_bad (_("invalid character %s in mnemonic"),
4130 output_invalid (*l));
4131 return NULL;
4132 }
252b5132 4133
29b0f896 4134 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4135 supported = 0;
4136 for (t = current_templates->start; t < current_templates->end; ++t)
4137 {
c0f3af97
L		 4138 supported |= cpu_flags_match (t);
4139 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4140 goto skip;
5c6af06e 4141 }
3629bb00 4142
c0f3af97 4143 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4144 {
4145 as_bad (flag_code == CODE_64BIT
4146 ? _("`%s' is not supported in 64-bit mode")
4147 : _("`%s' is only supported in 64-bit mode"),
4148 current_templates->start->name);
4149 return NULL;
4150 }
c0f3af97 4151 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4152 {
3629bb00 4153 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4154 current_templates->start->name,
41aacd83 4155 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4156 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4157 return NULL;
29b0f896 4158 }
3629bb00
L		 4159
4160skip:
4161 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4162 && (flag_code != CODE_16BIT))
29b0f896
AM		 4163 {
4164 as_warn (_("use .code16 to ensure correct addressing mode"));
4165 }
252b5132 4166
29b0f896
AM		 4167 return l;
4168}
252b5132 4169
29b0f896 4170static char *
e3bb37b5 4171parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4172{
4173 char *token_start;
3138f287 4174
29b0f896
AM		 4175 /* 1 if operand is pending after ','. */
4176 unsigned int expecting_operand = 0;
252b5132 4177
29b0f896
AM		 4178 /* Non-zero if operand parens not balanced. */
4179 unsigned int paren_not_balanced;
4180
4181 while (*l != END_OF_INSN)
4182 {
4183 /* Skip optional white space before operand. */
4184 if (is_space_char (*l))
4185 ++l;
d02603dc 4186 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4187 {
4188 as_bad (_("invalid character %s before operand %d"),
4189 output_invalid (*l),
4190 i.operands + 1);
4191 return NULL;
4192 }
d02603dc 4193 token_start = l; /* After white space. */
29b0f896
AM		 4194 paren_not_balanced = 0;
4195 while (paren_not_balanced || *l != ',')
4196 {
4197 if (*l == END_OF_INSN)
4198 {
4199 if (paren_not_balanced)
4200 {
4201 if (!intel_syntax)
4202 as_bad (_("unbalanced parenthesis in operand %d."),
4203 i.operands + 1);
4204 else
4205 as_bad (_("unbalanced brackets in operand %d."),
4206 i.operands + 1);
4207 return NULL;
4208 }
4209 else
4210 break; /* we are done */
4211 }
d02603dc 4212 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4213 {
4214 as_bad (_("invalid character %s in operand %d"),
4215 output_invalid (*l),
4216 i.operands + 1);
4217 return NULL;
4218 }
4219 if (!intel_syntax)
4220 {
4221 if (*l == '(')
4222 ++paren_not_balanced;
4223 if (*l == ')')
4224 --paren_not_balanced;
4225 }
4226 else
4227 {
4228 if (*l == '[')
4229 ++paren_not_balanced;
4230 if (*l == ']')
4231 --paren_not_balanced;
4232 }
4233 l++;
4234 }
4235 if (l != token_start)
4236 { /* Yes, we've read in another operand. */
4237 unsigned int operand_ok;
4238 this_operand = i.operands++;
4239 if (i.operands > MAX_OPERANDS)
4240 {
4241 as_bad (_("spurious operands; (%d operands/instruction max)"),
4242 MAX_OPERANDS);
4243 return NULL;
4244 }
9d46ce34 4245 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4246 /* Now parse operand adding info to 'i' as we go along. */
4247 END_STRING_AND_SAVE (l);
4248
4249 if (intel_syntax)
4250 operand_ok =
4251 i386_intel_operand (token_start,
4252 intel_float_operand (mnemonic));
4253 else
a7619375 4254 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4255
4256 RESTORE_END_STRING (l);
4257 if (!operand_ok)
4258 return NULL;
4259 }
4260 else
4261 {
4262 if (expecting_operand)
4263 {
4264 expecting_operand_after_comma:
4265 as_bad (_("expecting operand after ','; got nothing"));
4266 return NULL;
4267 }
4268 if (*l == ',')
4269 {
4270 as_bad (_("expecting operand before ','; got nothing"));
4271 return NULL;
4272 }
4273 }
7f3f1ea2 4274
29b0f896
AM		 4275 /* Now *l must be either ',' or END_OF_INSN. */
4276 if (*l == ',')
4277 {
4278 if (*++l == END_OF_INSN)
4279 {
4280 /* Just skip it, if it's \n complain. */
4281 goto expecting_operand_after_comma;
4282 }
4283 expecting_operand = 1;
4284 }
4285 }
4286 return l;
4287}
7f3f1ea2 4288
050dfa73 4289static void
4d456e3d 4290swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4291{
4292 union i386_op temp_op;
40fb9820 4293 i386_operand_type temp_type;
050dfa73 4294 enum bfd_reloc_code_real temp_reloc;
4eed87de 4295
050dfa73
MM		 4296 temp_type = i.types[xchg2];
4297 i.types[xchg2] = i.types[xchg1];
4298 i.types[xchg1] = temp_type;
4299 temp_op = i.op[xchg2];
4300 i.op[xchg2] = i.op[xchg1];
4301 i.op[xchg1] = temp_op;
4302 temp_reloc = i.reloc[xchg2];
4303 i.reloc[xchg2] = i.reloc[xchg1];
4304 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4305
4306 if (i.mask)
4307 {
4308 if (i.mask->operand == xchg1)
4309 i.mask->operand = xchg2;
4310 else if (i.mask->operand == xchg2)
4311 i.mask->operand = xchg1;
4312 }
4313 if (i.broadcast)
4314 {
4315 if (i.broadcast->operand == xchg1)
4316 i.broadcast->operand = xchg2;
4317 else if (i.broadcast->operand == xchg2)
4318 i.broadcast->operand = xchg1;
4319 }
4320 if (i.rounding)
4321 {
4322 if (i.rounding->operand == xchg1)
4323 i.rounding->operand = xchg2;
4324 else if (i.rounding->operand == xchg2)
4325 i.rounding->operand = xchg1;
4326 }
050dfa73
MM		 4327}
4328
29b0f896 4329static void
e3bb37b5 4330swap_operands (void)
29b0f896 4331{
b7c61d9a 4332 switch (i.operands)
050dfa73 4333 {
c0f3af97 4334 case 5:
b7c61d9a 4335 case 4:
4d456e3d 4336 swap_2_operands (1, i.operands - 2);
1a0670f3 4337 /* Fall through. */
b7c61d9a
L		 4338 case 3:
4339 case 2:
4d456e3d 4340 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4341 break;
4342 default:
4343 abort ();
29b0f896 4344 }
29b0f896
AM		 4345
4346 if (i.mem_operands == 2)
4347 {
4348 const seg_entry *temp_seg;
4349 temp_seg = i.seg[0];
4350 i.seg[0] = i.seg[1];
4351 i.seg[1] = temp_seg;
4352 }
4353}
252b5132 4354
29b0f896
AM		 4355/* Try to ensure constant immediates are represented in the smallest
4356 opcode possible. */
4357static void
e3bb37b5 4358optimize_imm (void)
29b0f896
AM		 4359{
4360 char guess_suffix = 0;
4361 int op;
252b5132 4362
29b0f896
AM		 4363 if (i.suffix)
4364 guess_suffix = i.suffix;
4365 else if (i.reg_operands)
4366 {
4367 /* Figure out a suffix from the last register operand specified.
4368 We can't do this properly yet, ie. excluding InOutPortReg,
4369 but the following works for instructions with immediates.
4370 In any case, we can't set i.suffix yet. */
4371 for (op = i.operands; --op >= 0;)
40fb9820 4372 if (i.types[op].bitfield.reg8)
7ab9ffdd 4373 {
40fb9820
L		 4374 guess_suffix = BYTE_MNEM_SUFFIX;
4375 break;
4376 }
4377 else if (i.types[op].bitfield.reg16)
252b5132 4378 {
40fb9820
L		 4379 guess_suffix = WORD_MNEM_SUFFIX;
4380 break;
4381 }
4382 else if (i.types[op].bitfield.reg32)
4383 {
4384 guess_suffix = LONG_MNEM_SUFFIX;
4385 break;
4386 }
4387 else if (i.types[op].bitfield.reg64)
4388 {
4389 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4390 break;
252b5132 4391 }
29b0f896
AM		 4392 }
4393 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4394 guess_suffix = WORD_MNEM_SUFFIX;
4395
4396 for (op = i.operands; --op >= 0;)
40fb9820 4397 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4398 {
4399 switch (i.op[op].imms->X_op)
252b5132 4400 {
29b0f896
AM		 4401 case O_constant:
4402 /* If a suffix is given, this operand may be shortened. */
4403 switch (guess_suffix)
252b5132 4404 {
29b0f896 4405 case LONG_MNEM_SUFFIX:
40fb9820
L		 4406 i.types[op].bitfield.imm32 = 1;
4407 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4408 break;
4409 case WORD_MNEM_SUFFIX:
40fb9820
L		 4410 i.types[op].bitfield.imm16 = 1;
4411 i.types[op].bitfield.imm32 = 1;
4412 i.types[op].bitfield.imm32s = 1;
4413 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4414 break;
4415 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4416 i.types[op].bitfield.imm8 = 1;
4417 i.types[op].bitfield.imm8s = 1;
4418 i.types[op].bitfield.imm16 = 1;
4419 i.types[op].bitfield.imm32 = 1;
4420 i.types[op].bitfield.imm32s = 1;
4421 i.types[op].bitfield.imm64 = 1;
29b0f896 4422 break;
252b5132 4423 }
252b5132 4424
29b0f896
AM		 4425 /* If this operand is at most 16 bits, convert it
4426 to a signed 16 bit number before trying to see
4427 whether it will fit in an even smaller size.
4428 This allows a 16-bit operand such as $0xffe0 to
4429 be recognised as within Imm8S range. */
40fb9820 4430 if ((i.types[op].bitfield.imm16)
29b0f896 4431 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4432 {
29b0f896
AM		 4433 i.op[op].imms->X_add_number =
4434 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4435 }
a28def75
L		 4436#ifdef BFD64
4437 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4438 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4439 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4440 == 0))
4441 {
4442 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4443 ^ ((offsetT) 1 << 31))
4444 - ((offsetT) 1 << 31));
4445 }
a28def75 4446#endif
40fb9820 4447 i.types[op]
c6fb90c8
L		 4448 = operand_type_or (i.types[op],
4449 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4450
29b0f896
AM		 4451 /* We must avoid matching of Imm32 templates when 64bit
4452 only immediate is available. */
4453 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4454 i.types[op].bitfield.imm32 = 0;
29b0f896 4455 break;
252b5132 4456
29b0f896
AM		 4457 case O_absent:
4458 case O_register:
4459 abort ();
4460
4461 /* Symbols and expressions. */
4462 default:
9cd96992
JB		 4463 /* Convert symbolic operand to proper sizes for matching, but don't
4464 prevent matching a set of insns that only supports sizes other
4465 than those matching the insn suffix. */
4466 {
40fb9820 4467 i386_operand_type mask, allowed;
d3ce72d0 4468 const insn_template *t;
9cd96992 4469
0dfbf9d7
L		 4470 operand_type_set (&mask, 0);
4471 operand_type_set (&allowed, 0);
40fb9820 4472
4eed87de
AM		 4473 for (t = current_templates->start;
4474 t < current_templates->end;
4475 ++t)
c6fb90c8
L		 4476 allowed = operand_type_or (allowed,
4477 t->operand_types[op]);
9cd96992
JB		 4478 switch (guess_suffix)
4479 {
4480 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4481 mask.bitfield.imm64 = 1;
4482 mask.bitfield.imm32s = 1;
9cd96992
JB		 4483 break;
4484 case LONG_MNEM_SUFFIX:
40fb9820 4485 mask.bitfield.imm32 = 1;
9cd96992
JB		 4486 break;
4487 case WORD_MNEM_SUFFIX:
40fb9820 4488 mask.bitfield.imm16 = 1;
9cd96992
JB		 4489 break;
4490 case BYTE_MNEM_SUFFIX:
40fb9820 4491 mask.bitfield.imm8 = 1;
9cd96992
JB		 4492 break;
4493 default:
9cd96992
JB		 4494 break;
4495 }
c6fb90c8 4496 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4497 if (!operand_type_all_zero (&allowed))
c6fb90c8 4498 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4499 }
29b0f896 4500 break;
252b5132 4501 }
29b0f896
AM		 4502 }
4503}
47926f60 4504
29b0f896
AM		 4505/* Try to use the smallest displacement type too. */
4506static void
e3bb37b5 4507optimize_disp (void)
29b0f896
AM		 4508{
4509 int op;
3e73aa7c 4510
29b0f896 4511 for (op = i.operands; --op >= 0;)
40fb9820 4512 if (operand_type_check (i.types[op], disp))
252b5132 4513 {
b300c311 4514 if (i.op[op].disps->X_op == O_constant)
252b5132 4515 {
91d6fa6a 4516 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4517
40fb9820 4518 if (i.types[op].bitfield.disp16
91d6fa6a 4519 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4520 {
4521 /* If this operand is at most 16 bits, convert
4522 to a signed 16 bit number and don't use 64bit
4523 displacement. */
91d6fa6a 4524 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4525 i.types[op].bitfield.disp64 = 0;
b300c311 4526 }
a28def75
L		 4527#ifdef BFD64
4528 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4529 if (i.types[op].bitfield.disp32
91d6fa6a 4530 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4531 {
4532 /* If this operand is at most 32 bits, convert
4533 to a signed 32 bit number and don't use 64bit
4534 displacement. */
91d6fa6a
NC		 4535 op_disp &= (((offsetT) 2 << 31) - 1);
4536 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4537 i.types[op].bitfield.disp64 = 0;
b300c311 4538 }
a28def75 4539#endif
91d6fa6a 4540 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4541 {
40fb9820
L		 4542 i.types[op].bitfield.disp8 = 0;
4543 i.types[op].bitfield.disp16 = 0;
4544 i.types[op].bitfield.disp32 = 0;
4545 i.types[op].bitfield.disp32s = 0;
4546 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4547 i.op[op].disps = 0;
4548 i.disp_operands--;
4549 }
4550 else if (flag_code == CODE_64BIT)
4551 {
91d6fa6a 4552 if (fits_in_signed_long (op_disp))
28a9d8f5 4553 {
40fb9820
L		 4554 i.types[op].bitfield.disp64 = 0;
4555 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4556 }
0e1147d9 4557 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4558 && fits_in_unsigned_long (op_disp))
40fb9820 4559 i.types[op].bitfield.disp32 = 1;
b300c311 4560 }
40fb9820
L		 4561 if ((i.types[op].bitfield.disp32
4562 || i.types[op].bitfield.disp32s
4563 || i.types[op].bitfield.disp16)
91d6fa6a 4564 && fits_in_signed_byte (op_disp))
40fb9820 4565 i.types[op].bitfield.disp8 = 1;
252b5132 4566 }
67a4f2b7
AO		 4567 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4568 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4569 {
4570 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4571 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4572 i.types[op].bitfield.disp8 = 0;
4573 i.types[op].bitfield.disp16 = 0;
4574 i.types[op].bitfield.disp32 = 0;
4575 i.types[op].bitfield.disp32s = 0;
4576 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4577 }
4578 else
b300c311 4579 /* We only support 64bit displacement on constants. */
40fb9820 4580 i.types[op].bitfield.disp64 = 0;
252b5132 4581 }
29b0f896
AM		 4582}
4583
6c30d220
L		 4584/* Check if operands are valid for the instruction. */
4585
4586static int
4587check_VecOperands (const insn_template *t)
4588{
43234a1e
L		 4589 unsigned int op;
4590
6c30d220
L		 4591 /* Without VSIB byte, we can't have a vector register for index. */
4592 if (!t->opcode_modifier.vecsib
4593 && i.index_reg
4594 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4595 || i.index_reg->reg_type.bitfield.regymm
4596 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4597 {
4598 i.error = unsupported_vector_index_register;
4599 return 1;
4600 }
4601
ad8ecc81
MZ		 4602 /* Check if default mask is allowed. */
4603 if (t->opcode_modifier.nodefmask
4604 && (!i.mask || i.mask->mask->reg_num == 0))
4605 {
4606 i.error = no_default_mask;
4607 return 1;
4608 }
4609
7bab8ab5
JB		 4610 /* For VSIB byte, we need a vector register for index, and all vector
4611 registers must be distinct. */
4612 if (t->opcode_modifier.vecsib)
4613 {
4614 if (!i.index_reg
6c30d220
L		 4615 || !((t->opcode_modifier.vecsib == VecSIB128
4616 && i.index_reg->reg_type.bitfield.regxmm)
4617 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4618 && i.index_reg->reg_type.bitfield.regymm)
4619 || (t->opcode_modifier.vecsib == VecSIB512
4620 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4621 {
4622 i.error = invalid_vsib_address;
4623 return 1;
4624 }
4625
43234a1e
L		 4626 gas_assert (i.reg_operands == 2 || i.mask);
4627 if (i.reg_operands == 2 && !i.mask)
4628 {
4629 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4630 || i.types[0].bitfield.regymm);
43234a1e 4631 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4632 || i.types[2].bitfield.regymm);
43234a1e
L		 4633 if (operand_check == check_none)
4634 return 0;
4635 if (register_number (i.op[0].regs)
4636 != register_number (i.index_reg)
4637 && register_number (i.op[2].regs)
4638 != register_number (i.index_reg)
4639 && register_number (i.op[0].regs)
4640 != register_number (i.op[2].regs))
4641 return 0;
4642 if (operand_check == check_error)
4643 {
4644 i.error = invalid_vector_register_set;
4645 return 1;
4646 }
4647 as_warn (_("mask, index, and destination registers should be distinct"));
4648 }
8444f82a
MZ		 4649 else if (i.reg_operands == 1 && i.mask)
4650 {
4651 if ((i.types[1].bitfield.regymm
4652 || i.types[1].bitfield.regzmm)
4653 && (register_number (i.op[1].regs)
4654 == register_number (i.index_reg)))
4655 {
4656 if (operand_check == check_error)
4657 {
4658 i.error = invalid_vector_register_set;
4659 return 1;
4660 }
4661 if (operand_check != check_none)
4662 as_warn (_("index and destination registers should be distinct"));
4663 }
4664 }
43234a1e 4665 }
7bab8ab5 4666
43234a1e
L		 4667 /* Check if broadcast is supported by the instruction and is applied
4668 to the memory operand. */
4669 if (i.broadcast)
4670 {
4671 int broadcasted_opnd_size;
4672
4673 /* Check if specified broadcast is supported in this instruction,
4674 and it's applied to memory operand of DWORD or QWORD type,
4675 depending on VecESize. */
4676 if (i.broadcast->type != t->opcode_modifier.broadcast
4677 || !i.types[i.broadcast->operand].bitfield.mem
4678 || (t->opcode_modifier.vecesize == 0
4679 && !i.types[i.broadcast->operand].bitfield.dword
4680 && !i.types[i.broadcast->operand].bitfield.unspecified)
4681 || (t->opcode_modifier.vecesize == 1
4682 && !i.types[i.broadcast->operand].bitfield.qword
4683 && !i.types[i.broadcast->operand].bitfield.unspecified))
4684 goto bad_broadcast;
4685
4686 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4687 if (i.broadcast->type == BROADCAST_1TO16)
4688 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4689 else if (i.broadcast->type == BROADCAST_1TO8)
4690 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4691 else if (i.broadcast->type == BROADCAST_1TO4)
4692 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4693 else if (i.broadcast->type == BROADCAST_1TO2)
4694 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4695 else
4696 goto bad_broadcast;
4697
4698 if ((broadcasted_opnd_size == 256
4699 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4700 || (broadcasted_opnd_size == 512
4701 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4702 {
4703 bad_broadcast:
4704 i.error = unsupported_broadcast;
4705 return 1;
4706 }
4707 }
4708 /* If broadcast is supported in this instruction, we need to check if
4709 operand of one-element size isn't specified without broadcast. */
4710 else if (t->opcode_modifier.broadcast && i.mem_operands)
4711 {
4712 /* Find memory operand. */
4713 for (op = 0; op < i.operands; op++)
4714 if (operand_type_check (i.types[op], anymem))
4715 break;
4716 gas_assert (op < i.operands);
4717 /* Check size of the memory operand. */
4718 if ((t->opcode_modifier.vecesize == 0
4719 && i.types[op].bitfield.dword)
4720 || (t->opcode_modifier.vecesize == 1
4721 && i.types[op].bitfield.qword))
4722 {
4723 i.error = broadcast_needed;
4724 return 1;
4725 }
4726 }
4727
4728 /* Check if requested masking is supported. */
4729 if (i.mask
4730 && (!t->opcode_modifier.masking
4731 || (i.mask->zeroing
4732 && t->opcode_modifier.masking == MERGING_MASKING)))
4733 {
4734 i.error = unsupported_masking;
4735 return 1;
4736 }
4737
4738 /* Check if masking is applied to dest operand. */
4739 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4740 {
4741 i.error = mask_not_on_destination;
4742 return 1;
4743 }
4744
43234a1e
L		 4745 /* Check RC/SAE. */
4746 if (i.rounding)
4747 {
4748 if ((i.rounding->type != saeonly
4749 && !t->opcode_modifier.staticrounding)
4750 || (i.rounding->type == saeonly
4751 && (t->opcode_modifier.staticrounding
4752 || !t->opcode_modifier.sae)))
4753 {
4754 i.error = unsupported_rc_sae;
4755 return 1;
4756 }
4757 /* If the instruction has several immediate operands and one of
4758 them is rounding, the rounding operand should be the last
4759 immediate operand. */
4760 if (i.imm_operands > 1
4761 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4762 {
43234a1e 4763 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4764 return 1;
4765 }
6c30d220
L		 4766 }
4767
43234a1e
L		 4768 /* Check vector Disp8 operand. */
4769 if (t->opcode_modifier.disp8memshift)
4770 {
4771 if (i.broadcast)
4772 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4773 else
4774 i.memshift = t->opcode_modifier.disp8memshift;
4775
4776 for (op = 0; op < i.operands; op++)
4777 if (operand_type_check (i.types[op], disp)
4778 && i.op[op].disps->X_op == O_constant)
4779 {
4780 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4781 int vec_disp8_ok
4782 = (i.disp_encoding != disp_encoding_32bit
4783 && fits_in_vec_disp8 (value));
43234a1e
L		 4784 if (t->operand_types [op].bitfield.vec_disp8)
4785 {
4786 if (vec_disp8_ok)
4787 i.types[op].bitfield.vec_disp8 = 1;
4788 else
4789 {
4790 /* Vector insn can only have Vec_Disp8/Disp32 in
4791 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4792 mode. */
4793 i.types[op].bitfield.disp8 = 0;
4794 if (flag_code != CODE_16BIT)
4795 i.types[op].bitfield.disp16 = 0;
4796 }
4797 }
4798 else if (flag_code != CODE_16BIT)
4799 {
4800 /* One form of this instruction supports vector Disp8.
4801 Try vector Disp8 if we need to use Disp32. */
4802 if (vec_disp8_ok && !fits_in_signed_byte (value))
4803 {
4804 i.error = try_vector_disp8;
4805 return 1;
4806 }
4807 }
4808 }
4809 }
4810 else
4811 i.memshift = -1;
4812
6c30d220
L		 4813 return 0;
4814}
4815
43f3e2ee 4816/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4817 operand types. */
4818
4819static int
4820VEX_check_operands (const insn_template *t)
4821{
86fa6981 4822 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4823 {
86fa6981
L		 4824 /* This instruction must be encoded with EVEX prefix. */
4825 if (!t->opcode_modifier.evex)
4826 {
4827 i.error = unsupported;
4828 return 1;
4829 }
4830 return 0;
43234a1e
L		 4831 }
4832
a683cc34 4833 if (!t->opcode_modifier.vex)
86fa6981
L		 4834 {
4835 /* This instruction template doesn't have VEX prefix. */
4836 if (i.vec_encoding != vex_encoding_default)
4837 {
4838 i.error = unsupported;
4839 return 1;
4840 }
4841 return 0;
4842 }
a683cc34
SP		 4843
4844 /* Only check VEX_Imm4, which must be the first operand. */
4845 if (t->operand_types[0].bitfield.vec_imm4)
4846 {
4847 if (i.op[0].imms->X_op != O_constant
4848 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4849 {
a65babc9 4850 i.error = bad_imm4;
891edac4
L		 4851 return 1;
4852 }
a683cc34
SP		 4853
4854 /* Turn off Imm8 so that update_imm won't complain. */
4855 i.types[0] = vec_imm4;
4856 }
4857
4858 return 0;
4859}
4860
d3ce72d0 4861static const insn_template *
83b16ac6 4862match_template (char mnem_suffix)
29b0f896
AM		 4863{
4864 /* Points to template once we've found it. */
d3ce72d0 4865 const insn_template *t;
40fb9820 4866 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4867 i386_operand_type overlap4;
29b0f896 4868 unsigned int found_reverse_match;
83b16ac6 4869 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4870 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4871 int addr_prefix_disp;
a5c311ca 4872 unsigned int j;
3629bb00 4873 unsigned int found_cpu_match;
45664ddb 4874 unsigned int check_register;
5614d22c 4875 enum i386_error specific_error = 0;
29b0f896 4876
c0f3af97
L		 4877#if MAX_OPERANDS != 5
4878# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4879#endif
4880
29b0f896 4881 found_reverse_match = 0;
539e75ad 4882 addr_prefix_disp = -1;
40fb9820
L		 4883
4884 memset (&suffix_check, 0, sizeof (suffix_check));
4885 if (i.suffix == BYTE_MNEM_SUFFIX)
4886 suffix_check.no_bsuf = 1;
4887 else if (i.suffix == WORD_MNEM_SUFFIX)
4888 suffix_check.no_wsuf = 1;
4889 else if (i.suffix == SHORT_MNEM_SUFFIX)
4890 suffix_check.no_ssuf = 1;
4891 else if (i.suffix == LONG_MNEM_SUFFIX)
4892 suffix_check.no_lsuf = 1;
4893 else if (i.suffix == QWORD_MNEM_SUFFIX)
4894 suffix_check.no_qsuf = 1;
4895 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4896 suffix_check.no_ldsuf = 1;
29b0f896 4897
83b16ac6
JB		 4898 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4899 if (intel_syntax)
4900 {
4901 switch (mnem_suffix)
4902 {
4903 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4904 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4905 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4906 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4907 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4908 }
4909 }
4910
01559ecc
L		 4911 /* Must have right number of operands. */
4912 i.error = number_of_operands_mismatch;
4913
45aa61fe 4914 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4915 {
539e75ad
L		 4916 addr_prefix_disp = -1;
4917
29b0f896
AM		 4918 if (i.operands != t->operands)
4919 continue;
4920
50aecf8c 4921 /* Check processor support. */
a65babc9 4922 i.error = unsupported;
c0f3af97
L		 4923 found_cpu_match = (cpu_flags_match (t)
4924 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4925 if (!found_cpu_match)
4926 continue;
4927
e1d4d893 4928 /* Check old gcc support. */
a65babc9 4929 i.error = old_gcc_only;
e1d4d893
L		 4930 if (!old_gcc && t->opcode_modifier.oldgcc)
4931 continue;
4932
4933 /* Check AT&T mnemonic. */
a65babc9 4934 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4935 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4936 continue;
4937
e92bae62 4938 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4939 i.error = unsupported_syntax;
5c07affc 4940 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4941 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4942 || (intel64 && t->opcode_modifier.amd64)
4943 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4944 continue;
4945
20592a94 4946 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4947 i.error = invalid_instruction_suffix;
567e4e96
L		 4948 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4949 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4950 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4951 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4952 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4953 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4954 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4955 continue;
83b16ac6
JB		 4956 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4957 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4958 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4959 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4960 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4961 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4962 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4963 continue;
29b0f896 4964
5c07affc 4965 if (!operand_size_match (t))
7d5e4556 4966 continue;
539e75ad 4967
5c07affc
L		 4968 for (j = 0; j < MAX_OPERANDS; j++)
4969 operand_types[j] = t->operand_types[j];
4970
45aa61fe
AM		 4971 /* In general, don't allow 64-bit operands in 32-bit mode. */
4972 if (i.suffix == QWORD_MNEM_SUFFIX
4973 && flag_code != CODE_64BIT
4974 && (intel_syntax
40fb9820 4975 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4976 && !intel_float_operand (t->name))
4977 : intel_float_operand (t->name) != 2)
40fb9820 4978 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4979 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4980 && !operand_types[0].bitfield.regymm
4981 && !operand_types[0].bitfield.regzmm)
40fb9820 4982 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4983 && operand_types[t->operands > 1].bitfield.regxmm
4984 && operand_types[t->operands > 1].bitfield.regymm
4985 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4986 && (t->base_opcode != 0x0fc7
4987 || t->extension_opcode != 1 /* cmpxchg8b */))
4988 continue;
4989
192dc9c6
JB		 4990 /* In general, don't allow 32-bit operands on pre-386. */
4991 else if (i.suffix == LONG_MNEM_SUFFIX
4992 && !cpu_arch_flags.bitfield.cpui386
4993 && (intel_syntax
4994 ? (!t->opcode_modifier.ignoresize
4995 && !intel_float_operand (t->name))
4996 : intel_float_operand (t->name) != 2)
4997 && ((!operand_types[0].bitfield.regmmx
4998 && !operand_types[0].bitfield.regxmm)
4999 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 5000 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 5001 continue;
5002
29b0f896 5003 /* Do not verify operands when there are none. */
50aecf8c 5004 else
29b0f896 5005 {
c6fb90c8 5006 if (!t->operands)
2dbab7d5
L		 5007 /* We've found a match; break out of loop. */
5008 break;
29b0f896 5009 }
252b5132 5010
539e75ad
L		 5011 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5012 into Disp32/Disp16/Disp32 operand. */
5013 if (i.prefix[ADDR_PREFIX] != 0)
5014 {
40fb9820 5015 /* There should be only one Disp operand. */
539e75ad
L		 5016 switch (flag_code)
5017 {
5018 case CODE_16BIT:
40fb9820
L		 5019 for (j = 0; j < MAX_OPERANDS; j++)
5020 {
5021 if (operand_types[j].bitfield.disp16)
5022 {
5023 addr_prefix_disp = j;
5024 operand_types[j].bitfield.disp32 = 1;
5025 operand_types[j].bitfield.disp16 = 0;
5026 break;
5027 }
5028 }
539e75ad
L		 5029 break;
5030 case CODE_32BIT:
40fb9820
L		 5031 for (j = 0; j < MAX_OPERANDS; j++)
5032 {
5033 if (operand_types[j].bitfield.disp32)
5034 {
5035 addr_prefix_disp = j;
5036 operand_types[j].bitfield.disp32 = 0;
5037 operand_types[j].bitfield.disp16 = 1;
5038 break;
5039 }
5040 }
539e75ad
L		 5041 break;
5042 case CODE_64BIT:
40fb9820
L		 5043 for (j = 0; j < MAX_OPERANDS; j++)
5044 {
5045 if (operand_types[j].bitfield.disp64)
5046 {
5047 addr_prefix_disp = j;
5048 operand_types[j].bitfield.disp64 = 0;
5049 operand_types[j].bitfield.disp32 = 1;
5050 break;
5051 }
5052 }
539e75ad
L		 5053 break;
5054 }
539e75ad
L		 5055 }
5056
02a86693
L		 5057 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5058 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5059 continue;
5060
56ffb741
L		 5061 /* We check register size if needed. */
5062 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5063 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5064 switch (t->operands)
5065 {
5066 case 1:
40fb9820 5067 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5068 continue;
5069 break;
5070 case 2:
33eaf5de 5071 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5072 only in 32bit mode and we can use opcode 0x90. In 64bit
5073 mode, we can't use 0x90 for xchg %eax, %eax since it should
5074 zero-extend %eax to %rax. */
5075 if (flag_code == CODE_64BIT
5076 && t->base_opcode == 0x90
0dfbf9d7
L		 5077 && operand_type_equal (&i.types [0], &acc32)
5078 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5079 continue;
86fa6981
L		 5080 /* If we want store form, we reverse direction of operands. */
5081 if (i.dir_encoding == dir_encoding_store
5082 && t->opcode_modifier.d)
5083 goto check_reverse;
1a0670f3 5084 /* Fall through. */
b6169b20 5085
29b0f896 5086 case 3:
86fa6981
L		 5087 /* If we want store form, we skip the current load. */
5088 if (i.dir_encoding == dir_encoding_store
5089 && i.mem_operands == 0
5090 && t->opcode_modifier.load)
fa99fab2 5091 continue;
1a0670f3 5092 /* Fall through. */
f48ff2ae 5093 case 4:
c0f3af97 5094 case 5:
c6fb90c8 5095 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5096 if (!operand_type_match (overlap0, i.types[0])
5097 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5098 || (check_register
5099 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 5100 operand_types[0],
5101 overlap1, i.types[1],
5102 operand_types[1])))
29b0f896
AM		 5103 {
5104 /* Check if other direction is valid ... */
40fb9820 5105 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5106 continue;
5107
b6169b20 5108check_reverse:
29b0f896 5109 /* Try reversing direction of operands. */
c6fb90c8
L		 5110 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5111 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5112 if (!operand_type_match (overlap0, i.types[0])
5113 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5114 || (check_register
5115 && !operand_type_register_match (overlap0,
5116 i.types[0],
5117 operand_types[1],
5118 overlap1,
5119 i.types[1],
5120 operand_types[0])))
29b0f896
AM		 5121 {
5122 /* Does not match either direction. */
5123 continue;
5124 }
5125 /* found_reverse_match holds which of D or FloatDR
5126 we've found. */
40fb9820 5127 if (t->opcode_modifier.d)
8a2ed489 5128 found_reverse_match = Opcode_D;
40fb9820 5129 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5130 found_reverse_match = Opcode_FloatD;
5131 else
5132 found_reverse_match = 0;
40fb9820 5133 if (t->opcode_modifier.floatr)
8a2ed489 5134 found_reverse_match |= Opcode_FloatR;
29b0f896 5135 }
f48ff2ae 5136 else
29b0f896 5137 {
f48ff2ae 5138 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5139 switch (t->operands)
5140 {
c0f3af97
L		 5141 case 5:
5142 overlap4 = operand_type_and (i.types[4],
5143 operand_types[4]);
1a0670f3 5144 /* Fall through. */
d1cbb4db 5145 case 4:
c6fb90c8
L		 5146 overlap3 = operand_type_and (i.types[3],
5147 operand_types[3]);
1a0670f3 5148 /* Fall through. */
d1cbb4db 5149 case 3:
c6fb90c8
L		 5150 overlap2 = operand_type_and (i.types[2],
5151 operand_types[2]);
d1cbb4db
L		 5152 break;
5153 }
29b0f896 5154
f48ff2ae
L		 5155 switch (t->operands)
5156 {
c0f3af97
L		 5157 case 5:
5158 if (!operand_type_match (overlap4, i.types[4])
5159 || !operand_type_register_match (overlap3,
5160 i.types[3],
5161 operand_types[3],
5162 overlap4,
5163 i.types[4],
5164 operand_types[4]))
5165 continue;
1a0670f3 5166 /* Fall through. */
f48ff2ae 5167 case 4:
40fb9820 5168 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5169 || (check_register
5170 && !operand_type_register_match (overlap2,
5171 i.types[2],
5172 operand_types[2],
5173 overlap3,
5174 i.types[3],
5175 operand_types[3])))
f48ff2ae 5176 continue;
1a0670f3 5177 /* Fall through. */
f48ff2ae
L		 5178 case 3:
5179 /* Here we make use of the fact that there are no
5180 reverse match 3 operand instructions, and all 3
5181 operand instructions only need to be checked for
5182 register consistency between operands 2 and 3. */
40fb9820 5183 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5184 || (check_register
5185 && !operand_type_register_match (overlap1,
5186 i.types[1],
5187 operand_types[1],
5188 overlap2,
5189 i.types[2],
5190 operand_types[2])))
f48ff2ae
L		 5191 continue;
5192 break;
5193 }
29b0f896 5194 }
f48ff2ae 5195 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5196 slip through to break. */
5197 }
3629bb00 5198 if (!found_cpu_match)
29b0f896
AM		 5199 {
5200 found_reverse_match = 0;
5201 continue;
5202 }
c0f3af97 5203
5614d22c
JB		 5204 /* Check if vector and VEX operands are valid. */
5205 if (check_VecOperands (t) || VEX_check_operands (t))
5206 {
5207 specific_error = i.error;
5208 continue;
5209 }
a683cc34 5210
29b0f896
AM		 5211 /* We've found a match; break out of loop. */
5212 break;
5213 }
5214
5215 if (t == current_templates->end)
5216 {
5217 /* We found no match. */
a65babc9 5218 const char *err_msg;
5614d22c 5219 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5220 {
5221 default:
5222 abort ();
86e026a4 5223 case operand_size_mismatch:
a65babc9
L		 5224 err_msg = _("operand size mismatch");
5225 break;
5226 case operand_type_mismatch:
5227 err_msg = _("operand type mismatch");
5228 break;
5229 case register_type_mismatch:
5230 err_msg = _("register type mismatch");
5231 break;
5232 case number_of_operands_mismatch:
5233 err_msg = _("number of operands mismatch");
5234 break;
5235 case invalid_instruction_suffix:
5236 err_msg = _("invalid instruction suffix");
5237 break;
5238 case bad_imm4:
4a2608e3 5239 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5240 break;
5241 case old_gcc_only:
5242 err_msg = _("only supported with old gcc");
5243 break;
5244 case unsupported_with_intel_mnemonic:
5245 err_msg = _("unsupported with Intel mnemonic");
5246 break;
5247 case unsupported_syntax:
5248 err_msg = _("unsupported syntax");
5249 break;
5250 case unsupported:
35262a23 5251 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5252 current_templates->start->name);
5253 return NULL;
6c30d220
L		 5254 case invalid_vsib_address:
5255 err_msg = _("invalid VSIB address");
5256 break;
7bab8ab5
JB		 5257 case invalid_vector_register_set:
5258 err_msg = _("mask, index, and destination registers must be distinct");
5259 break;
6c30d220
L		 5260 case unsupported_vector_index_register:
5261 err_msg = _("unsupported vector index register");
5262 break;
43234a1e
L		 5263 case unsupported_broadcast:
5264 err_msg = _("unsupported broadcast");
5265 break;
5266 case broadcast_not_on_src_operand:
5267 err_msg = _("broadcast not on source memory operand");
5268 break;
5269 case broadcast_needed:
5270 err_msg = _("broadcast is needed for operand of such type");
5271 break;
5272 case unsupported_masking:
5273 err_msg = _("unsupported masking");
5274 break;
5275 case mask_not_on_destination:
5276 err_msg = _("mask not on destination operand");
5277 break;
5278 case no_default_mask:
5279 err_msg = _("default mask isn't allowed");
5280 break;
5281 case unsupported_rc_sae:
5282 err_msg = _("unsupported static rounding/sae");
5283 break;
5284 case rc_sae_operand_not_last_imm:
5285 if (intel_syntax)
5286 err_msg = _("RC/SAE operand must precede immediate operands");
5287 else
5288 err_msg = _("RC/SAE operand must follow immediate operands");
5289 break;
5290 case invalid_register_operand:
5291 err_msg = _("invalid register operand");
5292 break;
a65babc9
L		 5293 }
5294 as_bad (_("%s for `%s'"), err_msg,
891edac4 5295 current_templates->start->name);
fa99fab2 5296 return NULL;
29b0f896 5297 }
252b5132 5298
29b0f896
AM		 5299 if (!quiet_warnings)
5300 {
5301 if (!intel_syntax
40fb9820
L		 5302 && (i.types[0].bitfield.jumpabsolute
5303 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5304 {
5305 as_warn (_("indirect %s without `*'"), t->name);
5306 }
5307
40fb9820
L		 5308 if (t->opcode_modifier.isprefix
5309 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5310 {
5311 /* Warn them that a data or address size prefix doesn't
5312 affect assembly of the next line of code. */
5313 as_warn (_("stand-alone `%s' prefix"), t->name);
5314 }
5315 }
5316
5317 /* Copy the template we found. */
5318 i.tm = *t;
539e75ad
L		 5319
5320 if (addr_prefix_disp != -1)
5321 i.tm.operand_types[addr_prefix_disp]
5322 = operand_types[addr_prefix_disp];
5323
29b0f896
AM		 5324 if (found_reverse_match)
5325 {
5326 /* If we found a reverse match we must alter the opcode
5327 direction bit. found_reverse_match holds bits to change
5328 (different for int & float insns). */
5329
5330 i.tm.base_opcode ^= found_reverse_match;
5331
539e75ad
L		 5332 i.tm.operand_types[0] = operand_types[1];
5333 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5334 }
5335
fa99fab2 5336 return t;
29b0f896
AM		 5337}
5338
5339static int
e3bb37b5 5340check_string (void)
29b0f896 5341{
40fb9820
L		 5342 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5343 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5344 {
5345 if (i.seg[0] != NULL && i.seg[0] != &es)
5346 {
a87af027 5347 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5348 i.tm.name,
a87af027
JB		 5349 mem_op + 1,
5350 register_prefix);
29b0f896
AM		 5351 return 0;
5352 }
5353 /* There's only ever one segment override allowed per instruction.
5354 This instruction possibly has a legal segment override on the
5355 second operand, so copy the segment to where non-string
5356 instructions store it, allowing common code. */
5357 i.seg[0] = i.seg[1];
5358 }
40fb9820 5359 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5360 {
5361 if (i.seg[1] != NULL && i.seg[1] != &es)
5362 {
a87af027 5363 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5364 i.tm.name,
a87af027
JB		 5365 mem_op + 2,
5366 register_prefix);
29b0f896
AM		 5367 return 0;
5368 }
5369 }
5370 return 1;
5371}
5372
5373static int
543613e9 5374process_suffix (void)
29b0f896
AM		 5375{
5376 /* If matched instruction specifies an explicit instruction mnemonic
5377 suffix, use it. */
40fb9820
L		 5378 if (i.tm.opcode_modifier.size16)
5379 i.suffix = WORD_MNEM_SUFFIX;
5380 else if (i.tm.opcode_modifier.size32)
5381 i.suffix = LONG_MNEM_SUFFIX;
5382 else if (i.tm.opcode_modifier.size64)
5383 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5384 else if (i.reg_operands)
5385 {
5386 /* If there's no instruction mnemonic suffix we try to invent one
5387 based on register operands. */
5388 if (!i.suffix)
5389 {
5390 /* We take i.suffix from the last register operand specified,
5391 Destination register type is more significant than source
381d071f
L		 5392 register type. crc32 in SSE4.2 prefers source register
5393 type. */
5394 if (i.tm.base_opcode == 0xf20f38f1)
5395 {
40fb9820
L		 5396 if (i.types[0].bitfield.reg16)
5397 i.suffix = WORD_MNEM_SUFFIX;
5398 else if (i.types[0].bitfield.reg32)
5399 i.suffix = LONG_MNEM_SUFFIX;
5400 else if (i.types[0].bitfield.reg64)
5401 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5402 }
9344ff29 5403 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5404 {
40fb9820 5405 if (i.types[0].bitfield.reg8)
20592a94
L		 5406 i.suffix = BYTE_MNEM_SUFFIX;
5407 }
381d071f
L		 5408
5409 if (!i.suffix)
5410 {
5411 int op;
5412
20592a94
L		 5413 if (i.tm.base_opcode == 0xf20f38f1
5414 || i.tm.base_opcode == 0xf20f38f0)
5415 {
5416 /* We have to know the operand size for crc32. */
5417 as_bad (_("ambiguous memory operand size for `%s`"),
5418 i.tm.name);
5419 return 0;
5420 }
5421
381d071f 5422 for (op = i.operands; --op >= 0;)
40fb9820 5423 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5424 {
40fb9820
L		 5425 if (i.types[op].bitfield.reg8)
5426 {
5427 i.suffix = BYTE_MNEM_SUFFIX;
5428 break;
5429 }
5430 else if (i.types[op].bitfield.reg16)
5431 {
5432 i.suffix = WORD_MNEM_SUFFIX;
5433 break;
5434 }
5435 else if (i.types[op].bitfield.reg32)
5436 {
5437 i.suffix = LONG_MNEM_SUFFIX;
5438 break;
5439 }
5440 else if (i.types[op].bitfield.reg64)
5441 {
5442 i.suffix = QWORD_MNEM_SUFFIX;
5443 break;
5444 }
381d071f
L		 5445 }
5446 }
29b0f896
AM		 5447 }
5448 else if (i.suffix == BYTE_MNEM_SUFFIX)
5449 {
2eb952a4
L		 5450 if (intel_syntax
5451 && i.tm.opcode_modifier.ignoresize
5452 && i.tm.opcode_modifier.no_bsuf)
5453 i.suffix = 0;
5454 else if (!check_byte_reg ())
29b0f896
AM		 5455 return 0;
5456 }
5457 else if (i.suffix == LONG_MNEM_SUFFIX)
5458 {
2eb952a4
L		 5459 if (intel_syntax
5460 && i.tm.opcode_modifier.ignoresize
5461 && i.tm.opcode_modifier.no_lsuf)
5462 i.suffix = 0;
5463 else if (!check_long_reg ())
29b0f896
AM		 5464 return 0;
5465 }
5466 else if (i.suffix == QWORD_MNEM_SUFFIX)
5467 {
955e1e6a
L		 5468 if (intel_syntax
5469 && i.tm.opcode_modifier.ignoresize
5470 && i.tm.opcode_modifier.no_qsuf)
5471 i.suffix = 0;
5472 else if (!check_qword_reg ())
29b0f896
AM		 5473 return 0;
5474 }
5475 else if (i.suffix == WORD_MNEM_SUFFIX)
5476 {
2eb952a4
L		 5477 if (intel_syntax
5478 && i.tm.opcode_modifier.ignoresize
5479 && i.tm.opcode_modifier.no_wsuf)
5480 i.suffix = 0;
5481 else if (!check_word_reg ())
29b0f896
AM		 5482 return 0;
5483 }
c0f3af97 5484 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5485 || i.suffix == YMMWORD_MNEM_SUFFIX
5486 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5487 {
43234a1e 5488 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5489 should check if it is a valid suffix. */
5490 }
40fb9820 5491 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5492 /* Do nothing if the instruction is going to ignore the prefix. */
5493 ;
5494 else
5495 abort ();
5496 }
40fb9820 5497 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5498 && !i.suffix
5499 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5500 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5501 {
5502 i.suffix = stackop_size;
5503 }
9306ca4a
JB		 5504 else if (intel_syntax
5505 && !i.suffix
40fb9820
L		 5506 && (i.tm.operand_types[0].bitfield.jumpabsolute
5507 || i.tm.opcode_modifier.jumpbyte
5508 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5509 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5510 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5511 {
5512 switch (flag_code)
5513 {
5514 case CODE_64BIT:
40fb9820 5515 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5516 {
5517 i.suffix = QWORD_MNEM_SUFFIX;
5518 break;
5519 }
1a0670f3 5520 /* Fall through. */
9306ca4a 5521 case CODE_32BIT:
40fb9820 5522 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5523 i.suffix = LONG_MNEM_SUFFIX;
5524 break;
5525 case CODE_16BIT:
40fb9820 5526 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5527 i.suffix = WORD_MNEM_SUFFIX;
5528 break;
5529 }
5530 }
252b5132 5531
9306ca4a 5532 if (!i.suffix)
29b0f896 5533 {
9306ca4a
JB		 5534 if (!intel_syntax)
5535 {
40fb9820 5536 if (i.tm.opcode_modifier.w)
9306ca4a 5537 {
4eed87de
AM		 5538 as_bad (_("no instruction mnemonic suffix given and "
5539 "no register operands; can't size instruction"));
9306ca4a
JB		 5540 return 0;
5541 }
5542 }
5543 else
5544 {
40fb9820 5545 unsigned int suffixes;
7ab9ffdd 5546
40fb9820
L		 5547 suffixes = !i.tm.opcode_modifier.no_bsuf;
5548 if (!i.tm.opcode_modifier.no_wsuf)
5549 suffixes |= 1 << 1;
5550 if (!i.tm.opcode_modifier.no_lsuf)
5551 suffixes |= 1 << 2;
fc4adea1 5552 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5553 suffixes |= 1 << 3;
5554 if (!i.tm.opcode_modifier.no_ssuf)
5555 suffixes |= 1 << 4;
5556 if (!i.tm.opcode_modifier.no_qsuf)
5557 suffixes |= 1 << 5;
5558
5559 /* There are more than suffix matches. */
5560 if (i.tm.opcode_modifier.w
9306ca4a 5561 || ((suffixes & (suffixes - 1))
40fb9820
L		 5562 && !i.tm.opcode_modifier.defaultsize
5563 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5564 {
5565 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5566 return 0;
5567 }
5568 }
29b0f896 5569 }
252b5132 5570
9306ca4a
JB		 5571 /* Change the opcode based on the operand size given by i.suffix;
5572 We don't need to change things for byte insns. */
5573
582d5edd
L		 5574 if (i.suffix
5575 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5576 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5577 && i.suffix != YMMWORD_MNEM_SUFFIX
5578 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5579 {
5580 /* It's not a byte, select word/dword operation. */
40fb9820 5581 if (i.tm.opcode_modifier.w)
29b0f896 5582 {
40fb9820 5583 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5584 i.tm.base_opcode |= 8;
5585 else
5586 i.tm.base_opcode |= 1;
5587 }
0f3f3d8b 5588
29b0f896
AM		 5589 /* Now select between word & dword operations via the operand
5590 size prefix, except for instructions that will ignore this
5591 prefix anyway. */
ca61edf2 5592 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5593 {
ca61edf2
L		 5594 /* The address size override prefix changes the size of the
5595 first operand. */
40fb9820
L		 5596 if ((flag_code == CODE_32BIT
5597 && i.op->regs[0].reg_type.bitfield.reg16)
5598 || (flag_code != CODE_32BIT
5599 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5600 if (!add_prefix (ADDR_PREFIX_OPCODE))
5601 return 0;
5602 }
5603 else if (i.suffix != QWORD_MNEM_SUFFIX
5604 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5605 && !i.tm.opcode_modifier.ignoresize
5606 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5607 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5608 || (flag_code == CODE_64BIT
40fb9820 5609 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5610 {
5611 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5612
40fb9820 5613 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5614 prefix = ADDR_PREFIX_OPCODE;
252b5132 5615
29b0f896
AM		 5616 if (!add_prefix (prefix))
5617 return 0;
24eab124 5618 }
252b5132 5619
29b0f896
AM		 5620 /* Set mode64 for an operand. */
5621 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5622 && flag_code == CODE_64BIT
40fb9820 5623 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5624 {
5625 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5626 need rex64. cmpxchg8b is also a special case. */
5627 if (! (i.operands == 2
5628 && i.tm.base_opcode == 0x90
5629 && i.tm.extension_opcode == None
0dfbf9d7
L		 5630 && operand_type_equal (&i.types [0], &acc64)
5631 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5632 && ! (i.operands == 1
5633 && i.tm.base_opcode == 0xfc7
5634 && i.tm.extension_opcode == 1
40fb9820
L		 5635 && !operand_type_check (i.types [0], reg)
5636 && operand_type_check (i.types [0], anymem)))
f6bee062 5637 i.rex |= REX_W;
46e883c5 5638 }
3e73aa7c 5639
29b0f896
AM		 5640 /* Size floating point instruction. */
5641 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5642 if (i.tm.opcode_modifier.floatmf)
543613e9 5643 i.tm.base_opcode ^= 4;
29b0f896 5644 }
7ecd2f8b 5645
29b0f896
AM		 5646 return 1;
5647}
3e73aa7c 5648
29b0f896 5649static int
543613e9 5650check_byte_reg (void)
29b0f896
AM		 5651{
5652 int op;
543613e9 5653
29b0f896
AM		 5654 for (op = i.operands; --op >= 0;)
5655 {
5656 /* If this is an eight bit register, it's OK. If it's the 16 or
5657 32 bit version of an eight bit register, we will just use the
5658 low portion, and that's OK too. */
40fb9820 5659 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5660 continue;
5661
5a819eb9
JB		 5662 /* I/O port address operands are OK too. */
5663 if (i.tm.operand_types[op].bitfield.inoutportreg)
5664 continue;
5665
9344ff29
L		 5666 /* crc32 doesn't generate this warning. */
5667 if (i.tm.base_opcode == 0xf20f38f0)
5668 continue;
5669
40fb9820
L		 5670 if ((i.types[op].bitfield.reg16
5671 || i.types[op].bitfield.reg32
5672 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5673 && i.op[op].regs->reg_num < 4
5674 /* Prohibit these changes in 64bit mode, since the lowering
5675 would be more complicated. */
5676 && flag_code != CODE_64BIT)
29b0f896 5677 {
29b0f896 5678#if REGISTER_WARNINGS
5a819eb9 5679 if (!quiet_warnings)
a540244d
L		 5680 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5681 register_prefix,
40fb9820 5682 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5683 ? REGNAM_AL - REGNAM_AX
5684 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5685 register_prefix,
29b0f896
AM		 5686 i.op[op].regs->reg_name,
5687 i.suffix);
5688#endif
5689 continue;
5690 }
5691 /* Any other register is bad. */
40fb9820
L		 5692 if (i.types[op].bitfield.reg16
5693 || i.types[op].bitfield.reg32
5694 || i.types[op].bitfield.reg64
5695 || i.types[op].bitfield.regmmx
5696 || i.types[op].bitfield.regxmm
c0f3af97 5697 || i.types[op].bitfield.regymm
43234a1e 5698 || i.types[op].bitfield.regzmm
40fb9820
L		 5699 || i.types[op].bitfield.sreg2
5700 || i.types[op].bitfield.sreg3
5701 || i.types[op].bitfield.control
5702 || i.types[op].bitfield.debug
5703 || i.types[op].bitfield.test
5704 || i.types[op].bitfield.floatreg
5705 || i.types[op].bitfield.floatacc)
29b0f896 5706 {
a540244d
L		 5707 as_bad (_("`%s%s' not allowed with `%s%c'"),
5708 register_prefix,
29b0f896
AM		 5709 i.op[op].regs->reg_name,
5710 i.tm.name,
5711 i.suffix);
5712 return 0;
5713 }
5714 }
5715 return 1;
5716}
5717
5718static int
e3bb37b5 5719check_long_reg (void)
29b0f896
AM		 5720{
5721 int op;
5722
5723 for (op = i.operands; --op >= 0;)
5724 /* Reject eight bit registers, except where the template requires
5725 them. (eg. movzb) */
40fb9820
L		 5726 if (i.types[op].bitfield.reg8
5727 && (i.tm.operand_types[op].bitfield.reg16
5728 || i.tm.operand_types[op].bitfield.reg32
5729 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5730 {
a540244d
L		 5731 as_bad (_("`%s%s' not allowed with `%s%c'"),
5732 register_prefix,
29b0f896
AM		 5733 i.op[op].regs->reg_name,
5734 i.tm.name,
5735 i.suffix);
5736 return 0;
5737 }
e4630f71 5738 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5739 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5740 && i.types[op].bitfield.reg16
5741 && (i.tm.operand_types[op].bitfield.reg32
5742 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5743 {
5744 /* Prohibit these changes in the 64bit mode, since the
5745 lowering is more complicated. */
5746 if (flag_code == CODE_64BIT)
252b5132 5747 {
2b5d6a91 5748 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5749 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5750 i.suffix);
5751 return 0;
252b5132 5752 }
29b0f896 5753#if REGISTER_WARNINGS
cecf1424
JB		 5754 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5755 register_prefix,
5756 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5757 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5758#endif
252b5132 5759 }
e4630f71 5760 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5761 else if (i.types[op].bitfield.reg64
5762 && (i.tm.operand_types[op].bitfield.reg32
5763 || i.tm.operand_types[op].bitfield.acc))
252b5132 5764 {
34828aad 5765 if (intel_syntax
ca61edf2 5766 && i.tm.opcode_modifier.toqword
40fb9820 5767 && !i.types[0].bitfield.regxmm)
34828aad 5768 {
ca61edf2 5769 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5770 i.suffix = QWORD_MNEM_SUFFIX;
5771 }
5772 else
5773 {
2b5d6a91 5774 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5775 register_prefix, i.op[op].regs->reg_name,
5776 i.suffix);
5777 return 0;
5778 }
29b0f896
AM		 5779 }
5780 return 1;
5781}
252b5132 5782
29b0f896 5783static int
e3bb37b5 5784check_qword_reg (void)
29b0f896
AM		 5785{
5786 int op;
252b5132 5787
29b0f896
AM		 5788 for (op = i.operands; --op >= 0; )
5789 /* Reject eight bit registers, except where the template requires
5790 them. (eg. movzb) */
40fb9820
L		 5791 if (i.types[op].bitfield.reg8
5792 && (i.tm.operand_types[op].bitfield.reg16
5793 || i.tm.operand_types[op].bitfield.reg32
5794 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5795 {
a540244d
L		 5796 as_bad (_("`%s%s' not allowed with `%s%c'"),
5797 register_prefix,
29b0f896
AM		 5798 i.op[op].regs->reg_name,
5799 i.tm.name,
5800 i.suffix);
5801 return 0;
5802 }
e4630f71 5803 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5804 else if ((i.types[op].bitfield.reg16
5805 || i.types[op].bitfield.reg32)
33d0ab95 5806 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5807 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5808 {
5809 /* Prohibit these changes in the 64bit mode, since the
5810 lowering is more complicated. */
34828aad 5811 if (intel_syntax
ca61edf2 5812 && i.tm.opcode_modifier.todword
40fb9820 5813 && !i.types[0].bitfield.regxmm)
34828aad 5814 {
ca61edf2 5815 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5816 i.suffix = LONG_MNEM_SUFFIX;
5817 }
5818 else
5819 {
2b5d6a91 5820 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5821 register_prefix, i.op[op].regs->reg_name,
5822 i.suffix);
5823 return 0;
5824 }
252b5132 5825 }
29b0f896
AM		 5826 return 1;
5827}
252b5132 5828
29b0f896 5829static int
e3bb37b5 5830check_word_reg (void)
29b0f896
AM		 5831{
5832 int op;
5833 for (op = i.operands; --op >= 0;)
5834 /* Reject eight bit registers, except where the template requires
5835 them. (eg. movzb) */
40fb9820
L		 5836 if (i.types[op].bitfield.reg8
5837 && (i.tm.operand_types[op].bitfield.reg16
5838 || i.tm.operand_types[op].bitfield.reg32
5839 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5840 {
a540244d
L		 5841 as_bad (_("`%s%s' not allowed with `%s%c'"),
5842 register_prefix,
29b0f896
AM		 5843 i.op[op].regs->reg_name,
5844 i.tm.name,
5845 i.suffix);
5846 return 0;
5847 }
e4630f71 5848 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5849 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5850 && (i.types[op].bitfield.reg32
5851 || i.types[op].bitfield.reg64)
40fb9820
L		 5852 && (i.tm.operand_types[op].bitfield.reg16
5853 || i.tm.operand_types[op].bitfield.acc))
252b5132 5854 {
29b0f896
AM		 5855 /* Prohibit these changes in the 64bit mode, since the
5856 lowering is more complicated. */
5857 if (flag_code == CODE_64BIT)
252b5132 5858 {
2b5d6a91 5859 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5860 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5861 i.suffix);
5862 return 0;
252b5132 5863 }
29b0f896 5864#if REGISTER_WARNINGS
cecf1424
JB		 5865 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5866 register_prefix,
5867 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5868 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5869#endif
5870 }
5871 return 1;
5872}
252b5132 5873
29b0f896 5874static int
40fb9820 5875update_imm (unsigned int j)
29b0f896 5876{
bc0844ae 5877 i386_operand_type overlap = i.types[j];
40fb9820
L		 5878 if ((overlap.bitfield.imm8
5879 || overlap.bitfield.imm8s
5880 || overlap.bitfield.imm16
5881 || overlap.bitfield.imm32
5882 || overlap.bitfield.imm32s
5883 || overlap.bitfield.imm64)
0dfbf9d7
L		 5884 && !operand_type_equal (&overlap, &imm8)
5885 && !operand_type_equal (&overlap, &imm8s)
5886 && !operand_type_equal (&overlap, &imm16)
5887 && !operand_type_equal (&overlap, &imm32)
5888 && !operand_type_equal (&overlap, &imm32s)
5889 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5890 {
5891 if (i.suffix)
5892 {
40fb9820
L		 5893 i386_operand_type temp;
5894
0dfbf9d7 5895 operand_type_set (&temp, 0);
7ab9ffdd 5896 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5897 {
5898 temp.bitfield.imm8 = overlap.bitfield.imm8;
5899 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5900 }
5901 else if (i.suffix == WORD_MNEM_SUFFIX)
5902 temp.bitfield.imm16 = overlap.bitfield.imm16;
5903 else if (i.suffix == QWORD_MNEM_SUFFIX)
5904 {
5905 temp.bitfield.imm64 = overlap.bitfield.imm64;
5906 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5907 }
5908 else
5909 temp.bitfield.imm32 = overlap.bitfield.imm32;
5910 overlap = temp;
29b0f896 5911 }
0dfbf9d7
L		 5912 else if (operand_type_equal (&overlap, &imm16_32_32s)
5913 || operand_type_equal (&overlap, &imm16_32)
5914 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5915 {
40fb9820 5916 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5917 overlap = imm16;
40fb9820 5918 else
65da13b5 5919 overlap = imm32s;
29b0f896 5920 }
0dfbf9d7
L		 5921 if (!operand_type_equal (&overlap, &imm8)
5922 && !operand_type_equal (&overlap, &imm8s)
5923 && !operand_type_equal (&overlap, &imm16)
5924 && !operand_type_equal (&overlap, &imm32)
5925 && !operand_type_equal (&overlap, &imm32s)
5926 && !operand_type_equal (&overlap, &imm64))
29b0f896 5927 {
4eed87de
AM		 5928 as_bad (_("no instruction mnemonic suffix given; "
5929 "can't determine immediate size"));
29b0f896
AM		 5930 return 0;
5931 }
5932 }
40fb9820 5933 i.types[j] = overlap;
29b0f896 5934
40fb9820
L		 5935 return 1;
5936}
5937
5938static int
5939finalize_imm (void)
5940{
bc0844ae 5941 unsigned int j, n;
29b0f896 5942
bc0844ae
L		 5943 /* Update the first 2 immediate operands. */
5944 n = i.operands > 2 ? 2 : i.operands;
5945 if (n)
5946 {
5947 for (j = 0; j < n; j++)
5948 if (update_imm (j) == 0)
5949 return 0;
40fb9820 5950
bc0844ae
L		 5951 /* The 3rd operand can't be immediate operand. */
5952 gas_assert (operand_type_check (i.types[2], imm) == 0);
5953 }
29b0f896
AM		 5954
5955 return 1;
5956}
5957
c0f3af97
L		 5958static int
5959bad_implicit_operand (int xmm)
5960{
91d6fa6a
NC		 5961 const char *ireg = xmm ? "xmm0" : "ymm0";
5962
c0f3af97
L		 5963 if (intel_syntax)
5964 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5965 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5966 else
5967 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5968 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5969 return 0;
5970}
5971
29b0f896 5972static int
e3bb37b5 5973process_operands (void)
29b0f896
AM		 5974{
5975 /* Default segment register this instruction will use for memory
5976 accesses. 0 means unknown. This is only for optimizing out
5977 unnecessary segment overrides. */
5978 const seg_entry *default_seg = 0;
5979
2426c15f 5980 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5981 {
91d6fa6a
NC		 5982 unsigned int dupl = i.operands;
5983 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5984 unsigned int j;
5985
c0f3af97 5986 /* The destination must be an xmm register. */
9c2799c2 5987 gas_assert (i.reg_operands
91d6fa6a 5988 && MAX_OPERANDS > dupl
7ab9ffdd 5989 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5990
5991 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5992 {
c0f3af97 5993 /* The first operand is implicit and must be xmm0. */
9c2799c2 5994 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5995 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5996 return bad_implicit_operand (1);
5997
8cd7925b 5998 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5999 {
6000 /* Keep xmm0 for instructions with VEX prefix and 3
6001 sources. */
6002 goto duplicate;
6003 }
e2ec9d29 6004 else
c0f3af97
L		 6005 {
6006 /* We remove the first xmm0 and keep the number of
6007 operands unchanged, which in fact duplicates the
6008 destination. */
6009 for (j = 1; j < i.operands; j++)
6010 {
6011 i.op[j - 1] = i.op[j];
6012 i.types[j - 1] = i.types[j];
6013 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6014 }
6015 }
6016 }
6017 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6018 {
91d6fa6a 6019 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6020 && (i.tm.opcode_modifier.vexsources
6021 == VEX3SOURCES));
c0f3af97
L		 6022
6023 /* Add the implicit xmm0 for instructions with VEX prefix
6024 and 3 sources. */
6025 for (j = i.operands; j > 0; j--)
6026 {
6027 i.op[j] = i.op[j - 1];
6028 i.types[j] = i.types[j - 1];
6029 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6030 }
6031 i.op[0].regs
6032 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6033 i.types[0] = regxmm;
c0f3af97
L		 6034 i.tm.operand_types[0] = regxmm;
6035
6036 i.operands += 2;
6037 i.reg_operands += 2;
6038 i.tm.operands += 2;
6039
91d6fa6a 6040 dupl++;
c0f3af97 6041 dest++;
91d6fa6a
NC		 6042 i.op[dupl] = i.op[dest];
6043 i.types[dupl] = i.types[dest];
6044 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6045 }
c0f3af97
L		 6046 else
6047 {
6048duplicate:
6049 i.operands++;
6050 i.reg_operands++;
6051 i.tm.operands++;
6052
91d6fa6a
NC		 6053 i.op[dupl] = i.op[dest];
6054 i.types[dupl] = i.types[dest];
6055 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6056 }
6057
6058 if (i.tm.opcode_modifier.immext)
6059 process_immext ();
6060 }
6061 else if (i.tm.opcode_modifier.firstxmm0)
6062 {
6063 unsigned int j;
6064
43234a1e 6065 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 6066 gas_assert (i.reg_operands
7ab9ffdd 6067 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 6068 || operand_type_equal (&i.types[0], &regymm)
6069 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 6070 if (register_number (i.op[0].regs) != 0)
c0f3af97 6071 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 6072
6073 for (j = 1; j < i.operands; j++)
6074 {
6075 i.op[j - 1] = i.op[j];
6076 i.types[j - 1] = i.types[j];
6077
6078 /* We need to adjust fields in i.tm since they are used by
6079 build_modrm_byte. */
6080 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6081 }
6082
e2ec9d29
L		 6083 i.operands--;
6084 i.reg_operands--;
e2ec9d29
L		 6085 i.tm.operands--;
6086 }
920d2ddc
IT		 6087 else if (i.tm.opcode_modifier.implicitquadgroup)
6088 {
6089 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6090 gas_assert (i.operands >= 2
6091 && (operand_type_equal (&i.types[1], &regxmm)
6092 || operand_type_equal (&i.types[1], &regymm)
6093 || operand_type_equal (&i.types[1], &regzmm)));
6094 unsigned int regnum = register_number (i.op[1].regs);
6095 unsigned int first_reg_in_group = regnum & ~3;
6096 unsigned int last_reg_in_group = first_reg_in_group + 3;
6097 if (regnum != first_reg_in_group) {
6098 as_warn (_("the second source register `%s%s' implicitly denotes"
6099 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6100 register_prefix, i.op[1].regs->reg_name,
6101 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6102 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6103 i.tm.name);
6104 }
6105 }
e2ec9d29
L		 6106 else if (i.tm.opcode_modifier.regkludge)
6107 {
6108 /* The imul $imm, %reg instruction is converted into
6109 imul $imm, %reg, %reg, and the clr %reg instruction
6110 is converted into xor %reg, %reg. */
6111
6112 unsigned int first_reg_op;
6113
6114 if (operand_type_check (i.types[0], reg))
6115 first_reg_op = 0;
6116 else
6117 first_reg_op = 1;
6118 /* Pretend we saw the extra register operand. */
9c2799c2 6119 gas_assert (i.reg_operands == 1
7ab9ffdd 6120 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6121 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6122 i.types[first_reg_op + 1] = i.types[first_reg_op];
6123 i.operands++;
6124 i.reg_operands++;
29b0f896
AM		 6125 }
6126
40fb9820 6127 if (i.tm.opcode_modifier.shortform)
29b0f896 6128 {
40fb9820
L		 6129 if (i.types[0].bitfield.sreg2
6130 || i.types[0].bitfield.sreg3)
29b0f896 6131 {
4eed87de
AM		 6132 if (i.tm.base_opcode == POP_SEG_SHORT
6133 && i.op[0].regs->reg_num == 1)
29b0f896 6134 {
a87af027 6135 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6136 return 0;
29b0f896 6137 }
4eed87de
AM		 6138 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6139 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6140 i.rex |= REX_B;
4eed87de
AM		 6141 }
6142 else
6143 {
7ab9ffdd 6144 /* The register or float register operand is in operand
85f10a01 6145 0 or 1. */
40fb9820 6146 unsigned int op;
7ab9ffdd
L		 6147
6148 if (i.types[0].bitfield.floatreg
6149 || operand_type_check (i.types[0], reg))
6150 op = 0;
6151 else
6152 op = 1;
4eed87de
AM		 6153 /* Register goes in low 3 bits of opcode. */
6154 i.tm.base_opcode |= i.op[op].regs->reg_num;
6155 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6156 i.rex |= REX_B;
40fb9820 6157 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6158 {
4eed87de
AM		 6159 /* Warn about some common errors, but press on regardless.
6160 The first case can be generated by gcc (<= 2.8.1). */
6161 if (i.operands == 2)
6162 {
6163 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6164 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6165 register_prefix, i.op[!intel_syntax].regs->reg_name,
6166 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6167 }
6168 else
6169 {
6170 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6171 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6172 register_prefix, i.op[0].regs->reg_name);
4eed87de 6173 }
29b0f896
AM		 6174 }
6175 }
6176 }
40fb9820 6177 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6178 {
6179 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6180 must be put into the modrm byte). Now, we make the modrm and
6181 index base bytes based on all the info we've collected. */
29b0f896
AM		 6182
6183 default_seg = build_modrm_byte ();
6184 }
8a2ed489 6185 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6186 {
6187 default_seg = &ds;
6188 }
40fb9820 6189 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6190 {
6191 /* For the string instructions that allow a segment override
6192 on one of their operands, the default segment is ds. */
6193 default_seg = &ds;
6194 }
6195
75178d9d
L		 6196 if (i.tm.base_opcode == 0x8d /* lea */
6197 && i.seg[0]
6198 && !quiet_warnings)
30123838 6199 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6200
6201 /* If a segment was explicitly specified, and the specified segment
6202 is not the default, use an opcode prefix to select it. If we
6203 never figured out what the default segment is, then default_seg
6204 will be zero at this point, and the specified segment prefix will
6205 always be used. */
29b0f896
AM		 6206 if ((i.seg[0]) && (i.seg[0] != default_seg))
6207 {
6208 if (!add_prefix (i.seg[0]->seg_prefix))
6209 return 0;
6210 }
6211 return 1;
6212}
6213
6214static const seg_entry *
e3bb37b5 6215build_modrm_byte (void)
29b0f896
AM		 6216{
6217 const seg_entry *default_seg = 0;
c0f3af97 6218 unsigned int source, dest;
8cd7925b 6219 int vex_3_sources;
c0f3af97
L		 6220
6221 /* The first operand of instructions with VEX prefix and 3 sources
6222 must be VEX_Imm4. */
8cd7925b 6223 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6224 if (vex_3_sources)
6225 {
91d6fa6a 6226 unsigned int nds, reg_slot;
4c2c6516 6227 expressionS *exp;
c0f3af97 6228
922d8de8 6229 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6230 && i.tm.opcode_modifier.immext)
6231 {
6232 dest = i.operands - 2;
6233 gas_assert (dest == 3);
6234 }
922d8de8 6235 else
a683cc34 6236 dest = i.operands - 1;
c0f3af97 6237 nds = dest - 1;
922d8de8 6238
a683cc34
SP		 6239 /* There are 2 kinds of instructions:
6240 1. 5 operands: 4 register operands or 3 register operands
6241 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6242 VexW0 or VexW1. The destination must be either XMM, YMM or
6243 ZMM register.
a683cc34
SP		 6244 2. 4 operands: 4 register operands or 3 register operands
6245 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6246 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6247 || (i.reg_operands == 3 && i.mem_operands == 1))
6248 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6249 && (i.tm.opcode_modifier.veximmext
6250 || (i.imm_operands == 1
6251 && i.types[0].bitfield.vec_imm4
6252 && (i.tm.opcode_modifier.vexw == VEXW0
6253 || i.tm.opcode_modifier.vexw == VEXW1)
6254 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6255 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6256 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6257
6258 if (i.imm_operands == 0)
6259 {
6260 /* When there is no immediate operand, generate an 8bit
6261 immediate operand to encode the first operand. */
6262 exp = &im_expressions[i.imm_operands++];
6263 i.op[i.operands].imms = exp;
6264 i.types[i.operands] = imm8;
6265 i.operands++;
6266 /* If VexW1 is set, the first operand is the source and
6267 the second operand is encoded in the immediate operand. */
6268 if (i.tm.opcode_modifier.vexw == VEXW1)
6269 {
6270 source = 0;
6271 reg_slot = 1;
6272 }
6273 else
6274 {
6275 source = 1;
6276 reg_slot = 0;
6277 }
6278
6279 /* FMA swaps REG and NDS. */
6280 if (i.tm.cpu_flags.bitfield.cpufma)
6281 {
6282 unsigned int tmp;
6283 tmp = reg_slot;
6284 reg_slot = nds;
6285 nds = tmp;
6286 }
6287
24981e7b
L		 6288 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6289 &regxmm)
a683cc34 6290 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6291 &regymm)
6292 || operand_type_equal (&i.tm.operand_types[reg_slot],
6293 &regzmm));
a683cc34 6294 exp->X_op = O_constant;
4c692bc7 6295 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6296 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6297 }
922d8de8 6298 else
a683cc34
SP		 6299 {
6300 unsigned int imm_slot;
6301
6302 if (i.tm.opcode_modifier.vexw == VEXW0)
6303 {
6304 /* If VexW0 is set, the third operand is the source and
6305 the second operand is encoded in the immediate
6306 operand. */
6307 source = 2;
6308 reg_slot = 1;
6309 }
6310 else
6311 {
6312 /* VexW1 is set, the second operand is the source and
6313 the third operand is encoded in the immediate
6314 operand. */
6315 source = 1;
6316 reg_slot = 2;
6317 }
6318
6319 if (i.tm.opcode_modifier.immext)
6320 {
33eaf5de 6321 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6322 operand. */
6323 imm_slot = i.operands - 1;
6324 source--;
6325 reg_slot--;
6326 }
6327 else
6328 {
6329 imm_slot = 0;
6330
6331 /* Turn on Imm8 so that output_imm will generate it. */
6332 i.types[imm_slot].bitfield.imm8 = 1;
6333 }
6334
24981e7b
L		 6335 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6336 &regxmm)
6337 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6338 &regymm)
6339 || operand_type_equal (&i.tm.operand_types[reg_slot],
6340 &regzmm));
a683cc34 6341 i.op[imm_slot].imms->X_add_number
4c692bc7 6342 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6343 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6344 }
6345
6346 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6347 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6348 &regymm)
6349 || operand_type_equal (&i.tm.operand_types[nds],
6350 &regzmm));
dae39acc 6351 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6352 }
6353 else
6354 source = dest = 0;
29b0f896
AM		 6355
6356 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6357 implicit registers do not count. If there are 3 register
6358 operands, it must be a instruction with VexNDS. For a
6359 instruction with VexNDD, the destination register is encoded
6360 in VEX prefix. If there are 4 register operands, it must be
6361 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6362 if (i.mem_operands == 0
6363 && ((i.reg_operands == 2
2426c15f 6364 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6365 || (i.reg_operands == 3
2426c15f 6366 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6367 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6368 {
cab737b9
L		 6369 switch (i.operands)
6370 {
6371 case 2:
6372 source = 0;
6373 break;
6374 case 3:
c81128dc
L		 6375 /* When there are 3 operands, one of them may be immediate,
6376 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6377 the first operand must be shift count register (cl) or it
6378 is an instruction with VexNDS. */
9c2799c2 6379 gas_assert (i.imm_operands == 1
7ab9ffdd 6380 || (i.imm_operands == 0
2426c15f 6381 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6382 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6383 if (operand_type_check (i.types[0], imm)
6384 || i.types[0].bitfield.shiftcount)
6385 source = 1;
6386 else
6387 source = 0;
cab737b9
L		 6388 break;
6389 case 4:
368d64cc
L		 6390 /* When there are 4 operands, the first two must be 8bit
6391 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6392 one.
6393
6394 For instructions with VexNDS, if the first operand
6395 an imm8, the source operand is the 2nd one. If the last
6396 operand is imm8, the source operand is the first one. */
9c2799c2 6397 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6398 && i.types[0].bitfield.imm8
6399 && i.types[1].bitfield.imm8)
2426c15f 6400 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6401 && i.imm_operands == 1
6402 && (i.types[0].bitfield.imm8
43234a1e
L		 6403 || i.types[i.operands - 1].bitfield.imm8
6404 || i.rounding)));
9f2670f2
L		 6405 if (i.imm_operands == 2)
6406 source = 2;
6407 else
c0f3af97
L		 6408 {
6409 if (i.types[0].bitfield.imm8)
6410 source = 1;
6411 else
6412 source = 0;
6413 }
c0f3af97
L		 6414 break;
6415 case 5:
43234a1e
L		 6416 if (i.tm.opcode_modifier.evex)
6417 {
6418 /* For EVEX instructions, when there are 5 operands, the
6419 first one must be immediate operand. If the second one
6420 is immediate operand, the source operand is the 3th
6421 one. If the last one is immediate operand, the source
6422 operand is the 2nd one. */
6423 gas_assert (i.imm_operands == 2
6424 && i.tm.opcode_modifier.sae
6425 && operand_type_check (i.types[0], imm));
6426 if (operand_type_check (i.types[1], imm))
6427 source = 2;
6428 else if (operand_type_check (i.types[4], imm))
6429 source = 1;
6430 else
6431 abort ();
6432 }
cab737b9
L		 6433 break;
6434 default:
6435 abort ();
6436 }
6437
c0f3af97
L		 6438 if (!vex_3_sources)
6439 {
6440 dest = source + 1;
6441
43234a1e
L		 6442 /* RC/SAE operand could be between DEST and SRC. That happens
6443 when one operand is GPR and the other one is XMM/YMM/ZMM
6444 register. */
6445 if (i.rounding && i.rounding->operand == (int) dest)
6446 dest++;
6447
2426c15f 6448 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6449 {
43234a1e
L		 6450 /* For instructions with VexNDS, the register-only source
6451 operand must be 32/64bit integer, XMM, YMM or ZMM
6452 register. It is encoded in VEX prefix. We need to
6453 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6454
6455 i386_operand_type op;
6456 unsigned int vvvv;
6457
6458 /* Check register-only source operand when two source
6459 operands are swapped. */
6460 if (!i.tm.operand_types[source].bitfield.baseindex
6461 && i.tm.operand_types[dest].bitfield.baseindex)
6462 {
6463 vvvv = source;
6464 source = dest;
6465 }
6466 else
6467 vvvv = dest;
6468
6469 op = i.tm.operand_types[vvvv];
fa99fab2 6470 op.bitfield.regmem = 0;
c0f3af97 6471 if ((dest + 1) >= i.operands
ac4eb736
AM		 6472 || (!op.bitfield.reg32
6473 && op.bitfield.reg64
f12dc422 6474 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6475 && !operand_type_equal (&op, &regymm)
6476 && !operand_type_equal (&op, &regzmm)
6477 && !operand_type_equal (&op, &regmask)))
c0f3af97 6478 abort ();
f12dc422 6479 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6480 dest++;
6481 }
6482 }
29b0f896
AM		 6483
6484 i.rm.mode = 3;
6485 /* One of the register operands will be encoded in the i.tm.reg
6486 field, the other in the combined i.tm.mode and i.tm.regmem
6487 fields. If no form of this instruction supports a memory
6488 destination operand, then we assume the source operand may
6489 sometimes be a memory operand and so we need to store the
6490 destination in the i.rm.reg field. */
40fb9820
L		 6491 if (!i.tm.operand_types[dest].bitfield.regmem
6492 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6493 {
6494 i.rm.reg = i.op[dest].regs->reg_num;
6495 i.rm.regmem = i.op[source].regs->reg_num;
6496 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6497 i.rex |= REX_R;
43234a1e
L		 6498 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6499 i.vrex |= REX_R;
29b0f896 6500 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6501 i.rex |= REX_B;
43234a1e
L		 6502 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6503 i.vrex |= REX_B;
29b0f896
AM		 6504 }
6505 else
6506 {
6507 i.rm.reg = i.op[source].regs->reg_num;
6508 i.rm.regmem = i.op[dest].regs->reg_num;
6509 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6510 i.rex |= REX_B;
43234a1e
L		 6511 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6512 i.vrex |= REX_B;
29b0f896 6513 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6514 i.rex |= REX_R;
43234a1e
L		 6515 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6516 i.vrex |= REX_R;
29b0f896 6517 }
161a04f6 6518 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6519 {
40fb9820
L		 6520 if (!i.types[0].bitfield.control
6521 && !i.types[1].bitfield.control)
c4a530c5 6522 abort ();
161a04f6 6523 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6524 add_prefix (LOCK_PREFIX_OPCODE);
6525 }
29b0f896
AM		 6526 }
6527 else
6528 { /* If it's not 2 reg operands... */
c0f3af97
L		 6529 unsigned int mem;
6530
29b0f896
AM		 6531 if (i.mem_operands)
6532 {
6533 unsigned int fake_zero_displacement = 0;
99018f42 6534 unsigned int op;
4eed87de 6535
7ab9ffdd
L		 6536 for (op = 0; op < i.operands; op++)
6537 if (operand_type_check (i.types[op], anymem))
6538 break;
7ab9ffdd 6539 gas_assert (op < i.operands);
29b0f896 6540
6c30d220
L		 6541 if (i.tm.opcode_modifier.vecsib)
6542 {
6543 if (i.index_reg->reg_num == RegEiz
6544 || i.index_reg->reg_num == RegRiz)
6545 abort ();
6546
6547 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6548 if (!i.base_reg)
6549 {
6550 i.sib.base = NO_BASE_REGISTER;
6551 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6552 /* No Vec_Disp8 if there is no base. */
6553 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6554 i.types[op].bitfield.disp8 = 0;
6555 i.types[op].bitfield.disp16 = 0;
6556 i.types[op].bitfield.disp64 = 0;
6557 if (flag_code != CODE_64BIT)
6558 {
6559 /* Must be 32 bit */
6560 i.types[op].bitfield.disp32 = 1;
6561 i.types[op].bitfield.disp32s = 0;
6562 }
6563 else
6564 {
6565 i.types[op].bitfield.disp32 = 0;
6566 i.types[op].bitfield.disp32s = 1;
6567 }
6568 }
6569 i.sib.index = i.index_reg->reg_num;
6570 if ((i.index_reg->reg_flags & RegRex) != 0)
6571 i.rex |= REX_X;
43234a1e
L		 6572 if ((i.index_reg->reg_flags & RegVRex) != 0)
6573 i.vrex |= REX_X;
6c30d220
L		 6574 }
6575
29b0f896
AM		 6576 default_seg = &ds;
6577
6578 if (i.base_reg == 0)
6579 {
6580 i.rm.mode = 0;
6581 if (!i.disp_operands)
6c30d220
L		 6582 {
6583 fake_zero_displacement = 1;
6584 /* Instructions with VSIB byte need 32bit displacement
6585 if there is no base register. */
6586 if (i.tm.opcode_modifier.vecsib)
6587 i.types[op].bitfield.disp32 = 1;
6588 }
29b0f896
AM		 6589 if (i.index_reg == 0)
6590 {
6c30d220 6591 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6592 /* Operand is just <disp> */
20f0a1fc 6593 if (flag_code == CODE_64BIT)
29b0f896
AM		 6594 {
6595 /* 64bit mode overwrites the 32bit absolute
6596 addressing by RIP relative addressing and
6597 absolute addressing is encoded by one of the
6598 redundant SIB forms. */
6599 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6600 i.sib.base = NO_BASE_REGISTER;
6601 i.sib.index = NO_INDEX_REGISTER;
fc225355 6602 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6603 ? disp32s : disp32);
20f0a1fc 6604 }
fc225355
L		 6605 else if ((flag_code == CODE_16BIT)
6606 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6607 {
6608 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6609 i.types[op] = disp16;
20f0a1fc
NC		 6610 }
6611 else
6612 {
6613 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6614 i.types[op] = disp32;
29b0f896
AM		 6615 }
6616 }
6c30d220 6617 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6618 {
6c30d220 6619 /* !i.base_reg && i.index_reg */
db51cc60
L		 6620 if (i.index_reg->reg_num == RegEiz
6621 || i.index_reg->reg_num == RegRiz)
6622 i.sib.index = NO_INDEX_REGISTER;
6623 else
6624 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6625 i.sib.base = NO_BASE_REGISTER;
6626 i.sib.scale = i.log2_scale_factor;
6627 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6628 /* No Vec_Disp8 if there is no base. */
6629 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6630 i.types[op].bitfield.disp8 = 0;
6631 i.types[op].bitfield.disp16 = 0;
6632 i.types[op].bitfield.disp64 = 0;
29b0f896 6633 if (flag_code != CODE_64BIT)
40fb9820
L		 6634 {
6635 /* Must be 32 bit */
6636 i.types[op].bitfield.disp32 = 1;
6637 i.types[op].bitfield.disp32s = 0;
6638 }
29b0f896 6639 else
40fb9820
L		 6640 {
6641 i.types[op].bitfield.disp32 = 0;
6642 i.types[op].bitfield.disp32s = 1;
6643 }
29b0f896 6644 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6645 i.rex |= REX_X;
29b0f896
AM		 6646 }
6647 }
6648 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6649 else if (i.base_reg->reg_num == RegRip ||
6650 i.base_reg->reg_num == RegEip)
29b0f896 6651 {
6c30d220 6652 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6653 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6654 i.types[op].bitfield.disp8 = 0;
6655 i.types[op].bitfield.disp16 = 0;
6656 i.types[op].bitfield.disp32 = 0;
6657 i.types[op].bitfield.disp32s = 1;
6658 i.types[op].bitfield.disp64 = 0;
43234a1e 6659 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6660 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6661 if (! i.disp_operands)
6662 fake_zero_displacement = 1;
29b0f896 6663 }
40fb9820 6664 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6665 {
6c30d220 6666 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6667 switch (i.base_reg->reg_num)
6668 {
6669 case 3: /* (%bx) */
6670 if (i.index_reg == 0)
6671 i.rm.regmem = 7;
6672 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6673 i.rm.regmem = i.index_reg->reg_num - 6;
6674 break;
6675 case 5: /* (%bp) */
6676 default_seg = &ss;
6677 if (i.index_reg == 0)
6678 {
6679 i.rm.regmem = 6;
40fb9820 6680 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6681 {
6682 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6683 if (i.tm.operand_types[op].bitfield.vec_disp8)
6684 i.types[op].bitfield.vec_disp8 = 1;
6685 else
6686 i.types[op].bitfield.disp8 = 1;
252b5132 6687 fake_zero_displacement = 1;
29b0f896
AM		 6688 }
6689 }
6690 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6691 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6692 break;
6693 default: /* (%si) -> 4 or (%di) -> 5 */
6694 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6695 }
6696 i.rm.mode = mode_from_disp_size (i.types[op]);
6697 }
6698 else /* i.base_reg and 32/64 bit mode */
6699 {
6700 if (flag_code == CODE_64BIT
40fb9820
L		 6701 && operand_type_check (i.types[op], disp))
6702 {
6703 i386_operand_type temp;
0dfbf9d7 6704 operand_type_set (&temp, 0);
40fb9820 6705 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6706 temp.bitfield.vec_disp8
6707 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6708 i.types[op] = temp;
6709 if (i.prefix[ADDR_PREFIX] == 0)
6710 i.types[op].bitfield.disp32s = 1;
6711 else
6712 i.types[op].bitfield.disp32 = 1;
6713 }
20f0a1fc 6714
6c30d220
L		 6715 if (!i.tm.opcode_modifier.vecsib)
6716 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6717 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6718 i.rex |= REX_B;
29b0f896
AM		 6719 i.sib.base = i.base_reg->reg_num;
6720 /* x86-64 ignores REX prefix bit here to avoid decoder
6721 complications. */
848930b2
JB		 6722 if (!(i.base_reg->reg_flags & RegRex)
6723 && (i.base_reg->reg_num == EBP_REG_NUM
6724 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6725 default_seg = &ss;
848930b2 6726 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6727 {
848930b2 6728 fake_zero_displacement = 1;
43234a1e
L		 6729 if (i.tm.operand_types [op].bitfield.vec_disp8)
6730 i.types[op].bitfield.vec_disp8 = 1;
6731 else
6732 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6733 }
6734 i.sib.scale = i.log2_scale_factor;
6735 if (i.index_reg == 0)
6736 {
6c30d220 6737 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6738 /* <disp>(%esp) becomes two byte modrm with no index
6739 register. We've already stored the code for esp
6740 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6741 Any base register besides %esp will not use the
6742 extra modrm byte. */
6743 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6744 }
6c30d220 6745 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6746 {
db51cc60
L		 6747 if (i.index_reg->reg_num == RegEiz
6748 || i.index_reg->reg_num == RegRiz)
6749 i.sib.index = NO_INDEX_REGISTER;
6750 else
6751 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6752 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6753 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6754 i.rex |= REX_X;
29b0f896 6755 }
67a4f2b7
AO		 6756
6757 if (i.disp_operands
6758 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6759 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6760 i.rm.mode = 0;
6761 else
a501d77e
L		 6762 {
6763 if (!fake_zero_displacement
6764 && !i.disp_operands
6765 && i.disp_encoding)
6766 {
6767 fake_zero_displacement = 1;
6768 if (i.disp_encoding == disp_encoding_8bit)
6769 i.types[op].bitfield.disp8 = 1;
6770 else
6771 i.types[op].bitfield.disp32 = 1;
6772 }
6773 i.rm.mode = mode_from_disp_size (i.types[op]);
6774 }
29b0f896 6775 }
252b5132 6776
29b0f896
AM		 6777 if (fake_zero_displacement)
6778 {
6779 /* Fakes a zero displacement assuming that i.types[op]
6780 holds the correct displacement size. */
6781 expressionS *exp;
6782
9c2799c2 6783 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6784 exp = &disp_expressions[i.disp_operands++];
6785 i.op[op].disps = exp;
6786 exp->X_op = O_constant;
6787 exp->X_add_number = 0;
6788 exp->X_add_symbol = (symbolS *) 0;
6789 exp->X_op_symbol = (symbolS *) 0;
6790 }
c0f3af97
L		 6791
6792 mem = op;
29b0f896 6793 }
c0f3af97
L		 6794 else
6795 mem = ~0;
252b5132 6796
8c43a48b 6797 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6798 {
6799 if (operand_type_check (i.types[0], imm))
6800 i.vex.register_specifier = NULL;
6801 else
6802 {
6803 /* VEX.vvvv encodes one of the sources when the first
6804 operand is not an immediate. */
1ef99a7b 6805 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6806 i.vex.register_specifier = i.op[0].regs;
6807 else
6808 i.vex.register_specifier = i.op[1].regs;
6809 }
6810
6811 /* Destination is a XMM register encoded in the ModRM.reg
6812 and VEX.R bit. */
6813 i.rm.reg = i.op[2].regs->reg_num;
6814 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6815 i.rex |= REX_R;
6816
6817 /* ModRM.rm and VEX.B encodes the other source. */
6818 if (!i.mem_operands)
6819 {
6820 i.rm.mode = 3;
6821
1ef99a7b 6822 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6823 i.rm.regmem = i.op[1].regs->reg_num;
6824 else
6825 i.rm.regmem = i.op[0].regs->reg_num;
6826
6827 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6828 i.rex |= REX_B;
6829 }
6830 }
2426c15f 6831 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6832 {
6833 i.vex.register_specifier = i.op[2].regs;
6834 if (!i.mem_operands)
6835 {
6836 i.rm.mode = 3;
6837 i.rm.regmem = i.op[1].regs->reg_num;
6838 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6839 i.rex |= REX_B;
6840 }
6841 }
29b0f896
AM		 6842 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6843 (if any) based on i.tm.extension_opcode. Again, we must be
6844 careful to make sure that segment/control/debug/test/MMX
6845 registers are coded into the i.rm.reg field. */
f88c9eb0 6846 else if (i.reg_operands)
29b0f896 6847 {
99018f42 6848 unsigned int op;
7ab9ffdd
L		 6849 unsigned int vex_reg = ~0;
6850
6851 for (op = 0; op < i.operands; op++)
6852 if (i.types[op].bitfield.reg8
6853 || i.types[op].bitfield.reg16
6854 || i.types[op].bitfield.reg32
6855 || i.types[op].bitfield.reg64
6856 || i.types[op].bitfield.regmmx
6857 || i.types[op].bitfield.regxmm
6858 || i.types[op].bitfield.regymm
7e8b059b 6859 || i.types[op].bitfield.regbnd
43234a1e
L		 6860 || i.types[op].bitfield.regzmm
6861 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6862 || i.types[op].bitfield.sreg2
6863 || i.types[op].bitfield.sreg3
6864 || i.types[op].bitfield.control
6865 || i.types[op].bitfield.debug
6866 || i.types[op].bitfield.test)
6867 break;
c0209578 6868
7ab9ffdd
L		 6869 if (vex_3_sources)
6870 op = dest;
2426c15f 6871 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6872 {
6873 /* For instructions with VexNDS, the register-only
6874 source operand is encoded in VEX prefix. */
6875 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6876
7ab9ffdd 6877 if (op > mem)
c0f3af97 6878 {
7ab9ffdd
L		 6879 vex_reg = op++;
6880 gas_assert (op < i.operands);
c0f3af97
L		 6881 }
6882 else
c0f3af97 6883 {
f12dc422
L		 6884 /* Check register-only source operand when two source
6885 operands are swapped. */
6886 if (!i.tm.operand_types[op].bitfield.baseindex
6887 && i.tm.operand_types[op + 1].bitfield.baseindex)
6888 {
6889 vex_reg = op;
6890 op += 2;
6891 gas_assert (mem == (vex_reg + 1)
6892 && op < i.operands);
6893 }
6894 else
6895 {
6896 vex_reg = op + 1;
6897 gas_assert (vex_reg < i.operands);
6898 }
c0f3af97 6899 }
7ab9ffdd 6900 }
2426c15f 6901 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6902 {
f12dc422 6903 /* For instructions with VexNDD, the register destination
7ab9ffdd 6904 is encoded in VEX prefix. */
f12dc422
L		 6905 if (i.mem_operands == 0)
6906 {
6907 /* There is no memory operand. */
6908 gas_assert ((op + 2) == i.operands);
6909 vex_reg = op + 1;
6910 }
6911 else
8d63c93e 6912 {
f12dc422
L		 6913 /* There are only 2 operands. */
6914 gas_assert (op < 2 && i.operands == 2);
6915 vex_reg = 1;
6916 }
7ab9ffdd
L		 6917 }
6918 else
6919 gas_assert (op < i.operands);
99018f42 6920
7ab9ffdd
L		 6921 if (vex_reg != (unsigned int) ~0)
6922 {
f12dc422 6923 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6924
f12dc422
L		 6925 if (type->bitfield.reg32 != 1
6926 && type->bitfield.reg64 != 1
6927 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6928 && !operand_type_equal (type, &regymm)
6929 && !operand_type_equal (type, &regzmm)
6930 && !operand_type_equal (type, &regmask))
7ab9ffdd 6931 abort ();
f88c9eb0 6932
7ab9ffdd
L		 6933 i.vex.register_specifier = i.op[vex_reg].regs;
6934 }
6935
1b9f0c97
L		 6936 /* Don't set OP operand twice. */
6937 if (vex_reg != op)
7ab9ffdd 6938 {
1b9f0c97
L		 6939 /* If there is an extension opcode to put here, the
6940 register number must be put into the regmem field. */
6941 if (i.tm.extension_opcode != None)
6942 {
6943 i.rm.regmem = i.op[op].regs->reg_num;
6944 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6945 i.rex |= REX_B;
43234a1e
L		 6946 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6947 i.vrex |= REX_B;
1b9f0c97
L		 6948 }
6949 else
6950 {
6951 i.rm.reg = i.op[op].regs->reg_num;
6952 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6953 i.rex |= REX_R;
43234a1e
L		 6954 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6955 i.vrex |= REX_R;
1b9f0c97 6956 }
7ab9ffdd 6957 }
252b5132 6958
29b0f896
AM		 6959 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6960 must set it to 3 to indicate this is a register operand
6961 in the regmem field. */
6962 if (!i.mem_operands)
6963 i.rm.mode = 3;
6964 }
252b5132 6965
29b0f896 6966 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6967 if (i.tm.extension_opcode != None)
29b0f896
AM		 6968 i.rm.reg = i.tm.extension_opcode;
6969 }
6970 return default_seg;
6971}
252b5132 6972
29b0f896 6973static void
e3bb37b5 6974output_branch (void)
29b0f896
AM		 6975{
6976 char *p;
f8a5c266 6977 int size;
29b0f896
AM		 6978 int code16;
6979 int prefix;
6980 relax_substateT subtype;
6981 symbolS *sym;
6982 offsetT off;
6983
f8a5c266 6984 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6985 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6986
6987 prefix = 0;
6988 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6989 {
29b0f896
AM		 6990 prefix = 1;
6991 i.prefixes -= 1;
6992 code16 ^= CODE16;
252b5132 6993 }
29b0f896
AM		 6994 /* Pentium4 branch hints. */
6995 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6996 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6997 {
29b0f896
AM		 6998 prefix++;
6999 i.prefixes--;
7000 }
7001 if (i.prefix[REX_PREFIX] != 0)
7002 {
7003 prefix++;
7004 i.prefixes--;
2f66722d
AM		 7005 }
7006
7e8b059b
L		 7007 /* BND prefixed jump. */
7008 if (i.prefix[BND_PREFIX] != 0)
7009 {
7010 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7011 i.prefixes -= 1;
7012 }
7013
29b0f896
AM		 7014 if (i.prefixes != 0 && !intel_syntax)
7015 as_warn (_("skipping prefixes on this instruction"));
7016
7017 /* It's always a symbol; End frag & setup for relax.
7018 Make sure there is enough room in this frag for the largest
7019 instruction we may generate in md_convert_frag. This is 2
7020 bytes for the opcode and room for the prefix and largest
7021 displacement. */
7022 frag_grow (prefix + 2 + 4);
7023 /* Prefix and 1 opcode byte go in fr_fix. */
7024 p = frag_more (prefix + 1);
7025 if (i.prefix[DATA_PREFIX] != 0)
7026 *p++ = DATA_PREFIX_OPCODE;
7027 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7028 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7029 *p++ = i.prefix[SEG_PREFIX];
7030 if (i.prefix[REX_PREFIX] != 0)
7031 *p++ = i.prefix[REX_PREFIX];
7032 *p = i.tm.base_opcode;
7033
7034 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7035 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7036 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7037 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7038 else
f8a5c266 7039 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7040 subtype |= code16;
3e73aa7c 7041
29b0f896
AM		 7042 sym = i.op[0].disps->X_add_symbol;
7043 off = i.op[0].disps->X_add_number;
3e73aa7c 7044
29b0f896
AM		 7045 if (i.op[0].disps->X_op != O_constant
7046 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7047 {
29b0f896
AM		 7048 /* Handle complex expressions. */
7049 sym = make_expr_symbol (i.op[0].disps);
7050 off = 0;
7051 }
3e73aa7c 7052
29b0f896
AM		 7053 /* 1 possible extra opcode + 4 byte displacement go in var part.
7054 Pass reloc in fr_var. */
d258b828 7055 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7056}
3e73aa7c 7057
29b0f896 7058static void
e3bb37b5 7059output_jump (void)
29b0f896
AM		 7060{
7061 char *p;
7062 int size;
3e02c1cc 7063 fixS *fixP;
29b0f896 7064
40fb9820 7065 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7066 {
7067 /* This is a loop or jecxz type instruction. */
7068 size = 1;
7069 if (i.prefix[ADDR_PREFIX] != 0)
7070 {
7071 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7072 i.prefixes -= 1;
7073 }
7074 /* Pentium4 branch hints. */
7075 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7076 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7077 {
7078 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7079 i.prefixes--;
3e73aa7c
JH		 7080 }
7081 }
29b0f896
AM		 7082 else
7083 {
7084 int code16;
3e73aa7c 7085
29b0f896
AM		 7086 code16 = 0;
7087 if (flag_code == CODE_16BIT)
7088 code16 = CODE16;
3e73aa7c 7089
29b0f896
AM		 7090 if (i.prefix[DATA_PREFIX] != 0)
7091 {
7092 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7093 i.prefixes -= 1;
7094 code16 ^= CODE16;
7095 }
252b5132 7096
29b0f896
AM		 7097 size = 4;
7098 if (code16)
7099 size = 2;
7100 }
9fcc94b6 7101
29b0f896
AM		 7102 if (i.prefix[REX_PREFIX] != 0)
7103 {
7104 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7105 i.prefixes -= 1;
7106 }
252b5132 7107
7e8b059b
L		 7108 /* BND prefixed jump. */
7109 if (i.prefix[BND_PREFIX] != 0)
7110 {
7111 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7112 i.prefixes -= 1;
7113 }
7114
29b0f896
AM		 7115 if (i.prefixes != 0 && !intel_syntax)
7116 as_warn (_("skipping prefixes on this instruction"));
e0890092 7117
42164a71
L		 7118 p = frag_more (i.tm.opcode_length + size);
7119 switch (i.tm.opcode_length)
7120 {
7121 case 2:
7122 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7123 /* Fall through. */
42164a71
L		 7124 case 1:
7125 *p++ = i.tm.base_opcode;
7126 break;
7127 default:
7128 abort ();
7129 }
e0890092 7130
3e02c1cc 7131 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7132 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7133
7134 /* All jumps handled here are signed, but don't use a signed limit
7135 check for 32 and 16 bit jumps as we want to allow wrap around at
7136 4G and 64k respectively. */
7137 if (size == 1)
7138 fixP->fx_signed = 1;
29b0f896 7139}
e0890092 7140
29b0f896 7141static void
e3bb37b5 7142output_interseg_jump (void)
29b0f896
AM		 7143{
7144 char *p;
7145 int size;
7146 int prefix;
7147 int code16;
252b5132 7148
29b0f896
AM		 7149 code16 = 0;
7150 if (flag_code == CODE_16BIT)
7151 code16 = CODE16;
a217f122 7152
29b0f896
AM		 7153 prefix = 0;
7154 if (i.prefix[DATA_PREFIX] != 0)
7155 {
7156 prefix = 1;
7157 i.prefixes -= 1;
7158 code16 ^= CODE16;
7159 }
7160 if (i.prefix[REX_PREFIX] != 0)
7161 {
7162 prefix++;
7163 i.prefixes -= 1;
7164 }
252b5132 7165
29b0f896
AM		 7166 size = 4;
7167 if (code16)
7168 size = 2;
252b5132 7169
29b0f896
AM		 7170 if (i.prefixes != 0 && !intel_syntax)
7171 as_warn (_("skipping prefixes on this instruction"));
252b5132 7172
29b0f896
AM		 7173 /* 1 opcode; 2 segment; offset */
7174 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7175
29b0f896
AM		 7176 if (i.prefix[DATA_PREFIX] != 0)
7177 *p++ = DATA_PREFIX_OPCODE;
252b5132 7178
29b0f896
AM		 7179 if (i.prefix[REX_PREFIX] != 0)
7180 *p++ = i.prefix[REX_PREFIX];
252b5132 7181
29b0f896
AM		 7182 *p++ = i.tm.base_opcode;
7183 if (i.op[1].imms->X_op == O_constant)
7184 {
7185 offsetT n = i.op[1].imms->X_add_number;
252b5132 7186
29b0f896
AM		 7187 if (size == 2
7188 && !fits_in_unsigned_word (n)
7189 && !fits_in_signed_word (n))
7190 {
7191 as_bad (_("16-bit jump out of range"));
7192 return;
7193 }
7194 md_number_to_chars (p, n, size);
7195 }
7196 else
7197 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7198 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7199 if (i.op[0].imms->X_op != O_constant)
7200 as_bad (_("can't handle non absolute segment in `%s'"),
7201 i.tm.name);
7202 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7203}
a217f122 7204
29b0f896 7205static void
e3bb37b5 7206output_insn (void)
29b0f896 7207{
2bbd9c25
JJ		 7208 fragS *insn_start_frag;
7209 offsetT insn_start_off;
7210
29b0f896
AM		 7211 /* Tie dwarf2 debug info to the address at the start of the insn.
7212 We can't do this after the insn has been output as the current
7213 frag may have been closed off. eg. by frag_var. */
7214 dwarf2_emit_insn (0);
7215
2bbd9c25
JJ		 7216 insn_start_frag = frag_now;
7217 insn_start_off = frag_now_fix ();
7218
29b0f896 7219 /* Output jumps. */
40fb9820 7220 if (i.tm.opcode_modifier.jump)
29b0f896 7221 output_branch ();
40fb9820
L		 7222 else if (i.tm.opcode_modifier.jumpbyte
7223 || i.tm.opcode_modifier.jumpdword)
29b0f896 7224 output_jump ();
40fb9820 7225 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7226 output_interseg_jump ();
7227 else
7228 {
7229 /* Output normal instructions here. */
7230 char *p;
7231 unsigned char *q;
47465058 7232 unsigned int j;
331d2d0d 7233 unsigned int prefix;
4dffcebc 7234
e4e00185
AS		 7235 if (avoid_fence
7236 && i.tm.base_opcode == 0xfae
7237 && i.operands == 1
7238 && i.imm_operands == 1
7239 && (i.op[0].imms->X_add_number == 0xe8
7240 || i.op[0].imms->X_add_number == 0xf0
7241 || i.op[0].imms->X_add_number == 0xf8))
7242 {
7243 /* Encode lfence, mfence, and sfence as
7244 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7245 offsetT val = 0x240483f0ULL;
7246 p = frag_more (5);
7247 md_number_to_chars (p, val, 5);
7248 return;
7249 }
7250
d022bddd
IT		 7251 /* Some processors fail on LOCK prefix. This options makes
7252 assembler ignore LOCK prefix and serves as a workaround. */
7253 if (omit_lock_prefix)
7254 {
7255 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7256 return;
7257 i.prefix[LOCK_PREFIX] = 0;
7258 }
7259
43234a1e
L		 7260 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7261 don't need the explicit prefix. */
7262 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7263 {
c0f3af97 7264 switch (i.tm.opcode_length)
bc4bd9ab 7265 {
c0f3af97
L		 7266 case 3:
7267 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7268 {
c0f3af97
L		 7269 prefix = (i.tm.base_opcode >> 24) & 0xff;
7270 goto check_prefix;
7271 }
7272 break;
7273 case 2:
7274 if ((i.tm.base_opcode & 0xff0000) != 0)
7275 {
7276 prefix = (i.tm.base_opcode >> 16) & 0xff;
7277 if (i.tm.cpu_flags.bitfield.cpupadlock)
7278 {
4dffcebc 7279check_prefix:
c0f3af97 7280 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7281 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7282 != REPE_PREFIX_OPCODE))
7283 add_prefix (prefix);
7284 }
7285 else
4dffcebc
L		 7286 add_prefix (prefix);
7287 }
c0f3af97
L		 7288 break;
7289 case 1:
7290 break;
7291 default:
7292 abort ();
bc4bd9ab 7293 }
c0f3af97 7294
6d19a37a 7295#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7296 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7297 R_X86_64_GOTTPOFF relocation so that linker can safely
7298 perform IE->LE optimization. */
7299 if (x86_elf_abi == X86_64_X32_ABI
7300 && i.operands == 2
7301 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7302 && i.prefix[REX_PREFIX] == 0)
7303 add_prefix (REX_OPCODE);
6d19a37a 7304#endif
cf61b747 7305
c0f3af97
L		 7306 /* The prefix bytes. */
7307 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7308 if (*q)
7309 FRAG_APPEND_1_CHAR (*q);
0f10071e 7310 }
ae5c1c7b 7311 else
c0f3af97
L		 7312 {
7313 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7314 if (*q)
7315 switch (j)
7316 {
7317 case REX_PREFIX:
7318 /* REX byte is encoded in VEX prefix. */
7319 break;
7320 case SEG_PREFIX:
7321 case ADDR_PREFIX:
7322 FRAG_APPEND_1_CHAR (*q);
7323 break;
7324 default:
7325 /* There should be no other prefixes for instructions
7326 with VEX prefix. */
7327 abort ();
7328 }
7329
43234a1e
L		 7330 /* For EVEX instructions i.vrex should become 0 after
7331 build_evex_prefix. For VEX instructions upper 16 registers
7332 aren't available, so VREX should be 0. */
7333 if (i.vrex)
7334 abort ();
c0f3af97
L		 7335 /* Now the VEX prefix. */
7336 p = frag_more (i.vex.length);
7337 for (j = 0; j < i.vex.length; j++)
7338 p[j] = i.vex.bytes[j];
7339 }
252b5132 7340
29b0f896 7341 /* Now the opcode; be careful about word order here! */
4dffcebc 7342 if (i.tm.opcode_length == 1)
29b0f896
AM		 7343 {
7344 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7345 }
7346 else
7347 {
4dffcebc 7348 switch (i.tm.opcode_length)
331d2d0d 7349 {
43234a1e
L		 7350 case 4:
7351 p = frag_more (4);
7352 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7353 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7354 break;
4dffcebc 7355 case 3:
331d2d0d
L		 7356 p = frag_more (3);
7357 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7358 break;
7359 case 2:
7360 p = frag_more (2);
7361 break;
7362 default:
7363 abort ();
7364 break;
331d2d0d 7365 }
0f10071e 7366
29b0f896
AM		 7367 /* Put out high byte first: can't use md_number_to_chars! */
7368 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7369 *p = i.tm.base_opcode & 0xff;
7370 }
3e73aa7c 7371
29b0f896 7372 /* Now the modrm byte and sib byte (if present). */
40fb9820 7373 if (i.tm.opcode_modifier.modrm)
29b0f896 7374 {
4a3523fa
L		 7375 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7376 | i.rm.reg << 3
7377 | i.rm.mode << 6));
29b0f896
AM		 7378 /* If i.rm.regmem == ESP (4)
7379 && i.rm.mode != (Register mode)
7380 && not 16 bit
7381 ==> need second modrm byte. */
7382 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7383 && i.rm.mode != 3
40fb9820 7384 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7385 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7386 | i.sib.index << 3
7387 | i.sib.scale << 6));
29b0f896 7388 }
3e73aa7c 7389
29b0f896 7390 if (i.disp_operands)
2bbd9c25 7391 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7392
29b0f896 7393 if (i.imm_operands)
2bbd9c25 7394 output_imm (insn_start_frag, insn_start_off);
29b0f896 7395 }
252b5132 7396
29b0f896
AM		 7397#ifdef DEBUG386
7398 if (flag_debug)
7399 {
7b81dfbb 7400 pi ("" /*line*/, &i);
29b0f896
AM		 7401 }
7402#endif /* DEBUG386 */
7403}
252b5132 7404
e205caa7
L		 7405/* Return the size of the displacement operand N. */
7406
7407static int
7408disp_size (unsigned int n)
7409{
7410 int size = 4;
43234a1e
L		 7411
7412 /* Vec_Disp8 has to be 8bit. */
7413 if (i.types[n].bitfield.vec_disp8)
7414 size = 1;
7415 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7416 size = 8;
7417 else if (i.types[n].bitfield.disp8)
7418 size = 1;
7419 else if (i.types[n].bitfield.disp16)
7420 size = 2;
e205caa7
L		 7421 return size;
7422}
7423
7424/* Return the size of the immediate operand N. */
7425
7426static int
7427imm_size (unsigned int n)
7428{
7429 int size = 4;
40fb9820
L		 7430 if (i.types[n].bitfield.imm64)
7431 size = 8;
7432 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7433 size = 1;
7434 else if (i.types[n].bitfield.imm16)
7435 size = 2;
e205caa7
L		 7436 return size;
7437}
7438
29b0f896 7439static void
64e74474 7440output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7441{
7442 char *p;
7443 unsigned int n;
252b5132 7444
29b0f896
AM		 7445 for (n = 0; n < i.operands; n++)
7446 {
43234a1e
L		 7447 if (i.types[n].bitfield.vec_disp8
7448 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7449 {
7450 if (i.op[n].disps->X_op == O_constant)
7451 {
e205caa7 7452 int size = disp_size (n);
43234a1e 7453 offsetT val = i.op[n].disps->X_add_number;
252b5132 7454
43234a1e
L		 7455 if (i.types[n].bitfield.vec_disp8)
7456 val >>= i.memshift;
7457 val = offset_in_range (val, size);
29b0f896
AM		 7458 p = frag_more (size);
7459 md_number_to_chars (p, val, size);
7460 }
7461 else
7462 {
f86103b7 7463 enum bfd_reloc_code_real reloc_type;
e205caa7 7464 int size = disp_size (n);
40fb9820 7465 int sign = i.types[n].bitfield.disp32s;
29b0f896 7466 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7467 fixS *fixP;
29b0f896 7468
e205caa7 7469 /* We can't have 8 bit displacement here. */
9c2799c2 7470 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7471
29b0f896
AM		 7472 /* The PC relative address is computed relative
7473 to the instruction boundary, so in case immediate
7474 fields follows, we need to adjust the value. */
7475 if (pcrel && i.imm_operands)
7476 {
29b0f896 7477 unsigned int n1;
e205caa7 7478 int sz = 0;
252b5132 7479
29b0f896 7480 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7481 if (operand_type_check (i.types[n1], imm))
252b5132 7482 {
e205caa7
L		 7483 /* Only one immediate is allowed for PC
7484 relative address. */
9c2799c2 7485 gas_assert (sz == 0);
e205caa7
L		 7486 sz = imm_size (n1);
7487 i.op[n].disps->X_add_number -= sz;
252b5132 7488 }
29b0f896 7489 /* We should find the immediate. */
9c2799c2 7490 gas_assert (sz != 0);
29b0f896 7491 }
520dc8e8 7492
29b0f896 7493 p = frag_more (size);
d258b828 7494 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7495 if (GOT_symbol
2bbd9c25 7496 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7497 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7498 || reloc_type == BFD_RELOC_X86_64_32S
7499 || (reloc_type == BFD_RELOC_64
7500 && object_64bit))
d6ab8113
JB		 7501 && (i.op[n].disps->X_op == O_symbol
7502 || (i.op[n].disps->X_op == O_add
7503 && ((symbol_get_value_expression
7504 (i.op[n].disps->X_op_symbol)->X_op)
7505 == O_subtract))))
7506 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7507 {
7508 offsetT add;
7509
7510 if (insn_start_frag == frag_now)
7511 add = (p - frag_now->fr_literal) - insn_start_off;
7512 else
7513 {
7514 fragS *fr;
7515
7516 add = insn_start_frag->fr_fix - insn_start_off;
7517 for (fr = insn_start_frag->fr_next;
7518 fr && fr != frag_now; fr = fr->fr_next)
7519 add += fr->fr_fix;
7520 add += p - frag_now->fr_literal;
7521 }
7522
4fa24527 7523 if (!object_64bit)
7b81dfbb
AJ		 7524 {
7525 reloc_type = BFD_RELOC_386_GOTPC;
7526 i.op[n].imms->X_add_number += add;
7527 }
7528 else if (reloc_type == BFD_RELOC_64)
7529 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7530 else
7b81dfbb
AJ		 7531 /* Don't do the adjustment for x86-64, as there
7532 the pcrel addressing is relative to the _next_
7533 insn, and that is taken care of in other code. */
d6ab8113 7534 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7535 }
02a86693
L		 7536 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7537 size, i.op[n].disps, pcrel,
7538 reloc_type);
7539 /* Check for "call/jmp *mem", "mov mem, %reg",
7540 "test %reg, mem" and "binop mem, %reg" where binop
7541 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7542 instructions. Always generate R_386_GOT32X for
7543 "sym*GOT" operand in 32-bit mode. */
7544 if ((generate_relax_relocations
7545 || (!object_64bit
7546 && i.rm.mode == 0
7547 && i.rm.regmem == 5))
7548 && (i.rm.mode == 2
7549 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7550 && ((i.operands == 1
7551 && i.tm.base_opcode == 0xff
7552 && (i.rm.reg == 2 || i.rm.reg == 4))
7553 || (i.operands == 2
7554 && (i.tm.base_opcode == 0x8b
7555 || i.tm.base_opcode == 0x85
7556 || (i.tm.base_opcode & 0xc7) == 0x03))))
7557 {
7558 if (object_64bit)
7559 {
7560 fixP->fx_tcbit = i.rex != 0;
7561 if (i.base_reg
7562 && (i.base_reg->reg_num == RegRip
7563 || i.base_reg->reg_num == RegEip))
7564 fixP->fx_tcbit2 = 1;
7565 }
7566 else
7567 fixP->fx_tcbit2 = 1;
7568 }
29b0f896
AM		 7569 }
7570 }
7571 }
7572}
252b5132 7573
29b0f896 7574static void
64e74474 7575output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7576{
7577 char *p;
7578 unsigned int n;
252b5132 7579
29b0f896
AM		 7580 for (n = 0; n < i.operands; n++)
7581 {
43234a1e
L		 7582 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7583 if (i.rounding && (int) n == i.rounding->operand)
7584 continue;
7585
40fb9820 7586 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7587 {
7588 if (i.op[n].imms->X_op == O_constant)
7589 {
e205caa7 7590 int size = imm_size (n);
29b0f896 7591 offsetT val;
b4cac588 7592
29b0f896
AM		 7593 val = offset_in_range (i.op[n].imms->X_add_number,
7594 size);
7595 p = frag_more (size);
7596 md_number_to_chars (p, val, size);
7597 }
7598 else
7599 {
7600 /* Not absolute_section.
7601 Need a 32-bit fixup (don't support 8bit
7602 non-absolute imms). Try to support other
7603 sizes ... */
f86103b7 7604 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7605 int size = imm_size (n);
7606 int sign;
29b0f896 7607
40fb9820 7608 if (i.types[n].bitfield.imm32s
a7d61044 7609 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7610 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7611 sign = 1;
e205caa7
L		 7612 else
7613 sign = 0;
520dc8e8 7614
29b0f896 7615 p = frag_more (size);
d258b828 7616 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7617
2bbd9c25
JJ		 7618 /* This is tough to explain. We end up with this one if we
7619 * have operands that look like
7620 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7621 * obtain the absolute address of the GOT, and it is strongly
7622 * preferable from a performance point of view to avoid using
7623 * a runtime relocation for this. The actual sequence of
7624 * instructions often look something like:
7625 *
7626 * call .L66
7627 * .L66:
7628 * popl %ebx
7629 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7630 *
7631 * The call and pop essentially return the absolute address
7632 * of the label .L66 and store it in %ebx. The linker itself
7633 * will ultimately change the first operand of the addl so
7634 * that %ebx points to the GOT, but to keep things simple, the
7635 * .o file must have this operand set so that it generates not
7636 * the absolute address of .L66, but the absolute address of
7637 * itself. This allows the linker itself simply treat a GOTPC
7638 * relocation as asking for a pcrel offset to the GOT to be
7639 * added in, and the addend of the relocation is stored in the
7640 * operand field for the instruction itself.
7641 *
7642 * Our job here is to fix the operand so that it would add
7643 * the correct offset so that %ebx would point to itself. The
7644 * thing that is tricky is that .-.L66 will point to the
7645 * beginning of the instruction, so we need to further modify
7646 * the operand so that it will point to itself. There are
7647 * other cases where you have something like:
7648 *
7649 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7650 *
7651 * and here no correction would be required. Internally in
7652 * the assembler we treat operands of this form as not being
7653 * pcrel since the '.' is explicitly mentioned, and I wonder
7654 * whether it would simplify matters to do it this way. Who
7655 * knows. In earlier versions of the PIC patches, the
7656 * pcrel_adjust field was used to store the correction, but
7657 * since the expression is not pcrel, I felt it would be
7658 * confusing to do it this way. */
7659
d6ab8113 7660 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7661 || reloc_type == BFD_RELOC_X86_64_32S
7662 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7663 && GOT_symbol
7664 && GOT_symbol == i.op[n].imms->X_add_symbol
7665 && (i.op[n].imms->X_op == O_symbol
7666 || (i.op[n].imms->X_op == O_add
7667 && ((symbol_get_value_expression
7668 (i.op[n].imms->X_op_symbol)->X_op)
7669 == O_subtract))))
7670 {
2bbd9c25
JJ		 7671 offsetT add;
7672
7673 if (insn_start_frag == frag_now)
7674 add = (p - frag_now->fr_literal) - insn_start_off;
7675 else
7676 {
7677 fragS *fr;
7678
7679 add = insn_start_frag->fr_fix - insn_start_off;
7680 for (fr = insn_start_frag->fr_next;
7681 fr && fr != frag_now; fr = fr->fr_next)
7682 add += fr->fr_fix;
7683 add += p - frag_now->fr_literal;
7684 }
7685
4fa24527 7686 if (!object_64bit)
d6ab8113 7687 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7688 else if (size == 4)
d6ab8113 7689 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7690 else if (size == 8)
7691 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7692 i.op[n].imms->X_add_number += add;
29b0f896 7693 }
29b0f896
AM		 7694 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7695 i.op[n].imms, 0, reloc_type);
7696 }
7697 }
7698 }
252b5132
RH		 7699}
7700\f
d182319b
JB		 7701/* x86_cons_fix_new is called via the expression parsing code when a
7702 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7703static int cons_sign = -1;
7704
7705void
e3bb37b5 7706x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7707 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7708{
d258b828 7709 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7710
7711#ifdef TE_PE
7712 if (exp->X_op == O_secrel)
7713 {
7714 exp->X_op = O_symbol;
7715 r = BFD_RELOC_32_SECREL;
7716 }
7717#endif
7718
7719 fix_new_exp (frag, off, len, exp, 0, r);
7720}
7721
357d1bd8
L		 7722/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7723 purpose of the `.dc.a' internal pseudo-op. */
7724
7725int
7726x86_address_bytes (void)
7727{
7728 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7729 return 4;
7730 return stdoutput->arch_info->bits_per_address / 8;
7731}
7732
d382c579
TG		 7733#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7734 || defined (LEX_AT)
d258b828 7735# define lex_got(reloc, adjust, types) NULL
718ddfc0 7736#else
f3c180ae
AM		 7737/* Parse operands of the form
7738 <symbol>@GOTOFF+<nnn>
7739 and similar .plt or .got references.
7740
7741 If we find one, set up the correct relocation in RELOC and copy the
7742 input string, minus the `@GOTOFF' into a malloc'd buffer for
7743 parsing by the calling routine. Return this buffer, and if ADJUST
7744 is non-null set it to the length of the string we removed from the
7745 input line. Otherwise return NULL. */
7746static char *
91d6fa6a 7747lex_got (enum bfd_reloc_code_real *rel,
64e74474 7748 int *adjust,
d258b828 7749 i386_operand_type *types)
f3c180ae 7750{
7b81dfbb
AJ		 7751 /* Some of the relocations depend on the size of what field is to
7752 be relocated. But in our callers i386_immediate and i386_displacement
7753 we don't yet know the operand size (this will be set by insn
7754 matching). Hence we record the word32 relocation here,
7755 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7756 static const struct {
7757 const char *str;
cff8d58a 7758 int len;
4fa24527 7759 const enum bfd_reloc_code_real rel[2];
40fb9820 7760 const i386_operand_type types64;
f3c180ae 7761 } gotrel[] = {
8ce3d284 7762#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7763 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7764 BFD_RELOC_SIZE32 },
7765 OPERAND_TYPE_IMM32_64 },
8ce3d284 7766#endif
cff8d58a
L		 7767 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7768 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7769 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7770 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7771 BFD_RELOC_X86_64_PLT32 },
40fb9820 7772 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7773 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7774 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7775 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7776 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7777 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7778 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7779 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7780 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7781 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7782 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7783 BFD_RELOC_X86_64_TLSGD },
40fb9820 7784 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7785 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7786 _dummy_first_bfd_reloc_code_real },
40fb9820 7787 OPERAND_TYPE_NONE },
cff8d58a
L		 7788 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7789 BFD_RELOC_X86_64_TLSLD },
40fb9820 7790 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7791 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7792 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7793 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7794 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7795 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7796 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7797 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7798 _dummy_first_bfd_reloc_code_real },
40fb9820 7799 OPERAND_TYPE_NONE },
cff8d58a
L		 7800 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7801 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7802 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7803 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7804 _dummy_first_bfd_reloc_code_real },
40fb9820 7805 OPERAND_TYPE_NONE },
cff8d58a
L		 7806 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7807 _dummy_first_bfd_reloc_code_real },
40fb9820 7808 OPERAND_TYPE_NONE },
cff8d58a
L		 7809 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7810 BFD_RELOC_X86_64_GOT32 },
40fb9820 7811 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7812 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7813 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7814 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7815 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7816 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7817 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7818 };
7819 char *cp;
7820 unsigned int j;
7821
d382c579 7822#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7823 if (!IS_ELF)
7824 return NULL;
d382c579 7825#endif
718ddfc0 7826
f3c180ae 7827 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7828 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7829 return NULL;
7830
47465058 7831 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7832 {
cff8d58a 7833 int len = gotrel[j].len;
28f81592 7834 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7835 {
4fa24527 7836 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7837 {
28f81592
AM		 7838 int first, second;
7839 char *tmpbuf, *past_reloc;
f3c180ae 7840
91d6fa6a 7841 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7842
3956db08
JB		 7843 if (types)
7844 {
7845 if (flag_code != CODE_64BIT)
40fb9820
L		 7846 {
7847 types->bitfield.imm32 = 1;
7848 types->bitfield.disp32 = 1;
7849 }
3956db08
JB		 7850 else
7851 *types = gotrel[j].types64;
7852 }
7853
8fd4256d 7854 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7855 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7856
28f81592 7857 /* The length of the first part of our input line. */
f3c180ae 7858 first = cp - input_line_pointer;
28f81592
AM		 7859
7860 /* The second part goes from after the reloc token until
67c11a9b 7861 (and including) an end_of_line char or comma. */
28f81592 7862 past_reloc = cp + 1 + len;
67c11a9b
AM		 7863 cp = past_reloc;
7864 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7865 ++cp;
7866 second = cp + 1 - past_reloc;
28f81592
AM		 7867
7868 /* Allocate and copy string. The trailing NUL shouldn't
7869 be necessary, but be safe. */
add39d23 7870 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7871 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7872 if (second != 0 && *past_reloc != ' ')
7873 /* Replace the relocation token with ' ', so that
7874 errors like foo@GOTOFF1 will be detected. */
7875 tmpbuf[first++] = ' ';
af89796a
L		 7876 else
7877 /* Increment length by 1 if the relocation token is
7878 removed. */
7879 len++;
7880 if (adjust)
7881 *adjust = len;
0787a12d
AM		 7882 memcpy (tmpbuf + first, past_reloc, second);
7883 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7884 return tmpbuf;
7885 }
7886
4fa24527
JB		 7887 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7888 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7889 return NULL;
7890 }
7891 }
7892
7893 /* Might be a symbol version string. Don't as_bad here. */
7894 return NULL;
7895}
4e4f7c87 7896#endif
f3c180ae 7897
a988325c
NC		 7898#ifdef TE_PE
7899#ifdef lex_got
7900#undef lex_got
7901#endif
7902/* Parse operands of the form
7903 <symbol>@SECREL32+<nnn>
7904
7905 If we find one, set up the correct relocation in RELOC and copy the
7906 input string, minus the `@SECREL32' into a malloc'd buffer for
7907 parsing by the calling routine. Return this buffer, and if ADJUST
7908 is non-null set it to the length of the string we removed from the
34bca508
L		 7909 input line. Otherwise return NULL.
7910
a988325c
NC		 7911 This function is copied from the ELF version above adjusted for PE targets. */
7912
7913static char *
7914lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7915 int *adjust ATTRIBUTE_UNUSED,
d258b828 7916 i386_operand_type *types)
a988325c
NC		 7917{
7918 static const struct
7919 {
7920 const char *str;
7921 int len;
7922 const enum bfd_reloc_code_real rel[2];
7923 const i386_operand_type types64;
7924 }
7925 gotrel[] =
7926 {
7927 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7928 BFD_RELOC_32_SECREL },
7929 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7930 };
7931
7932 char *cp;
7933 unsigned j;
7934
7935 for (cp = input_line_pointer; *cp != '@'; cp++)
7936 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7937 return NULL;
7938
7939 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7940 {
7941 int len = gotrel[j].len;
7942
7943 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7944 {
7945 if (gotrel[j].rel[object_64bit] != 0)
7946 {
7947 int first, second;
7948 char *tmpbuf, *past_reloc;
7949
7950 *rel = gotrel[j].rel[object_64bit];
7951 if (adjust)
7952 *adjust = len;
7953
7954 if (types)
7955 {
7956 if (flag_code != CODE_64BIT)
7957 {
7958 types->bitfield.imm32 = 1;
7959 types->bitfield.disp32 = 1;
7960 }
7961 else
7962 *types = gotrel[j].types64;
7963 }
7964
7965 /* The length of the first part of our input line. */
7966 first = cp - input_line_pointer;
7967
7968 /* The second part goes from after the reloc token until
7969 (and including) an end_of_line char or comma. */
7970 past_reloc = cp + 1 + len;
7971 cp = past_reloc;
7972 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7973 ++cp;
7974 second = cp + 1 - past_reloc;
7975
7976 /* Allocate and copy string. The trailing NUL shouldn't
7977 be necessary, but be safe. */
add39d23 7978 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7979 memcpy (tmpbuf, input_line_pointer, first);
7980 if (second != 0 && *past_reloc != ' ')
7981 /* Replace the relocation token with ' ', so that
7982 errors like foo@SECLREL321 will be detected. */
7983 tmpbuf[first++] = ' ';
7984 memcpy (tmpbuf + first, past_reloc, second);
7985 tmpbuf[first + second] = '\0';
7986 return tmpbuf;
7987 }
7988
7989 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7990 gotrel[j].str, 1 << (5 + object_64bit));
7991 return NULL;
7992 }
7993 }
7994
7995 /* Might be a symbol version string. Don't as_bad here. */
7996 return NULL;
7997}
7998
7999#endif /* TE_PE */
8000
62ebcb5c 8001bfd_reloc_code_real_type
e3bb37b5 8002x86_cons (expressionS *exp, int size)
f3c180ae 8003{
62ebcb5c
AM		 8004 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8005
ee86248c
JB		 8006 intel_syntax = -intel_syntax;
8007
3c7b9c2c 8008 exp->X_md = 0;
4fa24527 8009 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8010 {
8011 /* Handle @GOTOFF and the like in an expression. */
8012 char *save;
8013 char *gotfree_input_line;
4a57f2cf 8014 int adjust = 0;
f3c180ae
AM		 8015
8016 save = input_line_pointer;
d258b828 8017 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8018 if (gotfree_input_line)
8019 input_line_pointer = gotfree_input_line;
8020
8021 expression (exp);
8022
8023 if (gotfree_input_line)
8024 {
8025 /* expression () has merrily parsed up to the end of line,
8026 or a comma - in the wrong buffer. Transfer how far
8027 input_line_pointer has moved to the right buffer. */
8028 input_line_pointer = (save
8029 + (input_line_pointer - gotfree_input_line)
8030 + adjust);
8031 free (gotfree_input_line);
3992d3b7
AM		 8032 if (exp->X_op == O_constant
8033 || exp->X_op == O_absent
8034 || exp->X_op == O_illegal
0398aac5 8035 || exp->X_op == O_register
3992d3b7
AM		 8036 || exp->X_op == O_big)
8037 {
8038 char c = *input_line_pointer;
8039 *input_line_pointer = 0;
8040 as_bad (_("missing or invalid expression `%s'"), save);
8041 *input_line_pointer = c;
8042 }
f3c180ae
AM		 8043 }
8044 }
8045 else
8046 expression (exp);
ee86248c
JB		 8047
8048 intel_syntax = -intel_syntax;
8049
8050 if (intel_syntax)
8051 i386_intel_simplify (exp);
62ebcb5c
AM		 8052
8053 return got_reloc;
f3c180ae 8054}
f3c180ae 8055
9f32dd5b
L		 8056static void
8057signed_cons (int size)
6482c264 8058{
d182319b
JB		 8059 if (flag_code == CODE_64BIT)
8060 cons_sign = 1;
8061 cons (size);
8062 cons_sign = -1;
6482c264
NC		 8063}
8064
d182319b 8065#ifdef TE_PE
6482c264 8066static void
7016a5d5 8067pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8068{
8069 expressionS exp;
8070
8071 do
8072 {
8073 expression (&exp);
8074 if (exp.X_op == O_symbol)
8075 exp.X_op = O_secrel;
8076
8077 emit_expr (&exp, 4);
8078 }
8079 while (*input_line_pointer++ == ',');
8080
8081 input_line_pointer--;
8082 demand_empty_rest_of_line ();
8083}
6482c264
NC		 8084#endif
8085
43234a1e
L		 8086/* Handle Vector operations. */
8087
8088static char *
8089check_VecOperations (char *op_string, char *op_end)
8090{
8091 const reg_entry *mask;
8092 const char *saved;
8093 char *end_op;
8094
8095 while (*op_string
8096 && (op_end == NULL || op_string < op_end))
8097 {
8098 saved = op_string;
8099 if (*op_string == '{')
8100 {
8101 op_string++;
8102
8103 /* Check broadcasts. */
8104 if (strncmp (op_string, "1to", 3) == 0)
8105 {
8106 int bcst_type;
8107
8108 if (i.broadcast)
8109 goto duplicated_vec_op;
8110
8111 op_string += 3;
8112 if (*op_string == '8')
8113 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8114 else if (*op_string == '4')
8115 bcst_type = BROADCAST_1TO4;
8116 else if (*op_string == '2')
8117 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8118 else if (*op_string == '1'
8119 && *(op_string+1) == '6')
8120 {
8121 bcst_type = BROADCAST_1TO16;
8122 op_string++;
8123 }
8124 else
8125 {
8126 as_bad (_("Unsupported broadcast: `%s'"), saved);
8127 return NULL;
8128 }
8129 op_string++;
8130
8131 broadcast_op.type = bcst_type;
8132 broadcast_op.operand = this_operand;
8133 i.broadcast = &broadcast_op;
8134 }
8135 /* Check masking operation. */
8136 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8137 {
8138 /* k0 can't be used for write mask. */
8139 if (mask->reg_num == 0)
8140 {
8141 as_bad (_("`%s' can't be used for write mask"),
8142 op_string);
8143 return NULL;
8144 }
8145
8146 if (!i.mask)
8147 {
8148 mask_op.mask = mask;
8149 mask_op.zeroing = 0;
8150 mask_op.operand = this_operand;
8151 i.mask = &mask_op;
8152 }
8153 else
8154 {
8155 if (i.mask->mask)
8156 goto duplicated_vec_op;
8157
8158 i.mask->mask = mask;
8159
8160 /* Only "{z}" is allowed here. No need to check
8161 zeroing mask explicitly. */
8162 if (i.mask->operand != this_operand)
8163 {
8164 as_bad (_("invalid write mask `%s'"), saved);
8165 return NULL;
8166 }
8167 }
8168
8169 op_string = end_op;
8170 }
8171 /* Check zeroing-flag for masking operation. */
8172 else if (*op_string == 'z')
8173 {
8174 if (!i.mask)
8175 {
8176 mask_op.mask = NULL;
8177 mask_op.zeroing = 1;
8178 mask_op.operand = this_operand;
8179 i.mask = &mask_op;
8180 }
8181 else
8182 {
8183 if (i.mask->zeroing)
8184 {
8185 duplicated_vec_op:
8186 as_bad (_("duplicated `%s'"), saved);
8187 return NULL;
8188 }
8189
8190 i.mask->zeroing = 1;
8191
8192 /* Only "{%k}" is allowed here. No need to check mask
8193 register explicitly. */
8194 if (i.mask->operand != this_operand)
8195 {
8196 as_bad (_("invalid zeroing-masking `%s'"),
8197 saved);
8198 return NULL;
8199 }
8200 }
8201
8202 op_string++;
8203 }
8204 else
8205 goto unknown_vec_op;
8206
8207 if (*op_string != '}')
8208 {
8209 as_bad (_("missing `}' in `%s'"), saved);
8210 return NULL;
8211 }
8212 op_string++;
8213 continue;
8214 }
8215 unknown_vec_op:
8216 /* We don't know this one. */
8217 as_bad (_("unknown vector operation: `%s'"), saved);
8218 return NULL;
8219 }
8220
8221 return op_string;
8222}
8223
252b5132 8224static int
70e41ade 8225i386_immediate (char *imm_start)
252b5132
RH		 8226{
8227 char *save_input_line_pointer;
f3c180ae 8228 char *gotfree_input_line;
252b5132 8229 segT exp_seg = 0;
47926f60 8230 expressionS *exp;
40fb9820
L		 8231 i386_operand_type types;
8232
0dfbf9d7 8233 operand_type_set (&types, ~0);
252b5132
RH		 8234
8235 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8236 {
31b2323c
L		 8237 as_bad (_("at most %d immediate operands are allowed"),
8238 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8239 return 0;
8240 }
8241
8242 exp = &im_expressions[i.imm_operands++];
520dc8e8 8243 i.op[this_operand].imms = exp;
252b5132
RH		 8244
8245 if (is_space_char (*imm_start))
8246 ++imm_start;
8247
8248 save_input_line_pointer = input_line_pointer;
8249 input_line_pointer = imm_start;
8250
d258b828 8251 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8252 if (gotfree_input_line)
8253 input_line_pointer = gotfree_input_line;
252b5132
RH		 8254
8255 exp_seg = expression (exp);
8256
83183c0c 8257 SKIP_WHITESPACE ();
43234a1e
L		 8258
8259 /* Handle vector operations. */
8260 if (*input_line_pointer == '{')
8261 {
8262 input_line_pointer = check_VecOperations (input_line_pointer,
8263 NULL);
8264 if (input_line_pointer == NULL)
8265 return 0;
8266 }
8267
252b5132 8268 if (*input_line_pointer)
f3c180ae 8269 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8270
8271 input_line_pointer = save_input_line_pointer;
f3c180ae 8272 if (gotfree_input_line)
ee86248c
JB		 8273 {
8274 free (gotfree_input_line);
8275
8276 if (exp->X_op == O_constant || exp->X_op == O_register)
8277 exp->X_op = O_illegal;
8278 }
8279
8280 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8281}
252b5132 8282
ee86248c
JB		 8283static int
8284i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8285 i386_operand_type types, const char *imm_start)
8286{
8287 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8288 {
313c53d1
L		 8289 if (imm_start)
8290 as_bad (_("missing or invalid immediate expression `%s'"),
8291 imm_start);
3992d3b7 8292 return 0;
252b5132 8293 }
3e73aa7c 8294 else if (exp->X_op == O_constant)
252b5132 8295 {
47926f60 8296 /* Size it properly later. */
40fb9820 8297 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8298 /* If not 64bit, sign extend val. */
8299 if (flag_code != CODE_64BIT
4eed87de
AM		 8300 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8301 exp->X_add_number
8302 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8303 }
4c63da97 8304#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8305 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8306 && exp_seg != absolute_section
47926f60 8307 && exp_seg != text_section
24eab124
AM		 8308 && exp_seg != data_section
8309 && exp_seg != bss_section
8310 && exp_seg != undefined_section
f86103b7 8311 && !bfd_is_com_section (exp_seg))
252b5132 8312 {
d0b47220 8313 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8314 return 0;
8315 }
8316#endif
a841bdf5 8317 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8318 {
313c53d1
L		 8319 if (imm_start)
8320 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8321 return 0;
8322 }
252b5132
RH		 8323 else
8324 {
8325 /* This is an address. The size of the address will be
24eab124 8326 determined later, depending on destination register,
3e73aa7c 8327 suffix, or the default for the section. */
40fb9820
L		 8328 i.types[this_operand].bitfield.imm8 = 1;
8329 i.types[this_operand].bitfield.imm16 = 1;
8330 i.types[this_operand].bitfield.imm32 = 1;
8331 i.types[this_operand].bitfield.imm32s = 1;
8332 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8333 i.types[this_operand] = operand_type_and (i.types[this_operand],
8334 types);
252b5132
RH		 8335 }
8336
8337 return 1;
8338}
8339
551c1ca1 8340static char *
e3bb37b5 8341i386_scale (char *scale)
252b5132 8342{
551c1ca1
AM		 8343 offsetT val;
8344 char *save = input_line_pointer;
252b5132 8345
551c1ca1
AM		 8346 input_line_pointer = scale;
8347 val = get_absolute_expression ();
8348
8349 switch (val)
252b5132 8350 {
551c1ca1 8351 case 1:
252b5132
RH		 8352 i.log2_scale_factor = 0;
8353 break;
551c1ca1 8354 case 2:
252b5132
RH		 8355 i.log2_scale_factor = 1;
8356 break;
551c1ca1 8357 case 4:
252b5132
RH		 8358 i.log2_scale_factor = 2;
8359 break;
551c1ca1 8360 case 8:
252b5132
RH		 8361 i.log2_scale_factor = 3;
8362 break;
8363 default:
a724f0f4
JB		 8364 {
8365 char sep = *input_line_pointer;
8366
8367 *input_line_pointer = '\0';
8368 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8369 scale);
8370 *input_line_pointer = sep;
8371 input_line_pointer = save;
8372 return NULL;
8373 }
252b5132 8374 }
29b0f896 8375 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8376 {
8377 as_warn (_("scale factor of %d without an index register"),
24eab124 8378 1 << i.log2_scale_factor);
252b5132 8379 i.log2_scale_factor = 0;
252b5132 8380 }
551c1ca1
AM		 8381 scale = input_line_pointer;
8382 input_line_pointer = save;
8383 return scale;
252b5132
RH		 8384}
8385
252b5132 8386static int
e3bb37b5 8387i386_displacement (char *disp_start, char *disp_end)
252b5132 8388{
29b0f896 8389 expressionS *exp;
252b5132
RH		 8390 segT exp_seg = 0;
8391 char *save_input_line_pointer;
f3c180ae 8392 char *gotfree_input_line;
40fb9820
L		 8393 int override;
8394 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8395 int ret;
252b5132 8396
31b2323c
L		 8397 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8398 {
8399 as_bad (_("at most %d displacement operands are allowed"),
8400 MAX_MEMORY_OPERANDS);
8401 return 0;
8402 }
8403
0dfbf9d7 8404 operand_type_set (&bigdisp, 0);
40fb9820
L		 8405 if ((i.types[this_operand].bitfield.jumpabsolute)
8406 || (!current_templates->start->opcode_modifier.jump
8407 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8408 {
40fb9820 8409 bigdisp.bitfield.disp32 = 1;
e05278af 8410 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8411 if (flag_code == CODE_64BIT)
8412 {
8413 if (!override)
8414 {
8415 bigdisp.bitfield.disp32s = 1;
8416 bigdisp.bitfield.disp64 = 1;
8417 }
8418 }
8419 else if ((flag_code == CODE_16BIT) ^ override)
8420 {
8421 bigdisp.bitfield.disp32 = 0;
8422 bigdisp.bitfield.disp16 = 1;
8423 }
e05278af
JB		 8424 }
8425 else
8426 {
8427 /* For PC-relative branches, the width of the displacement
8428 is dependent upon data size, not address size. */
e05278af 8429 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8430 if (flag_code == CODE_64BIT)
8431 {
8432 if (override || i.suffix == WORD_MNEM_SUFFIX)
8433 bigdisp.bitfield.disp16 = 1;
8434 else
8435 {
8436 bigdisp.bitfield.disp32 = 1;
8437 bigdisp.bitfield.disp32s = 1;
8438 }
8439 }
8440 else
e05278af
JB		 8441 {
8442 if (!override)
8443 override = (i.suffix == (flag_code != CODE_16BIT
8444 ? WORD_MNEM_SUFFIX
8445 : LONG_MNEM_SUFFIX));
40fb9820
L		 8446 bigdisp.bitfield.disp32 = 1;
8447 if ((flag_code == CODE_16BIT) ^ override)
8448 {
8449 bigdisp.bitfield.disp32 = 0;
8450 bigdisp.bitfield.disp16 = 1;
8451 }
e05278af 8452 }
e05278af 8453 }
c6fb90c8
L		 8454 i.types[this_operand] = operand_type_or (i.types[this_operand],
8455 bigdisp);
252b5132
RH		 8456
8457 exp = &disp_expressions[i.disp_operands];
520dc8e8 8458 i.op[this_operand].disps = exp;
252b5132
RH		 8459 i.disp_operands++;
8460 save_input_line_pointer = input_line_pointer;
8461 input_line_pointer = disp_start;
8462 END_STRING_AND_SAVE (disp_end);
8463
8464#ifndef GCC_ASM_O_HACK
8465#define GCC_ASM_O_HACK 0
8466#endif
8467#if GCC_ASM_O_HACK
8468 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8469 if (i.types[this_operand].bitfield.baseIndex
24eab124 8470 && displacement_string_end[-1] == '+')
252b5132
RH		 8471 {
8472 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8473 constraint within gcc asm statements.
8474 For instance:
8475
8476 #define _set_tssldt_desc(n,addr,limit,type) \
8477 __asm__ __volatile__ ( \
8478 "movw %w2,%0\n\t" \
8479 "movw %w1,2+%0\n\t" \
8480 "rorl $16,%1\n\t" \
8481 "movb %b1,4+%0\n\t" \
8482 "movb %4,5+%0\n\t" \
8483 "movb $0,6+%0\n\t" \
8484 "movb %h1,7+%0\n\t" \
8485 "rorl $16,%1" \
8486 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8487
8488 This works great except that the output assembler ends
8489 up looking a bit weird if it turns out that there is
8490 no offset. You end up producing code that looks like:
8491
8492 #APP
8493 movw $235,(%eax)
8494 movw %dx,2+(%eax)
8495 rorl $16,%edx
8496 movb %dl,4+(%eax)
8497 movb $137,5+(%eax)
8498 movb $0,6+(%eax)
8499 movb %dh,7+(%eax)
8500 rorl $16,%edx
8501 #NO_APP
8502
47926f60 8503 So here we provide the missing zero. */
24eab124
AM		 8504
8505 *displacement_string_end = '0';
252b5132
RH		 8506 }
8507#endif
d258b828 8508 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8509 if (gotfree_input_line)
8510 input_line_pointer = gotfree_input_line;
252b5132 8511
24eab124 8512 exp_seg = expression (exp);
252b5132 8513
636c26b0
AM		 8514 SKIP_WHITESPACE ();
8515 if (*input_line_pointer)
8516 as_bad (_("junk `%s' after expression"), input_line_pointer);
8517#if GCC_ASM_O_HACK
8518 RESTORE_END_STRING (disp_end + 1);
8519#endif
636c26b0 8520 input_line_pointer = save_input_line_pointer;
636c26b0 8521 if (gotfree_input_line)
ee86248c
JB		 8522 {
8523 free (gotfree_input_line);
8524
8525 if (exp->X_op == O_constant || exp->X_op == O_register)
8526 exp->X_op = O_illegal;
8527 }
8528
8529 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8530
8531 RESTORE_END_STRING (disp_end);
8532
8533 return ret;
8534}
8535
8536static int
8537i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8538 i386_operand_type types, const char *disp_start)
8539{
8540 i386_operand_type bigdisp;
8541 int ret = 1;
636c26b0 8542
24eab124
AM		 8543 /* We do this to make sure that the section symbol is in
8544 the symbol table. We will ultimately change the relocation
47926f60 8545 to be relative to the beginning of the section. */
1ae12ab7 8546 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8547 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8548 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8549 {
636c26b0 8550 if (exp->X_op != O_symbol)
3992d3b7 8551 goto inv_disp;
636c26b0 8552
e5cb08ac 8553 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8554 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8555 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8556 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8557 exp->X_op = O_subtract;
8558 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8559 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8560 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8561 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8562 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8563 else
29b0f896 8564 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8565 }
252b5132 8566
3992d3b7
AM		 8567 else if (exp->X_op == O_absent
8568 || exp->X_op == O_illegal
ee86248c 8569 || exp->X_op == O_big)
2daf4fd8 8570 {
3992d3b7
AM		 8571 inv_disp:
8572 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8573 disp_start);
3992d3b7 8574 ret = 0;
2daf4fd8
AM		 8575 }
8576
0e1147d9
L		 8577 else if (flag_code == CODE_64BIT
8578 && !i.prefix[ADDR_PREFIX]
8579 && exp->X_op == O_constant)
8580 {
8581 /* Since displacement is signed extended to 64bit, don't allow
8582 disp32 and turn off disp32s if they are out of range. */
8583 i.types[this_operand].bitfield.disp32 = 0;
8584 if (!fits_in_signed_long (exp->X_add_number))
8585 {
8586 i.types[this_operand].bitfield.disp32s = 0;
8587 if (i.types[this_operand].bitfield.baseindex)
8588 {
8589 as_bad (_("0x%lx out range of signed 32bit displacement"),
8590 (long) exp->X_add_number);
8591 ret = 0;
8592 }
8593 }
8594 }
8595
4c63da97 8596#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8597 else if (exp->X_op != O_constant
8598 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8599 && exp_seg != absolute_section
8600 && exp_seg != text_section
8601 && exp_seg != data_section
8602 && exp_seg != bss_section
8603 && exp_seg != undefined_section
8604 && !bfd_is_com_section (exp_seg))
24eab124 8605 {
d0b47220 8606 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8607 ret = 0;
24eab124 8608 }
252b5132 8609#endif
3956db08 8610
40fb9820
L		 8611 /* Check if this is a displacement only operand. */
8612 bigdisp = i.types[this_operand];
8613 bigdisp.bitfield.disp8 = 0;
8614 bigdisp.bitfield.disp16 = 0;
8615 bigdisp.bitfield.disp32 = 0;
8616 bigdisp.bitfield.disp32s = 0;
8617 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8618 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8619 i.types[this_operand] = operand_type_and (i.types[this_operand],
8620 types);
3956db08 8621
3992d3b7 8622 return ret;
252b5132
RH		 8623}
8624
eecb386c 8625/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8626 Return 1 on success, 0 on a failure. */
8627
252b5132 8628static int
e3bb37b5 8629i386_index_check (const char *operand_string)
252b5132 8630{
fc0763e6 8631 const char *kind = "base/index";
be05d201
L		 8632 enum flag_code addr_mode;
8633
8634 if (i.prefix[ADDR_PREFIX])
8635 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8636 else
8637 {
8638 addr_mode = flag_code;
8639
24eab124 8640#if INFER_ADDR_PREFIX
be05d201
L		 8641 if (i.mem_operands == 0)
8642 {
8643 /* Infer address prefix from the first memory operand. */
8644 const reg_entry *addr_reg = i.base_reg;
8645
8646 if (addr_reg == NULL)
8647 addr_reg = i.index_reg;
eecb386c 8648
be05d201
L		 8649 if (addr_reg)
8650 {
8651 if (addr_reg->reg_num == RegEip
8652 || addr_reg->reg_num == RegEiz
8653 || addr_reg->reg_type.bitfield.reg32)
8654 addr_mode = CODE_32BIT;
8655 else if (flag_code != CODE_64BIT
8656 && addr_reg->reg_type.bitfield.reg16)
8657 addr_mode = CODE_16BIT;
8658
8659 if (addr_mode != flag_code)
8660 {
8661 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8662 i.prefixes += 1;
8663 /* Change the size of any displacement too. At most one
8664 of Disp16 or Disp32 is set.
8665 FIXME. There doesn't seem to be any real need for
8666 separate Disp16 and Disp32 flags. The same goes for
8667 Imm16 and Imm32. Removing them would probably clean
8668 up the code quite a lot. */
8669 if (flag_code != CODE_64BIT
8670 && (i.types[this_operand].bitfield.disp16
8671 || i.types[this_operand].bitfield.disp32))
8672 i.types[this_operand]
8673 = operand_type_xor (i.types[this_operand], disp16_32);
8674 }
8675 }
8676 }
24eab124 8677#endif
be05d201
L		 8678 }
8679
fc0763e6
JB		 8680 if (current_templates->start->opcode_modifier.isstring
8681 && !current_templates->start->opcode_modifier.immext
8682 && (current_templates->end[-1].opcode_modifier.isstring
8683 || i.mem_operands))
8684 {
8685 /* Memory operands of string insns are special in that they only allow
8686 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8687 const reg_entry *expected_reg;
8688 static const char *di_si[][2] =
8689 {
8690 { "esi", "edi" },
8691 { "si", "di" },
8692 { "rsi", "rdi" }
8693 };
8694 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8695
8696 kind = "string address";
8697
8325cc63 8698 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8699 {
8700 i386_operand_type type = current_templates->end[-1].operand_types[0];
8701
8702 if (!type.bitfield.baseindex
8703 || ((!i.mem_operands != !intel_syntax)
8704 && current_templates->end[-1].operand_types[1]
8705 .bitfield.baseindex))
8706 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8707 expected_reg = hash_find (reg_hash,
8708 di_si[addr_mode][type.bitfield.esseg]);
8709
fc0763e6
JB		 8710 }
8711 else
be05d201 8712 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8713
be05d201
L		 8714 if (i.base_reg != expected_reg
8715 || i.index_reg
fc0763e6 8716 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8717 {
be05d201
L		 8718 /* The second memory operand must have the same size as
8719 the first one. */
8720 if (i.mem_operands
8721 && i.base_reg
8722 && !((addr_mode == CODE_64BIT
8723 && i.base_reg->reg_type.bitfield.reg64)
8724 || (addr_mode == CODE_32BIT
8725 ? i.base_reg->reg_type.bitfield.reg32
8726 : i.base_reg->reg_type.bitfield.reg16)))
8727 goto bad_address;
8728
fc0763e6
JB		 8729 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8730 operand_string,
8731 intel_syntax ? '[' : '(',
8732 register_prefix,
be05d201 8733 expected_reg->reg_name,
fc0763e6 8734 intel_syntax ? ']' : ')');
be05d201 8735 return 1;
fc0763e6 8736 }
be05d201
L		 8737 else
8738 return 1;
8739
8740bad_address:
8741 as_bad (_("`%s' is not a valid %s expression"),
8742 operand_string, kind);
8743 return 0;
3e73aa7c
JH		 8744 }
8745 else
8746 {
be05d201
L		 8747 if (addr_mode != CODE_16BIT)
8748 {
8749 /* 32-bit/64-bit checks. */
8750 if ((i.base_reg
8751 && (addr_mode == CODE_64BIT
8752 ? !i.base_reg->reg_type.bitfield.reg64
8753 : !i.base_reg->reg_type.bitfield.reg32)
8754 && (i.index_reg
8755 || (i.base_reg->reg_num
8756 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8757 || (i.index_reg
8758 && !i.index_reg->reg_type.bitfield.regxmm
8759 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8760 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8761 && ((addr_mode == CODE_64BIT
8762 ? !(i.index_reg->reg_type.bitfield.reg64
8763 || i.index_reg->reg_num == RegRiz)
8764 : !(i.index_reg->reg_type.bitfield.reg32
8765 || i.index_reg->reg_num == RegEiz))
8766 || !i.index_reg->reg_type.bitfield.baseindex)))
8767 goto bad_address;
8178be5b
JB		 8768
8769 /* bndmk, bndldx, and bndstx have special restrictions. */
8770 if (current_templates->start->base_opcode == 0xf30f1b
8771 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8772 {
8773 /* They cannot use RIP-relative addressing. */
8774 if (i.base_reg && i.base_reg->reg_num == RegRip)
8775 {
8776 as_bad (_("`%s' cannot be used here"), operand_string);
8777 return 0;
8778 }
8779
8780 /* bndldx and bndstx ignore their scale factor. */
8781 if (current_templates->start->base_opcode != 0xf30f1b
8782 && i.log2_scale_factor)
8783 as_warn (_("register scaling is being ignored here"));
8784 }
be05d201
L		 8785 }
8786 else
3e73aa7c 8787 {
be05d201 8788 /* 16-bit checks. */
3e73aa7c 8789 if ((i.base_reg
40fb9820
L		 8790 && (!i.base_reg->reg_type.bitfield.reg16
8791 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8792 || (i.index_reg
40fb9820
L		 8793 && (!i.index_reg->reg_type.bitfield.reg16
8794 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8795 || !(i.base_reg
8796 && i.base_reg->reg_num < 6
8797 && i.index_reg->reg_num >= 6
8798 && i.log2_scale_factor == 0))))
be05d201 8799 goto bad_address;
3e73aa7c
JH		 8800 }
8801 }
be05d201 8802 return 1;
24eab124 8803}
252b5132 8804
43234a1e
L		 8805/* Handle vector immediates. */
8806
8807static int
8808RC_SAE_immediate (const char *imm_start)
8809{
8810 unsigned int match_found, j;
8811 const char *pstr = imm_start;
8812 expressionS *exp;
8813
8814 if (*pstr != '{')
8815 return 0;
8816
8817 pstr++;
8818 match_found = 0;
8819 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8820 {
8821 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8822 {
8823 if (!i.rounding)
8824 {
8825 rc_op.type = RC_NamesTable[j].type;
8826 rc_op.operand = this_operand;
8827 i.rounding = &rc_op;
8828 }
8829 else
8830 {
8831 as_bad (_("duplicated `%s'"), imm_start);
8832 return 0;
8833 }
8834 pstr += RC_NamesTable[j].len;
8835 match_found = 1;
8836 break;
8837 }
8838 }
8839 if (!match_found)
8840 return 0;
8841
8842 if (*pstr++ != '}')
8843 {
8844 as_bad (_("Missing '}': '%s'"), imm_start);
8845 return 0;
8846 }
8847 /* RC/SAE immediate string should contain nothing more. */;
8848 if (*pstr != 0)
8849 {
8850 as_bad (_("Junk after '}': '%s'"), imm_start);
8851 return 0;
8852 }
8853
8854 exp = &im_expressions[i.imm_operands++];
8855 i.op[this_operand].imms = exp;
8856
8857 exp->X_op = O_constant;
8858 exp->X_add_number = 0;
8859 exp->X_add_symbol = (symbolS *) 0;
8860 exp->X_op_symbol = (symbolS *) 0;
8861
8862 i.types[this_operand].bitfield.imm8 = 1;
8863 return 1;
8864}
8865
8325cc63
JB		 8866/* Only string instructions can have a second memory operand, so
8867 reduce current_templates to just those if it contains any. */
8868static int
8869maybe_adjust_templates (void)
8870{
8871 const insn_template *t;
8872
8873 gas_assert (i.mem_operands == 1);
8874
8875 for (t = current_templates->start; t < current_templates->end; ++t)
8876 if (t->opcode_modifier.isstring)
8877 break;
8878
8879 if (t < current_templates->end)
8880 {
8881 static templates aux_templates;
8882 bfd_boolean recheck;
8883
8884 aux_templates.start = t;
8885 for (; t < current_templates->end; ++t)
8886 if (!t->opcode_modifier.isstring)
8887 break;
8888 aux_templates.end = t;
8889
8890 /* Determine whether to re-check the first memory operand. */
8891 recheck = (aux_templates.start != current_templates->start
8892 || t != current_templates->end);
8893
8894 current_templates = &aux_templates;
8895
8896 if (recheck)
8897 {
8898 i.mem_operands = 0;
8899 if (i.memop1_string != NULL
8900 && i386_index_check (i.memop1_string) == 0)
8901 return 0;
8902 i.mem_operands = 1;
8903 }
8904 }
8905
8906 return 1;
8907}
8908
fc0763e6 8909/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8910 on error. */
252b5132 8911
252b5132 8912static int
a7619375 8913i386_att_operand (char *operand_string)
252b5132 8914{
af6bdddf
AM		 8915 const reg_entry *r;
8916 char *end_op;
24eab124 8917 char *op_string = operand_string;
252b5132 8918
24eab124 8919 if (is_space_char (*op_string))
252b5132
RH		 8920 ++op_string;
8921
24eab124 8922 /* We check for an absolute prefix (differentiating,
47926f60 8923 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8924 if (*op_string == ABSOLUTE_PREFIX)
8925 {
8926 ++op_string;
8927 if (is_space_char (*op_string))
8928 ++op_string;
40fb9820 8929 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8930 }
252b5132 8931
47926f60 8932 /* Check if operand is a register. */
4d1bb795 8933 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8934 {
40fb9820
L		 8935 i386_operand_type temp;
8936
24eab124
AM		 8937 /* Check for a segment override by searching for ':' after a
8938 segment register. */
8939 op_string = end_op;
8940 if (is_space_char (*op_string))
8941 ++op_string;
40fb9820
L		 8942 if (*op_string == ':'
8943 && (r->reg_type.bitfield.sreg2
8944 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8945 {
8946 switch (r->reg_num)
8947 {
8948 case 0:
8949 i.seg[i.mem_operands] = &es;
8950 break;
8951 case 1:
8952 i.seg[i.mem_operands] = &cs;
8953 break;
8954 case 2:
8955 i.seg[i.mem_operands] = &ss;
8956 break;
8957 case 3:
8958 i.seg[i.mem_operands] = &ds;
8959 break;
8960 case 4:
8961 i.seg[i.mem_operands] = &fs;
8962 break;
8963 case 5:
8964 i.seg[i.mem_operands] = &gs;
8965 break;
8966 }
252b5132 8967
24eab124 8968 /* Skip the ':' and whitespace. */
252b5132
RH		 8969 ++op_string;
8970 if (is_space_char (*op_string))
24eab124 8971 ++op_string;
252b5132 8972
24eab124
AM		 8973 if (!is_digit_char (*op_string)
8974 && !is_identifier_char (*op_string)
8975 && *op_string != '('
8976 && *op_string != ABSOLUTE_PREFIX)
8977 {
8978 as_bad (_("bad memory operand `%s'"), op_string);
8979 return 0;
8980 }
47926f60 8981 /* Handle case of %es:*foo. */
24eab124
AM		 8982 if (*op_string == ABSOLUTE_PREFIX)
8983 {
8984 ++op_string;
8985 if (is_space_char (*op_string))
8986 ++op_string;
40fb9820 8987 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8988 }
8989 goto do_memory_reference;
8990 }
43234a1e
L		 8991
8992 /* Handle vector operations. */
8993 if (*op_string == '{')
8994 {
8995 op_string = check_VecOperations (op_string, NULL);
8996 if (op_string == NULL)
8997 return 0;
8998 }
8999
24eab124
AM		 9000 if (*op_string)
9001 {
d0b47220 9002 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9003 return 0;
9004 }
40fb9820
L		 9005 temp = r->reg_type;
9006 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9007 i.types[this_operand] = operand_type_or (i.types[this_operand],
9008 temp);
7d5e4556 9009 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9010 i.op[this_operand].regs = r;
24eab124
AM		 9011 i.reg_operands++;
9012 }
af6bdddf
AM		 9013 else if (*op_string == REGISTER_PREFIX)
9014 {
9015 as_bad (_("bad register name `%s'"), op_string);
9016 return 0;
9017 }
24eab124 9018 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9019 {
24eab124 9020 ++op_string;
40fb9820 9021 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9022 {
d0b47220 9023 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9024 return 0;
9025 }
9026 if (!i386_immediate (op_string))
9027 return 0;
9028 }
43234a1e
L		 9029 else if (RC_SAE_immediate (operand_string))
9030 {
9031 /* If it is a RC or SAE immediate, do nothing. */
9032 ;
9033 }
24eab124
AM		 9034 else if (is_digit_char (*op_string)
9035 || is_identifier_char (*op_string)
d02603dc 9036 || *op_string == '"'
e5cb08ac 9037 || *op_string == '(')
24eab124 9038 {
47926f60 9039 /* This is a memory reference of some sort. */
af6bdddf 9040 char *base_string;
252b5132 9041
47926f60 9042 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9043 char *displacement_string_start;
9044 char *displacement_string_end;
43234a1e 9045 char *vop_start;
252b5132 9046
24eab124 9047 do_memory_reference:
8325cc63
JB		 9048 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9049 return 0;
24eab124 9050 if ((i.mem_operands == 1
40fb9820 9051 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9052 || i.mem_operands == 2)
9053 {
9054 as_bad (_("too many memory references for `%s'"),
9055 current_templates->start->name);
9056 return 0;
9057 }
252b5132 9058
24eab124
AM		 9059 /* Check for base index form. We detect the base index form by
9060 looking for an ')' at the end of the operand, searching
9061 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9062 after the '('. */
af6bdddf 9063 base_string = op_string + strlen (op_string);
c3332e24 9064
43234a1e
L		 9065 /* Handle vector operations. */
9066 vop_start = strchr (op_string, '{');
9067 if (vop_start && vop_start < base_string)
9068 {
9069 if (check_VecOperations (vop_start, base_string) == NULL)
9070 return 0;
9071 base_string = vop_start;
9072 }
9073
af6bdddf
AM		 9074 --base_string;
9075 if (is_space_char (*base_string))
9076 --base_string;
252b5132 9077
47926f60 9078 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9079 displacement_string_start = op_string;
9080 displacement_string_end = base_string + 1;
252b5132 9081
24eab124
AM		 9082 if (*base_string == ')')
9083 {
af6bdddf 9084 char *temp_string;
24eab124
AM		 9085 unsigned int parens_balanced = 1;
9086 /* We've already checked that the number of left & right ()'s are
47926f60 9087 equal, so this loop will not be infinite. */
24eab124
AM		 9088 do
9089 {
9090 base_string--;
9091 if (*base_string == ')')
9092 parens_balanced++;
9093 if (*base_string == '(')
9094 parens_balanced--;
9095 }
9096 while (parens_balanced);
c3332e24 9097
af6bdddf 9098 temp_string = base_string;
c3332e24 9099
24eab124 9100 /* Skip past '(' and whitespace. */
252b5132
RH		 9101 ++base_string;
9102 if (is_space_char (*base_string))
24eab124 9103 ++base_string;
252b5132 9104
af6bdddf 9105 if (*base_string == ','
4eed87de
AM		 9106 || ((i.base_reg = parse_register (base_string, &end_op))
9107 != NULL))
252b5132 9108 {
af6bdddf 9109 displacement_string_end = temp_string;
252b5132 9110
40fb9820 9111 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9112
af6bdddf 9113 if (i.base_reg)
24eab124 9114 {
24eab124
AM		 9115 base_string = end_op;
9116 if (is_space_char (*base_string))
9117 ++base_string;
af6bdddf
AM		 9118 }
9119
9120 /* There may be an index reg or scale factor here. */
9121 if (*base_string == ',')
9122 {
9123 ++base_string;
9124 if (is_space_char (*base_string))
9125 ++base_string;
9126
4eed87de
AM		 9127 if ((i.index_reg = parse_register (base_string, &end_op))
9128 != NULL)
24eab124 9129 {
af6bdddf 9130 base_string = end_op;
24eab124
AM		 9131 if (is_space_char (*base_string))
9132 ++base_string;
af6bdddf
AM		 9133 if (*base_string == ',')
9134 {
9135 ++base_string;
9136 if (is_space_char (*base_string))
9137 ++base_string;
9138 }
e5cb08ac 9139 else if (*base_string != ')')
af6bdddf 9140 {
4eed87de
AM		 9141 as_bad (_("expecting `,' or `)' "
9142 "after index register in `%s'"),
af6bdddf
AM		 9143 operand_string);
9144 return 0;
9145 }
24eab124 9146 }
af6bdddf 9147 else if (*base_string == REGISTER_PREFIX)
24eab124 9148 {
f76bf5e0
L		 9149 end_op = strchr (base_string, ',');
9150 if (end_op)
9151 *end_op = '\0';
af6bdddf 9152 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9153 return 0;
9154 }
252b5132 9155
47926f60 9156 /* Check for scale factor. */
551c1ca1 9157 if (*base_string != ')')
af6bdddf 9158 {
551c1ca1
AM		 9159 char *end_scale = i386_scale (base_string);
9160
9161 if (!end_scale)
af6bdddf 9162 return 0;
24eab124 9163
551c1ca1 9164 base_string = end_scale;
af6bdddf
AM		 9165 if (is_space_char (*base_string))
9166 ++base_string;
9167 if (*base_string != ')')
9168 {
4eed87de
AM		 9169 as_bad (_("expecting `)' "
9170 "after scale factor in `%s'"),
af6bdddf
AM		 9171 operand_string);
9172 return 0;
9173 }
9174 }
9175 else if (!i.index_reg)
24eab124 9176 {
4eed87de
AM		 9177 as_bad (_("expecting index register or scale factor "
9178 "after `,'; got '%c'"),
af6bdddf 9179 *base_string);
24eab124
AM		 9180 return 0;
9181 }
9182 }
af6bdddf 9183 else if (*base_string != ')')
24eab124 9184 {
4eed87de
AM		 9185 as_bad (_("expecting `,' or `)' "
9186 "after base register in `%s'"),
af6bdddf 9187 operand_string);
24eab124
AM		 9188 return 0;
9189 }
c3332e24 9190 }
af6bdddf 9191 else if (*base_string == REGISTER_PREFIX)
c3332e24 9192 {
f76bf5e0
L		 9193 end_op = strchr (base_string, ',');
9194 if (end_op)
9195 *end_op = '\0';
af6bdddf 9196 as_bad (_("bad register name `%s'"), base_string);
24eab124 9197 return 0;
c3332e24 9198 }
24eab124
AM		 9199 }
9200
9201 /* If there's an expression beginning the operand, parse it,
9202 assuming displacement_string_start and
9203 displacement_string_end are meaningful. */
9204 if (displacement_string_start != displacement_string_end)
9205 {
9206 if (!i386_displacement (displacement_string_start,
9207 displacement_string_end))
9208 return 0;
9209 }
9210
9211 /* Special case for (%dx) while doing input/output op. */
9212 if (i.base_reg
0dfbf9d7
L		 9213 && operand_type_equal (&i.base_reg->reg_type,
9214 &reg16_inoutportreg)
24eab124
AM		 9215 && i.index_reg == 0
9216 && i.log2_scale_factor == 0
9217 && i.seg[i.mem_operands] == 0
40fb9820 9218 && !operand_type_check (i.types[this_operand], disp))
24eab124 9219 {
65da13b5 9220 i.types[this_operand] = inoutportreg;
24eab124
AM		 9221 return 1;
9222 }
9223
eecb386c
AM		 9224 if (i386_index_check (operand_string) == 0)
9225 return 0;
5c07affc 9226 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9227 if (i.mem_operands == 0)
9228 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9229 i.mem_operands++;
9230 }
9231 else
ce8a8b2f
AM		 9232 {
9233 /* It's not a memory operand; argh! */
24eab124
AM		 9234 as_bad (_("invalid char %s beginning operand %d `%s'"),
9235 output_invalid (*op_string),
9236 this_operand + 1,
9237 op_string);
9238 return 0;
9239 }
47926f60 9240 return 1; /* Normal return. */
252b5132
RH		 9241}
9242\f
fa94de6b
RM		 9243/* Calculate the maximum variable size (i.e., excluding fr_fix)
9244 that an rs_machine_dependent frag may reach. */
9245
9246unsigned int
9247i386_frag_max_var (fragS *frag)
9248{
9249 /* The only relaxable frags are for jumps.
9250 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9251 gas_assert (frag->fr_type == rs_machine_dependent);
9252 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9253}
9254
b084df0b
L		 9255#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9256static int
8dcea932 9257elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9258{
9259 /* STT_GNU_IFUNC symbol must go through PLT. */
9260 if ((symbol_get_bfdsym (fr_symbol)->flags
9261 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9262 return 0;
9263
9264 if (!S_IS_EXTERNAL (fr_symbol))
9265 /* Symbol may be weak or local. */
9266 return !S_IS_WEAK (fr_symbol);
9267
8dcea932
L		 9268 /* Global symbols with non-default visibility can't be preempted. */
9269 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9270 return 1;
9271
9272 if (fr_var != NO_RELOC)
9273 switch ((enum bfd_reloc_code_real) fr_var)
9274 {
9275 case BFD_RELOC_386_PLT32:
9276 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9277 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9278 return 0;
9279 default:
9280 abort ();
9281 }
9282
b084df0b
L		 9283 /* Global symbols with default visibility in a shared library may be
9284 preempted by another definition. */
8dcea932 9285 return !shared;
b084df0b
L		 9286}
9287#endif
9288
ee7fcc42
AM		 9289/* md_estimate_size_before_relax()
9290
9291 Called just before relax() for rs_machine_dependent frags. The x86
9292 assembler uses these frags to handle variable size jump
9293 instructions.
9294
9295 Any symbol that is now undefined will not become defined.
9296 Return the correct fr_subtype in the frag.
9297 Return the initial "guess for variable size of frag" to caller.
9298 The guess is actually the growth beyond the fixed part. Whatever
9299 we do to grow the fixed or variable part contributes to our
9300 returned value. */
9301
252b5132 9302int
7016a5d5 9303md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9304{
252b5132 9305 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9306 check for un-relaxable symbols. On an ELF system, we can't relax
9307 an externally visible symbol, because it may be overridden by a
9308 shared library. */
9309 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9310#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9311 || (IS_ELF
8dcea932
L		 9312 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9313 fragP->fr_var))
fbeb56a4
DK		 9314#endif
9315#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9316 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9317 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9318#endif
9319 )
252b5132 9320 {
b98ef147
AM		 9321 /* Symbol is undefined in this segment, or we need to keep a
9322 reloc so that weak symbols can be overridden. */
9323 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9324 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9325 unsigned char *opcode;
9326 int old_fr_fix;
f6af82bd 9327
ee7fcc42 9328 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9329 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9330 else if (size == 2)
f6af82bd
AM		 9331 reloc_type = BFD_RELOC_16_PCREL;
9332 else
9333 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9334
ee7fcc42
AM		 9335 old_fr_fix = fragP->fr_fix;
9336 opcode = (unsigned char *) fragP->fr_opcode;
9337
fddf5b5b 9338 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9339 {
fddf5b5b
AM		 9340 case UNCOND_JUMP:
9341 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9342 opcode[0] = 0xe9;
252b5132 9343 fragP->fr_fix += size;
062cd5e7
AS		 9344 fix_new (fragP, old_fr_fix, size,
9345 fragP->fr_symbol,
9346 fragP->fr_offset, 1,
9347 reloc_type);
252b5132
RH		 9348 break;
9349
fddf5b5b 9350 case COND_JUMP86:
412167cb
AM		 9351 if (size == 2
9352 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9353 {
9354 /* Negate the condition, and branch past an
9355 unconditional jump. */
9356 opcode[0] ^= 1;
9357 opcode[1] = 3;
9358 /* Insert an unconditional jump. */
9359 opcode[2] = 0xe9;
9360 /* We added two extra opcode bytes, and have a two byte
9361 offset. */
9362 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9363 fix_new (fragP, old_fr_fix + 2, 2,
9364 fragP->fr_symbol,
9365 fragP->fr_offset, 1,
9366 reloc_type);
fddf5b5b
AM		 9367 break;
9368 }
9369 /* Fall through. */
9370
9371 case COND_JUMP:
412167cb
AM		 9372 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9373 {
3e02c1cc
AM		 9374 fixS *fixP;
9375
412167cb 9376 fragP->fr_fix += 1;
3e02c1cc
AM		 9377 fixP = fix_new (fragP, old_fr_fix, 1,
9378 fragP->fr_symbol,
9379 fragP->fr_offset, 1,
9380 BFD_RELOC_8_PCREL);
9381 fixP->fx_signed = 1;
412167cb
AM		 9382 break;
9383 }
93c2a809 9384
24eab124 9385 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9386 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9387 opcode[1] = opcode[0] + 0x10;
f6af82bd 9388 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9389 /* We've added an opcode byte. */
9390 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9391 fix_new (fragP, old_fr_fix + 1, size,
9392 fragP->fr_symbol,
9393 fragP->fr_offset, 1,
9394 reloc_type);
252b5132 9395 break;
fddf5b5b
AM		 9396
9397 default:
9398 BAD_CASE (fragP->fr_subtype);
9399 break;
252b5132
RH		 9400 }
9401 frag_wane (fragP);
ee7fcc42 9402 return fragP->fr_fix - old_fr_fix;
252b5132 9403 }
93c2a809 9404
93c2a809
AM		 9405 /* Guess size depending on current relax state. Initially the relax
9406 state will correspond to a short jump and we return 1, because
9407 the variable part of the frag (the branch offset) is one byte
9408 long. However, we can relax a section more than once and in that
9409 case we must either set fr_subtype back to the unrelaxed state,
9410 or return the value for the appropriate branch. */
9411 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9412}
9413
47926f60
KH		 9414/* Called after relax() is finished.
9415
9416 In: Address of frag.
9417 fr_type == rs_machine_dependent.
9418 fr_subtype is what the address relaxed to.
9419
9420 Out: Any fixSs and constants are set up.
9421 Caller will turn frag into a ".space 0". */
9422
252b5132 9423void
7016a5d5
TG		 9424md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9425 fragS *fragP)
252b5132 9426{
29b0f896 9427 unsigned char *opcode;
252b5132 9428 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9429 offsetT target_address;
9430 offsetT opcode_address;
252b5132 9431 unsigned int extension = 0;
847f7ad4 9432 offsetT displacement_from_opcode_start;
252b5132
RH		 9433
9434 opcode = (unsigned char *) fragP->fr_opcode;
9435
47926f60 9436 /* Address we want to reach in file space. */
252b5132 9437 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9438
47926f60 9439 /* Address opcode resides at in file space. */
252b5132
RH		 9440 opcode_address = fragP->fr_address + fragP->fr_fix;
9441
47926f60 9442 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9443 displacement_from_opcode_start = target_address - opcode_address;
9444
fddf5b5b 9445 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9446 {
47926f60
KH		 9447 /* Don't have to change opcode. */
9448 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9449 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9450 }
9451 else
9452 {
9453 if (no_cond_jump_promotion
9454 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9455 as_warn_where (fragP->fr_file, fragP->fr_line,
9456 _("long jump required"));
252b5132 9457
fddf5b5b
AM		 9458 switch (fragP->fr_subtype)
9459 {
9460 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9461 extension = 4; /* 1 opcode + 4 displacement */
9462 opcode[0] = 0xe9;
9463 where_to_put_displacement = &opcode[1];
9464 break;
252b5132 9465
fddf5b5b
AM		 9466 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9467 extension = 2; /* 1 opcode + 2 displacement */
9468 opcode[0] = 0xe9;
9469 where_to_put_displacement = &opcode[1];
9470 break;
252b5132 9471
fddf5b5b
AM		 9472 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9473 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9474 extension = 5; /* 2 opcode + 4 displacement */
9475 opcode[1] = opcode[0] + 0x10;
9476 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9477 where_to_put_displacement = &opcode[2];
9478 break;
252b5132 9479
fddf5b5b
AM		 9480 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9481 extension = 3; /* 2 opcode + 2 displacement */
9482 opcode[1] = opcode[0] + 0x10;
9483 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9484 where_to_put_displacement = &opcode[2];
9485 break;
252b5132 9486
fddf5b5b
AM		 9487 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9488 extension = 4;
9489 opcode[0] ^= 1;
9490 opcode[1] = 3;
9491 opcode[2] = 0xe9;
9492 where_to_put_displacement = &opcode[3];
9493 break;
9494
9495 default:
9496 BAD_CASE (fragP->fr_subtype);
9497 break;
9498 }
252b5132 9499 }
fddf5b5b 9500
7b81dfbb
AJ		 9501 /* If size if less then four we are sure that the operand fits,
9502 but if it's 4, then it could be that the displacement is larger
9503 then -/+ 2GB. */
9504 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9505 && object_64bit
9506 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9507 + ((addressT) 1 << 31))
9508 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9509 {
9510 as_bad_where (fragP->fr_file, fragP->fr_line,
9511 _("jump target out of range"));
9512 /* Make us emit 0. */
9513 displacement_from_opcode_start = extension;
9514 }
47926f60 9515 /* Now put displacement after opcode. */
252b5132
RH		 9516 md_number_to_chars ((char *) where_to_put_displacement,
9517 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9518 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9519 fragP->fr_fix += extension;
9520}
9521\f
7016a5d5 9522/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9523 by our caller that we have all the info we need to fix it up.
9524
7016a5d5
TG		 9525 Parameter valP is the pointer to the value of the bits.
9526
252b5132
RH		 9527 On the 386, immediates, displacements, and data pointers are all in
9528 the same (little-endian) format, so we don't need to care about which
9529 we are handling. */
9530
94f592af 9531void
7016a5d5 9532md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9533{
94f592af 9534 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9535 valueT value = *valP;
252b5132 9536
f86103b7 9537#if !defined (TE_Mach)
93382f6d
AM		 9538 if (fixP->fx_pcrel)
9539 {
9540 switch (fixP->fx_r_type)
9541 {
5865bb77
ILT		 9542 default:
9543 break;
9544
d6ab8113
JB		 9545 case BFD_RELOC_64:
9546 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9547 break;
93382f6d 9548 case BFD_RELOC_32:
ae8887b5 9549 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9550 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9551 break;
9552 case BFD_RELOC_16:
9553 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9554 break;
9555 case BFD_RELOC_8:
9556 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9557 break;
9558 }
9559 }
252b5132 9560
a161fe53 9561 if (fixP->fx_addsy != NULL
31312f95 9562 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9563 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9564 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9565 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9566 && !use_rela_relocations)
252b5132 9567 {
31312f95
AM		 9568 /* This is a hack. There should be a better way to handle this.
9569 This covers for the fact that bfd_install_relocation will
9570 subtract the current location (for partial_inplace, PC relative
9571 relocations); see more below. */
252b5132 9572#ifndef OBJ_AOUT
718ddfc0 9573 if (IS_ELF
252b5132
RH		 9574#ifdef TE_PE
9575 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9576#endif
9577 )
9578 value += fixP->fx_where + fixP->fx_frag->fr_address;
9579#endif
9580#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9581 if (IS_ELF)
252b5132 9582 {
6539b54b 9583 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9584
6539b54b 9585 if ((sym_seg == seg
2f66722d 9586 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9587 && sym_seg != absolute_section))
af65af87 9588 && !generic_force_reloc (fixP))
2f66722d
AM		 9589 {
9590 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9591 bfd_install_relocation subtracts them out again. I think
9592 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9593 it. FIXME. */
9594 value += fixP->fx_where + fixP->fx_frag->fr_address;
9595 }
252b5132
RH		 9596 }
9597#endif
9598#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9599 /* For some reason, the PE format does not store a
9600 section address offset for a PC relative symbol. */
9601 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9602 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9603 value += md_pcrel_from (fixP);
9604#endif
9605 }
fbeb56a4 9606#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9607 if (fixP->fx_addsy != NULL
9608 && S_IS_WEAK (fixP->fx_addsy)
9609 /* PR 16858: Do not modify weak function references. */
9610 && ! fixP->fx_pcrel)
fbeb56a4 9611 {
296a8689
NC		 9612#if !defined (TE_PEP)
9613 /* For x86 PE weak function symbols are neither PC-relative
9614 nor do they set S_IS_FUNCTION. So the only reliable way
9615 to detect them is to check the flags of their containing
9616 section. */
9617 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9618 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9619 ;
9620 else
9621#endif
fbeb56a4
DK		 9622 value -= S_GET_VALUE (fixP->fx_addsy);
9623 }
9624#endif
252b5132
RH		 9625
9626 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9627 and we must not disappoint it. */
252b5132 9628#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9629 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9630 switch (fixP->fx_r_type)
9631 {
9632 case BFD_RELOC_386_PLT32:
3e73aa7c 9633 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9634 /* Make the jump instruction point to the address of the operand. At
9635 runtime we merely add the offset to the actual PLT entry. */
9636 value = -4;
9637 break;
31312f95 9638
13ae64f3
JJ		 9639 case BFD_RELOC_386_TLS_GD:
9640 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9641 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9642 case BFD_RELOC_386_TLS_IE:
9643 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9644 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9645 case BFD_RELOC_X86_64_TLSGD:
9646 case BFD_RELOC_X86_64_TLSLD:
9647 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9648 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9649 value = 0; /* Fully resolved at runtime. No addend. */
9650 /* Fallthrough */
9651 case BFD_RELOC_386_TLS_LE:
9652 case BFD_RELOC_386_TLS_LDO_32:
9653 case BFD_RELOC_386_TLS_LE_32:
9654 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9655 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9656 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9657 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9658 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9659 break;
9660
67a4f2b7
AO		 9661 case BFD_RELOC_386_TLS_DESC_CALL:
9662 case BFD_RELOC_X86_64_TLSDESC_CALL:
9663 value = 0; /* Fully resolved at runtime. No addend. */
9664 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9665 fixP->fx_done = 0;
9666 return;
9667
47926f60
KH		 9668 case BFD_RELOC_VTABLE_INHERIT:
9669 case BFD_RELOC_VTABLE_ENTRY:
9670 fixP->fx_done = 0;
94f592af 9671 return;
47926f60
KH		 9672
9673 default:
9674 break;
9675 }
9676#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9677 *valP = value;
f86103b7 9678#endif /* !defined (TE_Mach) */
3e73aa7c 9679
3e73aa7c 9680 /* Are we finished with this relocation now? */
c6682705 9681 if (fixP->fx_addsy == NULL)
3e73aa7c 9682 fixP->fx_done = 1;
fbeb56a4
DK		 9683#if defined (OBJ_COFF) && defined (TE_PE)
9684 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9685 {
9686 fixP->fx_done = 0;
9687 /* Remember value for tc_gen_reloc. */
9688 fixP->fx_addnumber = value;
9689 /* Clear out the frag for now. */
9690 value = 0;
9691 }
9692#endif
3e73aa7c
JH		 9693 else if (use_rela_relocations)
9694 {
9695 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9696 /* Remember value for tc_gen_reloc. */
9697 fixP->fx_addnumber = value;
3e73aa7c
JH		 9698 value = 0;
9699 }
f86103b7 9700
94f592af 9701 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9702}
252b5132 9703\f
6d4af3c2 9704const char *
499ac353 9705md_atof (int type, char *litP, int *sizeP)
252b5132 9706{
499ac353
NC		 9707 /* This outputs the LITTLENUMs in REVERSE order;
9708 in accord with the bigendian 386. */
9709 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9710}
9711\f
2d545b82 9712static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9713
252b5132 9714static char *
e3bb37b5 9715output_invalid (int c)
252b5132 9716{
3882b010 9717 if (ISPRINT (c))
f9f21a03
L		 9718 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9719 "'%c'", c);
252b5132 9720 else
f9f21a03 9721 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9722 "(0x%x)", (unsigned char) c);
252b5132
RH		 9723 return output_invalid_buf;
9724}
9725
af6bdddf 9726/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9727
9728static const reg_entry *
4d1bb795 9729parse_real_register (char *reg_string, char **end_op)
252b5132 9730{
af6bdddf
AM		 9731 char *s = reg_string;
9732 char *p;
252b5132
RH		 9733 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9734 const reg_entry *r;
9735
9736 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9737 if (*s == REGISTER_PREFIX)
9738 ++s;
9739
9740 if (is_space_char (*s))
9741 ++s;
9742
9743 p = reg_name_given;
af6bdddf 9744 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9745 {
9746 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9747 return (const reg_entry *) NULL;
9748 s++;
252b5132
RH		 9749 }
9750
6588847e
DN		 9751 /* For naked regs, make sure that we are not dealing with an identifier.
9752 This prevents confusing an identifier like `eax_var' with register
9753 `eax'. */
9754 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9755 return (const reg_entry *) NULL;
9756
af6bdddf 9757 *end_op = s;
252b5132
RH		 9758
9759 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9760
5f47d35b 9761 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9762 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9763 {
5f47d35b
AM		 9764 if (is_space_char (*s))
9765 ++s;
9766 if (*s == '(')
9767 {
af6bdddf 9768 ++s;
5f47d35b
AM		 9769 if (is_space_char (*s))
9770 ++s;
9771 if (*s >= '0' && *s <= '7')
9772 {
db557034 9773 int fpr = *s - '0';
af6bdddf 9774 ++s;
5f47d35b
AM		 9775 if (is_space_char (*s))
9776 ++s;
9777 if (*s == ')')
9778 {
9779 *end_op = s + 1;
1e9cc1c2 9780 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9781 know (r);
9782 return r + fpr;
5f47d35b 9783 }
5f47d35b 9784 }
47926f60 9785 /* We have "%st(" then garbage. */
5f47d35b
AM		 9786 return (const reg_entry *) NULL;
9787 }
9788 }
9789
a60de03c
JB		 9790 if (r == NULL || allow_pseudo_reg)
9791 return r;
9792
0dfbf9d7 9793 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9794 return (const reg_entry *) NULL;
9795
192dc9c6
JB		 9796 if ((r->reg_type.bitfield.reg32
9797 || r->reg_type.bitfield.sreg3
9798 || r->reg_type.bitfield.control
9799 || r->reg_type.bitfield.debug
9800 || r->reg_type.bitfield.test)
9801 && !cpu_arch_flags.bitfield.cpui386)
9802 return (const reg_entry *) NULL;
9803
309d3373
JB		 9804 if (r->reg_type.bitfield.floatreg
9805 && !cpu_arch_flags.bitfield.cpu8087
9806 && !cpu_arch_flags.bitfield.cpu287
9807 && !cpu_arch_flags.bitfield.cpu387)
9808 return (const reg_entry *) NULL;
9809
1848e567 9810 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9811 return (const reg_entry *) NULL;
9812
1848e567 9813 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9814 return (const reg_entry *) NULL;
9815
1848e567 9816 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9817 return (const reg_entry *) NULL;
9818
1848e567
L		 9819 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9820 return (const reg_entry *) NULL;
9821
9822 if (r->reg_type.bitfield.regmask
9823 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9824 return (const reg_entry *) NULL;
9825
db51cc60 9826 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9827 if (!allow_index_reg
db51cc60
L		 9828 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9829 return (const reg_entry *) NULL;
9830
43234a1e
L		 9831 /* Upper 16 vector register is only available with VREX in 64bit
9832 mode. */
9833 if ((r->reg_flags & RegVRex))
9834 {
86fa6981
L		 9835 if (i.vec_encoding == vex_encoding_default)
9836 i.vec_encoding = vex_encoding_evex;
9837
43234a1e 9838 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9839 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9840 || flag_code != CODE_64BIT)
9841 return (const reg_entry *) NULL;
43234a1e
L		 9842 }
9843
a60de03c
JB		 9844 if (((r->reg_flags & (RegRex64 | RegRex))
9845 || r->reg_type.bitfield.reg64)
40fb9820 9846 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9847 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9848 && flag_code != CODE_64BIT)
20f0a1fc 9849 return (const reg_entry *) NULL;
1ae00879 9850
b7240065
JB		 9851 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9852 return (const reg_entry *) NULL;
9853
252b5132
RH		 9854 return r;
9855}
4d1bb795
JB		 9856
9857/* REG_STRING starts *before* REGISTER_PREFIX. */
9858
9859static const reg_entry *
9860parse_register (char *reg_string, char **end_op)
9861{
9862 const reg_entry *r;
9863
9864 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9865 r = parse_real_register (reg_string, end_op);
9866 else
9867 r = NULL;
9868 if (!r)
9869 {
9870 char *save = input_line_pointer;
9871 char c;
9872 symbolS *symbolP;
9873
9874 input_line_pointer = reg_string;
d02603dc 9875 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9876 symbolP = symbol_find (reg_string);
9877 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9878 {
9879 const expressionS *e = symbol_get_value_expression (symbolP);
9880
0398aac5 9881 know (e->X_op == O_register);
4eed87de 9882 know (e->X_add_number >= 0
c3fe08fa 9883 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9884 r = i386_regtab + e->X_add_number;
d3bb6b49 9885 if ((r->reg_flags & RegVRex))
86fa6981 9886 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9887 *end_op = input_line_pointer;
9888 }
9889 *input_line_pointer = c;
9890 input_line_pointer = save;
9891 }
9892 return r;
9893}
9894
9895int
9896i386_parse_name (char *name, expressionS *e, char *nextcharP)
9897{
9898 const reg_entry *r;
9899 char *end = input_line_pointer;
9900
9901 *end = *nextcharP;
9902 r = parse_register (name, &input_line_pointer);
9903 if (r && end <= input_line_pointer)
9904 {
9905 *nextcharP = *input_line_pointer;
9906 *input_line_pointer = 0;
9907 e->X_op = O_register;
9908 e->X_add_number = r - i386_regtab;
9909 return 1;
9910 }
9911 input_line_pointer = end;
9912 *end = 0;
ee86248c 9913 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9914}
9915
9916void
9917md_operand (expressionS *e)
9918{
ee86248c
JB		 9919 char *end;
9920 const reg_entry *r;
4d1bb795 9921
ee86248c
JB		 9922 switch (*input_line_pointer)
9923 {
9924 case REGISTER_PREFIX:
9925 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9926 if (r)
9927 {
9928 e->X_op = O_register;
9929 e->X_add_number = r - i386_regtab;
9930 input_line_pointer = end;
9931 }
ee86248c
JB		 9932 break;
9933
9934 case '[':
9c2799c2 9935 gas_assert (intel_syntax);
ee86248c
JB		 9936 end = input_line_pointer++;
9937 expression (e);
9938 if (*input_line_pointer == ']')
9939 {
9940 ++input_line_pointer;
9941 e->X_op_symbol = make_expr_symbol (e);
9942 e->X_add_symbol = NULL;
9943 e->X_add_number = 0;
9944 e->X_op = O_index;
9945 }
9946 else
9947 {
9948 e->X_op = O_absent;
9949 input_line_pointer = end;
9950 }
9951 break;
4d1bb795
JB		 9952 }
9953}
9954
252b5132 9955\f
4cc782b5 9956#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9957const char *md_shortopts = "kVQ:sqn";
252b5132 9958#else
12b55ccc 9959const char *md_shortopts = "qn";
252b5132 9960#endif
6e0b89ee 9961
3e73aa7c 9962#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9963#define OPTION_64 (OPTION_MD_BASE + 1)
9964#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9965#define OPTION_MARCH (OPTION_MD_BASE + 3)
9966#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9967#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9968#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9969#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9970#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9971#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9972#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9973#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9974#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9975#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9976#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9977#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9978#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9979#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9980#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9981#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9982#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9983#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9984#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9985#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9986#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9987#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9988
99ad8390
NC		 9989struct option md_longopts[] =
9990{
3e73aa7c 9991 {"32", no_argument, NULL, OPTION_32},
321098a5 9992#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9993 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9994 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9995#endif
9996#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9997 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9998 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9999#endif
b3b91714 10000 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10001 {"march", required_argument, NULL, OPTION_MARCH},
10002 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10003 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10004 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10005 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10006 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10007 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 10008 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10009 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10010 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10011 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10012 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10013 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10014 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10015# if defined (TE_PE) || defined (TE_PEP)
10016 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10017#endif
d1982f93 10018 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10019 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10020 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10021 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10022 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10023 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10024 {NULL, no_argument, NULL, 0}
10025};
10026size_t md_longopts_size = sizeof (md_longopts);
10027
10028int
17b9d67d 10029md_parse_option (int c, const char *arg)
252b5132 10030{
91d6fa6a 10031 unsigned int j;
293f5f65 10032 char *arch, *next, *saved;
9103f4f4 10033
252b5132
RH		 10034 switch (c)
10035 {
12b55ccc
L		 10036 case 'n':
10037 optimize_align_code = 0;
10038 break;
10039
a38cf1db
AM		 10040 case 'q':
10041 quiet_warnings = 1;
252b5132
RH		 10042 break;
10043
10044#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10045 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10046 should be emitted or not. FIXME: Not implemented. */
10047 case 'Q':
252b5132
RH		 10048 break;
10049
10050 /* -V: SVR4 argument to print version ID. */
10051 case 'V':
10052 print_version_id ();
10053 break;
10054
a38cf1db
AM		 10055 /* -k: Ignore for FreeBSD compatibility. */
10056 case 'k':
252b5132 10057 break;
4cc782b5
ILT		 10058
10059 case 's':
10060 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10061 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10062 break;
8dcea932
L		 10063
10064 case OPTION_MSHARED:
10065 shared = 1;
10066 break;
99ad8390 10067#endif
321098a5 10068#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10069 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10070 case OPTION_64:
10071 {
10072 const char **list, **l;
10073
3e73aa7c
JH		 10074 list = bfd_target_list ();
10075 for (l = list; *l != NULL; l++)
8620418b 10076 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10077 || strcmp (*l, "coff-x86-64") == 0
10078 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10079 || strcmp (*l, "pei-x86-64") == 0
10080 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10081 {
10082 default_arch = "x86_64";
10083 break;
10084 }
3e73aa7c 10085 if (*l == NULL)
2b5d6a91 10086 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10087 free (list);
10088 }
10089 break;
10090#endif
252b5132 10091
351f65ca 10092#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10093 case OPTION_X32:
351f65ca
L		 10094 if (IS_ELF)
10095 {
10096 const char **list, **l;
10097
10098 list = bfd_target_list ();
10099 for (l = list; *l != NULL; l++)
10100 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10101 {
10102 default_arch = "x86_64:32";
10103 break;
10104 }
10105 if (*l == NULL)
2b5d6a91 10106 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10107 free (list);
10108 }
10109 else
10110 as_fatal (_("32bit x86_64 is only supported for ELF"));
10111 break;
10112#endif
10113
6e0b89ee
AM		 10114 case OPTION_32:
10115 default_arch = "i386";
10116 break;
10117
b3b91714
AM		 10118 case OPTION_DIVIDE:
10119#ifdef SVR4_COMMENT_CHARS
10120 {
10121 char *n, *t;
10122 const char *s;
10123
add39d23 10124 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10125 t = n;
10126 for (s = i386_comment_chars; *s != '\0'; s++)
10127 if (*s != '/')
10128 *t++ = *s;
10129 *t = '\0';
10130 i386_comment_chars = n;
10131 }
10132#endif
10133 break;
10134
9103f4f4 10135 case OPTION_MARCH:
293f5f65
L		 10136 saved = xstrdup (arg);
10137 arch = saved;
10138 /* Allow -march=+nosse. */
10139 if (*arch == '+')
10140 arch++;
6305a203 10141 do
9103f4f4 10142 {
6305a203 10143 if (*arch == '.')
2b5d6a91 10144 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10145 next = strchr (arch, '+');
10146 if (next)
10147 *next++ = '\0';
91d6fa6a 10148 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10149 {
91d6fa6a 10150 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10151 {
6305a203 10152 /* Processor. */
1ded5609
JB		 10153 if (! cpu_arch[j].flags.bitfield.cpui386)
10154 continue;
10155
91d6fa6a 10156 cpu_arch_name = cpu_arch[j].name;
6305a203 10157 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10158 cpu_arch_flags = cpu_arch[j].flags;
10159 cpu_arch_isa = cpu_arch[j].type;
10160 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10161 if (!cpu_arch_tune_set)
10162 {
10163 cpu_arch_tune = cpu_arch_isa;
10164 cpu_arch_tune_flags = cpu_arch_isa_flags;
10165 }
10166 break;
10167 }
91d6fa6a
NC		 10168 else if (*cpu_arch [j].name == '.'
10169 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10170 {
33eaf5de 10171 /* ISA extension. */
6305a203 10172 i386_cpu_flags flags;
309d3373 10173
293f5f65
L		 10174 flags = cpu_flags_or (cpu_arch_flags,
10175 cpu_arch[j].flags);
81486035 10176
5b64d091 10177 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10178 {
10179 if (cpu_sub_arch_name)
10180 {
10181 char *name = cpu_sub_arch_name;
10182 cpu_sub_arch_name = concat (name,
91d6fa6a 10183 cpu_arch[j].name,
1bf57e9f 10184 (const char *) NULL);
6305a203
L		 10185 free (name);
10186 }
10187 else
91d6fa6a 10188 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10189 cpu_arch_flags = flags;
a586129e 10190 cpu_arch_isa_flags = flags;
6305a203
L		 10191 }
10192 break;
ccc9c027 10193 }
9103f4f4 10194 }
6305a203 10195
293f5f65
L		 10196 if (j >= ARRAY_SIZE (cpu_arch))
10197 {
33eaf5de 10198 /* Disable an ISA extension. */
293f5f65
L		 10199 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10200 if (strcmp (arch, cpu_noarch [j].name) == 0)
10201 {
10202 i386_cpu_flags flags;
10203
10204 flags = cpu_flags_and_not (cpu_arch_flags,
10205 cpu_noarch[j].flags);
10206 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10207 {
10208 if (cpu_sub_arch_name)
10209 {
10210 char *name = cpu_sub_arch_name;
10211 cpu_sub_arch_name = concat (arch,
10212 (const char *) NULL);
10213 free (name);
10214 }
10215 else
10216 cpu_sub_arch_name = xstrdup (arch);
10217 cpu_arch_flags = flags;
10218 cpu_arch_isa_flags = flags;
10219 }
10220 break;
10221 }
10222
10223 if (j >= ARRAY_SIZE (cpu_noarch))
10224 j = ARRAY_SIZE (cpu_arch);
10225 }
10226
91d6fa6a 10227 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10228 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10229
10230 arch = next;
9103f4f4 10231 }
293f5f65
L		 10232 while (next != NULL);
10233 free (saved);
9103f4f4
L		 10234 break;
10235
10236 case OPTION_MTUNE:
10237 if (*arg == '.')
2b5d6a91 10238 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10239 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10240 {
91d6fa6a 10241 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10242 {
ccc9c027 10243 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10244 cpu_arch_tune = cpu_arch [j].type;
10245 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10246 break;
10247 }
10248 }
91d6fa6a 10249 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10250 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10251 break;
10252
1efbbeb4
L		 10253 case OPTION_MMNEMONIC:
10254 if (strcasecmp (arg, "att") == 0)
10255 intel_mnemonic = 0;
10256 else if (strcasecmp (arg, "intel") == 0)
10257 intel_mnemonic = 1;
10258 else
2b5d6a91 10259 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10260 break;
10261
10262 case OPTION_MSYNTAX:
10263 if (strcasecmp (arg, "att") == 0)
10264 intel_syntax = 0;
10265 else if (strcasecmp (arg, "intel") == 0)
10266 intel_syntax = 1;
10267 else
2b5d6a91 10268 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10269 break;
10270
10271 case OPTION_MINDEX_REG:
10272 allow_index_reg = 1;
10273 break;
10274
10275 case OPTION_MNAKED_REG:
10276 allow_naked_reg = 1;
10277 break;
10278
10279 case OPTION_MOLD_GCC:
10280 old_gcc = 1;
1efbbeb4
L		 10281 break;
10282
c0f3af97
L		 10283 case OPTION_MSSE2AVX:
10284 sse2avx = 1;
10285 break;
10286
daf50ae7
L		 10287 case OPTION_MSSE_CHECK:
10288 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10289 sse_check = check_error;
daf50ae7 10290 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10291 sse_check = check_warning;
daf50ae7 10292 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10293 sse_check = check_none;
daf50ae7 10294 else
2b5d6a91 10295 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10296 break;
10297
7bab8ab5
JB		 10298 case OPTION_MOPERAND_CHECK:
10299 if (strcasecmp (arg, "error") == 0)
10300 operand_check = check_error;
10301 else if (strcasecmp (arg, "warning") == 0)
10302 operand_check = check_warning;
10303 else if (strcasecmp (arg, "none") == 0)
10304 operand_check = check_none;
10305 else
10306 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10307 break;
10308
539f890d
L		 10309 case OPTION_MAVXSCALAR:
10310 if (strcasecmp (arg, "128") == 0)
10311 avxscalar = vex128;
10312 else if (strcasecmp (arg, "256") == 0)
10313 avxscalar = vex256;
10314 else
2b5d6a91 10315 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10316 break;
10317
7e8b059b
L		 10318 case OPTION_MADD_BND_PREFIX:
10319 add_bnd_prefix = 1;
10320 break;
10321
43234a1e
L		 10322 case OPTION_MEVEXLIG:
10323 if (strcmp (arg, "128") == 0)
10324 evexlig = evexl128;
10325 else if (strcmp (arg, "256") == 0)
10326 evexlig = evexl256;
10327 else if (strcmp (arg, "512") == 0)
10328 evexlig = evexl512;
10329 else
10330 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10331 break;
10332
d3d3c6db
IT		 10333 case OPTION_MEVEXRCIG:
10334 if (strcmp (arg, "rne") == 0)
10335 evexrcig = rne;
10336 else if (strcmp (arg, "rd") == 0)
10337 evexrcig = rd;
10338 else if (strcmp (arg, "ru") == 0)
10339 evexrcig = ru;
10340 else if (strcmp (arg, "rz") == 0)
10341 evexrcig = rz;
10342 else
10343 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10344 break;
10345
43234a1e
L		 10346 case OPTION_MEVEXWIG:
10347 if (strcmp (arg, "0") == 0)
10348 evexwig = evexw0;
10349 else if (strcmp (arg, "1") == 0)
10350 evexwig = evexw1;
10351 else
10352 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10353 break;
10354
167ad85b
TG		 10355# if defined (TE_PE) || defined (TE_PEP)
10356 case OPTION_MBIG_OBJ:
10357 use_big_obj = 1;
10358 break;
10359#endif
10360
d1982f93 10361 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10362 if (strcasecmp (arg, "yes") == 0)
10363 omit_lock_prefix = 1;
10364 else if (strcasecmp (arg, "no") == 0)
10365 omit_lock_prefix = 0;
10366 else
10367 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10368 break;
10369
e4e00185
AS		 10370 case OPTION_MFENCE_AS_LOCK_ADD:
10371 if (strcasecmp (arg, "yes") == 0)
10372 avoid_fence = 1;
10373 else if (strcasecmp (arg, "no") == 0)
10374 avoid_fence = 0;
10375 else
10376 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10377 break;
10378
0cb4071e
L		 10379 case OPTION_MRELAX_RELOCATIONS:
10380 if (strcasecmp (arg, "yes") == 0)
10381 generate_relax_relocations = 1;
10382 else if (strcasecmp (arg, "no") == 0)
10383 generate_relax_relocations = 0;
10384 else
10385 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10386 break;
10387
5db04b09 10388 case OPTION_MAMD64:
e89c5eaa 10389 intel64 = 0;
5db04b09
L		 10390 break;
10391
10392 case OPTION_MINTEL64:
e89c5eaa 10393 intel64 = 1;
5db04b09
L		 10394 break;
10395
252b5132
RH		 10396 default:
10397 return 0;
10398 }
10399 return 1;
10400}
10401
8a2c8fef
L		 10402#define MESSAGE_TEMPLATE \
10403" "
10404
293f5f65
L		 10405static char *
10406output_message (FILE *stream, char *p, char *message, char *start,
10407 int *left_p, const char *name, int len)
10408{
10409 int size = sizeof (MESSAGE_TEMPLATE);
10410 int left = *left_p;
10411
10412 /* Reserve 2 spaces for ", " or ",\0" */
10413 left -= len + 2;
10414
10415 /* Check if there is any room. */
10416 if (left >= 0)
10417 {
10418 if (p != start)
10419 {
10420 *p++ = ',';
10421 *p++ = ' ';
10422 }
10423 p = mempcpy (p, name, len);
10424 }
10425 else
10426 {
10427 /* Output the current message now and start a new one. */
10428 *p++ = ',';
10429 *p = '\0';
10430 fprintf (stream, "%s\n", message);
10431 p = start;
10432 left = size - (start - message) - len - 2;
10433
10434 gas_assert (left >= 0);
10435
10436 p = mempcpy (p, name, len);
10437 }
10438
10439 *left_p = left;
10440 return p;
10441}
10442
8a2c8fef 10443static void
1ded5609 10444show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10445{
10446 static char message[] = MESSAGE_TEMPLATE;
10447 char *start = message + 27;
10448 char *p;
10449 int size = sizeof (MESSAGE_TEMPLATE);
10450 int left;
10451 const char *name;
10452 int len;
10453 unsigned int j;
10454
10455 p = start;
10456 left = size - (start - message);
10457 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10458 {
10459 /* Should it be skipped? */
10460 if (cpu_arch [j].skip)
10461 continue;
10462
10463 name = cpu_arch [j].name;
10464 len = cpu_arch [j].len;
10465 if (*name == '.')
10466 {
10467 /* It is an extension. Skip if we aren't asked to show it. */
10468 if (ext)
10469 {
10470 name++;
10471 len--;
10472 }
10473 else
10474 continue;
10475 }
10476 else if (ext)
10477 {
10478 /* It is an processor. Skip if we show only extension. */
10479 continue;
10480 }
1ded5609
JB		 10481 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10482 {
10483 /* It is an impossible processor - skip. */
10484 continue;
10485 }
8a2c8fef 10486
293f5f65 10487 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10488 }
10489
293f5f65
L		 10490 /* Display disabled extensions. */
10491 if (ext)
10492 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10493 {
10494 name = cpu_noarch [j].name;
10495 len = cpu_noarch [j].len;
10496 p = output_message (stream, p, message, start, &left, name,
10497 len);
10498 }
10499
8a2c8fef
L		 10500 *p = '\0';
10501 fprintf (stream, "%s\n", message);
10502}
10503
252b5132 10504void
8a2c8fef 10505md_show_usage (FILE *stream)
252b5132 10506{
4cc782b5
ILT		 10507#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10508 fprintf (stream, _("\
a38cf1db
AM		 10509 -Q ignored\n\
10510 -V print assembler version number\n\
b3b91714
AM		 10511 -k ignored\n"));
10512#endif
10513 fprintf (stream, _("\
12b55ccc 10514 -n Do not optimize code alignment\n\
b3b91714
AM		 10515 -q quieten some warnings\n"));
10516#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10517 fprintf (stream, _("\
a38cf1db 10518 -s ignored\n"));
b3b91714 10519#endif
321098a5
L		 10520#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10521 || defined (TE_PE) || defined (TE_PEP))
751d281c 10522 fprintf (stream, _("\
570561f7 10523 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10524#endif
b3b91714
AM		 10525#ifdef SVR4_COMMENT_CHARS
10526 fprintf (stream, _("\
10527 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10528#else
10529 fprintf (stream, _("\
b3b91714 10530 --divide ignored\n"));
4cc782b5 10531#endif
9103f4f4 10532 fprintf (stream, _("\
6305a203 10533 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10534 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10535 show_arch (stream, 0, 1);
8a2c8fef
L		 10536 fprintf (stream, _("\
10537 EXTENSION is combination of:\n"));
1ded5609 10538 show_arch (stream, 1, 0);
6305a203 10539 fprintf (stream, _("\
8a2c8fef 10540 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10541 show_arch (stream, 0, 0);
ba104c83 10542 fprintf (stream, _("\
c0f3af97
L		 10543 -msse2avx encode SSE instructions with VEX prefix\n"));
10544 fprintf (stream, _("\
daf50ae7
L		 10545 -msse-check=[none|error|warning]\n\
10546 check SSE instructions\n"));
10547 fprintf (stream, _("\
7bab8ab5
JB		 10548 -moperand-check=[none|error|warning]\n\
10549 check operand combinations for validity\n"));
10550 fprintf (stream, _("\
539f890d
L		 10551 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10552 length\n"));
10553 fprintf (stream, _("\
43234a1e
L		 10554 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10555 length\n"));
10556 fprintf (stream, _("\
10557 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10558 for EVEX.W bit ignored instructions\n"));
10559 fprintf (stream, _("\
d3d3c6db
IT		 10560 -mevexrcig=[rne|rd|ru|rz]\n\
10561 encode EVEX instructions with specific EVEX.RC value\n\
10562 for SAE-only ignored instructions\n"));
10563 fprintf (stream, _("\
ba104c83
L		 10564 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10565 fprintf (stream, _("\
10566 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10567 fprintf (stream, _("\
10568 -mindex-reg support pseudo index registers\n"));
10569 fprintf (stream, _("\
10570 -mnaked-reg don't require `%%' prefix for registers\n"));
10571 fprintf (stream, _("\
10572 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10573 fprintf (stream, _("\
10574 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10575 fprintf (stream, _("\
10576 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10577# if defined (TE_PE) || defined (TE_PEP)
10578 fprintf (stream, _("\
10579 -mbig-obj generate big object files\n"));
10580#endif
d022bddd
IT		 10581 fprintf (stream, _("\
10582 -momit-lock-prefix=[no|yes]\n\
10583 strip all lock prefixes\n"));
5db04b09 10584 fprintf (stream, _("\
e4e00185
AS		 10585 -mfence-as-lock-add=[no|yes]\n\
10586 encode lfence, mfence and sfence as\n\
10587 lock addl $0x0, (%%{re}sp)\n"));
10588 fprintf (stream, _("\
0cb4071e
L		 10589 -mrelax-relocations=[no|yes]\n\
10590 generate relax relocations\n"));
10591 fprintf (stream, _("\
5db04b09
L		 10592 -mamd64 accept only AMD64 ISA\n"));
10593 fprintf (stream, _("\
10594 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10595}
10596
3e73aa7c 10597#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10598 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10599 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10600
10601/* Pick the target format to use. */
10602
47926f60 10603const char *
e3bb37b5 10604i386_target_format (void)
252b5132 10605{
351f65ca
L		 10606 if (!strncmp (default_arch, "x86_64", 6))
10607 {
10608 update_code_flag (CODE_64BIT, 1);
10609 if (default_arch[6] == '\0')
7f56bc95 10610 x86_elf_abi = X86_64_ABI;
351f65ca 10611 else
7f56bc95 10612 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10613 }
3e73aa7c 10614 else if (!strcmp (default_arch, "i386"))
78f12dd3 10615 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10616 else if (!strcmp (default_arch, "iamcu"))
10617 {
10618 update_code_flag (CODE_32BIT, 1);
10619 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10620 {
10621 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10622 cpu_arch_name = "iamcu";
10623 cpu_sub_arch_name = NULL;
10624 cpu_arch_flags = iamcu_flags;
10625 cpu_arch_isa = PROCESSOR_IAMCU;
10626 cpu_arch_isa_flags = iamcu_flags;
10627 if (!cpu_arch_tune_set)
10628 {
10629 cpu_arch_tune = cpu_arch_isa;
10630 cpu_arch_tune_flags = cpu_arch_isa_flags;
10631 }
10632 }
8d471ec1 10633 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10634 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10635 cpu_arch_name);
10636 }
3e73aa7c 10637 else
2b5d6a91 10638 as_fatal (_("unknown architecture"));
89507696
JB		 10639
10640 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10641 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10642 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10643 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10644
252b5132
RH		 10645 switch (OUTPUT_FLAVOR)
10646 {
9384f2ff 10647#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10648 case bfd_target_aout_flavour:
47926f60 10649 return AOUT_TARGET_FORMAT;
4c63da97 10650#endif
9384f2ff
AM		 10651#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10652# if defined (TE_PE) || defined (TE_PEP)
10653 case bfd_target_coff_flavour:
167ad85b
TG		 10654 if (flag_code == CODE_64BIT)
10655 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10656 else
10657 return "pe-i386";
9384f2ff 10658# elif defined (TE_GO32)
0561d57c
JK		 10659 case bfd_target_coff_flavour:
10660 return "coff-go32";
9384f2ff 10661# else
252b5132
RH		 10662 case bfd_target_coff_flavour:
10663 return "coff-i386";
9384f2ff 10664# endif
4c63da97 10665#endif
3e73aa7c 10666#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10667 case bfd_target_elf_flavour:
3e73aa7c 10668 {
351f65ca
L		 10669 const char *format;
10670
10671 switch (x86_elf_abi)
4fa24527 10672 {
351f65ca
L		 10673 default:
10674 format = ELF_TARGET_FORMAT;
10675 break;
7f56bc95 10676 case X86_64_ABI:
351f65ca 10677 use_rela_relocations = 1;
4fa24527 10678 object_64bit = 1;
351f65ca
L		 10679 format = ELF_TARGET_FORMAT64;
10680 break;
7f56bc95 10681 case X86_64_X32_ABI:
4fa24527 10682 use_rela_relocations = 1;
351f65ca 10683 object_64bit = 1;
862be3fb 10684 disallow_64bit_reloc = 1;
351f65ca
L		 10685 format = ELF_TARGET_FORMAT32;
10686 break;
4fa24527 10687 }
3632d14b 10688 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10689 {
7f56bc95 10690 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10691 as_fatal (_("Intel L1OM is 64bit only"));
10692 return ELF_TARGET_L1OM_FORMAT;
10693 }
b49f93f6 10694 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10695 {
10696 if (x86_elf_abi != X86_64_ABI)
10697 as_fatal (_("Intel K1OM is 64bit only"));
10698 return ELF_TARGET_K1OM_FORMAT;
10699 }
81486035
L		 10700 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10701 {
10702 if (x86_elf_abi != I386_ABI)
10703 as_fatal (_("Intel MCU is 32bit only"));
10704 return ELF_TARGET_IAMCU_FORMAT;
10705 }
8a9036a4 10706 else
351f65ca 10707 return format;
3e73aa7c 10708 }
e57f8c65
TG		 10709#endif
10710#if defined (OBJ_MACH_O)
10711 case bfd_target_mach_o_flavour:
d382c579
TG		 10712 if (flag_code == CODE_64BIT)
10713 {
10714 use_rela_relocations = 1;
10715 object_64bit = 1;
10716 return "mach-o-x86-64";
10717 }
10718 else
10719 return "mach-o-i386";
4c63da97 10720#endif
252b5132
RH		 10721 default:
10722 abort ();
10723 return NULL;
10724 }
10725}
10726
47926f60 10727#endif /* OBJ_MAYBE_ more than one */
252b5132 10728\f
252b5132 10729symbolS *
7016a5d5 10730md_undefined_symbol (char *name)
252b5132 10731{
18dc2407
ILT		 10732 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10733 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10734 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10735 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10736 {
10737 if (!GOT_symbol)
10738 {
10739 if (symbol_find (name))
10740 as_bad (_("GOT already in symbol table"));
10741 GOT_symbol = symbol_new (name, undefined_section,
10742 (valueT) 0, &zero_address_frag);
10743 };
10744 return GOT_symbol;
10745 }
252b5132
RH		 10746 return 0;
10747}
10748
10749/* Round up a section size to the appropriate boundary. */
47926f60 10750
252b5132 10751valueT
7016a5d5 10752md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10753{
4c63da97
AM		 10754#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10755 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10756 {
10757 /* For a.out, force the section size to be aligned. If we don't do
10758 this, BFD will align it for us, but it will not write out the
10759 final bytes of the section. This may be a bug in BFD, but it is
10760 easier to fix it here since that is how the other a.out targets
10761 work. */
10762 int align;
10763
10764 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10765 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10766 }
252b5132
RH		 10767#endif
10768
10769 return size;
10770}
10771
10772/* On the i386, PC-relative offsets are relative to the start of the
10773 next instruction. That is, the address of the offset, plus its
10774 size, since the offset is always the last part of the insn. */
10775
10776long
e3bb37b5 10777md_pcrel_from (fixS *fixP)
252b5132
RH		 10778{
10779 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10780}
10781
10782#ifndef I386COFF
10783
10784static void
e3bb37b5 10785s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10786{
29b0f896 10787 int temp;
252b5132 10788
8a75718c
JB		 10789#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10790 if (IS_ELF)
10791 obj_elf_section_change_hook ();
10792#endif
252b5132
RH		 10793 temp = get_absolute_expression ();
10794 subseg_set (bss_section, (subsegT) temp);
10795 demand_empty_rest_of_line ();
10796}
10797
10798#endif
10799
252b5132 10800void
e3bb37b5 10801i386_validate_fix (fixS *fixp)
252b5132 10802{
02a86693 10803 if (fixp->fx_subsy)
252b5132 10804 {
02a86693 10805 if (fixp->fx_subsy == GOT_symbol)
23df1078 10806 {
02a86693
L		 10807 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10808 {
10809 if (!object_64bit)
10810 abort ();
10811#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10812 if (fixp->fx_tcbit2)
56ceb5b5
L		 10813 fixp->fx_r_type = (fixp->fx_tcbit
10814 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10815 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10816 else
10817#endif
10818 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10819 }
d6ab8113 10820 else
02a86693
L		 10821 {
10822 if (!object_64bit)
10823 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10824 else
10825 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10826 }
10827 fixp->fx_subsy = 0;
23df1078 10828 }
252b5132 10829 }
02a86693
L		 10830#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10831 else if (!object_64bit)
10832 {
10833 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10834 && fixp->fx_tcbit2)
10835 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10836 }
10837#endif
252b5132
RH		 10838}
10839
252b5132 10840arelent *
7016a5d5 10841tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10842{
10843 arelent *rel;
10844 bfd_reloc_code_real_type code;
10845
10846 switch (fixp->fx_r_type)
10847 {
8ce3d284 10848#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10849 case BFD_RELOC_SIZE32:
10850 case BFD_RELOC_SIZE64:
10851 if (S_IS_DEFINED (fixp->fx_addsy)
10852 && !S_IS_EXTERNAL (fixp->fx_addsy))
10853 {
10854 /* Resolve size relocation against local symbol to size of
10855 the symbol plus addend. */
10856 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10857 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10858 && !fits_in_unsigned_long (value))
10859 as_bad_where (fixp->fx_file, fixp->fx_line,
10860 _("symbol size computation overflow"));
10861 fixp->fx_addsy = NULL;
10862 fixp->fx_subsy = NULL;
10863 md_apply_fix (fixp, (valueT *) &value, NULL);
10864 return NULL;
10865 }
8ce3d284 10866#endif
1a0670f3 10867 /* Fall through. */
8fd4256d 10868
3e73aa7c
JH		 10869 case BFD_RELOC_X86_64_PLT32:
10870 case BFD_RELOC_X86_64_GOT32:
10871 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10872 case BFD_RELOC_X86_64_GOTPCRELX:
10873 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10874 case BFD_RELOC_386_PLT32:
10875 case BFD_RELOC_386_GOT32:
02a86693 10876 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10877 case BFD_RELOC_386_GOTOFF:
10878 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10879 case BFD_RELOC_386_TLS_GD:
10880 case BFD_RELOC_386_TLS_LDM:
10881 case BFD_RELOC_386_TLS_LDO_32:
10882 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10883 case BFD_RELOC_386_TLS_IE:
10884 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10885 case BFD_RELOC_386_TLS_LE_32:
10886 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10887 case BFD_RELOC_386_TLS_GOTDESC:
10888 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10889 case BFD_RELOC_X86_64_TLSGD:
10890 case BFD_RELOC_X86_64_TLSLD:
10891 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10892 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10893 case BFD_RELOC_X86_64_GOTTPOFF:
10894 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10895 case BFD_RELOC_X86_64_TPOFF64:
10896 case BFD_RELOC_X86_64_GOTOFF64:
10897 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10898 case BFD_RELOC_X86_64_GOT64:
10899 case BFD_RELOC_X86_64_GOTPCREL64:
10900 case BFD_RELOC_X86_64_GOTPC64:
10901 case BFD_RELOC_X86_64_GOTPLT64:
10902 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10903 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10904 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10905 case BFD_RELOC_RVA:
10906 case BFD_RELOC_VTABLE_ENTRY:
10907 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10908#ifdef TE_PE
10909 case BFD_RELOC_32_SECREL:
10910#endif
252b5132
RH		 10911 code = fixp->fx_r_type;
10912 break;
dbbaec26
L		 10913 case BFD_RELOC_X86_64_32S:
10914 if (!fixp->fx_pcrel)
10915 {
10916 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10917 code = fixp->fx_r_type;
10918 break;
10919 }
1a0670f3 10920 /* Fall through. */
252b5132 10921 default:
93382f6d 10922 if (fixp->fx_pcrel)
252b5132 10923 {
93382f6d
AM		 10924 switch (fixp->fx_size)
10925 {
10926 default:
b091f402
AM		 10927 as_bad_where (fixp->fx_file, fixp->fx_line,
10928 _("can not do %d byte pc-relative relocation"),
10929 fixp->fx_size);
93382f6d
AM		 10930 code = BFD_RELOC_32_PCREL;
10931 break;
10932 case 1: code = BFD_RELOC_8_PCREL; break;
10933 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10934 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10935#ifdef BFD64
10936 case 8: code = BFD_RELOC_64_PCREL; break;
10937#endif
93382f6d
AM		 10938 }
10939 }
10940 else
10941 {
10942 switch (fixp->fx_size)
10943 {
10944 default:
b091f402
AM		 10945 as_bad_where (fixp->fx_file, fixp->fx_line,
10946 _("can not do %d byte relocation"),
10947 fixp->fx_size);
93382f6d
AM		 10948 code = BFD_RELOC_32;
10949 break;
10950 case 1: code = BFD_RELOC_8; break;
10951 case 2: code = BFD_RELOC_16; break;
10952 case 4: code = BFD_RELOC_32; break;
937149dd 10953#ifdef BFD64
3e73aa7c 10954 case 8: code = BFD_RELOC_64; break;
937149dd 10955#endif
93382f6d 10956 }
252b5132
RH		 10957 }
10958 break;
10959 }
252b5132 10960
d182319b
JB		 10961 if ((code == BFD_RELOC_32
10962 || code == BFD_RELOC_32_PCREL
10963 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10964 && GOT_symbol
10965 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10966 {
4fa24527 10967 if (!object_64bit)
d6ab8113
JB		 10968 code = BFD_RELOC_386_GOTPC;
10969 else
10970 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10971 }
7b81dfbb
AJ		 10972 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10973 && GOT_symbol
10974 && fixp->fx_addsy == GOT_symbol)
10975 {
10976 code = BFD_RELOC_X86_64_GOTPC64;
10977 }
252b5132 10978
add39d23
TS		 10979 rel = XNEW (arelent);
10980 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10981 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10982
10983 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10984
3e73aa7c
JH		 10985 if (!use_rela_relocations)
10986 {
10987 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10988 vtable entry to be used in the relocation's section offset. */
10989 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10990 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10991#if defined (OBJ_COFF) && defined (TE_PE)
10992 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10993 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10994 else
10995#endif
c6682705 10996 rel->addend = 0;
3e73aa7c
JH		 10997 }
10998 /* Use the rela in 64bit mode. */
252b5132 10999 else
3e73aa7c 11000 {
862be3fb
L		 11001 if (disallow_64bit_reloc)
11002 switch (code)
11003 {
862be3fb
L		 11004 case BFD_RELOC_X86_64_DTPOFF64:
11005 case BFD_RELOC_X86_64_TPOFF64:
11006 case BFD_RELOC_64_PCREL:
11007 case BFD_RELOC_X86_64_GOTOFF64:
11008 case BFD_RELOC_X86_64_GOT64:
11009 case BFD_RELOC_X86_64_GOTPCREL64:
11010 case BFD_RELOC_X86_64_GOTPC64:
11011 case BFD_RELOC_X86_64_GOTPLT64:
11012 case BFD_RELOC_X86_64_PLTOFF64:
11013 as_bad_where (fixp->fx_file, fixp->fx_line,
11014 _("cannot represent relocation type %s in x32 mode"),
11015 bfd_get_reloc_code_name (code));
11016 break;
11017 default:
11018 break;
11019 }
11020
062cd5e7
AS		 11021 if (!fixp->fx_pcrel)
11022 rel->addend = fixp->fx_offset;
11023 else
11024 switch (code)
11025 {
11026 case BFD_RELOC_X86_64_PLT32:
11027 case BFD_RELOC_X86_64_GOT32:
11028 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11029 case BFD_RELOC_X86_64_GOTPCRELX:
11030 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11031 case BFD_RELOC_X86_64_TLSGD:
11032 case BFD_RELOC_X86_64_TLSLD:
11033 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11034 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11035 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11036 rel->addend = fixp->fx_offset - fixp->fx_size;
11037 break;
11038 default:
11039 rel->addend = (section->vma
11040 - fixp->fx_size
11041 + fixp->fx_addnumber
11042 + md_pcrel_from (fixp));
11043 break;
11044 }
3e73aa7c
JH		 11045 }
11046
252b5132
RH		 11047 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11048 if (rel->howto == NULL)
11049 {
11050 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11051 _("cannot represent relocation type %s"),
252b5132
RH		 11052 bfd_get_reloc_code_name (code));
11053 /* Set howto to a garbage value so that we can keep going. */
11054 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11055 gas_assert (rel->howto != NULL);
252b5132
RH		 11056 }
11057
11058 return rel;
11059}
11060
ee86248c 11061#include "tc-i386-intel.c"
54cfded0 11062
a60de03c
JB		 11063void
11064tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11065{
a60de03c
JB		 11066 int saved_naked_reg;
11067 char saved_register_dot;
54cfded0 11068
a60de03c
JB		 11069 saved_naked_reg = allow_naked_reg;
11070 allow_naked_reg = 1;
11071 saved_register_dot = register_chars['.'];
11072 register_chars['.'] = '.';
11073 allow_pseudo_reg = 1;
11074 expression_and_evaluate (exp);
11075 allow_pseudo_reg = 0;
11076 register_chars['.'] = saved_register_dot;
11077 allow_naked_reg = saved_naked_reg;
11078
e96d56a1 11079 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11080 {
a60de03c
JB		 11081 if ((addressT) exp->X_add_number < i386_regtab_size)
11082 {
11083 exp->X_op = O_constant;
11084 exp->X_add_number = i386_regtab[exp->X_add_number]
11085 .dw2_regnum[flag_code >> 1];
11086 }
11087 else
11088 exp->X_op = O_illegal;
54cfded0 11089 }
54cfded0
AM		 11090}
11091
11092void
11093tc_x86_frame_initial_instructions (void)
11094{
a60de03c
JB		 11095 static unsigned int sp_regno[2];
11096
11097 if (!sp_regno[flag_code >> 1])
11098 {
11099 char *saved_input = input_line_pointer;
11100 char sp[][4] = {"esp", "rsp"};
11101 expressionS exp;
a4447b93 11102
a60de03c
JB		 11103 input_line_pointer = sp[flag_code >> 1];
11104 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11105 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11106 sp_regno[flag_code >> 1] = exp.X_add_number;
11107 input_line_pointer = saved_input;
11108 }
a4447b93 11109
61ff971f
L		 11110 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11111 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11112}
d2b2c203 11113
d7921315
L		 11114int
11115x86_dwarf2_addr_size (void)
11116{
11117#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11118 if (x86_elf_abi == X86_64_X32_ABI)
11119 return 4;
11120#endif
11121 return bfd_arch_bits_per_address (stdoutput) / 8;
11122}
11123
d2b2c203
DJ		 11124int
11125i386_elf_section_type (const char *str, size_t len)
11126{
11127 if (flag_code == CODE_64BIT
11128 && len == sizeof ("unwind") - 1
11129 && strncmp (str, "unwind", 6) == 0)
11130 return SHT_X86_64_UNWIND;
11131
11132 return -1;
11133}
bb41ade5 11134
ad5fec3b
EB		 11135#ifdef TE_SOLARIS
11136void
11137i386_solaris_fix_up_eh_frame (segT sec)
11138{
11139 if (flag_code == CODE_64BIT)
11140 elf_section_type (sec) = SHT_X86_64_UNWIND;
11141}
11142#endif
11143
bb41ade5
AM		 11144#ifdef TE_PE
11145void
11146tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11147{
91d6fa6a 11148 expressionS exp;
bb41ade5 11149
91d6fa6a
NC		 11150 exp.X_op = O_secrel;
11151 exp.X_add_symbol = symbol;
11152 exp.X_add_number = 0;
11153 emit_expr (&exp, size);
bb41ade5
AM		 11154}
11155#endif
3b22753a
L		 11156
11157#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11158/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11159
01e1a5bc 11160bfd_vma
6d4af3c2 11161x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11162{
11163 if (flag_code == CODE_64BIT)
11164 {
11165 if (letter == 'l')
11166 return SHF_X86_64_LARGE;
11167
8f3bae45 11168 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11169 }
3b22753a 11170 else
8f3bae45 11171 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11172 return -1;
11173}
11174
01e1a5bc 11175bfd_vma
3b22753a
L		 11176x86_64_section_word (char *str, size_t len)
11177{
8620418b 11178 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11179 return SHF_X86_64_LARGE;
11180
11181 return -1;
11182}
11183
11184static void
11185handle_large_common (int small ATTRIBUTE_UNUSED)
11186{
11187 if (flag_code != CODE_64BIT)
11188 {
11189 s_comm_internal (0, elf_common_parse);
11190 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11191 }
11192 else
11193 {
11194 static segT lbss_section;
11195 asection *saved_com_section_ptr = elf_com_section_ptr;
11196 asection *saved_bss_section = bss_section;
11197
11198 if (lbss_section == NULL)
11199 {
11200 flagword applicable;
11201 segT seg = now_seg;
11202 subsegT subseg = now_subseg;
11203
11204 /* The .lbss section is for local .largecomm symbols. */
11205 lbss_section = subseg_new (".lbss", 0);
11206 applicable = bfd_applicable_section_flags (stdoutput);
11207 bfd_set_section_flags (stdoutput, lbss_section,
11208 applicable & SEC_ALLOC);
11209 seg_info (lbss_section)->bss = 1;
11210
11211 subseg_set (seg, subseg);
11212 }
11213
11214 elf_com_section_ptr = &_bfd_elf_large_com_section;
11215 bss_section = lbss_section;
11216
11217 s_comm_internal (0, elf_common_parse);
11218
11219 elf_com_section_ptr = saved_com_section_ptr;
11220 bss_section = saved_bss_section;
11221 }
11222}
11223#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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