]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - gas/config/tc-i386.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
2006-12-13 Dave Brolley <brolley@redhat.com>
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
ccc9c027
L		 327/* If we have selected a cpu we are generating instructions for. */
328static int cpu_arch_tune_set = 0;
329
9103f4f4
L		 330/* Cpu we are generating instructions for. */
331static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332
333/* CPU feature flags of cpu we are generating instructions for. */
334static unsigned int cpu_arch_tune_flags = 0;
335
ccc9c027
L		 336/* CPU instruction set architecture used. */
337static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338
9103f4f4
L		 339/* CPU feature flags of instruction set architecture used. */
340static unsigned int cpu_arch_isa_flags = 0;
341
fddf5b5b
AM		 342/* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344static unsigned int no_cond_jump_promotion = 0;
345
29b0f896 346/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 347static symbolS *GOT_symbol;
29b0f896 348
a4447b93
RH		 349/* The dwarf2 return column, adjusted for 32 or 64 bit. */
350unsigned int x86_dwarf2_return_column;
351
352/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353int x86_cie_data_alignment;
354
252b5132 355/* Interface to relax_segment.
fddf5b5b
AM		 356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
252b5132 359
47926f60 360/* Types. */
93c2a809
AM		 361#define UNCOND_JUMP 0
362#define COND_JUMP 1
363#define COND_JUMP86 2
fddf5b5b 364
47926f60 365/* Sizes. */
252b5132
RH		 366#define CODE16 1
367#define SMALL 0
29b0f896 368#define SMALL16 (SMALL | CODE16)
252b5132 369#define BIG 2
29b0f896 370#define BIG16 (BIG | CODE16)
252b5132
RH		 371
372#ifndef INLINE
373#ifdef __GNUC__
374#define INLINE __inline__
375#else
376#define INLINE
377#endif
378#endif
379
fddf5b5b
AM		 380#define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382#define TYPE_FROM_RELAX_STATE(s) \
383 ((s) >> 2)
384#define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 386
387/* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
394
395const relax_typeS md_relax_table[] =
396{
24eab124
AM		 397 /* The fields are:
398 1) most positive reach of this state,
399 2) most negative reach of this state,
93c2a809 400 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 401 4) which index into the table to try if we can't fit into this one. */
252b5132 402
fddf5b5b 403 /* UNCOND_JUMP states. */
93c2a809
AM		 404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
252b5132 408 {0, 0, 4, 0},
93c2a809
AM		 409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 411 {0, 0, 2, 0},
412
93c2a809
AM		 413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
fddf5b5b 419 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 420 1 extra opcode byte, 2 displacement bytes. */
421 {0, 0, 3, 0},
422
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
428 {0, 0, 5, 0},
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
431 {0, 0, 4, 0}
252b5132
RH		 432};
433
9103f4f4
L		 434static const arch_entry cpu_arch[] =
435{
436 {"generic32", PROCESSOR_GENERIC32,
d32cad65 437 Cpu186|Cpu286|Cpu386},
9103f4f4 438 {"generic64", PROCESSOR_GENERIC64,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 442 0},
9103f4f4 443 {"i186", PROCESSOR_UNKNOWN,
d32cad65 444 Cpu186},
9103f4f4 445 {"i286", PROCESSOR_UNKNOWN,
d32cad65 446 Cpu186|Cpu286},
9103f4f4 447 {"i386", PROCESSOR_GENERIC32,
d32cad65 448 Cpu186|Cpu286|Cpu386},
9103f4f4 449 {"i486", PROCESSOR_I486,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 451 {"i586", PROCESSOR_PENTIUM,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 453 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 455 {"pentium", PROCESSOR_PENTIUM,
d32cad65 456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 459 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 463 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
d32cad65 467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
d32cad65 470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 472 {"yonah", PROCESSOR_CORE,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 475 {"core", PROCESSOR_CORE,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
478 {"merom", PROCESSOR_CORE2,
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
480 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
481 {"core2", PROCESSOR_CORE2,
482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
483 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 484 {"k6", PROCESSOR_K6,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 486 {"k6_2", PROCESSOR_K6,
d32cad65 487 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 488 {"athlon", PROCESSOR_ATHLON,
d32cad65 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
491 {"sledgehammer", PROCESSOR_K8,
d32cad65 492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
494 {"opteron", PROCESSOR_K8,
d32cad65 495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 496 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
497 {"k8", PROCESSOR_K8,
d32cad65 498 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 499 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 500 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 501 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
502 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
503 |CpuABM},
9103f4f4
L		 504 {".mmx", PROCESSOR_UNKNOWN,
505 CpuMMX},
506 {".sse", PROCESSOR_UNKNOWN,
507 CpuMMX|CpuMMX2|CpuSSE},
508 {".sse2", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
510 {".sse3", PROCESSOR_UNKNOWN,
511 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 512 {".ssse3", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 514 {".3dnow", PROCESSOR_UNKNOWN,
515 CpuMMX|Cpu3dnow},
516 {".3dnowa", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
518 {".padlock", PROCESSOR_UNKNOWN,
519 CpuPadLock},
520 {".pacifica", PROCESSOR_UNKNOWN,
521 CpuSVME},
522 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 523 CpuSVME},
524 {".sse4a", PROCESSOR_UNKNOWN,
525 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
526 {".abm", PROCESSOR_UNKNOWN,
527 CpuABM}
e413e4e9
AM		 528};
529
29b0f896
AM		 530const pseudo_typeS md_pseudo_table[] =
531{
532#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
533 {"align", s_align_bytes, 0},
534#else
535 {"align", s_align_ptwo, 0},
536#endif
537 {"arch", set_cpu_arch, 0},
538#ifndef I386COFF
539 {"bss", s_bss, 0},
540#endif
541 {"ffloat", float_cons, 'f'},
542 {"dfloat", float_cons, 'd'},
543 {"tfloat", float_cons, 'x'},
544 {"value", cons, 2},
d182319b 545 {"slong", signed_cons, 4},
29b0f896
AM		 546 {"noopt", s_ignore, 0},
547 {"optim", s_ignore, 0},
548 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
549 {"code16", set_code_flag, CODE_16BIT},
550 {"code32", set_code_flag, CODE_32BIT},
551 {"code64", set_code_flag, CODE_64BIT},
552 {"intel_syntax", set_intel_syntax, 1},
553 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 554#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
555 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 556#else
557 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
558 {"loc", dwarf2_directive_loc, 0},
559 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 560#endif
6482c264
NC		 561#ifdef TE_PE
562 {"secrel32", pe_directive_secrel, 0},
563#endif
29b0f896
AM		 564 {0, 0, 0}
565};
566
567/* For interface with expression (). */
568extern char *input_line_pointer;
569
570/* Hash table for instruction mnemonic lookup. */
571static struct hash_control *op_hash;
572
573/* Hash table for register lookup. */
574static struct hash_control *reg_hash;
575\f
252b5132
RH		 576void
577i386_align_code (fragP, count)
578 fragS *fragP;
579 int count;
580{
ce8a8b2f
AM		 581 /* Various efficient no-op patterns for aligning code labels.
582 Note: Don't try to assemble the instructions in the comments.
583 0L and 0w are not legal. */
252b5132
RH		 584 static const char f32_1[] =
585 {0x90}; /* nop */
586 static const char f32_2[] =
ccc9c027 587 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 588 static const char f32_3[] =
589 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
590 static const char f32_4[] =
591 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
592 static const char f32_5[] =
593 {0x90, /* nop */
594 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
595 static const char f32_6[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
597 static const char f32_7[] =
598 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
599 static const char f32_8[] =
600 {0x90, /* nop */
601 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
602 static const char f32_9[] =
603 {0x89,0xf6, /* movl %esi,%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_10[] =
606 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_11[] =
609 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_12[] =
612 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
613 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
614 static const char f32_13[] =
615 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
616 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
617 static const char f32_14[] =
618 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
619 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
620 static const char f32_15[] =
621 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 623 static const char f16_3[] =
624 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 625 static const char f16_4[] =
626 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
627 static const char f16_5[] =
628 {0x90, /* nop */
629 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
630 static const char f16_6[] =
631 {0x89,0xf6, /* mov %si,%si */
632 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
633 static const char f16_7[] =
634 {0x8d,0x74,0x00, /* lea 0(%si),%si */
635 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
636 static const char f16_8[] =
637 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
638 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
639 static const char *const f32_patt[] = {
640 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
641 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
642 };
643 static const char *const f16_patt[] = {
c3332e24 644 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 645 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
646 };
ccc9c027
L		 647 /* nopl (%[re]ax) */
648 static const char alt_3[] =
649 {0x0f,0x1f,0x00};
650 /* nopl 0(%[re]ax) */
651 static const char alt_4[] =
652 {0x0f,0x1f,0x40,0x00};
653 /* nopl 0(%[re]ax,%[re]ax,1) */
654 static const char alt_5[] =
655 {0x0f,0x1f,0x44,0x00,0x00};
656 /* nopw 0(%[re]ax,%[re]ax,1) */
657 static const char alt_6[] =
658 {0x66,0x0f,0x1f,0x44,0x00,0x00};
659 /* nopl 0L(%[re]ax) */
660 static const char alt_7[] =
661 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
662 /* nopl 0L(%[re]ax,%[re]ax,1) */
663 static const char alt_8[] =
664 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* nopw 0L(%[re]ax,%[re]ax,1) */
666 static const char alt_9[] =
667 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_10[] =
670 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
671 /* data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_11[] =
674 {0x66,
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
676 /* data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_12[] =
680 {0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 nopw %cs:0L(%[re]ax,%[re]ax,1) */
687 static const char alt_long_13[] =
688 {0x66,
689 0x66,
690 0x66,
691 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
692 /* data16
693 data16
694 data16
695 data16
696 nopw %cs:0L(%[re]ax,%[re]ax,1) */
697 static const char alt_long_14[] =
698 {0x66,
699 0x66,
700 0x66,
701 0x66,
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* data16
704 data16
705 data16
706 data16
707 data16
708 nopw %cs:0L(%[re]ax,%[re]ax,1) */
709 static const char alt_long_15[] =
710 {0x66,
711 0x66,
712 0x66,
713 0x66,
714 0x66,
715 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
716 /* nopl 0(%[re]ax,%[re]ax,1)
717 nopw 0(%[re]ax,%[re]ax,1) */
718 static const char alt_short_11[] =
719 {0x0f,0x1f,0x44,0x00,0x00,
720 0x66,0x0f,0x1f,0x44,0x00,0x00};
721 /* nopw 0(%[re]ax,%[re]ax,1)
722 nopw 0(%[re]ax,%[re]ax,1) */
723 static const char alt_short_12[] =
724 {0x66,0x0f,0x1f,0x44,0x00,0x00,
725 0x66,0x0f,0x1f,0x44,0x00,0x00};
726 /* nopw 0(%[re]ax,%[re]ax,1)
727 nopl 0L(%[re]ax) */
728 static const char alt_short_13[] =
729 {0x66,0x0f,0x1f,0x44,0x00,0x00,
730 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
731 /* nopl 0L(%[re]ax)
732 nopl 0L(%[re]ax) */
733 static const char alt_short_14[] =
734 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
735 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
736 /* nopl 0L(%[re]ax)
737 nopl 0L(%[re]ax,%[re]ax,1) */
738 static const char alt_short_15[] =
739 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
740 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
741 static const char *const alt_short_patt[] = {
742 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
743 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
744 alt_short_14, alt_short_15
745 };
746 static const char *const alt_long_patt[] = {
747 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
748 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
749 alt_long_14, alt_long_15
750 };
252b5132 751
33fef721
JH		 752 if (count <= 0 || count > 15)
753 return;
3e73aa7c 754
ccc9c027
L		 755 /* We need to decide which NOP sequence to use for 32bit and
756 64bit. When -mtune= is used:
757
758 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
759 f32_patt will be used.
050dfa73 760 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 761 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 762 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 763 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 764 and PROCESSOR_GENERIC64, alt_short_patt will be used.
765
766 When -mtune= isn't used, alt_short_patt will be used if
767 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
768
769 When -march= or .arch is used, we can't use anything beyond
770 cpu_arch_isa_flags. */
771
772 if (flag_code == CODE_16BIT)
773 {
774 memcpy (fragP->fr_literal + fragP->fr_fix,
775 f16_patt[count - 1], count);
776 if (count > 8)
777 /* Adjust jump offset. */
778 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
779 }
780 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 781 {
33fef721
JH		 782 int i;
783 int nnops = (count + 3) / 4;
784 int len = count / nnops;
785 int remains = count - nnops * len;
786 int pos = 0;
787
ccc9c027
L		 788 /* The recommended way to pad 64bit code is to use NOPs preceded
789 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 790 for (i = 0; i < remains; i++)
252b5132 791 {
33fef721
JH		 792 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
793 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
794 pos += len + 1;
795 }
796 for (; i < nnops; i++)
797 {
798 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
799 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
800 pos += len;
252b5132 801 }
252b5132 802 }
33fef721 803 else
ccc9c027
L		 804 {
805 const char *const *patt = NULL;
806
807 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
808 {
809 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
810 switch (cpu_arch_tune)
811 {
812 case PROCESSOR_UNKNOWN:
813 /* We use cpu_arch_isa_flags to check if we SHOULD
814 optimize for Cpu686. */
815 if ((cpu_arch_isa_flags & Cpu686) != 0)
816 patt = alt_short_patt;
817 else
818 patt = f32_patt;
819 break;
ef05d495 820 case PROCESSOR_CORE2:
ccc9c027
L		 821 patt = alt_long_patt;
822 break;
823 case PROCESSOR_PENTIUMPRO:
824 case PROCESSOR_PENTIUM4:
825 case PROCESSOR_NOCONA:
ef05d495 826 case PROCESSOR_CORE:
ccc9c027
L		 827 case PROCESSOR_K6:
828 case PROCESSOR_ATHLON:
829 case PROCESSOR_K8:
830 case PROCESSOR_GENERIC64:
050dfa73 831 case PROCESSOR_AMDFAM10:
ccc9c027
L		 832 patt = alt_short_patt;
833 break;
834 case PROCESSOR_I486:
835 case PROCESSOR_PENTIUM:
836 case PROCESSOR_GENERIC32:
837 patt = f32_patt;
838 break;
839 }
840 }
841 else
842 {
843 switch (cpu_arch_tune)
844 {
845 case PROCESSOR_UNKNOWN:
846 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
847 PROCESSOR_UNKNOWN. */
848 abort ();
849 break;
850
851 case PROCESSOR_I486:
852 case PROCESSOR_PENTIUM:
853 case PROCESSOR_PENTIUMPRO:
854 case PROCESSOR_PENTIUM4:
855 case PROCESSOR_NOCONA:
ef05d495 856 case PROCESSOR_CORE:
ccc9c027
L		 857 case PROCESSOR_K6:
858 case PROCESSOR_ATHLON:
859 case PROCESSOR_K8:
050dfa73 860 case PROCESSOR_AMDFAM10:
ccc9c027
L		 861 case PROCESSOR_GENERIC32:
862 /* We use cpu_arch_isa_flags to check if we CAN optimize
863 for Cpu686. */
864 if ((cpu_arch_isa_flags & Cpu686) != 0)
865 patt = alt_short_patt;
866 else
867 patt = f32_patt;
868 break;
ef05d495 869 case PROCESSOR_CORE2:
ccc9c027
L		 870 if ((cpu_arch_isa_flags & Cpu686) != 0)
871 patt = alt_long_patt;
872 else
873 patt = f32_patt;
874 break;
875 case PROCESSOR_GENERIC64:
876 patt = alt_short_patt;
877 break;
878 }
879 }
880
33fef721 881 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 882 patt[count - 1], count);
883 }
33fef721 884 fragP->fr_var = count;
252b5132
RH		 885}
886
252b5132
RH		 887static INLINE unsigned int
888mode_from_disp_size (t)
889 unsigned int t;
890{
3e73aa7c 891 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 892}
893
894static INLINE int
895fits_in_signed_byte (num)
847f7ad4 896 offsetT num;
252b5132
RH		 897{
898 return (num >= -128) && (num <= 127);
47926f60 899}
252b5132
RH		 900
901static INLINE int
902fits_in_unsigned_byte (num)
847f7ad4 903 offsetT num;
252b5132
RH		 904{
905 return (num & 0xff) == num;
47926f60 906}
252b5132
RH		 907
908static INLINE int
909fits_in_unsigned_word (num)
847f7ad4 910 offsetT num;
252b5132
RH		 911{
912 return (num & 0xffff) == num;
47926f60 913}
252b5132
RH		 914
915static INLINE int
916fits_in_signed_word (num)
847f7ad4 917 offsetT num;
252b5132
RH		 918{
919 return (-32768 <= num) && (num <= 32767);
47926f60 920}
3e73aa7c
JH		 921static INLINE int
922fits_in_signed_long (num)
923 offsetT num ATTRIBUTE_UNUSED;
924{
925#ifndef BFD64
926 return 1;
927#else
928 return (!(((offsetT) -1 << 31) & num)
929 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
930#endif
931} /* fits_in_signed_long() */
932static INLINE int
933fits_in_unsigned_long (num)
934 offsetT num ATTRIBUTE_UNUSED;
935{
936#ifndef BFD64
937 return 1;
938#else
939 return (num & (((offsetT) 2 << 31) - 1)) == num;
940#endif
941} /* fits_in_unsigned_long() */
252b5132
RH		 942
943static int
944smallest_imm_type (num)
847f7ad4 945 offsetT num;
252b5132 946{
d32cad65 947 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 948 {
949 /* This code is disabled on the 486 because all the Imm1 forms
950 in the opcode table are slower on the i486. They're the
951 versions with the implicitly specified single-position
952 displacement, which has another syntax if you really want to
953 use that form. */
954 if (num == 1)
3e73aa7c 955 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 956 }
252b5132 957 return (fits_in_signed_byte (num)
3e73aa7c 958 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 959 : fits_in_unsigned_byte (num)
3e73aa7c 960 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 961 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 962 ? (Imm16 | Imm32 | Imm32S | Imm64)
963 : fits_in_signed_long (num)
964 ? (Imm32 | Imm32S | Imm64)
965 : fits_in_unsigned_long (num)
966 ? (Imm32 | Imm64)
967 : Imm64);
47926f60 968}
252b5132 969
847f7ad4
AM		 970static offsetT
971offset_in_range (val, size)
972 offsetT val;
973 int size;
974{
508866be 975 addressT mask;
ba2adb93 976
847f7ad4
AM		 977 switch (size)
978 {
508866be
L		 979 case 1: mask = ((addressT) 1 << 8) - 1; break;
980 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 981 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 982#ifdef BFD64
983 case 8: mask = ((addressT) 2 << 63) - 1; break;
984#endif
47926f60 985 default: abort ();
847f7ad4
AM		 986 }
987
ba2adb93 988 /* If BFD64, sign extend val. */
3e73aa7c
JH		 989 if (!use_rela_relocations)
990 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
991 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 992
47926f60 993 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 994 {
995 char buf1[40], buf2[40];
996
997 sprint_value (buf1, val);
998 sprint_value (buf2, val & mask);
999 as_warn (_("%s shortened to %s"), buf1, buf2);
1000 }
1001 return val & mask;
1002}
1003
252b5132
RH		 1004/* Returns 0 if attempting to add a prefix where one from the same
1005 class already exists, 1 if non rep/repne added, 2 if rep/repne
1006 added. */
1007static int
1008add_prefix (prefix)
1009 unsigned int prefix;
1010{
1011 int ret = 1;
b1905489 1012 unsigned int q;
252b5132 1013
29b0f896
AM		 1014 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1015 && flag_code == CODE_64BIT)
b1905489
JB		 1016 {
1017 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1018 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1019 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1020 ret = 0;
1021 q = REX_PREFIX;
1022 }
3e73aa7c 1023 else
b1905489
JB		 1024 {
1025 switch (prefix)
1026 {
1027 default:
1028 abort ();
1029
1030 case CS_PREFIX_OPCODE:
1031 case DS_PREFIX_OPCODE:
1032 case ES_PREFIX_OPCODE:
1033 case FS_PREFIX_OPCODE:
1034 case GS_PREFIX_OPCODE:
1035 case SS_PREFIX_OPCODE:
1036 q = SEG_PREFIX;
1037 break;
1038
1039 case REPNE_PREFIX_OPCODE:
1040 case REPE_PREFIX_OPCODE:
1041 ret = 2;
1042 /* fall thru */
1043 case LOCK_PREFIX_OPCODE:
1044 q = LOCKREP_PREFIX;
1045 break;
1046
1047 case FWAIT_OPCODE:
1048 q = WAIT_PREFIX;
1049 break;
1050
1051 case ADDR_PREFIX_OPCODE:
1052 q = ADDR_PREFIX;
1053 break;
1054
1055 case DATA_PREFIX_OPCODE:
1056 q = DATA_PREFIX;
1057 break;
1058 }
1059 if (i.prefix[q] != 0)
1060 ret = 0;
1061 }
252b5132 1062
b1905489 1063 if (ret)
252b5132 1064 {
b1905489
JB		 1065 if (!i.prefix[q])
1066 ++i.prefixes;
1067 i.prefix[q] |= prefix;
252b5132 1068 }
b1905489
JB		 1069 else
1070 as_bad (_("same type of prefix used twice"));
252b5132 1071
252b5132
RH		 1072 return ret;
1073}
1074
1075static void
3e73aa7c 1076set_code_flag (value)
e5cb08ac 1077 int value;
eecb386c 1078{
3e73aa7c
JH		 1079 flag_code = value;
1080 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1081 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1082 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1083 {
1084 as_bad (_("64bit mode not supported on this CPU."));
1085 }
1086 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1087 {
1088 as_bad (_("32bit mode not supported on this CPU."));
1089 }
eecb386c
AM		 1090 stackop_size = '\0';
1091}
1092
1093static void
3e73aa7c
JH		 1094set_16bit_gcc_code_flag (new_code_flag)
1095 int new_code_flag;
252b5132 1096{
3e73aa7c
JH		 1097 flag_code = new_code_flag;
1098 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1099 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1100 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1101}
1102
1103static void
1104set_intel_syntax (syntax_flag)
eecb386c 1105 int syntax_flag;
252b5132
RH		 1106{
1107 /* Find out if register prefixing is specified. */
1108 int ask_naked_reg = 0;
1109
1110 SKIP_WHITESPACE ();
29b0f896 1111 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1112 {
1113 char *string = input_line_pointer;
1114 int e = get_symbol_end ();
1115
47926f60 1116 if (strcmp (string, "prefix") == 0)
252b5132 1117 ask_naked_reg = 1;
47926f60 1118 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1119 ask_naked_reg = -1;
1120 else
d0b47220 1121 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1122 *input_line_pointer = e;
1123 }
1124 demand_empty_rest_of_line ();
c3332e24 1125
252b5132
RH		 1126 intel_syntax = syntax_flag;
1127
1128 if (ask_naked_reg == 0)
f86103b7
AM		 1129 allow_naked_reg = (intel_syntax
1130 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1131 else
1132 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1133
1134 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1135 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1136}
1137
e413e4e9
AM		 1138static void
1139set_cpu_arch (dummy)
47926f60 1140 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1141{
47926f60 1142 SKIP_WHITESPACE ();
e413e4e9 1143
29b0f896 1144 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1145 {
1146 char *string = input_line_pointer;
1147 int e = get_symbol_end ();
9103f4f4 1148 unsigned int i;
e413e4e9 1149
9103f4f4 1150 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1151 {
1152 if (strcmp (string, cpu_arch[i].name) == 0)
1153 {
5c6af06e
JB		 1154 if (*string != '.')
1155 {
1156 cpu_arch_name = cpu_arch[i].name;
1157 cpu_sub_arch_name = NULL;
1158 cpu_arch_flags = (cpu_arch[i].flags
1159 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1160 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1161 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1162 if (!cpu_arch_tune_set)
1163 {
1164 cpu_arch_tune = cpu_arch_isa;
1165 cpu_arch_tune_flags = cpu_arch_isa_flags;
1166 }
5c6af06e
JB		 1167 break;
1168 }
1169 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1170 {
1171 cpu_sub_arch_name = cpu_arch[i].name;
1172 cpu_arch_flags |= cpu_arch[i].flags;
1173 }
1174 *input_line_pointer = e;
1175 demand_empty_rest_of_line ();
1176 return;
e413e4e9
AM		 1177 }
1178 }
9103f4f4 1179 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1180 as_bad (_("no such architecture: `%s'"), string);
1181
1182 *input_line_pointer = e;
1183 }
1184 else
1185 as_bad (_("missing cpu architecture"));
1186
fddf5b5b
AM		 1187 no_cond_jump_promotion = 0;
1188 if (*input_line_pointer == ','
29b0f896 1189 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1190 {
1191 char *string = ++input_line_pointer;
1192 int e = get_symbol_end ();
1193
1194 if (strcmp (string, "nojumps") == 0)
1195 no_cond_jump_promotion = 1;
1196 else if (strcmp (string, "jumps") == 0)
1197 ;
1198 else
1199 as_bad (_("no such architecture modifier: `%s'"), string);
1200
1201 *input_line_pointer = e;
1202 }
1203
e413e4e9
AM		 1204 demand_empty_rest_of_line ();
1205}
1206
b9d79e03
JH		 1207unsigned long
1208i386_mach ()
1209{
1210 if (!strcmp (default_arch, "x86_64"))
1211 return bfd_mach_x86_64;
1212 else if (!strcmp (default_arch, "i386"))
1213 return bfd_mach_i386_i386;
1214 else
1215 as_fatal (_("Unknown architecture"));
1216}
b9d79e03 1217\f
252b5132
RH		 1218void
1219md_begin ()
1220{
1221 const char *hash_err;
1222
47926f60 1223 /* Initialize op_hash hash table. */
252b5132
RH		 1224 op_hash = hash_new ();
1225
1226 {
29b0f896
AM		 1227 const template *optab;
1228 templates *core_optab;
252b5132 1229
47926f60
KH		 1230 /* Setup for loop. */
1231 optab = i386_optab;
252b5132
RH		 1232 core_optab = (templates *) xmalloc (sizeof (templates));
1233 core_optab->start = optab;
1234
1235 while (1)
1236 {
1237 ++optab;
1238 if (optab->name == NULL
1239 || strcmp (optab->name, (optab - 1)->name) != 0)
1240 {
1241 /* different name --> ship out current template list;
47926f60 1242 add to hash table; & begin anew. */
252b5132
RH		 1243 core_optab->end = optab;
1244 hash_err = hash_insert (op_hash,
1245 (optab - 1)->name,
1246 (PTR) core_optab);
1247 if (hash_err)
1248 {
252b5132
RH		 1249 as_fatal (_("Internal Error: Can't hash %s: %s"),
1250 (optab - 1)->name,
1251 hash_err);
1252 }
1253 if (optab->name == NULL)
1254 break;
1255 core_optab = (templates *) xmalloc (sizeof (templates));
1256 core_optab->start = optab;
1257 }
1258 }
1259 }
1260
47926f60 1261 /* Initialize reg_hash hash table. */
252b5132
RH		 1262 reg_hash = hash_new ();
1263 {
29b0f896 1264 const reg_entry *regtab;
252b5132
RH		 1265
1266 for (regtab = i386_regtab;
1267 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1268 regtab++)
1269 {
1270 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1271 if (hash_err)
3e73aa7c
JH		 1272 as_fatal (_("Internal Error: Can't hash %s: %s"),
1273 regtab->reg_name,
1274 hash_err);
252b5132
RH		 1275 }
1276 }
1277
47926f60 1278 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1279 {
29b0f896
AM		 1280 int c;
1281 char *p;
252b5132
RH		 1282
1283 for (c = 0; c < 256; c++)
1284 {
3882b010 1285 if (ISDIGIT (c))
252b5132
RH		 1286 {
1287 digit_chars[c] = c;
1288 mnemonic_chars[c] = c;
1289 register_chars[c] = c;
1290 operand_chars[c] = c;
1291 }
3882b010 1292 else if (ISLOWER (c))
252b5132
RH		 1293 {
1294 mnemonic_chars[c] = c;
1295 register_chars[c] = c;
1296 operand_chars[c] = c;
1297 }
3882b010 1298 else if (ISUPPER (c))
252b5132 1299 {
3882b010 1300 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1301 register_chars[c] = mnemonic_chars[c];
1302 operand_chars[c] = c;
1303 }
1304
3882b010 1305 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1306 identifier_chars[c] = c;
1307 else if (c >= 128)
1308 {
1309 identifier_chars[c] = c;
1310 operand_chars[c] = c;
1311 }
1312 }
1313
1314#ifdef LEX_AT
1315 identifier_chars['@'] = '@';
32137342
NC		 1316#endif
1317#ifdef LEX_QM
1318 identifier_chars['?'] = '?';
1319 operand_chars['?'] = '?';
252b5132 1320#endif
252b5132 1321 digit_chars['-'] = '-';
791fe849 1322 mnemonic_chars['-'] = '-';
252b5132
RH		 1323 identifier_chars['_'] = '_';
1324 identifier_chars['.'] = '.';
1325
1326 for (p = operand_special_chars; *p != '\0'; p++)
1327 operand_chars[(unsigned char) *p] = *p;
1328 }
1329
1330#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1331 if (IS_ELF)
252b5132
RH		 1332 {
1333 record_alignment (text_section, 2);
1334 record_alignment (data_section, 2);
1335 record_alignment (bss_section, 2);
1336 }
1337#endif
a4447b93
RH		 1338
1339 if (flag_code == CODE_64BIT)
1340 {
1341 x86_dwarf2_return_column = 16;
1342 x86_cie_data_alignment = -8;
1343 }
1344 else
1345 {
1346 x86_dwarf2_return_column = 8;
1347 x86_cie_data_alignment = -4;
1348 }
252b5132
RH		 1349}
1350
1351void
1352i386_print_statistics (file)
1353 FILE *file;
1354{
1355 hash_print_statistics (file, "i386 opcode", op_hash);
1356 hash_print_statistics (file, "i386 register", reg_hash);
1357}
1358\f
252b5132
RH		 1359#ifdef DEBUG386
1360
ce8a8b2f 1361/* Debugging routines for md_assemble. */
252b5132
RH		 1362static void pi PARAMS ((char *, i386_insn *));
1363static void pte PARAMS ((template *));
1364static void pt PARAMS ((unsigned int));
1365static void pe PARAMS ((expressionS *));
1366static void ps PARAMS ((symbolS *));
1367
1368static void
1369pi (line, x)
1370 char *line;
1371 i386_insn *x;
1372{
09f131f2 1373 unsigned int i;
252b5132
RH		 1374
1375 fprintf (stdout, "%s: template ", line);
1376 pte (&x->tm);
09f131f2
JH		 1377 fprintf (stdout, " address: base %s index %s scale %x\n",
1378 x->base_reg ? x->base_reg->reg_name : "none",
1379 x->index_reg ? x->index_reg->reg_name : "none",
1380 x->log2_scale_factor);
1381 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1382 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1383 fprintf (stdout, " sib: base %x index %x scale %x\n",
1384 x->sib.base, x->sib.index, x->sib.scale);
1385 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1386 (x->rex & REX_MODE64) != 0,
1387 (x->rex & REX_EXTX) != 0,
1388 (x->rex & REX_EXTY) != 0,
1389 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1390 for (i = 0; i < x->operands; i++)
1391 {
1392 fprintf (stdout, " #%d: ", i + 1);
1393 pt (x->types[i]);
1394 fprintf (stdout, "\n");
1395 if (x->types[i]
3f4438ab 1396 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1397 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1398 if (x->types[i] & Imm)
520dc8e8 1399 pe (x->op[i].imms);
252b5132 1400 if (x->types[i] & Disp)
520dc8e8 1401 pe (x->op[i].disps);
252b5132
RH		 1402 }
1403}
1404
1405static void
1406pte (t)
1407 template *t;
1408{
09f131f2 1409 unsigned int i;
252b5132 1410 fprintf (stdout, " %d operands ", t->operands);
47926f60 1411 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1412 if (t->extension_opcode != None)
1413 fprintf (stdout, "ext %x ", t->extension_opcode);
1414 if (t->opcode_modifier & D)
1415 fprintf (stdout, "D");
1416 if (t->opcode_modifier & W)
1417 fprintf (stdout, "W");
1418 fprintf (stdout, "\n");
1419 for (i = 0; i < t->operands; i++)
1420 {
1421 fprintf (stdout, " #%d type ", i + 1);
1422 pt (t->operand_types[i]);
1423 fprintf (stdout, "\n");
1424 }
1425}
1426
1427static void
1428pe (e)
1429 expressionS *e;
1430{
24eab124 1431 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1432 fprintf (stdout, " add_number %ld (%lx)\n",
1433 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1434 if (e->X_add_symbol)
1435 {
1436 fprintf (stdout, " add_symbol ");
1437 ps (e->X_add_symbol);
1438 fprintf (stdout, "\n");
1439 }
1440 if (e->X_op_symbol)
1441 {
1442 fprintf (stdout, " op_symbol ");
1443 ps (e->X_op_symbol);
1444 fprintf (stdout, "\n");
1445 }
1446}
1447
1448static void
1449ps (s)
1450 symbolS *s;
1451{
1452 fprintf (stdout, "%s type %s%s",
1453 S_GET_NAME (s),
1454 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1455 segment_name (S_GET_SEGMENT (s)));
1456}
1457
7b81dfbb 1458static struct type_name
252b5132
RH		 1459 {
1460 unsigned int mask;
1461 char *tname;
1462 }
7b81dfbb 1463const type_names[] =
252b5132
RH		 1464{
1465 { Reg8, "r8" },
1466 { Reg16, "r16" },
1467 { Reg32, "r32" },
09f131f2 1468 { Reg64, "r64" },
252b5132
RH		 1469 { Imm8, "i8" },
1470 { Imm8S, "i8s" },
1471 { Imm16, "i16" },
1472 { Imm32, "i32" },
09f131f2
JH		 1473 { Imm32S, "i32s" },
1474 { Imm64, "i64" },
252b5132
RH		 1475 { Imm1, "i1" },
1476 { BaseIndex, "BaseIndex" },
1477 { Disp8, "d8" },
1478 { Disp16, "d16" },
1479 { Disp32, "d32" },
09f131f2
JH		 1480 { Disp32S, "d32s" },
1481 { Disp64, "d64" },
252b5132
RH		 1482 { InOutPortReg, "InOutPortReg" },
1483 { ShiftCount, "ShiftCount" },
1484 { Control, "control reg" },
1485 { Test, "test reg" },
1486 { Debug, "debug reg" },
1487 { FloatReg, "FReg" },
1488 { FloatAcc, "FAcc" },
1489 { SReg2, "SReg2" },
1490 { SReg3, "SReg3" },
1491 { Acc, "Acc" },
1492 { JumpAbsolute, "Jump Absolute" },
1493 { RegMMX, "rMMX" },
3f4438ab 1494 { RegXMM, "rXMM" },
252b5132
RH		 1495 { EsSeg, "es" },
1496 { 0, "" }
1497};
1498
1499static void
1500pt (t)
1501 unsigned int t;
1502{
29b0f896 1503 const struct type_name *ty;
252b5132 1504
09f131f2
JH		 1505 for (ty = type_names; ty->mask; ty++)
1506 if (t & ty->mask)
1507 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1508 fflush (stdout);
1509}
1510
1511#endif /* DEBUG386 */
1512\f
252b5132 1513static bfd_reloc_code_real_type
3956db08 1514reloc (unsigned int size,
64e74474
AM		 1515 int pcrel,
1516 int sign,
1517 bfd_reloc_code_real_type other)
252b5132 1518{
47926f60 1519 if (other != NO_RELOC)
3956db08
JB		 1520 {
1521 reloc_howto_type *reloc;
1522
1523 if (size == 8)
1524 switch (other)
1525 {
64e74474
AM		 1526 case BFD_RELOC_X86_64_GOT32:
1527 return BFD_RELOC_X86_64_GOT64;
1528 break;
1529 case BFD_RELOC_X86_64_PLTOFF64:
1530 return BFD_RELOC_X86_64_PLTOFF64;
1531 break;
1532 case BFD_RELOC_X86_64_GOTPC32:
1533 other = BFD_RELOC_X86_64_GOTPC64;
1534 break;
1535 case BFD_RELOC_X86_64_GOTPCREL:
1536 other = BFD_RELOC_X86_64_GOTPCREL64;
1537 break;
1538 case BFD_RELOC_X86_64_TPOFF32:
1539 other = BFD_RELOC_X86_64_TPOFF64;
1540 break;
1541 case BFD_RELOC_X86_64_DTPOFF32:
1542 other = BFD_RELOC_X86_64_DTPOFF64;
1543 break;
1544 default:
1545 break;
3956db08 1546 }
e05278af
JB		 1547
1548 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1549 if (size == 4 && flag_code != CODE_64BIT)
1550 sign = -1;
1551
3956db08
JB		 1552 reloc = bfd_reloc_type_lookup (stdoutput, other);
1553 if (!reloc)
1554 as_bad (_("unknown relocation (%u)"), other);
1555 else if (size != bfd_get_reloc_size (reloc))
1556 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1557 bfd_get_reloc_size (reloc),
1558 size);
1559 else if (pcrel && !reloc->pc_relative)
1560 as_bad (_("non-pc-relative relocation for pc-relative field"));
1561 else if ((reloc->complain_on_overflow == complain_overflow_signed
1562 && !sign)
1563 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1564 && sign > 0))
3956db08
JB		 1565 as_bad (_("relocated field and relocation type differ in signedness"));
1566 else
1567 return other;
1568 return NO_RELOC;
1569 }
252b5132
RH		 1570
1571 if (pcrel)
1572 {
3e73aa7c 1573 if (!sign)
3956db08 1574 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1575 switch (size)
1576 {
1577 case 1: return BFD_RELOC_8_PCREL;
1578 case 2: return BFD_RELOC_16_PCREL;
1579 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1580 case 8: return BFD_RELOC_64_PCREL;
252b5132 1581 }
3956db08 1582 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1583 }
1584 else
1585 {
3956db08 1586 if (sign > 0)
e5cb08ac 1587 switch (size)
3e73aa7c
JH		 1588 {
1589 case 4: return BFD_RELOC_X86_64_32S;
1590 }
1591 else
1592 switch (size)
1593 {
1594 case 1: return BFD_RELOC_8;
1595 case 2: return BFD_RELOC_16;
1596 case 4: return BFD_RELOC_32;
1597 case 8: return BFD_RELOC_64;
1598 }
3956db08
JB		 1599 as_bad (_("cannot do %s %u byte relocation"),
1600 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1601 }
1602
bfb32b52 1603 abort ();
252b5132
RH		 1604 return BFD_RELOC_NONE;
1605}
1606
47926f60
KH		 1607/* Here we decide which fixups can be adjusted to make them relative to
1608 the beginning of the section instead of the symbol. Basically we need
1609 to make sure that the dynamic relocations are done correctly, so in
1610 some cases we force the original symbol to be used. */
1611
252b5132 1612int
c0c949c7 1613tc_i386_fix_adjustable (fixP)
31312f95 1614 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1615{
6d249963 1616#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1617 if (!IS_ELF)
31312f95
AM		 1618 return 1;
1619
a161fe53
AM		 1620 /* Don't adjust pc-relative references to merge sections in 64-bit
1621 mode. */
1622 if (use_rela_relocations
1623 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1624 && fixP->fx_pcrel)
252b5132 1625 return 0;
31312f95 1626
8d01d9a9
AJ		 1627 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1628 and changed later by validate_fix. */
1629 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1630 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1631 return 0;
1632
ce8a8b2f 1633 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1634 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1635 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1636 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1639 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1647 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1648 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1652 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1653 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1654 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1655 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1656 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1658 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1659 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1660 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1661 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1662 return 0;
31312f95 1663#endif
252b5132
RH		 1664 return 1;
1665}
252b5132 1666
29b0f896 1667static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1668
1669static int
252b5132 1670intel_float_operand (mnemonic)
29b0f896 1671 const char *mnemonic;
252b5132 1672{
9306ca4a
JB		 1673 /* Note that the value returned is meaningful only for opcodes with (memory)
1674 operands, hence the code here is free to improperly handle opcodes that
1675 have no operands (for better performance and smaller code). */
1676
1677 if (mnemonic[0] != 'f')
1678 return 0; /* non-math */
1679
1680 switch (mnemonic[1])
1681 {
1682 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1683 the fs segment override prefix not currently handled because no
1684 call path can make opcodes without operands get here */
1685 case 'i':
1686 return 2 /* integer op */;
1687 case 'l':
1688 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1689 return 3; /* fldcw/fldenv */
1690 break;
1691 case 'n':
1692 if (mnemonic[2] != 'o' /* fnop */)
1693 return 3; /* non-waiting control op */
1694 break;
1695 case 'r':
1696 if (mnemonic[2] == 's')
1697 return 3; /* frstor/frstpm */
1698 break;
1699 case 's':
1700 if (mnemonic[2] == 'a')
1701 return 3; /* fsave */
1702 if (mnemonic[2] == 't')
1703 {
1704 switch (mnemonic[3])
1705 {
1706 case 'c': /* fstcw */
1707 case 'd': /* fstdw */
1708 case 'e': /* fstenv */
1709 case 's': /* fsts[gw] */
1710 return 3;
1711 }
1712 }
1713 break;
1714 case 'x':
1715 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1716 return 0; /* fxsave/fxrstor are not really math ops */
1717 break;
1718 }
252b5132 1719
9306ca4a 1720 return 1;
252b5132
RH		 1721}
1722
1723/* This is the guts of the machine-dependent assembler. LINE points to a
1724 machine dependent instruction. This function is supposed to emit
1725 the frags/bytes it assembles to. */
1726
1727void
1728md_assemble (line)
1729 char *line;
1730{
252b5132 1731 int j;
252b5132
RH		 1732 char mnemonic[MAX_MNEM_SIZE];
1733
47926f60 1734 /* Initialize globals. */
252b5132
RH		 1735 memset (&i, '\0', sizeof (i));
1736 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1737 i.reloc[j] = NO_RELOC;
252b5132
RH		 1738 memset (disp_expressions, '\0', sizeof (disp_expressions));
1739 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1740 save_stack_p = save_stack;
252b5132
RH		 1741
1742 /* First parse an instruction mnemonic & call i386_operand for the operands.
1743 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1744 start of a (possibly prefixed) mnemonic. */
252b5132 1745
29b0f896
AM		 1746 line = parse_insn (line, mnemonic);
1747 if (line == NULL)
1748 return;
252b5132 1749
29b0f896
AM		 1750 line = parse_operands (line, mnemonic);
1751 if (line == NULL)
1752 return;
252b5132 1753
050dfa73
MM		 1754 /* The order of the immediates should be reversed
1755 for 2 immediates extrq and insertq instructions */
1756 if ((i.imm_operands == 2) &&
1757 ((strcmp (mnemonic, "extrq") == 0)
1758 || (strcmp (mnemonic, "insertq") == 0)))
1759 {
1760 swap_imm_operands ();
1761 /* "extrq" and insertq" are the only two instructions whose operands
1762 have to be reversed even though they have two immediate operands.
1763 */
1764 if (intel_syntax)
1765 swap_operands ();
1766 }
1767
29b0f896
AM		 1768 /* Now we've parsed the mnemonic into a set of templates, and have the
1769 operands at hand. */
1770
1771 /* All intel opcodes have reversed operands except for "bound" and
1772 "enter". We also don't reverse intersegment "jmp" and "call"
1773 instructions with 2 immediate operands so that the immediate segment
050dfa73 1774 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1775 if (intel_syntax && i.operands > 1
1776 && (strcmp (mnemonic, "bound") != 0)
30123838 1777 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1778 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1779 swap_operands ();
1780
1781 if (i.imm_operands)
1782 optimize_imm ();
1783
b300c311
L		 1784 /* Don't optimize displacement for movabs since it only takes 64bit
1785 displacement. */
1786 if (i.disp_operands
1787 && (flag_code != CODE_64BIT
1788 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1789 optimize_disp ();
1790
1791 /* Next, we find a template that matches the given insn,
1792 making sure the overlap of the given operands types is consistent
1793 with the template operand types. */
252b5132 1794
29b0f896
AM		 1795 if (!match_template ())
1796 return;
252b5132 1797
cd61ebfe
AM		 1798 if (intel_syntax)
1799 {
1800 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1801 if (SYSV386_COMPAT
1802 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1803 i.tm.base_opcode ^= FloatR;
1804
1805 /* Zap movzx and movsx suffix. The suffix may have been set from
1806 "word ptr" or "byte ptr" on the source operand, but we'll use
1807 the suffix later to choose the destination register. */
1808 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1809 {
1810 if (i.reg_operands < 2
1811 && !i.suffix
1812 && (~i.tm.opcode_modifier
1813 & (No_bSuf
1814 | No_wSuf
1815 | No_lSuf
1816 | No_sSuf
1817 | No_xSuf
1818 | No_qSuf)))
1819 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1820
1821 i.suffix = 0;
1822 }
cd61ebfe 1823 }
24eab124 1824
29b0f896
AM		 1825 if (i.tm.opcode_modifier & FWait)
1826 if (!add_prefix (FWAIT_OPCODE))
1827 return;
252b5132 1828
29b0f896
AM		 1829 /* Check string instruction segment overrides. */
1830 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1831 {
1832 if (!check_string ())
5dd0794d 1833 return;
29b0f896 1834 }
5dd0794d 1835
29b0f896
AM		 1836 if (!process_suffix ())
1837 return;
e413e4e9 1838
29b0f896
AM		 1839 /* Make still unresolved immediate matches conform to size of immediate
1840 given in i.suffix. */
1841 if (!finalize_imm ())
1842 return;
252b5132 1843
29b0f896
AM		 1844 if (i.types[0] & Imm1)
1845 i.imm_operands = 0; /* kludge for shift insns. */
1846 if (i.types[0] & ImplicitRegister)
1847 i.reg_operands--;
1848 if (i.types[1] & ImplicitRegister)
1849 i.reg_operands--;
1850 if (i.types[2] & ImplicitRegister)
1851 i.reg_operands--;
252b5132 1852
29b0f896
AM		 1853 if (i.tm.opcode_modifier & ImmExt)
1854 {
02fc3089
L		 1855 expressionS *exp;
1856
b7d9ef37 1857 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1858 {
b7d9ef37 1859 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1860 operands with an opcode suffix which is coded in the same
1861 place as an 8-bit immediate field would be. Here we check
1862 those operands and remove them afterwards. */
1863 unsigned int x;
1864
a4622f40 1865 for (x = 0; x < i.operands; x++)
ca164297
L		 1866 if (i.op[x].regs->reg_num != x)
1867 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1868 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1869 i.operands = 0;
1870 }
1871
29b0f896
AM		 1872 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1873 opcode suffix which is coded in the same place as an 8-bit
1874 immediate field would be. Here we fake an 8-bit immediate
1875 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1876
29b0f896 1877 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1878
29b0f896
AM		 1879 exp = &im_expressions[i.imm_operands++];
1880 i.op[i.operands].imms = exp;
1881 i.types[i.operands++] = Imm8;
1882 exp->X_op = O_constant;
1883 exp->X_add_number = i.tm.extension_opcode;
1884 i.tm.extension_opcode = None;
1885 }
252b5132 1886
29b0f896
AM		 1887 /* For insns with operands there are more diddles to do to the opcode. */
1888 if (i.operands)
1889 {
1890 if (!process_operands ())
1891 return;
1892 }
1893 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1894 {
1895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1896 as_warn (_("translating to `%sp'"), i.tm.name);
1897 }
252b5132 1898
29b0f896
AM		 1899 /* Handle conversion of 'int $3' --> special int3 insn. */
1900 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1901 {
1902 i.tm.base_opcode = INT3_OPCODE;
1903 i.imm_operands = 0;
1904 }
252b5132 1905
29b0f896
AM		 1906 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1907 && i.op[0].disps->X_op == O_constant)
1908 {
1909 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1910 the absolute address given by the constant. Since ix86 jumps and
1911 calls are pc relative, we need to generate a reloc. */
1912 i.op[0].disps->X_add_symbol = &abs_symbol;
1913 i.op[0].disps->X_op = O_symbol;
1914 }
252b5132 1915
29b0f896
AM		 1916 if ((i.tm.opcode_modifier & Rex64) != 0)
1917 i.rex |= REX_MODE64;
252b5132 1918
29b0f896
AM		 1919 /* For 8 bit registers we need an empty rex prefix. Also if the
1920 instruction already has a prefix, we need to convert old
1921 registers to new ones. */
773f551c 1922
29b0f896
AM		 1923 if (((i.types[0] & Reg8) != 0
1924 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1925 || ((i.types[1] & Reg8) != 0
1926 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1927 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1928 && i.rex != 0))
1929 {
1930 int x;
726c5dcd 1931
29b0f896
AM		 1932 i.rex |= REX_OPCODE;
1933 for (x = 0; x < 2; x++)
1934 {
1935 /* Look for 8 bit operand that uses old registers. */
1936 if ((i.types[x] & Reg8) != 0
1937 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1938 {
29b0f896
AM		 1939 /* In case it is "hi" register, give up. */
1940 if (i.op[x].regs->reg_num > 3)
0477af35 1941 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1942 i.op[x].regs->reg_name);
773f551c 1943
29b0f896
AM		 1944 /* Otherwise it is equivalent to the extended register.
1945 Since the encoding doesn't change this is merely
1946 cosmetic cleanup for debug output. */
1947
1948 i.op[x].regs = i.op[x].regs + 8;
773f551c 1949 }
29b0f896
AM		 1950 }
1951 }
773f551c 1952
29b0f896
AM		 1953 if (i.rex != 0)
1954 add_prefix (REX_OPCODE | i.rex);
1955
1956 /* We are ready to output the insn. */
1957 output_insn ();
1958}
1959
1960static char *
1961parse_insn (line, mnemonic)
1962 char *line;
1963 char *mnemonic;
1964{
1965 char *l = line;
1966 char *token_start = l;
1967 char *mnem_p;
5c6af06e
JB		 1968 int supported;
1969 const template *t;
29b0f896
AM		 1970
1971 /* Non-zero if we found a prefix only acceptable with string insns. */
1972 const char *expecting_string_instruction = NULL;
45288df1 1973
29b0f896
AM		 1974 while (1)
1975 {
1976 mnem_p = mnemonic;
1977 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1978 {
1979 mnem_p++;
1980 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1981 {
29b0f896
AM		 1982 as_bad (_("no such instruction: `%s'"), token_start);
1983 return NULL;
1984 }
1985 l++;
1986 }
1987 if (!is_space_char (*l)
1988 && *l != END_OF_INSN
e44823cf
JB		 1989 && (intel_syntax
1990 || (*l != PREFIX_SEPARATOR
1991 && *l != ',')))
29b0f896
AM		 1992 {
1993 as_bad (_("invalid character %s in mnemonic"),
1994 output_invalid (*l));
1995 return NULL;
1996 }
1997 if (token_start == l)
1998 {
e44823cf 1999 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2000 as_bad (_("expecting prefix; got nothing"));
2001 else
2002 as_bad (_("expecting mnemonic; got nothing"));
2003 return NULL;
2004 }
45288df1 2005
29b0f896
AM		 2006 /* Look up instruction (or prefix) via hash table. */
2007 current_templates = hash_find (op_hash, mnemonic);
47926f60 2008
29b0f896
AM		 2009 if (*l != END_OF_INSN
2010 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2011 && current_templates
2012 && (current_templates->start->opcode_modifier & IsPrefix))
2013 {
2dd88dca
JB		 2014 if (current_templates->start->cpu_flags
2015 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2016 {
2017 as_bad ((flag_code != CODE_64BIT
2018 ? _("`%s' is only supported in 64-bit mode")
2019 : _("`%s' is not supported in 64-bit mode")),
2020 current_templates->start->name);
2021 return NULL;
2022 }
29b0f896
AM		 2023 /* If we are in 16-bit mode, do not allow addr16 or data16.
2024 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2025 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2026 && flag_code != CODE_64BIT
2027 && (((current_templates->start->opcode_modifier & Size32) != 0)
2028 ^ (flag_code == CODE_16BIT)))
2029 {
2030 as_bad (_("redundant %s prefix"),
2031 current_templates->start->name);
2032 return NULL;
45288df1 2033 }
29b0f896
AM		 2034 /* Add prefix, checking for repeated prefixes. */
2035 switch (add_prefix (current_templates->start->base_opcode))
2036 {
2037 case 0:
2038 return NULL;
2039 case 2:
2040 expecting_string_instruction = current_templates->start->name;
2041 break;
2042 }
2043 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2044 token_start = ++l;
2045 }
2046 else
2047 break;
2048 }
45288df1 2049
29b0f896
AM		 2050 if (!current_templates)
2051 {
2052 /* See if we can get a match by trimming off a suffix. */
2053 switch (mnem_p[-1])
2054 {
2055 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2056 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2057 i.suffix = SHORT_MNEM_SUFFIX;
2058 else
29b0f896
AM		 2059 case BYTE_MNEM_SUFFIX:
2060 case QWORD_MNEM_SUFFIX:
2061 i.suffix = mnem_p[-1];
2062 mnem_p[-1] = '\0';
2063 current_templates = hash_find (op_hash, mnemonic);
2064 break;
2065 case SHORT_MNEM_SUFFIX:
2066 case LONG_MNEM_SUFFIX:
2067 if (!intel_syntax)
2068 {
2069 i.suffix = mnem_p[-1];
2070 mnem_p[-1] = '\0';
2071 current_templates = hash_find (op_hash, mnemonic);
2072 }
2073 break;
252b5132 2074
29b0f896
AM		 2075 /* Intel Syntax. */
2076 case 'd':
2077 if (intel_syntax)
2078 {
9306ca4a 2079 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2080 i.suffix = SHORT_MNEM_SUFFIX;
2081 else
2082 i.suffix = LONG_MNEM_SUFFIX;
2083 mnem_p[-1] = '\0';
2084 current_templates = hash_find (op_hash, mnemonic);
2085 }
2086 break;
2087 }
2088 if (!current_templates)
2089 {
2090 as_bad (_("no such instruction: `%s'"), token_start);
2091 return NULL;
2092 }
2093 }
252b5132 2094
29b0f896
AM		 2095 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2096 {
2097 /* Check for a branch hint. We allow ",pt" and ",pn" for
2098 predict taken and predict not taken respectively.
2099 I'm not sure that branch hints actually do anything on loop
2100 and jcxz insns (JumpByte) for current Pentium4 chips. They
2101 may work in the future and it doesn't hurt to accept them
2102 now. */
2103 if (l[0] == ',' && l[1] == 'p')
2104 {
2105 if (l[2] == 't')
2106 {
2107 if (!add_prefix (DS_PREFIX_OPCODE))
2108 return NULL;
2109 l += 3;
2110 }
2111 else if (l[2] == 'n')
2112 {
2113 if (!add_prefix (CS_PREFIX_OPCODE))
2114 return NULL;
2115 l += 3;
2116 }
2117 }
2118 }
2119 /* Any other comma loses. */
2120 if (*l == ',')
2121 {
2122 as_bad (_("invalid character %s in mnemonic"),
2123 output_invalid (*l));
2124 return NULL;
2125 }
252b5132 2126
29b0f896 2127 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2128 supported = 0;
2129 for (t = current_templates->start; t < current_templates->end; ++t)
2130 {
2131 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2132 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2133 supported |= 1;
5c6af06e 2134 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2135 supported |= 2;
5c6af06e
JB		 2136 }
2137 if (!(supported & 2))
2138 {
2139 as_bad (flag_code == CODE_64BIT
2140 ? _("`%s' is not supported in 64-bit mode")
2141 : _("`%s' is only supported in 64-bit mode"),
2142 current_templates->start->name);
2143 return NULL;
2144 }
2145 if (!(supported & 1))
29b0f896 2146 {
5c6af06e
JB		 2147 as_warn (_("`%s' is not supported on `%s%s'"),
2148 current_templates->start->name,
2149 cpu_arch_name,
2150 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2151 }
2152 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2153 {
2154 as_warn (_("use .code16 to ensure correct addressing mode"));
2155 }
252b5132 2156
29b0f896 2157 /* Check for rep/repne without a string instruction. */
f41bbced 2158 if (expecting_string_instruction)
29b0f896 2159 {
f41bbced
JB		 2160 static templates override;
2161
2162 for (t = current_templates->start; t < current_templates->end; ++t)
2163 if (t->opcode_modifier & IsString)
2164 break;
2165 if (t >= current_templates->end)
2166 {
2167 as_bad (_("expecting string instruction after `%s'"),
64e74474 2168 expecting_string_instruction);
f41bbced
JB		 2169 return NULL;
2170 }
2171 for (override.start = t; t < current_templates->end; ++t)
2172 if (!(t->opcode_modifier & IsString))
2173 break;
2174 override.end = t;
2175 current_templates = &override;
29b0f896 2176 }
252b5132 2177
29b0f896
AM		 2178 return l;
2179}
252b5132 2180
29b0f896
AM		 2181static char *
2182parse_operands (l, mnemonic)
2183 char *l;
2184 const char *mnemonic;
2185{
2186 char *token_start;
3138f287 2187
29b0f896
AM		 2188 /* 1 if operand is pending after ','. */
2189 unsigned int expecting_operand = 0;
252b5132 2190
29b0f896
AM		 2191 /* Non-zero if operand parens not balanced. */
2192 unsigned int paren_not_balanced;
2193
2194 while (*l != END_OF_INSN)
2195 {
2196 /* Skip optional white space before operand. */
2197 if (is_space_char (*l))
2198 ++l;
2199 if (!is_operand_char (*l) && *l != END_OF_INSN)
2200 {
2201 as_bad (_("invalid character %s before operand %d"),
2202 output_invalid (*l),
2203 i.operands + 1);
2204 return NULL;
2205 }
2206 token_start = l; /* after white space */
2207 paren_not_balanced = 0;
2208 while (paren_not_balanced || *l != ',')
2209 {
2210 if (*l == END_OF_INSN)
2211 {
2212 if (paren_not_balanced)
2213 {
2214 if (!intel_syntax)
2215 as_bad (_("unbalanced parenthesis in operand %d."),
2216 i.operands + 1);
2217 else
2218 as_bad (_("unbalanced brackets in operand %d."),
2219 i.operands + 1);
2220 return NULL;
2221 }
2222 else
2223 break; /* we are done */
2224 }
2225 else if (!is_operand_char (*l) && !is_space_char (*l))
2226 {
2227 as_bad (_("invalid character %s in operand %d"),
2228 output_invalid (*l),
2229 i.operands + 1);
2230 return NULL;
2231 }
2232 if (!intel_syntax)
2233 {
2234 if (*l == '(')
2235 ++paren_not_balanced;
2236 if (*l == ')')
2237 --paren_not_balanced;
2238 }
2239 else
2240 {
2241 if (*l == '[')
2242 ++paren_not_balanced;
2243 if (*l == ']')
2244 --paren_not_balanced;
2245 }
2246 l++;
2247 }
2248 if (l != token_start)
2249 { /* Yes, we've read in another operand. */
2250 unsigned int operand_ok;
2251 this_operand = i.operands++;
2252 if (i.operands > MAX_OPERANDS)
2253 {
2254 as_bad (_("spurious operands; (%d operands/instruction max)"),
2255 MAX_OPERANDS);
2256 return NULL;
2257 }
2258 /* Now parse operand adding info to 'i' as we go along. */
2259 END_STRING_AND_SAVE (l);
2260
2261 if (intel_syntax)
2262 operand_ok =
2263 i386_intel_operand (token_start,
2264 intel_float_operand (mnemonic));
2265 else
2266 operand_ok = i386_operand (token_start);
2267
2268 RESTORE_END_STRING (l);
2269 if (!operand_ok)
2270 return NULL;
2271 }
2272 else
2273 {
2274 if (expecting_operand)
2275 {
2276 expecting_operand_after_comma:
2277 as_bad (_("expecting operand after ','; got nothing"));
2278 return NULL;
2279 }
2280 if (*l == ',')
2281 {
2282 as_bad (_("expecting operand before ','; got nothing"));
2283 return NULL;
2284 }
2285 }
7f3f1ea2 2286
29b0f896
AM		 2287 /* Now *l must be either ',' or END_OF_INSN. */
2288 if (*l == ',')
2289 {
2290 if (*++l == END_OF_INSN)
2291 {
2292 /* Just skip it, if it's \n complain. */
2293 goto expecting_operand_after_comma;
2294 }
2295 expecting_operand = 1;
2296 }
2297 }
2298 return l;
2299}
7f3f1ea2 2300
050dfa73
MM		 2301static void
2302swap_imm_operands ()
2303{
2304 union i386_op temp_op;
2305 unsigned int temp_type;
2306 enum bfd_reloc_code_real temp_reloc;
2307 int xchg1 = 0;
2308 int xchg2 = 1;
2309
2310 temp_type = i.types[xchg2];
2311 i.types[xchg2] = i.types[xchg1];
2312 i.types[xchg1] = temp_type;
2313 temp_op = i.op[xchg2];
2314 i.op[xchg2] = i.op[xchg1];
2315 i.op[xchg1] = temp_op;
2316 temp_reloc = i.reloc[xchg2];
2317 i.reloc[xchg2] = i.reloc[xchg1];
2318 i.reloc[xchg1] = temp_reloc;
2319}
2320
2321
29b0f896
AM		 2322static void
2323swap_operands ()
2324{
2325 union i386_op temp_op;
2326 unsigned int temp_type;
f86103b7 2327 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2328 int xchg1 = 0;
2329 int xchg2 = 0;
252b5132 2330
050dfa73
MM		 2331 if (i.operands == 4)
2332 /* There will be two exchanges in a 4 operand instruction.
2333 First exchange is the done inside this block.(1st and 4rth operand)
2334 The next exchange is done outside this block.(2nd and 3rd operand) */
2335 {
2336 xchg1 = 0;
2337 xchg2 = 3;
2338 temp_type = i.types[xchg2];
2339 i.types[xchg2] = i.types[xchg1];
2340 i.types[xchg1] = temp_type;
2341 temp_op = i.op[xchg2];
2342 i.op[xchg2] = i.op[xchg1];
2343 i.op[xchg1] = temp_op;
2344 temp_reloc = i.reloc[xchg2];
2345 i.reloc[xchg2] = i.reloc[xchg1];
2346 i.reloc[xchg1] = temp_reloc;
2347 xchg1 = 1;
2348 xchg2 = 2;
2349 }
2350
29b0f896
AM		 2351 if (i.operands == 2)
2352 {
2353 xchg1 = 0;
2354 xchg2 = 1;
2355 }
2356 else if (i.operands == 3)
2357 {
2358 xchg1 = 0;
2359 xchg2 = 2;
2360 }
2361 temp_type = i.types[xchg2];
2362 i.types[xchg2] = i.types[xchg1];
2363 i.types[xchg1] = temp_type;
2364 temp_op = i.op[xchg2];
2365 i.op[xchg2] = i.op[xchg1];
2366 i.op[xchg1] = temp_op;
2367 temp_reloc = i.reloc[xchg2];
2368 i.reloc[xchg2] = i.reloc[xchg1];
2369 i.reloc[xchg1] = temp_reloc;
2370
2371 if (i.mem_operands == 2)
2372 {
2373 const seg_entry *temp_seg;
2374 temp_seg = i.seg[0];
2375 i.seg[0] = i.seg[1];
2376 i.seg[1] = temp_seg;
2377 }
2378}
252b5132 2379
29b0f896
AM		 2380/* Try to ensure constant immediates are represented in the smallest
2381 opcode possible. */
2382static void
2383optimize_imm ()
2384{
2385 char guess_suffix = 0;
2386 int op;
252b5132 2387
29b0f896
AM		 2388 if (i.suffix)
2389 guess_suffix = i.suffix;
2390 else if (i.reg_operands)
2391 {
2392 /* Figure out a suffix from the last register operand specified.
2393 We can't do this properly yet, ie. excluding InOutPortReg,
2394 but the following works for instructions with immediates.
2395 In any case, we can't set i.suffix yet. */
2396 for (op = i.operands; --op >= 0;)
2397 if (i.types[op] & Reg)
252b5132 2398 {
29b0f896
AM		 2399 if (i.types[op] & Reg8)
2400 guess_suffix = BYTE_MNEM_SUFFIX;
2401 else if (i.types[op] & Reg16)
2402 guess_suffix = WORD_MNEM_SUFFIX;
2403 else if (i.types[op] & Reg32)
2404 guess_suffix = LONG_MNEM_SUFFIX;
2405 else if (i.types[op] & Reg64)
2406 guess_suffix = QWORD_MNEM_SUFFIX;
2407 break;
252b5132 2408 }
29b0f896
AM		 2409 }
2410 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2411 guess_suffix = WORD_MNEM_SUFFIX;
2412
2413 for (op = i.operands; --op >= 0;)
2414 if (i.types[op] & Imm)
2415 {
2416 switch (i.op[op].imms->X_op)
252b5132 2417 {
29b0f896
AM		 2418 case O_constant:
2419 /* If a suffix is given, this operand may be shortened. */
2420 switch (guess_suffix)
252b5132 2421 {
29b0f896
AM		 2422 case LONG_MNEM_SUFFIX:
2423 i.types[op] |= Imm32 | Imm64;
2424 break;
2425 case WORD_MNEM_SUFFIX:
2426 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2427 break;
2428 case BYTE_MNEM_SUFFIX:
2429 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2430 break;
252b5132 2431 }
252b5132 2432
29b0f896
AM		 2433 /* If this operand is at most 16 bits, convert it
2434 to a signed 16 bit number before trying to see
2435 whether it will fit in an even smaller size.
2436 This allows a 16-bit operand such as $0xffe0 to
2437 be recognised as within Imm8S range. */
2438 if ((i.types[op] & Imm16)
2439 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2440 {
29b0f896
AM		 2441 i.op[op].imms->X_add_number =
2442 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2443 }
2444 if ((i.types[op] & Imm32)
2445 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2446 == 0))
2447 {
2448 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2449 ^ ((offsetT) 1 << 31))
2450 - ((offsetT) 1 << 31));
2451 }
2452 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2453
29b0f896
AM		 2454 /* We must avoid matching of Imm32 templates when 64bit
2455 only immediate is available. */
2456 if (guess_suffix == QWORD_MNEM_SUFFIX)
2457 i.types[op] &= ~Imm32;
2458 break;
252b5132 2459
29b0f896
AM		 2460 case O_absent:
2461 case O_register:
2462 abort ();
2463
2464 /* Symbols and expressions. */
2465 default:
9cd96992
JB		 2466 /* Convert symbolic operand to proper sizes for matching, but don't
2467 prevent matching a set of insns that only supports sizes other
2468 than those matching the insn suffix. */
2469 {
2470 unsigned int mask, allowed = 0;
2471 const template *t;
2472
2473 for (t = current_templates->start; t < current_templates->end; ++t)
2474 allowed |= t->operand_types[op];
2475 switch (guess_suffix)
2476 {
2477 case QWORD_MNEM_SUFFIX:
2478 mask = Imm64 | Imm32S;
2479 break;
2480 case LONG_MNEM_SUFFIX:
2481 mask = Imm32;
2482 break;
2483 case WORD_MNEM_SUFFIX:
2484 mask = Imm16;
2485 break;
2486 case BYTE_MNEM_SUFFIX:
2487 mask = Imm8;
2488 break;
2489 default:
2490 mask = 0;
2491 break;
2492 }
64e74474
AM		 2493 if (mask & allowed)
2494 i.types[op] &= mask;
9cd96992 2495 }
29b0f896 2496 break;
252b5132 2497 }
29b0f896
AM		 2498 }
2499}
47926f60 2500
29b0f896
AM		 2501/* Try to use the smallest displacement type too. */
2502static void
2503optimize_disp ()
2504{
2505 int op;
3e73aa7c 2506
29b0f896 2507 for (op = i.operands; --op >= 0;)
b300c311 2508 if (i.types[op] & Disp)
252b5132 2509 {
b300c311 2510 if (i.op[op].disps->X_op == O_constant)
252b5132 2511 {
b300c311 2512 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2513
b300c311
L		 2514 if ((i.types[op] & Disp16)
2515 && (disp & ~(offsetT) 0xffff) == 0)
2516 {
2517 /* If this operand is at most 16 bits, convert
2518 to a signed 16 bit number and don't use 64bit
2519 displacement. */
2520 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2521 i.types[op] &= ~Disp64;
2522 }
2523 if ((i.types[op] & Disp32)
2524 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2525 {
2526 /* If this operand is at most 32 bits, convert
2527 to a signed 32 bit number and don't use 64bit
2528 displacement. */
2529 disp &= (((offsetT) 2 << 31) - 1);
2530 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2531 i.types[op] &= ~Disp64;
2532 }
2533 if (!disp && (i.types[op] & BaseIndex))
2534 {
2535 i.types[op] &= ~Disp;
2536 i.op[op].disps = 0;
2537 i.disp_operands--;
2538 }
2539 else if (flag_code == CODE_64BIT)
2540 {
2541 if (fits_in_signed_long (disp))
28a9d8f5
L		 2542 {
2543 i.types[op] &= ~Disp64;
2544 i.types[op] |= Disp32S;
2545 }
b300c311
L		 2546 if (fits_in_unsigned_long (disp))
2547 i.types[op] |= Disp32;
2548 }
2549 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2550 && fits_in_signed_byte (disp))
2551 i.types[op] |= Disp8;
252b5132 2552 }
67a4f2b7
AO		 2553 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2554 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2555 {
2556 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2557 i.op[op].disps, 0, i.reloc[op]);
2558 i.types[op] &= ~Disp;
2559 }
2560 else
b300c311
L		 2561 /* We only support 64bit displacement on constants. */
2562 i.types[op] &= ~Disp64;
252b5132 2563 }
29b0f896
AM		 2564}
2565
2566static int
2567match_template ()
2568{
2569 /* Points to template once we've found it. */
2570 const template *t;
2571 unsigned int overlap0, overlap1, overlap2;
2572 unsigned int found_reverse_match;
2573 int suffix_check;
539e75ad
L		 2574 unsigned int operand_types [3];
2575 int addr_prefix_disp;
29b0f896
AM		 2576
2577#define MATCH(overlap, given, template) \
2578 ((overlap & ~JumpAbsolute) \
2579 && (((given) & (BaseIndex | JumpAbsolute)) \
2580 == ((overlap) & (BaseIndex | JumpAbsolute))))
2581
2582 /* If given types r0 and r1 are registers they must be of the same type
2583 unless the expected operand type register overlap is null.
2584 Note that Acc in a template matches every size of reg. */
2585#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2586 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2587 || ((g0) & Reg) == ((g1) & Reg) \
2588 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2589
2590 overlap0 = 0;
2591 overlap1 = 0;
2592 overlap2 = 0;
2593 found_reverse_match = 0;
539e75ad
L		 2594 operand_types [0] = 0;
2595 operand_types [1] = 0;
2596 operand_types [2] = 0;
2597 addr_prefix_disp = -1;
29b0f896
AM		 2598 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2599 ? No_bSuf
2600 : (i.suffix == WORD_MNEM_SUFFIX
2601 ? No_wSuf
2602 : (i.suffix == SHORT_MNEM_SUFFIX
2603 ? No_sSuf
2604 : (i.suffix == LONG_MNEM_SUFFIX
2605 ? No_lSuf
2606 : (i.suffix == QWORD_MNEM_SUFFIX
2607 ? No_qSuf
2608 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2609 ? No_xSuf : 0))))));
2610
45aa61fe 2611 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2612 {
539e75ad
L		 2613 addr_prefix_disp = -1;
2614
29b0f896
AM		 2615 /* Must have right number of operands. */
2616 if (i.operands != t->operands)
2617 continue;
2618
2619 /* Check the suffix, except for some instructions in intel mode. */
2620 if ((t->opcode_modifier & suffix_check)
2621 && !(intel_syntax
9306ca4a 2622 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2623 continue;
2624
539e75ad
L		 2625 operand_types [0] = t->operand_types [0];
2626 operand_types [1] = t->operand_types [1];
2627 operand_types [2] = t->operand_types [2];
2628
45aa61fe
AM		 2629 /* In general, don't allow 64-bit operands in 32-bit mode. */
2630 if (i.suffix == QWORD_MNEM_SUFFIX
2631 && flag_code != CODE_64BIT
2632 && (intel_syntax
2633 ? (!(t->opcode_modifier & IgnoreSize)
2634 && !intel_float_operand (t->name))
2635 : intel_float_operand (t->name) != 2)
539e75ad
L		 2636 && (!(operand_types[0] & (RegMMX | RegXMM))
2637 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2638 && (t->base_opcode != 0x0fc7
2639 || t->extension_opcode != 1 /* cmpxchg8b */))
2640 continue;
2641
29b0f896
AM		 2642 /* Do not verify operands when there are none. */
2643 else if (!t->operands)
2644 {
2645 if (t->cpu_flags & ~cpu_arch_flags)
2646 continue;
2647 /* We've found a match; break out of loop. */
2648 break;
2649 }
252b5132 2650
539e75ad
L		 2651 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2652 into Disp32/Disp16/Disp32 operand. */
2653 if (i.prefix[ADDR_PREFIX] != 0)
2654 {
2655 unsigned int j, DispOn = 0, DispOff = 0;
2656
2657 switch (flag_code)
2658 {
2659 case CODE_16BIT:
2660 DispOn = Disp32;
2661 DispOff = Disp16;
2662 break;
2663 case CODE_32BIT:
2664 DispOn = Disp16;
2665 DispOff = Disp32;
2666 break;
2667 case CODE_64BIT:
2668 DispOn = Disp32;
2669 DispOff = Disp64;
2670 break;
2671 }
2672
2673 for (j = 0; j < 3; j++)
2674 {
2675 /* There should be only one Disp operand. */
2676 if ((operand_types[j] & DispOff))
2677 {
2678 addr_prefix_disp = j;
2679 operand_types[j] |= DispOn;
2680 operand_types[j] &= ~DispOff;
2681 break;
2682 }
2683 }
2684 }
2685
2686 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2687 switch (t->operands)
2688 {
2689 case 1:
539e75ad 2690 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2691 continue;
2692 break;
2693 case 2:
2694 case 3:
539e75ad
L		 2695 overlap1 = i.types[1] & operand_types[1];
2696 if (!MATCH (overlap0, i.types[0], operand_types[0])
2697 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2698 /* monitor in SSE3 is a very special case. The first
708587a4 2699 register and the second register may have different
cb712a9e
L		 2700 sizes. */
2701 || !((t->base_opcode == 0x0f01
2702 && t->extension_opcode == 0xc8)
2703 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2704 operand_types[0],
cb712a9e 2705 overlap1, i.types[1],
539e75ad 2706 operand_types[1])))
29b0f896
AM		 2707 {
2708 /* Check if other direction is valid ... */
2709 if ((t->opcode_modifier & (D | FloatD)) == 0)
2710 continue;
2711
2712 /* Try reversing direction of operands. */
539e75ad
L		 2713 overlap0 = i.types[0] & operand_types[1];
2714 overlap1 = i.types[1] & operand_types[0];
2715 if (!MATCH (overlap0, i.types[0], operand_types[1])
2716 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2717 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2718 operand_types[1],
29b0f896 2719 overlap1, i.types[1],
539e75ad 2720 operand_types[0]))
29b0f896
AM		 2721 {
2722 /* Does not match either direction. */
2723 continue;
2724 }
2725 /* found_reverse_match holds which of D or FloatDR
2726 we've found. */
2727 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2728 }
2729 /* Found a forward 2 operand match here. */
2730 else if (t->operands == 3)
2731 {
2732 /* Here we make use of the fact that there are no
2733 reverse match 3 operand instructions, and all 3
2734 operand instructions only need to be checked for
2735 register consistency between operands 2 and 3. */
539e75ad
L		 2736 overlap2 = i.types[2] & operand_types[2];
2737 if (!MATCH (overlap2, i.types[2], operand_types[2])
29b0f896 2738 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
539e75ad 2739 operand_types[1],
29b0f896 2740 overlap2, i.types[2],
539e75ad 2741 operand_types[2]))
29b0f896
AM		 2742
2743 continue;
2744 }
2745 /* Found either forward/reverse 2 or 3 operand match here:
2746 slip through to break. */
2747 }
2748 if (t->cpu_flags & ~cpu_arch_flags)
2749 {
2750 found_reverse_match = 0;
2751 continue;
2752 }
2753 /* We've found a match; break out of loop. */
2754 break;
2755 }
2756
2757 if (t == current_templates->end)
2758 {
2759 /* We found no match. */
2760 as_bad (_("suffix or operands invalid for `%s'"),
2761 current_templates->start->name);
2762 return 0;
2763 }
252b5132 2764
29b0f896
AM		 2765 if (!quiet_warnings)
2766 {
2767 if (!intel_syntax
2768 && ((i.types[0] & JumpAbsolute)
539e75ad 2769 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2770 {
2771 as_warn (_("indirect %s without `*'"), t->name);
2772 }
2773
2774 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2775 == (IsPrefix | IgnoreSize))
2776 {
2777 /* Warn them that a data or address size prefix doesn't
2778 affect assembly of the next line of code. */
2779 as_warn (_("stand-alone `%s' prefix"), t->name);
2780 }
2781 }
2782
2783 /* Copy the template we found. */
2784 i.tm = *t;
539e75ad
L		 2785
2786 if (addr_prefix_disp != -1)
2787 i.tm.operand_types[addr_prefix_disp]
2788 = operand_types[addr_prefix_disp];
2789
29b0f896
AM		 2790 if (found_reverse_match)
2791 {
2792 /* If we found a reverse match we must alter the opcode
2793 direction bit. found_reverse_match holds bits to change
2794 (different for int & float insns). */
2795
2796 i.tm.base_opcode ^= found_reverse_match;
2797
539e75ad
L		 2798 i.tm.operand_types[0] = operand_types[1];
2799 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2800 }
2801
2802 return 1;
2803}
2804
2805static int
2806check_string ()
2807{
2808 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2809 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2810 {
2811 if (i.seg[0] != NULL && i.seg[0] != &es)
2812 {
2813 as_bad (_("`%s' operand %d must use `%%es' segment"),
2814 i.tm.name,
2815 mem_op + 1);
2816 return 0;
2817 }
2818 /* There's only ever one segment override allowed per instruction.
2819 This instruction possibly has a legal segment override on the
2820 second operand, so copy the segment to where non-string
2821 instructions store it, allowing common code. */
2822 i.seg[0] = i.seg[1];
2823 }
2824 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2825 {
2826 if (i.seg[1] != NULL && i.seg[1] != &es)
2827 {
2828 as_bad (_("`%s' operand %d must use `%%es' segment"),
2829 i.tm.name,
2830 mem_op + 2);
2831 return 0;
2832 }
2833 }
2834 return 1;
2835}
2836
2837static int
543613e9 2838process_suffix (void)
29b0f896
AM		 2839{
2840 /* If matched instruction specifies an explicit instruction mnemonic
2841 suffix, use it. */
2842 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2843 {
2844 if (i.tm.opcode_modifier & Size16)
2845 i.suffix = WORD_MNEM_SUFFIX;
2846 else if (i.tm.opcode_modifier & Size64)
2847 i.suffix = QWORD_MNEM_SUFFIX;
2848 else
2849 i.suffix = LONG_MNEM_SUFFIX;
2850 }
2851 else if (i.reg_operands)
2852 {
2853 /* If there's no instruction mnemonic suffix we try to invent one
2854 based on register operands. */
2855 if (!i.suffix)
2856 {
2857 /* We take i.suffix from the last register operand specified,
2858 Destination register type is more significant than source
2859 register type. */
2860 int op;
543613e9 2861
29b0f896
AM		 2862 for (op = i.operands; --op >= 0;)
2863 if ((i.types[op] & Reg)
2864 && !(i.tm.operand_types[op] & InOutPortReg))
2865 {
2866 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2867 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2868 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2869 LONG_MNEM_SUFFIX);
2870 break;
2871 }
2872 }
2873 else if (i.suffix == BYTE_MNEM_SUFFIX)
2874 {
2875 if (!check_byte_reg ())
2876 return 0;
2877 }
2878 else if (i.suffix == LONG_MNEM_SUFFIX)
2879 {
2880 if (!check_long_reg ())
2881 return 0;
2882 }
2883 else if (i.suffix == QWORD_MNEM_SUFFIX)
2884 {
2885 if (!check_qword_reg ())
2886 return 0;
2887 }
2888 else if (i.suffix == WORD_MNEM_SUFFIX)
2889 {
2890 if (!check_word_reg ())
2891 return 0;
2892 }
2893 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2894 /* Do nothing if the instruction is going to ignore the prefix. */
2895 ;
2896 else
2897 abort ();
2898 }
9306ca4a
JB		 2899 else if ((i.tm.opcode_modifier & DefaultSize)
2900 && !i.suffix
2901 /* exclude fldenv/frstor/fsave/fstenv */
2902 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2903 {
2904 i.suffix = stackop_size;
2905 }
9306ca4a
JB		 2906 else if (intel_syntax
2907 && !i.suffix
2908 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2909 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2910 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2911 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2912 {
2913 switch (flag_code)
2914 {
2915 case CODE_64BIT:
2916 if (!(i.tm.opcode_modifier & No_qSuf))
2917 {
2918 i.suffix = QWORD_MNEM_SUFFIX;
2919 break;
2920 }
2921 case CODE_32BIT:
2922 if (!(i.tm.opcode_modifier & No_lSuf))
2923 i.suffix = LONG_MNEM_SUFFIX;
2924 break;
2925 case CODE_16BIT:
2926 if (!(i.tm.opcode_modifier & No_wSuf))
2927 i.suffix = WORD_MNEM_SUFFIX;
2928 break;
2929 }
2930 }
252b5132 2931
9306ca4a 2932 if (!i.suffix)
29b0f896 2933 {
9306ca4a
JB		 2934 if (!intel_syntax)
2935 {
2936 if (i.tm.opcode_modifier & W)
2937 {
2938 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2939 return 0;
2940 }
2941 }
2942 else
2943 {
64e74474
AM		 2944 unsigned int suffixes = (~i.tm.opcode_modifier
2945 & (No_bSuf
2946 | No_wSuf
2947 | No_lSuf
2948 | No_sSuf
2949 | No_xSuf
2950 | No_qSuf));
9306ca4a
JB		 2951
2952 if ((i.tm.opcode_modifier & W)
2953 || ((suffixes & (suffixes - 1))
2954 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2955 {
2956 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2957 return 0;
2958 }
2959 }
29b0f896 2960 }
252b5132 2961
9306ca4a
JB		 2962 /* Change the opcode based on the operand size given by i.suffix;
2963 We don't need to change things for byte insns. */
2964
29b0f896
AM		 2965 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2966 {
2967 /* It's not a byte, select word/dword operation. */
2968 if (i.tm.opcode_modifier & W)
2969 {
2970 if (i.tm.opcode_modifier & ShortForm)
2971 i.tm.base_opcode |= 8;
2972 else
2973 i.tm.base_opcode |= 1;
2974 }
0f3f3d8b 2975
29b0f896
AM		 2976 /* Now select between word & dword operations via the operand
2977 size prefix, except for instructions that will ignore this
2978 prefix anyway. */
cb712a9e
L		 2979 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2980 {
2981 /* monitor in SSE3 is a very special case. The default size
2982 of AX is the size of mode. The address size override
2983 prefix will change the size of AX. */
2984 if (i.op->regs[0].reg_type &
2985 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2986 if (!add_prefix (ADDR_PREFIX_OPCODE))
2987 return 0;
2988 }
2989 else if (i.suffix != QWORD_MNEM_SUFFIX
2990 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2991 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2992 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2993 || (flag_code == CODE_64BIT
2994 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2995 {
2996 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2997
29b0f896
AM		 2998 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2999 prefix = ADDR_PREFIX_OPCODE;
252b5132 3000
29b0f896
AM		 3001 if (!add_prefix (prefix))
3002 return 0;
24eab124 3003 }
252b5132 3004
29b0f896
AM		 3005 /* Set mode64 for an operand. */
3006 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3007 && flag_code == CODE_64BIT
29b0f896 3008 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3009 {
3010 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3011 need rex64. */
3012 if (i.operands != 2
3013 || i.types [0] != (Acc | Reg64)
3014 || i.types [1] != (Acc | Reg64)
3015 || strcmp (i.tm.name, "xchg") != 0)
3016 i.rex |= REX_MODE64;
3017 }
3e73aa7c 3018
29b0f896
AM		 3019 /* Size floating point instruction. */
3020 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3021 if (i.tm.opcode_modifier & FloatMF)
3022 i.tm.base_opcode ^= 4;
29b0f896 3023 }
7ecd2f8b 3024
29b0f896
AM		 3025 return 1;
3026}
3e73aa7c 3027
29b0f896 3028static int
543613e9 3029check_byte_reg (void)
29b0f896
AM		 3030{
3031 int op;
543613e9 3032
29b0f896
AM		 3033 for (op = i.operands; --op >= 0;)
3034 {
3035 /* If this is an eight bit register, it's OK. If it's the 16 or
3036 32 bit version of an eight bit register, we will just use the
3037 low portion, and that's OK too. */
3038 if (i.types[op] & Reg8)
3039 continue;
3040
3041 /* movzx and movsx should not generate this warning. */
3042 if (intel_syntax
3043 && (i.tm.base_opcode == 0xfb7
3044 || i.tm.base_opcode == 0xfb6
3045 || i.tm.base_opcode == 0x63
3046 || i.tm.base_opcode == 0xfbe
3047 || i.tm.base_opcode == 0xfbf))
3048 continue;
3049
65ec77d2 3050 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3051 {
3052 /* Prohibit these changes in the 64bit mode, since the
3053 lowering is more complicated. */
3054 if (flag_code == CODE_64BIT
3055 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3056 {
0f3f3d8b 3057 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3058 i.op[op].regs->reg_name,
3059 i.suffix);
3060 return 0;
3061 }
3062#if REGISTER_WARNINGS
3063 if (!quiet_warnings
3064 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3065 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3066 (i.op[op].regs + (i.types[op] & Reg16
3067 ? REGNAM_AL - REGNAM_AX
3068 : REGNAM_AL - REGNAM_EAX))->reg_name,
3069 i.op[op].regs->reg_name,
3070 i.suffix);
3071#endif
3072 continue;
3073 }
3074 /* Any other register is bad. */
3075 if (i.types[op] & (Reg | RegMMX | RegXMM
3076 | SReg2 | SReg3
3077 | Control | Debug | Test
3078 | FloatReg | FloatAcc))
3079 {
3080 as_bad (_("`%%%s' not allowed with `%s%c'"),
3081 i.op[op].regs->reg_name,
3082 i.tm.name,
3083 i.suffix);
3084 return 0;
3085 }
3086 }
3087 return 1;
3088}
3089
3090static int
3091check_long_reg ()
3092{
3093 int op;
3094
3095 for (op = i.operands; --op >= 0;)
3096 /* Reject eight bit registers, except where the template requires
3097 them. (eg. movzb) */
3098 if ((i.types[op] & Reg8) != 0
3099 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3100 {
3101 as_bad (_("`%%%s' not allowed with `%s%c'"),
3102 i.op[op].regs->reg_name,
3103 i.tm.name,
3104 i.suffix);
3105 return 0;
3106 }
3107 /* Warn if the e prefix on a general reg is missing. */
3108 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3109 && (i.types[op] & Reg16) != 0
3110 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3111 {
3112 /* Prohibit these changes in the 64bit mode, since the
3113 lowering is more complicated. */
3114 if (flag_code == CODE_64BIT)
252b5132 3115 {
0f3f3d8b 3116 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3117 i.op[op].regs->reg_name,
3118 i.suffix);
3119 return 0;
252b5132 3120 }
29b0f896
AM		 3121#if REGISTER_WARNINGS
3122 else
3123 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3124 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3125 i.op[op].regs->reg_name,
3126 i.suffix);
3127#endif
252b5132 3128 }
29b0f896
AM		 3129 /* Warn if the r prefix on a general reg is missing. */
3130 else if ((i.types[op] & Reg64) != 0
3131 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3132 {
0f3f3d8b 3133 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3134 i.op[op].regs->reg_name,
3135 i.suffix);
3136 return 0;
3137 }
3138 return 1;
3139}
252b5132 3140
29b0f896
AM		 3141static int
3142check_qword_reg ()
3143{
3144 int op;
252b5132 3145
29b0f896
AM		 3146 for (op = i.operands; --op >= 0; )
3147 /* Reject eight bit registers, except where the template requires
3148 them. (eg. movzb) */
3149 if ((i.types[op] & Reg8) != 0
3150 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3151 {
3152 as_bad (_("`%%%s' not allowed with `%s%c'"),
3153 i.op[op].regs->reg_name,
3154 i.tm.name,
3155 i.suffix);
3156 return 0;
3157 }
3158 /* Warn if the e prefix on a general reg is missing. */
3159 else if (((i.types[op] & Reg16) != 0
3160 || (i.types[op] & Reg32) != 0)
3161 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3162 {
3163 /* Prohibit these changes in the 64bit mode, since the
3164 lowering is more complicated. */
0f3f3d8b 3165 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3166 i.op[op].regs->reg_name,
3167 i.suffix);
3168 return 0;
252b5132 3169 }
29b0f896
AM		 3170 return 1;
3171}
252b5132 3172
29b0f896
AM		 3173static int
3174check_word_reg ()
3175{
3176 int op;
3177 for (op = i.operands; --op >= 0;)
3178 /* Reject eight bit registers, except where the template requires
3179 them. (eg. movzb) */
3180 if ((i.types[op] & Reg8) != 0
3181 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3182 {
3183 as_bad (_("`%%%s' not allowed with `%s%c'"),
3184 i.op[op].regs->reg_name,
3185 i.tm.name,
3186 i.suffix);
3187 return 0;
3188 }
3189 /* Warn if the e prefix on a general reg is present. */
3190 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3191 && (i.types[op] & Reg32) != 0
3192 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3193 {
29b0f896
AM		 3194 /* Prohibit these changes in the 64bit mode, since the
3195 lowering is more complicated. */
3196 if (flag_code == CODE_64BIT)
252b5132 3197 {
0f3f3d8b 3198 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3199 i.op[op].regs->reg_name,
3200 i.suffix);
3201 return 0;
252b5132 3202 }
29b0f896
AM		 3203 else
3204#if REGISTER_WARNINGS
3205 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3206 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3207 i.op[op].regs->reg_name,
3208 i.suffix);
3209#endif
3210 }
3211 return 1;
3212}
252b5132 3213
29b0f896
AM		 3214static int
3215finalize_imm ()
3216{
3217 unsigned int overlap0, overlap1, overlap2;
3218
3219 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3220 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3221 && overlap0 != Imm8 && overlap0 != Imm8S
3222 && overlap0 != Imm16 && overlap0 != Imm32S
3223 && overlap0 != Imm32 && overlap0 != Imm64)
3224 {
3225 if (i.suffix)
3226 {
3227 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3228 ? Imm8 | Imm8S
3229 : (i.suffix == WORD_MNEM_SUFFIX
3230 ? Imm16
3231 : (i.suffix == QWORD_MNEM_SUFFIX
3232 ? Imm64 | Imm32S
3233 : Imm32)));
3234 }
3235 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3236 || overlap0 == (Imm16 | Imm32)
3237 || overlap0 == (Imm16 | Imm32S))
3238 {
3239 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3240 ? Imm16 : Imm32S);
3241 }
3242 if (overlap0 != Imm8 && overlap0 != Imm8S
3243 && overlap0 != Imm16 && overlap0 != Imm32S
3244 && overlap0 != Imm32 && overlap0 != Imm64)
3245 {
3246 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3247 return 0;
3248 }
3249 }
3250 i.types[0] = overlap0;
3251
3252 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3253 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3254 && overlap1 != Imm8 && overlap1 != Imm8S
3255 && overlap1 != Imm16 && overlap1 != Imm32S
3256 && overlap1 != Imm32 && overlap1 != Imm64)
3257 {
3258 if (i.suffix)
3259 {
3260 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3261 ? Imm8 | Imm8S
3262 : (i.suffix == WORD_MNEM_SUFFIX
3263 ? Imm16
3264 : (i.suffix == QWORD_MNEM_SUFFIX
3265 ? Imm64 | Imm32S
3266 : Imm32)));
3267 }
3268 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3269 || overlap1 == (Imm16 | Imm32)
3270 || overlap1 == (Imm16 | Imm32S))
3271 {
3272 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3273 ? Imm16 : Imm32S);
3274 }
3275 if (overlap1 != Imm8 && overlap1 != Imm8S
3276 && overlap1 != Imm16 && overlap1 != Imm32S
3277 && overlap1 != Imm32 && overlap1 != Imm64)
3278 {
3279 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3280 return 0;
3281 }
3282 }
3283 i.types[1] = overlap1;
3284
3285 overlap2 = i.types[2] & i.tm.operand_types[2];
3286 assert ((overlap2 & Imm) == 0);
3287 i.types[2] = overlap2;
3288
3289 return 1;
3290}
3291
3292static int
3293process_operands ()
3294{
3295 /* Default segment register this instruction will use for memory
3296 accesses. 0 means unknown. This is only for optimizing out
3297 unnecessary segment overrides. */
3298 const seg_entry *default_seg = 0;
3299
3300 /* The imul $imm, %reg instruction is converted into
3301 imul $imm, %reg, %reg, and the clr %reg instruction
3302 is converted into xor %reg, %reg. */
3303 if (i.tm.opcode_modifier & regKludge)
3304 {
3305 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3306 /* Pretend we saw the extra register operand. */
3307 assert (i.op[first_reg_op + 1].regs == 0);
3308 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3309 i.types[first_reg_op + 1] = i.types[first_reg_op];
3310 i.reg_operands = 2;
3311 }
3312
3313 if (i.tm.opcode_modifier & ShortForm)
3314 {
3315 /* The register or float register operand is in operand 0 or 1. */
3316 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3317 /* Register goes in low 3 bits of opcode. */
3318 i.tm.base_opcode |= i.op[op].regs->reg_num;
3319 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3320 i.rex |= REX_EXTZ;
3321 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3322 {
3323 /* Warn about some common errors, but press on regardless.
3324 The first case can be generated by gcc (<= 2.8.1). */
3325 if (i.operands == 2)
3326 {
3327 /* Reversed arguments on faddp, fsubp, etc. */
3328 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3329 i.op[1].regs->reg_name,
3330 i.op[0].regs->reg_name);
3331 }
3332 else
3333 {
3334 /* Extraneous `l' suffix on fp insn. */
3335 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3336 i.op[0].regs->reg_name);
3337 }
3338 }
3339 }
3340 else if (i.tm.opcode_modifier & Modrm)
3341 {
3342 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3343 must be put into the modrm byte). Now, we make the modrm and
3344 index base bytes based on all the info we've collected. */
29b0f896
AM		 3345
3346 default_seg = build_modrm_byte ();
3347 }
3348 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3349 {
3350 if (i.tm.base_opcode == POP_SEG_SHORT
3351 && i.op[0].regs->reg_num == 1)
3352 {
3353 as_bad (_("you can't `pop %%cs'"));
3354 return 0;
3355 }
3356 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3357 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3358 i.rex |= REX_EXTZ;
3359 }
3360 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3361 {
3362 default_seg = &ds;
3363 }
3364 else if ((i.tm.opcode_modifier & IsString) != 0)
3365 {
3366 /* For the string instructions that allow a segment override
3367 on one of their operands, the default segment is ds. */
3368 default_seg = &ds;
3369 }
3370
30123838
JB		 3371 if ((i.tm.base_opcode == 0x8d /* lea */
3372 || (i.tm.cpu_flags & CpuSVME))
3373 && i.seg[0] && !quiet_warnings)
3374 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3375
3376 /* If a segment was explicitly specified, and the specified segment
3377 is not the default, use an opcode prefix to select it. If we
3378 never figured out what the default segment is, then default_seg
3379 will be zero at this point, and the specified segment prefix will
3380 always be used. */
29b0f896
AM		 3381 if ((i.seg[0]) && (i.seg[0] != default_seg))
3382 {
3383 if (!add_prefix (i.seg[0]->seg_prefix))
3384 return 0;
3385 }
3386 return 1;
3387}
3388
3389static const seg_entry *
3390build_modrm_byte ()
3391{
3392 const seg_entry *default_seg = 0;
3393
3394 /* i.reg_operands MUST be the number of real register operands;
3395 implicit registers do not count. */
3396 if (i.reg_operands == 2)
3397 {
3398 unsigned int source, dest;
3399 source = ((i.types[0]
3400 & (Reg | RegMMX | RegXMM
3401 | SReg2 | SReg3
3402 | Control | Debug | Test))
3403 ? 0 : 1);
050dfa73
MM		 3404
3405 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3406 bytes and hence source operand will be in the next byte after the immediates */
3407 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3408 dest = source + 1;
3409
3410 i.rm.mode = 3;
3411 /* One of the register operands will be encoded in the i.tm.reg
3412 field, the other in the combined i.tm.mode and i.tm.regmem
3413 fields. If no form of this instruction supports a memory
3414 destination operand, then we assume the source operand may
3415 sometimes be a memory operand and so we need to store the
3416 destination in the i.rm.reg field. */
3417 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3418 {
3419 i.rm.reg = i.op[dest].regs->reg_num;
3420 i.rm.regmem = i.op[source].regs->reg_num;
3421 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3422 i.rex |= REX_EXTX;
3423 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3424 i.rex |= REX_EXTZ;
3425 }
3426 else
3427 {
3428 i.rm.reg = i.op[source].regs->reg_num;
3429 i.rm.regmem = i.op[dest].regs->reg_num;
3430 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3431 i.rex |= REX_EXTZ;
3432 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3433 i.rex |= REX_EXTX;
3434 }
c4a530c5
JB		 3435 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3436 {
3437 if (!((i.types[0] | i.types[1]) & Control))
3438 abort ();
3439 i.rex &= ~(REX_EXTX | REX_EXTZ);
3440 add_prefix (LOCK_PREFIX_OPCODE);
3441 }
29b0f896
AM		 3442 }
3443 else
3444 { /* If it's not 2 reg operands... */
3445 if (i.mem_operands)
3446 {
3447 unsigned int fake_zero_displacement = 0;
3448 unsigned int op = ((i.types[0] & AnyMem)
3449 ? 0
3450 : (i.types[1] & AnyMem) ? 1 : 2);
3451
3452 default_seg = &ds;
3453
3454 if (i.base_reg == 0)
3455 {
3456 i.rm.mode = 0;
3457 if (!i.disp_operands)
3458 fake_zero_displacement = 1;
3459 if (i.index_reg == 0)
3460 {
3461 /* Operand is just <disp> */
20f0a1fc 3462 if (flag_code == CODE_64BIT)
29b0f896
AM		 3463 {
3464 /* 64bit mode overwrites the 32bit absolute
3465 addressing by RIP relative addressing and
3466 absolute addressing is encoded by one of the
3467 redundant SIB forms. */
3468 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3469 i.sib.base = NO_BASE_REGISTER;
3470 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3471 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3472 }
3473 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3474 {
3475 i.rm.regmem = NO_BASE_REGISTER_16;
3476 i.types[op] = Disp16;
3477 }
3478 else
3479 {
3480 i.rm.regmem = NO_BASE_REGISTER;
3481 i.types[op] = Disp32;
29b0f896
AM		 3482 }
3483 }
3484 else /* !i.base_reg && i.index_reg */
3485 {
3486 i.sib.index = i.index_reg->reg_num;
3487 i.sib.base = NO_BASE_REGISTER;
3488 i.sib.scale = i.log2_scale_factor;
3489 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3490 i.types[op] &= ~Disp;
3491 if (flag_code != CODE_64BIT)
3492 i.types[op] |= Disp32; /* Must be 32 bit */
3493 else
3494 i.types[op] |= Disp32S;
3495 if ((i.index_reg->reg_flags & RegRex) != 0)
3496 i.rex |= REX_EXTY;
3497 }
3498 }
3499 /* RIP addressing for 64bit mode. */
3500 else if (i.base_reg->reg_type == BaseIndex)
3501 {
3502 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3503 i.types[op] &= ~ Disp;
29b0f896
AM		 3504 i.types[op] |= Disp32S;
3505 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3506 if (! i.disp_operands)
3507 fake_zero_displacement = 1;
29b0f896
AM		 3508 }
3509 else if (i.base_reg->reg_type & Reg16)
3510 {
3511 switch (i.base_reg->reg_num)
3512 {
3513 case 3: /* (%bx) */
3514 if (i.index_reg == 0)
3515 i.rm.regmem = 7;
3516 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3517 i.rm.regmem = i.index_reg->reg_num - 6;
3518 break;
3519 case 5: /* (%bp) */
3520 default_seg = &ss;
3521 if (i.index_reg == 0)
3522 {
3523 i.rm.regmem = 6;
3524 if ((i.types[op] & Disp) == 0)
3525 {
3526 /* fake (%bp) into 0(%bp) */
3527 i.types[op] |= Disp8;
252b5132 3528 fake_zero_displacement = 1;
29b0f896
AM		 3529 }
3530 }
3531 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3532 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3533 break;
3534 default: /* (%si) -> 4 or (%di) -> 5 */
3535 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3536 }
3537 i.rm.mode = mode_from_disp_size (i.types[op]);
3538 }
3539 else /* i.base_reg and 32/64 bit mode */
3540 {
3541 if (flag_code == CODE_64BIT
3542 && (i.types[op] & Disp))
20f0a1fc
NC		 3543 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3544
29b0f896
AM		 3545 i.rm.regmem = i.base_reg->reg_num;
3546 if ((i.base_reg->reg_flags & RegRex) != 0)
3547 i.rex |= REX_EXTZ;
3548 i.sib.base = i.base_reg->reg_num;
3549 /* x86-64 ignores REX prefix bit here to avoid decoder
3550 complications. */
3551 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3552 {
3553 default_seg = &ss;
3554 if (i.disp_operands == 0)
3555 {
3556 fake_zero_displacement = 1;
3557 i.types[op] |= Disp8;
3558 }
3559 }
3560 else if (i.base_reg->reg_num == ESP_REG_NUM)
3561 {
3562 default_seg = &ss;
3563 }
3564 i.sib.scale = i.log2_scale_factor;
3565 if (i.index_reg == 0)
3566 {
3567 /* <disp>(%esp) becomes two byte modrm with no index
3568 register. We've already stored the code for esp
3569 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3570 Any base register besides %esp will not use the
3571 extra modrm byte. */
3572 i.sib.index = NO_INDEX_REGISTER;
3573#if !SCALE1_WHEN_NO_INDEX
3574 /* Another case where we force the second modrm byte. */
3575 if (i.log2_scale_factor)
3576 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3577#endif
29b0f896
AM		 3578 }
3579 else
3580 {
3581 i.sib.index = i.index_reg->reg_num;
3582 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3583 if ((i.index_reg->reg_flags & RegRex) != 0)
3584 i.rex |= REX_EXTY;
3585 }
67a4f2b7
AO		 3586
3587 if (i.disp_operands
3588 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3589 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3590 i.rm.mode = 0;
3591 else
3592 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3593 }
252b5132 3594
29b0f896
AM		 3595 if (fake_zero_displacement)
3596 {
3597 /* Fakes a zero displacement assuming that i.types[op]
3598 holds the correct displacement size. */
3599 expressionS *exp;
3600
3601 assert (i.op[op].disps == 0);
3602 exp = &disp_expressions[i.disp_operands++];
3603 i.op[op].disps = exp;
3604 exp->X_op = O_constant;
3605 exp->X_add_number = 0;
3606 exp->X_add_symbol = (symbolS *) 0;
3607 exp->X_op_symbol = (symbolS *) 0;
3608 }
3609 }
252b5132 3610
29b0f896
AM		 3611 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3612 (if any) based on i.tm.extension_opcode. Again, we must be
3613 careful to make sure that segment/control/debug/test/MMX
3614 registers are coded into the i.rm.reg field. */
3615 if (i.reg_operands)
3616 {
3617 unsigned int op =
3618 ((i.types[0]
3619 & (Reg | RegMMX | RegXMM
3620 | SReg2 | SReg3
3621 | Control | Debug | Test))
3622 ? 0
3623 : ((i.types[1]
3624 & (Reg | RegMMX | RegXMM
3625 | SReg2 | SReg3
3626 | Control | Debug | Test))
3627 ? 1
3628 : 2));
3629 /* If there is an extension opcode to put here, the register
3630 number must be put into the regmem field. */
3631 if (i.tm.extension_opcode != None)
3632 {
3633 i.rm.regmem = i.op[op].regs->reg_num;
3634 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3635 i.rex |= REX_EXTZ;
3636 }
3637 else
3638 {
3639 i.rm.reg = i.op[op].regs->reg_num;
3640 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3641 i.rex |= REX_EXTX;
3642 }
252b5132 3643
29b0f896
AM		 3644 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3645 must set it to 3 to indicate this is a register operand
3646 in the regmem field. */
3647 if (!i.mem_operands)
3648 i.rm.mode = 3;
3649 }
252b5132 3650
29b0f896
AM		 3651 /* Fill in i.rm.reg field with extension opcode (if any). */
3652 if (i.tm.extension_opcode != None)
3653 i.rm.reg = i.tm.extension_opcode;
3654 }
3655 return default_seg;
3656}
252b5132 3657
29b0f896
AM		 3658static void
3659output_branch ()
3660{
3661 char *p;
3662 int code16;
3663 int prefix;
3664 relax_substateT subtype;
3665 symbolS *sym;
3666 offsetT off;
3667
3668 code16 = 0;
3669 if (flag_code == CODE_16BIT)
3670 code16 = CODE16;
3671
3672 prefix = 0;
3673 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3674 {
29b0f896
AM		 3675 prefix = 1;
3676 i.prefixes -= 1;
3677 code16 ^= CODE16;
252b5132 3678 }
29b0f896
AM		 3679 /* Pentium4 branch hints. */
3680 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3681 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3682 {
29b0f896
AM		 3683 prefix++;
3684 i.prefixes--;
3685 }
3686 if (i.prefix[REX_PREFIX] != 0)
3687 {
3688 prefix++;
3689 i.prefixes--;
2f66722d
AM		 3690 }
3691
29b0f896
AM		 3692 if (i.prefixes != 0 && !intel_syntax)
3693 as_warn (_("skipping prefixes on this instruction"));
3694
3695 /* It's always a symbol; End frag & setup for relax.
3696 Make sure there is enough room in this frag for the largest
3697 instruction we may generate in md_convert_frag. This is 2
3698 bytes for the opcode and room for the prefix and largest
3699 displacement. */
3700 frag_grow (prefix + 2 + 4);
3701 /* Prefix and 1 opcode byte go in fr_fix. */
3702 p = frag_more (prefix + 1);
3703 if (i.prefix[DATA_PREFIX] != 0)
3704 *p++ = DATA_PREFIX_OPCODE;
3705 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3706 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3707 *p++ = i.prefix[SEG_PREFIX];
3708 if (i.prefix[REX_PREFIX] != 0)
3709 *p++ = i.prefix[REX_PREFIX];
3710 *p = i.tm.base_opcode;
3711
3712 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3713 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3714 else if ((cpu_arch_flags & Cpu386) != 0)
3715 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3716 else
3717 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3718 subtype |= code16;
3e73aa7c 3719
29b0f896
AM		 3720 sym = i.op[0].disps->X_add_symbol;
3721 off = i.op[0].disps->X_add_number;
3e73aa7c 3722
29b0f896
AM		 3723 if (i.op[0].disps->X_op != O_constant
3724 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3725 {
29b0f896
AM		 3726 /* Handle complex expressions. */
3727 sym = make_expr_symbol (i.op[0].disps);
3728 off = 0;
3729 }
3e73aa7c 3730
29b0f896
AM		 3731 /* 1 possible extra opcode + 4 byte displacement go in var part.
3732 Pass reloc in fr_var. */
3733 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3734}
3e73aa7c 3735
29b0f896
AM		 3736static void
3737output_jump ()
3738{
3739 char *p;
3740 int size;
3e02c1cc 3741 fixS *fixP;
29b0f896
AM		 3742
3743 if (i.tm.opcode_modifier & JumpByte)
3744 {
3745 /* This is a loop or jecxz type instruction. */
3746 size = 1;
3747 if (i.prefix[ADDR_PREFIX] != 0)
3748 {
3749 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3750 i.prefixes -= 1;
3751 }
3752 /* Pentium4 branch hints. */
3753 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3754 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3755 {
3756 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3757 i.prefixes--;
3e73aa7c
JH		 3758 }
3759 }
29b0f896
AM		 3760 else
3761 {
3762 int code16;
3e73aa7c 3763
29b0f896
AM		 3764 code16 = 0;
3765 if (flag_code == CODE_16BIT)
3766 code16 = CODE16;
3e73aa7c 3767
29b0f896
AM		 3768 if (i.prefix[DATA_PREFIX] != 0)
3769 {
3770 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3771 i.prefixes -= 1;
3772 code16 ^= CODE16;
3773 }
252b5132 3774
29b0f896
AM		 3775 size = 4;
3776 if (code16)
3777 size = 2;
3778 }
9fcc94b6 3779
29b0f896
AM		 3780 if (i.prefix[REX_PREFIX] != 0)
3781 {
3782 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3783 i.prefixes -= 1;
3784 }
252b5132 3785
29b0f896
AM		 3786 if (i.prefixes != 0 && !intel_syntax)
3787 as_warn (_("skipping prefixes on this instruction"));
e0890092 3788
29b0f896
AM		 3789 p = frag_more (1 + size);
3790 *p++ = i.tm.base_opcode;
e0890092 3791
3e02c1cc
AM		 3792 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3793 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3794
3795 /* All jumps handled here are signed, but don't use a signed limit
3796 check for 32 and 16 bit jumps as we want to allow wrap around at
3797 4G and 64k respectively. */
3798 if (size == 1)
3799 fixP->fx_signed = 1;
29b0f896 3800}
e0890092 3801
29b0f896
AM		 3802static void
3803output_interseg_jump ()
3804{
3805 char *p;
3806 int size;
3807 int prefix;
3808 int code16;
252b5132 3809
29b0f896
AM		 3810 code16 = 0;
3811 if (flag_code == CODE_16BIT)
3812 code16 = CODE16;
a217f122 3813
29b0f896
AM		 3814 prefix = 0;
3815 if (i.prefix[DATA_PREFIX] != 0)
3816 {
3817 prefix = 1;
3818 i.prefixes -= 1;
3819 code16 ^= CODE16;
3820 }
3821 if (i.prefix[REX_PREFIX] != 0)
3822 {
3823 prefix++;
3824 i.prefixes -= 1;
3825 }
252b5132 3826
29b0f896
AM		 3827 size = 4;
3828 if (code16)
3829 size = 2;
252b5132 3830
29b0f896
AM		 3831 if (i.prefixes != 0 && !intel_syntax)
3832 as_warn (_("skipping prefixes on this instruction"));
252b5132 3833
29b0f896
AM		 3834 /* 1 opcode; 2 segment; offset */
3835 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3836
29b0f896
AM		 3837 if (i.prefix[DATA_PREFIX] != 0)
3838 *p++ = DATA_PREFIX_OPCODE;
252b5132 3839
29b0f896
AM		 3840 if (i.prefix[REX_PREFIX] != 0)
3841 *p++ = i.prefix[REX_PREFIX];
252b5132 3842
29b0f896
AM		 3843 *p++ = i.tm.base_opcode;
3844 if (i.op[1].imms->X_op == O_constant)
3845 {
3846 offsetT n = i.op[1].imms->X_add_number;
252b5132 3847
29b0f896
AM		 3848 if (size == 2
3849 && !fits_in_unsigned_word (n)
3850 && !fits_in_signed_word (n))
3851 {
3852 as_bad (_("16-bit jump out of range"));
3853 return;
3854 }
3855 md_number_to_chars (p, n, size);
3856 }
3857 else
3858 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3859 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3860 if (i.op[0].imms->X_op != O_constant)
3861 as_bad (_("can't handle non absolute segment in `%s'"),
3862 i.tm.name);
3863 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3864}
a217f122 3865
29b0f896
AM		 3866static void
3867output_insn ()
3868{
2bbd9c25
JJ		 3869 fragS *insn_start_frag;
3870 offsetT insn_start_off;
3871
29b0f896
AM		 3872 /* Tie dwarf2 debug info to the address at the start of the insn.
3873 We can't do this after the insn has been output as the current
3874 frag may have been closed off. eg. by frag_var. */
3875 dwarf2_emit_insn (0);
3876
2bbd9c25
JJ		 3877 insn_start_frag = frag_now;
3878 insn_start_off = frag_now_fix ();
3879
29b0f896
AM		 3880 /* Output jumps. */
3881 if (i.tm.opcode_modifier & Jump)
3882 output_branch ();
3883 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3884 output_jump ();
3885 else if (i.tm.opcode_modifier & JumpInterSegment)
3886 output_interseg_jump ();
3887 else
3888 {
3889 /* Output normal instructions here. */
3890 char *p;
3891 unsigned char *q;
331d2d0d 3892 unsigned int prefix;
252b5132 3893
ef05d495
L		 3894 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3895 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3896 use one more higher byte to specify a prefix the instruction
3897 requires. */
3898 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3899 {
331d2d0d
L		 3900 if (i.tm.base_opcode & 0xff000000)
3901 {
3902 prefix = (i.tm.base_opcode >> 24) & 0xff;
3903 goto check_prefix;
3904 }
3905 }
3906 else if ((i.tm.base_opcode & 0xff0000) != 0)
3907 {
3908 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3909 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3910 {
64e74474 3911 check_prefix:
bc4bd9ab
MK		 3912 if (prefix != REPE_PREFIX_OPCODE
3913 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3914 add_prefix (prefix);
3915 }
3916 else
331d2d0d 3917 add_prefix (prefix);
0f10071e 3918 }
252b5132 3919
29b0f896
AM		 3920 /* The prefix bytes. */
3921 for (q = i.prefix;
3922 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3923 q++)
3924 {
3925 if (*q)
3926 {
3927 p = frag_more (1);
3928 md_number_to_chars (p, (valueT) *q, 1);
3929 }
3930 }
252b5132 3931
29b0f896
AM		 3932 /* Now the opcode; be careful about word order here! */
3933 if (fits_in_unsigned_byte (i.tm.base_opcode))
3934 {
3935 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3936 }
3937 else
3938 {
ef05d495 3939 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3940 {
3941 p = frag_more (3);
3942 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3943 }
3944 else
3945 p = frag_more (2);
0f10071e 3946
29b0f896
AM		 3947 /* Put out high byte first: can't use md_number_to_chars! */
3948 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3949 *p = i.tm.base_opcode & 0xff;
3950 }
3e73aa7c 3951
29b0f896
AM		 3952 /* Now the modrm byte and sib byte (if present). */
3953 if (i.tm.opcode_modifier & Modrm)
3954 {
3955 p = frag_more (1);
3956 md_number_to_chars (p,
3957 (valueT) (i.rm.regmem << 0
3958 | i.rm.reg << 3
3959 | i.rm.mode << 6),
3960 1);
3961 /* If i.rm.regmem == ESP (4)
3962 && i.rm.mode != (Register mode)
3963 && not 16 bit
3964 ==> need second modrm byte. */
3965 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3966 && i.rm.mode != 3
3967 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3968 {
3969 p = frag_more (1);
3970 md_number_to_chars (p,
3971 (valueT) (i.sib.base << 0
3972 | i.sib.index << 3
3973 | i.sib.scale << 6),
3974 1);
3975 }
3976 }
3e73aa7c 3977
29b0f896 3978 if (i.disp_operands)
2bbd9c25 3979 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3980
29b0f896 3981 if (i.imm_operands)
2bbd9c25 3982 output_imm (insn_start_frag, insn_start_off);
29b0f896 3983 }
252b5132 3984
29b0f896
AM		 3985#ifdef DEBUG386
3986 if (flag_debug)
3987 {
7b81dfbb 3988 pi ("" /*line*/, &i);
29b0f896
AM		 3989 }
3990#endif /* DEBUG386 */
3991}
252b5132 3992
29b0f896 3993static void
64e74474 3994output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3995{
3996 char *p;
3997 unsigned int n;
252b5132 3998
29b0f896
AM		 3999 for (n = 0; n < i.operands; n++)
4000 {
4001 if (i.types[n] & Disp)
4002 {
4003 if (i.op[n].disps->X_op == O_constant)
4004 {
4005 int size;
4006 offsetT val;
252b5132 4007
29b0f896
AM		 4008 size = 4;
4009 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4010 {
4011 size = 2;
4012 if (i.types[n] & Disp8)
4013 size = 1;
4014 if (i.types[n] & Disp64)
4015 size = 8;
4016 }
4017 val = offset_in_range (i.op[n].disps->X_add_number,
4018 size);
4019 p = frag_more (size);
4020 md_number_to_chars (p, val, size);
4021 }
4022 else
4023 {
f86103b7 4024 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4025 int size = 4;
4026 int sign = 0;
4027 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4028
4029 /* The PC relative address is computed relative
4030 to the instruction boundary, so in case immediate
4031 fields follows, we need to adjust the value. */
4032 if (pcrel && i.imm_operands)
4033 {
4034 int imm_size = 4;
4035 unsigned int n1;
252b5132 4036
29b0f896
AM		 4037 for (n1 = 0; n1 < i.operands; n1++)
4038 if (i.types[n1] & Imm)
252b5132 4039 {
29b0f896 4040 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4041 {
29b0f896
AM		 4042 imm_size = 2;
4043 if (i.types[n1] & (Imm8 | Imm8S))
4044 imm_size = 1;
4045 if (i.types[n1] & Imm64)
4046 imm_size = 8;
252b5132 4047 }
29b0f896 4048 break;
252b5132 4049 }
29b0f896
AM		 4050 /* We should find the immediate. */
4051 if (n1 == i.operands)
4052 abort ();
4053 i.op[n].disps->X_add_number -= imm_size;
4054 }
520dc8e8 4055
29b0f896
AM		 4056 if (i.types[n] & Disp32S)
4057 sign = 1;
3e73aa7c 4058
29b0f896
AM		 4059 if (i.types[n] & (Disp16 | Disp64))
4060 {
4061 size = 2;
4062 if (i.types[n] & Disp64)
4063 size = 8;
4064 }
520dc8e8 4065
29b0f896 4066 p = frag_more (size);
2bbd9c25 4067 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4068 if (GOT_symbol
2bbd9c25 4069 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4070 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4071 || reloc_type == BFD_RELOC_X86_64_32S
4072 || (reloc_type == BFD_RELOC_64
4073 && object_64bit))
d6ab8113
JB		 4074 && (i.op[n].disps->X_op == O_symbol
4075 || (i.op[n].disps->X_op == O_add
4076 && ((symbol_get_value_expression
4077 (i.op[n].disps->X_op_symbol)->X_op)
4078 == O_subtract))))
4079 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4080 {
4081 offsetT add;
4082
4083 if (insn_start_frag == frag_now)
4084 add = (p - frag_now->fr_literal) - insn_start_off;
4085 else
4086 {
4087 fragS *fr;
4088
4089 add = insn_start_frag->fr_fix - insn_start_off;
4090 for (fr = insn_start_frag->fr_next;
4091 fr && fr != frag_now; fr = fr->fr_next)
4092 add += fr->fr_fix;
4093 add += p - frag_now->fr_literal;
4094 }
4095
4fa24527 4096 if (!object_64bit)
7b81dfbb
AJ		 4097 {
4098 reloc_type = BFD_RELOC_386_GOTPC;
4099 i.op[n].imms->X_add_number += add;
4100 }
4101 else if (reloc_type == BFD_RELOC_64)
4102 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4103 else
7b81dfbb
AJ		 4104 /* Don't do the adjustment for x86-64, as there
4105 the pcrel addressing is relative to the _next_
4106 insn, and that is taken care of in other code. */
d6ab8113 4107 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4108 }
062cd5e7 4109 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4110 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4111 }
4112 }
4113 }
4114}
252b5132 4115
29b0f896 4116static void
64e74474 4117output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4118{
4119 char *p;
4120 unsigned int n;
252b5132 4121
29b0f896
AM		 4122 for (n = 0; n < i.operands; n++)
4123 {
4124 if (i.types[n] & Imm)
4125 {
4126 if (i.op[n].imms->X_op == O_constant)
4127 {
4128 int size;
4129 offsetT val;
b4cac588 4130
29b0f896
AM		 4131 size = 4;
4132 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4133 {
4134 size = 2;
4135 if (i.types[n] & (Imm8 | Imm8S))
4136 size = 1;
4137 else if (i.types[n] & Imm64)
4138 size = 8;
4139 }
4140 val = offset_in_range (i.op[n].imms->X_add_number,
4141 size);
4142 p = frag_more (size);
4143 md_number_to_chars (p, val, size);
4144 }
4145 else
4146 {
4147 /* Not absolute_section.
4148 Need a 32-bit fixup (don't support 8bit
4149 non-absolute imms). Try to support other
4150 sizes ... */
f86103b7 4151 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4152 int size = 4;
4153 int sign = 0;
4154
4155 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4156 && (i.suffix == QWORD_MNEM_SUFFIX
4157 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4158 sign = 1;
4159 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4160 {
4161 size = 2;
4162 if (i.types[n] & (Imm8 | Imm8S))
4163 size = 1;
4164 if (i.types[n] & Imm64)
4165 size = 8;
4166 }
520dc8e8 4167
29b0f896
AM		 4168 p = frag_more (size);
4169 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4170
2bbd9c25
JJ		 4171 /* This is tough to explain. We end up with this one if we
4172 * have operands that look like
4173 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4174 * obtain the absolute address of the GOT, and it is strongly
4175 * preferable from a performance point of view to avoid using
4176 * a runtime relocation for this. The actual sequence of
4177 * instructions often look something like:
4178 *
4179 * call .L66
4180 * .L66:
4181 * popl %ebx
4182 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4183 *
4184 * The call and pop essentially return the absolute address
4185 * of the label .L66 and store it in %ebx. The linker itself
4186 * will ultimately change the first operand of the addl so
4187 * that %ebx points to the GOT, but to keep things simple, the
4188 * .o file must have this operand set so that it generates not
4189 * the absolute address of .L66, but the absolute address of
4190 * itself. This allows the linker itself simply treat a GOTPC
4191 * relocation as asking for a pcrel offset to the GOT to be
4192 * added in, and the addend of the relocation is stored in the
4193 * operand field for the instruction itself.
4194 *
4195 * Our job here is to fix the operand so that it would add
4196 * the correct offset so that %ebx would point to itself. The
4197 * thing that is tricky is that .-.L66 will point to the
4198 * beginning of the instruction, so we need to further modify
4199 * the operand so that it will point to itself. There are
4200 * other cases where you have something like:
4201 *
4202 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4203 *
4204 * and here no correction would be required. Internally in
4205 * the assembler we treat operands of this form as not being
4206 * pcrel since the '.' is explicitly mentioned, and I wonder
4207 * whether it would simplify matters to do it this way. Who
4208 * knows. In earlier versions of the PIC patches, the
4209 * pcrel_adjust field was used to store the correction, but
4210 * since the expression is not pcrel, I felt it would be
4211 * confusing to do it this way. */
4212
d6ab8113 4213 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4214 || reloc_type == BFD_RELOC_X86_64_32S
4215 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4216 && GOT_symbol
4217 && GOT_symbol == i.op[n].imms->X_add_symbol
4218 && (i.op[n].imms->X_op == O_symbol
4219 || (i.op[n].imms->X_op == O_add
4220 && ((symbol_get_value_expression
4221 (i.op[n].imms->X_op_symbol)->X_op)
4222 == O_subtract))))
4223 {
2bbd9c25
JJ		 4224 offsetT add;
4225
4226 if (insn_start_frag == frag_now)
4227 add = (p - frag_now->fr_literal) - insn_start_off;
4228 else
4229 {
4230 fragS *fr;
4231
4232 add = insn_start_frag->fr_fix - insn_start_off;
4233 for (fr = insn_start_frag->fr_next;
4234 fr && fr != frag_now; fr = fr->fr_next)
4235 add += fr->fr_fix;
4236 add += p - frag_now->fr_literal;
4237 }
4238
4fa24527 4239 if (!object_64bit)
d6ab8113 4240 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4241 else if (size == 4)
d6ab8113 4242 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4243 else if (size == 8)
4244 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4245 i.op[n].imms->X_add_number += add;
29b0f896 4246 }
29b0f896
AM		 4247 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4248 i.op[n].imms, 0, reloc_type);
4249 }
4250 }
4251 }
252b5132
RH		 4252}
4253\f
d182319b
JB		 4254/* x86_cons_fix_new is called via the expression parsing code when a
4255 reloc is needed. We use this hook to get the correct .got reloc. */
4256static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4257static int cons_sign = -1;
4258
4259void
4260x86_cons_fix_new (fragS *frag,
64e74474
AM		 4261 unsigned int off,
4262 unsigned int len,
4263 expressionS *exp)
d182319b
JB		 4264{
4265 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4266
4267 got_reloc = NO_RELOC;
4268
4269#ifdef TE_PE
4270 if (exp->X_op == O_secrel)
4271 {
4272 exp->X_op = O_symbol;
4273 r = BFD_RELOC_32_SECREL;
4274 }
4275#endif
4276
4277 fix_new_exp (frag, off, len, exp, 0, r);
4278}
4279
718ddfc0
JB		 4280#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4281# define lex_got(reloc, adjust, types) NULL
4282#else
f3c180ae
AM		 4283/* Parse operands of the form
4284 <symbol>@GOTOFF+<nnn>
4285 and similar .plt or .got references.
4286
4287 If we find one, set up the correct relocation in RELOC and copy the
4288 input string, minus the `@GOTOFF' into a malloc'd buffer for
4289 parsing by the calling routine. Return this buffer, and if ADJUST
4290 is non-null set it to the length of the string we removed from the
4291 input line. Otherwise return NULL. */
4292static char *
3956db08 4293lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4294 int *adjust,
4295 unsigned int *types)
f3c180ae 4296{
7b81dfbb
AJ		 4297 /* Some of the relocations depend on the size of what field is to
4298 be relocated. But in our callers i386_immediate and i386_displacement
4299 we don't yet know the operand size (this will be set by insn
4300 matching). Hence we record the word32 relocation here,
4301 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4302 static const struct {
4303 const char *str;
4fa24527 4304 const enum bfd_reloc_code_real rel[2];
3956db08 4305 const unsigned int types64;
f3c180ae 4306 } gotrel[] = {
7b81dfbb 4307 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4308 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4309 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4310 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4311 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4312 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4313 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4314 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4315 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4316 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4317 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4318 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4319 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4320 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4321 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4322 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4323 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4324 };
4325 char *cp;
4326 unsigned int j;
4327
718ddfc0
JB		 4328 if (!IS_ELF)
4329 return NULL;
4330
f3c180ae
AM		 4331 for (cp = input_line_pointer; *cp != '@'; cp++)
4332 if (is_end_of_line[(unsigned char) *cp])
4333 return NULL;
4334
4335 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4336 {
4337 int len;
4338
4339 len = strlen (gotrel[j].str);
28f81592 4340 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4341 {
4fa24527 4342 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4343 {
28f81592
AM		 4344 int first, second;
4345 char *tmpbuf, *past_reloc;
f3c180ae 4346
4fa24527 4347 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4348 if (adjust)
4349 *adjust = len;
f3c180ae 4350
3956db08
JB		 4351 if (types)
4352 {
4353 if (flag_code != CODE_64BIT)
4354 *types = Imm32|Disp32;
4355 else
4356 *types = gotrel[j].types64;
4357 }
4358
f3c180ae
AM		 4359 if (GOT_symbol == NULL)
4360 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4361
4362 /* Replace the relocation token with ' ', so that
4363 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4364
4365 /* The length of the first part of our input line. */
f3c180ae 4366 first = cp - input_line_pointer;
28f81592
AM		 4367
4368 /* The second part goes from after the reloc token until
4369 (and including) an end_of_line char. Don't use strlen
4370 here as the end_of_line char may not be a NUL. */
4371 past_reloc = cp + 1 + len;
4372 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4373 ;
4374 second = cp - past_reloc;
4375
4376 /* Allocate and copy string. The trailing NUL shouldn't
4377 be necessary, but be safe. */
4378 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4379 memcpy (tmpbuf, input_line_pointer, first);
4380 tmpbuf[first] = ' ';
28f81592
AM		 4381 memcpy (tmpbuf + first + 1, past_reloc, second);
4382 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4383 return tmpbuf;
4384 }
4385
4fa24527
JB		 4386 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4387 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4388 return NULL;
4389 }
4390 }
4391
4392 /* Might be a symbol version string. Don't as_bad here. */
4393 return NULL;
4394}
4395
f3c180ae
AM		 4396void
4397x86_cons (exp, size)
4398 expressionS *exp;
4399 int size;
4400{
4fa24527 4401 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4402 {
4403 /* Handle @GOTOFF and the like in an expression. */
4404 char *save;
4405 char *gotfree_input_line;
4406 int adjust;
4407
4408 save = input_line_pointer;
3956db08 4409 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4410 if (gotfree_input_line)
4411 input_line_pointer = gotfree_input_line;
4412
4413 expression (exp);
4414
4415 if (gotfree_input_line)
4416 {
4417 /* expression () has merrily parsed up to the end of line,
4418 or a comma - in the wrong buffer. Transfer how far
4419 input_line_pointer has moved to the right buffer. */
4420 input_line_pointer = (save
4421 + (input_line_pointer - gotfree_input_line)
4422 + adjust);
4423 free (gotfree_input_line);
4424 }
4425 }
4426 else
4427 expression (exp);
4428}
4429#endif
4430
d182319b 4431static void signed_cons (int size)
6482c264 4432{
d182319b
JB		 4433 if (flag_code == CODE_64BIT)
4434 cons_sign = 1;
4435 cons (size);
4436 cons_sign = -1;
6482c264
NC		 4437}
4438
d182319b 4439#ifdef TE_PE
6482c264
NC		 4440static void
4441pe_directive_secrel (dummy)
4442 int dummy ATTRIBUTE_UNUSED;
4443{
4444 expressionS exp;
4445
4446 do
4447 {
4448 expression (&exp);
4449 if (exp.X_op == O_symbol)
4450 exp.X_op = O_secrel;
4451
4452 emit_expr (&exp, 4);
4453 }
4454 while (*input_line_pointer++ == ',');
4455
4456 input_line_pointer--;
4457 demand_empty_rest_of_line ();
4458}
6482c264
NC		 4459#endif
4460
252b5132
RH		 4461static int i386_immediate PARAMS ((char *));
4462
4463static int
4464i386_immediate (imm_start)
4465 char *imm_start;
4466{
4467 char *save_input_line_pointer;
f3c180ae 4468 char *gotfree_input_line;
252b5132 4469 segT exp_seg = 0;
47926f60 4470 expressionS *exp;
3956db08 4471 unsigned int types = ~0U;
252b5132
RH		 4472
4473 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4474 {
d0b47220 4475 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4476 return 0;
4477 }
4478
4479 exp = &im_expressions[i.imm_operands++];
520dc8e8 4480 i.op[this_operand].imms = exp;
252b5132
RH		 4481
4482 if (is_space_char (*imm_start))
4483 ++imm_start;
4484
4485 save_input_line_pointer = input_line_pointer;
4486 input_line_pointer = imm_start;
4487
3956db08 4488 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4489 if (gotfree_input_line)
4490 input_line_pointer = gotfree_input_line;
252b5132
RH		 4491
4492 exp_seg = expression (exp);
4493
83183c0c 4494 SKIP_WHITESPACE ();
252b5132 4495 if (*input_line_pointer)
f3c180ae 4496 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4497
4498 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4499 if (gotfree_input_line)
4500 free (gotfree_input_line);
252b5132 4501
2daf4fd8 4502 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4503 {
47926f60 4504 /* Missing or bad expr becomes absolute 0. */
d0b47220 4505 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4506 imm_start);
252b5132
RH		 4507 exp->X_op = O_constant;
4508 exp->X_add_number = 0;
4509 exp->X_add_symbol = (symbolS *) 0;
4510 exp->X_op_symbol = (symbolS *) 0;
252b5132 4511 }
3e73aa7c 4512 else if (exp->X_op == O_constant)
252b5132 4513 {
47926f60 4514 /* Size it properly later. */
3e73aa7c
JH		 4515 i.types[this_operand] |= Imm64;
4516 /* If BFD64, sign extend val. */
4517 if (!use_rela_relocations)
4518 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4519 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4520 }
4c63da97 4521#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4522 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4523 && exp_seg != absolute_section
47926f60 4524 && exp_seg != text_section
24eab124
AM		 4525 && exp_seg != data_section
4526 && exp_seg != bss_section
4527 && exp_seg != undefined_section
f86103b7 4528 && !bfd_is_com_section (exp_seg))
252b5132 4529 {
d0b47220 4530 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4531 return 0;
4532 }
4533#endif
bb8f5920
L		 4534 else if (!intel_syntax && exp->X_op == O_register)
4535 {
4536 as_bad (_("illegal immediate register operand %s"), imm_start);
4537 return 0;
4538 }
252b5132
RH		 4539 else
4540 {
4541 /* This is an address. The size of the address will be
24eab124 4542 determined later, depending on destination register,
3e73aa7c
JH		 4543 suffix, or the default for the section. */
4544 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4545 i.types[this_operand] &= types;
252b5132
RH		 4546 }
4547
4548 return 1;
4549}
4550
551c1ca1 4551static char *i386_scale PARAMS ((char *));
252b5132 4552
551c1ca1 4553static char *
252b5132
RH		 4554i386_scale (scale)
4555 char *scale;
4556{
551c1ca1
AM		 4557 offsetT val;
4558 char *save = input_line_pointer;
252b5132 4559
551c1ca1
AM		 4560 input_line_pointer = scale;
4561 val = get_absolute_expression ();
4562
4563 switch (val)
252b5132 4564 {
551c1ca1 4565 case 1:
252b5132
RH		 4566 i.log2_scale_factor = 0;
4567 break;
551c1ca1 4568 case 2:
252b5132
RH		 4569 i.log2_scale_factor = 1;
4570 break;
551c1ca1 4571 case 4:
252b5132
RH		 4572 i.log2_scale_factor = 2;
4573 break;
551c1ca1 4574 case 8:
252b5132
RH		 4575 i.log2_scale_factor = 3;
4576 break;
4577 default:
a724f0f4
JB		 4578 {
4579 char sep = *input_line_pointer;
4580
4581 *input_line_pointer = '\0';
4582 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4583 scale);
4584 *input_line_pointer = sep;
4585 input_line_pointer = save;
4586 return NULL;
4587 }
252b5132 4588 }
29b0f896 4589 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4590 {
4591 as_warn (_("scale factor of %d without an index register"),
24eab124 4592 1 << i.log2_scale_factor);
252b5132
RH		 4593#if SCALE1_WHEN_NO_INDEX
4594 i.log2_scale_factor = 0;
4595#endif
4596 }
551c1ca1
AM		 4597 scale = input_line_pointer;
4598 input_line_pointer = save;
4599 return scale;
252b5132
RH		 4600}
4601
4602static int i386_displacement PARAMS ((char *, char *));
4603
4604static int
4605i386_displacement (disp_start, disp_end)
4606 char *disp_start;
4607 char *disp_end;
4608{
29b0f896 4609 expressionS *exp;
252b5132
RH		 4610 segT exp_seg = 0;
4611 char *save_input_line_pointer;
f3c180ae 4612 char *gotfree_input_line;
e05278af 4613 int bigdisp, override;
3956db08 4614 unsigned int types = Disp;
252b5132 4615
e05278af
JB		 4616 if ((i.types[this_operand] & JumpAbsolute)
4617 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4618 {
4619 bigdisp = Disp32;
4620 override = (i.prefix[ADDR_PREFIX] != 0);
4621 }
4622 else
4623 {
4624 /* For PC-relative branches, the width of the displacement
4625 is dependent upon data size, not address size. */
4626 bigdisp = 0;
4627 override = (i.prefix[DATA_PREFIX] != 0);
4628 }
3e73aa7c 4629 if (flag_code == CODE_64BIT)
7ecd2f8b 4630 {
e05278af 4631 if (!bigdisp)
64e74474
AM		 4632 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4633 ? Disp16
4634 : Disp32S | Disp32);
e05278af 4635 else if (!override)
3956db08 4636 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4637 }
e05278af
JB		 4638 else
4639 {
4640 if (!bigdisp)
4641 {
4642 if (!override)
4643 override = (i.suffix == (flag_code != CODE_16BIT
4644 ? WORD_MNEM_SUFFIX
4645 : LONG_MNEM_SUFFIX));
4646 bigdisp = Disp32;
4647 }
4648 if ((flag_code == CODE_16BIT) ^ override)
4649 bigdisp = Disp16;
4650 }
252b5132
RH		 4651 i.types[this_operand] |= bigdisp;
4652
4653 exp = &disp_expressions[i.disp_operands];
520dc8e8 4654 i.op[this_operand].disps = exp;
252b5132
RH		 4655 i.disp_operands++;
4656 save_input_line_pointer = input_line_pointer;
4657 input_line_pointer = disp_start;
4658 END_STRING_AND_SAVE (disp_end);
4659
4660#ifndef GCC_ASM_O_HACK
4661#define GCC_ASM_O_HACK 0
4662#endif
4663#if GCC_ASM_O_HACK
4664 END_STRING_AND_SAVE (disp_end + 1);
4665 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4666 && displacement_string_end[-1] == '+')
252b5132
RH		 4667 {
4668 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4669 constraint within gcc asm statements.
4670 For instance:
4671
4672 #define _set_tssldt_desc(n,addr,limit,type) \
4673 __asm__ __volatile__ ( \
4674 "movw %w2,%0\n\t" \
4675 "movw %w1,2+%0\n\t" \
4676 "rorl $16,%1\n\t" \
4677 "movb %b1,4+%0\n\t" \
4678 "movb %4,5+%0\n\t" \
4679 "movb $0,6+%0\n\t" \
4680 "movb %h1,7+%0\n\t" \
4681 "rorl $16,%1" \
4682 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4683
4684 This works great except that the output assembler ends
4685 up looking a bit weird if it turns out that there is
4686 no offset. You end up producing code that looks like:
4687
4688 #APP
4689 movw $235,(%eax)
4690 movw %dx,2+(%eax)
4691 rorl $16,%edx
4692 movb %dl,4+(%eax)
4693 movb $137,5+(%eax)
4694 movb $0,6+(%eax)
4695 movb %dh,7+(%eax)
4696 rorl $16,%edx
4697 #NO_APP
4698
47926f60 4699 So here we provide the missing zero. */
24eab124
AM		 4700
4701 *displacement_string_end = '0';
252b5132
RH		 4702 }
4703#endif
3956db08 4704 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4705 if (gotfree_input_line)
4706 input_line_pointer = gotfree_input_line;
252b5132 4707
24eab124 4708 exp_seg = expression (exp);
252b5132 4709
636c26b0
AM		 4710 SKIP_WHITESPACE ();
4711 if (*input_line_pointer)
4712 as_bad (_("junk `%s' after expression"), input_line_pointer);
4713#if GCC_ASM_O_HACK
4714 RESTORE_END_STRING (disp_end + 1);
4715#endif
4716 RESTORE_END_STRING (disp_end);
4717 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4718 if (gotfree_input_line)
4719 free (gotfree_input_line);
636c26b0 4720
24eab124
AM		 4721 /* We do this to make sure that the section symbol is in
4722 the symbol table. We will ultimately change the relocation
47926f60 4723 to be relative to the beginning of the section. */
1ae12ab7 4724 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4725 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4726 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4727 {
636c26b0
AM		 4728 if (exp->X_op != O_symbol)
4729 {
4730 as_bad (_("bad expression used with @%s"),
4731 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4732 ? "GOTPCREL"
4733 : "GOTOFF"));
4734 return 0;
4735 }
4736
e5cb08ac 4737 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4738 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4739 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4740 exp->X_op = O_subtract;
4741 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4742 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4743 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4744 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4745 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4746 else
29b0f896 4747 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4748 }
252b5132 4749
2daf4fd8
AM		 4750 if (exp->X_op == O_absent || exp->X_op == O_big)
4751 {
47926f60 4752 /* Missing or bad expr becomes absolute 0. */
d0b47220 4753 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4754 disp_start);
4755 exp->X_op = O_constant;
4756 exp->X_add_number = 0;
4757 exp->X_add_symbol = (symbolS *) 0;
4758 exp->X_op_symbol = (symbolS *) 0;
4759 }
4760
4c63da97 4761#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4762 if (exp->X_op != O_constant
45288df1 4763 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4764 && exp_seg != absolute_section
45288df1
AM		 4765 && exp_seg != text_section
4766 && exp_seg != data_section
4767 && exp_seg != bss_section
31312f95 4768 && exp_seg != undefined_section
f86103b7 4769 && !bfd_is_com_section (exp_seg))
24eab124 4770 {
d0b47220 4771 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4772 return 0;
4773 }
252b5132 4774#endif
3956db08
JB		 4775
4776 if (!(i.types[this_operand] & ~Disp))
4777 i.types[this_operand] &= types;
4778
252b5132
RH		 4779 return 1;
4780}
4781
e5cb08ac 4782static int i386_index_check PARAMS ((const char *));
252b5132 4783
eecb386c 4784/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4785 Return 1 on success, 0 on a failure. */
4786
252b5132 4787static int
eecb386c
AM		 4788i386_index_check (operand_string)
4789 const char *operand_string;
252b5132 4790{
3e73aa7c 4791 int ok;
24eab124 4792#if INFER_ADDR_PREFIX
eecb386c
AM		 4793 int fudged = 0;
4794
24eab124
AM		 4795 tryprefix:
4796#endif
3e73aa7c 4797 ok = 1;
30123838
JB		 4798 if ((current_templates->start->cpu_flags & CpuSVME)
4799 && current_templates->end[-1].operand_types[0] == AnyMem)
4800 {
4801 /* Memory operands of SVME insns are special in that they only allow
4802 rAX as their memory address and ignore any segment override. */
4803 unsigned RegXX;
4804
4805 /* SKINIT is even more restrictive: it always requires EAX. */
4806 if (strcmp (current_templates->start->name, "skinit") == 0)
4807 RegXX = Reg32;
4808 else if (flag_code == CODE_64BIT)
4809 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4810 else
64e74474
AM		 4811 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4812 ? Reg16
4813 : Reg32);
30123838
JB		 4814 if (!i.base_reg
4815 || !(i.base_reg->reg_type & Acc)
4816 || !(i.base_reg->reg_type & RegXX)
4817 || i.index_reg
4818 || (i.types[0] & Disp))
4819 ok = 0;
4820 }
4821 else if (flag_code == CODE_64BIT)
64e74474
AM		 4822 {
4823 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4824
4825 if ((i.base_reg
4826 && ((i.base_reg->reg_type & RegXX) == 0)
4827 && (i.base_reg->reg_type != BaseIndex
4828 || i.index_reg))
4829 || (i.index_reg
4830 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4831 != (RegXX | BaseIndex))))
4832 ok = 0;
3e73aa7c
JH		 4833 }
4834 else
4835 {
4836 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4837 {
4838 /* 16bit checks. */
4839 if ((i.base_reg
29b0f896
AM		 4840 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4841 != (Reg16 | BaseIndex)))
3e73aa7c 4842 || (i.index_reg
29b0f896
AM		 4843 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4844 != (Reg16 | BaseIndex))
4845 || !(i.base_reg
4846 && i.base_reg->reg_num < 6
4847 && i.index_reg->reg_num >= 6
4848 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4849 ok = 0;
4850 }
4851 else
e5cb08ac 4852 {
3e73aa7c
JH		 4853 /* 32bit checks. */
4854 if ((i.base_reg
4855 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4856 || (i.index_reg
29b0f896
AM		 4857 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4858 != (Reg32 | BaseIndex))))
e5cb08ac 4859 ok = 0;
3e73aa7c
JH		 4860 }
4861 }
4862 if (!ok)
24eab124
AM		 4863 {
4864#if INFER_ADDR_PREFIX
20f0a1fc 4865 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4866 {
4867 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4868 i.prefixes += 1;
b23bac36
AM		 4869 /* Change the size of any displacement too. At most one of
4870 Disp16 or Disp32 is set.
4871 FIXME. There doesn't seem to be any real need for separate
4872 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4873 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4874 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4875 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4876 fudged = 1;
24eab124
AM		 4877 goto tryprefix;
4878 }
eecb386c
AM		 4879 if (fudged)
4880 as_bad (_("`%s' is not a valid base/index expression"),
4881 operand_string);
4882 else
c388dee8 4883#endif
eecb386c
AM		 4884 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4885 operand_string,
3e73aa7c 4886 flag_code_names[flag_code]);
24eab124 4887 }
20f0a1fc 4888 return ok;
24eab124 4889}
252b5132 4890
252b5132 4891/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4892 on error. */
252b5132 4893
252b5132
RH		 4894static int
4895i386_operand (operand_string)
4896 char *operand_string;
4897{
af6bdddf
AM		 4898 const reg_entry *r;
4899 char *end_op;
24eab124 4900 char *op_string = operand_string;
252b5132 4901
24eab124 4902 if (is_space_char (*op_string))
252b5132
RH		 4903 ++op_string;
4904
24eab124 4905 /* We check for an absolute prefix (differentiating,
47926f60 4906 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4907 if (*op_string == ABSOLUTE_PREFIX)
4908 {
4909 ++op_string;
4910 if (is_space_char (*op_string))
4911 ++op_string;
4912 i.types[this_operand] |= JumpAbsolute;
4913 }
252b5132 4914
47926f60 4915 /* Check if operand is a register. */
4d1bb795 4916 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4917 {
24eab124
AM		 4918 /* Check for a segment override by searching for ':' after a
4919 segment register. */
4920 op_string = end_op;
4921 if (is_space_char (*op_string))
4922 ++op_string;
4923 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4924 {
4925 switch (r->reg_num)
4926 {
4927 case 0:
4928 i.seg[i.mem_operands] = &es;
4929 break;
4930 case 1:
4931 i.seg[i.mem_operands] = &cs;
4932 break;
4933 case 2:
4934 i.seg[i.mem_operands] = &ss;
4935 break;
4936 case 3:
4937 i.seg[i.mem_operands] = &ds;
4938 break;
4939 case 4:
4940 i.seg[i.mem_operands] = &fs;
4941 break;
4942 case 5:
4943 i.seg[i.mem_operands] = &gs;
4944 break;
4945 }
252b5132 4946
24eab124 4947 /* Skip the ':' and whitespace. */
252b5132
RH		 4948 ++op_string;
4949 if (is_space_char (*op_string))
24eab124 4950 ++op_string;
252b5132 4951
24eab124
AM		 4952 if (!is_digit_char (*op_string)
4953 && !is_identifier_char (*op_string)
4954 && *op_string != '('
4955 && *op_string != ABSOLUTE_PREFIX)
4956 {
4957 as_bad (_("bad memory operand `%s'"), op_string);
4958 return 0;
4959 }
47926f60 4960 /* Handle case of %es:*foo. */
24eab124
AM		 4961 if (*op_string == ABSOLUTE_PREFIX)
4962 {
4963 ++op_string;
4964 if (is_space_char (*op_string))
4965 ++op_string;
4966 i.types[this_operand] |= JumpAbsolute;
4967 }
4968 goto do_memory_reference;
4969 }
4970 if (*op_string)
4971 {
d0b47220 4972 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4973 return 0;
4974 }
4975 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4976 i.op[this_operand].regs = r;
24eab124
AM		 4977 i.reg_operands++;
4978 }
af6bdddf
AM		 4979 else if (*op_string == REGISTER_PREFIX)
4980 {
4981 as_bad (_("bad register name `%s'"), op_string);
4982 return 0;
4983 }
24eab124 4984 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4985 {
24eab124
AM		 4986 ++op_string;
4987 if (i.types[this_operand] & JumpAbsolute)
4988 {
d0b47220 4989 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4990 return 0;
4991 }
4992 if (!i386_immediate (op_string))
4993 return 0;
4994 }
4995 else if (is_digit_char (*op_string)
4996 || is_identifier_char (*op_string)
e5cb08ac 4997 || *op_string == '(')
24eab124 4998 {
47926f60 4999 /* This is a memory reference of some sort. */
af6bdddf 5000 char *base_string;
252b5132 5001
47926f60 5002 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5003 char *displacement_string_start;
5004 char *displacement_string_end;
252b5132 5005
24eab124 5006 do_memory_reference:
24eab124
AM		 5007 if ((i.mem_operands == 1
5008 && (current_templates->start->opcode_modifier & IsString) == 0)
5009 || i.mem_operands == 2)
5010 {
5011 as_bad (_("too many memory references for `%s'"),
5012 current_templates->start->name);
5013 return 0;
5014 }
252b5132 5015
24eab124
AM		 5016 /* Check for base index form. We detect the base index form by
5017 looking for an ')' at the end of the operand, searching
5018 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5019 after the '('. */
af6bdddf 5020 base_string = op_string + strlen (op_string);
c3332e24 5021
af6bdddf
AM		 5022 --base_string;
5023 if (is_space_char (*base_string))
5024 --base_string;
252b5132 5025
47926f60 5026 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5027 displacement_string_start = op_string;
5028 displacement_string_end = base_string + 1;
252b5132 5029
24eab124
AM		 5030 if (*base_string == ')')
5031 {
af6bdddf 5032 char *temp_string;
24eab124
AM		 5033 unsigned int parens_balanced = 1;
5034 /* We've already checked that the number of left & right ()'s are
47926f60 5035 equal, so this loop will not be infinite. */
24eab124
AM		 5036 do
5037 {
5038 base_string--;
5039 if (*base_string == ')')
5040 parens_balanced++;
5041 if (*base_string == '(')
5042 parens_balanced--;
5043 }
5044 while (parens_balanced);
c3332e24 5045
af6bdddf 5046 temp_string = base_string;
c3332e24 5047
24eab124 5048 /* Skip past '(' and whitespace. */
252b5132
RH		 5049 ++base_string;
5050 if (is_space_char (*base_string))
24eab124 5051 ++base_string;
252b5132 5052
af6bdddf 5053 if (*base_string == ','
4d1bb795 5054 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5055 {
af6bdddf 5056 displacement_string_end = temp_string;
252b5132 5057
af6bdddf 5058 i.types[this_operand] |= BaseIndex;
252b5132 5059
af6bdddf 5060 if (i.base_reg)
24eab124 5061 {
24eab124
AM		 5062 base_string = end_op;
5063 if (is_space_char (*base_string))
5064 ++base_string;
af6bdddf
AM		 5065 }
5066
5067 /* There may be an index reg or scale factor here. */
5068 if (*base_string == ',')
5069 {
5070 ++base_string;
5071 if (is_space_char (*base_string))
5072 ++base_string;
5073
4d1bb795 5074 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5075 {
af6bdddf 5076 base_string = end_op;
24eab124
AM		 5077 if (is_space_char (*base_string))
5078 ++base_string;
af6bdddf
AM		 5079 if (*base_string == ',')
5080 {
5081 ++base_string;
5082 if (is_space_char (*base_string))
5083 ++base_string;
5084 }
e5cb08ac 5085 else if (*base_string != ')')
af6bdddf
AM		 5086 {
5087 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5088 operand_string);
5089 return 0;
5090 }
24eab124 5091 }
af6bdddf 5092 else if (*base_string == REGISTER_PREFIX)
24eab124 5093 {
af6bdddf 5094 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5095 return 0;
5096 }
252b5132 5097
47926f60 5098 /* Check for scale factor. */
551c1ca1 5099 if (*base_string != ')')
af6bdddf 5100 {
551c1ca1
AM		 5101 char *end_scale = i386_scale (base_string);
5102
5103 if (!end_scale)
af6bdddf 5104 return 0;
24eab124 5105
551c1ca1 5106 base_string = end_scale;
af6bdddf
AM		 5107 if (is_space_char (*base_string))
5108 ++base_string;
5109 if (*base_string != ')')
5110 {
5111 as_bad (_("expecting `)' after scale factor in `%s'"),
5112 operand_string);
5113 return 0;
5114 }
5115 }
5116 else if (!i.index_reg)
24eab124 5117 {
af6bdddf
AM		 5118 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5119 *base_string);
24eab124
AM		 5120 return 0;
5121 }
5122 }
af6bdddf 5123 else if (*base_string != ')')
24eab124 5124 {
af6bdddf
AM		 5125 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5126 operand_string);
24eab124
AM		 5127 return 0;
5128 }
c3332e24 5129 }
af6bdddf 5130 else if (*base_string == REGISTER_PREFIX)
c3332e24 5131 {
af6bdddf 5132 as_bad (_("bad register name `%s'"), base_string);
24eab124 5133 return 0;
c3332e24 5134 }
24eab124
AM		 5135 }
5136
5137 /* If there's an expression beginning the operand, parse it,
5138 assuming displacement_string_start and
5139 displacement_string_end are meaningful. */
5140 if (displacement_string_start != displacement_string_end)
5141 {
5142 if (!i386_displacement (displacement_string_start,
5143 displacement_string_end))
5144 return 0;
5145 }
5146
5147 /* Special case for (%dx) while doing input/output op. */
5148 if (i.base_reg
5149 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5150 && i.index_reg == 0
5151 && i.log2_scale_factor == 0
5152 && i.seg[i.mem_operands] == 0
5153 && (i.types[this_operand] & Disp) == 0)
5154 {
5155 i.types[this_operand] = InOutPortReg;
5156 return 1;
5157 }
5158
eecb386c
AM		 5159 if (i386_index_check (operand_string) == 0)
5160 return 0;
24eab124
AM		 5161 i.mem_operands++;
5162 }
5163 else
ce8a8b2f
AM		 5164 {
5165 /* It's not a memory operand; argh! */
24eab124
AM		 5166 as_bad (_("invalid char %s beginning operand %d `%s'"),
5167 output_invalid (*op_string),
5168 this_operand + 1,
5169 op_string);
5170 return 0;
5171 }
47926f60 5172 return 1; /* Normal return. */
252b5132
RH		 5173}
5174\f
ee7fcc42
AM		 5175/* md_estimate_size_before_relax()
5176
5177 Called just before relax() for rs_machine_dependent frags. The x86
5178 assembler uses these frags to handle variable size jump
5179 instructions.
5180
5181 Any symbol that is now undefined will not become defined.
5182 Return the correct fr_subtype in the frag.
5183 Return the initial "guess for variable size of frag" to caller.
5184 The guess is actually the growth beyond the fixed part. Whatever
5185 we do to grow the fixed or variable part contributes to our
5186 returned value. */
5187
252b5132
RH		 5188int
5189md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5190 fragS *fragP;
5191 segT segment;
252b5132 5192{
252b5132 5193 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5194 check for un-relaxable symbols. On an ELF system, we can't relax
5195 an externally visible symbol, because it may be overridden by a
5196 shared library. */
5197 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5198#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5199 || (IS_ELF
31312f95
AM		 5200 && (S_IS_EXTERNAL (fragP->fr_symbol)
5201 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5202#endif
5203 )
252b5132 5204 {
b98ef147
AM		 5205 /* Symbol is undefined in this segment, or we need to keep a
5206 reloc so that weak symbols can be overridden. */
5207 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5208 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5209 unsigned char *opcode;
5210 int old_fr_fix;
f6af82bd 5211
ee7fcc42
AM		 5212 if (fragP->fr_var != NO_RELOC)
5213 reloc_type = fragP->fr_var;
b98ef147 5214 else if (size == 2)
f6af82bd
AM		 5215 reloc_type = BFD_RELOC_16_PCREL;
5216 else
5217 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5218
ee7fcc42
AM		 5219 old_fr_fix = fragP->fr_fix;
5220 opcode = (unsigned char *) fragP->fr_opcode;
5221
fddf5b5b 5222 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5223 {
fddf5b5b
AM		 5224 case UNCOND_JUMP:
5225 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5226 opcode[0] = 0xe9;
252b5132 5227 fragP->fr_fix += size;
062cd5e7
AS		 5228 fix_new (fragP, old_fr_fix, size,
5229 fragP->fr_symbol,
5230 fragP->fr_offset, 1,
5231 reloc_type);
252b5132
RH		 5232 break;
5233
fddf5b5b 5234 case COND_JUMP86:
412167cb
AM		 5235 if (size == 2
5236 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5237 {
5238 /* Negate the condition, and branch past an
5239 unconditional jump. */
5240 opcode[0] ^= 1;
5241 opcode[1] = 3;
5242 /* Insert an unconditional jump. */
5243 opcode[2] = 0xe9;
5244 /* We added two extra opcode bytes, and have a two byte
5245 offset. */
5246 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5247 fix_new (fragP, old_fr_fix + 2, 2,
5248 fragP->fr_symbol,
5249 fragP->fr_offset, 1,
5250 reloc_type);
fddf5b5b
AM		 5251 break;
5252 }
5253 /* Fall through. */
5254
5255 case COND_JUMP:
412167cb
AM		 5256 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5257 {
3e02c1cc
AM		 5258 fixS *fixP;
5259
412167cb 5260 fragP->fr_fix += 1;
3e02c1cc
AM		 5261 fixP = fix_new (fragP, old_fr_fix, 1,
5262 fragP->fr_symbol,
5263 fragP->fr_offset, 1,
5264 BFD_RELOC_8_PCREL);
5265 fixP->fx_signed = 1;
412167cb
AM		 5266 break;
5267 }
93c2a809 5268
24eab124 5269 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5270 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5271 opcode[1] = opcode[0] + 0x10;
f6af82bd 5272 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5273 /* We've added an opcode byte. */
5274 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5275 fix_new (fragP, old_fr_fix + 1, size,
5276 fragP->fr_symbol,
5277 fragP->fr_offset, 1,
5278 reloc_type);
252b5132 5279 break;
fddf5b5b
AM		 5280
5281 default:
5282 BAD_CASE (fragP->fr_subtype);
5283 break;
252b5132
RH		 5284 }
5285 frag_wane (fragP);
ee7fcc42 5286 return fragP->fr_fix - old_fr_fix;
252b5132 5287 }
93c2a809 5288
93c2a809
AM		 5289 /* Guess size depending on current relax state. Initially the relax
5290 state will correspond to a short jump and we return 1, because
5291 the variable part of the frag (the branch offset) is one byte
5292 long. However, we can relax a section more than once and in that
5293 case we must either set fr_subtype back to the unrelaxed state,
5294 or return the value for the appropriate branch. */
5295 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5296}
5297
47926f60
KH		 5298/* Called after relax() is finished.
5299
5300 In: Address of frag.
5301 fr_type == rs_machine_dependent.
5302 fr_subtype is what the address relaxed to.
5303
5304 Out: Any fixSs and constants are set up.
5305 Caller will turn frag into a ".space 0". */
5306
252b5132
RH		 5307void
5308md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5309 bfd *abfd ATTRIBUTE_UNUSED;
5310 segT sec ATTRIBUTE_UNUSED;
29b0f896 5311 fragS *fragP;
252b5132 5312{
29b0f896 5313 unsigned char *opcode;
252b5132 5314 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5315 offsetT target_address;
5316 offsetT opcode_address;
252b5132 5317 unsigned int extension = 0;
847f7ad4 5318 offsetT displacement_from_opcode_start;
252b5132
RH		 5319
5320 opcode = (unsigned char *) fragP->fr_opcode;
5321
47926f60 5322 /* Address we want to reach in file space. */
252b5132 5323 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5324
47926f60 5325 /* Address opcode resides at in file space. */
252b5132
RH		 5326 opcode_address = fragP->fr_address + fragP->fr_fix;
5327
47926f60 5328 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5329 displacement_from_opcode_start = target_address - opcode_address;
5330
fddf5b5b 5331 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5332 {
47926f60
KH		 5333 /* Don't have to change opcode. */
5334 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5335 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5336 }
5337 else
5338 {
5339 if (no_cond_jump_promotion
5340 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5341 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5342
fddf5b5b
AM		 5343 switch (fragP->fr_subtype)
5344 {
5345 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5346 extension = 4; /* 1 opcode + 4 displacement */
5347 opcode[0] = 0xe9;
5348 where_to_put_displacement = &opcode[1];
5349 break;
252b5132 5350
fddf5b5b
AM		 5351 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5352 extension = 2; /* 1 opcode + 2 displacement */
5353 opcode[0] = 0xe9;
5354 where_to_put_displacement = &opcode[1];
5355 break;
252b5132 5356
fddf5b5b
AM		 5357 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5358 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5359 extension = 5; /* 2 opcode + 4 displacement */
5360 opcode[1] = opcode[0] + 0x10;
5361 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5362 where_to_put_displacement = &opcode[2];
5363 break;
252b5132 5364
fddf5b5b
AM		 5365 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5366 extension = 3; /* 2 opcode + 2 displacement */
5367 opcode[1] = opcode[0] + 0x10;
5368 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5369 where_to_put_displacement = &opcode[2];
5370 break;
252b5132 5371
fddf5b5b
AM		 5372 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5373 extension = 4;
5374 opcode[0] ^= 1;
5375 opcode[1] = 3;
5376 opcode[2] = 0xe9;
5377 where_to_put_displacement = &opcode[3];
5378 break;
5379
5380 default:
5381 BAD_CASE (fragP->fr_subtype);
5382 break;
5383 }
252b5132 5384 }
fddf5b5b 5385
7b81dfbb
AJ		 5386 /* If size if less then four we are sure that the operand fits,
5387 but if it's 4, then it could be that the displacement is larger
5388 then -/+ 2GB. */
5389 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5390 && object_64bit
5391 && ((addressT) (displacement_from_opcode_start - extension
5392 + ((addressT) 1 << 31))
5393 > (((addressT) 2 << 31) - 1)))
5394 {
5395 as_bad_where (fragP->fr_file, fragP->fr_line,
5396 _("jump target out of range"));
5397 /* Make us emit 0. */
5398 displacement_from_opcode_start = extension;
5399 }
47926f60 5400 /* Now put displacement after opcode. */
252b5132
RH		 5401 md_number_to_chars ((char *) where_to_put_displacement,
5402 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5403 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5404 fragP->fr_fix += extension;
5405}
5406\f
47926f60
KH		 5407/* Size of byte displacement jmp. */
5408int md_short_jump_size = 2;
5409
5410/* Size of dword displacement jmp. */
5411int md_long_jump_size = 5;
252b5132 5412
252b5132
RH		 5413void
5414md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5415 char *ptr;
5416 addressT from_addr, to_addr;
ab9da554
ILT		 5417 fragS *frag ATTRIBUTE_UNUSED;
5418 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5419{
847f7ad4 5420 offsetT offset;
252b5132
RH		 5421
5422 offset = to_addr - (from_addr + 2);
47926f60
KH		 5423 /* Opcode for byte-disp jump. */
5424 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5425 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5426}
5427
5428void
5429md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5430 char *ptr;
5431 addressT from_addr, to_addr;
a38cf1db
AM		 5432 fragS *frag ATTRIBUTE_UNUSED;
5433 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5434{
847f7ad4 5435 offsetT offset;
252b5132 5436
a38cf1db
AM		 5437 offset = to_addr - (from_addr + 5);
5438 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5439 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5440}
5441\f
5442/* Apply a fixup (fixS) to segment data, once it has been determined
5443 by our caller that we have all the info we need to fix it up.
5444
5445 On the 386, immediates, displacements, and data pointers are all in
5446 the same (little-endian) format, so we don't need to care about which
5447 we are handling. */
5448
94f592af 5449void
55cf6793 5450md_apply_fix (fixP, valP, seg)
47926f60
KH		 5451 /* The fix we're to put in. */
5452 fixS *fixP;
47926f60 5453 /* Pointer to the value of the bits. */
c6682705 5454 valueT *valP;
47926f60
KH		 5455 /* Segment fix is from. */
5456 segT seg ATTRIBUTE_UNUSED;
252b5132 5457{
94f592af 5458 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5459 valueT value = *valP;
252b5132 5460
f86103b7 5461#if !defined (TE_Mach)
93382f6d
AM		 5462 if (fixP->fx_pcrel)
5463 {
5464 switch (fixP->fx_r_type)
5465 {
5865bb77
ILT		 5466 default:
5467 break;
5468
d6ab8113
JB		 5469 case BFD_RELOC_64:
5470 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5471 break;
93382f6d 5472 case BFD_RELOC_32:
ae8887b5 5473 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5474 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5475 break;
5476 case BFD_RELOC_16:
5477 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5478 break;
5479 case BFD_RELOC_8:
5480 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5481 break;
5482 }
5483 }
252b5132 5484
a161fe53 5485 if (fixP->fx_addsy != NULL
31312f95 5486 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5487 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5488 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5489 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5490 && !use_rela_relocations)
252b5132 5491 {
31312f95
AM		 5492 /* This is a hack. There should be a better way to handle this.
5493 This covers for the fact that bfd_install_relocation will
5494 subtract the current location (for partial_inplace, PC relative
5495 relocations); see more below. */
252b5132 5496#ifndef OBJ_AOUT
718ddfc0 5497 if (IS_ELF
252b5132
RH		 5498#ifdef TE_PE
5499 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5500#endif
5501 )
5502 value += fixP->fx_where + fixP->fx_frag->fr_address;
5503#endif
5504#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5505 if (IS_ELF)
252b5132 5506 {
6539b54b 5507 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5508
6539b54b 5509 if ((sym_seg == seg
2f66722d 5510 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5511 && sym_seg != absolute_section))
ae6063d4 5512 && !generic_force_reloc (fixP))
2f66722d
AM		 5513 {
5514 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5515 bfd_install_relocation subtracts them out again. I think
5516 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5517 it. FIXME. */
5518 value += fixP->fx_where + fixP->fx_frag->fr_address;
5519 }
252b5132
RH		 5520 }
5521#endif
5522#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5523 /* For some reason, the PE format does not store a
5524 section address offset for a PC relative symbol. */
5525 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5526 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5527 value += md_pcrel_from (fixP);
5528#endif
5529 }
5530
5531 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5532 and we must not disappoint it. */
252b5132 5533#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5534 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5535 switch (fixP->fx_r_type)
5536 {
5537 case BFD_RELOC_386_PLT32:
3e73aa7c 5538 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5539 /* Make the jump instruction point to the address of the operand. At
5540 runtime we merely add the offset to the actual PLT entry. */
5541 value = -4;
5542 break;
31312f95 5543
13ae64f3
JJ		 5544 case BFD_RELOC_386_TLS_GD:
5545 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5546 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5547 case BFD_RELOC_386_TLS_IE:
5548 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5549 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5550 case BFD_RELOC_X86_64_TLSGD:
5551 case BFD_RELOC_X86_64_TLSLD:
5552 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5553 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5554 value = 0; /* Fully resolved at runtime. No addend. */
5555 /* Fallthrough */
5556 case BFD_RELOC_386_TLS_LE:
5557 case BFD_RELOC_386_TLS_LDO_32:
5558 case BFD_RELOC_386_TLS_LE_32:
5559 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5560 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5561 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5562 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5563 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5564 break;
5565
67a4f2b7
AO		 5566 case BFD_RELOC_386_TLS_DESC_CALL:
5567 case BFD_RELOC_X86_64_TLSDESC_CALL:
5568 value = 0; /* Fully resolved at runtime. No addend. */
5569 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5570 fixP->fx_done = 0;
5571 return;
5572
00f7efb6
JJ		 5573 case BFD_RELOC_386_GOT32:
5574 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5575 value = 0; /* Fully resolved at runtime. No addend. */
5576 break;
47926f60
KH		 5577
5578 case BFD_RELOC_VTABLE_INHERIT:
5579 case BFD_RELOC_VTABLE_ENTRY:
5580 fixP->fx_done = 0;
94f592af 5581 return;
47926f60
KH		 5582
5583 default:
5584 break;
5585 }
5586#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5587 *valP = value;
f86103b7 5588#endif /* !defined (TE_Mach) */
3e73aa7c 5589
3e73aa7c 5590 /* Are we finished with this relocation now? */
c6682705 5591 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5592 fixP->fx_done = 1;
5593 else if (use_rela_relocations)
5594 {
5595 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5596 /* Remember value for tc_gen_reloc. */
5597 fixP->fx_addnumber = value;
3e73aa7c
JH		 5598 value = 0;
5599 }
f86103b7 5600
94f592af 5601 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5602}
252b5132 5603\f
252b5132
RH		 5604#define MAX_LITTLENUMS 6
5605
47926f60
KH		 5606/* Turn the string pointed to by litP into a floating point constant
5607 of type TYPE, and emit the appropriate bytes. The number of
5608 LITTLENUMS emitted is stored in *SIZEP. An error message is
5609 returned, or NULL on OK. */
5610
252b5132
RH		 5611char *
5612md_atof (type, litP, sizeP)
2ab9b79e 5613 int type;
252b5132
RH		 5614 char *litP;
5615 int *sizeP;
5616{
5617 int prec;
5618 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5619 LITTLENUM_TYPE *wordP;
5620 char *t;
5621
5622 switch (type)
5623 {
5624 case 'f':
5625 case 'F':
5626 prec = 2;
5627 break;
5628
5629 case 'd':
5630 case 'D':
5631 prec = 4;
5632 break;
5633
5634 case 'x':
5635 case 'X':
5636 prec = 5;
5637 break;
5638
5639 default:
5640 *sizeP = 0;
5641 return _("Bad call to md_atof ()");
5642 }
5643 t = atof_ieee (input_line_pointer, type, words);
5644 if (t)
5645 input_line_pointer = t;
5646
5647 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5648 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5649 the bigendian 386. */
5650 for (wordP = words + prec - 1; prec--;)
5651 {
5652 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5653 litP += sizeof (LITTLENUM_TYPE);
5654 }
5655 return 0;
5656}
5657\f
2d545b82 5658static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5659
252b5132
RH		 5660static char *
5661output_invalid (c)
5662 int c;
5663{
3882b010 5664 if (ISPRINT (c))
f9f21a03
L		 5665 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5666 "'%c'", c);
252b5132 5667 else
f9f21a03 5668 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5669 "(0x%x)", (unsigned char) c);
252b5132
RH		 5670 return output_invalid_buf;
5671}
5672
af6bdddf 5673/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5674
5675static const reg_entry *
4d1bb795 5676parse_real_register (char *reg_string, char **end_op)
252b5132 5677{
af6bdddf
AM		 5678 char *s = reg_string;
5679 char *p;
252b5132
RH		 5680 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5681 const reg_entry *r;
5682
5683 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5684 if (*s == REGISTER_PREFIX)
5685 ++s;
5686
5687 if (is_space_char (*s))
5688 ++s;
5689
5690 p = reg_name_given;
af6bdddf 5691 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5692 {
5693 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5694 return (const reg_entry *) NULL;
5695 s++;
252b5132
RH		 5696 }
5697
6588847e
DN		 5698 /* For naked regs, make sure that we are not dealing with an identifier.
5699 This prevents confusing an identifier like `eax_var' with register
5700 `eax'. */
5701 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5702 return (const reg_entry *) NULL;
5703
af6bdddf 5704 *end_op = s;
252b5132
RH		 5705
5706 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5707
5f47d35b 5708 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5709 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5710 {
5f47d35b
AM		 5711 if (is_space_char (*s))
5712 ++s;
5713 if (*s == '(')
5714 {
af6bdddf 5715 ++s;
5f47d35b
AM		 5716 if (is_space_char (*s))
5717 ++s;
5718 if (*s >= '0' && *s <= '7')
5719 {
5720 r = &i386_float_regtab[*s - '0'];
af6bdddf 5721 ++s;
5f47d35b
AM		 5722 if (is_space_char (*s))
5723 ++s;
5724 if (*s == ')')
5725 {
5726 *end_op = s + 1;
5727 return r;
5728 }
5f47d35b 5729 }
47926f60 5730 /* We have "%st(" then garbage. */
5f47d35b
AM		 5731 return (const reg_entry *) NULL;
5732 }
5733 }
5734
1ae00879 5735 if (r != NULL
20f0a1fc 5736 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5737 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5738 && flag_code != CODE_64BIT)
20f0a1fc 5739 return (const reg_entry *) NULL;
1ae00879 5740
252b5132
RH		 5741 return r;
5742}
4d1bb795
JB		 5743
5744/* REG_STRING starts *before* REGISTER_PREFIX. */
5745
5746static const reg_entry *
5747parse_register (char *reg_string, char **end_op)
5748{
5749 const reg_entry *r;
5750
5751 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5752 r = parse_real_register (reg_string, end_op);
5753 else
5754 r = NULL;
5755 if (!r)
5756 {
5757 char *save = input_line_pointer;
5758 char c;
5759 symbolS *symbolP;
5760
5761 input_line_pointer = reg_string;
5762 c = get_symbol_end ();
5763 symbolP = symbol_find (reg_string);
5764 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5765 {
5766 const expressionS *e = symbol_get_value_expression (symbolP);
5767
5768 know (e->X_op == O_register);
5769 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5770 r = i386_regtab + e->X_add_number;
5771 *end_op = input_line_pointer;
5772 }
5773 *input_line_pointer = c;
5774 input_line_pointer = save;
5775 }
5776 return r;
5777}
5778
5779int
5780i386_parse_name (char *name, expressionS *e, char *nextcharP)
5781{
5782 const reg_entry *r;
5783 char *end = input_line_pointer;
5784
5785 *end = *nextcharP;
5786 r = parse_register (name, &input_line_pointer);
5787 if (r && end <= input_line_pointer)
5788 {
5789 *nextcharP = *input_line_pointer;
5790 *input_line_pointer = 0;
5791 e->X_op = O_register;
5792 e->X_add_number = r - i386_regtab;
5793 return 1;
5794 }
5795 input_line_pointer = end;
5796 *end = 0;
5797 return 0;
5798}
5799
5800void
5801md_operand (expressionS *e)
5802{
5803 if (*input_line_pointer == REGISTER_PREFIX)
5804 {
5805 char *end;
5806 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5807
5808 if (r)
5809 {
5810 e->X_op = O_register;
5811 e->X_add_number = r - i386_regtab;
5812 input_line_pointer = end;
5813 }
5814 }
5815}
5816
252b5132 5817\f
4cc782b5 5818#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5819const char *md_shortopts = "kVQ:sqn";
252b5132 5820#else
12b55ccc 5821const char *md_shortopts = "qn";
252b5132 5822#endif
6e0b89ee 5823
3e73aa7c 5824#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5825#define OPTION_64 (OPTION_MD_BASE + 1)
5826#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5827#define OPTION_MARCH (OPTION_MD_BASE + 3)
5828#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5829
99ad8390
NC		 5830struct option md_longopts[] =
5831{
3e73aa7c 5832 {"32", no_argument, NULL, OPTION_32},
99ad8390 5833#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5834 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5835#endif
b3b91714 5836 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5837 {"march", required_argument, NULL, OPTION_MARCH},
5838 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5839 {NULL, no_argument, NULL, 0}
5840};
5841size_t md_longopts_size = sizeof (md_longopts);
5842
5843int
9103f4f4 5844md_parse_option (int c, char *arg)
252b5132 5845{
9103f4f4
L		 5846 unsigned int i;
5847
252b5132
RH		 5848 switch (c)
5849 {
12b55ccc
L		 5850 case 'n':
5851 optimize_align_code = 0;
5852 break;
5853
a38cf1db
AM		 5854 case 'q':
5855 quiet_warnings = 1;
252b5132
RH		 5856 break;
5857
5858#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5859 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5860 should be emitted or not. FIXME: Not implemented. */
5861 case 'Q':
252b5132
RH		 5862 break;
5863
5864 /* -V: SVR4 argument to print version ID. */
5865 case 'V':
5866 print_version_id ();
5867 break;
5868
a38cf1db
AM		 5869 /* -k: Ignore for FreeBSD compatibility. */
5870 case 'k':
252b5132 5871 break;
4cc782b5
ILT		 5872
5873 case 's':
5874 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5875 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5876 break;
99ad8390
NC		 5877#endif
5878#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5879 case OPTION_64:
5880 {
5881 const char **list, **l;
5882
3e73aa7c
JH		 5883 list = bfd_target_list ();
5884 for (l = list; *l != NULL; l++)
8620418b 5885 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5886 || strcmp (*l, "coff-x86-64") == 0
5887 || strcmp (*l, "pe-x86-64") == 0
5888 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5889 {
5890 default_arch = "x86_64";
5891 break;
5892 }
3e73aa7c 5893 if (*l == NULL)
6e0b89ee 5894 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5895 free (list);
5896 }
5897 break;
5898#endif
252b5132 5899
6e0b89ee
AM		 5900 case OPTION_32:
5901 default_arch = "i386";
5902 break;
5903
b3b91714
AM		 5904 case OPTION_DIVIDE:
5905#ifdef SVR4_COMMENT_CHARS
5906 {
5907 char *n, *t;
5908 const char *s;
5909
5910 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5911 t = n;
5912 for (s = i386_comment_chars; *s != '\0'; s++)
5913 if (*s != '/')
5914 *t++ = *s;
5915 *t = '\0';
5916 i386_comment_chars = n;
5917 }
5918#endif
5919 break;
5920
9103f4f4
L		 5921 case OPTION_MARCH:
5922 if (*arg == '.')
5923 as_fatal (_("Invalid -march= option: `%s'"), arg);
5924 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5925 {
5926 if (strcmp (arg, cpu_arch [i].name) == 0)
5927 {
ccc9c027 5928 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5929 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5930 if (!cpu_arch_tune_set)
5931 {
5932 cpu_arch_tune = cpu_arch_isa;
5933 cpu_arch_tune_flags = cpu_arch_isa_flags;
5934 }
9103f4f4
L		 5935 break;
5936 }
5937 }
5938 if (i >= ARRAY_SIZE (cpu_arch))
5939 as_fatal (_("Invalid -march= option: `%s'"), arg);
5940 break;
5941
5942 case OPTION_MTUNE:
5943 if (*arg == '.')
5944 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5945 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5946 {
5947 if (strcmp (arg, cpu_arch [i].name) == 0)
5948 {
ccc9c027 5949 cpu_arch_tune_set = 1;
9103f4f4
L		 5950 cpu_arch_tune = cpu_arch [i].type;
5951 cpu_arch_tune_flags = cpu_arch[i].flags;
5952 break;
5953 }
5954 }
5955 if (i >= ARRAY_SIZE (cpu_arch))
5956 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5957 break;
5958
252b5132
RH		 5959 default:
5960 return 0;
5961 }
5962 return 1;
5963}
5964
5965void
5966md_show_usage (stream)
5967 FILE *stream;
5968{
4cc782b5
ILT		 5969#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5970 fprintf (stream, _("\
a38cf1db
AM		 5971 -Q ignored\n\
5972 -V print assembler version number\n\
b3b91714
AM		 5973 -k ignored\n"));
5974#endif
5975 fprintf (stream, _("\
12b55ccc 5976 -n Do not optimize code alignment\n\
b3b91714
AM		 5977 -q quieten some warnings\n"));
5978#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5979 fprintf (stream, _("\
a38cf1db 5980 -s ignored\n"));
b3b91714
AM		 5981#endif
5982#ifdef SVR4_COMMENT_CHARS
5983 fprintf (stream, _("\
5984 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5985#else
5986 fprintf (stream, _("\
b3b91714 5987 --divide ignored\n"));
4cc782b5 5988#endif
9103f4f4
L		 5989 fprintf (stream, _("\
5990 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5991 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 5992 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 5993
252b5132
RH		 5994}
5995
99ad8390
NC		 5996#if defined(TE_PEP)
5997const char *
5998x86_64_target_format (void)
5999{
6000 if (strcmp (default_arch, "x86_64") == 0)
6001 {
6002 set_code_flag (CODE_64BIT);
6003 return COFF_TARGET_FORMAT;
6004 }
6005 else if (strcmp (default_arch, "i386") == 0)
6006 {
6007 set_code_flag (CODE_32BIT);
6008 return "coff-i386";
6009 }
6010
6011 as_fatal (_("Unknown architecture"));
6012 return NULL;
6013}
6014#endif
6015
3e73aa7c
JH		 6016#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6017 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6018
6019/* Pick the target format to use. */
6020
47926f60 6021const char *
252b5132
RH		 6022i386_target_format ()
6023{
3e73aa7c 6024 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6025 {
6026 set_code_flag (CODE_64BIT);
6027 if (cpu_arch_isa_flags == 0)
d32cad65 6028 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6029 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6030 |CpuSSE|CpuSSE2;
ccc9c027 6031 if (cpu_arch_tune_flags == 0)
d32cad65 6032 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6033 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6034 |CpuSSE|CpuSSE2;
9103f4f4 6035 }
3e73aa7c 6036 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6037 {
6038 set_code_flag (CODE_32BIT);
6039 if (cpu_arch_isa_flags == 0)
d32cad65 6040 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6041 if (cpu_arch_tune_flags == 0)
d32cad65 6042 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6043 }
3e73aa7c
JH		 6044 else
6045 as_fatal (_("Unknown architecture"));
252b5132
RH		 6046 switch (OUTPUT_FLAVOR)
6047 {
4c63da97
AM		 6048#ifdef OBJ_MAYBE_AOUT
6049 case bfd_target_aout_flavour:
47926f60 6050 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6051#endif
6052#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6053 case bfd_target_coff_flavour:
6054 return "coff-i386";
4c63da97 6055#endif
3e73aa7c 6056#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6057 case bfd_target_elf_flavour:
3e73aa7c 6058 {
e5cb08ac 6059 if (flag_code == CODE_64BIT)
4fa24527
JB		 6060 {
6061 object_64bit = 1;
6062 use_rela_relocations = 1;
6063 }
9d7cbccd 6064 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6065 }
4c63da97 6066#endif
252b5132
RH		 6067 default:
6068 abort ();
6069 return NULL;
6070 }
6071}
6072
47926f60 6073#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6074
6075#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6076void i386_elf_emit_arch_note ()
6077{
718ddfc0 6078 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6079 {
6080 char *p;
6081 asection *seg = now_seg;
6082 subsegT subseg = now_subseg;
6083 Elf_Internal_Note i_note;
6084 Elf_External_Note e_note;
6085 asection *note_secp;
6086 int len;
6087
6088 /* Create the .note section. */
6089 note_secp = subseg_new (".note", 0);
6090 bfd_set_section_flags (stdoutput,
6091 note_secp,
6092 SEC_HAS_CONTENTS | SEC_READONLY);
6093
6094 /* Process the arch string. */
6095 len = strlen (cpu_arch_name);
6096
6097 i_note.namesz = len + 1;
6098 i_note.descsz = 0;
6099 i_note.type = NT_ARCH;
6100 p = frag_more (sizeof (e_note.namesz));
6101 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6102 p = frag_more (sizeof (e_note.descsz));
6103 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6104 p = frag_more (sizeof (e_note.type));
6105 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6106 p = frag_more (len + 1);
6107 strcpy (p, cpu_arch_name);
6108
6109 frag_align (2, 0, 0);
6110
6111 subseg_set (seg, subseg);
6112 }
6113}
6114#endif
252b5132 6115\f
252b5132
RH		 6116symbolS *
6117md_undefined_symbol (name)
6118 char *name;
6119{
18dc2407
ILT		 6120 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6121 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6122 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6123 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6124 {
6125 if (!GOT_symbol)
6126 {
6127 if (symbol_find (name))
6128 as_bad (_("GOT already in symbol table"));
6129 GOT_symbol = symbol_new (name, undefined_section,
6130 (valueT) 0, &zero_address_frag);
6131 };
6132 return GOT_symbol;
6133 }
252b5132
RH		 6134 return 0;
6135}
6136
6137/* Round up a section size to the appropriate boundary. */
47926f60 6138
252b5132
RH		 6139valueT
6140md_section_align (segment, size)
ab9da554 6141 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6142 valueT size;
6143{
4c63da97
AM		 6144#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6145 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6146 {
6147 /* For a.out, force the section size to be aligned. If we don't do
6148 this, BFD will align it for us, but it will not write out the
6149 final bytes of the section. This may be a bug in BFD, but it is
6150 easier to fix it here since that is how the other a.out targets
6151 work. */
6152 int align;
6153
6154 align = bfd_get_section_alignment (stdoutput, segment);
6155 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6156 }
252b5132
RH		 6157#endif
6158
6159 return size;
6160}
6161
6162/* On the i386, PC-relative offsets are relative to the start of the
6163 next instruction. That is, the address of the offset, plus its
6164 size, since the offset is always the last part of the insn. */
6165
6166long
6167md_pcrel_from (fixP)
6168 fixS *fixP;
6169{
6170 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6171}
6172
6173#ifndef I386COFF
6174
6175static void
6176s_bss (ignore)
ab9da554 6177 int ignore ATTRIBUTE_UNUSED;
252b5132 6178{
29b0f896 6179 int temp;
252b5132 6180
8a75718c
JB		 6181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6182 if (IS_ELF)
6183 obj_elf_section_change_hook ();
6184#endif
252b5132
RH		 6185 temp = get_absolute_expression ();
6186 subseg_set (bss_section, (subsegT) temp);
6187 demand_empty_rest_of_line ();
6188}
6189
6190#endif
6191
252b5132
RH		 6192void
6193i386_validate_fix (fixp)
6194 fixS *fixp;
6195{
6196 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6197 {
23df1078
JH		 6198 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6199 {
4fa24527 6200 if (!object_64bit)
23df1078
JH		 6201 abort ();
6202 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6203 }
6204 else
6205 {
4fa24527 6206 if (!object_64bit)
d6ab8113
JB		 6207 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6208 else
6209 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6210 }
252b5132
RH		 6211 fixp->fx_subsy = 0;
6212 }
6213}
6214
252b5132
RH		 6215arelent *
6216tc_gen_reloc (section, fixp)
ab9da554 6217 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6218 fixS *fixp;
6219{
6220 arelent *rel;
6221 bfd_reloc_code_real_type code;
6222
6223 switch (fixp->fx_r_type)
6224 {
3e73aa7c
JH		 6225 case BFD_RELOC_X86_64_PLT32:
6226 case BFD_RELOC_X86_64_GOT32:
6227 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6228 case BFD_RELOC_386_PLT32:
6229 case BFD_RELOC_386_GOT32:
6230 case BFD_RELOC_386_GOTOFF:
6231 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6232 case BFD_RELOC_386_TLS_GD:
6233 case BFD_RELOC_386_TLS_LDM:
6234 case BFD_RELOC_386_TLS_LDO_32:
6235 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6236 case BFD_RELOC_386_TLS_IE:
6237 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6238 case BFD_RELOC_386_TLS_LE_32:
6239 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6240 case BFD_RELOC_386_TLS_GOTDESC:
6241 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6242 case BFD_RELOC_X86_64_TLSGD:
6243 case BFD_RELOC_X86_64_TLSLD:
6244 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6245 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6246 case BFD_RELOC_X86_64_GOTTPOFF:
6247 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6248 case BFD_RELOC_X86_64_TPOFF64:
6249 case BFD_RELOC_X86_64_GOTOFF64:
6250 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6251 case BFD_RELOC_X86_64_GOT64:
6252 case BFD_RELOC_X86_64_GOTPCREL64:
6253 case BFD_RELOC_X86_64_GOTPC64:
6254 case BFD_RELOC_X86_64_GOTPLT64:
6255 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6256 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6257 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6258 case BFD_RELOC_RVA:
6259 case BFD_RELOC_VTABLE_ENTRY:
6260 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6261#ifdef TE_PE
6262 case BFD_RELOC_32_SECREL:
6263#endif
252b5132
RH		 6264 code = fixp->fx_r_type;
6265 break;
dbbaec26
L		 6266 case BFD_RELOC_X86_64_32S:
6267 if (!fixp->fx_pcrel)
6268 {
6269 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6270 code = fixp->fx_r_type;
6271 break;
6272 }
252b5132 6273 default:
93382f6d 6274 if (fixp->fx_pcrel)
252b5132 6275 {
93382f6d
AM		 6276 switch (fixp->fx_size)
6277 {
6278 default:
b091f402
AM		 6279 as_bad_where (fixp->fx_file, fixp->fx_line,
6280 _("can not do %d byte pc-relative relocation"),
6281 fixp->fx_size);
93382f6d
AM		 6282 code = BFD_RELOC_32_PCREL;
6283 break;
6284 case 1: code = BFD_RELOC_8_PCREL; break;
6285 case 2: code = BFD_RELOC_16_PCREL; break;
6286 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6287#ifdef BFD64
6288 case 8: code = BFD_RELOC_64_PCREL; break;
6289#endif
93382f6d
AM		 6290 }
6291 }
6292 else
6293 {
6294 switch (fixp->fx_size)
6295 {
6296 default:
b091f402
AM		 6297 as_bad_where (fixp->fx_file, fixp->fx_line,
6298 _("can not do %d byte relocation"),
6299 fixp->fx_size);
93382f6d
AM		 6300 code = BFD_RELOC_32;
6301 break;
6302 case 1: code = BFD_RELOC_8; break;
6303 case 2: code = BFD_RELOC_16; break;
6304 case 4: code = BFD_RELOC_32; break;
937149dd 6305#ifdef BFD64
3e73aa7c 6306 case 8: code = BFD_RELOC_64; break;
937149dd 6307#endif
93382f6d 6308 }
252b5132
RH		 6309 }
6310 break;
6311 }
252b5132 6312
d182319b
JB		 6313 if ((code == BFD_RELOC_32
6314 || code == BFD_RELOC_32_PCREL
6315 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6316 && GOT_symbol
6317 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6318 {
4fa24527 6319 if (!object_64bit)
d6ab8113
JB		 6320 code = BFD_RELOC_386_GOTPC;
6321 else
6322 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6323 }
7b81dfbb
AJ		 6324 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6325 && GOT_symbol
6326 && fixp->fx_addsy == GOT_symbol)
6327 {
6328 code = BFD_RELOC_X86_64_GOTPC64;
6329 }
252b5132
RH		 6330
6331 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6332 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6333 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6334
6335 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6336
3e73aa7c
JH		 6337 if (!use_rela_relocations)
6338 {
6339 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6340 vtable entry to be used in the relocation's section offset. */
6341 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6342 rel->address = fixp->fx_offset;
252b5132 6343
c6682705 6344 rel->addend = 0;
3e73aa7c
JH		 6345 }
6346 /* Use the rela in 64bit mode. */
252b5132 6347 else
3e73aa7c 6348 {
062cd5e7
AS		 6349 if (!fixp->fx_pcrel)
6350 rel->addend = fixp->fx_offset;
6351 else
6352 switch (code)
6353 {
6354 case BFD_RELOC_X86_64_PLT32:
6355 case BFD_RELOC_X86_64_GOT32:
6356 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6357 case BFD_RELOC_X86_64_TLSGD:
6358 case BFD_RELOC_X86_64_TLSLD:
6359 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6360 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6361 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6362 rel->addend = fixp->fx_offset - fixp->fx_size;
6363 break;
6364 default:
6365 rel->addend = (section->vma
6366 - fixp->fx_size
6367 + fixp->fx_addnumber
6368 + md_pcrel_from (fixp));
6369 break;
6370 }
3e73aa7c
JH		 6371 }
6372
252b5132
RH		 6373 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6374 if (rel->howto == NULL)
6375 {
6376 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6377 _("cannot represent relocation type %s"),
252b5132
RH		 6378 bfd_get_reloc_code_name (code));
6379 /* Set howto to a garbage value so that we can keep going. */
6380 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6381 assert (rel->howto != NULL);
6382 }
6383
6384 return rel;
6385}
6386
64a0c779
DN		 6387\f
6388/* Parse operands using Intel syntax. This implements a recursive descent
6389 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6390 Programmer's Guide.
6391
6392 FIXME: We do not recognize the full operand grammar defined in the MASM
6393 documentation. In particular, all the structure/union and
6394 high-level macro operands are missing.
6395
6396 Uppercase words are terminals, lower case words are non-terminals.
6397 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6398 bars '|' denote choices. Most grammar productions are implemented in
6399 functions called 'intel_<production>'.
6400
6401 Initial production is 'expr'.
6402
9306ca4a 6403 addOp + | -
64a0c779
DN		 6404
6405 alpha [a-zA-Z]
6406
9306ca4a
JB		 6407 binOp & | AND | \| | OR | ^ | XOR
6408
64a0c779
DN		 6409 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6410
6411 constant digits [[ radixOverride ]]
6412
9306ca4a 6413 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6414
6415 digits decdigit
b77a7acd
AJ		 6416 | digits decdigit
6417 | digits hexdigit
64a0c779
DN		 6418
6419 decdigit [0-9]
6420
9306ca4a
JB		 6421 e04 e04 addOp e05
6422 | e05
6423
6424 e05 e05 binOp e06
b77a7acd 6425 | e06
64a0c779
DN		 6426
6427 e06 e06 mulOp e09
b77a7acd 6428 | e09
64a0c779
DN		 6429
6430 e09 OFFSET e10
a724f0f4
JB		 6431 | SHORT e10
6432 | + e10
6433 | - e10
9306ca4a
JB		 6434 | ~ e10
6435 | NOT e10
64a0c779
DN		 6436 | e09 PTR e10
6437 | e09 : e10
6438 | e10
6439
6440 e10 e10 [ expr ]
b77a7acd 6441 | e11
64a0c779
DN		 6442
6443 e11 ( expr )
b77a7acd 6444 | [ expr ]
64a0c779
DN		 6445 | constant
6446 | dataType
6447 | id
6448 | $
6449 | register
6450
a724f0f4 6451 => expr expr cmpOp e04
9306ca4a 6452 | e04
64a0c779
DN		 6453
6454 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6455 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6456
6457 hexdigit a | b | c | d | e | f
b77a7acd 6458 | A | B | C | D | E | F
64a0c779
DN		 6459
6460 id alpha
b77a7acd 6461 | id alpha
64a0c779
DN		 6462 | id decdigit
6463
9306ca4a 6464 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6465
6466 quote " | '
6467
6468 register specialRegister
b77a7acd 6469 | gpRegister
64a0c779
DN		 6470 | byteRegister
6471
6472 segmentRegister CS | DS | ES | FS | GS | SS
6473
9306ca4a 6474 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6475 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6476 | TR3 | TR4 | TR5 | TR6 | TR7
6477
64a0c779
DN		 6478 We simplify the grammar in obvious places (e.g., register parsing is
6479 done by calling parse_register) and eliminate immediate left recursion
6480 to implement a recursive-descent parser.
6481
a724f0f4
JB		 6482 expr e04 expr'
6483
6484 expr' cmpOp e04 expr'
6485 | Empty
9306ca4a
JB		 6486
6487 e04 e05 e04'
6488
6489 e04' addOp e05 e04'
6490 | Empty
64a0c779
DN		 6491
6492 e05 e06 e05'
6493
9306ca4a 6494 e05' binOp e06 e05'
b77a7acd 6495 | Empty
64a0c779
DN		 6496
6497 e06 e09 e06'
6498
6499 e06' mulOp e09 e06'
b77a7acd 6500 | Empty
64a0c779
DN		 6501
6502 e09 OFFSET e10 e09'
a724f0f4
JB		 6503 | SHORT e10'
6504 | + e10'
6505 | - e10'
6506 | ~ e10'
6507 | NOT e10'
b77a7acd 6508 | e10 e09'
64a0c779
DN		 6509
6510 e09' PTR e10 e09'
b77a7acd 6511 | : e10 e09'
64a0c779
DN		 6512 | Empty
6513
6514 e10 e11 e10'
6515
6516 e10' [ expr ] e10'
b77a7acd 6517 | Empty
64a0c779
DN		 6518
6519 e11 ( expr )
b77a7acd 6520 | [ expr ]
64a0c779
DN		 6521 | BYTE
6522 | WORD
6523 | DWORD
9306ca4a 6524 | FWORD
64a0c779 6525 | QWORD
9306ca4a
JB		 6526 | TBYTE
6527 | OWORD
6528 | XMMWORD
64a0c779
DN		 6529 | .
6530 | $
6531 | register
6532 | id
6533 | constant */
6534
6535/* Parsing structure for the intel syntax parser. Used to implement the
6536 semantic actions for the operand grammar. */
6537struct intel_parser_s
6538 {
6539 char *op_string; /* The string being parsed. */
6540 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6541 int op_modifier; /* Operand modifier. */
64a0c779 6542 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6543 int in_offset; /* >=1 if parsing operand of offset. */
6544 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6545 const reg_entry *reg; /* Last register reference found. */
6546 char *disp; /* Displacement string being built. */
a724f0f4 6547 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6548 };
6549
6550static struct intel_parser_s intel_parser;
6551
6552/* Token structure for parsing intel syntax. */
6553struct intel_token
6554 {
6555 int code; /* Token code. */
6556 const reg_entry *reg; /* Register entry for register tokens. */
6557 char *str; /* String representation. */
6558 };
6559
6560static struct intel_token cur_token, prev_token;
6561
50705ef4
AM		 6562/* Token codes for the intel parser. Since T_SHORT is already used
6563 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6564#define T_NIL -1
6565#define T_CONST 1
6566#define T_REG 2
6567#define T_BYTE 3
6568#define T_WORD 4
9306ca4a
JB		 6569#define T_DWORD 5
6570#define T_FWORD 6
6571#define T_QWORD 7
6572#define T_TBYTE 8
6573#define T_XMMWORD 9
50705ef4 6574#undef T_SHORT
9306ca4a
JB		 6575#define T_SHORT 10
6576#define T_OFFSET 11
6577#define T_PTR 12
6578#define T_ID 13
6579#define T_SHL 14
6580#define T_SHR 15
64a0c779
DN		 6581
6582/* Prototypes for intel parser functions. */
6583static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6584static void intel_get_token PARAMS ((void));
6585static void intel_putback_token PARAMS ((void));
6586static int intel_expr PARAMS ((void));
9306ca4a 6587static int intel_e04 PARAMS ((void));
cce0cbdc 6588static int intel_e05 PARAMS ((void));
cce0cbdc 6589static int intel_e06 PARAMS ((void));
cce0cbdc 6590static int intel_e09 PARAMS ((void));
a724f0f4 6591static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6592static int intel_e10 PARAMS ((void));
cce0cbdc 6593static int intel_e11 PARAMS ((void));
64a0c779 6594
64a0c779
DN		 6595static int
6596i386_intel_operand (operand_string, got_a_float)
6597 char *operand_string;
6598 int got_a_float;
6599{
6600 int ret;
6601 char *p;
6602
a724f0f4
JB		 6603 p = intel_parser.op_string = xstrdup (operand_string);
6604 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6605
6606 for (;;)
64a0c779 6607 {
a724f0f4
JB		 6608 /* Initialize token holders. */
6609 cur_token.code = prev_token.code = T_NIL;
6610 cur_token.reg = prev_token.reg = NULL;
6611 cur_token.str = prev_token.str = NULL;
6612
6613 /* Initialize parser structure. */
6614 intel_parser.got_a_float = got_a_float;
6615 intel_parser.op_modifier = 0;
6616 intel_parser.is_mem = 0;
6617 intel_parser.in_offset = 0;
6618 intel_parser.in_bracket = 0;
6619 intel_parser.reg = NULL;
6620 intel_parser.disp[0] = '\0';
6621 intel_parser.next_operand = NULL;
6622
6623 /* Read the first token and start the parser. */
6624 intel_get_token ();
6625 ret = intel_expr ();
6626
6627 if (!ret)
6628 break;
6629
9306ca4a
JB		 6630 if (cur_token.code != T_NIL)
6631 {
6632 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6633 current_templates->start->name, cur_token.str);
6634 ret = 0;
6635 }
64a0c779
DN		 6636 /* If we found a memory reference, hand it over to i386_displacement
6637 to fill in the rest of the operand fields. */
9306ca4a 6638 else if (intel_parser.is_mem)
64a0c779
DN		 6639 {
6640 if ((i.mem_operands == 1
6641 && (current_templates->start->opcode_modifier & IsString) == 0)
6642 || i.mem_operands == 2)
6643 {
6644 as_bad (_("too many memory references for '%s'"),
6645 current_templates->start->name);
6646 ret = 0;
6647 }
6648 else
6649 {
6650 char *s = intel_parser.disp;
6651 i.mem_operands++;
6652
a724f0f4
JB		 6653 if (!quiet_warnings && intel_parser.is_mem < 0)
6654 /* See the comments in intel_bracket_expr. */
6655 as_warn (_("Treating `%s' as memory reference"), operand_string);
6656
64a0c779
DN		 6657 /* Add the displacement expression. */
6658 if (*s != '\0')
a4622f40
AM		 6659 ret = i386_displacement (s, s + strlen (s));
6660 if (ret)
a724f0f4
JB		 6661 {
6662 /* Swap base and index in 16-bit memory operands like
6663 [si+bx]. Since i386_index_check is also used in AT&T
6664 mode we have to do that here. */
6665 if (i.base_reg
6666 && i.index_reg
6667 && (i.base_reg->reg_type & Reg16)
6668 && (i.index_reg->reg_type & Reg16)
6669 && i.base_reg->reg_num >= 6
6670 && i.index_reg->reg_num < 6)
6671 {
6672 const reg_entry *base = i.index_reg;
6673
6674 i.index_reg = i.base_reg;
6675 i.base_reg = base;
6676 }
6677 ret = i386_index_check (operand_string);
6678 }
64a0c779
DN		 6679 }
6680 }
6681
6682 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6683 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6684 || intel_parser.reg == NULL)
6685 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6686
6687 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6688 ret = 0;
6689 if (!ret || !intel_parser.next_operand)
6690 break;
6691 intel_parser.op_string = intel_parser.next_operand;
6692 this_operand = i.operands++;
64a0c779
DN		 6693 }
6694
6695 free (p);
6696 free (intel_parser.disp);
6697
6698 return ret;
6699}
6700
a724f0f4
JB		 6701#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6702
6703/* expr e04 expr'
6704
6705 expr' cmpOp e04 expr'
6706 | Empty */
64a0c779
DN		 6707static int
6708intel_expr ()
6709{
a724f0f4
JB		 6710 /* XXX Implement the comparison operators. */
6711 return intel_e04 ();
9306ca4a
JB		 6712}
6713
a724f0f4 6714/* e04 e05 e04'
9306ca4a 6715
a724f0f4 6716 e04' addOp e05 e04'
9306ca4a
JB		 6717 | Empty */
6718static int
6719intel_e04 ()
6720{
a724f0f4 6721 int nregs = -1;
9306ca4a 6722
a724f0f4 6723 for (;;)
9306ca4a 6724 {
a724f0f4
JB		 6725 if (!intel_e05())
6726 return 0;
9306ca4a 6727
a724f0f4
JB		 6728 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6729 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6730
a724f0f4
JB		 6731 if (cur_token.code == '+')
6732 nregs = -1;
6733 else if (cur_token.code == '-')
6734 nregs = NUM_ADDRESS_REGS;
6735 else
6736 return 1;
64a0c779 6737
a724f0f4
JB		 6738 strcat (intel_parser.disp, cur_token.str);
6739 intel_match_token (cur_token.code);
6740 }
64a0c779
DN		 6741}
6742
64a0c779
DN		 6743/* e05 e06 e05'
6744
9306ca4a 6745 e05' binOp e06 e05'
64a0c779
DN		 6746 | Empty */
6747static int
6748intel_e05 ()
6749{
a724f0f4 6750 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6751
a724f0f4 6752 for (;;)
64a0c779 6753 {
a724f0f4
JB		 6754 if (!intel_e06())
6755 return 0;
6756
6757 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6758 {
6759 char str[2];
6760
6761 str[0] = cur_token.code;
6762 str[1] = 0;
6763 strcat (intel_parser.disp, str);
6764 }
6765 else
6766 break;
9306ca4a 6767
64a0c779
DN		 6768 intel_match_token (cur_token.code);
6769
a724f0f4
JB		 6770 if (nregs < 0)
6771 nregs = ~nregs;
64a0c779 6772 }
a724f0f4
JB		 6773 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6774 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6775 return 1;
4a1805b1 6776}
64a0c779
DN		 6777
6778/* e06 e09 e06'
6779
6780 e06' mulOp e09 e06'
b77a7acd 6781 | Empty */
64a0c779
DN		 6782static int
6783intel_e06 ()
6784{
a724f0f4 6785 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6786
a724f0f4 6787 for (;;)
64a0c779 6788 {
a724f0f4
JB		 6789 if (!intel_e09())
6790 return 0;
9306ca4a 6791
a724f0f4
JB		 6792 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6793 {
6794 char str[2];
9306ca4a 6795
a724f0f4
JB		 6796 str[0] = cur_token.code;
6797 str[1] = 0;
6798 strcat (intel_parser.disp, str);
6799 }
6800 else if (cur_token.code == T_SHL)
6801 strcat (intel_parser.disp, "<<");
6802 else if (cur_token.code == T_SHR)
6803 strcat (intel_parser.disp, ">>");
6804 else
6805 break;
9306ca4a 6806
64e74474 6807 intel_match_token (cur_token.code);
64a0c779 6808
a724f0f4
JB		 6809 if (nregs < 0)
6810 nregs = ~nregs;
64a0c779 6811 }
a724f0f4
JB		 6812 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6813 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6814 return 1;
64a0c779
DN		 6815}
6816
a724f0f4
JB		 6817/* e09 OFFSET e09
6818 | SHORT e09
6819 | + e09
6820 | - e09
6821 | ~ e09
6822 | NOT e09
9306ca4a
JB		 6823 | e10 e09'
6824
64a0c779 6825 e09' PTR e10 e09'
b77a7acd 6826 | : e10 e09'
64a0c779
DN		 6827 | Empty */
6828static int
6829intel_e09 ()
6830{
a724f0f4
JB		 6831 int nregs = ~NUM_ADDRESS_REGS;
6832 int in_offset = 0;
6833
6834 for (;;)
64a0c779 6835 {
a724f0f4
JB		 6836 /* Don't consume constants here. */
6837 if (cur_token.code == '+' || cur_token.code == '-')
6838 {
6839 /* Need to look one token ahead - if the next token
6840 is a constant, the current token is its sign. */
6841 int next_code;
6842
6843 intel_match_token (cur_token.code);
6844 next_code = cur_token.code;
6845 intel_putback_token ();
6846 if (next_code == T_CONST)
6847 break;
6848 }
6849
6850 /* e09 OFFSET e09 */
6851 if (cur_token.code == T_OFFSET)
6852 {
6853 if (!in_offset++)
6854 ++intel_parser.in_offset;
6855 }
6856
6857 /* e09 SHORT e09 */
6858 else if (cur_token.code == T_SHORT)
6859 intel_parser.op_modifier |= 1 << T_SHORT;
6860
6861 /* e09 + e09 */
6862 else if (cur_token.code == '+')
6863 strcat (intel_parser.disp, "+");
6864
6865 /* e09 - e09
6866 | ~ e09
6867 | NOT e09 */
6868 else if (cur_token.code == '-' || cur_token.code == '~')
6869 {
6870 char str[2];
64a0c779 6871
a724f0f4
JB		 6872 if (nregs < 0)
6873 nregs = ~nregs;
6874 str[0] = cur_token.code;
6875 str[1] = 0;
6876 strcat (intel_parser.disp, str);
6877 }
6878
6879 /* e09 e10 e09' */
6880 else
6881 break;
6882
6883 intel_match_token (cur_token.code);
64a0c779
DN		 6884 }
6885
a724f0f4 6886 for (;;)
9306ca4a 6887 {
a724f0f4
JB		 6888 if (!intel_e10 ())
6889 return 0;
9306ca4a 6890
a724f0f4
JB		 6891 /* e09' PTR e10 e09' */
6892 if (cur_token.code == T_PTR)
6893 {
6894 char suffix;
9306ca4a 6895
a724f0f4
JB		 6896 if (prev_token.code == T_BYTE)
6897 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6898
a724f0f4
JB		 6899 else if (prev_token.code == T_WORD)
6900 {
6901 if (current_templates->start->name[0] == 'l'
6902 && current_templates->start->name[2] == 's'
6903 && current_templates->start->name[3] == 0)
6904 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6905 else if (intel_parser.got_a_float == 2) /* "fi..." */
6906 suffix = SHORT_MNEM_SUFFIX;
6907 else
6908 suffix = WORD_MNEM_SUFFIX;
6909 }
64a0c779 6910
a724f0f4
JB		 6911 else if (prev_token.code == T_DWORD)
6912 {
6913 if (current_templates->start->name[0] == 'l'
6914 && current_templates->start->name[2] == 's'
6915 && current_templates->start->name[3] == 0)
6916 suffix = WORD_MNEM_SUFFIX;
6917 else if (flag_code == CODE_16BIT
6918 && (current_templates->start->opcode_modifier
435acd52 6919 & (Jump | JumpDword)))
a724f0f4
JB		 6920 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6921 else if (intel_parser.got_a_float == 1) /* "f..." */
6922 suffix = SHORT_MNEM_SUFFIX;
6923 else
6924 suffix = LONG_MNEM_SUFFIX;
6925 }
9306ca4a 6926
a724f0f4
JB		 6927 else if (prev_token.code == T_FWORD)
6928 {
6929 if (current_templates->start->name[0] == 'l'
6930 && current_templates->start->name[2] == 's'
6931 && current_templates->start->name[3] == 0)
6932 suffix = LONG_MNEM_SUFFIX;
6933 else if (!intel_parser.got_a_float)
6934 {
6935 if (flag_code == CODE_16BIT)
6936 add_prefix (DATA_PREFIX_OPCODE);
6937 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6938 }
6939 else
6940 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6941 }
64a0c779 6942
a724f0f4
JB		 6943 else if (prev_token.code == T_QWORD)
6944 {
6945 if (intel_parser.got_a_float == 1) /* "f..." */
6946 suffix = LONG_MNEM_SUFFIX;
6947 else
6948 suffix = QWORD_MNEM_SUFFIX;
6949 }
64a0c779 6950
a724f0f4
JB		 6951 else if (prev_token.code == T_TBYTE)
6952 {
6953 if (intel_parser.got_a_float == 1)
6954 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6955 else
6956 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6957 }
9306ca4a 6958
a724f0f4 6959 else if (prev_token.code == T_XMMWORD)
9306ca4a 6960 {
a724f0f4
JB		 6961 /* XXX ignored for now, but accepted since gcc uses it */
6962 suffix = 0;
9306ca4a 6963 }
64a0c779 6964
f16b83df 6965 else
a724f0f4
JB		 6966 {
6967 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6968 return 0;
6969 }
6970
435acd52
JB		 6971 /* Operands for jump/call using 'ptr' notation denote absolute
6972 addresses. */
6973 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6974 i.types[this_operand] |= JumpAbsolute;
6975
a724f0f4
JB		 6976 if (current_templates->start->base_opcode == 0x8d /* lea */)
6977 ;
6978 else if (!i.suffix)
6979 i.suffix = suffix;
6980 else if (i.suffix != suffix)
6981 {
6982 as_bad (_("Conflicting operand modifiers"));
6983 return 0;
6984 }
64a0c779 6985
9306ca4a
JB		 6986 }
6987
a724f0f4
JB		 6988 /* e09' : e10 e09' */
6989 else if (cur_token.code == ':')
9306ca4a 6990 {
a724f0f4
JB		 6991 if (prev_token.code != T_REG)
6992 {
6993 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6994 segment/group identifier (which we don't have), using comma
6995 as the operand separator there is even less consistent, since
6996 there all branches only have a single operand. */
6997 if (this_operand != 0
6998 || intel_parser.in_offset
6999 || intel_parser.in_bracket
7000 || (!(current_templates->start->opcode_modifier
7001 & (Jump|JumpDword|JumpInterSegment))
7002 && !(current_templates->start->operand_types[0]
7003 & JumpAbsolute)))
7004 return intel_match_token (T_NIL);
7005 /* Remember the start of the 2nd operand and terminate 1st
7006 operand here.
7007 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7008 another expression), but it gets at least the simplest case
7009 (a plain number or symbol on the left side) right. */
7010 intel_parser.next_operand = intel_parser.op_string;
7011 *--intel_parser.op_string = '\0';
7012 return intel_match_token (':');
7013 }
9306ca4a 7014 }
64a0c779 7015
a724f0f4 7016 /* e09' Empty */
64a0c779 7017 else
a724f0f4 7018 break;
64a0c779 7019
a724f0f4
JB		 7020 intel_match_token (cur_token.code);
7021
7022 }
7023
7024 if (in_offset)
7025 {
7026 --intel_parser.in_offset;
7027 if (nregs < 0)
7028 nregs = ~nregs;
7029 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7030 {
a724f0f4 7031 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7032 return 0;
7033 }
a724f0f4
JB		 7034 intel_parser.op_modifier |= 1 << T_OFFSET;
7035 }
9306ca4a 7036
a724f0f4
JB		 7037 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7038 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7039 return 1;
7040}
64a0c779 7041
a724f0f4
JB		 7042static int
7043intel_bracket_expr ()
7044{
7045 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7046 const char *start = intel_parser.op_string;
7047 int len;
7048
7049 if (i.op[this_operand].regs)
7050 return intel_match_token (T_NIL);
7051
7052 intel_match_token ('[');
7053
7054 /* Mark as a memory operand only if it's not already known to be an
7055 offset expression. If it's an offset expression, we need to keep
7056 the brace in. */
7057 if (!intel_parser.in_offset)
7058 {
7059 ++intel_parser.in_bracket;
435acd52
JB		 7060
7061 /* Operands for jump/call inside brackets denote absolute addresses. */
7062 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7063 i.types[this_operand] |= JumpAbsolute;
7064
a724f0f4
JB		 7065 /* Unfortunately gas always diverged from MASM in a respect that can't
7066 be easily fixed without risking to break code sequences likely to be
7067 encountered (the testsuite even check for this): MASM doesn't consider
7068 an expression inside brackets unconditionally as a memory reference.
7069 When that is e.g. a constant, an offset expression, or the sum of the
7070 two, this is still taken as a constant load. gas, however, always
7071 treated these as memory references. As a compromise, we'll try to make
7072 offset expressions inside brackets work the MASM way (since that's
7073 less likely to be found in real world code), but make constants alone
7074 continue to work the traditional gas way. In either case, issue a
7075 warning. */
7076 intel_parser.op_modifier &= ~was_offset;
64a0c779 7077 }
a724f0f4 7078 else
64e74474 7079 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7080
7081 /* Add a '+' to the displacement string if necessary. */
7082 if (*intel_parser.disp != '\0'
7083 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7084 strcat (intel_parser.disp, "+");
64a0c779 7085
a724f0f4
JB		 7086 if (intel_expr ()
7087 && (len = intel_parser.op_string - start - 1,
7088 intel_match_token (']')))
64a0c779 7089 {
a724f0f4
JB		 7090 /* Preserve brackets when the operand is an offset expression. */
7091 if (intel_parser.in_offset)
7092 strcat (intel_parser.disp, "]");
7093 else
7094 {
7095 --intel_parser.in_bracket;
7096 if (i.base_reg || i.index_reg)
7097 intel_parser.is_mem = 1;
7098 if (!intel_parser.is_mem)
7099 {
7100 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7101 /* Defer the warning until all of the operand was parsed. */
7102 intel_parser.is_mem = -1;
7103 else if (!quiet_warnings)
7104 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7105 }
7106 }
7107 intel_parser.op_modifier |= was_offset;
64a0c779 7108
a724f0f4 7109 return 1;
64a0c779 7110 }
a724f0f4 7111 return 0;
64a0c779
DN		 7112}
7113
7114/* e10 e11 e10'
7115
7116 e10' [ expr ] e10'
b77a7acd 7117 | Empty */
64a0c779
DN		 7118static int
7119intel_e10 ()
7120{
a724f0f4
JB		 7121 if (!intel_e11 ())
7122 return 0;
64a0c779 7123
a724f0f4 7124 while (cur_token.code == '[')
64a0c779 7125 {
a724f0f4 7126 if (!intel_bracket_expr ())
21d6c4af 7127 return 0;
64a0c779
DN		 7128 }
7129
a724f0f4 7130 return 1;
64a0c779
DN		 7131}
7132
64a0c779 7133/* e11 ( expr )
b77a7acd 7134 | [ expr ]
64a0c779
DN		 7135 | BYTE
7136 | WORD
7137 | DWORD
9306ca4a 7138 | FWORD
64a0c779 7139 | QWORD
9306ca4a
JB		 7140 | TBYTE
7141 | OWORD
7142 | XMMWORD
4a1805b1 7143 | $
64a0c779
DN		 7144 | .
7145 | register
7146 | id
7147 | constant */
7148static int
7149intel_e11 ()
7150{
a724f0f4 7151 switch (cur_token.code)
64a0c779 7152 {
a724f0f4
JB		 7153 /* e11 ( expr ) */
7154 case '(':
64a0c779
DN		 7155 intel_match_token ('(');
7156 strcat (intel_parser.disp, "(");
7157
7158 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7159 {
7160 strcat (intel_parser.disp, ")");
7161 return 1;
7162 }
a724f0f4 7163 return 0;
4a1805b1 7164
a724f0f4
JB		 7165 /* e11 [ expr ] */
7166 case '[':
a724f0f4 7167 return intel_bracket_expr ();
64a0c779 7168
a724f0f4
JB		 7169 /* e11 $
7170 | . */
7171 case '.':
64a0c779
DN		 7172 strcat (intel_parser.disp, cur_token.str);
7173 intel_match_token (cur_token.code);
21d6c4af
DN		 7174
7175 /* Mark as a memory operand only if it's not already known to be an
7176 offset expression. */
a724f0f4 7177 if (!intel_parser.in_offset)
21d6c4af 7178 intel_parser.is_mem = 1;
64a0c779
DN		 7179
7180 return 1;
64a0c779 7181
a724f0f4
JB		 7182 /* e11 register */
7183 case T_REG:
7184 {
7185 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7186
a724f0f4 7187 intel_match_token (T_REG);
64a0c779 7188
a724f0f4
JB		 7189 /* Check for segment change. */
7190 if (cur_token.code == ':')
7191 {
7192 if (!(reg->reg_type & (SReg2 | SReg3)))
7193 {
7194 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7195 return 0;
7196 }
7197 else if (i.seg[i.mem_operands])
7198 as_warn (_("Extra segment override ignored"));
7199 else
7200 {
7201 if (!intel_parser.in_offset)
7202 intel_parser.is_mem = 1;
7203 switch (reg->reg_num)
7204 {
7205 case 0:
7206 i.seg[i.mem_operands] = &es;
7207 break;
7208 case 1:
7209 i.seg[i.mem_operands] = &cs;
7210 break;
7211 case 2:
7212 i.seg[i.mem_operands] = &ss;
7213 break;
7214 case 3:
7215 i.seg[i.mem_operands] = &ds;
7216 break;
7217 case 4:
7218 i.seg[i.mem_operands] = &fs;
7219 break;
7220 case 5:
7221 i.seg[i.mem_operands] = &gs;
7222 break;
7223 }
7224 }
7225 }
64a0c779 7226
a724f0f4
JB		 7227 /* Not a segment register. Check for register scaling. */
7228 else if (cur_token.code == '*')
7229 {
7230 if (!intel_parser.in_bracket)
7231 {
7232 as_bad (_("Register scaling only allowed in memory operands"));
7233 return 0;
7234 }
64a0c779 7235
a724f0f4
JB		 7236 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7237 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7238 else if (i.index_reg)
7239 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7240
a724f0f4
JB		 7241 /* What follows must be a valid scale. */
7242 intel_match_token ('*');
7243 i.index_reg = reg;
7244 i.types[this_operand] |= BaseIndex;
64a0c779 7245
a724f0f4
JB		 7246 /* Set the scale after setting the register (otherwise,
7247 i386_scale will complain) */
7248 if (cur_token.code == '+' || cur_token.code == '-')
7249 {
7250 char *str, sign = cur_token.code;
7251 intel_match_token (cur_token.code);
7252 if (cur_token.code != T_CONST)
7253 {
7254 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7255 cur_token.str);
7256 return 0;
7257 }
7258 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7259 strcpy (str + 1, cur_token.str);
7260 *str = sign;
7261 if (!i386_scale (str))
7262 return 0;
7263 free (str);
7264 }
7265 else if (!i386_scale (cur_token.str))
64a0c779 7266 return 0;
a724f0f4
JB		 7267 intel_match_token (cur_token.code);
7268 }
64a0c779 7269
a724f0f4
JB		 7270 /* No scaling. If this is a memory operand, the register is either a
7271 base register (first occurrence) or an index register (second
7272 occurrence). */
7b0441f6 7273 else if (intel_parser.in_bracket)
a724f0f4 7274 {
64a0c779 7275
a724f0f4
JB		 7276 if (!i.base_reg)
7277 i.base_reg = reg;
7278 else if (!i.index_reg)
7279 i.index_reg = reg;
7280 else
7281 {
7282 as_bad (_("Too many register references in memory operand"));
7283 return 0;
7284 }
64a0c779 7285
a724f0f4
JB		 7286 i.types[this_operand] |= BaseIndex;
7287 }
4a1805b1 7288
4d1bb795
JB		 7289 /* It's neither base nor index. */
7290 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7291 {
7292 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7293 i.op[this_operand].regs = reg;
7294 i.reg_operands++;
7295 }
7296 else
7297 {
7298 as_bad (_("Invalid use of register"));
7299 return 0;
7300 }
64a0c779 7301
a724f0f4
JB		 7302 /* Since registers are not part of the displacement string (except
7303 when we're parsing offset operands), we may need to remove any
7304 preceding '+' from the displacement string. */
7305 if (*intel_parser.disp != '\0'
7306 && !intel_parser.in_offset)
7307 {
7308 char *s = intel_parser.disp;
7309 s += strlen (s) - 1;
7310 if (*s == '+')
7311 *s = '\0';
7312 }
4a1805b1 7313
a724f0f4
JB		 7314 return 1;
7315 }
7316
7317 /* e11 BYTE
7318 | WORD
7319 | DWORD
7320 | FWORD
7321 | QWORD
7322 | TBYTE
7323 | OWORD
7324 | XMMWORD */
7325 case T_BYTE:
7326 case T_WORD:
7327 case T_DWORD:
7328 case T_FWORD:
7329 case T_QWORD:
7330 case T_TBYTE:
7331 case T_XMMWORD:
7332 intel_match_token (cur_token.code);
64a0c779 7333
a724f0f4
JB		 7334 if (cur_token.code == T_PTR)
7335 return 1;
7336
7337 /* It must have been an identifier. */
7338 intel_putback_token ();
7339 cur_token.code = T_ID;
7340 /* FALLTHRU */
7341
7342 /* e11 id
7343 | constant */
7344 case T_ID:
7345 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7346 {
7347 symbolS *symbolP;
7348
a724f0f4
JB		 7349 /* The identifier represents a memory reference only if it's not
7350 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7351 symbolP = symbol_find(cur_token.str);
7352 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7353 intel_parser.is_mem = 1;
7354 }
a724f0f4 7355 /* FALLTHRU */
64a0c779 7356
a724f0f4
JB		 7357 case T_CONST:
7358 case '-':
7359 case '+':
7360 {
7361 char *save_str, sign = 0;
64a0c779 7362
a724f0f4
JB		 7363 /* Allow constants that start with `+' or `-'. */
7364 if (cur_token.code == '-' || cur_token.code == '+')
7365 {
7366 sign = cur_token.code;
7367 intel_match_token (cur_token.code);
7368 if (cur_token.code != T_CONST)
7369 {
7370 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7371 cur_token.str);
7372 return 0;
7373 }
7374 }
64a0c779 7375
a724f0f4
JB		 7376 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7377 strcpy (save_str + !!sign, cur_token.str);
7378 if (sign)
7379 *save_str = sign;
64a0c779 7380
a724f0f4
JB		 7381 /* Get the next token to check for register scaling. */
7382 intel_match_token (cur_token.code);
64a0c779 7383
a724f0f4
JB		 7384 /* Check if this constant is a scaling factor for an index register. */
7385 if (cur_token.code == '*')
7386 {
7387 if (intel_match_token ('*') && cur_token.code == T_REG)
7388 {
7389 const reg_entry *reg = cur_token.reg;
7390
7391 if (!intel_parser.in_bracket)
7392 {
7393 as_bad (_("Register scaling only allowed in memory operands"));
7394 return 0;
7395 }
7396
7397 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7398 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7399 else if (i.index_reg)
7400 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7401
7402 /* The constant is followed by `* reg', so it must be
7403 a valid scale. */
7404 i.index_reg = reg;
7405 i.types[this_operand] |= BaseIndex;
7406
7407 /* Set the scale after setting the register (otherwise,
7408 i386_scale will complain) */
7409 if (!i386_scale (save_str))
64a0c779 7410 return 0;
a724f0f4
JB		 7411 intel_match_token (T_REG);
7412
7413 /* Since registers are not part of the displacement
7414 string, we may need to remove any preceding '+' from
7415 the displacement string. */
7416 if (*intel_parser.disp != '\0')
7417 {
7418 char *s = intel_parser.disp;
7419 s += strlen (s) - 1;
7420 if (*s == '+')
7421 *s = '\0';
7422 }
7423
7424 free (save_str);
7425
7426 return 1;
7427 }
64a0c779 7428
a724f0f4
JB		 7429 /* The constant was not used for register scaling. Since we have
7430 already consumed the token following `*' we now need to put it
7431 back in the stream. */
64a0c779 7432 intel_putback_token ();
a724f0f4 7433 }
64a0c779 7434
a724f0f4
JB		 7435 /* Add the constant to the displacement string. */
7436 strcat (intel_parser.disp, save_str);
7437 free (save_str);
64a0c779 7438
a724f0f4
JB		 7439 return 1;
7440 }
64a0c779
DN		 7441 }
7442
64a0c779
DN		 7443 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7444 return 0;
7445}
7446
64a0c779
DN		 7447/* Match the given token against cur_token. If they match, read the next
7448 token from the operand string. */
7449static int
7450intel_match_token (code)
e5cb08ac 7451 int code;
64a0c779
DN		 7452{
7453 if (cur_token.code == code)
7454 {
7455 intel_get_token ();
7456 return 1;
7457 }
7458 else
7459 {
0477af35 7460 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7461 return 0;
7462 }
7463}
7464
64a0c779
DN		 7465/* Read a new token from intel_parser.op_string and store it in cur_token. */
7466static void
7467intel_get_token ()
7468{
7469 char *end_op;
7470 const reg_entry *reg;
7471 struct intel_token new_token;
7472
7473 new_token.code = T_NIL;
7474 new_token.reg = NULL;
7475 new_token.str = NULL;
7476
4a1805b1 7477 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7478 cur_token to prev_token. */
7479 if (prev_token.str)
7480 free (prev_token.str);
7481
7482 prev_token = cur_token;
7483
7484 /* Skip whitespace. */
7485 while (is_space_char (*intel_parser.op_string))
7486 intel_parser.op_string++;
7487
7488 /* Return an empty token if we find nothing else on the line. */
7489 if (*intel_parser.op_string == '\0')
7490 {
7491 cur_token = new_token;
7492 return;
7493 }
7494
7495 /* The new token cannot be larger than the remainder of the operand
7496 string. */
a724f0f4 7497 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7498 new_token.str[0] = '\0';
7499
7500 if (strchr ("0123456789", *intel_parser.op_string))
7501 {
7502 char *p = new_token.str;
7503 char *q = intel_parser.op_string;
7504 new_token.code = T_CONST;
7505
7506 /* Allow any kind of identifier char to encompass floating point and
7507 hexadecimal numbers. */
7508 while (is_identifier_char (*q))
7509 *p++ = *q++;
7510 *p = '\0';
7511
7512 /* Recognize special symbol names [0-9][bf]. */
7513 if (strlen (intel_parser.op_string) == 2
4a1805b1 7514 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7515 || intel_parser.op_string[1] == 'f'))
7516 new_token.code = T_ID;
7517 }
7518
4d1bb795 7519 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7520 {
4d1bb795
JB		 7521 size_t len = end_op - intel_parser.op_string;
7522
64a0c779
DN		 7523 new_token.code = T_REG;
7524 new_token.reg = reg;
7525
4d1bb795
JB		 7526 memcpy (new_token.str, intel_parser.op_string, len);
7527 new_token.str[len] = '\0';
64a0c779
DN		 7528 }
7529
7530 else if (is_identifier_char (*intel_parser.op_string))
7531 {
7532 char *p = new_token.str;
7533 char *q = intel_parser.op_string;
7534
7535 /* A '.' or '$' followed by an identifier char is an identifier.
7536 Otherwise, it's operator '.' followed by an expression. */
7537 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7538 {
9306ca4a
JB		 7539 new_token.code = '.';
7540 new_token.str[0] = '.';
64a0c779
DN		 7541 new_token.str[1] = '\0';
7542 }
7543 else
7544 {
7545 while (is_identifier_char (*q) || *q == '@')
7546 *p++ = *q++;
7547 *p = '\0';
7548
9306ca4a
JB		 7549 if (strcasecmp (new_token.str, "NOT") == 0)
7550 new_token.code = '~';
7551
7552 else if (strcasecmp (new_token.str, "MOD") == 0)
7553 new_token.code = '%';
7554
7555 else if (strcasecmp (new_token.str, "AND") == 0)
7556 new_token.code = '&';
7557
7558 else if (strcasecmp (new_token.str, "OR") == 0)
7559 new_token.code = '|';
7560
7561 else if (strcasecmp (new_token.str, "XOR") == 0)
7562 new_token.code = '^';
7563
7564 else if (strcasecmp (new_token.str, "SHL") == 0)
7565 new_token.code = T_SHL;
7566
7567 else if (strcasecmp (new_token.str, "SHR") == 0)
7568 new_token.code = T_SHR;
7569
7570 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7571 new_token.code = T_BYTE;
7572
7573 else if (strcasecmp (new_token.str, "WORD") == 0)
7574 new_token.code = T_WORD;
7575
7576 else if (strcasecmp (new_token.str, "DWORD") == 0)
7577 new_token.code = T_DWORD;
7578
9306ca4a
JB		 7579 else if (strcasecmp (new_token.str, "FWORD") == 0)
7580 new_token.code = T_FWORD;
7581
64a0c779
DN		 7582 else if (strcasecmp (new_token.str, "QWORD") == 0)
7583 new_token.code = T_QWORD;
7584
9306ca4a
JB		 7585 else if (strcasecmp (new_token.str, "TBYTE") == 0
7586 /* XXX remove (gcc still uses it) */
7587 || strcasecmp (new_token.str, "XWORD") == 0)
7588 new_token.code = T_TBYTE;
7589
7590 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7591 || strcasecmp (new_token.str, "OWORD") == 0)
7592 new_token.code = T_XMMWORD;
64a0c779
DN		 7593
7594 else if (strcasecmp (new_token.str, "PTR") == 0)
7595 new_token.code = T_PTR;
7596
7597 else if (strcasecmp (new_token.str, "SHORT") == 0)
7598 new_token.code = T_SHORT;
7599
7600 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7601 {
7602 new_token.code = T_OFFSET;
7603
7604 /* ??? This is not mentioned in the MASM grammar but gcc
7605 makes use of it with -mintel-syntax. OFFSET may be
7606 followed by FLAT: */
7607 if (strncasecmp (q, " FLAT:", 6) == 0)
7608 strcat (new_token.str, " FLAT:");
7609 }
7610
7611 /* ??? This is not mentioned in the MASM grammar. */
7612 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7613 {
7614 new_token.code = T_OFFSET;
7615 if (*q == ':')
7616 strcat (new_token.str, ":");
7617 else
7618 as_bad (_("`:' expected"));
7619 }
64a0c779
DN		 7620
7621 else
7622 new_token.code = T_ID;
7623 }
7624 }
7625
9306ca4a
JB		 7626 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7627 {
7628 new_token.code = *intel_parser.op_string;
7629 new_token.str[0] = *intel_parser.op_string;
7630 new_token.str[1] = '\0';
7631 }
7632
7633 else if (strchr ("<>", *intel_parser.op_string)
7634 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7635 {
7636 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7637 new_token.str[0] = *intel_parser.op_string;
7638 new_token.str[1] = *intel_parser.op_string;
7639 new_token.str[2] = '\0';
7640 }
7641
64a0c779 7642 else
0477af35 7643 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7644
7645 intel_parser.op_string += strlen (new_token.str);
7646 cur_token = new_token;
7647}
7648
64a0c779
DN		 7649/* Put cur_token back into the token stream and make cur_token point to
7650 prev_token. */
7651static void
7652intel_putback_token ()
7653{
a724f0f4
JB		 7654 if (cur_token.code != T_NIL)
7655 {
7656 intel_parser.op_string -= strlen (cur_token.str);
7657 free (cur_token.str);
7658 }
64a0c779 7659 cur_token = prev_token;
4a1805b1 7660
64a0c779
DN		 7661 /* Forget prev_token. */
7662 prev_token.code = T_NIL;
7663 prev_token.reg = NULL;
7664 prev_token.str = NULL;
7665}
54cfded0 7666
a4447b93 7667int
1df69f4f 7668tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7669{
7670 unsigned int regnum;
7671 unsigned int regnames_count;
089dfecd 7672 static const char *const regnames_32[] =
54cfded0 7673 {
a4447b93
RH		 7674 "eax", "ecx", "edx", "ebx",
7675 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7676 "eip", "eflags", NULL,
7677 "st0", "st1", "st2", "st3",
7678 "st4", "st5", "st6", "st7",
7679 NULL, NULL,
7680 "xmm0", "xmm1", "xmm2", "xmm3",
7681 "xmm4", "xmm5", "xmm6", "xmm7",
7682 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7683 "mm4", "mm5", "mm6", "mm7",
7684 "fcw", "fsw", "mxcsr",
7685 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7686 "tr", "ldtr"
54cfded0 7687 };
089dfecd 7688 static const char *const regnames_64[] =
54cfded0 7689 {
089dfecd
JB		 7690 "rax", "rdx", "rcx", "rbx",
7691 "rsi", "rdi", "rbp", "rsp",
7692 "r8", "r9", "r10", "r11",
54cfded0 7693 "r12", "r13", "r14", "r15",
089dfecd
JB		 7694 "rip",
7695 "xmm0", "xmm1", "xmm2", "xmm3",
7696 "xmm4", "xmm5", "xmm6", "xmm7",
7697 "xmm8", "xmm9", "xmm10", "xmm11",
7698 "xmm12", "xmm13", "xmm14", "xmm15",
7699 "st0", "st1", "st2", "st3",
7700 "st4", "st5", "st6", "st7",
7701 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7702 "mm4", "mm5", "mm6", "mm7",
7703 "rflags",
7704 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7705 "fs.base", "gs.base", NULL, NULL,
7706 "tr", "ldtr",
7707 "mxcsr", "fcw", "fsw"
54cfded0 7708 };
089dfecd 7709 const char *const *regnames;
54cfded0
AM		 7710
7711 if (flag_code == CODE_64BIT)
7712 {
7713 regnames = regnames_64;
0cea6190 7714 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7715 }
7716 else
7717 {
7718 regnames = regnames_32;
0cea6190 7719 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7720 }
7721
7722 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7723 if (regnames[regnum] != NULL
7724 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7725 return regnum;
7726
54cfded0
AM		 7727 return -1;
7728}
7729
7730void
7731tc_x86_frame_initial_instructions (void)
7732{
a4447b93
RH		 7733 static unsigned int sp_regno;
7734
7735 if (!sp_regno)
7736 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7737 ? "rsp" : "esp");
7738
7739 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7740 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7741}
d2b2c203
DJ		 7742
7743int
7744i386_elf_section_type (const char *str, size_t len)
7745{
7746 if (flag_code == CODE_64BIT
7747 && len == sizeof ("unwind") - 1
7748 && strncmp (str, "unwind", 6) == 0)
7749 return SHT_X86_64_UNWIND;
7750
7751 return -1;
7752}
bb41ade5
AM		 7753
7754#ifdef TE_PE
7755void
7756tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7757{
7758 expressionS expr;
7759
7760 expr.X_op = O_secrel;
7761 expr.X_add_symbol = symbol;
7762 expr.X_add_number = 0;
7763 emit_expr (&expr, size);
7764}
7765#endif
3b22753a
L		 7766
7767#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7768/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7769
7770int
7771x86_64_section_letter (int letter, char **ptr_msg)
7772{
7773 if (flag_code == CODE_64BIT)
7774 {
7775 if (letter == 'l')
7776 return SHF_X86_64_LARGE;
7777
7778 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7779 }
3b22753a 7780 else
64e74474 7781 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7782 return -1;
7783}
7784
7785int
7786x86_64_section_word (char *str, size_t len)
7787{
8620418b 7788 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7789 return SHF_X86_64_LARGE;
7790
7791 return -1;
7792}
7793
7794static void
7795handle_large_common (int small ATTRIBUTE_UNUSED)
7796{
7797 if (flag_code != CODE_64BIT)
7798 {
7799 s_comm_internal (0, elf_common_parse);
7800 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7801 }
7802 else
7803 {
7804 static segT lbss_section;
7805 asection *saved_com_section_ptr = elf_com_section_ptr;
7806 asection *saved_bss_section = bss_section;
7807
7808 if (lbss_section == NULL)
7809 {
7810 flagword applicable;
7811 segT seg = now_seg;
7812 subsegT subseg = now_subseg;
7813
7814 /* The .lbss section is for local .largecomm symbols. */
7815 lbss_section = subseg_new (".lbss", 0);
7816 applicable = bfd_applicable_section_flags (stdoutput);
7817 bfd_set_section_flags (stdoutput, lbss_section,
7818 applicable & SEC_ALLOC);
7819 seg_info (lbss_section)->bss = 1;
7820
7821 subseg_set (seg, subseg);
7822 }
7823
7824 elf_com_section_ptr = &_bfd_elf_large_com_section;
7825 bss_section = lbss_section;
7826
7827 s_comm_internal (0, elf_common_parse);
7828
7829 elf_com_section_ptr = saved_com_section_ptr;
7830 bss_section = saved_bss_section;
7831 }
7832}
7833#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
A mirror of the official binutils-gdb repository