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* binutils-all/testranges.s: Replace .value with .short.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
6305a203
L		 117/* 386 opcode byte to code indirect addressing. */
118typedef struct
119{
120 unsigned base;
121 unsigned index;
122 unsigned scale;
123}
124sib_byte;
125
6305a203
L		 126/* x86 arch names, types and features */
127typedef struct
128{
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132}
133arch_entry;
134
e3bb37b5
L		 135static void set_code_flag (int);
136static void set_16bit_gcc_code_flag (int);
137static void set_intel_syntax (int);
1efbbeb4 138static void set_intel_mnemonic (int);
db51cc60 139static void set_allow_index_reg (int);
cb19c032 140static void set_sse_check (int);
e3bb37b5 141static void set_cpu_arch (int);
6482c264 142#ifdef TE_PE
e3bb37b5 143static void pe_directive_secrel (int);
6482c264 144#endif
e3bb37b5
L		 145static void signed_cons (int);
146static char *output_invalid (int c);
ee86248c
JB		 147static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
148 const char *);
149static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
150 const char *);
a7619375 151static int i386_att_operand (char *);
e3bb37b5 152static int i386_intel_operand (char *, int);
ee86248c
JB		 153static int i386_intel_simplify (expressionS *);
154static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 155static const reg_entry *parse_register (char *, char **);
156static char *parse_insn (char *, char *);
157static char *parse_operands (char *, const char *);
158static void swap_operands (void);
4d456e3d 159static void swap_2_operands (int, int);
e3bb37b5
L		 160static void optimize_imm (void);
161static void optimize_disp (void);
fa99fab2 162static const template *match_template (void);
e3bb37b5
L		 163static int check_string (void);
164static int process_suffix (void);
165static int check_byte_reg (void);
166static int check_long_reg (void);
167static int check_qword_reg (void);
168static int check_word_reg (void);
169static int finalize_imm (void);
170static int process_operands (void);
171static const seg_entry *build_modrm_byte (void);
172static void output_insn (void);
173static void output_imm (fragS *, offsetT);
174static void output_disp (fragS *, offsetT);
29b0f896 175#ifndef I386COFF
e3bb37b5 176static void s_bss (int);
252b5132 177#endif
17d4e2a2
L		 178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179static void handle_large_common (int small ATTRIBUTE_UNUSED);
180#endif
252b5132 181
a847613f 182static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 183
c0f3af97
L		 184/* VEX prefix. */
185typedef struct
186{
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
189 unsigned int length;
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
192} vex_prefix;
193
252b5132 194/* 'md_assemble ()' gathers together information and puts it into a
47926f60 195 i386_insn. */
252b5132 196
520dc8e8
AM		 197union i386_op
198 {
199 expressionS *disps;
200 expressionS *imms;
201 const reg_entry *regs;
202 };
203
252b5132
RH		 204struct _i386_insn
205 {
47926f60 206 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 207 template tm;
208
7d5e4556
L		 209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
252b5132
RH		 211 char suffix;
212
47926f60 213 /* OPERANDS gives the number of given operands. */
252b5132
RH		 214 unsigned int operands;
215
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
47926f60 218 operands. */
252b5132
RH		 219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
220
221 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 222 use OP[i] for the corresponding operand. */
40fb9820 223 i386_operand_type types[MAX_OPERANDS];
252b5132 224
520dc8e8
AM		 225 /* Displacement expression, immediate expression, or register for each
226 operand. */
227 union i386_op op[MAX_OPERANDS];
252b5132 228
3e73aa7c
JH		 229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231#define Operand_PCrel 1
232
252b5132 233 /* Relocation type for operand */
f86103b7 234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 235
252b5132
RH		 236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
241
242 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 243 explicit segment overrides are given. */
ce8a8b2f 244 const seg_entry *seg[2];
252b5132
RH		 245
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
250
251 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 252 addressing modes of this insn are encoded. */
252b5132 253 modrm_byte rm;
3e73aa7c 254 rex_byte rex;
252b5132 255 sib_byte sib;
c0f3af97 256 vex_prefix vex;
b6169b20
L		 257
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
252b5132
RH		 260 };
261
262typedef struct _i386_insn i386_insn;
263
264/* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
32137342 266const char extra_symbol_chars[] = "*%-(["
252b5132 267#ifdef LEX_AT
32137342
NC		 268 "@"
269#endif
270#ifdef LEX_QM
271 "?"
252b5132 272#endif
32137342 273 ;
252b5132 274
29b0f896
AM		 275#if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 277 && !defined (TE_GNU) \
29b0f896 278 && !defined (TE_LINUX) \
32137342 279 && !defined (TE_NETWARE) \
29b0f896
AM		 280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
252b5132 282/* This array holds the chars that always start a comment. If the
b3b91714
AM		 283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285const char *i386_comment_chars = "#/";
286#define SVR4_COMMENT_CHARS 1
252b5132 287#define PREFIX_SEPARATOR '\\'
252b5132 288
b3b91714
AM		 289#else
290const char *i386_comment_chars = "#";
291#define PREFIX_SEPARATOR '/'
292#endif
293
252b5132
RH		 294/* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 298 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
252b5132 301 '/' isn't otherwise defined. */
b3b91714 302const char line_comment_chars[] = "#/";
252b5132 303
63a0b638 304const char line_separator_chars[] = ";";
252b5132 305
ce8a8b2f
AM		 306/* Chars that can be used to separate mant from exp in floating point
307 nums. */
252b5132
RH		 308const char EXP_CHARS[] = "eE";
309
ce8a8b2f
AM		 310/* Chars that mean this number is a floating point constant
311 As in 0f12.456
312 or 0d1.2345e12. */
252b5132
RH		 313const char FLT_CHARS[] = "fFdDxX";
314
ce8a8b2f 315/* Tables for lexical analysis. */
252b5132
RH		 316static char mnemonic_chars[256];
317static char register_chars[256];
318static char operand_chars[256];
319static char identifier_chars[256];
320static char digit_chars[256];
321
ce8a8b2f 322/* Lexical macros. */
252b5132
RH		 323#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324#define is_operand_char(x) (operand_chars[(unsigned char) x])
325#define is_register_char(x) (register_chars[(unsigned char) x])
326#define is_space_char(x) ((x) == ' ')
327#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328#define is_digit_char(x) (digit_chars[(unsigned char) x])
329
0234cb7c 330/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 331static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
332
333/* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
47926f60 336 assembler instruction). */
252b5132 337static char save_stack[32];
ce8a8b2f 338static char *save_stack_p;
252b5132
RH		 339#define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341#define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
343
47926f60 344/* The instruction we're assembling. */
252b5132
RH		 345static i386_insn i;
346
347/* Possible templates for current insn. */
348static const templates *current_templates;
349
31b2323c
L		 350/* Per instruction expressionS buffers: max displacements & immediates. */
351static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 353
47926f60 354/* Current operand we are working on. */
ee86248c 355static int this_operand = -1;
252b5132 356
3e73aa7c
JH		 357/* We support four different modes. FLAG_CODE variable is used to distinguish
358 these. */
359
360enum flag_code {
361 CODE_32BIT,
362 CODE_16BIT,
363 CODE_64BIT };
364
365static enum flag_code flag_code;
4fa24527 366static unsigned int object_64bit;
3e73aa7c
JH		 367static int use_rela_relocations = 0;
368
369/* The names used to print error messages. */
b77a7acd 370static const char *flag_code_names[] =
3e73aa7c
JH		 371 {
372 "32",
373 "16",
374 "64"
375 };
252b5132 376
47926f60
KH		 377/* 1 for intel syntax,
378 0 if att syntax. */
379static int intel_syntax = 0;
252b5132 380
1efbbeb4
L		 381/* 1 for intel mnemonic,
382 0 if att mnemonic. */
383static int intel_mnemonic = !SYSV386_COMPAT;
384
5209009a 385/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 386static int old_gcc = OLDGCC_COMPAT;
387
a60de03c
JB		 388/* 1 if pseudo registers are permitted. */
389static int allow_pseudo_reg = 0;
390
47926f60
KH		 391/* 1 if register prefix % not required. */
392static int allow_naked_reg = 0;
252b5132 393
ba104c83 394/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 395static int allow_index_reg = 0;
396
daf50ae7
L		 397static enum
398 {
399 sse_check_none = 0,
400 sse_check_warning,
401 sse_check_error
402 }
403sse_check;
404
2ca3ace5
L		 405/* Register prefix used for error message. */
406static const char *register_prefix = "%";
407
47926f60
KH		 408/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411static char stackop_size = '\0';
eecb386c 412
12b55ccc
L		 413/* Non-zero to optimize code alignment. */
414int optimize_align_code = 1;
415
47926f60
KH		 416/* Non-zero to quieten some warnings. */
417static int quiet_warnings = 0;
a38cf1db 418
47926f60
KH		 419/* CPU name. */
420static const char *cpu_arch_name = NULL;
6305a203 421static char *cpu_sub_arch_name = NULL;
a38cf1db 422
47926f60 423/* CPU feature flags. */
40fb9820
L		 424static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
425
ccc9c027
L		 426/* If we have selected a cpu we are generating instructions for. */
427static int cpu_arch_tune_set = 0;
428
9103f4f4 429/* Cpu we are generating instructions for. */
fbf3f584 430enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 431
432/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 433static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 434
ccc9c027 435/* CPU instruction set architecture used. */
fbf3f584 436enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 437
9103f4f4 438/* CPU feature flags of instruction set architecture used. */
fbf3f584 439i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 440
fddf5b5b
AM		 441/* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443static unsigned int no_cond_jump_promotion = 0;
444
c0f3af97
L		 445/* Encode SSE instructions with VEX prefix. */
446static unsigned int sse2avx;
447
29b0f896 448/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 449static symbolS *GOT_symbol;
29b0f896 450
a4447b93
RH		 451/* The dwarf2 return column, adjusted for 32 or 64 bit. */
452unsigned int x86_dwarf2_return_column;
453
454/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455int x86_cie_data_alignment;
456
252b5132 457/* Interface to relax_segment.
fddf5b5b
AM		 458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
252b5132 461
47926f60 462/* Types. */
93c2a809
AM		 463#define UNCOND_JUMP 0
464#define COND_JUMP 1
465#define COND_JUMP86 2
fddf5b5b 466
47926f60 467/* Sizes. */
252b5132
RH		 468#define CODE16 1
469#define SMALL 0
29b0f896 470#define SMALL16 (SMALL | CODE16)
252b5132 471#define BIG 2
29b0f896 472#define BIG16 (BIG | CODE16)
252b5132
RH		 473
474#ifndef INLINE
475#ifdef __GNUC__
476#define INLINE __inline__
477#else
478#define INLINE
479#endif
480#endif
481
fddf5b5b
AM		 482#define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484#define TYPE_FROM_RELAX_STATE(s) \
485 ((s) >> 2)
486#define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 488
489/* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
496
497const relax_typeS md_relax_table[] =
498{
24eab124
AM		 499 /* The fields are:
500 1) most positive reach of this state,
501 2) most negative reach of this state,
93c2a809 502 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 503 4) which index into the table to try if we can't fit into this one. */
252b5132 504
fddf5b5b 505 /* UNCOND_JUMP states. */
93c2a809
AM		 506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
252b5132 510 {0, 0, 4, 0},
93c2a809
AM		 511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 513 {0, 0, 2, 0},
514
93c2a809
AM		 515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
520 {0, 0, 5, 0},
fddf5b5b 521 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 522 1 extra opcode byte, 2 displacement bytes. */
523 {0, 0, 3, 0},
524
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
533 {0, 0, 4, 0}
252b5132
RH		 534};
535
9103f4f4
L		 536static const arch_entry cpu_arch[] =
537{
6305a203
L		 538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
543 CPU_NONE_FLAGS },
544 { "i186", PROCESSOR_UNKNOWN,
545 CPU_I186_FLAGS },
546 { "i286", PROCESSOR_UNKNOWN,
547 CPU_I286_FLAGS },
548 { "i386", PROCESSOR_I386,
549 CPU_I386_FLAGS },
550 { "i486", PROCESSOR_I486,
551 CPU_I486_FLAGS },
552 { "i586", PROCESSOR_PENTIUM,
553 CPU_I586_FLAGS },
554 { "i686", PROCESSOR_PENTIUMPRO,
555 CPU_I686_FLAGS },
556 { "pentium", PROCESSOR_PENTIUM,
557 CPU_I586_FLAGS },
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
559 CPU_I686_FLAGS },
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
561 CPU_P2_FLAGS },
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
563 CPU_P3_FLAGS },
564 { "pentium4", PROCESSOR_PENTIUM4,
565 CPU_P4_FLAGS },
566 { "prescott", PROCESSOR_NOCONA,
567 CPU_CORE_FLAGS },
568 { "nocona", PROCESSOR_NOCONA,
569 CPU_NOCONA_FLAGS },
570 { "yonah", PROCESSOR_CORE,
571 CPU_CORE_FLAGS },
572 { "core", PROCESSOR_CORE,
573 CPU_CORE_FLAGS },
574 { "merom", PROCESSOR_CORE2,
575 CPU_CORE2_FLAGS },
576 { "core2", PROCESSOR_CORE2,
577 CPU_CORE2_FLAGS },
bd5295b2
L		 578 { "corei7", PROCESSOR_COREI7,
579 CPU_COREI7_FLAGS },
8a9036a4
L		 580 { "l1om", PROCESSOR_GENERIC64,
581 CPU_L1OM_FLAGS },
6305a203
L		 582 { "k6", PROCESSOR_K6,
583 CPU_K6_FLAGS },
584 { "k6_2", PROCESSOR_K6,
585 CPU_K6_2_FLAGS },
586 { "athlon", PROCESSOR_ATHLON,
587 CPU_ATHLON_FLAGS },
588 { "sledgehammer", PROCESSOR_K8,
589 CPU_K8_FLAGS },
590 { "opteron", PROCESSOR_K8,
591 CPU_K8_FLAGS },
592 { "k8", PROCESSOR_K8,
593 CPU_K8_FLAGS },
594 { "amdfam10", PROCESSOR_AMDFAM10,
595 CPU_AMDFAM10_FLAGS },
309d3373
JB		 596 { ".8087", PROCESSOR_UNKNOWN,
597 CPU_8087_FLAGS },
598 { ".287", PROCESSOR_UNKNOWN,
599 CPU_287_FLAGS },
600 { ".387", PROCESSOR_UNKNOWN,
601 CPU_387_FLAGS },
602 { ".no87", PROCESSOR_UNKNOWN,
603 CPU_ANY87_FLAGS },
6305a203
L		 604 { ".mmx", PROCESSOR_UNKNOWN,
605 CPU_MMX_FLAGS },
309d3373
JB		 606 { ".nommx", PROCESSOR_UNKNOWN,
607 CPU_3DNOWA_FLAGS },
6305a203
L		 608 { ".sse", PROCESSOR_UNKNOWN,
609 CPU_SSE_FLAGS },
610 { ".sse2", PROCESSOR_UNKNOWN,
611 CPU_SSE2_FLAGS },
612 { ".sse3", PROCESSOR_UNKNOWN,
613 CPU_SSE3_FLAGS },
614 { ".ssse3", PROCESSOR_UNKNOWN,
615 CPU_SSSE3_FLAGS },
616 { ".sse4.1", PROCESSOR_UNKNOWN,
617 CPU_SSE4_1_FLAGS },
618 { ".sse4.2", PROCESSOR_UNKNOWN,
619 CPU_SSE4_2_FLAGS },
620 { ".sse4", PROCESSOR_UNKNOWN,
621 CPU_SSE4_2_FLAGS },
309d3373
JB		 622 { ".nosse", PROCESSOR_UNKNOWN,
623 CPU_ANY_SSE_FLAGS },
c0f3af97
L		 624 { ".avx", PROCESSOR_UNKNOWN,
625 CPU_AVX_FLAGS },
309d3373
JB		 626 { ".noavx", PROCESSOR_UNKNOWN,
627 CPU_ANY_AVX_FLAGS },
6305a203
L		 628 { ".vmx", PROCESSOR_UNKNOWN,
629 CPU_VMX_FLAGS },
630 { ".smx", PROCESSOR_UNKNOWN,
631 CPU_SMX_FLAGS },
f03fe4c1
L		 632 { ".xsave", PROCESSOR_UNKNOWN,
633 CPU_XSAVE_FLAGS },
c0f3af97
L		 634 { ".aes", PROCESSOR_UNKNOWN,
635 CPU_AES_FLAGS },
594ab6a3
L		 636 { ".pclmul", PROCESSOR_UNKNOWN,
637 CPU_PCLMUL_FLAGS },
c0f3af97 638 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 639 CPU_PCLMUL_FLAGS },
c0f3af97
L		 640 { ".fma", PROCESSOR_UNKNOWN,
641 CPU_FMA_FLAGS },
922d8de8
DR		 642 { ".fma4", PROCESSOR_UNKNOWN,
643 CPU_FMA4_FLAGS },
f1f8f695
L		 644 { ".movbe", PROCESSOR_UNKNOWN,
645 CPU_MOVBE_FLAGS },
646 { ".ept", PROCESSOR_UNKNOWN,
647 CPU_EPT_FLAGS },
bd5295b2
L		 648 { ".clflush", PROCESSOR_UNKNOWN,
649 CPU_CLFLUSH_FLAGS },
650 { ".syscall", PROCESSOR_UNKNOWN,
651 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 652 { ".rdtscp", PROCESSOR_UNKNOWN,
653 CPU_RDTSCP_FLAGS },
6305a203
L		 654 { ".3dnow", PROCESSOR_UNKNOWN,
655 CPU_3DNOW_FLAGS },
656 { ".3dnowa", PROCESSOR_UNKNOWN,
657 CPU_3DNOWA_FLAGS },
658 { ".padlock", PROCESSOR_UNKNOWN,
659 CPU_PADLOCK_FLAGS },
660 { ".pacifica", PROCESSOR_UNKNOWN,
661 CPU_SVME_FLAGS },
662 { ".svme", PROCESSOR_UNKNOWN,
663 CPU_SVME_FLAGS },
664 { ".sse4a", PROCESSOR_UNKNOWN,
665 CPU_SSE4A_FLAGS },
666 { ".abm", PROCESSOR_UNKNOWN,
667 CPU_ABM_FLAGS },
e413e4e9
AM		 668};
669
704209c0 670#ifdef I386COFF
a6c24e68
NC		 671/* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
673
674static symbolS *
675pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
676{
677 addressT align = 0;
678
679 SKIP_WHITESPACE ();
680
7ab9ffdd 681 if (needs_align
a6c24e68
NC		 682 && *input_line_pointer == ',')
683 {
684 align = parse_align (needs_align - 1);
7ab9ffdd 685
a6c24e68
NC		 686 if (align == (addressT) -1)
687 return NULL;
688 }
689 else
690 {
691 if (size >= 8)
692 align = 3;
693 else if (size >= 4)
694 align = 2;
695 else if (size >= 2)
696 align = 1;
697 else
698 align = 0;
699 }
700
701 bss_alloc (symbolP, size, align);
702 return symbolP;
703}
704
704209c0 705static void
a6c24e68
NC		 706pe_lcomm (int needs_align)
707{
708 s_comm_internal (needs_align * 2, pe_lcomm_internal);
709}
704209c0 710#endif
a6c24e68 711
29b0f896
AM		 712const pseudo_typeS md_pseudo_table[] =
713{
714#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes, 0},
716#else
717 {"align", s_align_ptwo, 0},
718#endif
719 {"arch", set_cpu_arch, 0},
720#ifndef I386COFF
721 {"bss", s_bss, 0},
a6c24e68
NC		 722#else
723 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 724#endif
725 {"ffloat", float_cons, 'f'},
726 {"dfloat", float_cons, 'd'},
727 {"tfloat", float_cons, 'x'},
728 {"value", cons, 2},
d182319b 729 {"slong", signed_cons, 4},
29b0f896
AM		 730 {"noopt", s_ignore, 0},
731 {"optim", s_ignore, 0},
732 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
733 {"code16", set_code_flag, CODE_16BIT},
734 {"code32", set_code_flag, CODE_32BIT},
735 {"code64", set_code_flag, CODE_64BIT},
736 {"intel_syntax", set_intel_syntax, 1},
737 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 738 {"intel_mnemonic", set_intel_mnemonic, 1},
739 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 740 {"allow_index_reg", set_allow_index_reg, 1},
741 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 742 {"sse_check", set_sse_check, 0},
3b22753a
L		 743#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common, 0},
07a53e5c 745#else
e3bb37b5 746 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 747 {"loc", dwarf2_directive_loc, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 749#endif
6482c264
NC		 750#ifdef TE_PE
751 {"secrel32", pe_directive_secrel, 0},
752#endif
29b0f896
AM		 753 {0, 0, 0}
754};
755
756/* For interface with expression (). */
757extern char *input_line_pointer;
758
759/* Hash table for instruction mnemonic lookup. */
760static struct hash_control *op_hash;
761
762/* Hash table for register lookup. */
763static struct hash_control *reg_hash;
764\f
252b5132 765void
e3bb37b5 766i386_align_code (fragS *fragP, int count)
252b5132 767{
ce8a8b2f
AM		 768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
252b5132
RH		 771 static const char f32_1[] =
772 {0x90}; /* nop */
773 static const char f32_2[] =
ccc9c027 774 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 775 static const char f32_3[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5[] =
780 {0x90, /* nop */
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8[] =
787 {0x90, /* nop */
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 807 static const char f16_3[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 809 static const char f16_4[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5[] =
812 {0x90, /* nop */
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 823 static const char jump_31[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 828 static const char *const f32_patt[] = {
829 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 830 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 831 };
832 static const char *const f16_patt[] = {
76bc74dc 833 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 834 };
ccc9c027
L		 835 /* nopl (%[re]ax) */
836 static const char alt_3[] =
837 {0x0f,0x1f,0x00};
838 /* nopl 0(%[re]ax) */
839 static const char alt_4[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
859 /* data16
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11[] =
862 {0x66,
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 data16
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12[] =
868 {0x66,
869 0x66,
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* data16
872 data16
873 data16
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13[] =
876 {0x66,
877 0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 data16
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14[] =
886 {0x66,
887 0x66,
888 0x66,
889 0x66,
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
891 /* data16
892 data16
893 data16
894 data16
895 data16
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15[] =
898 {0x66,
899 0x66,
900 0x66,
901 0x66,
902 0x66,
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
915 nopl 0L(%[re]ax) */
916 static const char alt_short_13[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
919 /* nopl 0L(%[re]ax)
920 nopl 0L(%[re]ax) */
921 static const char alt_short_14[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
924 /* nopl 0L(%[re]ax)
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt[] = {
930 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
931 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
932 alt_short_14, alt_short_15
933 };
934 static const char *const alt_long_patt[] = {
935 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
936 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
937 alt_long_14, alt_long_15
938 };
252b5132 939
76bc74dc
L		 940 /* Only align for at least a positive non-zero boundary. */
941 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 942 return;
3e73aa7c 943
ccc9c027
L		 944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
4eed87de 946
76bc74dc
L		 947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 954
76bc74dc
L		 955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
957 be used.
ccc9c027
L		 958
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
961
962 if (flag_code == CODE_16BIT)
963 {
ccc9c027 964 if (count > 8)
33fef721 965 {
76bc74dc
L		 966 memcpy (fragP->fr_literal + fragP->fr_fix,
967 jump_31, count);
968 /* Adjust jump offset. */
969 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 970 }
76bc74dc
L		 971 else
972 memcpy (fragP->fr_literal + fragP->fr_fix,
973 f16_patt[count - 1], count);
252b5132 974 }
33fef721 975 else
ccc9c027
L		 976 {
977 const char *const *patt = NULL;
978
fbf3f584 979 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 980 {
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune)
983 {
984 case PROCESSOR_UNKNOWN:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
fbf3f584 987 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 988 patt = alt_long_patt;
ccc9c027
L		 989 else
990 patt = f32_patt;
991 break;
ccc9c027
L		 992 case PROCESSOR_PENTIUMPRO:
993 case PROCESSOR_PENTIUM4:
994 case PROCESSOR_NOCONA:
ef05d495 995 case PROCESSOR_CORE:
76bc74dc 996 case PROCESSOR_CORE2:
bd5295b2 997 case PROCESSOR_COREI7:
76bc74dc
L		 998 case PROCESSOR_GENERIC64:
999 patt = alt_long_patt;
1000 break;
ccc9c027
L		 1001 case PROCESSOR_K6:
1002 case PROCESSOR_ATHLON:
1003 case PROCESSOR_K8:
4eed87de 1004 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1005 patt = alt_short_patt;
1006 break;
76bc74dc 1007 case PROCESSOR_I386:
ccc9c027
L		 1008 case PROCESSOR_I486:
1009 case PROCESSOR_PENTIUM:
1010 case PROCESSOR_GENERIC32:
1011 patt = f32_patt;
1012 break;
4eed87de 1013 }
ccc9c027
L		 1014 }
1015 else
1016 {
fbf3f584 1017 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1018 {
1019 case PROCESSOR_UNKNOWN:
e6a14101 1020 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1021 PROCESSOR_UNKNOWN. */
1022 abort ();
1023 break;
1024
76bc74dc 1025 case PROCESSOR_I386:
ccc9c027
L		 1026 case PROCESSOR_I486:
1027 case PROCESSOR_PENTIUM:
ccc9c027
L		 1028 case PROCESSOR_K6:
1029 case PROCESSOR_ATHLON:
1030 case PROCESSOR_K8:
4eed87de 1031 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1032 case PROCESSOR_GENERIC32:
1033 /* We use cpu_arch_isa_flags to check if we CAN optimize
1034 for Cpu686. */
fbf3f584 1035 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1036 patt = alt_short_patt;
1037 else
1038 patt = f32_patt;
1039 break;
76bc74dc
L		 1040 case PROCESSOR_PENTIUMPRO:
1041 case PROCESSOR_PENTIUM4:
1042 case PROCESSOR_NOCONA:
1043 case PROCESSOR_CORE:
ef05d495 1044 case PROCESSOR_CORE2:
bd5295b2 1045 case PROCESSOR_COREI7:
fbf3f584 1046 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1047 patt = alt_long_patt;
1048 else
1049 patt = f32_patt;
1050 break;
1051 case PROCESSOR_GENERIC64:
76bc74dc 1052 patt = alt_long_patt;
ccc9c027 1053 break;
4eed87de 1054 }
ccc9c027
L		 1055 }
1056
76bc74dc
L		 1057 if (patt == f32_patt)
1058 {
1059 /* If the padding is less than 15 bytes, we use the normal
1060 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1061 its offset. */
1062 int limit;
1063
1064 /* For 64bit, the limit is 3 bytes. */
1065 if (flag_code == CODE_64BIT
1066 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1067 limit = 3;
1068 else
1069 limit = 15;
1070 if (count < limit)
76bc74dc
L		 1071 memcpy (fragP->fr_literal + fragP->fr_fix,
1072 patt[count - 1], count);
1073 else
1074 {
1075 memcpy (fragP->fr_literal + fragP->fr_fix,
1076 jump_31, count);
1077 /* Adjust jump offset. */
1078 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1079 }
1080 }
1081 else
1082 {
1083 /* Maximum length of an instruction is 15 byte. If the
1084 padding is greater than 15 bytes and we don't use jump,
1085 we have to break it into smaller pieces. */
1086 int padding = count;
1087 while (padding > 15)
1088 {
1089 padding -= 15;
1090 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1091 patt [14], 15);
1092 }
1093
1094 if (padding)
1095 memcpy (fragP->fr_literal + fragP->fr_fix,
1096 patt [padding - 1], padding);
1097 }
ccc9c027 1098 }
33fef721 1099 fragP->fr_var = count;
252b5132
RH		 1100}
1101
c6fb90c8 1102static INLINE int
0dfbf9d7 1103operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1104{
0dfbf9d7 1105 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1106 {
1107 case 3:
0dfbf9d7 1108 if (x->array[2])
c6fb90c8
L		 1109 return 0;
1110 case 2:
0dfbf9d7 1111 if (x->array[1])
c6fb90c8
L		 1112 return 0;
1113 case 1:
0dfbf9d7 1114 return !x->array[0];
c6fb90c8
L		 1115 default:
1116 abort ();
1117 }
40fb9820
L		 1118}
1119
c6fb90c8 1120static INLINE void
0dfbf9d7 1121operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1122{
0dfbf9d7 1123 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1124 {
1125 case 3:
0dfbf9d7 1126 x->array[2] = v;
c6fb90c8 1127 case 2:
0dfbf9d7 1128 x->array[1] = v;
c6fb90c8 1129 case 1:
0dfbf9d7 1130 x->array[0] = v;
c6fb90c8
L		 1131 break;
1132 default:
1133 abort ();
1134 }
1135}
40fb9820 1136
c6fb90c8 1137static INLINE int
0dfbf9d7
L		 1138operand_type_equal (const union i386_operand_type *x,
1139 const union i386_operand_type *y)
c6fb90c8 1140{
0dfbf9d7 1141 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1142 {
1143 case 3:
0dfbf9d7 1144 if (x->array[2] != y->array[2])
c6fb90c8
L		 1145 return 0;
1146 case 2:
0dfbf9d7 1147 if (x->array[1] != y->array[1])
c6fb90c8
L		 1148 return 0;
1149 case 1:
0dfbf9d7 1150 return x->array[0] == y->array[0];
c6fb90c8
L		 1151 break;
1152 default:
1153 abort ();
1154 }
1155}
40fb9820 1156
0dfbf9d7
L		 1157static INLINE int
1158cpu_flags_all_zero (const union i386_cpu_flags *x)
1159{
1160 switch (ARRAY_SIZE(x->array))
1161 {
1162 case 3:
1163 if (x->array[2])
1164 return 0;
1165 case 2:
1166 if (x->array[1])
1167 return 0;
1168 case 1:
1169 return !x->array[0];
1170 default:
1171 abort ();
1172 }
1173}
1174
1175static INLINE void
1176cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1177{
1178 switch (ARRAY_SIZE(x->array))
1179 {
1180 case 3:
1181 x->array[2] = v;
1182 case 2:
1183 x->array[1] = v;
1184 case 1:
1185 x->array[0] = v;
1186 break;
1187 default:
1188 abort ();
1189 }
1190}
1191
1192static INLINE int
1193cpu_flags_equal (const union i386_cpu_flags *x,
1194 const union i386_cpu_flags *y)
1195{
1196 switch (ARRAY_SIZE(x->array))
1197 {
1198 case 3:
1199 if (x->array[2] != y->array[2])
1200 return 0;
1201 case 2:
1202 if (x->array[1] != y->array[1])
1203 return 0;
1204 case 1:
1205 return x->array[0] == y->array[0];
1206 break;
1207 default:
1208 abort ();
1209 }
1210}
c6fb90c8
L		 1211
1212static INLINE int
1213cpu_flags_check_cpu64 (i386_cpu_flags f)
1214{
1215 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1216 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1217}
1218
c6fb90c8
L		 1219static INLINE i386_cpu_flags
1220cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1221{
c6fb90c8
L		 1222 switch (ARRAY_SIZE (x.array))
1223 {
1224 case 3:
1225 x.array [2] &= y.array [2];
1226 case 2:
1227 x.array [1] &= y.array [1];
1228 case 1:
1229 x.array [0] &= y.array [0];
1230 break;
1231 default:
1232 abort ();
1233 }
1234 return x;
1235}
40fb9820 1236
c6fb90c8
L		 1237static INLINE i386_cpu_flags
1238cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1239{
c6fb90c8 1240 switch (ARRAY_SIZE (x.array))
40fb9820 1241 {
c6fb90c8
L		 1242 case 3:
1243 x.array [2] |= y.array [2];
1244 case 2:
1245 x.array [1] |= y.array [1];
1246 case 1:
1247 x.array [0] |= y.array [0];
40fb9820
L		 1248 break;
1249 default:
1250 abort ();
1251 }
40fb9820
L		 1252 return x;
1253}
1254
309d3373
JB		 1255static INLINE i386_cpu_flags
1256cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1257{
1258 switch (ARRAY_SIZE (x.array))
1259 {
1260 case 3:
1261 x.array [2] &= ~y.array [2];
1262 case 2:
1263 x.array [1] &= ~y.array [1];
1264 case 1:
1265 x.array [0] &= ~y.array [0];
1266 break;
1267 default:
1268 abort ();
1269 }
1270 return x;
1271}
1272
c0f3af97
L		 1273#define CPU_FLAGS_ARCH_MATCH 0x1
1274#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1275#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1276#define CPU_FLAGS_PCLMUL_MATCH 0x8
1277#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1278
a5ff0eb2 1279#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1280 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1281 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1282#define CPU_FLAGS_PERFECT_MATCH \
1283 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1284
1285/* Return CPU flags match bits. */
3629bb00 1286
40fb9820 1287static int
c0f3af97 1288cpu_flags_match (const template *t)
40fb9820 1289{
c0f3af97
L		 1290 i386_cpu_flags x = t->cpu_flags;
1291 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1292
1293 x.bitfield.cpu64 = 0;
1294 x.bitfield.cpuno64 = 0;
1295
0dfbf9d7 1296 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1297 {
1298 /* This instruction is available on all archs. */
1299 match |= CPU_FLAGS_32BIT_MATCH;
1300 }
3629bb00
L		 1301 else
1302 {
c0f3af97 1303 /* This instruction is available only on some archs. */
3629bb00
L		 1304 i386_cpu_flags cpu = cpu_arch_flags;
1305
1306 cpu.bitfield.cpu64 = 0;
1307 cpu.bitfield.cpuno64 = 0;
1308 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1309 if (!cpu_flags_all_zero (&cpu))
1310 {
a5ff0eb2
L		 1311 if (x.bitfield.cpuavx)
1312 {
ce2f5b3c 1313 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1314 if (cpu.bitfield.cpuavx)
1315 {
1316 /* Check SSE2AVX. */
1317 if (!t->opcode_modifier.sse2avx|| sse2avx)
1318 {
1319 match |= (CPU_FLAGS_ARCH_MATCH
1320 | CPU_FLAGS_AVX_MATCH);
1321 /* Check AES. */
1322 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1323 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1324 /* Check PCLMUL. */
1325 if (!x.bitfield.cpupclmul
1326 || cpu.bitfield.cpupclmul)
1327 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1328 }
1329 }
1330 else
1331 match |= CPU_FLAGS_ARCH_MATCH;
1332 }
1333 else
c0f3af97
L		 1334 match |= CPU_FLAGS_32BIT_MATCH;
1335 }
3629bb00 1336 }
c0f3af97 1337 return match;
40fb9820
L		 1338}
1339
c6fb90c8
L		 1340static INLINE i386_operand_type
1341operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1342{
c6fb90c8
L		 1343 switch (ARRAY_SIZE (x.array))
1344 {
1345 case 3:
1346 x.array [2] &= y.array [2];
1347 case 2:
1348 x.array [1] &= y.array [1];
1349 case 1:
1350 x.array [0] &= y.array [0];
1351 break;
1352 default:
1353 abort ();
1354 }
1355 return x;
40fb9820
L		 1356}
1357
c6fb90c8
L		 1358static INLINE i386_operand_type
1359operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1360{
c6fb90c8 1361 switch (ARRAY_SIZE (x.array))
40fb9820 1362 {
c6fb90c8
L		 1363 case 3:
1364 x.array [2] |= y.array [2];
1365 case 2:
1366 x.array [1] |= y.array [1];
1367 case 1:
1368 x.array [0] |= y.array [0];
40fb9820
L		 1369 break;
1370 default:
1371 abort ();
1372 }
c6fb90c8
L		 1373 return x;
1374}
40fb9820 1375
c6fb90c8
L		 1376static INLINE i386_operand_type
1377operand_type_xor (i386_operand_type x, i386_operand_type y)
1378{
1379 switch (ARRAY_SIZE (x.array))
1380 {
1381 case 3:
1382 x.array [2] ^= y.array [2];
1383 case 2:
1384 x.array [1] ^= y.array [1];
1385 case 1:
1386 x.array [0] ^= y.array [0];
1387 break;
1388 default:
1389 abort ();
1390 }
40fb9820
L		 1391 return x;
1392}
1393
1394static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1395static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1396static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1397static const i386_operand_type inoutportreg
1398 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1399static const i386_operand_type reg16_inoutportreg
1400 = OPERAND_TYPE_REG16_INOUTPORTREG;
1401static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1402static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1403static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1404static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1405static const i386_operand_type anydisp
1406 = OPERAND_TYPE_ANYDISP;
40fb9820 1407static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1408static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1409static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1410static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1411static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1412static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1413static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1414static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1415static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1416static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1417static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1418
1419enum operand_type
1420{
1421 reg,
40fb9820
L		 1422 imm,
1423 disp,
1424 anymem
1425};
1426
c6fb90c8 1427static INLINE int
40fb9820
L		 1428operand_type_check (i386_operand_type t, enum operand_type c)
1429{
1430 switch (c)
1431 {
1432 case reg:
1433 return (t.bitfield.reg8
1434 || t.bitfield.reg16
1435 || t.bitfield.reg32
1436 || t.bitfield.reg64);
1437
40fb9820
L		 1438 case imm:
1439 return (t.bitfield.imm8
1440 || t.bitfield.imm8s
1441 || t.bitfield.imm16
1442 || t.bitfield.imm32
1443 || t.bitfield.imm32s
1444 || t.bitfield.imm64);
1445
1446 case disp:
1447 return (t.bitfield.disp8
1448 || t.bitfield.disp16
1449 || t.bitfield.disp32
1450 || t.bitfield.disp32s
1451 || t.bitfield.disp64);
1452
1453 case anymem:
1454 return (t.bitfield.disp8
1455 || t.bitfield.disp16
1456 || t.bitfield.disp32
1457 || t.bitfield.disp32s
1458 || t.bitfield.disp64
1459 || t.bitfield.baseindex);
1460
1461 default:
1462 abort ();
1463 }
2cfe26b6
AM		 1464
1465 return 0;
40fb9820
L		 1466}
1467
5c07affc
L		 1468/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1469 operand J for instruction template T. */
1470
1471static INLINE int
1472match_reg_size (const template *t, unsigned int j)
1473{
1474 return !((i.types[j].bitfield.byte
1475 && !t->operand_types[j].bitfield.byte)
1476 || (i.types[j].bitfield.word
1477 && !t->operand_types[j].bitfield.word)
1478 || (i.types[j].bitfield.dword
1479 && !t->operand_types[j].bitfield.dword)
1480 || (i.types[j].bitfield.qword
1481 && !t->operand_types[j].bitfield.qword));
1482}
1483
1484/* Return 1 if there is no conflict in any size on operand J for
1485 instruction template T. */
1486
1487static INLINE int
1488match_mem_size (const template *t, unsigned int j)
1489{
1490 return (match_reg_size (t, j)
1491 && !((i.types[j].bitfield.unspecified
1492 && !t->operand_types[j].bitfield.unspecified)
1493 || (i.types[j].bitfield.fword
1494 && !t->operand_types[j].bitfield.fword)
1495 || (i.types[j].bitfield.tbyte
1496 && !t->operand_types[j].bitfield.tbyte)
1497 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1498 && !t->operand_types[j].bitfield.xmmword)
1499 || (i.types[j].bitfield.ymmword
1500 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1501}
1502
1503/* Return 1 if there is no size conflict on any operands for
1504 instruction template T. */
1505
1506static INLINE int
1507operand_size_match (const template *t)
1508{
1509 unsigned int j;
1510 int match = 1;
1511
1512 /* Don't check jump instructions. */
1513 if (t->opcode_modifier.jump
1514 || t->opcode_modifier.jumpbyte
1515 || t->opcode_modifier.jumpdword
1516 || t->opcode_modifier.jumpintersegment)
1517 return match;
1518
1519 /* Check memory and accumulator operand size. */
1520 for (j = 0; j < i.operands; j++)
1521 {
1522 if (t->operand_types[j].bitfield.anysize)
1523 continue;
1524
1525 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1526 {
1527 match = 0;
1528 break;
1529 }
1530
1531 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1532 {
1533 match = 0;
1534 break;
1535 }
1536 }
1537
1538 if (match
1539 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1540 return match;
1541
1542 /* Check reverse. */
9c2799c2 1543 gas_assert (i.operands == 2);
5c07affc
L		 1544
1545 match = 1;
1546 for (j = 0; j < 2; j++)
1547 {
1548 if (t->operand_types[j].bitfield.acc
1549 && !match_reg_size (t, j ? 0 : 1))
1550 {
1551 match = 0;
1552 break;
1553 }
1554
1555 if (i.types[j].bitfield.mem
1556 && !match_mem_size (t, j ? 0 : 1))
1557 {
1558 match = 0;
1559 break;
1560 }
1561 }
1562
1563 return match;
1564}
1565
c6fb90c8 1566static INLINE int
40fb9820
L		 1567operand_type_match (i386_operand_type overlap,
1568 i386_operand_type given)
1569{
1570 i386_operand_type temp = overlap;
1571
1572 temp.bitfield.jumpabsolute = 0;
7d5e4556 1573 temp.bitfield.unspecified = 0;
5c07affc
L		 1574 temp.bitfield.byte = 0;
1575 temp.bitfield.word = 0;
1576 temp.bitfield.dword = 0;
1577 temp.bitfield.fword = 0;
1578 temp.bitfield.qword = 0;
1579 temp.bitfield.tbyte = 0;
1580 temp.bitfield.xmmword = 0;
c0f3af97 1581 temp.bitfield.ymmword = 0;
0dfbf9d7 1582 if (operand_type_all_zero (&temp))
40fb9820
L		 1583 return 0;
1584
1585 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1586 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1587}
1588
7d5e4556 1589/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1590 unless the expected operand type register overlap is null.
1591 Note that Acc in a template matches every size of reg. */
1592
c6fb90c8 1593static INLINE int
40fb9820
L		 1594operand_type_register_match (i386_operand_type m0,
1595 i386_operand_type g0,
1596 i386_operand_type t0,
1597 i386_operand_type m1,
1598 i386_operand_type g1,
1599 i386_operand_type t1)
1600{
1601 if (!operand_type_check (g0, reg))
1602 return 1;
1603
1604 if (!operand_type_check (g1, reg))
1605 return 1;
1606
1607 if (g0.bitfield.reg8 == g1.bitfield.reg8
1608 && g0.bitfield.reg16 == g1.bitfield.reg16
1609 && g0.bitfield.reg32 == g1.bitfield.reg32
1610 && g0.bitfield.reg64 == g1.bitfield.reg64)
1611 return 1;
1612
1613 if (m0.bitfield.acc)
1614 {
1615 t0.bitfield.reg8 = 1;
1616 t0.bitfield.reg16 = 1;
1617 t0.bitfield.reg32 = 1;
1618 t0.bitfield.reg64 = 1;
1619 }
1620
1621 if (m1.bitfield.acc)
1622 {
1623 t1.bitfield.reg8 = 1;
1624 t1.bitfield.reg16 = 1;
1625 t1.bitfield.reg32 = 1;
1626 t1.bitfield.reg64 = 1;
1627 }
1628
1629 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1630 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1631 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1632 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1633}
1634
252b5132 1635static INLINE unsigned int
40fb9820 1636mode_from_disp_size (i386_operand_type t)
252b5132 1637{
40fb9820
L		 1638 if (t.bitfield.disp8)
1639 return 1;
1640 else if (t.bitfield.disp16
1641 || t.bitfield.disp32
1642 || t.bitfield.disp32s)
1643 return 2;
1644 else
1645 return 0;
252b5132
RH		 1646}
1647
1648static INLINE int
e3bb37b5 1649fits_in_signed_byte (offsetT num)
252b5132
RH		 1650{
1651 return (num >= -128) && (num <= 127);
47926f60 1652}
252b5132
RH		 1653
1654static INLINE int
e3bb37b5 1655fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1656{
1657 return (num & 0xff) == num;
47926f60 1658}
252b5132
RH		 1659
1660static INLINE int
e3bb37b5 1661fits_in_unsigned_word (offsetT num)
252b5132
RH		 1662{
1663 return (num & 0xffff) == num;
47926f60 1664}
252b5132
RH		 1665
1666static INLINE int
e3bb37b5 1667fits_in_signed_word (offsetT num)
252b5132
RH		 1668{
1669 return (-32768 <= num) && (num <= 32767);
47926f60 1670}
2a962e6d 1671
3e73aa7c 1672static INLINE int
e3bb37b5 1673fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1674{
1675#ifndef BFD64
1676 return 1;
1677#else
1678 return (!(((offsetT) -1 << 31) & num)
1679 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1680#endif
1681} /* fits_in_signed_long() */
2a962e6d 1682
3e73aa7c 1683static INLINE int
e3bb37b5 1684fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1685{
1686#ifndef BFD64
1687 return 1;
1688#else
1689 return (num & (((offsetT) 2 << 31) - 1)) == num;
1690#endif
1691} /* fits_in_unsigned_long() */
252b5132 1692
40fb9820 1693static i386_operand_type
e3bb37b5 1694smallest_imm_type (offsetT num)
252b5132 1695{
40fb9820 1696 i386_operand_type t;
7ab9ffdd 1697
0dfbf9d7 1698 operand_type_set (&t, 0);
40fb9820
L		 1699 t.bitfield.imm64 = 1;
1700
1701 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1702 {
1703 /* This code is disabled on the 486 because all the Imm1 forms
1704 in the opcode table are slower on the i486. They're the
1705 versions with the implicitly specified single-position
1706 displacement, which has another syntax if you really want to
1707 use that form. */
40fb9820
L		 1708 t.bitfield.imm1 = 1;
1709 t.bitfield.imm8 = 1;
1710 t.bitfield.imm8s = 1;
1711 t.bitfield.imm16 = 1;
1712 t.bitfield.imm32 = 1;
1713 t.bitfield.imm32s = 1;
1714 }
1715 else if (fits_in_signed_byte (num))
1716 {
1717 t.bitfield.imm8 = 1;
1718 t.bitfield.imm8s = 1;
1719 t.bitfield.imm16 = 1;
1720 t.bitfield.imm32 = 1;
1721 t.bitfield.imm32s = 1;
1722 }
1723 else if (fits_in_unsigned_byte (num))
1724 {
1725 t.bitfield.imm8 = 1;
1726 t.bitfield.imm16 = 1;
1727 t.bitfield.imm32 = 1;
1728 t.bitfield.imm32s = 1;
1729 }
1730 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1731 {
1732 t.bitfield.imm16 = 1;
1733 t.bitfield.imm32 = 1;
1734 t.bitfield.imm32s = 1;
1735 }
1736 else if (fits_in_signed_long (num))
1737 {
1738 t.bitfield.imm32 = 1;
1739 t.bitfield.imm32s = 1;
1740 }
1741 else if (fits_in_unsigned_long (num))
1742 t.bitfield.imm32 = 1;
1743
1744 return t;
47926f60 1745}
252b5132 1746
847f7ad4 1747static offsetT
e3bb37b5 1748offset_in_range (offsetT val, int size)
847f7ad4 1749{
508866be 1750 addressT mask;
ba2adb93 1751
847f7ad4
AM		 1752 switch (size)
1753 {
508866be
L		 1754 case 1: mask = ((addressT) 1 << 8) - 1; break;
1755 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1756 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1757#ifdef BFD64
1758 case 8: mask = ((addressT) 2 << 63) - 1; break;
1759#endif
47926f60 1760 default: abort ();
847f7ad4
AM		 1761 }
1762
ba2adb93 1763 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1764 if (!use_rela_relocations)
1765 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1766 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1767
47926f60 1768 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1769 {
1770 char buf1[40], buf2[40];
1771
1772 sprint_value (buf1, val);
1773 sprint_value (buf2, val & mask);
1774 as_warn (_("%s shortened to %s"), buf1, buf2);
1775 }
1776 return val & mask;
1777}
1778
252b5132
RH		 1779/* Returns 0 if attempting to add a prefix where one from the same
1780 class already exists, 1 if non rep/repne added, 2 if rep/repne
1781 added. */
1782static int
e3bb37b5 1783add_prefix (unsigned int prefix)
252b5132
RH		 1784{
1785 int ret = 1;
b1905489 1786 unsigned int q;
252b5132 1787
29b0f896
AM		 1788 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1789 && flag_code == CODE_64BIT)
b1905489 1790 {
161a04f6
L		 1791 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1792 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1793 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1794 ret = 0;
1795 q = REX_PREFIX;
1796 }
3e73aa7c 1797 else
b1905489
JB		 1798 {
1799 switch (prefix)
1800 {
1801 default:
1802 abort ();
1803
1804 case CS_PREFIX_OPCODE:
1805 case DS_PREFIX_OPCODE:
1806 case ES_PREFIX_OPCODE:
1807 case FS_PREFIX_OPCODE:
1808 case GS_PREFIX_OPCODE:
1809 case SS_PREFIX_OPCODE:
1810 q = SEG_PREFIX;
1811 break;
1812
1813 case REPNE_PREFIX_OPCODE:
1814 case REPE_PREFIX_OPCODE:
1815 ret = 2;
1816 /* fall thru */
1817 case LOCK_PREFIX_OPCODE:
1818 q = LOCKREP_PREFIX;
1819 break;
1820
1821 case FWAIT_OPCODE:
1822 q = WAIT_PREFIX;
1823 break;
1824
1825 case ADDR_PREFIX_OPCODE:
1826 q = ADDR_PREFIX;
1827 break;
1828
1829 case DATA_PREFIX_OPCODE:
1830 q = DATA_PREFIX;
1831 break;
1832 }
1833 if (i.prefix[q] != 0)
1834 ret = 0;
1835 }
252b5132 1836
b1905489 1837 if (ret)
252b5132 1838 {
b1905489
JB		 1839 if (!i.prefix[q])
1840 ++i.prefixes;
1841 i.prefix[q] |= prefix;
252b5132 1842 }
b1905489
JB		 1843 else
1844 as_bad (_("same type of prefix used twice"));
252b5132 1845
252b5132
RH		 1846 return ret;
1847}
1848
1849static void
e3bb37b5 1850set_code_flag (int value)
eecb386c 1851{
3e73aa7c 1852 flag_code = value;
40fb9820
L		 1853 if (flag_code == CODE_64BIT)
1854 {
1855 cpu_arch_flags.bitfield.cpu64 = 1;
1856 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1857 }
1858 else
1859 {
1860 cpu_arch_flags.bitfield.cpu64 = 0;
1861 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1862 }
1863 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1864 {
1865 as_bad (_("64bit mode not supported on this CPU."));
1866 }
40fb9820 1867 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1868 {
1869 as_bad (_("32bit mode not supported on this CPU."));
1870 }
eecb386c
AM		 1871 stackop_size = '\0';
1872}
1873
1874static void
e3bb37b5 1875set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1876{
3e73aa7c 1877 flag_code = new_code_flag;
40fb9820
L		 1878 if (flag_code != CODE_16BIT)
1879 abort ();
1880 cpu_arch_flags.bitfield.cpu64 = 0;
1881 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1882 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1883}
1884
1885static void
e3bb37b5 1886set_intel_syntax (int syntax_flag)
252b5132
RH		 1887{
1888 /* Find out if register prefixing is specified. */
1889 int ask_naked_reg = 0;
1890
1891 SKIP_WHITESPACE ();
29b0f896 1892 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1893 {
1894 char *string = input_line_pointer;
1895 int e = get_symbol_end ();
1896
47926f60 1897 if (strcmp (string, "prefix") == 0)
252b5132 1898 ask_naked_reg = 1;
47926f60 1899 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1900 ask_naked_reg = -1;
1901 else
d0b47220 1902 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1903 *input_line_pointer = e;
1904 }
1905 demand_empty_rest_of_line ();
c3332e24 1906
252b5132
RH		 1907 intel_syntax = syntax_flag;
1908
1909 if (ask_naked_reg == 0)
f86103b7
AM		 1910 allow_naked_reg = (intel_syntax
1911 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1912 else
1913 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1914
ee86248c 1915 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1916
e4a3b5a4 1917 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1918 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1919 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1920}
1921
1efbbeb4
L		 1922static void
1923set_intel_mnemonic (int mnemonic_flag)
1924{
e1d4d893 1925 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1926}
1927
db51cc60
L		 1928static void
1929set_allow_index_reg (int flag)
1930{
1931 allow_index_reg = flag;
1932}
1933
cb19c032
L		 1934static void
1935set_sse_check (int dummy ATTRIBUTE_UNUSED)
1936{
1937 SKIP_WHITESPACE ();
1938
1939 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1940 {
1941 char *string = input_line_pointer;
1942 int e = get_symbol_end ();
1943
1944 if (strcmp (string, "none") == 0)
1945 sse_check = sse_check_none;
1946 else if (strcmp (string, "warning") == 0)
1947 sse_check = sse_check_warning;
1948 else if (strcmp (string, "error") == 0)
1949 sse_check = sse_check_error;
1950 else
1951 as_bad (_("bad argument to sse_check directive."));
1952 *input_line_pointer = e;
1953 }
1954 else
1955 as_bad (_("missing argument for sse_check directive"));
1956
1957 demand_empty_rest_of_line ();
1958}
1959
8a9036a4
L		 1960static void
1961check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1962 i386_cpu_flags new ATTRIBUTE_UNUSED)
1963{
1964#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1965 static const char *arch;
1966
1967 /* Intel LIOM is only supported on ELF. */
1968 if (!IS_ELF)
1969 return;
1970
1971 if (!arch)
1972 {
1973 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1974 use default_arch. */
1975 arch = cpu_arch_name;
1976 if (!arch)
1977 arch = default_arch;
1978 }
1979
1980 /* If we are targeting Intel L1OM, wm must enable it. */
1981 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1982 || new.bitfield.cpul1om)
1983 return;
1984
1985 as_bad (_("`%s' is not supported on `%s'"), name, arch);
1986#endif
1987}
1988
e413e4e9 1989static void
e3bb37b5 1990set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1991{
47926f60 1992 SKIP_WHITESPACE ();
e413e4e9 1993
29b0f896 1994 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1995 {
1996 char *string = input_line_pointer;
1997 int e = get_symbol_end ();
9103f4f4 1998 unsigned int i;
40fb9820 1999 i386_cpu_flags flags;
e413e4e9 2000
9103f4f4 2001 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 2002 {
2003 if (strcmp (string, cpu_arch[i].name) == 0)
2004 {
8a9036a4
L		 2005 check_cpu_arch_compatible (string, cpu_arch[i].flags);
2006
5c6af06e
JB		 2007 if (*string != '.')
2008 {
2009 cpu_arch_name = cpu_arch[i].name;
2010 cpu_sub_arch_name = NULL;
40fb9820
L		 2011 cpu_arch_flags = cpu_arch[i].flags;
2012 if (flag_code == CODE_64BIT)
2013 {
2014 cpu_arch_flags.bitfield.cpu64 = 1;
2015 cpu_arch_flags.bitfield.cpuno64 = 0;
2016 }
2017 else
2018 {
2019 cpu_arch_flags.bitfield.cpu64 = 0;
2020 cpu_arch_flags.bitfield.cpuno64 = 1;
2021 }
ccc9c027 2022 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 2023 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 2024 if (!cpu_arch_tune_set)
2025 {
2026 cpu_arch_tune = cpu_arch_isa;
2027 cpu_arch_tune_flags = cpu_arch_isa_flags;
2028 }
5c6af06e
JB		 2029 break;
2030 }
40fb9820 2031
309d3373
JB		 2032 if (strncmp (string + 1, "no", 2))
2033 flags = cpu_flags_or (cpu_arch_flags,
2034 cpu_arch[i].flags);
2035 else
2036 flags = cpu_flags_and_not (cpu_arch_flags,
2037 cpu_arch[i].flags);
0dfbf9d7 2038 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2039 {
6305a203
L		 2040 if (cpu_sub_arch_name)
2041 {
2042 char *name = cpu_sub_arch_name;
2043 cpu_sub_arch_name = concat (name,
2044 cpu_arch[i].name,
1bf57e9f 2045 (const char *) NULL);
6305a203
L		 2046 free (name);
2047 }
2048 else
2049 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2050 cpu_arch_flags = flags;
5c6af06e
JB		 2051 }
2052 *input_line_pointer = e;
2053 demand_empty_rest_of_line ();
2054 return;
e413e4e9
AM		 2055 }
2056 }
9103f4f4 2057 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2058 as_bad (_("no such architecture: `%s'"), string);
2059
2060 *input_line_pointer = e;
2061 }
2062 else
2063 as_bad (_("missing cpu architecture"));
2064
fddf5b5b
AM		 2065 no_cond_jump_promotion = 0;
2066 if (*input_line_pointer == ','
29b0f896 2067 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2068 {
2069 char *string = ++input_line_pointer;
2070 int e = get_symbol_end ();
2071
2072 if (strcmp (string, "nojumps") == 0)
2073 no_cond_jump_promotion = 1;
2074 else if (strcmp (string, "jumps") == 0)
2075 ;
2076 else
2077 as_bad (_("no such architecture modifier: `%s'"), string);
2078
2079 *input_line_pointer = e;
2080 }
2081
e413e4e9
AM		 2082 demand_empty_rest_of_line ();
2083}
2084
8a9036a4
L		 2085enum bfd_architecture
2086i386_arch (void)
2087{
2088 if (cpu_arch_isa_flags.bitfield.cpul1om)
2089 {
2090 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2091 || flag_code != CODE_64BIT)
2092 as_fatal (_("Intel L1OM is 64bit ELF only"));
2093 return bfd_arch_l1om;
2094 }
2095 else
2096 return bfd_arch_i386;
2097}
2098
b9d79e03
JH		 2099unsigned long
2100i386_mach ()
2101{
2102 if (!strcmp (default_arch, "x86_64"))
8a9036a4
L		 2103 {
2104 if (cpu_arch_isa_flags.bitfield.cpul1om)
2105 {
2106 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2107 as_fatal (_("Intel L1OM is 64bit ELF only"));
2108 return bfd_mach_l1om;
2109 }
2110 else
2111 return bfd_mach_x86_64;
2112 }
b9d79e03
JH		 2113 else if (!strcmp (default_arch, "i386"))
2114 return bfd_mach_i386_i386;
2115 else
2116 as_fatal (_("Unknown architecture"));
2117}
b9d79e03 2118\f
252b5132
RH		 2119void
2120md_begin ()
2121{
2122 const char *hash_err;
2123
47926f60 2124 /* Initialize op_hash hash table. */
252b5132
RH		 2125 op_hash = hash_new ();
2126
2127 {
29b0f896
AM		 2128 const template *optab;
2129 templates *core_optab;
252b5132 2130
47926f60
KH		 2131 /* Setup for loop. */
2132 optab = i386_optab;
252b5132
RH		 2133 core_optab = (templates *) xmalloc (sizeof (templates));
2134 core_optab->start = optab;
2135
2136 while (1)
2137 {
2138 ++optab;
2139 if (optab->name == NULL
2140 || strcmp (optab->name, (optab - 1)->name) != 0)
2141 {
2142 /* different name --> ship out current template list;
47926f60 2143 add to hash table; & begin anew. */
252b5132
RH		 2144 core_optab->end = optab;
2145 hash_err = hash_insert (op_hash,
2146 (optab - 1)->name,
5a49b8ac 2147 (void *) core_optab);
252b5132
RH		 2148 if (hash_err)
2149 {
252b5132
RH		 2150 as_fatal (_("Internal Error: Can't hash %s: %s"),
2151 (optab - 1)->name,
2152 hash_err);
2153 }
2154 if (optab->name == NULL)
2155 break;
2156 core_optab = (templates *) xmalloc (sizeof (templates));
2157 core_optab->start = optab;
2158 }
2159 }
2160 }
2161
47926f60 2162 /* Initialize reg_hash hash table. */
252b5132
RH		 2163 reg_hash = hash_new ();
2164 {
29b0f896 2165 const reg_entry *regtab;
c3fe08fa 2166 unsigned int regtab_size = i386_regtab_size;
252b5132 2167
c3fe08fa 2168 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2169 {
5a49b8ac 2170 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2171 if (hash_err)
3e73aa7c
JH		 2172 as_fatal (_("Internal Error: Can't hash %s: %s"),
2173 regtab->reg_name,
2174 hash_err);
252b5132
RH		 2175 }
2176 }
2177
47926f60 2178 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2179 {
29b0f896
AM		 2180 int c;
2181 char *p;
252b5132
RH		 2182
2183 for (c = 0; c < 256; c++)
2184 {
3882b010 2185 if (ISDIGIT (c))
252b5132
RH		 2186 {
2187 digit_chars[c] = c;
2188 mnemonic_chars[c] = c;
2189 register_chars[c] = c;
2190 operand_chars[c] = c;
2191 }
3882b010 2192 else if (ISLOWER (c))
252b5132
RH		 2193 {
2194 mnemonic_chars[c] = c;
2195 register_chars[c] = c;
2196 operand_chars[c] = c;
2197 }
3882b010 2198 else if (ISUPPER (c))
252b5132 2199 {
3882b010 2200 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2201 register_chars[c] = mnemonic_chars[c];
2202 operand_chars[c] = c;
2203 }
2204
3882b010 2205 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2206 identifier_chars[c] = c;
2207 else if (c >= 128)
2208 {
2209 identifier_chars[c] = c;
2210 operand_chars[c] = c;
2211 }
2212 }
2213
2214#ifdef LEX_AT
2215 identifier_chars['@'] = '@';
32137342
NC		 2216#endif
2217#ifdef LEX_QM
2218 identifier_chars['?'] = '?';
2219 operand_chars['?'] = '?';
252b5132 2220#endif
252b5132 2221 digit_chars['-'] = '-';
c0f3af97 2222 mnemonic_chars['_'] = '_';
791fe849 2223 mnemonic_chars['-'] = '-';
0003779b 2224 mnemonic_chars['.'] = '.';
252b5132
RH		 2225 identifier_chars['_'] = '_';
2226 identifier_chars['.'] = '.';
2227
2228 for (p = operand_special_chars; *p != '\0'; p++)
2229 operand_chars[(unsigned char) *p] = *p;
2230 }
2231
2232#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2233 if (IS_ELF)
252b5132
RH		 2234 {
2235 record_alignment (text_section, 2);
2236 record_alignment (data_section, 2);
2237 record_alignment (bss_section, 2);
2238 }
2239#endif
a4447b93
RH		 2240
2241 if (flag_code == CODE_64BIT)
2242 {
2243 x86_dwarf2_return_column = 16;
2244 x86_cie_data_alignment = -8;
2245 }
2246 else
2247 {
2248 x86_dwarf2_return_column = 8;
2249 x86_cie_data_alignment = -4;
2250 }
252b5132
RH		 2251}
2252
2253void
e3bb37b5 2254i386_print_statistics (FILE *file)
252b5132
RH		 2255{
2256 hash_print_statistics (file, "i386 opcode", op_hash);
2257 hash_print_statistics (file, "i386 register", reg_hash);
2258}
2259\f
252b5132
RH		 2260#ifdef DEBUG386
2261
ce8a8b2f 2262/* Debugging routines for md_assemble. */
e3bb37b5 2263static void pte (template *);
40fb9820 2264static void pt (i386_operand_type);
e3bb37b5
L		 2265static void pe (expressionS *);
2266static void ps (symbolS *);
252b5132
RH		 2267
2268static void
e3bb37b5 2269pi (char *line, i386_insn *x)
252b5132 2270{
09f131f2 2271 unsigned int i;
252b5132
RH		 2272
2273 fprintf (stdout, "%s: template ", line);
2274 pte (&x->tm);
09f131f2
JH		 2275 fprintf (stdout, " address: base %s index %s scale %x\n",
2276 x->base_reg ? x->base_reg->reg_name : "none",
2277 x->index_reg ? x->index_reg->reg_name : "none",
2278 x->log2_scale_factor);
2279 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2280 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2281 fprintf (stdout, " sib: base %x index %x scale %x\n",
2282 x->sib.base, x->sib.index, x->sib.scale);
2283 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2284 (x->rex & REX_W) != 0,
2285 (x->rex & REX_R) != 0,
2286 (x->rex & REX_X) != 0,
2287 (x->rex & REX_B) != 0);
252b5132
RH		 2288 for (i = 0; i < x->operands; i++)
2289 {
2290 fprintf (stdout, " #%d: ", i + 1);
2291 pt (x->types[i]);
2292 fprintf (stdout, "\n");
40fb9820
L		 2293 if (x->types[i].bitfield.reg8
2294 || x->types[i].bitfield.reg16
2295 || x->types[i].bitfield.reg32
2296 || x->types[i].bitfield.reg64
2297 || x->types[i].bitfield.regmmx
2298 || x->types[i].bitfield.regxmm
c0f3af97 2299 || x->types[i].bitfield.regymm
40fb9820
L		 2300 || x->types[i].bitfield.sreg2
2301 || x->types[i].bitfield.sreg3
2302 || x->types[i].bitfield.control
2303 || x->types[i].bitfield.debug
2304 || x->types[i].bitfield.test)
520dc8e8 2305 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2306 if (operand_type_check (x->types[i], imm))
520dc8e8 2307 pe (x->op[i].imms);
40fb9820 2308 if (operand_type_check (x->types[i], disp))
520dc8e8 2309 pe (x->op[i].disps);
252b5132
RH		 2310 }
2311}
2312
2313static void
e3bb37b5 2314pte (template *t)
252b5132 2315{
09f131f2 2316 unsigned int i;
252b5132 2317 fprintf (stdout, " %d operands ", t->operands);
47926f60 2318 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2319 if (t->extension_opcode != None)
2320 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2321 if (t->opcode_modifier.d)
252b5132 2322 fprintf (stdout, "D");
40fb9820 2323 if (t->opcode_modifier.w)
252b5132
RH		 2324 fprintf (stdout, "W");
2325 fprintf (stdout, "\n");
2326 for (i = 0; i < t->operands; i++)
2327 {
2328 fprintf (stdout, " #%d type ", i + 1);
2329 pt (t->operand_types[i]);
2330 fprintf (stdout, "\n");
2331 }
2332}
2333
2334static void
e3bb37b5 2335pe (expressionS *e)
252b5132 2336{
24eab124 2337 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2338 fprintf (stdout, " add_number %ld (%lx)\n",
2339 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2340 if (e->X_add_symbol)
2341 {
2342 fprintf (stdout, " add_symbol ");
2343 ps (e->X_add_symbol);
2344 fprintf (stdout, "\n");
2345 }
2346 if (e->X_op_symbol)
2347 {
2348 fprintf (stdout, " op_symbol ");
2349 ps (e->X_op_symbol);
2350 fprintf (stdout, "\n");
2351 }
2352}
2353
2354static void
e3bb37b5 2355ps (symbolS *s)
252b5132
RH		 2356{
2357 fprintf (stdout, "%s type %s%s",
2358 S_GET_NAME (s),
2359 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2360 segment_name (S_GET_SEGMENT (s)));
2361}
2362
7b81dfbb 2363static struct type_name
252b5132 2364 {
40fb9820
L		 2365 i386_operand_type mask;
2366 const char *name;
252b5132 2367 }
7b81dfbb 2368const type_names[] =
252b5132 2369{
40fb9820
L		 2370 { OPERAND_TYPE_REG8, "r8" },
2371 { OPERAND_TYPE_REG16, "r16" },
2372 { OPERAND_TYPE_REG32, "r32" },
2373 { OPERAND_TYPE_REG64, "r64" },
2374 { OPERAND_TYPE_IMM8, "i8" },
2375 { OPERAND_TYPE_IMM8, "i8s" },
2376 { OPERAND_TYPE_IMM16, "i16" },
2377 { OPERAND_TYPE_IMM32, "i32" },
2378 { OPERAND_TYPE_IMM32S, "i32s" },
2379 { OPERAND_TYPE_IMM64, "i64" },
2380 { OPERAND_TYPE_IMM1, "i1" },
2381 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2382 { OPERAND_TYPE_DISP8, "d8" },
2383 { OPERAND_TYPE_DISP16, "d16" },
2384 { OPERAND_TYPE_DISP32, "d32" },
2385 { OPERAND_TYPE_DISP32S, "d32s" },
2386 { OPERAND_TYPE_DISP64, "d64" },
2387 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2388 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2389 { OPERAND_TYPE_CONTROL, "control reg" },
2390 { OPERAND_TYPE_TEST, "test reg" },
2391 { OPERAND_TYPE_DEBUG, "debug reg" },
2392 { OPERAND_TYPE_FLOATREG, "FReg" },
2393 { OPERAND_TYPE_FLOATACC, "FAcc" },
2394 { OPERAND_TYPE_SREG2, "SReg2" },
2395 { OPERAND_TYPE_SREG3, "SReg3" },
2396 { OPERAND_TYPE_ACC, "Acc" },
2397 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2398 { OPERAND_TYPE_REGMMX, "rMMX" },
2399 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2400 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2401 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2402};
2403
2404static void
40fb9820 2405pt (i386_operand_type t)
252b5132 2406{
40fb9820 2407 unsigned int j;
c6fb90c8 2408 i386_operand_type a;
252b5132 2409
40fb9820 2410 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2411 {
2412 a = operand_type_and (t, type_names[j].mask);
0349dc08 2413 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2414 fprintf (stdout, "%s, ", type_names[j].name);
2415 }
252b5132
RH		 2416 fflush (stdout);
2417}
2418
2419#endif /* DEBUG386 */
2420\f
252b5132 2421static bfd_reloc_code_real_type
3956db08 2422reloc (unsigned int size,
64e74474
AM		 2423 int pcrel,
2424 int sign,
2425 bfd_reloc_code_real_type other)
252b5132 2426{
47926f60 2427 if (other != NO_RELOC)
3956db08
JB		 2428 {
2429 reloc_howto_type *reloc;
2430
2431 if (size == 8)
2432 switch (other)
2433 {
64e74474
AM		 2434 case BFD_RELOC_X86_64_GOT32:
2435 return BFD_RELOC_X86_64_GOT64;
2436 break;
2437 case BFD_RELOC_X86_64_PLTOFF64:
2438 return BFD_RELOC_X86_64_PLTOFF64;
2439 break;
2440 case BFD_RELOC_X86_64_GOTPC32:
2441 other = BFD_RELOC_X86_64_GOTPC64;
2442 break;
2443 case BFD_RELOC_X86_64_GOTPCREL:
2444 other = BFD_RELOC_X86_64_GOTPCREL64;
2445 break;
2446 case BFD_RELOC_X86_64_TPOFF32:
2447 other = BFD_RELOC_X86_64_TPOFF64;
2448 break;
2449 case BFD_RELOC_X86_64_DTPOFF32:
2450 other = BFD_RELOC_X86_64_DTPOFF64;
2451 break;
2452 default:
2453 break;
3956db08 2454 }
e05278af
JB		 2455
2456 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2457 if (size == 4 && flag_code != CODE_64BIT)
2458 sign = -1;
2459
3956db08
JB		 2460 reloc = bfd_reloc_type_lookup (stdoutput, other);
2461 if (!reloc)
2462 as_bad (_("unknown relocation (%u)"), other);
2463 else if (size != bfd_get_reloc_size (reloc))
2464 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2465 bfd_get_reloc_size (reloc),
2466 size);
2467 else if (pcrel && !reloc->pc_relative)
2468 as_bad (_("non-pc-relative relocation for pc-relative field"));
2469 else if ((reloc->complain_on_overflow == complain_overflow_signed
2470 && !sign)
2471 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2472 && sign > 0))
3956db08
JB		 2473 as_bad (_("relocated field and relocation type differ in signedness"));
2474 else
2475 return other;
2476 return NO_RELOC;
2477 }
252b5132
RH		 2478
2479 if (pcrel)
2480 {
3e73aa7c 2481 if (!sign)
3956db08 2482 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2483 switch (size)
2484 {
2485 case 1: return BFD_RELOC_8_PCREL;
2486 case 2: return BFD_RELOC_16_PCREL;
2487 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2488 case 8: return BFD_RELOC_64_PCREL;
252b5132 2489 }
3956db08 2490 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2491 }
2492 else
2493 {
3956db08 2494 if (sign > 0)
e5cb08ac 2495 switch (size)
3e73aa7c
JH		 2496 {
2497 case 4: return BFD_RELOC_X86_64_32S;
2498 }
2499 else
2500 switch (size)
2501 {
2502 case 1: return BFD_RELOC_8;
2503 case 2: return BFD_RELOC_16;
2504 case 4: return BFD_RELOC_32;
2505 case 8: return BFD_RELOC_64;
2506 }
3956db08
JB		 2507 as_bad (_("cannot do %s %u byte relocation"),
2508 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2509 }
2510
0cc9e1d3 2511 return NO_RELOC;
252b5132
RH		 2512}
2513
47926f60
KH		 2514/* Here we decide which fixups can be adjusted to make them relative to
2515 the beginning of the section instead of the symbol. Basically we need
2516 to make sure that the dynamic relocations are done correctly, so in
2517 some cases we force the original symbol to be used. */
2518
252b5132 2519int
e3bb37b5 2520tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2521{
6d249963 2522#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2523 if (!IS_ELF)
31312f95
AM		 2524 return 1;
2525
a161fe53
AM		 2526 /* Don't adjust pc-relative references to merge sections in 64-bit
2527 mode. */
2528 if (use_rela_relocations
2529 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2530 && fixP->fx_pcrel)
252b5132 2531 return 0;
31312f95 2532
8d01d9a9
AJ		 2533 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2534 and changed later by validate_fix. */
2535 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2536 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2537 return 0;
2538
ce8a8b2f 2539 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2540 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2541 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2542 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2543 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2544 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2545 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2546 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2547 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2548 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2549 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2550 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2551 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2552 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2553 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2554 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2555 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2556 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2557 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2558 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2559 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2560 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2561 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2562 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2563 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2564 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2565 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2566 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2567 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2568 return 0;
d8045f23
NC		 2569
2570 if (fixP->fx_addsy != NULL
2571 && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION)
2572 return 0;
31312f95 2573#endif
252b5132
RH		 2574 return 1;
2575}
252b5132 2576
b4cac588 2577static int
e3bb37b5 2578intel_float_operand (const char *mnemonic)
252b5132 2579{
9306ca4a
JB		 2580 /* Note that the value returned is meaningful only for opcodes with (memory)
2581 operands, hence the code here is free to improperly handle opcodes that
2582 have no operands (for better performance and smaller code). */
2583
2584 if (mnemonic[0] != 'f')
2585 return 0; /* non-math */
2586
2587 switch (mnemonic[1])
2588 {
2589 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2590 the fs segment override prefix not currently handled because no
2591 call path can make opcodes without operands get here */
2592 case 'i':
2593 return 2 /* integer op */;
2594 case 'l':
2595 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2596 return 3; /* fldcw/fldenv */
2597 break;
2598 case 'n':
2599 if (mnemonic[2] != 'o' /* fnop */)
2600 return 3; /* non-waiting control op */
2601 break;
2602 case 'r':
2603 if (mnemonic[2] == 's')
2604 return 3; /* frstor/frstpm */
2605 break;
2606 case 's':
2607 if (mnemonic[2] == 'a')
2608 return 3; /* fsave */
2609 if (mnemonic[2] == 't')
2610 {
2611 switch (mnemonic[3])
2612 {
2613 case 'c': /* fstcw */
2614 case 'd': /* fstdw */
2615 case 'e': /* fstenv */
2616 case 's': /* fsts[gw] */
2617 return 3;
2618 }
2619 }
2620 break;
2621 case 'x':
2622 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2623 return 0; /* fxsave/fxrstor are not really math ops */
2624 break;
2625 }
252b5132 2626
9306ca4a 2627 return 1;
252b5132
RH		 2628}
2629
c0f3af97
L		 2630/* Build the VEX prefix. */
2631
2632static void
fa99fab2 2633build_vex_prefix (const template *t)
c0f3af97
L		 2634{
2635 unsigned int register_specifier;
2636 unsigned int implied_prefix;
2637 unsigned int vector_length;
2638
2639 /* Check register specifier. */
2640 if (i.vex.register_specifier)
2641 {
2642 register_specifier = i.vex.register_specifier->reg_num;
2643 if ((i.vex.register_specifier->reg_flags & RegRex))
2644 register_specifier += 8;
2645 register_specifier = ~register_specifier & 0xf;
2646 }
2647 else
2648 register_specifier = 0xf;
2649
fa99fab2
L		 2650 /* Use 2-byte VEX prefix by swappping destination and source
2651 operand. */
2652 if (!i.swap_operand
2653 && i.operands == i.reg_operands
2654 && i.tm.opcode_modifier.vex0f
2655 && i.tm.opcode_modifier.s
2656 && i.rex == REX_B)
2657 {
2658 unsigned int xchg = i.operands - 1;
2659 union i386_op temp_op;
2660 i386_operand_type temp_type;
2661
2662 temp_type = i.types[xchg];
2663 i.types[xchg] = i.types[0];
2664 i.types[0] = temp_type;
2665 temp_op = i.op[xchg];
2666 i.op[xchg] = i.op[0];
2667 i.op[0] = temp_op;
2668
9c2799c2 2669 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2670
2671 i.rex = REX_R;
2672 xchg = i.rm.regmem;
2673 i.rm.regmem = i.rm.reg;
2674 i.rm.reg = xchg;
2675
2676 /* Use the next insn. */
2677 i.tm = t[1];
2678 }
2679
c0f3af97
L		 2680 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2681
2682 switch ((i.tm.base_opcode >> 8) & 0xff)
2683 {
2684 case 0:
2685 implied_prefix = 0;
2686 break;
2687 case DATA_PREFIX_OPCODE:
2688 implied_prefix = 1;
2689 break;
2690 case REPE_PREFIX_OPCODE:
2691 implied_prefix = 2;
2692 break;
2693 case REPNE_PREFIX_OPCODE:
2694 implied_prefix = 3;
2695 break;
2696 default:
2697 abort ();
2698 }
2699
2700 /* Use 2-byte VEX prefix if possible. */
2701 if (i.tm.opcode_modifier.vex0f
2702 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2703 {
2704 /* 2-byte VEX prefix. */
2705 unsigned int r;
2706
2707 i.vex.length = 2;
2708 i.vex.bytes[0] = 0xc5;
2709
2710 /* Check the REX.R bit. */
2711 r = (i.rex & REX_R) ? 0 : 1;
2712 i.vex.bytes[1] = (r << 7
2713 | register_specifier << 3
2714 | vector_length << 2
2715 | implied_prefix);
2716 }
2717 else
2718 {
2719 /* 3-byte VEX prefix. */
2720 unsigned int m, w;
2721
2722 if (i.tm.opcode_modifier.vex0f)
2723 m = 0x1;
2724 else if (i.tm.opcode_modifier.vex0f38)
2725 m = 0x2;
2726 else if (i.tm.opcode_modifier.vex0f3a)
2727 m = 0x3;
2728 else
2729 abort ();
2730
2731 i.vex.length = 3;
2732 i.vex.bytes[0] = 0xc4;
2733
2734 /* The high 3 bits of the second VEX byte are 1's compliment
2735 of RXB bits from REX. */
2736 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2737
2738 /* Check the REX.W bit. */
2739 w = (i.rex & REX_W) ? 1 : 0;
2740 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2741 {
2742 if (w)
2743 abort ();
2744
2745 if (i.tm.opcode_modifier.vexw1)
2746 w = 1;
2747 }
2748
2749 i.vex.bytes[2] = (w << 7
2750 | register_specifier << 3
2751 | vector_length << 2
2752 | implied_prefix);
2753 }
2754}
2755
65da13b5
L		 2756static void
2757process_immext (void)
2758{
2759 expressionS *exp;
2760
2761 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2762 {
1fed0ba1
L		 2763 /* SSE3 Instructions have the fixed operands with an opcode
2764 suffix which is coded in the same place as an 8-bit immediate
2765 field would be. Here we check those operands and remove them
2766 afterwards. */
65da13b5
L		 2767 unsigned int x;
2768
2769 for (x = 0; x < i.operands; x++)
2770 if (i.op[x].regs->reg_num != x)
2771 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2772 register_prefix, i.op[x].regs->reg_name, x + 1,
2773 i.tm.name);
2774
2775 i.operands = 0;
65da13b5
L		 2776 }
2777
c0f3af97 2778 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2779 which is coded in the same place as an 8-bit immediate field
2780 would be. Here we fake an 8-bit immediate operand from the
2781 opcode suffix stored in tm.extension_opcode.
2782
c1e679ec 2783 AVX instructions also use this encoding, for some of
c0f3af97 2784 3 argument instructions. */
65da13b5 2785
9c2799c2 2786 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2787 && (i.operands <= 2
2788 || (i.tm.opcode_modifier.vex
2789 && i.operands <= 4)));
65da13b5
L		 2790
2791 exp = &im_expressions[i.imm_operands++];
2792 i.op[i.operands].imms = exp;
2793 i.types[i.operands] = imm8;
2794 i.operands++;
2795 exp->X_op = O_constant;
2796 exp->X_add_number = i.tm.extension_opcode;
2797 i.tm.extension_opcode = None;
2798}
2799
252b5132
RH		 2800/* This is the guts of the machine-dependent assembler. LINE points to a
2801 machine dependent instruction. This function is supposed to emit
2802 the frags/bytes it assembles to. */
2803
2804void
65da13b5 2805md_assemble (char *line)
252b5132 2806{
40fb9820 2807 unsigned int j;
252b5132 2808 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2809 const template *t;
252b5132 2810
47926f60 2811 /* Initialize globals. */
252b5132
RH		 2812 memset (&i, '\0', sizeof (i));
2813 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2814 i.reloc[j] = NO_RELOC;
252b5132
RH		 2815 memset (disp_expressions, '\0', sizeof (disp_expressions));
2816 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2817 save_stack_p = save_stack;
252b5132
RH		 2818
2819 /* First parse an instruction mnemonic & call i386_operand for the operands.
2820 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2821 start of a (possibly prefixed) mnemonic. */
252b5132 2822
29b0f896
AM		 2823 line = parse_insn (line, mnemonic);
2824 if (line == NULL)
2825 return;
252b5132 2826
29b0f896 2827 line = parse_operands (line, mnemonic);
ee86248c 2828 this_operand = -1;
29b0f896
AM		 2829 if (line == NULL)
2830 return;
252b5132 2831
29b0f896
AM		 2832 /* Now we've parsed the mnemonic into a set of templates, and have the
2833 operands at hand. */
2834
2835 /* All intel opcodes have reversed operands except for "bound" and
2836 "enter". We also don't reverse intersegment "jmp" and "call"
2837 instructions with 2 immediate operands so that the immediate segment
050dfa73 2838 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2839 if (intel_syntax
2840 && i.operands > 1
29b0f896 2841 && (strcmp (mnemonic, "bound") != 0)
30123838 2842 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2843 && !(operand_type_check (i.types[0], imm)
2844 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2845 swap_operands ();
2846
ec56d5c0
JB		 2847 /* The order of the immediates should be reversed
2848 for 2 immediates extrq and insertq instructions */
2849 if (i.imm_operands == 2
2850 && (strcmp (mnemonic, "extrq") == 0
2851 || strcmp (mnemonic, "insertq") == 0))
2852 swap_2_operands (0, 1);
2853
29b0f896
AM		 2854 if (i.imm_operands)
2855 optimize_imm ();
2856
b300c311
L		 2857 /* Don't optimize displacement for movabs since it only takes 64bit
2858 displacement. */
2859 if (i.disp_operands
2860 && (flag_code != CODE_64BIT
2861 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2862 optimize_disp ();
2863
2864 /* Next, we find a template that matches the given insn,
2865 making sure the overlap of the given operands types is consistent
2866 with the template operand types. */
252b5132 2867
fa99fab2 2868 if (!(t = match_template ()))
29b0f896 2869 return;
252b5132 2870
daf50ae7 2871 if (sse_check != sse_check_none
81f8a913 2872 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2873 && (i.tm.cpu_flags.bitfield.cpusse
2874 || i.tm.cpu_flags.bitfield.cpusse2
2875 || i.tm.cpu_flags.bitfield.cpusse3
2876 || i.tm.cpu_flags.bitfield.cpussse3
2877 || i.tm.cpu_flags.bitfield.cpusse4_1
2878 || i.tm.cpu_flags.bitfield.cpusse4_2))
2879 {
2880 (sse_check == sse_check_warning
2881 ? as_warn
2882 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2883 }
2884
321fd21e
L		 2885 /* Zap movzx and movsx suffix. The suffix has been set from
2886 "word ptr" or "byte ptr" on the source operand in Intel syntax
2887 or extracted from mnemonic in AT&T syntax. But we'll use
2888 the destination register to choose the suffix for encoding. */
2889 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2890 {
321fd21e
L		 2891 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2892 there is no suffix, the default will be byte extension. */
2893 if (i.reg_operands != 2
2894 && !i.suffix
7ab9ffdd 2895 && intel_syntax)
321fd21e
L		 2896 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2897
2898 i.suffix = 0;
cd61ebfe 2899 }
24eab124 2900
40fb9820 2901 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2902 if (!add_prefix (FWAIT_OPCODE))
2903 return;
252b5132 2904
29b0f896 2905 /* Check string instruction segment overrides. */
40fb9820 2906 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2907 {
2908 if (!check_string ())
5dd0794d 2909 return;
fc0763e6 2910 i.disp_operands = 0;
29b0f896 2911 }
5dd0794d 2912
29b0f896
AM		 2913 if (!process_suffix ())
2914 return;
e413e4e9 2915
bc0844ae
L		 2916 /* Update operand types. */
2917 for (j = 0; j < i.operands; j++)
2918 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2919
29b0f896
AM		 2920 /* Make still unresolved immediate matches conform to size of immediate
2921 given in i.suffix. */
2922 if (!finalize_imm ())
2923 return;
252b5132 2924
40fb9820 2925 if (i.types[0].bitfield.imm1)
29b0f896 2926 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2927
9afe6eb8
L		 2928 /* We only need to check those implicit registers for instructions
2929 with 3 operands or less. */
2930 if (i.operands <= 3)
2931 for (j = 0; j < i.operands; j++)
2932 if (i.types[j].bitfield.inoutportreg
2933 || i.types[j].bitfield.shiftcount
2934 || i.types[j].bitfield.acc
2935 || i.types[j].bitfield.floatacc)
2936 i.reg_operands--;
40fb9820 2937
c0f3af97
L		 2938 /* ImmExt should be processed after SSE2AVX. */
2939 if (!i.tm.opcode_modifier.sse2avx
2940 && i.tm.opcode_modifier.immext)
65da13b5 2941 process_immext ();
252b5132 2942
29b0f896
AM		 2943 /* For insns with operands there are more diddles to do to the opcode. */
2944 if (i.operands)
2945 {
2946 if (!process_operands ())
2947 return;
2948 }
40fb9820 2949 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2950 {
2951 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2952 as_warn (_("translating to `%sp'"), i.tm.name);
2953 }
252b5132 2954
c0f3af97 2955 if (i.tm.opcode_modifier.vex)
fa99fab2 2956 build_vex_prefix (t);
c0f3af97 2957
29b0f896
AM		 2958 /* Handle conversion of 'int $3' --> special int3 insn. */
2959 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2960 {
2961 i.tm.base_opcode = INT3_OPCODE;
2962 i.imm_operands = 0;
2963 }
252b5132 2964
40fb9820
L		 2965 if ((i.tm.opcode_modifier.jump
2966 || i.tm.opcode_modifier.jumpbyte
2967 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2968 && i.op[0].disps->X_op == O_constant)
2969 {
2970 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2971 the absolute address given by the constant. Since ix86 jumps and
2972 calls are pc relative, we need to generate a reloc. */
2973 i.op[0].disps->X_add_symbol = &abs_symbol;
2974 i.op[0].disps->X_op = O_symbol;
2975 }
252b5132 2976
40fb9820 2977 if (i.tm.opcode_modifier.rex64)
161a04f6 2978 i.rex |= REX_W;
252b5132 2979
29b0f896
AM		 2980 /* For 8 bit registers we need an empty rex prefix. Also if the
2981 instruction already has a prefix, we need to convert old
2982 registers to new ones. */
773f551c 2983
40fb9820 2984 if ((i.types[0].bitfield.reg8
29b0f896 2985 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2986 || (i.types[1].bitfield.reg8
29b0f896 2987 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2988 || ((i.types[0].bitfield.reg8
2989 || i.types[1].bitfield.reg8)
29b0f896
AM		 2990 && i.rex != 0))
2991 {
2992 int x;
726c5dcd 2993
29b0f896
AM		 2994 i.rex |= REX_OPCODE;
2995 for (x = 0; x < 2; x++)
2996 {
2997 /* Look for 8 bit operand that uses old registers. */
40fb9820 2998 if (i.types[x].bitfield.reg8
29b0f896 2999 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3000 {
29b0f896
AM		 3001 /* In case it is "hi" register, give up. */
3002 if (i.op[x].regs->reg_num > 3)
a540244d 3003 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3004 "instruction requiring REX prefix."),
a540244d 3005 register_prefix, i.op[x].regs->reg_name);
773f551c 3006
29b0f896
AM		 3007 /* Otherwise it is equivalent to the extended register.
3008 Since the encoding doesn't change this is merely
3009 cosmetic cleanup for debug output. */
3010
3011 i.op[x].regs = i.op[x].regs + 8;
773f551c 3012 }
29b0f896
AM		 3013 }
3014 }
773f551c 3015
7ab9ffdd 3016 if (i.rex != 0)
29b0f896
AM		 3017 add_prefix (REX_OPCODE | i.rex);
3018
3019 /* We are ready to output the insn. */
3020 output_insn ();
3021}
3022
3023static char *
e3bb37b5 3024parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3025{
3026 char *l = line;
3027 char *token_start = l;
3028 char *mnem_p;
5c6af06e
JB		 3029 int supported;
3030 const template *t;
b6169b20 3031 char *dot_p = NULL;
29b0f896
AM		 3032
3033 /* Non-zero if we found a prefix only acceptable with string insns. */
3034 const char *expecting_string_instruction = NULL;
45288df1 3035
29b0f896
AM		 3036 while (1)
3037 {
3038 mnem_p = mnemonic;
3039 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3040 {
b6169b20
L		 3041 if (*mnem_p == '.')
3042 dot_p = mnem_p;
29b0f896
AM		 3043 mnem_p++;
3044 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3045 {
29b0f896
AM		 3046 as_bad (_("no such instruction: `%s'"), token_start);
3047 return NULL;
3048 }
3049 l++;
3050 }
3051 if (!is_space_char (*l)
3052 && *l != END_OF_INSN
e44823cf
JB		 3053 && (intel_syntax
3054 || (*l != PREFIX_SEPARATOR
3055 && *l != ',')))
29b0f896
AM		 3056 {
3057 as_bad (_("invalid character %s in mnemonic"),
3058 output_invalid (*l));
3059 return NULL;
3060 }
3061 if (token_start == l)
3062 {
e44823cf 3063 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3064 as_bad (_("expecting prefix; got nothing"));
3065 else
3066 as_bad (_("expecting mnemonic; got nothing"));
3067 return NULL;
3068 }
45288df1 3069
29b0f896
AM		 3070 /* Look up instruction (or prefix) via hash table. */
3071 current_templates = hash_find (op_hash, mnemonic);
47926f60 3072
29b0f896
AM		 3073 if (*l != END_OF_INSN
3074 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3075 && current_templates
40fb9820 3076 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3077 {
c6fb90c8 3078 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3079 {
3080 as_bad ((flag_code != CODE_64BIT
3081 ? _("`%s' is only supported in 64-bit mode")
3082 : _("`%s' is not supported in 64-bit mode")),
3083 current_templates->start->name);
3084 return NULL;
3085 }
29b0f896
AM		 3086 /* If we are in 16-bit mode, do not allow addr16 or data16.
3087 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3088 if ((current_templates->start->opcode_modifier.size16
3089 || current_templates->start->opcode_modifier.size32)
29b0f896 3090 && flag_code != CODE_64BIT
40fb9820 3091 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3092 ^ (flag_code == CODE_16BIT)))
3093 {
3094 as_bad (_("redundant %s prefix"),
3095 current_templates->start->name);
3096 return NULL;
45288df1 3097 }
29b0f896
AM		 3098 /* Add prefix, checking for repeated prefixes. */
3099 switch (add_prefix (current_templates->start->base_opcode))
3100 {
3101 case 0:
3102 return NULL;
3103 case 2:
3104 expecting_string_instruction = current_templates->start->name;
3105 break;
3106 }
3107 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3108 token_start = ++l;
3109 }
3110 else
3111 break;
3112 }
45288df1 3113
30a55f88 3114 if (!current_templates)
b6169b20 3115 {
30a55f88
L		 3116 /* Check if we should swap operand in encoding. */
3117 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3118 i.swap_operand = 1;
3119 else
3120 goto check_suffix;
3121 mnem_p = dot_p;
3122 *dot_p = '\0';
3123 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3124 }
3125
29b0f896
AM		 3126 if (!current_templates)
3127 {
b6169b20 3128check_suffix:
29b0f896
AM		 3129 /* See if we can get a match by trimming off a suffix. */
3130 switch (mnem_p[-1])
3131 {
3132 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3133 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3134 i.suffix = SHORT_MNEM_SUFFIX;
3135 else
29b0f896
AM		 3136 case BYTE_MNEM_SUFFIX:
3137 case QWORD_MNEM_SUFFIX:
3138 i.suffix = mnem_p[-1];
3139 mnem_p[-1] = '\0';
3140 current_templates = hash_find (op_hash, mnemonic);
3141 break;
3142 case SHORT_MNEM_SUFFIX:
3143 case LONG_MNEM_SUFFIX:
3144 if (!intel_syntax)
3145 {
3146 i.suffix = mnem_p[-1];
3147 mnem_p[-1] = '\0';
3148 current_templates = hash_find (op_hash, mnemonic);
3149 }
3150 break;
252b5132 3151
29b0f896
AM		 3152 /* Intel Syntax. */
3153 case 'd':
3154 if (intel_syntax)
3155 {
9306ca4a 3156 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3157 i.suffix = SHORT_MNEM_SUFFIX;
3158 else
3159 i.suffix = LONG_MNEM_SUFFIX;
3160 mnem_p[-1] = '\0';
3161 current_templates = hash_find (op_hash, mnemonic);
3162 }
3163 break;
3164 }
3165 if (!current_templates)
3166 {
3167 as_bad (_("no such instruction: `%s'"), token_start);
3168 return NULL;
3169 }
3170 }
252b5132 3171
40fb9820
L		 3172 if (current_templates->start->opcode_modifier.jump
3173 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3174 {
3175 /* Check for a branch hint. We allow ",pt" and ",pn" for
3176 predict taken and predict not taken respectively.
3177 I'm not sure that branch hints actually do anything on loop
3178 and jcxz insns (JumpByte) for current Pentium4 chips. They
3179 may work in the future and it doesn't hurt to accept them
3180 now. */
3181 if (l[0] == ',' && l[1] == 'p')
3182 {
3183 if (l[2] == 't')
3184 {
3185 if (!add_prefix (DS_PREFIX_OPCODE))
3186 return NULL;
3187 l += 3;
3188 }
3189 else if (l[2] == 'n')
3190 {
3191 if (!add_prefix (CS_PREFIX_OPCODE))
3192 return NULL;
3193 l += 3;
3194 }
3195 }
3196 }
3197 /* Any other comma loses. */
3198 if (*l == ',')
3199 {
3200 as_bad (_("invalid character %s in mnemonic"),
3201 output_invalid (*l));
3202 return NULL;
3203 }
252b5132 3204
29b0f896 3205 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3206 supported = 0;
3207 for (t = current_templates->start; t < current_templates->end; ++t)
3208 {
c0f3af97
L		 3209 supported |= cpu_flags_match (t);
3210 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3211 goto skip;
5c6af06e 3212 }
3629bb00 3213
c0f3af97 3214 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3215 {
3216 as_bad (flag_code == CODE_64BIT
3217 ? _("`%s' is not supported in 64-bit mode")
3218 : _("`%s' is only supported in 64-bit mode"),
3219 current_templates->start->name);
3220 return NULL;
3221 }
c0f3af97 3222 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3223 {
3629bb00 3224 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3225 current_templates->start->name,
41aacd83 3226 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3227 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3228 return NULL;
29b0f896 3229 }
3629bb00
L		 3230
3231skip:
3232 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3233 && (flag_code != CODE_16BIT))
29b0f896
AM		 3234 {
3235 as_warn (_("use .code16 to ensure correct addressing mode"));
3236 }
252b5132 3237
29b0f896 3238 /* Check for rep/repne without a string instruction. */
f41bbced 3239 if (expecting_string_instruction)
29b0f896 3240 {
f41bbced
JB		 3241 static templates override;
3242
3243 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3244 if (t->opcode_modifier.isstring)
f41bbced
JB		 3245 break;
3246 if (t >= current_templates->end)
3247 {
3248 as_bad (_("expecting string instruction after `%s'"),
64e74474 3249 expecting_string_instruction);
f41bbced
JB		 3250 return NULL;
3251 }
3252 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3253 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3254 break;
3255 override.end = t;
3256 current_templates = &override;
29b0f896 3257 }
252b5132 3258
29b0f896
AM		 3259 return l;
3260}
252b5132 3261
29b0f896 3262static char *
e3bb37b5 3263parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3264{
3265 char *token_start;
3138f287 3266
29b0f896
AM		 3267 /* 1 if operand is pending after ','. */
3268 unsigned int expecting_operand = 0;
252b5132 3269
29b0f896
AM		 3270 /* Non-zero if operand parens not balanced. */
3271 unsigned int paren_not_balanced;
3272
3273 while (*l != END_OF_INSN)
3274 {
3275 /* Skip optional white space before operand. */
3276 if (is_space_char (*l))
3277 ++l;
3278 if (!is_operand_char (*l) && *l != END_OF_INSN)
3279 {
3280 as_bad (_("invalid character %s before operand %d"),
3281 output_invalid (*l),
3282 i.operands + 1);
3283 return NULL;
3284 }
3285 token_start = l; /* after white space */
3286 paren_not_balanced = 0;
3287 while (paren_not_balanced || *l != ',')
3288 {
3289 if (*l == END_OF_INSN)
3290 {
3291 if (paren_not_balanced)
3292 {
3293 if (!intel_syntax)
3294 as_bad (_("unbalanced parenthesis in operand %d."),
3295 i.operands + 1);
3296 else
3297 as_bad (_("unbalanced brackets in operand %d."),
3298 i.operands + 1);
3299 return NULL;
3300 }
3301 else
3302 break; /* we are done */
3303 }
3304 else if (!is_operand_char (*l) && !is_space_char (*l))
3305 {
3306 as_bad (_("invalid character %s in operand %d"),
3307 output_invalid (*l),
3308 i.operands + 1);
3309 return NULL;
3310 }
3311 if (!intel_syntax)
3312 {
3313 if (*l == '(')
3314 ++paren_not_balanced;
3315 if (*l == ')')
3316 --paren_not_balanced;
3317 }
3318 else
3319 {
3320 if (*l == '[')
3321 ++paren_not_balanced;
3322 if (*l == ']')
3323 --paren_not_balanced;
3324 }
3325 l++;
3326 }
3327 if (l != token_start)
3328 { /* Yes, we've read in another operand. */
3329 unsigned int operand_ok;
3330 this_operand = i.operands++;
7d5e4556 3331 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3332 if (i.operands > MAX_OPERANDS)
3333 {
3334 as_bad (_("spurious operands; (%d operands/instruction max)"),
3335 MAX_OPERANDS);
3336 return NULL;
3337 }
3338 /* Now parse operand adding info to 'i' as we go along. */
3339 END_STRING_AND_SAVE (l);
3340
3341 if (intel_syntax)
3342 operand_ok =
3343 i386_intel_operand (token_start,
3344 intel_float_operand (mnemonic));
3345 else
a7619375 3346 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3347
3348 RESTORE_END_STRING (l);
3349 if (!operand_ok)
3350 return NULL;
3351 }
3352 else
3353 {
3354 if (expecting_operand)
3355 {
3356 expecting_operand_after_comma:
3357 as_bad (_("expecting operand after ','; got nothing"));
3358 return NULL;
3359 }
3360 if (*l == ',')
3361 {
3362 as_bad (_("expecting operand before ','; got nothing"));
3363 return NULL;
3364 }
3365 }
7f3f1ea2 3366
29b0f896
AM		 3367 /* Now *l must be either ',' or END_OF_INSN. */
3368 if (*l == ',')
3369 {
3370 if (*++l == END_OF_INSN)
3371 {
3372 /* Just skip it, if it's \n complain. */
3373 goto expecting_operand_after_comma;
3374 }
3375 expecting_operand = 1;
3376 }
3377 }
3378 return l;
3379}
7f3f1ea2 3380
050dfa73 3381static void
4d456e3d 3382swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3383{
3384 union i386_op temp_op;
40fb9820 3385 i386_operand_type temp_type;
050dfa73 3386 enum bfd_reloc_code_real temp_reloc;
4eed87de 3387
050dfa73
MM		 3388 temp_type = i.types[xchg2];
3389 i.types[xchg2] = i.types[xchg1];
3390 i.types[xchg1] = temp_type;
3391 temp_op = i.op[xchg2];
3392 i.op[xchg2] = i.op[xchg1];
3393 i.op[xchg1] = temp_op;
3394 temp_reloc = i.reloc[xchg2];
3395 i.reloc[xchg2] = i.reloc[xchg1];
3396 i.reloc[xchg1] = temp_reloc;
3397}
3398
29b0f896 3399static void
e3bb37b5 3400swap_operands (void)
29b0f896 3401{
b7c61d9a 3402 switch (i.operands)
050dfa73 3403 {
c0f3af97 3404 case 5:
b7c61d9a 3405 case 4:
4d456e3d 3406 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3407 case 3:
3408 case 2:
4d456e3d 3409 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3410 break;
3411 default:
3412 abort ();
29b0f896 3413 }
29b0f896
AM		 3414
3415 if (i.mem_operands == 2)
3416 {
3417 const seg_entry *temp_seg;
3418 temp_seg = i.seg[0];
3419 i.seg[0] = i.seg[1];
3420 i.seg[1] = temp_seg;
3421 }
3422}
252b5132 3423
29b0f896
AM		 3424/* Try to ensure constant immediates are represented in the smallest
3425 opcode possible. */
3426static void
e3bb37b5 3427optimize_imm (void)
29b0f896
AM		 3428{
3429 char guess_suffix = 0;
3430 int op;
252b5132 3431
29b0f896
AM		 3432 if (i.suffix)
3433 guess_suffix = i.suffix;
3434 else if (i.reg_operands)
3435 {
3436 /* Figure out a suffix from the last register operand specified.
3437 We can't do this properly yet, ie. excluding InOutPortReg,
3438 but the following works for instructions with immediates.
3439 In any case, we can't set i.suffix yet. */
3440 for (op = i.operands; --op >= 0;)
40fb9820 3441 if (i.types[op].bitfield.reg8)
7ab9ffdd 3442 {
40fb9820
L		 3443 guess_suffix = BYTE_MNEM_SUFFIX;
3444 break;
3445 }
3446 else if (i.types[op].bitfield.reg16)
252b5132 3447 {
40fb9820
L		 3448 guess_suffix = WORD_MNEM_SUFFIX;
3449 break;
3450 }
3451 else if (i.types[op].bitfield.reg32)
3452 {
3453 guess_suffix = LONG_MNEM_SUFFIX;
3454 break;
3455 }
3456 else if (i.types[op].bitfield.reg64)
3457 {
3458 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3459 break;
252b5132 3460 }
29b0f896
AM		 3461 }
3462 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3463 guess_suffix = WORD_MNEM_SUFFIX;
3464
3465 for (op = i.operands; --op >= 0;)
40fb9820 3466 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3467 {
3468 switch (i.op[op].imms->X_op)
252b5132 3469 {
29b0f896
AM		 3470 case O_constant:
3471 /* If a suffix is given, this operand may be shortened. */
3472 switch (guess_suffix)
252b5132 3473 {
29b0f896 3474 case LONG_MNEM_SUFFIX:
40fb9820
L		 3475 i.types[op].bitfield.imm32 = 1;
3476 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3477 break;
3478 case WORD_MNEM_SUFFIX:
40fb9820
L		 3479 i.types[op].bitfield.imm16 = 1;
3480 i.types[op].bitfield.imm32 = 1;
3481 i.types[op].bitfield.imm32s = 1;
3482 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3483 break;
3484 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3485 i.types[op].bitfield.imm8 = 1;
3486 i.types[op].bitfield.imm8s = 1;
3487 i.types[op].bitfield.imm16 = 1;
3488 i.types[op].bitfield.imm32 = 1;
3489 i.types[op].bitfield.imm32s = 1;
3490 i.types[op].bitfield.imm64 = 1;
29b0f896 3491 break;
252b5132 3492 }
252b5132 3493
29b0f896
AM		 3494 /* If this operand is at most 16 bits, convert it
3495 to a signed 16 bit number before trying to see
3496 whether it will fit in an even smaller size.
3497 This allows a 16-bit operand such as $0xffe0 to
3498 be recognised as within Imm8S range. */
40fb9820 3499 if ((i.types[op].bitfield.imm16)
29b0f896 3500 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3501 {
29b0f896
AM		 3502 i.op[op].imms->X_add_number =
3503 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3504 }
40fb9820 3505 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3506 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3507 == 0))
3508 {
3509 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3510 ^ ((offsetT) 1 << 31))
3511 - ((offsetT) 1 << 31));
3512 }
40fb9820 3513 i.types[op]
c6fb90c8
L		 3514 = operand_type_or (i.types[op],
3515 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3516
29b0f896
AM		 3517 /* We must avoid matching of Imm32 templates when 64bit
3518 only immediate is available. */
3519 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3520 i.types[op].bitfield.imm32 = 0;
29b0f896 3521 break;
252b5132 3522
29b0f896
AM		 3523 case O_absent:
3524 case O_register:
3525 abort ();
3526
3527 /* Symbols and expressions. */
3528 default:
9cd96992
JB		 3529 /* Convert symbolic operand to proper sizes for matching, but don't
3530 prevent matching a set of insns that only supports sizes other
3531 than those matching the insn suffix. */
3532 {
40fb9820 3533 i386_operand_type mask, allowed;
9cd96992
JB		 3534 const template *t;
3535
0dfbf9d7
L		 3536 operand_type_set (&mask, 0);
3537 operand_type_set (&allowed, 0);
40fb9820 3538
4eed87de
AM		 3539 for (t = current_templates->start;
3540 t < current_templates->end;
3541 ++t)
c6fb90c8
L		 3542 allowed = operand_type_or (allowed,
3543 t->operand_types[op]);
9cd96992
JB		 3544 switch (guess_suffix)
3545 {
3546 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3547 mask.bitfield.imm64 = 1;
3548 mask.bitfield.imm32s = 1;
9cd96992
JB		 3549 break;
3550 case LONG_MNEM_SUFFIX:
40fb9820 3551 mask.bitfield.imm32 = 1;
9cd96992
JB		 3552 break;
3553 case WORD_MNEM_SUFFIX:
40fb9820 3554 mask.bitfield.imm16 = 1;
9cd96992
JB		 3555 break;
3556 case BYTE_MNEM_SUFFIX:
40fb9820 3557 mask.bitfield.imm8 = 1;
9cd96992
JB		 3558 break;
3559 default:
9cd96992
JB		 3560 break;
3561 }
c6fb90c8 3562 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3563 if (!operand_type_all_zero (&allowed))
c6fb90c8 3564 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3565 }
29b0f896 3566 break;
252b5132 3567 }
29b0f896
AM		 3568 }
3569}
47926f60 3570
29b0f896
AM		 3571/* Try to use the smallest displacement type too. */
3572static void
e3bb37b5 3573optimize_disp (void)
29b0f896
AM		 3574{
3575 int op;
3e73aa7c 3576
29b0f896 3577 for (op = i.operands; --op >= 0;)
40fb9820 3578 if (operand_type_check (i.types[op], disp))
252b5132 3579 {
b300c311 3580 if (i.op[op].disps->X_op == O_constant)
252b5132 3581 {
b300c311 3582 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3583
40fb9820 3584 if (i.types[op].bitfield.disp16
b300c311
L		 3585 && (disp & ~(offsetT) 0xffff) == 0)
3586 {
3587 /* If this operand is at most 16 bits, convert
3588 to a signed 16 bit number and don't use 64bit
3589 displacement. */
3590 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3591 i.types[op].bitfield.disp64 = 0;
b300c311 3592 }
40fb9820 3593 if (i.types[op].bitfield.disp32
b300c311
L		 3594 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3595 {
3596 /* If this operand is at most 32 bits, convert
3597 to a signed 32 bit number and don't use 64bit
3598 displacement. */
3599 disp &= (((offsetT) 2 << 31) - 1);
3600 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3601 i.types[op].bitfield.disp64 = 0;
b300c311 3602 }
40fb9820 3603 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3604 {
40fb9820
L		 3605 i.types[op].bitfield.disp8 = 0;
3606 i.types[op].bitfield.disp16 = 0;
3607 i.types[op].bitfield.disp32 = 0;
3608 i.types[op].bitfield.disp32s = 0;
3609 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3610 i.op[op].disps = 0;
3611 i.disp_operands--;
3612 }
3613 else if (flag_code == CODE_64BIT)
3614 {
3615 if (fits_in_signed_long (disp))
28a9d8f5 3616 {
40fb9820
L		 3617 i.types[op].bitfield.disp64 = 0;
3618 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3619 }
b300c311 3620 if (fits_in_unsigned_long (disp))
40fb9820 3621 i.types[op].bitfield.disp32 = 1;
b300c311 3622 }
40fb9820
L		 3623 if ((i.types[op].bitfield.disp32
3624 || i.types[op].bitfield.disp32s
3625 || i.types[op].bitfield.disp16)
b300c311 3626 && fits_in_signed_byte (disp))
40fb9820 3627 i.types[op].bitfield.disp8 = 1;
252b5132 3628 }
67a4f2b7
AO		 3629 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3630 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3631 {
3632 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3633 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3634 i.types[op].bitfield.disp8 = 0;
3635 i.types[op].bitfield.disp16 = 0;
3636 i.types[op].bitfield.disp32 = 0;
3637 i.types[op].bitfield.disp32s = 0;
3638 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3639 }
3640 else
b300c311 3641 /* We only support 64bit displacement on constants. */
40fb9820 3642 i.types[op].bitfield.disp64 = 0;
252b5132 3643 }
29b0f896
AM		 3644}
3645
fa99fab2 3646static const template *
e3bb37b5 3647match_template (void)
29b0f896
AM		 3648{
3649 /* Points to template once we've found it. */
3650 const template *t;
40fb9820 3651 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3652 i386_operand_type overlap4;
29b0f896 3653 unsigned int found_reverse_match;
40fb9820
L		 3654 i386_opcode_modifier suffix_check;
3655 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3656 int addr_prefix_disp;
a5c311ca 3657 unsigned int j;
3629bb00 3658 unsigned int found_cpu_match;
45664ddb 3659 unsigned int check_register;
29b0f896 3660
c0f3af97
L		 3661#if MAX_OPERANDS != 5
3662# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3663#endif
3664
29b0f896 3665 found_reverse_match = 0;
539e75ad 3666 addr_prefix_disp = -1;
40fb9820
L		 3667
3668 memset (&suffix_check, 0, sizeof (suffix_check));
3669 if (i.suffix == BYTE_MNEM_SUFFIX)
3670 suffix_check.no_bsuf = 1;
3671 else if (i.suffix == WORD_MNEM_SUFFIX)
3672 suffix_check.no_wsuf = 1;
3673 else if (i.suffix == SHORT_MNEM_SUFFIX)
3674 suffix_check.no_ssuf = 1;
3675 else if (i.suffix == LONG_MNEM_SUFFIX)
3676 suffix_check.no_lsuf = 1;
3677 else if (i.suffix == QWORD_MNEM_SUFFIX)
3678 suffix_check.no_qsuf = 1;
3679 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3680 suffix_check.no_ldsuf = 1;
29b0f896 3681
45aa61fe 3682 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3683 {
539e75ad
L		 3684 addr_prefix_disp = -1;
3685
29b0f896
AM		 3686 /* Must have right number of operands. */
3687 if (i.operands != t->operands)
3688 continue;
3689
50aecf8c 3690 /* Check processor support. */
c0f3af97
L		 3691 found_cpu_match = (cpu_flags_match (t)
3692 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3693 if (!found_cpu_match)
3694 continue;
3695
e1d4d893
L		 3696 /* Check old gcc support. */
3697 if (!old_gcc && t->opcode_modifier.oldgcc)
3698 continue;
3699
3700 /* Check AT&T mnemonic. */
3701 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3702 continue;
3703
5c07affc
L		 3704 /* Check AT&T syntax Intel syntax. */
3705 if ((intel_syntax && t->opcode_modifier.attsyntax)
3706 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3707 continue;
3708
20592a94 3709 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3710 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3711 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3712 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3713 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3714 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3715 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3716 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3717 continue;
3718
5c07affc 3719 if (!operand_size_match (t))
7d5e4556 3720 continue;
539e75ad 3721
5c07affc
L		 3722 for (j = 0; j < MAX_OPERANDS; j++)
3723 operand_types[j] = t->operand_types[j];
3724
45aa61fe
AM		 3725 /* In general, don't allow 64-bit operands in 32-bit mode. */
3726 if (i.suffix == QWORD_MNEM_SUFFIX
3727 && flag_code != CODE_64BIT
3728 && (intel_syntax
40fb9820 3729 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3730 && !intel_float_operand (t->name))
3731 : intel_float_operand (t->name) != 2)
40fb9820 3732 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3733 && !operand_types[0].bitfield.regxmm
3734 && !operand_types[0].bitfield.regymm)
40fb9820 3735 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3736 && !!operand_types[t->operands > 1].bitfield.regxmm
3737 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3738 && (t->base_opcode != 0x0fc7
3739 || t->extension_opcode != 1 /* cmpxchg8b */))
3740 continue;
3741
192dc9c6
JB		 3742 /* In general, don't allow 32-bit operands on pre-386. */
3743 else if (i.suffix == LONG_MNEM_SUFFIX
3744 && !cpu_arch_flags.bitfield.cpui386
3745 && (intel_syntax
3746 ? (!t->opcode_modifier.ignoresize
3747 && !intel_float_operand (t->name))
3748 : intel_float_operand (t->name) != 2)
3749 && ((!operand_types[0].bitfield.regmmx
3750 && !operand_types[0].bitfield.regxmm)
3751 || (!operand_types[t->operands > 1].bitfield.regmmx
3752 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3753 continue;
3754
29b0f896 3755 /* Do not verify operands when there are none. */
50aecf8c 3756 else
29b0f896 3757 {
c6fb90c8 3758 if (!t->operands)
2dbab7d5
L		 3759 /* We've found a match; break out of loop. */
3760 break;
29b0f896 3761 }
252b5132 3762
539e75ad
L		 3763 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3764 into Disp32/Disp16/Disp32 operand. */
3765 if (i.prefix[ADDR_PREFIX] != 0)
3766 {
40fb9820 3767 /* There should be only one Disp operand. */
539e75ad
L		 3768 switch (flag_code)
3769 {
3770 case CODE_16BIT:
40fb9820
L		 3771 for (j = 0; j < MAX_OPERANDS; j++)
3772 {
3773 if (operand_types[j].bitfield.disp16)
3774 {
3775 addr_prefix_disp = j;
3776 operand_types[j].bitfield.disp32 = 1;
3777 operand_types[j].bitfield.disp16 = 0;
3778 break;
3779 }
3780 }
539e75ad
L		 3781 break;
3782 case CODE_32BIT:
40fb9820
L		 3783 for (j = 0; j < MAX_OPERANDS; j++)
3784 {
3785 if (operand_types[j].bitfield.disp32)
3786 {
3787 addr_prefix_disp = j;
3788 operand_types[j].bitfield.disp32 = 0;
3789 operand_types[j].bitfield.disp16 = 1;
3790 break;
3791 }
3792 }
539e75ad
L		 3793 break;
3794 case CODE_64BIT:
40fb9820
L		 3795 for (j = 0; j < MAX_OPERANDS; j++)
3796 {
3797 if (operand_types[j].bitfield.disp64)
3798 {
3799 addr_prefix_disp = j;
3800 operand_types[j].bitfield.disp64 = 0;
3801 operand_types[j].bitfield.disp32 = 1;
3802 break;
3803 }
3804 }
539e75ad
L		 3805 break;
3806 }
539e75ad
L		 3807 }
3808
45664ddb
L		 3809 /* We check register size only if size of operands can be
3810 encoded the canonical way. */
3811 check_register = t->opcode_modifier.w;
c6fb90c8 3812 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3813 switch (t->operands)
3814 {
3815 case 1:
40fb9820 3816 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3817 continue;
3818 break;
3819 case 2:
8b38ad71
L		 3820 /* xchg %eax, %eax is a special case. It is an aliase for nop
3821 only in 32bit mode and we can use opcode 0x90. In 64bit
3822 mode, we can't use 0x90 for xchg %eax, %eax since it should
3823 zero-extend %eax to %rax. */
3824 if (flag_code == CODE_64BIT
3825 && t->base_opcode == 0x90
0dfbf9d7
L		 3826 && operand_type_equal (&i.types [0], &acc32)
3827 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3828 continue;
b6169b20
L		 3829 if (i.swap_operand)
3830 {
3831 /* If we swap operand in encoding, we either match
3832 the next one or reverse direction of operands. */
3833 if (t->opcode_modifier.s)
3834 continue;
3835 else if (t->opcode_modifier.d)
3836 goto check_reverse;
3837 }
3838
29b0f896 3839 case 3:
fa99fab2
L		 3840 /* If we swap operand in encoding, we match the next one. */
3841 if (i.swap_operand && t->opcode_modifier.s)
3842 continue;
f48ff2ae 3843 case 4:
c0f3af97 3844 case 5:
c6fb90c8 3845 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3846 if (!operand_type_match (overlap0, i.types[0])
3847 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3848 || (check_register
3849 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3850 operand_types[0],
3851 overlap1, i.types[1],
3852 operand_types[1])))
29b0f896
AM		 3853 {
3854 /* Check if other direction is valid ... */
40fb9820 3855 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3856 continue;
3857
b6169b20 3858check_reverse:
29b0f896 3859 /* Try reversing direction of operands. */
c6fb90c8
L		 3860 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3861 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3862 if (!operand_type_match (overlap0, i.types[0])
3863 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3864 || (check_register
3865 && !operand_type_register_match (overlap0,
3866 i.types[0],
3867 operand_types[1],
3868 overlap1,
3869 i.types[1],
3870 operand_types[0])))
29b0f896
AM		 3871 {
3872 /* Does not match either direction. */
3873 continue;
3874 }
3875 /* found_reverse_match holds which of D or FloatDR
3876 we've found. */
40fb9820 3877 if (t->opcode_modifier.d)
8a2ed489 3878 found_reverse_match = Opcode_D;
40fb9820 3879 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3880 found_reverse_match = Opcode_FloatD;
3881 else
3882 found_reverse_match = 0;
40fb9820 3883 if (t->opcode_modifier.floatr)
8a2ed489 3884 found_reverse_match |= Opcode_FloatR;
29b0f896 3885 }
f48ff2ae 3886 else
29b0f896 3887 {
f48ff2ae 3888 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3889 switch (t->operands)
3890 {
c0f3af97
L		 3891 case 5:
3892 overlap4 = operand_type_and (i.types[4],
3893 operand_types[4]);
d1cbb4db 3894 case 4:
c6fb90c8
L		 3895 overlap3 = operand_type_and (i.types[3],
3896 operand_types[3]);
d1cbb4db 3897 case 3:
c6fb90c8
L		 3898 overlap2 = operand_type_and (i.types[2],
3899 operand_types[2]);
d1cbb4db
L		 3900 break;
3901 }
29b0f896 3902
f48ff2ae
L		 3903 switch (t->operands)
3904 {
c0f3af97
L		 3905 case 5:
3906 if (!operand_type_match (overlap4, i.types[4])
3907 || !operand_type_register_match (overlap3,
3908 i.types[3],
3909 operand_types[3],
3910 overlap4,
3911 i.types[4],
3912 operand_types[4]))
3913 continue;
f48ff2ae 3914 case 4:
40fb9820 3915 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3916 || (check_register
3917 && !operand_type_register_match (overlap2,
3918 i.types[2],
3919 operand_types[2],
3920 overlap3,
3921 i.types[3],
3922 operand_types[3])))
f48ff2ae
L		 3923 continue;
3924 case 3:
3925 /* Here we make use of the fact that there are no
3926 reverse match 3 operand instructions, and all 3
3927 operand instructions only need to be checked for
3928 register consistency between operands 2 and 3. */
40fb9820 3929 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3930 || (check_register
3931 && !operand_type_register_match (overlap1,
3932 i.types[1],
3933 operand_types[1],
3934 overlap2,
3935 i.types[2],
3936 operand_types[2])))
f48ff2ae
L		 3937 continue;
3938 break;
3939 }
29b0f896 3940 }
f48ff2ae 3941 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3942 slip through to break. */
3943 }
3629bb00 3944 if (!found_cpu_match)
29b0f896
AM		 3945 {
3946 found_reverse_match = 0;
3947 continue;
3948 }
c0f3af97 3949
29b0f896
AM		 3950 /* We've found a match; break out of loop. */
3951 break;
3952 }
3953
3954 if (t == current_templates->end)
3955 {
3956 /* We found no match. */
95f283e8
L		 3957 if (intel_syntax)
3958 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3959 current_templates->start->name);
3960 else
3961 as_bad (_("suffix or operands invalid for `%s'"),
3962 current_templates->start->name);
fa99fab2 3963 return NULL;
29b0f896 3964 }
252b5132 3965
29b0f896
AM		 3966 if (!quiet_warnings)
3967 {
3968 if (!intel_syntax
40fb9820
L		 3969 && (i.types[0].bitfield.jumpabsolute
3970 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3971 {
3972 as_warn (_("indirect %s without `*'"), t->name);
3973 }
3974
40fb9820
L		 3975 if (t->opcode_modifier.isprefix
3976 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3977 {
3978 /* Warn them that a data or address size prefix doesn't
3979 affect assembly of the next line of code. */
3980 as_warn (_("stand-alone `%s' prefix"), t->name);
3981 }
3982 }
3983
3984 /* Copy the template we found. */
3985 i.tm = *t;
539e75ad
L		 3986
3987 if (addr_prefix_disp != -1)
3988 i.tm.operand_types[addr_prefix_disp]
3989 = operand_types[addr_prefix_disp];
3990
29b0f896
AM		 3991 if (found_reverse_match)
3992 {
3993 /* If we found a reverse match we must alter the opcode
3994 direction bit. found_reverse_match holds bits to change
3995 (different for int & float insns). */
3996
3997 i.tm.base_opcode ^= found_reverse_match;
3998
539e75ad
L		 3999 i.tm.operand_types[0] = operand_types[1];
4000 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4001 }
4002
fa99fab2 4003 return t;
29b0f896
AM		 4004}
4005
4006static int
e3bb37b5 4007check_string (void)
29b0f896 4008{
40fb9820
L		 4009 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4010 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4011 {
4012 if (i.seg[0] != NULL && i.seg[0] != &es)
4013 {
a87af027 4014 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4015 i.tm.name,
a87af027
JB		 4016 mem_op + 1,
4017 register_prefix);
29b0f896
AM		 4018 return 0;
4019 }
4020 /* There's only ever one segment override allowed per instruction.
4021 This instruction possibly has a legal segment override on the
4022 second operand, so copy the segment to where non-string
4023 instructions store it, allowing common code. */
4024 i.seg[0] = i.seg[1];
4025 }
40fb9820 4026 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4027 {
4028 if (i.seg[1] != NULL && i.seg[1] != &es)
4029 {
a87af027 4030 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4031 i.tm.name,
a87af027
JB		 4032 mem_op + 2,
4033 register_prefix);
29b0f896
AM		 4034 return 0;
4035 }
4036 }
4037 return 1;
4038}
4039
4040static int
543613e9 4041process_suffix (void)
29b0f896
AM		 4042{
4043 /* If matched instruction specifies an explicit instruction mnemonic
4044 suffix, use it. */
40fb9820
L		 4045 if (i.tm.opcode_modifier.size16)
4046 i.suffix = WORD_MNEM_SUFFIX;
4047 else if (i.tm.opcode_modifier.size32)
4048 i.suffix = LONG_MNEM_SUFFIX;
4049 else if (i.tm.opcode_modifier.size64)
4050 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4051 else if (i.reg_operands)
4052 {
4053 /* If there's no instruction mnemonic suffix we try to invent one
4054 based on register operands. */
4055 if (!i.suffix)
4056 {
4057 /* We take i.suffix from the last register operand specified,
4058 Destination register type is more significant than source
381d071f
L		 4059 register type. crc32 in SSE4.2 prefers source register
4060 type. */
4061 if (i.tm.base_opcode == 0xf20f38f1)
4062 {
40fb9820
L		 4063 if (i.types[0].bitfield.reg16)
4064 i.suffix = WORD_MNEM_SUFFIX;
4065 else if (i.types[0].bitfield.reg32)
4066 i.suffix = LONG_MNEM_SUFFIX;
4067 else if (i.types[0].bitfield.reg64)
4068 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4069 }
9344ff29 4070 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4071 {
40fb9820 4072 if (i.types[0].bitfield.reg8)
20592a94
L		 4073 i.suffix = BYTE_MNEM_SUFFIX;
4074 }
381d071f
L		 4075
4076 if (!i.suffix)
4077 {
4078 int op;
4079
20592a94
L		 4080 if (i.tm.base_opcode == 0xf20f38f1
4081 || i.tm.base_opcode == 0xf20f38f0)
4082 {
4083 /* We have to know the operand size for crc32. */
4084 as_bad (_("ambiguous memory operand size for `%s`"),
4085 i.tm.name);
4086 return 0;
4087 }
4088
381d071f 4089 for (op = i.operands; --op >= 0;)
40fb9820 4090 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4091 {
40fb9820
L		 4092 if (i.types[op].bitfield.reg8)
4093 {
4094 i.suffix = BYTE_MNEM_SUFFIX;
4095 break;
4096 }
4097 else if (i.types[op].bitfield.reg16)
4098 {
4099 i.suffix = WORD_MNEM_SUFFIX;
4100 break;
4101 }
4102 else if (i.types[op].bitfield.reg32)
4103 {
4104 i.suffix = LONG_MNEM_SUFFIX;
4105 break;
4106 }
4107 else if (i.types[op].bitfield.reg64)
4108 {
4109 i.suffix = QWORD_MNEM_SUFFIX;
4110 break;
4111 }
381d071f
L		 4112 }
4113 }
29b0f896
AM		 4114 }
4115 else if (i.suffix == BYTE_MNEM_SUFFIX)
4116 {
4117 if (!check_byte_reg ())
4118 return 0;
4119 }
4120 else if (i.suffix == LONG_MNEM_SUFFIX)
4121 {
4122 if (!check_long_reg ())
4123 return 0;
4124 }
4125 else if (i.suffix == QWORD_MNEM_SUFFIX)
4126 {
955e1e6a
L		 4127 if (intel_syntax
4128 && i.tm.opcode_modifier.ignoresize
4129 && i.tm.opcode_modifier.no_qsuf)
4130 i.suffix = 0;
4131 else if (!check_qword_reg ())
29b0f896
AM		 4132 return 0;
4133 }
4134 else if (i.suffix == WORD_MNEM_SUFFIX)
4135 {
4136 if (!check_word_reg ())
4137 return 0;
4138 }
c0f3af97
L		 4139 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4140 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4141 {
c0f3af97 4142 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4143 should check if it is a valid suffix. */
4144 }
40fb9820 4145 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4146 /* Do nothing if the instruction is going to ignore the prefix. */
4147 ;
4148 else
4149 abort ();
4150 }
40fb9820 4151 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4152 && !i.suffix
4153 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4154 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4155 {
4156 i.suffix = stackop_size;
4157 }
9306ca4a
JB		 4158 else if (intel_syntax
4159 && !i.suffix
40fb9820
L		 4160 && (i.tm.operand_types[0].bitfield.jumpabsolute
4161 || i.tm.opcode_modifier.jumpbyte
4162 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4163 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4164 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4165 {
4166 switch (flag_code)
4167 {
4168 case CODE_64BIT:
40fb9820 4169 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4170 {
4171 i.suffix = QWORD_MNEM_SUFFIX;
4172 break;
4173 }
4174 case CODE_32BIT:
40fb9820 4175 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4176 i.suffix = LONG_MNEM_SUFFIX;
4177 break;
4178 case CODE_16BIT:
40fb9820 4179 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4180 i.suffix = WORD_MNEM_SUFFIX;
4181 break;
4182 }
4183 }
252b5132 4184
9306ca4a 4185 if (!i.suffix)
29b0f896 4186 {
9306ca4a
JB		 4187 if (!intel_syntax)
4188 {
40fb9820 4189 if (i.tm.opcode_modifier.w)
9306ca4a 4190 {
4eed87de
AM		 4191 as_bad (_("no instruction mnemonic suffix given and "
4192 "no register operands; can't size instruction"));
9306ca4a
JB		 4193 return 0;
4194 }
4195 }
4196 else
4197 {
40fb9820 4198 unsigned int suffixes;
7ab9ffdd 4199
40fb9820
L		 4200 suffixes = !i.tm.opcode_modifier.no_bsuf;
4201 if (!i.tm.opcode_modifier.no_wsuf)
4202 suffixes |= 1 << 1;
4203 if (!i.tm.opcode_modifier.no_lsuf)
4204 suffixes |= 1 << 2;
fc4adea1 4205 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4206 suffixes |= 1 << 3;
4207 if (!i.tm.opcode_modifier.no_ssuf)
4208 suffixes |= 1 << 4;
4209 if (!i.tm.opcode_modifier.no_qsuf)
4210 suffixes |= 1 << 5;
4211
4212 /* There are more than suffix matches. */
4213 if (i.tm.opcode_modifier.w
9306ca4a 4214 || ((suffixes & (suffixes - 1))
40fb9820
L		 4215 && !i.tm.opcode_modifier.defaultsize
4216 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4217 {
4218 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4219 return 0;
4220 }
4221 }
29b0f896 4222 }
252b5132 4223
9306ca4a
JB		 4224 /* Change the opcode based on the operand size given by i.suffix;
4225 We don't need to change things for byte insns. */
4226
582d5edd
L		 4227 if (i.suffix
4228 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4229 && i.suffix != XMMWORD_MNEM_SUFFIX
4230 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4231 {
4232 /* It's not a byte, select word/dword operation. */
40fb9820 4233 if (i.tm.opcode_modifier.w)
29b0f896 4234 {
40fb9820 4235 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4236 i.tm.base_opcode |= 8;
4237 else
4238 i.tm.base_opcode |= 1;
4239 }
0f3f3d8b 4240
29b0f896
AM		 4241 /* Now select between word & dword operations via the operand
4242 size prefix, except for instructions that will ignore this
4243 prefix anyway. */
ca61edf2 4244 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4245 {
ca61edf2
L		 4246 /* The address size override prefix changes the size of the
4247 first operand. */
40fb9820
L		 4248 if ((flag_code == CODE_32BIT
4249 && i.op->regs[0].reg_type.bitfield.reg16)
4250 || (flag_code != CODE_32BIT
4251 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4252 if (!add_prefix (ADDR_PREFIX_OPCODE))
4253 return 0;
4254 }
4255 else if (i.suffix != QWORD_MNEM_SUFFIX
4256 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4257 && !i.tm.opcode_modifier.ignoresize
4258 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4259 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4260 || (flag_code == CODE_64BIT
40fb9820 4261 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4262 {
4263 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4264
40fb9820 4265 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4266 prefix = ADDR_PREFIX_OPCODE;
252b5132 4267
29b0f896
AM		 4268 if (!add_prefix (prefix))
4269 return 0;
24eab124 4270 }
252b5132 4271
29b0f896
AM		 4272 /* Set mode64 for an operand. */
4273 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4274 && flag_code == CODE_64BIT
40fb9820 4275 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4276 {
4277 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4278 need rex64. cmpxchg8b is also a special case. */
4279 if (! (i.operands == 2
4280 && i.tm.base_opcode == 0x90
4281 && i.tm.extension_opcode == None
0dfbf9d7
L		 4282 && operand_type_equal (&i.types [0], &acc64)
4283 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4284 && ! (i.operands == 1
4285 && i.tm.base_opcode == 0xfc7
4286 && i.tm.extension_opcode == 1
40fb9820
L		 4287 && !operand_type_check (i.types [0], reg)
4288 && operand_type_check (i.types [0], anymem)))
f6bee062 4289 i.rex |= REX_W;
46e883c5 4290 }
3e73aa7c 4291
29b0f896
AM		 4292 /* Size floating point instruction. */
4293 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4294 if (i.tm.opcode_modifier.floatmf)
543613e9 4295 i.tm.base_opcode ^= 4;
29b0f896 4296 }
7ecd2f8b 4297
29b0f896
AM		 4298 return 1;
4299}
3e73aa7c 4300
29b0f896 4301static int
543613e9 4302check_byte_reg (void)
29b0f896
AM		 4303{
4304 int op;
543613e9 4305
29b0f896
AM		 4306 for (op = i.operands; --op >= 0;)
4307 {
4308 /* If this is an eight bit register, it's OK. If it's the 16 or
4309 32 bit version of an eight bit register, we will just use the
4310 low portion, and that's OK too. */
40fb9820 4311 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4312 continue;
4313
ca61edf2
L		 4314 /* Don't generate this warning if not needed. */
4315 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4316 continue;
4317
9344ff29
L		 4318 /* crc32 doesn't generate this warning. */
4319 if (i.tm.base_opcode == 0xf20f38f0)
4320 continue;
4321
40fb9820
L		 4322 if ((i.types[op].bitfield.reg16
4323 || i.types[op].bitfield.reg32
4324 || i.types[op].bitfield.reg64)
4325 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4326 {
4327 /* Prohibit these changes in the 64bit mode, since the
4328 lowering is more complicated. */
4329 if (flag_code == CODE_64BIT
40fb9820 4330 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4331 {
2ca3ace5
L		 4332 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4333 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4334 i.suffix);
4335 return 0;
4336 }
4337#if REGISTER_WARNINGS
4338 if (!quiet_warnings
40fb9820 4339 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4340 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4341 register_prefix,
40fb9820 4342 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4343 ? REGNAM_AL - REGNAM_AX
4344 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4345 register_prefix,
29b0f896
AM		 4346 i.op[op].regs->reg_name,
4347 i.suffix);
4348#endif
4349 continue;
4350 }
4351 /* Any other register is bad. */
40fb9820
L		 4352 if (i.types[op].bitfield.reg16
4353 || i.types[op].bitfield.reg32
4354 || i.types[op].bitfield.reg64
4355 || i.types[op].bitfield.regmmx
4356 || i.types[op].bitfield.regxmm
c0f3af97 4357 || i.types[op].bitfield.regymm
40fb9820
L		 4358 || i.types[op].bitfield.sreg2
4359 || i.types[op].bitfield.sreg3
4360 || i.types[op].bitfield.control
4361 || i.types[op].bitfield.debug
4362 || i.types[op].bitfield.test
4363 || i.types[op].bitfield.floatreg
4364 || i.types[op].bitfield.floatacc)
29b0f896 4365 {
a540244d
L		 4366 as_bad (_("`%s%s' not allowed with `%s%c'"),
4367 register_prefix,
29b0f896
AM		 4368 i.op[op].regs->reg_name,
4369 i.tm.name,
4370 i.suffix);
4371 return 0;
4372 }
4373 }
4374 return 1;
4375}
4376
4377static int
e3bb37b5 4378check_long_reg (void)
29b0f896
AM		 4379{
4380 int op;
4381
4382 for (op = i.operands; --op >= 0;)
4383 /* Reject eight bit registers, except where the template requires
4384 them. (eg. movzb) */
40fb9820
L		 4385 if (i.types[op].bitfield.reg8
4386 && (i.tm.operand_types[op].bitfield.reg16
4387 || i.tm.operand_types[op].bitfield.reg32
4388 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4389 {
a540244d
L		 4390 as_bad (_("`%s%s' not allowed with `%s%c'"),
4391 register_prefix,
29b0f896
AM		 4392 i.op[op].regs->reg_name,
4393 i.tm.name,
4394 i.suffix);
4395 return 0;
4396 }
4397 /* Warn if the e prefix on a general reg is missing. */
4398 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4399 && i.types[op].bitfield.reg16
4400 && (i.tm.operand_types[op].bitfield.reg32
4401 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4402 {
4403 /* Prohibit these changes in the 64bit mode, since the
4404 lowering is more complicated. */
4405 if (flag_code == CODE_64BIT)
252b5132 4406 {
2ca3ace5
L		 4407 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4408 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4409 i.suffix);
4410 return 0;
252b5132 4411 }
29b0f896
AM		 4412#if REGISTER_WARNINGS
4413 else
a540244d
L		 4414 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4415 register_prefix,
29b0f896 4416 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4417 register_prefix,
29b0f896
AM		 4418 i.op[op].regs->reg_name,
4419 i.suffix);
4420#endif
252b5132 4421 }
29b0f896 4422 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4423 else if (i.types[op].bitfield.reg64
4424 && (i.tm.operand_types[op].bitfield.reg32
4425 || i.tm.operand_types[op].bitfield.acc))
252b5132 4426 {
34828aad 4427 if (intel_syntax
ca61edf2 4428 && i.tm.opcode_modifier.toqword
40fb9820 4429 && !i.types[0].bitfield.regxmm)
34828aad 4430 {
ca61edf2 4431 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4432 i.suffix = QWORD_MNEM_SUFFIX;
4433 }
4434 else
4435 {
4436 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4437 register_prefix, i.op[op].regs->reg_name,
4438 i.suffix);
4439 return 0;
4440 }
29b0f896
AM		 4441 }
4442 return 1;
4443}
252b5132 4444
29b0f896 4445static int
e3bb37b5 4446check_qword_reg (void)
29b0f896
AM		 4447{
4448 int op;
252b5132 4449
29b0f896
AM		 4450 for (op = i.operands; --op >= 0; )
4451 /* Reject eight bit registers, except where the template requires
4452 them. (eg. movzb) */
40fb9820
L		 4453 if (i.types[op].bitfield.reg8
4454 && (i.tm.operand_types[op].bitfield.reg16
4455 || i.tm.operand_types[op].bitfield.reg32
4456 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4457 {
a540244d
L		 4458 as_bad (_("`%s%s' not allowed with `%s%c'"),
4459 register_prefix,
29b0f896
AM		 4460 i.op[op].regs->reg_name,
4461 i.tm.name,
4462 i.suffix);
4463 return 0;
4464 }
4465 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4466 else if ((i.types[op].bitfield.reg16
4467 || i.types[op].bitfield.reg32)
4468 && (i.tm.operand_types[op].bitfield.reg32
4469 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4470 {
4471 /* Prohibit these changes in the 64bit mode, since the
4472 lowering is more complicated. */
34828aad 4473 if (intel_syntax
ca61edf2 4474 && i.tm.opcode_modifier.todword
40fb9820 4475 && !i.types[0].bitfield.regxmm)
34828aad 4476 {
ca61edf2 4477 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4478 i.suffix = LONG_MNEM_SUFFIX;
4479 }
4480 else
4481 {
4482 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4483 register_prefix, i.op[op].regs->reg_name,
4484 i.suffix);
4485 return 0;
4486 }
252b5132 4487 }
29b0f896
AM		 4488 return 1;
4489}
252b5132 4490
29b0f896 4491static int
e3bb37b5 4492check_word_reg (void)
29b0f896
AM		 4493{
4494 int op;
4495 for (op = i.operands; --op >= 0;)
4496 /* Reject eight bit registers, except where the template requires
4497 them. (eg. movzb) */
40fb9820
L		 4498 if (i.types[op].bitfield.reg8
4499 && (i.tm.operand_types[op].bitfield.reg16
4500 || i.tm.operand_types[op].bitfield.reg32
4501 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4502 {
a540244d
L		 4503 as_bad (_("`%s%s' not allowed with `%s%c'"),
4504 register_prefix,
29b0f896
AM		 4505 i.op[op].regs->reg_name,
4506 i.tm.name,
4507 i.suffix);
4508 return 0;
4509 }
4510 /* Warn if the e prefix on a general reg is present. */
4511 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4512 && i.types[op].bitfield.reg32
4513 && (i.tm.operand_types[op].bitfield.reg16
4514 || i.tm.operand_types[op].bitfield.acc))
252b5132 4515 {
29b0f896
AM		 4516 /* Prohibit these changes in the 64bit mode, since the
4517 lowering is more complicated. */
4518 if (flag_code == CODE_64BIT)
252b5132 4519 {
2ca3ace5
L		 4520 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4521 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4522 i.suffix);
4523 return 0;
252b5132 4524 }
29b0f896
AM		 4525 else
4526#if REGISTER_WARNINGS
a540244d
L		 4527 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4528 register_prefix,
29b0f896 4529 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4530 register_prefix,
29b0f896
AM		 4531 i.op[op].regs->reg_name,
4532 i.suffix);
4533#endif
4534 }
4535 return 1;
4536}
252b5132 4537
29b0f896 4538static int
40fb9820 4539update_imm (unsigned int j)
29b0f896 4540{
bc0844ae 4541 i386_operand_type overlap = i.types[j];
40fb9820
L		 4542 if ((overlap.bitfield.imm8
4543 || overlap.bitfield.imm8s
4544 || overlap.bitfield.imm16
4545 || overlap.bitfield.imm32
4546 || overlap.bitfield.imm32s
4547 || overlap.bitfield.imm64)
0dfbf9d7
L		 4548 && !operand_type_equal (&overlap, &imm8)
4549 && !operand_type_equal (&overlap, &imm8s)
4550 && !operand_type_equal (&overlap, &imm16)
4551 && !operand_type_equal (&overlap, &imm32)
4552 && !operand_type_equal (&overlap, &imm32s)
4553 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4554 {
4555 if (i.suffix)
4556 {
40fb9820
L		 4557 i386_operand_type temp;
4558
0dfbf9d7 4559 operand_type_set (&temp, 0);
7ab9ffdd 4560 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4561 {
4562 temp.bitfield.imm8 = overlap.bitfield.imm8;
4563 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4564 }
4565 else if (i.suffix == WORD_MNEM_SUFFIX)
4566 temp.bitfield.imm16 = overlap.bitfield.imm16;
4567 else if (i.suffix == QWORD_MNEM_SUFFIX)
4568 {
4569 temp.bitfield.imm64 = overlap.bitfield.imm64;
4570 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4571 }
4572 else
4573 temp.bitfield.imm32 = overlap.bitfield.imm32;
4574 overlap = temp;
29b0f896 4575 }
0dfbf9d7
L		 4576 else if (operand_type_equal (&overlap, &imm16_32_32s)
4577 || operand_type_equal (&overlap, &imm16_32)
4578 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4579 {
40fb9820 4580 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4581 overlap = imm16;
40fb9820 4582 else
65da13b5 4583 overlap = imm32s;
29b0f896 4584 }
0dfbf9d7
L		 4585 if (!operand_type_equal (&overlap, &imm8)
4586 && !operand_type_equal (&overlap, &imm8s)
4587 && !operand_type_equal (&overlap, &imm16)
4588 && !operand_type_equal (&overlap, &imm32)
4589 && !operand_type_equal (&overlap, &imm32s)
4590 && !operand_type_equal (&overlap, &imm64))
29b0f896 4591 {
4eed87de
AM		 4592 as_bad (_("no instruction mnemonic suffix given; "
4593 "can't determine immediate size"));
29b0f896
AM		 4594 return 0;
4595 }
4596 }
40fb9820 4597 i.types[j] = overlap;
29b0f896 4598
40fb9820
L		 4599 return 1;
4600}
4601
4602static int
4603finalize_imm (void)
4604{
bc0844ae 4605 unsigned int j, n;
29b0f896 4606
bc0844ae
L		 4607 /* Update the first 2 immediate operands. */
4608 n = i.operands > 2 ? 2 : i.operands;
4609 if (n)
4610 {
4611 for (j = 0; j < n; j++)
4612 if (update_imm (j) == 0)
4613 return 0;
40fb9820 4614
bc0844ae
L		 4615 /* The 3rd operand can't be immediate operand. */
4616 gas_assert (operand_type_check (i.types[2], imm) == 0);
4617 }
29b0f896
AM		 4618
4619 return 1;
4620}
4621
c0f3af97
L		 4622static int
4623bad_implicit_operand (int xmm)
4624{
4625 const char *reg = xmm ? "xmm0" : "ymm0";
4626 if (intel_syntax)
4627 as_bad (_("the last operand of `%s' must be `%s%s'"),
4628 i.tm.name, register_prefix, reg);
4629 else
4630 as_bad (_("the first operand of `%s' must be `%s%s'"),
4631 i.tm.name, register_prefix, reg);
4632 return 0;
4633}
4634
29b0f896 4635static int
e3bb37b5 4636process_operands (void)
29b0f896
AM		 4637{
4638 /* Default segment register this instruction will use for memory
4639 accesses. 0 means unknown. This is only for optimizing out
4640 unnecessary segment overrides. */
4641 const seg_entry *default_seg = 0;
4642
c0f3af97
L		 4643 if (i.tm.opcode_modifier.sse2avx
4644 && (i.tm.opcode_modifier.vexnds
4645 || i.tm.opcode_modifier.vexndd))
29b0f896 4646 {
c0f3af97
L		 4647 unsigned int dup = i.operands;
4648 unsigned int dest = dup - 1;
9fcfb3d7
L		 4649 unsigned int j;
4650
c0f3af97 4651 /* The destination must be an xmm register. */
9c2799c2 4652 gas_assert (i.reg_operands
7ab9ffdd
L		 4653 && MAX_OPERANDS > dup
4654 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4655
4656 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4657 {
c0f3af97 4658 /* The first operand is implicit and must be xmm0. */
9c2799c2 4659 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4660 if (i.op[0].regs->reg_num != 0)
4661 return bad_implicit_operand (1);
4662
4663 if (i.tm.opcode_modifier.vex3sources)
4664 {
4665 /* Keep xmm0 for instructions with VEX prefix and 3
4666 sources. */
4667 goto duplicate;
4668 }
e2ec9d29 4669 else
c0f3af97
L		 4670 {
4671 /* We remove the first xmm0 and keep the number of
4672 operands unchanged, which in fact duplicates the
4673 destination. */
4674 for (j = 1; j < i.operands; j++)
4675 {
4676 i.op[j - 1] = i.op[j];
4677 i.types[j - 1] = i.types[j];
4678 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4679 }
4680 }
4681 }
4682 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4683 {
9c2799c2 4684 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4685 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4686
4687 /* Add the implicit xmm0 for instructions with VEX prefix
4688 and 3 sources. */
4689 for (j = i.operands; j > 0; j--)
4690 {
4691 i.op[j] = i.op[j - 1];
4692 i.types[j] = i.types[j - 1];
4693 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4694 }
4695 i.op[0].regs
4696 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4697 i.types[0] = regxmm;
c0f3af97
L		 4698 i.tm.operand_types[0] = regxmm;
4699
4700 i.operands += 2;
4701 i.reg_operands += 2;
4702 i.tm.operands += 2;
4703
4704 dup++;
4705 dest++;
4706 i.op[dup] = i.op[dest];
4707 i.types[dup] = i.types[dest];
4708 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4709 }
c0f3af97
L		 4710 else
4711 {
4712duplicate:
4713 i.operands++;
4714 i.reg_operands++;
4715 i.tm.operands++;
4716
4717 i.op[dup] = i.op[dest];
4718 i.types[dup] = i.types[dest];
4719 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4720 }
4721
4722 if (i.tm.opcode_modifier.immext)
4723 process_immext ();
4724 }
4725 else if (i.tm.opcode_modifier.firstxmm0)
4726 {
4727 unsigned int j;
4728
4729 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4730 gas_assert (i.reg_operands
7ab9ffdd
L		 4731 && (operand_type_equal (&i.types[0], &regxmm)
4732 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4733 if (i.op[0].regs->reg_num != 0)
4734 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4735
4736 for (j = 1; j < i.operands; j++)
4737 {
4738 i.op[j - 1] = i.op[j];
4739 i.types[j - 1] = i.types[j];
4740
4741 /* We need to adjust fields in i.tm since they are used by
4742 build_modrm_byte. */
4743 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4744 }
4745
e2ec9d29
L		 4746 i.operands--;
4747 i.reg_operands--;
e2ec9d29
L		 4748 i.tm.operands--;
4749 }
4750 else if (i.tm.opcode_modifier.regkludge)
4751 {
4752 /* The imul $imm, %reg instruction is converted into
4753 imul $imm, %reg, %reg, and the clr %reg instruction
4754 is converted into xor %reg, %reg. */
4755
4756 unsigned int first_reg_op;
4757
4758 if (operand_type_check (i.types[0], reg))
4759 first_reg_op = 0;
4760 else
4761 first_reg_op = 1;
4762 /* Pretend we saw the extra register operand. */
9c2799c2 4763 gas_assert (i.reg_operands == 1
7ab9ffdd 4764 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4765 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4766 i.types[first_reg_op + 1] = i.types[first_reg_op];
4767 i.operands++;
4768 i.reg_operands++;
29b0f896
AM		 4769 }
4770
40fb9820 4771 if (i.tm.opcode_modifier.shortform)
29b0f896 4772 {
40fb9820
L		 4773 if (i.types[0].bitfield.sreg2
4774 || i.types[0].bitfield.sreg3)
29b0f896 4775 {
4eed87de
AM		 4776 if (i.tm.base_opcode == POP_SEG_SHORT
4777 && i.op[0].regs->reg_num == 1)
29b0f896 4778 {
a87af027 4779 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4780 return 0;
29b0f896 4781 }
4eed87de
AM		 4782 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4783 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4784 i.rex |= REX_B;
4eed87de
AM		 4785 }
4786 else
4787 {
7ab9ffdd 4788 /* The register or float register operand is in operand
85f10a01 4789 0 or 1. */
40fb9820 4790 unsigned int op;
7ab9ffdd
L		 4791
4792 if (i.types[0].bitfield.floatreg
4793 || operand_type_check (i.types[0], reg))
4794 op = 0;
4795 else
4796 op = 1;
4eed87de
AM		 4797 /* Register goes in low 3 bits of opcode. */
4798 i.tm.base_opcode |= i.op[op].regs->reg_num;
4799 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4800 i.rex |= REX_B;
40fb9820 4801 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4802 {
4eed87de
AM		 4803 /* Warn about some common errors, but press on regardless.
4804 The first case can be generated by gcc (<= 2.8.1). */
4805 if (i.operands == 2)
4806 {
4807 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4808 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4809 register_prefix, i.op[!intel_syntax].regs->reg_name,
4810 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4811 }
4812 else
4813 {
4814 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4815 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4816 register_prefix, i.op[0].regs->reg_name);
4eed87de 4817 }
29b0f896
AM		 4818 }
4819 }
4820 }
40fb9820 4821 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4822 {
4823 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4824 must be put into the modrm byte). Now, we make the modrm and
4825 index base bytes based on all the info we've collected. */
29b0f896
AM		 4826
4827 default_seg = build_modrm_byte ();
4828 }
8a2ed489 4829 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4830 {
4831 default_seg = &ds;
4832 }
40fb9820 4833 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4834 {
4835 /* For the string instructions that allow a segment override
4836 on one of their operands, the default segment is ds. */
4837 default_seg = &ds;
4838 }
4839
75178d9d
L		 4840 if (i.tm.base_opcode == 0x8d /* lea */
4841 && i.seg[0]
4842 && !quiet_warnings)
30123838 4843 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4844
4845 /* If a segment was explicitly specified, and the specified segment
4846 is not the default, use an opcode prefix to select it. If we
4847 never figured out what the default segment is, then default_seg
4848 will be zero at this point, and the specified segment prefix will
4849 always be used. */
29b0f896
AM		 4850 if ((i.seg[0]) && (i.seg[0] != default_seg))
4851 {
4852 if (!add_prefix (i.seg[0]->seg_prefix))
4853 return 0;
4854 }
4855 return 1;
4856}
4857
4858static const seg_entry *
e3bb37b5 4859build_modrm_byte (void)
29b0f896
AM		 4860{
4861 const seg_entry *default_seg = 0;
c0f3af97 4862 unsigned int source, dest;
7ab9ffdd 4863 int vex_3_sources;
c0f3af97
L		 4864
4865 /* The first operand of instructions with VEX prefix and 3 sources
4866 must be VEX_Imm4. */
4867 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4868 if (vex_3_sources)
4869 {
4870 unsigned int nds, reg;
4871
922d8de8
DR		 4872 if (i.tm.opcode_modifier.veximmext
4873 && i.tm.opcode_modifier.immext)
4874 {
4875 dest = i.operands - 2;
4876 gas_assert (dest == 3);
4877 }
4878 else
0bfee649 4879 dest = i.operands - 1;
c0f3af97 4880 nds = dest - 1;
922d8de8
DR		 4881
4882 /* This instruction must have 4 register operands
4883 or 3 register operands plus 1 memory operand.
4884 It must have VexNDS and VexImmExt. */
4885 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4886 || (i.reg_operands == 3 && i.mem_operands == 1))
4887 && i.tm.opcode_modifier.vexnds
4888 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4889 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4890 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4891
0bfee649
L		 4892 /* Generate an 8bit immediate operand to encode the register
4893 operand. */
4894 expressionS *exp = &im_expressions[i.imm_operands++];
4895 i.op[i.operands].imms = exp;
4896 i.types[i.operands] = imm8;
4897 i.operands++;
922d8de8
DR		 4898 /* If VexW1 is set, the first operand is the source and
4899 the second operand is encoded in the immediate operand. */
4900 if (i.tm.opcode_modifier.vexw1)
4901 {
4902 source = 0;
4903 reg = 1;
4904 }
4905 else
4906 {
4907 source = 1;
4908 reg = 0;
4909 }
4910 /* FMA4 swaps REG and NDS. */
4911 if (i.tm.cpu_flags.bitfield.cpufma4)
4912 {
4913 unsigned int tmp;
4914 tmp = reg;
4915 reg = nds;
4916 nds = tmp;
4917 }
4918 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4919 || operand_type_equal (&i.tm.operand_types[reg],
4920 &regymm))
4921 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
4922 || operand_type_equal (&i.tm.operand_types[nds],
4923 &regymm)));
0bfee649
L		 4924 exp->X_op = O_constant;
4925 exp->X_add_number
922d8de8
DR		 4926 = ((i.op[reg].regs->reg_num
4927 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4928 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4929 }
4930 else
4931 source = dest = 0;
29b0f896
AM		 4932
4933 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4934 implicit registers do not count. If there are 3 register
4935 operands, it must be a instruction with VexNDS. For a
4936 instruction with VexNDD, the destination register is encoded
4937 in VEX prefix. If there are 4 register operands, it must be
4938 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4939 if (i.mem_operands == 0
4940 && ((i.reg_operands == 2
4941 && !i.tm.opcode_modifier.vexndd)
4942 || (i.reg_operands == 3
4943 && i.tm.opcode_modifier.vexnds)
4944 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4945 {
cab737b9
L		 4946 switch (i.operands)
4947 {
4948 case 2:
4949 source = 0;
4950 break;
4951 case 3:
c81128dc
L		 4952 /* When there are 3 operands, one of them may be immediate,
4953 which may be the first or the last operand. Otherwise,
c0f3af97
L		 4954 the first operand must be shift count register (cl) or it
4955 is an instruction with VexNDS. */
9c2799c2 4956 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 4957 || (i.imm_operands == 0
4958 && (i.tm.opcode_modifier.vexnds
4959 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 4960 if (operand_type_check (i.types[0], imm)
4961 || i.types[0].bitfield.shiftcount)
4962 source = 1;
4963 else
4964 source = 0;
cab737b9
L		 4965 break;
4966 case 4:
368d64cc
L		 4967 /* When there are 4 operands, the first two must be 8bit
4968 immediate operands. The source operand will be the 3rd
c0f3af97
L		 4969 one.
4970
4971 For instructions with VexNDS, if the first operand
4972 an imm8, the source operand is the 2nd one. If the last
4973 operand is imm8, the source operand is the first one. */
9c2799c2 4974 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 4975 && i.types[0].bitfield.imm8
4976 && i.types[1].bitfield.imm8)
4977 || (i.tm.opcode_modifier.vexnds
4978 && i.imm_operands == 1
4979 && (i.types[0].bitfield.imm8
4980 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 4981 if (i.tm.opcode_modifier.vexnds)
4982 {
4983 if (i.types[0].bitfield.imm8)
4984 source = 1;
4985 else
4986 source = 0;
4987 }
4988 else
4989 source = 2;
4990 break;
4991 case 5:
cab737b9
L		 4992 break;
4993 default:
4994 abort ();
4995 }
4996
c0f3af97
L		 4997 if (!vex_3_sources)
4998 {
4999 dest = source + 1;
5000
5001 if (i.tm.opcode_modifier.vexnds)
5002 {
5003 /* For instructions with VexNDS, the register-only
5004 source operand must be XMM or YMM register. It is
fa99fab2
L		 5005 encoded in VEX prefix. We need to clear RegMem bit
5006 before calling operand_type_equal. */
5007 i386_operand_type op = i.tm.operand_types[dest];
5008 op.bitfield.regmem = 0;
c0f3af97 5009 if ((dest + 1) >= i.operands
fa99fab2
L		 5010 || (!operand_type_equal (&op, &regxmm)
5011 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5012 abort ();
5013 i.vex.register_specifier = i.op[dest].regs;
5014 dest++;
5015 }
5016 }
29b0f896
AM		 5017
5018 i.rm.mode = 3;
5019 /* One of the register operands will be encoded in the i.tm.reg
5020 field, the other in the combined i.tm.mode and i.tm.regmem
5021 fields. If no form of this instruction supports a memory
5022 destination operand, then we assume the source operand may
5023 sometimes be a memory operand and so we need to store the
5024 destination in the i.rm.reg field. */
40fb9820
L		 5025 if (!i.tm.operand_types[dest].bitfield.regmem
5026 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5027 {
5028 i.rm.reg = i.op[dest].regs->reg_num;
5029 i.rm.regmem = i.op[source].regs->reg_num;
5030 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5031 i.rex |= REX_R;
29b0f896 5032 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5033 i.rex |= REX_B;
29b0f896
AM		 5034 }
5035 else
5036 {
5037 i.rm.reg = i.op[source].regs->reg_num;
5038 i.rm.regmem = i.op[dest].regs->reg_num;
5039 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5040 i.rex |= REX_B;
29b0f896 5041 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5042 i.rex |= REX_R;
29b0f896 5043 }
161a04f6 5044 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5045 {
40fb9820
L		 5046 if (!i.types[0].bitfield.control
5047 && !i.types[1].bitfield.control)
c4a530c5 5048 abort ();
161a04f6 5049 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5050 add_prefix (LOCK_PREFIX_OPCODE);
5051 }
29b0f896
AM		 5052 }
5053 else
5054 { /* If it's not 2 reg operands... */
c0f3af97
L		 5055 unsigned int mem;
5056
29b0f896
AM		 5057 if (i.mem_operands)
5058 {
5059 unsigned int fake_zero_displacement = 0;
99018f42 5060 unsigned int op;
4eed87de 5061
7ab9ffdd
L		 5062 for (op = 0; op < i.operands; op++)
5063 if (operand_type_check (i.types[op], anymem))
5064 break;
7ab9ffdd 5065 gas_assert (op < i.operands);
29b0f896
AM		 5066
5067 default_seg = &ds;
5068
5069 if (i.base_reg == 0)
5070 {
5071 i.rm.mode = 0;
5072 if (!i.disp_operands)
5073 fake_zero_displacement = 1;
5074 if (i.index_reg == 0)
5075 {
5076 /* Operand is just <disp> */
20f0a1fc 5077 if (flag_code == CODE_64BIT)
29b0f896
AM		 5078 {
5079 /* 64bit mode overwrites the 32bit absolute
5080 addressing by RIP relative addressing and
5081 absolute addressing is encoded by one of the
5082 redundant SIB forms. */
5083 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5084 i.sib.base = NO_BASE_REGISTER;
5085 i.sib.index = NO_INDEX_REGISTER;
fc225355 5086 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5087 ? disp32s : disp32);
20f0a1fc 5088 }
fc225355
L		 5089 else if ((flag_code == CODE_16BIT)
5090 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5091 {
5092 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5093 i.types[op] = disp16;
20f0a1fc
NC		 5094 }
5095 else
5096 {
5097 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5098 i.types[op] = disp32;
29b0f896
AM		 5099 }
5100 }
5101 else /* !i.base_reg && i.index_reg */
5102 {
db51cc60
L		 5103 if (i.index_reg->reg_num == RegEiz
5104 || i.index_reg->reg_num == RegRiz)
5105 i.sib.index = NO_INDEX_REGISTER;
5106 else
5107 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5108 i.sib.base = NO_BASE_REGISTER;
5109 i.sib.scale = i.log2_scale_factor;
5110 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5111 i.types[op].bitfield.disp8 = 0;
5112 i.types[op].bitfield.disp16 = 0;
5113 i.types[op].bitfield.disp64 = 0;
29b0f896 5114 if (flag_code != CODE_64BIT)
40fb9820
L		 5115 {
5116 /* Must be 32 bit */
5117 i.types[op].bitfield.disp32 = 1;
5118 i.types[op].bitfield.disp32s = 0;
5119 }
29b0f896 5120 else
40fb9820
L		 5121 {
5122 i.types[op].bitfield.disp32 = 0;
5123 i.types[op].bitfield.disp32s = 1;
5124 }
29b0f896 5125 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5126 i.rex |= REX_X;
29b0f896
AM		 5127 }
5128 }
5129 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5130 else if (i.base_reg->reg_num == RegRip ||
5131 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5132 {
5133 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5134 i.types[op].bitfield.disp8 = 0;
5135 i.types[op].bitfield.disp16 = 0;
5136 i.types[op].bitfield.disp32 = 0;
5137 i.types[op].bitfield.disp32s = 1;
5138 i.types[op].bitfield.disp64 = 0;
71903a11 5139 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5140 if (! i.disp_operands)
5141 fake_zero_displacement = 1;
29b0f896 5142 }
40fb9820 5143 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5144 {
5145 switch (i.base_reg->reg_num)
5146 {
5147 case 3: /* (%bx) */
5148 if (i.index_reg == 0)
5149 i.rm.regmem = 7;
5150 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5151 i.rm.regmem = i.index_reg->reg_num - 6;
5152 break;
5153 case 5: /* (%bp) */
5154 default_seg = &ss;
5155 if (i.index_reg == 0)
5156 {
5157 i.rm.regmem = 6;
40fb9820 5158 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5159 {
5160 /* fake (%bp) into 0(%bp) */
40fb9820 5161 i.types[op].bitfield.disp8 = 1;
252b5132 5162 fake_zero_displacement = 1;
29b0f896
AM		 5163 }
5164 }
5165 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5166 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5167 break;
5168 default: /* (%si) -> 4 or (%di) -> 5 */
5169 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5170 }
5171 i.rm.mode = mode_from_disp_size (i.types[op]);
5172 }
5173 else /* i.base_reg and 32/64 bit mode */
5174 {
5175 if (flag_code == CODE_64BIT
40fb9820
L		 5176 && operand_type_check (i.types[op], disp))
5177 {
5178 i386_operand_type temp;
0dfbf9d7 5179 operand_type_set (&temp, 0);
40fb9820
L		 5180 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5181 i.types[op] = temp;
5182 if (i.prefix[ADDR_PREFIX] == 0)
5183 i.types[op].bitfield.disp32s = 1;
5184 else
5185 i.types[op].bitfield.disp32 = 1;
5186 }
20f0a1fc 5187
29b0f896
AM		 5188 i.rm.regmem = i.base_reg->reg_num;
5189 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5190 i.rex |= REX_B;
29b0f896
AM		 5191 i.sib.base = i.base_reg->reg_num;
5192 /* x86-64 ignores REX prefix bit here to avoid decoder
5193 complications. */
5194 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5195 {
5196 default_seg = &ss;
5197 if (i.disp_operands == 0)
5198 {
5199 fake_zero_displacement = 1;
40fb9820 5200 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5201 }
5202 }
5203 else if (i.base_reg->reg_num == ESP_REG_NUM)
5204 {
5205 default_seg = &ss;
5206 }
5207 i.sib.scale = i.log2_scale_factor;
5208 if (i.index_reg == 0)
5209 {
5210 /* <disp>(%esp) becomes two byte modrm with no index
5211 register. We've already stored the code for esp
5212 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5213 Any base register besides %esp will not use the
5214 extra modrm byte. */
5215 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5216 }
5217 else
5218 {
db51cc60
L		 5219 if (i.index_reg->reg_num == RegEiz
5220 || i.index_reg->reg_num == RegRiz)
5221 i.sib.index = NO_INDEX_REGISTER;
5222 else
5223 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5224 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5225 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5226 i.rex |= REX_X;
29b0f896 5227 }
67a4f2b7
AO		 5228
5229 if (i.disp_operands
5230 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5231 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5232 i.rm.mode = 0;
5233 else
5234 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5235 }
252b5132 5236
29b0f896
AM		 5237 if (fake_zero_displacement)
5238 {
5239 /* Fakes a zero displacement assuming that i.types[op]
5240 holds the correct displacement size. */
5241 expressionS *exp;
5242
9c2799c2 5243 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5244 exp = &disp_expressions[i.disp_operands++];
5245 i.op[op].disps = exp;
5246 exp->X_op = O_constant;
5247 exp->X_add_number = 0;
5248 exp->X_add_symbol = (symbolS *) 0;
5249 exp->X_op_symbol = (symbolS *) 0;
5250 }
c0f3af97
L		 5251
5252 mem = op;
29b0f896 5253 }
c0f3af97
L		 5254 else
5255 mem = ~0;
252b5132 5256
29b0f896
AM		 5257 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5258 (if any) based on i.tm.extension_opcode. Again, we must be
5259 careful to make sure that segment/control/debug/test/MMX
5260 registers are coded into the i.rm.reg field. */
5261 if (i.reg_operands)
5262 {
99018f42 5263 unsigned int op;
7ab9ffdd
L		 5264 unsigned int vex_reg = ~0;
5265
5266 for (op = 0; op < i.operands; op++)
5267 if (i.types[op].bitfield.reg8
5268 || i.types[op].bitfield.reg16
5269 || i.types[op].bitfield.reg32
5270 || i.types[op].bitfield.reg64
5271 || i.types[op].bitfield.regmmx
5272 || i.types[op].bitfield.regxmm
5273 || i.types[op].bitfield.regymm
5274 || i.types[op].bitfield.sreg2
5275 || i.types[op].bitfield.sreg3
5276 || i.types[op].bitfield.control
5277 || i.types[op].bitfield.debug
5278 || i.types[op].bitfield.test)
5279 break;
c0209578 5280
7ab9ffdd
L		 5281 if (vex_3_sources)
5282 op = dest;
5283 else if (i.tm.opcode_modifier.vexnds)
5284 {
5285 /* For instructions with VexNDS, the register-only
5286 source operand is encoded in VEX prefix. */
5287 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5288
7ab9ffdd 5289 if (op > mem)
c0f3af97 5290 {
7ab9ffdd
L		 5291 vex_reg = op++;
5292 gas_assert (op < i.operands);
c0f3af97
L		 5293 }
5294 else
c0f3af97 5295 {
7ab9ffdd
L		 5296 vex_reg = op + 1;
5297 gas_assert (vex_reg < i.operands);
c0f3af97 5298 }
7ab9ffdd
L		 5299 }
5300 else if (i.tm.opcode_modifier.vexndd)
5301 {
5302 /* For instructions with VexNDD, there should be
5303 no memory operand and the register destination
5304 is encoded in VEX prefix. */
5305 gas_assert (i.mem_operands == 0
5306 && (op + 2) == i.operands);
5307 vex_reg = op + 1;
5308 }
5309 else
5310 gas_assert (op < i.operands);
99018f42 5311
7ab9ffdd
L		 5312 if (vex_reg != (unsigned int) ~0)
5313 {
5314 gas_assert (i.reg_operands == 2);
5315
5316 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5317 & regxmm)
5318 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5319 &regymm))
5320 abort ();
5321 i.vex.register_specifier = i.op[vex_reg].regs;
5322 }
5323
5324 /* If there is an extension opcode to put here, the
5325 register number must be put into the regmem field. */
5326 if (i.tm.extension_opcode != None)
5327 {
5328 i.rm.regmem = i.op[op].regs->reg_num;
5329 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5330 i.rex |= REX_B;
5331 }
5332 else
5333 {
5334 i.rm.reg = i.op[op].regs->reg_num;
5335 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5336 i.rex |= REX_R;
5337 }
252b5132 5338
29b0f896
AM		 5339 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5340 must set it to 3 to indicate this is a register operand
5341 in the regmem field. */
5342 if (!i.mem_operands)
5343 i.rm.mode = 3;
5344 }
252b5132 5345
29b0f896 5346 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5347 if (i.tm.extension_opcode != None)
29b0f896
AM		 5348 i.rm.reg = i.tm.extension_opcode;
5349 }
5350 return default_seg;
5351}
252b5132 5352
29b0f896 5353static void
e3bb37b5 5354output_branch (void)
29b0f896
AM		 5355{
5356 char *p;
5357 int code16;
5358 int prefix;
5359 relax_substateT subtype;
5360 symbolS *sym;
5361 offsetT off;
5362
5363 code16 = 0;
5364 if (flag_code == CODE_16BIT)
5365 code16 = CODE16;
5366
5367 prefix = 0;
5368 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5369 {
29b0f896
AM		 5370 prefix = 1;
5371 i.prefixes -= 1;
5372 code16 ^= CODE16;
252b5132 5373 }
29b0f896
AM		 5374 /* Pentium4 branch hints. */
5375 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5376 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5377 {
29b0f896
AM		 5378 prefix++;
5379 i.prefixes--;
5380 }
5381 if (i.prefix[REX_PREFIX] != 0)
5382 {
5383 prefix++;
5384 i.prefixes--;
2f66722d
AM		 5385 }
5386
29b0f896
AM		 5387 if (i.prefixes != 0 && !intel_syntax)
5388 as_warn (_("skipping prefixes on this instruction"));
5389
5390 /* It's always a symbol; End frag & setup for relax.
5391 Make sure there is enough room in this frag for the largest
5392 instruction we may generate in md_convert_frag. This is 2
5393 bytes for the opcode and room for the prefix and largest
5394 displacement. */
5395 frag_grow (prefix + 2 + 4);
5396 /* Prefix and 1 opcode byte go in fr_fix. */
5397 p = frag_more (prefix + 1);
5398 if (i.prefix[DATA_PREFIX] != 0)
5399 *p++ = DATA_PREFIX_OPCODE;
5400 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5401 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5402 *p++ = i.prefix[SEG_PREFIX];
5403 if (i.prefix[REX_PREFIX] != 0)
5404 *p++ = i.prefix[REX_PREFIX];
5405 *p = i.tm.base_opcode;
5406
5407 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5408 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5409 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5410 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5411 else
5412 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5413 subtype |= code16;
3e73aa7c 5414
29b0f896
AM		 5415 sym = i.op[0].disps->X_add_symbol;
5416 off = i.op[0].disps->X_add_number;
3e73aa7c 5417
29b0f896
AM		 5418 if (i.op[0].disps->X_op != O_constant
5419 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5420 {
29b0f896
AM		 5421 /* Handle complex expressions. */
5422 sym = make_expr_symbol (i.op[0].disps);
5423 off = 0;
5424 }
3e73aa7c 5425
29b0f896
AM		 5426 /* 1 possible extra opcode + 4 byte displacement go in var part.
5427 Pass reloc in fr_var. */
5428 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5429}
3e73aa7c 5430
29b0f896 5431static void
e3bb37b5 5432output_jump (void)
29b0f896
AM		 5433{
5434 char *p;
5435 int size;
3e02c1cc 5436 fixS *fixP;
29b0f896 5437
40fb9820 5438 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5439 {
5440 /* This is a loop or jecxz type instruction. */
5441 size = 1;
5442 if (i.prefix[ADDR_PREFIX] != 0)
5443 {
5444 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5445 i.prefixes -= 1;
5446 }
5447 /* Pentium4 branch hints. */
5448 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5449 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5450 {
5451 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5452 i.prefixes--;
3e73aa7c
JH		 5453 }
5454 }
29b0f896
AM		 5455 else
5456 {
5457 int code16;
3e73aa7c 5458
29b0f896
AM		 5459 code16 = 0;
5460 if (flag_code == CODE_16BIT)
5461 code16 = CODE16;
3e73aa7c 5462
29b0f896
AM		 5463 if (i.prefix[DATA_PREFIX] != 0)
5464 {
5465 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5466 i.prefixes -= 1;
5467 code16 ^= CODE16;
5468 }
252b5132 5469
29b0f896
AM		 5470 size = 4;
5471 if (code16)
5472 size = 2;
5473 }
9fcc94b6 5474
29b0f896
AM		 5475 if (i.prefix[REX_PREFIX] != 0)
5476 {
5477 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5478 i.prefixes -= 1;
5479 }
252b5132 5480
29b0f896
AM		 5481 if (i.prefixes != 0 && !intel_syntax)
5482 as_warn (_("skipping prefixes on this instruction"));
e0890092 5483
29b0f896
AM		 5484 p = frag_more (1 + size);
5485 *p++ = i.tm.base_opcode;
e0890092 5486
3e02c1cc
AM		 5487 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5488 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5489
5490 /* All jumps handled here are signed, but don't use a signed limit
5491 check for 32 and 16 bit jumps as we want to allow wrap around at
5492 4G and 64k respectively. */
5493 if (size == 1)
5494 fixP->fx_signed = 1;
29b0f896 5495}
e0890092 5496
29b0f896 5497static void
e3bb37b5 5498output_interseg_jump (void)
29b0f896
AM		 5499{
5500 char *p;
5501 int size;
5502 int prefix;
5503 int code16;
252b5132 5504
29b0f896
AM		 5505 code16 = 0;
5506 if (flag_code == CODE_16BIT)
5507 code16 = CODE16;
a217f122 5508
29b0f896
AM		 5509 prefix = 0;
5510 if (i.prefix[DATA_PREFIX] != 0)
5511 {
5512 prefix = 1;
5513 i.prefixes -= 1;
5514 code16 ^= CODE16;
5515 }
5516 if (i.prefix[REX_PREFIX] != 0)
5517 {
5518 prefix++;
5519 i.prefixes -= 1;
5520 }
252b5132 5521
29b0f896
AM		 5522 size = 4;
5523 if (code16)
5524 size = 2;
252b5132 5525
29b0f896
AM		 5526 if (i.prefixes != 0 && !intel_syntax)
5527 as_warn (_("skipping prefixes on this instruction"));
252b5132 5528
29b0f896
AM		 5529 /* 1 opcode; 2 segment; offset */
5530 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5531
29b0f896
AM		 5532 if (i.prefix[DATA_PREFIX] != 0)
5533 *p++ = DATA_PREFIX_OPCODE;
252b5132 5534
29b0f896
AM		 5535 if (i.prefix[REX_PREFIX] != 0)
5536 *p++ = i.prefix[REX_PREFIX];
252b5132 5537
29b0f896
AM		 5538 *p++ = i.tm.base_opcode;
5539 if (i.op[1].imms->X_op == O_constant)
5540 {
5541 offsetT n = i.op[1].imms->X_add_number;
252b5132 5542
29b0f896
AM		 5543 if (size == 2
5544 && !fits_in_unsigned_word (n)
5545 && !fits_in_signed_word (n))
5546 {
5547 as_bad (_("16-bit jump out of range"));
5548 return;
5549 }
5550 md_number_to_chars (p, n, size);
5551 }
5552 else
5553 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5554 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5555 if (i.op[0].imms->X_op != O_constant)
5556 as_bad (_("can't handle non absolute segment in `%s'"),
5557 i.tm.name);
5558 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5559}
a217f122 5560
29b0f896 5561static void
e3bb37b5 5562output_insn (void)
29b0f896 5563{
2bbd9c25
JJ		 5564 fragS *insn_start_frag;
5565 offsetT insn_start_off;
5566
29b0f896
AM		 5567 /* Tie dwarf2 debug info to the address at the start of the insn.
5568 We can't do this after the insn has been output as the current
5569 frag may have been closed off. eg. by frag_var. */
5570 dwarf2_emit_insn (0);
5571
2bbd9c25
JJ		 5572 insn_start_frag = frag_now;
5573 insn_start_off = frag_now_fix ();
5574
29b0f896 5575 /* Output jumps. */
40fb9820 5576 if (i.tm.opcode_modifier.jump)
29b0f896 5577 output_branch ();
40fb9820
L		 5578 else if (i.tm.opcode_modifier.jumpbyte
5579 || i.tm.opcode_modifier.jumpdword)
29b0f896 5580 output_jump ();
40fb9820 5581 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5582 output_interseg_jump ();
5583 else
5584 {
5585 /* Output normal instructions here. */
5586 char *p;
5587 unsigned char *q;
47465058 5588 unsigned int j;
331d2d0d 5589 unsigned int prefix;
4dffcebc 5590
c0f3af97
L		 5591 /* Since the VEX prefix contains the implicit prefix, we don't
5592 need the explicit prefix. */
5593 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5594 {
c0f3af97 5595 switch (i.tm.opcode_length)
bc4bd9ab 5596 {
c0f3af97
L		 5597 case 3:
5598 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5599 {
c0f3af97
L		 5600 prefix = (i.tm.base_opcode >> 24) & 0xff;
5601 goto check_prefix;
5602 }
5603 break;
5604 case 2:
5605 if ((i.tm.base_opcode & 0xff0000) != 0)
5606 {
5607 prefix = (i.tm.base_opcode >> 16) & 0xff;
5608 if (i.tm.cpu_flags.bitfield.cpupadlock)
5609 {
4dffcebc 5610check_prefix:
c0f3af97
L		 5611 if (prefix != REPE_PREFIX_OPCODE
5612 || (i.prefix[LOCKREP_PREFIX]
5613 != REPE_PREFIX_OPCODE))
5614 add_prefix (prefix);
5615 }
5616 else
4dffcebc
L		 5617 add_prefix (prefix);
5618 }
c0f3af97
L		 5619 break;
5620 case 1:
5621 break;
5622 default:
5623 abort ();
bc4bd9ab 5624 }
c0f3af97
L		 5625
5626 /* The prefix bytes. */
5627 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5628 if (*q)
5629 FRAG_APPEND_1_CHAR (*q);
0f10071e 5630 }
252b5132 5631
c0f3af97
L		 5632 if (i.tm.opcode_modifier.vex)
5633 {
5634 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5635 if (*q)
5636 switch (j)
5637 {
5638 case REX_PREFIX:
5639 /* REX byte is encoded in VEX prefix. */
5640 break;
5641 case SEG_PREFIX:
5642 case ADDR_PREFIX:
5643 FRAG_APPEND_1_CHAR (*q);
5644 break;
5645 default:
5646 /* There should be no other prefixes for instructions
5647 with VEX prefix. */
5648 abort ();
5649 }
5650
5651 /* Now the VEX prefix. */
5652 p = frag_more (i.vex.length);
5653 for (j = 0; j < i.vex.length; j++)
5654 p[j] = i.vex.bytes[j];
5655 }
252b5132 5656
29b0f896 5657 /* Now the opcode; be careful about word order here! */
4dffcebc 5658 if (i.tm.opcode_length == 1)
29b0f896
AM		 5659 {
5660 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5661 }
5662 else
5663 {
4dffcebc 5664 switch (i.tm.opcode_length)
331d2d0d 5665 {
4dffcebc 5666 case 3:
331d2d0d
L		 5667 p = frag_more (3);
5668 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5669 break;
5670 case 2:
5671 p = frag_more (2);
5672 break;
5673 default:
5674 abort ();
5675 break;
331d2d0d 5676 }
0f10071e 5677
29b0f896
AM		 5678 /* Put out high byte first: can't use md_number_to_chars! */
5679 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5680 *p = i.tm.base_opcode & 0xff;
5681 }
3e73aa7c 5682
29b0f896 5683 /* Now the modrm byte and sib byte (if present). */
40fb9820 5684 if (i.tm.opcode_modifier.modrm)
29b0f896 5685 {
4a3523fa
L		 5686 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5687 | i.rm.reg << 3
5688 | i.rm.mode << 6));
29b0f896
AM		 5689 /* If i.rm.regmem == ESP (4)
5690 && i.rm.mode != (Register mode)
5691 && not 16 bit
5692 ==> need second modrm byte. */
5693 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5694 && i.rm.mode != 3
40fb9820 5695 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5696 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5697 | i.sib.index << 3
5698 | i.sib.scale << 6));
29b0f896 5699 }
3e73aa7c 5700
29b0f896 5701 if (i.disp_operands)
2bbd9c25 5702 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5703
29b0f896 5704 if (i.imm_operands)
2bbd9c25 5705 output_imm (insn_start_frag, insn_start_off);
29b0f896 5706 }
252b5132 5707
29b0f896
AM		 5708#ifdef DEBUG386
5709 if (flag_debug)
5710 {
7b81dfbb 5711 pi ("" /*line*/, &i);
29b0f896
AM		 5712 }
5713#endif /* DEBUG386 */
5714}
252b5132 5715
e205caa7
L		 5716/* Return the size of the displacement operand N. */
5717
5718static int
5719disp_size (unsigned int n)
5720{
5721 int size = 4;
40fb9820
L		 5722 if (i.types[n].bitfield.disp64)
5723 size = 8;
5724 else if (i.types[n].bitfield.disp8)
5725 size = 1;
5726 else if (i.types[n].bitfield.disp16)
5727 size = 2;
e205caa7
L		 5728 return size;
5729}
5730
5731/* Return the size of the immediate operand N. */
5732
5733static int
5734imm_size (unsigned int n)
5735{
5736 int size = 4;
40fb9820
L		 5737 if (i.types[n].bitfield.imm64)
5738 size = 8;
5739 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5740 size = 1;
5741 else if (i.types[n].bitfield.imm16)
5742 size = 2;
e205caa7
L		 5743 return size;
5744}
5745
29b0f896 5746static void
64e74474 5747output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5748{
5749 char *p;
5750 unsigned int n;
252b5132 5751
29b0f896
AM		 5752 for (n = 0; n < i.operands; n++)
5753 {
40fb9820 5754 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5755 {
5756 if (i.op[n].disps->X_op == O_constant)
5757 {
e205caa7 5758 int size = disp_size (n);
29b0f896 5759 offsetT val;
252b5132 5760
29b0f896
AM		 5761 val = offset_in_range (i.op[n].disps->X_add_number,
5762 size);
5763 p = frag_more (size);
5764 md_number_to_chars (p, val, size);
5765 }
5766 else
5767 {
f86103b7 5768 enum bfd_reloc_code_real reloc_type;
e205caa7 5769 int size = disp_size (n);
40fb9820 5770 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5771 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5772
e205caa7 5773 /* We can't have 8 bit displacement here. */
9c2799c2 5774 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5775
29b0f896
AM		 5776 /* The PC relative address is computed relative
5777 to the instruction boundary, so in case immediate
5778 fields follows, we need to adjust the value. */
5779 if (pcrel && i.imm_operands)
5780 {
29b0f896 5781 unsigned int n1;
e205caa7 5782 int sz = 0;
252b5132 5783
29b0f896 5784 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5785 if (operand_type_check (i.types[n1], imm))
252b5132 5786 {
e205caa7
L		 5787 /* Only one immediate is allowed for PC
5788 relative address. */
9c2799c2 5789 gas_assert (sz == 0);
e205caa7
L		 5790 sz = imm_size (n1);
5791 i.op[n].disps->X_add_number -= sz;
252b5132 5792 }
29b0f896 5793 /* We should find the immediate. */
9c2799c2 5794 gas_assert (sz != 0);
29b0f896 5795 }
520dc8e8 5796
29b0f896 5797 p = frag_more (size);
2bbd9c25 5798 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5799 if (GOT_symbol
2bbd9c25 5800 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5801 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5802 || reloc_type == BFD_RELOC_X86_64_32S
5803 || (reloc_type == BFD_RELOC_64
5804 && object_64bit))
d6ab8113
JB		 5805 && (i.op[n].disps->X_op == O_symbol
5806 || (i.op[n].disps->X_op == O_add
5807 && ((symbol_get_value_expression
5808 (i.op[n].disps->X_op_symbol)->X_op)
5809 == O_subtract))))
5810 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5811 {
5812 offsetT add;
5813
5814 if (insn_start_frag == frag_now)
5815 add = (p - frag_now->fr_literal) - insn_start_off;
5816 else
5817 {
5818 fragS *fr;
5819
5820 add = insn_start_frag->fr_fix - insn_start_off;
5821 for (fr = insn_start_frag->fr_next;
5822 fr && fr != frag_now; fr = fr->fr_next)
5823 add += fr->fr_fix;
5824 add += p - frag_now->fr_literal;
5825 }
5826
4fa24527 5827 if (!object_64bit)
7b81dfbb
AJ		 5828 {
5829 reloc_type = BFD_RELOC_386_GOTPC;
5830 i.op[n].imms->X_add_number += add;
5831 }
5832 else if (reloc_type == BFD_RELOC_64)
5833 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5834 else
7b81dfbb
AJ		 5835 /* Don't do the adjustment for x86-64, as there
5836 the pcrel addressing is relative to the _next_
5837 insn, and that is taken care of in other code. */
d6ab8113 5838 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5839 }
062cd5e7 5840 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5841 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5842 }
5843 }
5844 }
5845}
252b5132 5846
29b0f896 5847static void
64e74474 5848output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5849{
5850 char *p;
5851 unsigned int n;
252b5132 5852
29b0f896
AM		 5853 for (n = 0; n < i.operands; n++)
5854 {
40fb9820 5855 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5856 {
5857 if (i.op[n].imms->X_op == O_constant)
5858 {
e205caa7 5859 int size = imm_size (n);
29b0f896 5860 offsetT val;
b4cac588 5861
29b0f896
AM		 5862 val = offset_in_range (i.op[n].imms->X_add_number,
5863 size);
5864 p = frag_more (size);
5865 md_number_to_chars (p, val, size);
5866 }
5867 else
5868 {
5869 /* Not absolute_section.
5870 Need a 32-bit fixup (don't support 8bit
5871 non-absolute imms). Try to support other
5872 sizes ... */
f86103b7 5873 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5874 int size = imm_size (n);
5875 int sign;
29b0f896 5876
40fb9820 5877 if (i.types[n].bitfield.imm32s
a7d61044 5878 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5879 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5880 sign = 1;
e205caa7
L		 5881 else
5882 sign = 0;
520dc8e8 5883
29b0f896
AM		 5884 p = frag_more (size);
5885 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5886
2bbd9c25
JJ		 5887 /* This is tough to explain. We end up with this one if we
5888 * have operands that look like
5889 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5890 * obtain the absolute address of the GOT, and it is strongly
5891 * preferable from a performance point of view to avoid using
5892 * a runtime relocation for this. The actual sequence of
5893 * instructions often look something like:
5894 *
5895 * call .L66
5896 * .L66:
5897 * popl %ebx
5898 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5899 *
5900 * The call and pop essentially return the absolute address
5901 * of the label .L66 and store it in %ebx. The linker itself
5902 * will ultimately change the first operand of the addl so
5903 * that %ebx points to the GOT, but to keep things simple, the
5904 * .o file must have this operand set so that it generates not
5905 * the absolute address of .L66, but the absolute address of
5906 * itself. This allows the linker itself simply treat a GOTPC
5907 * relocation as asking for a pcrel offset to the GOT to be
5908 * added in, and the addend of the relocation is stored in the
5909 * operand field for the instruction itself.
5910 *
5911 * Our job here is to fix the operand so that it would add
5912 * the correct offset so that %ebx would point to itself. The
5913 * thing that is tricky is that .-.L66 will point to the
5914 * beginning of the instruction, so we need to further modify
5915 * the operand so that it will point to itself. There are
5916 * other cases where you have something like:
5917 *
5918 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5919 *
5920 * and here no correction would be required. Internally in
5921 * the assembler we treat operands of this form as not being
5922 * pcrel since the '.' is explicitly mentioned, and I wonder
5923 * whether it would simplify matters to do it this way. Who
5924 * knows. In earlier versions of the PIC patches, the
5925 * pcrel_adjust field was used to store the correction, but
5926 * since the expression is not pcrel, I felt it would be
5927 * confusing to do it this way. */
5928
d6ab8113 5929 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5930 || reloc_type == BFD_RELOC_X86_64_32S
5931 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5932 && GOT_symbol
5933 && GOT_symbol == i.op[n].imms->X_add_symbol
5934 && (i.op[n].imms->X_op == O_symbol
5935 || (i.op[n].imms->X_op == O_add
5936 && ((symbol_get_value_expression
5937 (i.op[n].imms->X_op_symbol)->X_op)
5938 == O_subtract))))
5939 {
2bbd9c25
JJ		 5940 offsetT add;
5941
5942 if (insn_start_frag == frag_now)
5943 add = (p - frag_now->fr_literal) - insn_start_off;
5944 else
5945 {
5946 fragS *fr;
5947
5948 add = insn_start_frag->fr_fix - insn_start_off;
5949 for (fr = insn_start_frag->fr_next;
5950 fr && fr != frag_now; fr = fr->fr_next)
5951 add += fr->fr_fix;
5952 add += p - frag_now->fr_literal;
5953 }
5954
4fa24527 5955 if (!object_64bit)
d6ab8113 5956 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5957 else if (size == 4)
d6ab8113 5958 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5959 else if (size == 8)
5960 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5961 i.op[n].imms->X_add_number += add;
29b0f896 5962 }
29b0f896
AM		 5963 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5964 i.op[n].imms, 0, reloc_type);
5965 }
5966 }
5967 }
252b5132
RH		 5968}
5969\f
d182319b
JB		 5970/* x86_cons_fix_new is called via the expression parsing code when a
5971 reloc is needed. We use this hook to get the correct .got reloc. */
5972static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5973static int cons_sign = -1;
5974
5975void
e3bb37b5 5976x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5977 expressionS *exp)
d182319b
JB		 5978{
5979 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5980
5981 got_reloc = NO_RELOC;
5982
5983#ifdef TE_PE
5984 if (exp->X_op == O_secrel)
5985 {
5986 exp->X_op = O_symbol;
5987 r = BFD_RELOC_32_SECREL;
5988 }
5989#endif
5990
5991 fix_new_exp (frag, off, len, exp, 0, r);
5992}
5993
718ddfc0
JB		 5994#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5995# define lex_got(reloc, adjust, types) NULL
5996#else
f3c180ae
AM		 5997/* Parse operands of the form
5998 <symbol>@GOTOFF+<nnn>
5999 and similar .plt or .got references.
6000
6001 If we find one, set up the correct relocation in RELOC and copy the
6002 input string, minus the `@GOTOFF' into a malloc'd buffer for
6003 parsing by the calling routine. Return this buffer, and if ADJUST
6004 is non-null set it to the length of the string we removed from the
6005 input line. Otherwise return NULL. */
6006static char *
3956db08 6007lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6008 int *adjust,
40fb9820 6009 i386_operand_type *types)
f3c180ae 6010{
7b81dfbb
AJ		 6011 /* Some of the relocations depend on the size of what field is to
6012 be relocated. But in our callers i386_immediate and i386_displacement
6013 we don't yet know the operand size (this will be set by insn
6014 matching). Hence we record the word32 relocation here,
6015 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6016 static const struct {
6017 const char *str;
4fa24527 6018 const enum bfd_reloc_code_real rel[2];
40fb9820 6019 const i386_operand_type types64;
f3c180ae 6020 } gotrel[] = {
4eed87de
AM		 6021 { "PLTOFF", { 0,
6022 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6023 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6024 { "PLT", { BFD_RELOC_386_PLT32,
6025 BFD_RELOC_X86_64_PLT32 },
40fb9820 6026 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6027 { "GOTPLT", { 0,
6028 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6029 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6030 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6031 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6032 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6033 { "GOTPCREL", { 0,
6034 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6035 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6036 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6037 BFD_RELOC_X86_64_TLSGD },
40fb9820 6038 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6039 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6040 0 },
40fb9820 6041 OPERAND_TYPE_NONE },
4eed87de
AM		 6042 { "TLSLD", { 0,
6043 BFD_RELOC_X86_64_TLSLD },
40fb9820 6044 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6045 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6046 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6047 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6048 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6049 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6050 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6051 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6052 0 },
40fb9820 6053 OPERAND_TYPE_NONE },
4eed87de
AM		 6054 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6055 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6056
40fb9820 6057 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6058 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6059 0 },
40fb9820 6060 OPERAND_TYPE_NONE },
4eed87de
AM		 6061 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6062 0 },
40fb9820 6063 OPERAND_TYPE_NONE },
4eed87de
AM		 6064 { "GOT", { BFD_RELOC_386_GOT32,
6065 BFD_RELOC_X86_64_GOT32 },
40fb9820 6066 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6067 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6068 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6069 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6070 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6071 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6072 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6073 };
6074 char *cp;
6075 unsigned int j;
6076
718ddfc0
JB		 6077 if (!IS_ELF)
6078 return NULL;
6079
f3c180ae 6080 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6081 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6082 return NULL;
6083
47465058 6084 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6085 {
6086 int len;
6087
6088 len = strlen (gotrel[j].str);
28f81592 6089 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6090 {
4fa24527 6091 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6092 {
28f81592
AM		 6093 int first, second;
6094 char *tmpbuf, *past_reloc;
f3c180ae 6095
4fa24527 6096 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6097 if (adjust)
6098 *adjust = len;
f3c180ae 6099
3956db08
JB		 6100 if (types)
6101 {
6102 if (flag_code != CODE_64BIT)
40fb9820
L		 6103 {
6104 types->bitfield.imm32 = 1;
6105 types->bitfield.disp32 = 1;
6106 }
3956db08
JB		 6107 else
6108 *types = gotrel[j].types64;
6109 }
6110
f3c180ae
AM		 6111 if (GOT_symbol == NULL)
6112 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6113
28f81592 6114 /* The length of the first part of our input line. */
f3c180ae 6115 first = cp - input_line_pointer;
28f81592
AM		 6116
6117 /* The second part goes from after the reloc token until
67c11a9b 6118 (and including) an end_of_line char or comma. */
28f81592 6119 past_reloc = cp + 1 + len;
67c11a9b
AM		 6120 cp = past_reloc;
6121 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6122 ++cp;
6123 second = cp + 1 - past_reloc;
28f81592
AM		 6124
6125 /* Allocate and copy string. The trailing NUL shouldn't
6126 be necessary, but be safe. */
6127 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6128 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6129 if (second != 0 && *past_reloc != ' ')
6130 /* Replace the relocation token with ' ', so that
6131 errors like foo@GOTOFF1 will be detected. */
6132 tmpbuf[first++] = ' ';
6133 memcpy (tmpbuf + first, past_reloc, second);
6134 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6135 return tmpbuf;
6136 }
6137
4fa24527
JB		 6138 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6139 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6140 return NULL;
6141 }
6142 }
6143
6144 /* Might be a symbol version string. Don't as_bad here. */
6145 return NULL;
6146}
6147
f3c180ae 6148void
e3bb37b5 6149x86_cons (expressionS *exp, int size)
f3c180ae 6150{
ee86248c
JB		 6151 intel_syntax = -intel_syntax;
6152
4fa24527 6153 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6154 {
6155 /* Handle @GOTOFF and the like in an expression. */
6156 char *save;
6157 char *gotfree_input_line;
6158 int adjust;
6159
6160 save = input_line_pointer;
3956db08 6161 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6162 if (gotfree_input_line)
6163 input_line_pointer = gotfree_input_line;
6164
6165 expression (exp);
6166
6167 if (gotfree_input_line)
6168 {
6169 /* expression () has merrily parsed up to the end of line,
6170 or a comma - in the wrong buffer. Transfer how far
6171 input_line_pointer has moved to the right buffer. */
6172 input_line_pointer = (save
6173 + (input_line_pointer - gotfree_input_line)
6174 + adjust);
6175 free (gotfree_input_line);
3992d3b7
AM		 6176 if (exp->X_op == O_constant
6177 || exp->X_op == O_absent
6178 || exp->X_op == O_illegal
6179 || exp->X_op == O_register
6180 || exp->X_op == O_big)
6181 {
6182 char c = *input_line_pointer;
6183 *input_line_pointer = 0;
6184 as_bad (_("missing or invalid expression `%s'"), save);
6185 *input_line_pointer = c;
6186 }
f3c180ae
AM		 6187 }
6188 }
6189 else
6190 expression (exp);
ee86248c
JB		 6191
6192 intel_syntax = -intel_syntax;
6193
6194 if (intel_syntax)
6195 i386_intel_simplify (exp);
f3c180ae
AM		 6196}
6197#endif
6198
d182319b 6199static void signed_cons (int size)
6482c264 6200{
d182319b
JB		 6201 if (flag_code == CODE_64BIT)
6202 cons_sign = 1;
6203 cons (size);
6204 cons_sign = -1;
6482c264
NC		 6205}
6206
d182319b 6207#ifdef TE_PE
6482c264
NC		 6208static void
6209pe_directive_secrel (dummy)
6210 int dummy ATTRIBUTE_UNUSED;
6211{
6212 expressionS exp;
6213
6214 do
6215 {
6216 expression (&exp);
6217 if (exp.X_op == O_symbol)
6218 exp.X_op = O_secrel;
6219
6220 emit_expr (&exp, 4);
6221 }
6222 while (*input_line_pointer++ == ',');
6223
6224 input_line_pointer--;
6225 demand_empty_rest_of_line ();
6226}
6482c264
NC		 6227#endif
6228
252b5132 6229static int
70e41ade 6230i386_immediate (char *imm_start)
252b5132
RH		 6231{
6232 char *save_input_line_pointer;
f3c180ae 6233 char *gotfree_input_line;
252b5132 6234 segT exp_seg = 0;
47926f60 6235 expressionS *exp;
40fb9820
L		 6236 i386_operand_type types;
6237
0dfbf9d7 6238 operand_type_set (&types, ~0);
252b5132
RH		 6239
6240 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6241 {
31b2323c
L		 6242 as_bad (_("at most %d immediate operands are allowed"),
6243 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6244 return 0;
6245 }
6246
6247 exp = &im_expressions[i.imm_operands++];
520dc8e8 6248 i.op[this_operand].imms = exp;
252b5132
RH		 6249
6250 if (is_space_char (*imm_start))
6251 ++imm_start;
6252
6253 save_input_line_pointer = input_line_pointer;
6254 input_line_pointer = imm_start;
6255
3956db08 6256 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6257 if (gotfree_input_line)
6258 input_line_pointer = gotfree_input_line;
252b5132
RH		 6259
6260 exp_seg = expression (exp);
6261
83183c0c 6262 SKIP_WHITESPACE ();
252b5132 6263 if (*input_line_pointer)
f3c180ae 6264 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6265
6266 input_line_pointer = save_input_line_pointer;
f3c180ae 6267 if (gotfree_input_line)
ee86248c
JB		 6268 {
6269 free (gotfree_input_line);
6270
6271 if (exp->X_op == O_constant || exp->X_op == O_register)
6272 exp->X_op = O_illegal;
6273 }
6274
6275 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6276}
252b5132 6277
ee86248c
JB		 6278static int
6279i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6280 i386_operand_type types, const char *imm_start)
6281{
6282 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6283 {
3992d3b7 6284 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6285 imm_start);
3992d3b7 6286 return 0;
252b5132 6287 }
3e73aa7c 6288 else if (exp->X_op == O_constant)
252b5132 6289 {
47926f60 6290 /* Size it properly later. */
40fb9820 6291 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6292 /* If BFD64, sign extend val. */
4eed87de
AM		 6293 if (!use_rela_relocations
6294 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6295 exp->X_add_number
6296 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6297 }
4c63da97 6298#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6299 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6300 && exp_seg != absolute_section
47926f60 6301 && exp_seg != text_section
24eab124
AM		 6302 && exp_seg != data_section
6303 && exp_seg != bss_section
6304 && exp_seg != undefined_section
f86103b7 6305 && !bfd_is_com_section (exp_seg))
252b5132 6306 {
d0b47220 6307 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6308 return 0;
6309 }
6310#endif
bb8f5920
L		 6311 else if (!intel_syntax && exp->X_op == O_register)
6312 {
6313 as_bad (_("illegal immediate register operand %s"), imm_start);
6314 return 0;
6315 }
252b5132
RH		 6316 else
6317 {
6318 /* This is an address. The size of the address will be
24eab124 6319 determined later, depending on destination register,
3e73aa7c 6320 suffix, or the default for the section. */
40fb9820
L		 6321 i.types[this_operand].bitfield.imm8 = 1;
6322 i.types[this_operand].bitfield.imm16 = 1;
6323 i.types[this_operand].bitfield.imm32 = 1;
6324 i.types[this_operand].bitfield.imm32s = 1;
6325 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6326 i.types[this_operand] = operand_type_and (i.types[this_operand],
6327 types);
252b5132
RH		 6328 }
6329
6330 return 1;
6331}
6332
551c1ca1 6333static char *
e3bb37b5 6334i386_scale (char *scale)
252b5132 6335{
551c1ca1
AM		 6336 offsetT val;
6337 char *save = input_line_pointer;
252b5132 6338
551c1ca1
AM		 6339 input_line_pointer = scale;
6340 val = get_absolute_expression ();
6341
6342 switch (val)
252b5132 6343 {
551c1ca1 6344 case 1:
252b5132
RH		 6345 i.log2_scale_factor = 0;
6346 break;
551c1ca1 6347 case 2:
252b5132
RH		 6348 i.log2_scale_factor = 1;
6349 break;
551c1ca1 6350 case 4:
252b5132
RH		 6351 i.log2_scale_factor = 2;
6352 break;
551c1ca1 6353 case 8:
252b5132
RH		 6354 i.log2_scale_factor = 3;
6355 break;
6356 default:
a724f0f4
JB		 6357 {
6358 char sep = *input_line_pointer;
6359
6360 *input_line_pointer = '\0';
6361 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6362 scale);
6363 *input_line_pointer = sep;
6364 input_line_pointer = save;
6365 return NULL;
6366 }
252b5132 6367 }
29b0f896 6368 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6369 {
6370 as_warn (_("scale factor of %d without an index register"),
24eab124 6371 1 << i.log2_scale_factor);
252b5132 6372 i.log2_scale_factor = 0;
252b5132 6373 }
551c1ca1
AM		 6374 scale = input_line_pointer;
6375 input_line_pointer = save;
6376 return scale;
252b5132
RH		 6377}
6378
252b5132 6379static int
e3bb37b5 6380i386_displacement (char *disp_start, char *disp_end)
252b5132 6381{
29b0f896 6382 expressionS *exp;
252b5132
RH		 6383 segT exp_seg = 0;
6384 char *save_input_line_pointer;
f3c180ae 6385 char *gotfree_input_line;
40fb9820
L		 6386 int override;
6387 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6388 int ret;
252b5132 6389
31b2323c
L		 6390 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6391 {
6392 as_bad (_("at most %d displacement operands are allowed"),
6393 MAX_MEMORY_OPERANDS);
6394 return 0;
6395 }
6396
0dfbf9d7 6397 operand_type_set (&bigdisp, 0);
40fb9820
L		 6398 if ((i.types[this_operand].bitfield.jumpabsolute)
6399 || (!current_templates->start->opcode_modifier.jump
6400 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6401 {
40fb9820 6402 bigdisp.bitfield.disp32 = 1;
e05278af 6403 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6404 if (flag_code == CODE_64BIT)
6405 {
6406 if (!override)
6407 {
6408 bigdisp.bitfield.disp32s = 1;
6409 bigdisp.bitfield.disp64 = 1;
6410 }
6411 }
6412 else if ((flag_code == CODE_16BIT) ^ override)
6413 {
6414 bigdisp.bitfield.disp32 = 0;
6415 bigdisp.bitfield.disp16 = 1;
6416 }
e05278af
JB		 6417 }
6418 else
6419 {
6420 /* For PC-relative branches, the width of the displacement
6421 is dependent upon data size, not address size. */
e05278af 6422 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6423 if (flag_code == CODE_64BIT)
6424 {
6425 if (override || i.suffix == WORD_MNEM_SUFFIX)
6426 bigdisp.bitfield.disp16 = 1;
6427 else
6428 {
6429 bigdisp.bitfield.disp32 = 1;
6430 bigdisp.bitfield.disp32s = 1;
6431 }
6432 }
6433 else
e05278af
JB		 6434 {
6435 if (!override)
6436 override = (i.suffix == (flag_code != CODE_16BIT
6437 ? WORD_MNEM_SUFFIX
6438 : LONG_MNEM_SUFFIX));
40fb9820
L		 6439 bigdisp.bitfield.disp32 = 1;
6440 if ((flag_code == CODE_16BIT) ^ override)
6441 {
6442 bigdisp.bitfield.disp32 = 0;
6443 bigdisp.bitfield.disp16 = 1;
6444 }
e05278af 6445 }
e05278af 6446 }
c6fb90c8
L		 6447 i.types[this_operand] = operand_type_or (i.types[this_operand],
6448 bigdisp);
252b5132
RH		 6449
6450 exp = &disp_expressions[i.disp_operands];
520dc8e8 6451 i.op[this_operand].disps = exp;
252b5132
RH		 6452 i.disp_operands++;
6453 save_input_line_pointer = input_line_pointer;
6454 input_line_pointer = disp_start;
6455 END_STRING_AND_SAVE (disp_end);
6456
6457#ifndef GCC_ASM_O_HACK
6458#define GCC_ASM_O_HACK 0
6459#endif
6460#if GCC_ASM_O_HACK
6461 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6462 if (i.types[this_operand].bitfield.baseIndex
24eab124 6463 && displacement_string_end[-1] == '+')
252b5132
RH		 6464 {
6465 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6466 constraint within gcc asm statements.
6467 For instance:
6468
6469 #define _set_tssldt_desc(n,addr,limit,type) \
6470 __asm__ __volatile__ ( \
6471 "movw %w2,%0\n\t" \
6472 "movw %w1,2+%0\n\t" \
6473 "rorl $16,%1\n\t" \
6474 "movb %b1,4+%0\n\t" \
6475 "movb %4,5+%0\n\t" \
6476 "movb $0,6+%0\n\t" \
6477 "movb %h1,7+%0\n\t" \
6478 "rorl $16,%1" \
6479 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6480
6481 This works great except that the output assembler ends
6482 up looking a bit weird if it turns out that there is
6483 no offset. You end up producing code that looks like:
6484
6485 #APP
6486 movw $235,(%eax)
6487 movw %dx,2+(%eax)
6488 rorl $16,%edx
6489 movb %dl,4+(%eax)
6490 movb $137,5+(%eax)
6491 movb $0,6+(%eax)
6492 movb %dh,7+(%eax)
6493 rorl $16,%edx
6494 #NO_APP
6495
47926f60 6496 So here we provide the missing zero. */
24eab124
AM		 6497
6498 *displacement_string_end = '0';
252b5132
RH		 6499 }
6500#endif
3956db08 6501 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6502 if (gotfree_input_line)
6503 input_line_pointer = gotfree_input_line;
252b5132 6504
24eab124 6505 exp_seg = expression (exp);
252b5132 6506
636c26b0
AM		 6507 SKIP_WHITESPACE ();
6508 if (*input_line_pointer)
6509 as_bad (_("junk `%s' after expression"), input_line_pointer);
6510#if GCC_ASM_O_HACK
6511 RESTORE_END_STRING (disp_end + 1);
6512#endif
636c26b0 6513 input_line_pointer = save_input_line_pointer;
636c26b0 6514 if (gotfree_input_line)
ee86248c
JB		 6515 {
6516 free (gotfree_input_line);
6517
6518 if (exp->X_op == O_constant || exp->X_op == O_register)
6519 exp->X_op = O_illegal;
6520 }
6521
6522 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6523
6524 RESTORE_END_STRING (disp_end);
6525
6526 return ret;
6527}
6528
6529static int
6530i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6531 i386_operand_type types, const char *disp_start)
6532{
6533 i386_operand_type bigdisp;
6534 int ret = 1;
636c26b0 6535
24eab124
AM		 6536 /* We do this to make sure that the section symbol is in
6537 the symbol table. We will ultimately change the relocation
47926f60 6538 to be relative to the beginning of the section. */
1ae12ab7 6539 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6540 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6541 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6542 {
636c26b0 6543 if (exp->X_op != O_symbol)
3992d3b7 6544 goto inv_disp;
636c26b0 6545
e5cb08ac 6546 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6547 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6548 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6549 exp->X_op = O_subtract;
6550 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6551 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6552 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6553 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6554 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6555 else
29b0f896 6556 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6557 }
252b5132 6558
3992d3b7
AM		 6559 else if (exp->X_op == O_absent
6560 || exp->X_op == O_illegal
ee86248c 6561 || exp->X_op == O_big)
2daf4fd8 6562 {
3992d3b7
AM		 6563 inv_disp:
6564 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6565 disp_start);
3992d3b7 6566 ret = 0;
2daf4fd8
AM		 6567 }
6568
4c63da97 6569#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6570 else if (exp->X_op != O_constant
6571 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6572 && exp_seg != absolute_section
6573 && exp_seg != text_section
6574 && exp_seg != data_section
6575 && exp_seg != bss_section
6576 && exp_seg != undefined_section
6577 && !bfd_is_com_section (exp_seg))
24eab124 6578 {
d0b47220 6579 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6580 ret = 0;
24eab124 6581 }
252b5132 6582#endif
3956db08 6583
40fb9820
L		 6584 /* Check if this is a displacement only operand. */
6585 bigdisp = i.types[this_operand];
6586 bigdisp.bitfield.disp8 = 0;
6587 bigdisp.bitfield.disp16 = 0;
6588 bigdisp.bitfield.disp32 = 0;
6589 bigdisp.bitfield.disp32s = 0;
6590 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6591 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6592 i.types[this_operand] = operand_type_and (i.types[this_operand],
6593 types);
3956db08 6594
3992d3b7 6595 return ret;
252b5132
RH		 6596}
6597
eecb386c 6598/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6599 Return 1 on success, 0 on a failure. */
6600
252b5132 6601static int
e3bb37b5 6602i386_index_check (const char *operand_string)
252b5132 6603{
3e73aa7c 6604 int ok;
fc0763e6 6605 const char *kind = "base/index";
24eab124 6606#if INFER_ADDR_PREFIX
eecb386c
AM		 6607 int fudged = 0;
6608
24eab124
AM		 6609 tryprefix:
6610#endif
3e73aa7c 6611 ok = 1;
fc0763e6
JB		 6612 if (current_templates->start->opcode_modifier.isstring
6613 && !current_templates->start->opcode_modifier.immext
6614 && (current_templates->end[-1].opcode_modifier.isstring
6615 || i.mem_operands))
6616 {
6617 /* Memory operands of string insns are special in that they only allow
6618 a single register (rDI, rSI, or rBX) as their memory address. */
6619 unsigned int expected;
6620
6621 kind = "string address";
6622
6623 if (current_templates->start->opcode_modifier.w)
6624 {
6625 i386_operand_type type = current_templates->end[-1].operand_types[0];
6626
6627 if (!type.bitfield.baseindex
6628 || ((!i.mem_operands != !intel_syntax)
6629 && current_templates->end[-1].operand_types[1]
6630 .bitfield.baseindex))
6631 type = current_templates->end[-1].operand_types[1];
6632 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6633 }
6634 else
6635 expected = 3 /* rBX */;
6636
6637 if (!i.base_reg || i.index_reg
6638 || operand_type_check (i.types[this_operand], disp))
6639 ok = -1;
6640 else if (!(flag_code == CODE_64BIT
6641 ? i.prefix[ADDR_PREFIX]
6642 ? i.base_reg->reg_type.bitfield.reg32
6643 : i.base_reg->reg_type.bitfield.reg64
6644 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6645 ? i.base_reg->reg_type.bitfield.reg32
6646 : i.base_reg->reg_type.bitfield.reg16))
6647 ok = 0;
6648 else if (i.base_reg->reg_num != expected)
6649 ok = -1;
6650
6651 if (ok < 0)
6652 {
6653 unsigned int j;
6654
6655 for (j = 0; j < i386_regtab_size; ++j)
6656 if ((flag_code == CODE_64BIT
6657 ? i.prefix[ADDR_PREFIX]
6658 ? i386_regtab[j].reg_type.bitfield.reg32
6659 : i386_regtab[j].reg_type.bitfield.reg64
6660 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6661 ? i386_regtab[j].reg_type.bitfield.reg32
6662 : i386_regtab[j].reg_type.bitfield.reg16)
6663 && i386_regtab[j].reg_num == expected)
6664 break;
9c2799c2 6665 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6666 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6667 operand_string,
6668 intel_syntax ? '[' : '(',
6669 register_prefix,
6670 i386_regtab[j].reg_name,
6671 intel_syntax ? ']' : ')');
6672 ok = 1;
6673 }
6674 }
6675 else if (flag_code == CODE_64BIT)
64e74474 6676 {
64e74474 6677 if ((i.base_reg
40fb9820
L		 6678 && ((i.prefix[ADDR_PREFIX] == 0
6679 && !i.base_reg->reg_type.bitfield.reg64)
6680 || (i.prefix[ADDR_PREFIX]
6681 && !i.base_reg->reg_type.bitfield.reg32))
6682 && (i.index_reg
9a04903e
JB		 6683 || i.base_reg->reg_num !=
6684 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6685 || (i.index_reg
40fb9820
L		 6686 && (!i.index_reg->reg_type.bitfield.baseindex
6687 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6688 && i.index_reg->reg_num != RegRiz
6689 && !i.index_reg->reg_type.bitfield.reg64
6690 )
40fb9820 6691 || (i.prefix[ADDR_PREFIX]
db51cc60 6692 && i.index_reg->reg_num != RegEiz
40fb9820 6693 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6694 ok = 0;
3e73aa7c
JH		 6695 }
6696 else
6697 {
6698 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6699 {
6700 /* 16bit checks. */
6701 if ((i.base_reg
40fb9820
L		 6702 && (!i.base_reg->reg_type.bitfield.reg16
6703 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6704 || (i.index_reg
40fb9820
L		 6705 && (!i.index_reg->reg_type.bitfield.reg16
6706 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6707 || !(i.base_reg
6708 && i.base_reg->reg_num < 6
6709 && i.index_reg->reg_num >= 6
6710 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6711 ok = 0;
6712 }
6713 else
e5cb08ac 6714 {
3e73aa7c
JH		 6715 /* 32bit checks. */
6716 if ((i.base_reg
40fb9820 6717 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6718 || (i.index_reg
db51cc60
L		 6719 && ((!i.index_reg->reg_type.bitfield.reg32
6720 && i.index_reg->reg_num != RegEiz)
40fb9820 6721 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6722 ok = 0;
3e73aa7c
JH		 6723 }
6724 }
6725 if (!ok)
24eab124
AM		 6726 {
6727#if INFER_ADDR_PREFIX
fc0763e6 6728 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6729 {
6730 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6731 i.prefixes += 1;
b23bac36
AM		 6732 /* Change the size of any displacement too. At most one of
6733 Disp16 or Disp32 is set.
6734 FIXME. There doesn't seem to be any real need for separate
6735 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6736 Removing them would probably clean up the code quite a lot. */
4eed87de 6737 if (flag_code != CODE_64BIT
40fb9820
L		 6738 && (i.types[this_operand].bitfield.disp16
6739 || i.types[this_operand].bitfield.disp32))
6740 i.types[this_operand]
c6fb90c8 6741 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6742 fudged = 1;
24eab124
AM		 6743 goto tryprefix;
6744 }
eecb386c 6745 if (fudged)
fc0763e6
JB		 6746 as_bad (_("`%s' is not a valid %s expression"),
6747 operand_string,
6748 kind);
eecb386c 6749 else
c388dee8 6750#endif
fc0763e6 6751 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6752 operand_string,
fc0763e6
JB		 6753 flag_code_names[i.prefix[ADDR_PREFIX]
6754 ? flag_code == CODE_32BIT
6755 ? CODE_16BIT
6756 : CODE_32BIT
6757 : flag_code],
6758 kind);
24eab124 6759 }
20f0a1fc 6760 return ok;
24eab124 6761}
252b5132 6762
fc0763e6 6763/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6764 on error. */
252b5132 6765
252b5132 6766static int
a7619375 6767i386_att_operand (char *operand_string)
252b5132 6768{
af6bdddf
AM		 6769 const reg_entry *r;
6770 char *end_op;
24eab124 6771 char *op_string = operand_string;
252b5132 6772
24eab124 6773 if (is_space_char (*op_string))
252b5132
RH		 6774 ++op_string;
6775
24eab124 6776 /* We check for an absolute prefix (differentiating,
47926f60 6777 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6778 if (*op_string == ABSOLUTE_PREFIX)
6779 {
6780 ++op_string;
6781 if (is_space_char (*op_string))
6782 ++op_string;
40fb9820 6783 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6784 }
252b5132 6785
47926f60 6786 /* Check if operand is a register. */
4d1bb795 6787 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6788 {
40fb9820
L		 6789 i386_operand_type temp;
6790
24eab124
AM		 6791 /* Check for a segment override by searching for ':' after a
6792 segment register. */
6793 op_string = end_op;
6794 if (is_space_char (*op_string))
6795 ++op_string;
40fb9820
L		 6796 if (*op_string == ':'
6797 && (r->reg_type.bitfield.sreg2
6798 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6799 {
6800 switch (r->reg_num)
6801 {
6802 case 0:
6803 i.seg[i.mem_operands] = &es;
6804 break;
6805 case 1:
6806 i.seg[i.mem_operands] = &cs;
6807 break;
6808 case 2:
6809 i.seg[i.mem_operands] = &ss;
6810 break;
6811 case 3:
6812 i.seg[i.mem_operands] = &ds;
6813 break;
6814 case 4:
6815 i.seg[i.mem_operands] = &fs;
6816 break;
6817 case 5:
6818 i.seg[i.mem_operands] = &gs;
6819 break;
6820 }
252b5132 6821
24eab124 6822 /* Skip the ':' and whitespace. */
252b5132
RH		 6823 ++op_string;
6824 if (is_space_char (*op_string))
24eab124 6825 ++op_string;
252b5132 6826
24eab124
AM		 6827 if (!is_digit_char (*op_string)
6828 && !is_identifier_char (*op_string)
6829 && *op_string != '('
6830 && *op_string != ABSOLUTE_PREFIX)
6831 {
6832 as_bad (_("bad memory operand `%s'"), op_string);
6833 return 0;
6834 }
47926f60 6835 /* Handle case of %es:*foo. */
24eab124
AM		 6836 if (*op_string == ABSOLUTE_PREFIX)
6837 {
6838 ++op_string;
6839 if (is_space_char (*op_string))
6840 ++op_string;
40fb9820 6841 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6842 }
6843 goto do_memory_reference;
6844 }
6845 if (*op_string)
6846 {
d0b47220 6847 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6848 return 0;
6849 }
40fb9820
L		 6850 temp = r->reg_type;
6851 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6852 i.types[this_operand] = operand_type_or (i.types[this_operand],
6853 temp);
7d5e4556 6854 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6855 i.op[this_operand].regs = r;
24eab124
AM		 6856 i.reg_operands++;
6857 }
af6bdddf
AM		 6858 else if (*op_string == REGISTER_PREFIX)
6859 {
6860 as_bad (_("bad register name `%s'"), op_string);
6861 return 0;
6862 }
24eab124 6863 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6864 {
24eab124 6865 ++op_string;
40fb9820 6866 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6867 {
d0b47220 6868 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6869 return 0;
6870 }
6871 if (!i386_immediate (op_string))
6872 return 0;
6873 }
6874 else if (is_digit_char (*op_string)
6875 || is_identifier_char (*op_string)
e5cb08ac 6876 || *op_string == '(')
24eab124 6877 {
47926f60 6878 /* This is a memory reference of some sort. */
af6bdddf 6879 char *base_string;
252b5132 6880
47926f60 6881 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6882 char *displacement_string_start;
6883 char *displacement_string_end;
252b5132 6884
24eab124 6885 do_memory_reference:
24eab124 6886 if ((i.mem_operands == 1
40fb9820 6887 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6888 || i.mem_operands == 2)
6889 {
6890 as_bad (_("too many memory references for `%s'"),
6891 current_templates->start->name);
6892 return 0;
6893 }
252b5132 6894
24eab124
AM		 6895 /* Check for base index form. We detect the base index form by
6896 looking for an ')' at the end of the operand, searching
6897 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6898 after the '('. */
af6bdddf 6899 base_string = op_string + strlen (op_string);
c3332e24 6900
af6bdddf
AM		 6901 --base_string;
6902 if (is_space_char (*base_string))
6903 --base_string;
252b5132 6904
47926f60 6905 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6906 displacement_string_start = op_string;
6907 displacement_string_end = base_string + 1;
252b5132 6908
24eab124
AM		 6909 if (*base_string == ')')
6910 {
af6bdddf 6911 char *temp_string;
24eab124
AM		 6912 unsigned int parens_balanced = 1;
6913 /* We've already checked that the number of left & right ()'s are
47926f60 6914 equal, so this loop will not be infinite. */
24eab124
AM		 6915 do
6916 {
6917 base_string--;
6918 if (*base_string == ')')
6919 parens_balanced++;
6920 if (*base_string == '(')
6921 parens_balanced--;
6922 }
6923 while (parens_balanced);
c3332e24 6924
af6bdddf 6925 temp_string = base_string;
c3332e24 6926
24eab124 6927 /* Skip past '(' and whitespace. */
252b5132
RH		 6928 ++base_string;
6929 if (is_space_char (*base_string))
24eab124 6930 ++base_string;
252b5132 6931
af6bdddf 6932 if (*base_string == ','
4eed87de
AM		 6933 || ((i.base_reg = parse_register (base_string, &end_op))
6934 != NULL))
252b5132 6935 {
af6bdddf 6936 displacement_string_end = temp_string;
252b5132 6937
40fb9820 6938 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6939
af6bdddf 6940 if (i.base_reg)
24eab124 6941 {
24eab124
AM		 6942 base_string = end_op;
6943 if (is_space_char (*base_string))
6944 ++base_string;
af6bdddf
AM		 6945 }
6946
6947 /* There may be an index reg or scale factor here. */
6948 if (*base_string == ',')
6949 {
6950 ++base_string;
6951 if (is_space_char (*base_string))
6952 ++base_string;
6953
4eed87de
AM		 6954 if ((i.index_reg = parse_register (base_string, &end_op))
6955 != NULL)
24eab124 6956 {
af6bdddf 6957 base_string = end_op;
24eab124
AM		 6958 if (is_space_char (*base_string))
6959 ++base_string;
af6bdddf
AM		 6960 if (*base_string == ',')
6961 {
6962 ++base_string;
6963 if (is_space_char (*base_string))
6964 ++base_string;
6965 }
e5cb08ac 6966 else if (*base_string != ')')
af6bdddf 6967 {
4eed87de
AM		 6968 as_bad (_("expecting `,' or `)' "
6969 "after index register in `%s'"),
af6bdddf
AM		 6970 operand_string);
6971 return 0;
6972 }
24eab124 6973 }
af6bdddf 6974 else if (*base_string == REGISTER_PREFIX)
24eab124 6975 {
af6bdddf 6976 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6977 return 0;
6978 }
252b5132 6979
47926f60 6980 /* Check for scale factor. */
551c1ca1 6981 if (*base_string != ')')
af6bdddf 6982 {
551c1ca1
AM		 6983 char *end_scale = i386_scale (base_string);
6984
6985 if (!end_scale)
af6bdddf 6986 return 0;
24eab124 6987
551c1ca1 6988 base_string = end_scale;
af6bdddf
AM		 6989 if (is_space_char (*base_string))
6990 ++base_string;
6991 if (*base_string != ')')
6992 {
4eed87de
AM		 6993 as_bad (_("expecting `)' "
6994 "after scale factor in `%s'"),
af6bdddf
AM		 6995 operand_string);
6996 return 0;
6997 }
6998 }
6999 else if (!i.index_reg)
24eab124 7000 {
4eed87de
AM		 7001 as_bad (_("expecting index register or scale factor "
7002 "after `,'; got '%c'"),
af6bdddf 7003 *base_string);
24eab124
AM		 7004 return 0;
7005 }
7006 }
af6bdddf 7007 else if (*base_string != ')')
24eab124 7008 {
4eed87de
AM		 7009 as_bad (_("expecting `,' or `)' "
7010 "after base register in `%s'"),
af6bdddf 7011 operand_string);
24eab124
AM		 7012 return 0;
7013 }
c3332e24 7014 }
af6bdddf 7015 else if (*base_string == REGISTER_PREFIX)
c3332e24 7016 {
af6bdddf 7017 as_bad (_("bad register name `%s'"), base_string);
24eab124 7018 return 0;
c3332e24 7019 }
24eab124
AM		 7020 }
7021
7022 /* If there's an expression beginning the operand, parse it,
7023 assuming displacement_string_start and
7024 displacement_string_end are meaningful. */
7025 if (displacement_string_start != displacement_string_end)
7026 {
7027 if (!i386_displacement (displacement_string_start,
7028 displacement_string_end))
7029 return 0;
7030 }
7031
7032 /* Special case for (%dx) while doing input/output op. */
7033 if (i.base_reg
0dfbf9d7
L		 7034 && operand_type_equal (&i.base_reg->reg_type,
7035 &reg16_inoutportreg)
24eab124
AM		 7036 && i.index_reg == 0
7037 && i.log2_scale_factor == 0
7038 && i.seg[i.mem_operands] == 0
40fb9820 7039 && !operand_type_check (i.types[this_operand], disp))
24eab124 7040 {
65da13b5 7041 i.types[this_operand] = inoutportreg;
24eab124
AM		 7042 return 1;
7043 }
7044
eecb386c
AM		 7045 if (i386_index_check (operand_string) == 0)
7046 return 0;
5c07affc 7047 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7048 i.mem_operands++;
7049 }
7050 else
ce8a8b2f
AM		 7051 {
7052 /* It's not a memory operand; argh! */
24eab124
AM		 7053 as_bad (_("invalid char %s beginning operand %d `%s'"),
7054 output_invalid (*op_string),
7055 this_operand + 1,
7056 op_string);
7057 return 0;
7058 }
47926f60 7059 return 1; /* Normal return. */
252b5132
RH		 7060}
7061\f
ee7fcc42
AM		 7062/* md_estimate_size_before_relax()
7063
7064 Called just before relax() for rs_machine_dependent frags. The x86
7065 assembler uses these frags to handle variable size jump
7066 instructions.
7067
7068 Any symbol that is now undefined will not become defined.
7069 Return the correct fr_subtype in the frag.
7070 Return the initial "guess for variable size of frag" to caller.
7071 The guess is actually the growth beyond the fixed part. Whatever
7072 we do to grow the fixed or variable part contributes to our
7073 returned value. */
7074
252b5132
RH		 7075int
7076md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7077 fragS *fragP;
7078 segT segment;
252b5132 7079{
252b5132 7080 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7081 check for un-relaxable symbols. On an ELF system, we can't relax
7082 an externally visible symbol, because it may be overridden by a
7083 shared library. */
7084 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7085#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7086 || (IS_ELF
31312f95 7087 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7088 || S_IS_WEAK (fragP->fr_symbol)
7089 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7090 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7091#endif
7092#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7093 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7094 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7095#endif
7096 )
252b5132 7097 {
b98ef147
AM		 7098 /* Symbol is undefined in this segment, or we need to keep a
7099 reloc so that weak symbols can be overridden. */
7100 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7101 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7102 unsigned char *opcode;
7103 int old_fr_fix;
f6af82bd 7104
ee7fcc42
AM		 7105 if (fragP->fr_var != NO_RELOC)
7106 reloc_type = fragP->fr_var;
b98ef147 7107 else if (size == 2)
f6af82bd
AM		 7108 reloc_type = BFD_RELOC_16_PCREL;
7109 else
7110 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7111
ee7fcc42
AM		 7112 old_fr_fix = fragP->fr_fix;
7113 opcode = (unsigned char *) fragP->fr_opcode;
7114
fddf5b5b 7115 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7116 {
fddf5b5b
AM		 7117 case UNCOND_JUMP:
7118 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7119 opcode[0] = 0xe9;
252b5132 7120 fragP->fr_fix += size;
062cd5e7
AS		 7121 fix_new (fragP, old_fr_fix, size,
7122 fragP->fr_symbol,
7123 fragP->fr_offset, 1,
7124 reloc_type);
252b5132
RH		 7125 break;
7126
fddf5b5b 7127 case COND_JUMP86:
412167cb
AM		 7128 if (size == 2
7129 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7130 {
7131 /* Negate the condition, and branch past an
7132 unconditional jump. */
7133 opcode[0] ^= 1;
7134 opcode[1] = 3;
7135 /* Insert an unconditional jump. */
7136 opcode[2] = 0xe9;
7137 /* We added two extra opcode bytes, and have a two byte
7138 offset. */
7139 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7140 fix_new (fragP, old_fr_fix + 2, 2,
7141 fragP->fr_symbol,
7142 fragP->fr_offset, 1,
7143 reloc_type);
fddf5b5b
AM		 7144 break;
7145 }
7146 /* Fall through. */
7147
7148 case COND_JUMP:
412167cb
AM		 7149 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7150 {
3e02c1cc
AM		 7151 fixS *fixP;
7152
412167cb 7153 fragP->fr_fix += 1;
3e02c1cc
AM		 7154 fixP = fix_new (fragP, old_fr_fix, 1,
7155 fragP->fr_symbol,
7156 fragP->fr_offset, 1,
7157 BFD_RELOC_8_PCREL);
7158 fixP->fx_signed = 1;
412167cb
AM		 7159 break;
7160 }
93c2a809 7161
24eab124 7162 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7163 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7164 opcode[1] = opcode[0] + 0x10;
f6af82bd 7165 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7166 /* We've added an opcode byte. */
7167 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7168 fix_new (fragP, old_fr_fix + 1, size,
7169 fragP->fr_symbol,
7170 fragP->fr_offset, 1,
7171 reloc_type);
252b5132 7172 break;
fddf5b5b
AM		 7173
7174 default:
7175 BAD_CASE (fragP->fr_subtype);
7176 break;
252b5132
RH		 7177 }
7178 frag_wane (fragP);
ee7fcc42 7179 return fragP->fr_fix - old_fr_fix;
252b5132 7180 }
93c2a809 7181
93c2a809
AM		 7182 /* Guess size depending on current relax state. Initially the relax
7183 state will correspond to a short jump and we return 1, because
7184 the variable part of the frag (the branch offset) is one byte
7185 long. However, we can relax a section more than once and in that
7186 case we must either set fr_subtype back to the unrelaxed state,
7187 or return the value for the appropriate branch. */
7188 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7189}
7190
47926f60
KH		 7191/* Called after relax() is finished.
7192
7193 In: Address of frag.
7194 fr_type == rs_machine_dependent.
7195 fr_subtype is what the address relaxed to.
7196
7197 Out: Any fixSs and constants are set up.
7198 Caller will turn frag into a ".space 0". */
7199
252b5132
RH		 7200void
7201md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7202 bfd *abfd ATTRIBUTE_UNUSED;
7203 segT sec ATTRIBUTE_UNUSED;
29b0f896 7204 fragS *fragP;
252b5132 7205{
29b0f896 7206 unsigned char *opcode;
252b5132 7207 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7208 offsetT target_address;
7209 offsetT opcode_address;
252b5132 7210 unsigned int extension = 0;
847f7ad4 7211 offsetT displacement_from_opcode_start;
252b5132
RH		 7212
7213 opcode = (unsigned char *) fragP->fr_opcode;
7214
47926f60 7215 /* Address we want to reach in file space. */
252b5132 7216 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7217
47926f60 7218 /* Address opcode resides at in file space. */
252b5132
RH		 7219 opcode_address = fragP->fr_address + fragP->fr_fix;
7220
47926f60 7221 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7222 displacement_from_opcode_start = target_address - opcode_address;
7223
fddf5b5b 7224 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7225 {
47926f60
KH		 7226 /* Don't have to change opcode. */
7227 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7228 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7229 }
7230 else
7231 {
7232 if (no_cond_jump_promotion
7233 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7234 as_warn_where (fragP->fr_file, fragP->fr_line,
7235 _("long jump required"));
252b5132 7236
fddf5b5b
AM		 7237 switch (fragP->fr_subtype)
7238 {
7239 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7240 extension = 4; /* 1 opcode + 4 displacement */
7241 opcode[0] = 0xe9;
7242 where_to_put_displacement = &opcode[1];
7243 break;
252b5132 7244
fddf5b5b
AM		 7245 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7246 extension = 2; /* 1 opcode + 2 displacement */
7247 opcode[0] = 0xe9;
7248 where_to_put_displacement = &opcode[1];
7249 break;
252b5132 7250
fddf5b5b
AM		 7251 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7252 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7253 extension = 5; /* 2 opcode + 4 displacement */
7254 opcode[1] = opcode[0] + 0x10;
7255 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7256 where_to_put_displacement = &opcode[2];
7257 break;
252b5132 7258
fddf5b5b
AM		 7259 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7260 extension = 3; /* 2 opcode + 2 displacement */
7261 opcode[1] = opcode[0] + 0x10;
7262 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7263 where_to_put_displacement = &opcode[2];
7264 break;
252b5132 7265
fddf5b5b
AM		 7266 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7267 extension = 4;
7268 opcode[0] ^= 1;
7269 opcode[1] = 3;
7270 opcode[2] = 0xe9;
7271 where_to_put_displacement = &opcode[3];
7272 break;
7273
7274 default:
7275 BAD_CASE (fragP->fr_subtype);
7276 break;
7277 }
252b5132 7278 }
fddf5b5b 7279
7b81dfbb
AJ		 7280 /* If size if less then four we are sure that the operand fits,
7281 but if it's 4, then it could be that the displacement is larger
7282 then -/+ 2GB. */
7283 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7284 && object_64bit
7285 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7286 + ((addressT) 1 << 31))
7287 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7288 {
7289 as_bad_where (fragP->fr_file, fragP->fr_line,
7290 _("jump target out of range"));
7291 /* Make us emit 0. */
7292 displacement_from_opcode_start = extension;
7293 }
47926f60 7294 /* Now put displacement after opcode. */
252b5132
RH		 7295 md_number_to_chars ((char *) where_to_put_displacement,
7296 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7297 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7298 fragP->fr_fix += extension;
7299}
7300\f
252b5132
RH		 7301/* Apply a fixup (fixS) to segment data, once it has been determined
7302 by our caller that we have all the info we need to fix it up.
7303
7304 On the 386, immediates, displacements, and data pointers are all in
7305 the same (little-endian) format, so we don't need to care about which
7306 we are handling. */
7307
94f592af 7308void
55cf6793 7309md_apply_fix (fixP, valP, seg)
47926f60
KH		 7310 /* The fix we're to put in. */
7311 fixS *fixP;
47926f60 7312 /* Pointer to the value of the bits. */
c6682705 7313 valueT *valP;
47926f60
KH		 7314 /* Segment fix is from. */
7315 segT seg ATTRIBUTE_UNUSED;
252b5132 7316{
94f592af 7317 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7318 valueT value = *valP;
252b5132 7319
f86103b7 7320#if !defined (TE_Mach)
93382f6d
AM		 7321 if (fixP->fx_pcrel)
7322 {
7323 switch (fixP->fx_r_type)
7324 {
5865bb77
ILT		 7325 default:
7326 break;
7327
d6ab8113
JB		 7328 case BFD_RELOC_64:
7329 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7330 break;
93382f6d 7331 case BFD_RELOC_32:
ae8887b5 7332 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7333 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7334 break;
7335 case BFD_RELOC_16:
7336 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7337 break;
7338 case BFD_RELOC_8:
7339 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7340 break;
7341 }
7342 }
252b5132 7343
a161fe53 7344 if (fixP->fx_addsy != NULL
31312f95 7345 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7346 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7347 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7348 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7349 && !use_rela_relocations)
252b5132 7350 {
31312f95
AM		 7351 /* This is a hack. There should be a better way to handle this.
7352 This covers for the fact that bfd_install_relocation will
7353 subtract the current location (for partial_inplace, PC relative
7354 relocations); see more below. */
252b5132 7355#ifndef OBJ_AOUT
718ddfc0 7356 if (IS_ELF
252b5132
RH		 7357#ifdef TE_PE
7358 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7359#endif
7360 )
7361 value += fixP->fx_where + fixP->fx_frag->fr_address;
7362#endif
7363#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7364 if (IS_ELF)
252b5132 7365 {
6539b54b 7366 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7367
6539b54b 7368 if ((sym_seg == seg
2f66722d 7369 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7370 && sym_seg != absolute_section))
c25bc9fc 7371 && !TC_FORCE_RELOCATION (fixP))
2f66722d
AM		 7372 {
7373 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7374 bfd_install_relocation subtracts them out again. I think
7375 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7376 it. FIXME. */
7377 value += fixP->fx_where + fixP->fx_frag->fr_address;
7378 }
252b5132
RH		 7379 }
7380#endif
7381#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7382 /* For some reason, the PE format does not store a
7383 section address offset for a PC relative symbol. */
7384 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7385 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7386 value += md_pcrel_from (fixP);
7387#endif
7388 }
fbeb56a4
DK		 7389#if defined (OBJ_COFF) && defined (TE_PE)
7390 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7391 {
7392 value -= S_GET_VALUE (fixP->fx_addsy);
7393 }
7394#endif
252b5132
RH		 7395
7396 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7397 and we must not disappoint it. */
252b5132 7398#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7399 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7400 switch (fixP->fx_r_type)
7401 {
7402 case BFD_RELOC_386_PLT32:
3e73aa7c 7403 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7404 /* Make the jump instruction point to the address of the operand. At
7405 runtime we merely add the offset to the actual PLT entry. */
7406 value = -4;
7407 break;
31312f95 7408
13ae64f3
JJ		 7409 case BFD_RELOC_386_TLS_GD:
7410 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7411 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7412 case BFD_RELOC_386_TLS_IE:
7413 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7414 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7415 case BFD_RELOC_X86_64_TLSGD:
7416 case BFD_RELOC_X86_64_TLSLD:
7417 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7418 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7419 value = 0; /* Fully resolved at runtime. No addend. */
7420 /* Fallthrough */
7421 case BFD_RELOC_386_TLS_LE:
7422 case BFD_RELOC_386_TLS_LDO_32:
7423 case BFD_RELOC_386_TLS_LE_32:
7424 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7425 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7426 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7427 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7428 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7429 break;
7430
67a4f2b7
AO		 7431 case BFD_RELOC_386_TLS_DESC_CALL:
7432 case BFD_RELOC_X86_64_TLSDESC_CALL:
7433 value = 0; /* Fully resolved at runtime. No addend. */
7434 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7435 fixP->fx_done = 0;
7436 return;
7437
00f7efb6
JJ		 7438 case BFD_RELOC_386_GOT32:
7439 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7440 value = 0; /* Fully resolved at runtime. No addend. */
7441 break;
47926f60
KH		 7442
7443 case BFD_RELOC_VTABLE_INHERIT:
7444 case BFD_RELOC_VTABLE_ENTRY:
7445 fixP->fx_done = 0;
94f592af 7446 return;
47926f60
KH		 7447
7448 default:
7449 break;
7450 }
7451#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7452 *valP = value;
f86103b7 7453#endif /* !defined (TE_Mach) */
3e73aa7c 7454
3e73aa7c 7455 /* Are we finished with this relocation now? */
c6682705 7456 if (fixP->fx_addsy == NULL)
3e73aa7c 7457 fixP->fx_done = 1;
fbeb56a4
DK		 7458#if defined (OBJ_COFF) && defined (TE_PE)
7459 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7460 {
7461 fixP->fx_done = 0;
7462 /* Remember value for tc_gen_reloc. */
7463 fixP->fx_addnumber = value;
7464 /* Clear out the frag for now. */
7465 value = 0;
7466 }
7467#endif
3e73aa7c
JH		 7468 else if (use_rela_relocations)
7469 {
7470 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7471 /* Remember value for tc_gen_reloc. */
7472 fixP->fx_addnumber = value;
3e73aa7c
JH		 7473 value = 0;
7474 }
f86103b7 7475
94f592af 7476 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7477}
252b5132 7478\f
252b5132 7479char *
499ac353 7480md_atof (int type, char *litP, int *sizeP)
252b5132 7481{
499ac353
NC		 7482 /* This outputs the LITTLENUMs in REVERSE order;
7483 in accord with the bigendian 386. */
7484 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7485}
7486\f
2d545b82 7487static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7488
252b5132 7489static char *
e3bb37b5 7490output_invalid (int c)
252b5132 7491{
3882b010 7492 if (ISPRINT (c))
f9f21a03
L		 7493 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7494 "'%c'", c);
252b5132 7495 else
f9f21a03 7496 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7497 "(0x%x)", (unsigned char) c);
252b5132
RH		 7498 return output_invalid_buf;
7499}
7500
af6bdddf 7501/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7502
7503static const reg_entry *
4d1bb795 7504parse_real_register (char *reg_string, char **end_op)
252b5132 7505{
af6bdddf
AM		 7506 char *s = reg_string;
7507 char *p;
252b5132
RH		 7508 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7509 const reg_entry *r;
7510
7511 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7512 if (*s == REGISTER_PREFIX)
7513 ++s;
7514
7515 if (is_space_char (*s))
7516 ++s;
7517
7518 p = reg_name_given;
af6bdddf 7519 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7520 {
7521 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7522 return (const reg_entry *) NULL;
7523 s++;
252b5132
RH		 7524 }
7525
6588847e
DN		 7526 /* For naked regs, make sure that we are not dealing with an identifier.
7527 This prevents confusing an identifier like `eax_var' with register
7528 `eax'. */
7529 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7530 return (const reg_entry *) NULL;
7531
af6bdddf 7532 *end_op = s;
252b5132
RH		 7533
7534 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7535
5f47d35b 7536 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7537 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7538 {
5f47d35b
AM		 7539 if (is_space_char (*s))
7540 ++s;
7541 if (*s == '(')
7542 {
af6bdddf 7543 ++s;
5f47d35b
AM		 7544 if (is_space_char (*s))
7545 ++s;
7546 if (*s >= '0' && *s <= '7')
7547 {
db557034 7548 int fpr = *s - '0';
af6bdddf 7549 ++s;
5f47d35b
AM		 7550 if (is_space_char (*s))
7551 ++s;
7552 if (*s == ')')
7553 {
7554 *end_op = s + 1;
db557034
AM		 7555 r = hash_find (reg_hash, "st(0)");
7556 know (r);
7557 return r + fpr;
5f47d35b 7558 }
5f47d35b 7559 }
47926f60 7560 /* We have "%st(" then garbage. */
5f47d35b
AM		 7561 return (const reg_entry *) NULL;
7562 }
7563 }
7564
a60de03c
JB		 7565 if (r == NULL || allow_pseudo_reg)
7566 return r;
7567
0dfbf9d7 7568 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7569 return (const reg_entry *) NULL;
7570
192dc9c6
JB		 7571 if ((r->reg_type.bitfield.reg32
7572 || r->reg_type.bitfield.sreg3
7573 || r->reg_type.bitfield.control
7574 || r->reg_type.bitfield.debug
7575 || r->reg_type.bitfield.test)
7576 && !cpu_arch_flags.bitfield.cpui386)
7577 return (const reg_entry *) NULL;
7578
309d3373
JB		 7579 if (r->reg_type.bitfield.floatreg
7580 && !cpu_arch_flags.bitfield.cpu8087
7581 && !cpu_arch_flags.bitfield.cpu287
7582 && !cpu_arch_flags.bitfield.cpu387)
7583 return (const reg_entry *) NULL;
7584
192dc9c6
JB		 7585 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7586 return (const reg_entry *) NULL;
7587
7588 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7589 return (const reg_entry *) NULL;
7590
40f12533
L		 7591 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7592 return (const reg_entry *) NULL;
7593
db51cc60 7594 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7595 if (!allow_index_reg
db51cc60
L		 7596 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7597 return (const reg_entry *) NULL;
7598
a60de03c
JB		 7599 if (((r->reg_flags & (RegRex64 | RegRex))
7600 || r->reg_type.bitfield.reg64)
40fb9820 7601 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7602 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7603 && flag_code != CODE_64BIT)
20f0a1fc 7604 return (const reg_entry *) NULL;
1ae00879 7605
b7240065
JB		 7606 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7607 return (const reg_entry *) NULL;
7608
252b5132
RH		 7609 return r;
7610}
4d1bb795
JB		 7611
7612/* REG_STRING starts *before* REGISTER_PREFIX. */
7613
7614static const reg_entry *
7615parse_register (char *reg_string, char **end_op)
7616{
7617 const reg_entry *r;
7618
7619 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7620 r = parse_real_register (reg_string, end_op);
7621 else
7622 r = NULL;
7623 if (!r)
7624 {
7625 char *save = input_line_pointer;
7626 char c;
7627 symbolS *symbolP;
7628
7629 input_line_pointer = reg_string;
7630 c = get_symbol_end ();
7631 symbolP = symbol_find (reg_string);
7632 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7633 {
7634 const expressionS *e = symbol_get_value_expression (symbolP);
7635
7636 know (e->X_op == O_register);
4eed87de 7637 know (e->X_add_number >= 0
c3fe08fa 7638 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7639 r = i386_regtab + e->X_add_number;
7640 *end_op = input_line_pointer;
7641 }
7642 *input_line_pointer = c;
7643 input_line_pointer = save;
7644 }
7645 return r;
7646}
7647
7648int
7649i386_parse_name (char *name, expressionS *e, char *nextcharP)
7650{
7651 const reg_entry *r;
7652 char *end = input_line_pointer;
7653
7654 *end = *nextcharP;
7655 r = parse_register (name, &input_line_pointer);
7656 if (r && end <= input_line_pointer)
7657 {
7658 *nextcharP = *input_line_pointer;
7659 *input_line_pointer = 0;
7660 e->X_op = O_register;
7661 e->X_add_number = r - i386_regtab;
7662 return 1;
7663 }
7664 input_line_pointer = end;
7665 *end = 0;
ee86248c 7666 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7667}
7668
7669void
7670md_operand (expressionS *e)
7671{
ee86248c
JB		 7672 char *end;
7673 const reg_entry *r;
4d1bb795 7674
ee86248c
JB		 7675 switch (*input_line_pointer)
7676 {
7677 case REGISTER_PREFIX:
7678 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7679 if (r)
7680 {
7681 e->X_op = O_register;
7682 e->X_add_number = r - i386_regtab;
7683 input_line_pointer = end;
7684 }
ee86248c
JB		 7685 break;
7686
7687 case '[':
9c2799c2 7688 gas_assert (intel_syntax);
ee86248c
JB		 7689 end = input_line_pointer++;
7690 expression (e);
7691 if (*input_line_pointer == ']')
7692 {
7693 ++input_line_pointer;
7694 e->X_op_symbol = make_expr_symbol (e);
7695 e->X_add_symbol = NULL;
7696 e->X_add_number = 0;
7697 e->X_op = O_index;
7698 }
7699 else
7700 {
7701 e->X_op = O_absent;
7702 input_line_pointer = end;
7703 }
7704 break;
4d1bb795
JB		 7705 }
7706}
7707
252b5132 7708\f
4cc782b5 7709#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7710const char *md_shortopts = "kVQ:sqn";
252b5132 7711#else
12b55ccc 7712const char *md_shortopts = "qn";
252b5132 7713#endif
6e0b89ee 7714
3e73aa7c 7715#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7716#define OPTION_64 (OPTION_MD_BASE + 1)
7717#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7718#define OPTION_MARCH (OPTION_MD_BASE + 3)
7719#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7720#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7721#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7722#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7723#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7724#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7725#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7726#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7727
99ad8390
NC		 7728struct option md_longopts[] =
7729{
3e73aa7c 7730 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7731#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7732 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7733 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7734#endif
b3b91714 7735 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7736 {"march", required_argument, NULL, OPTION_MARCH},
7737 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7738 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7739 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7740 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7741 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7742 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7743 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7744 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7745 {NULL, no_argument, NULL, 0}
7746};
7747size_t md_longopts_size = sizeof (md_longopts);
7748
7749int
9103f4f4 7750md_parse_option (int c, char *arg)
252b5132 7751{
9103f4f4 7752 unsigned int i;
6305a203 7753 char *arch, *next;
9103f4f4 7754
252b5132
RH		 7755 switch (c)
7756 {
12b55ccc
L		 7757 case 'n':
7758 optimize_align_code = 0;
7759 break;
7760
a38cf1db
AM		 7761 case 'q':
7762 quiet_warnings = 1;
252b5132
RH		 7763 break;
7764
7765#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7766 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7767 should be emitted or not. FIXME: Not implemented. */
7768 case 'Q':
252b5132
RH		 7769 break;
7770
7771 /* -V: SVR4 argument to print version ID. */
7772 case 'V':
7773 print_version_id ();
7774 break;
7775
a38cf1db
AM		 7776 /* -k: Ignore for FreeBSD compatibility. */
7777 case 'k':
252b5132 7778 break;
4cc782b5
ILT		 7779
7780 case 's':
7781 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7782 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7783 break;
99ad8390 7784#endif
321098a5
L		 7785#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7786 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7787 case OPTION_64:
7788 {
7789 const char **list, **l;
7790
3e73aa7c
JH		 7791 list = bfd_target_list ();
7792 for (l = list; *l != NULL; l++)
8620418b 7793 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7794 || strcmp (*l, "coff-x86-64") == 0
7795 || strcmp (*l, "pe-x86-64") == 0
7796 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7797 {
7798 default_arch = "x86_64";
7799 break;
7800 }
3e73aa7c 7801 if (*l == NULL)
6e0b89ee 7802 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7803 free (list);
7804 }
7805 break;
7806#endif
252b5132 7807
6e0b89ee
AM		 7808 case OPTION_32:
7809 default_arch = "i386";
7810 break;
7811
b3b91714
AM		 7812 case OPTION_DIVIDE:
7813#ifdef SVR4_COMMENT_CHARS
7814 {
7815 char *n, *t;
7816 const char *s;
7817
7818 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7819 t = n;
7820 for (s = i386_comment_chars; *s != '\0'; s++)
7821 if (*s != '/')
7822 *t++ = *s;
7823 *t = '\0';
7824 i386_comment_chars = n;
7825 }
7826#endif
7827 break;
7828
9103f4f4 7829 case OPTION_MARCH:
6305a203
L		 7830 arch = xstrdup (arg);
7831 do
9103f4f4 7832 {
6305a203
L		 7833 if (*arch == '.')
7834 as_fatal (_("Invalid -march= option: `%s'"), arg);
7835 next = strchr (arch, '+');
7836 if (next)
7837 *next++ = '\0';
7838 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7839 {
6305a203 7840 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7841 {
6305a203
L		 7842 /* Processor. */
7843 cpu_arch_name = cpu_arch[i].name;
7844 cpu_sub_arch_name = NULL;
7845 cpu_arch_flags = cpu_arch[i].flags;
7846 cpu_arch_isa = cpu_arch[i].type;
7847 cpu_arch_isa_flags = cpu_arch[i].flags;
7848 if (!cpu_arch_tune_set)
7849 {
7850 cpu_arch_tune = cpu_arch_isa;
7851 cpu_arch_tune_flags = cpu_arch_isa_flags;
7852 }
7853 break;
7854 }
7855 else if (*cpu_arch [i].name == '.'
7856 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7857 {
7858 /* ISA entension. */
7859 i386_cpu_flags flags;
309d3373
JB		 7860
7861 if (strncmp (arch, "no", 2))
7862 flags = cpu_flags_or (cpu_arch_flags,
7863 cpu_arch[i].flags);
7864 else
7865 flags = cpu_flags_and_not (cpu_arch_flags,
7866 cpu_arch[i].flags);
0dfbf9d7 7867 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7868 {
7869 if (cpu_sub_arch_name)
7870 {
7871 char *name = cpu_sub_arch_name;
7872 cpu_sub_arch_name = concat (name,
7873 cpu_arch[i].name,
1bf57e9f 7874 (const char *) NULL);
6305a203
L		 7875 free (name);
7876 }
7877 else
7878 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7879 cpu_arch_flags = flags;
7880 }
7881 break;
ccc9c027 7882 }
9103f4f4 7883 }
6305a203
L		 7884
7885 if (i >= ARRAY_SIZE (cpu_arch))
7886 as_fatal (_("Invalid -march= option: `%s'"), arg);
7887
7888 arch = next;
9103f4f4 7889 }
6305a203 7890 while (next != NULL );
9103f4f4
L		 7891 break;
7892
7893 case OPTION_MTUNE:
7894 if (*arg == '.')
7895 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7896 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7897 {
7898 if (strcmp (arg, cpu_arch [i].name) == 0)
7899 {
ccc9c027 7900 cpu_arch_tune_set = 1;
9103f4f4
L		 7901 cpu_arch_tune = cpu_arch [i].type;
7902 cpu_arch_tune_flags = cpu_arch[i].flags;
7903 break;
7904 }
7905 }
7906 if (i >= ARRAY_SIZE (cpu_arch))
7907 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7908 break;
7909
1efbbeb4
L		 7910 case OPTION_MMNEMONIC:
7911 if (strcasecmp (arg, "att") == 0)
7912 intel_mnemonic = 0;
7913 else if (strcasecmp (arg, "intel") == 0)
7914 intel_mnemonic = 1;
7915 else
7916 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7917 break;
7918
7919 case OPTION_MSYNTAX:
7920 if (strcasecmp (arg, "att") == 0)
7921 intel_syntax = 0;
7922 else if (strcasecmp (arg, "intel") == 0)
7923 intel_syntax = 1;
7924 else
7925 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7926 break;
7927
7928 case OPTION_MINDEX_REG:
7929 allow_index_reg = 1;
7930 break;
7931
7932 case OPTION_MNAKED_REG:
7933 allow_naked_reg = 1;
7934 break;
7935
7936 case OPTION_MOLD_GCC:
7937 old_gcc = 1;
1efbbeb4
L		 7938 break;
7939
c0f3af97
L		 7940 case OPTION_MSSE2AVX:
7941 sse2avx = 1;
7942 break;
7943
daf50ae7
L		 7944 case OPTION_MSSE_CHECK:
7945 if (strcasecmp (arg, "error") == 0)
7946 sse_check = sse_check_error;
7947 else if (strcasecmp (arg, "warning") == 0)
7948 sse_check = sse_check_warning;
7949 else if (strcasecmp (arg, "none") == 0)
7950 sse_check = sse_check_none;
7951 else
7952 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7953 break;
7954
252b5132
RH		 7955 default:
7956 return 0;
7957 }
7958 return 1;
7959}
7960
7961void
7962md_show_usage (stream)
7963 FILE *stream;
7964{
4cc782b5
ILT		 7965#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7966 fprintf (stream, _("\
a38cf1db
AM		 7967 -Q ignored\n\
7968 -V print assembler version number\n\
b3b91714
AM		 7969 -k ignored\n"));
7970#endif
7971 fprintf (stream, _("\
12b55ccc 7972 -n Do not optimize code alignment\n\
b3b91714
AM		 7973 -q quieten some warnings\n"));
7974#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7975 fprintf (stream, _("\
a38cf1db 7976 -s ignored\n"));
b3b91714 7977#endif
321098a5
L		 7978#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7979 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 7980 fprintf (stream, _("\
7981 --32/--64 generate 32bit/64bit code\n"));
7982#endif
b3b91714
AM		 7983#ifdef SVR4_COMMENT_CHARS
7984 fprintf (stream, _("\
7985 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7986#else
7987 fprintf (stream, _("\
b3b91714 7988 --divide ignored\n"));
4cc782b5 7989#endif
9103f4f4 7990 fprintf (stream, _("\
6305a203
L		 7991 -march=CPU[,+EXTENSION...]\n\
7992 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7993 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7994 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 7995 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
7996 amdfam10, generic32, generic64\n\
599121aa 7997 EXTENSION is combination of:\n\
309d3373
JB		 7998 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
7999 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8000 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 8001 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
922d8de8 8002 svme, abm, padlock, fma4\n"));
6305a203 8003 fprintf (stream, _("\
2cb4f3d5
L		 8004 -mtune=CPU optimize for CPU, CPU is one of:\n\
8005 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8006 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 8007 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8008 amdfam10, generic32, generic64\n"));
ba104c83 8009 fprintf (stream, _("\
c0f3af97
L		 8010 -msse2avx encode SSE instructions with VEX prefix\n"));
8011 fprintf (stream, _("\
daf50ae7
L		 8012 -msse-check=[none|error|warning]\n\
8013 check SSE instructions\n"));
8014 fprintf (stream, _("\
ba104c83
L		 8015 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8016 fprintf (stream, _("\
8017 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8018 fprintf (stream, _("\
8019 -mindex-reg support pseudo index registers\n"));
8020 fprintf (stream, _("\
8021 -mnaked-reg don't require `%%' prefix for registers\n"));
8022 fprintf (stream, _("\
8023 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8024}
8025
3e73aa7c 8026#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8027 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8028 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8029
8030/* Pick the target format to use. */
8031
47926f60 8032const char *
e3bb37b5 8033i386_target_format (void)
252b5132 8034{
3e73aa7c 8035 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8036 {
8037 set_code_flag (CODE_64BIT);
0dfbf9d7 8038 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8039 {
8040 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8041 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8042 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8043 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8044 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8045 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8046 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8047 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8048 cpu_arch_isa_flags.bitfield.cpusse = 1;
8049 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8050 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8051 }
0dfbf9d7 8052 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8053 {
8054 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8055 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8056 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8057 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8058 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8059 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8060 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8061 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8062 cpu_arch_tune_flags.bitfield.cpusse = 1;
8063 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8064 }
9103f4f4 8065 }
3e73aa7c 8066 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8067 {
8068 set_code_flag (CODE_32BIT);
0dfbf9d7 8069 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8070 {
8071 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8072 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8073 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8074 }
0dfbf9d7 8075 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8076 {
8077 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8078 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8079 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8080 }
9103f4f4 8081 }
3e73aa7c
JH		 8082 else
8083 as_fatal (_("Unknown architecture"));
252b5132
RH		 8084 switch (OUTPUT_FLAVOR)
8085 {
321098a5 8086#if defined (TE_PE) || defined (TE_PEP)
872ce6ff 8087 case bfd_target_coff_flavour:
321098a5 8088 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
872ce6ff 8089#endif
4c63da97
AM		 8090#ifdef OBJ_MAYBE_AOUT
8091 case bfd_target_aout_flavour:
47926f60 8092 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8093#endif
8094#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8095 case bfd_target_coff_flavour:
8096 return "coff-i386";
4c63da97 8097#endif
3e73aa7c 8098#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8099 case bfd_target_elf_flavour:
3e73aa7c 8100 {
e5cb08ac 8101 if (flag_code == CODE_64BIT)
4fa24527
JB		 8102 {
8103 object_64bit = 1;
8104 use_rela_relocations = 1;
8105 }
8a9036a4
L		 8106 if (cpu_arch_isa_flags.bitfield.cpul1om)
8107 {
8108 if (flag_code != CODE_64BIT)
8109 as_fatal (_("Intel L1OM is 64bit only"));
8110 return ELF_TARGET_L1OM_FORMAT;
8111 }
8112 else
8113 return (flag_code == CODE_64BIT
8114 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8115 }
e57f8c65
TG		 8116#endif
8117#if defined (OBJ_MACH_O)
8118 case bfd_target_mach_o_flavour:
8119 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8120#endif
252b5132
RH		 8121 default:
8122 abort ();
8123 return NULL;
8124 }
8125}
8126
47926f60 8127#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8128
8129#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8130void
8131i386_elf_emit_arch_note (void)
a847613f 8132{
718ddfc0 8133 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8134 {
8135 char *p;
8136 asection *seg = now_seg;
8137 subsegT subseg = now_subseg;
8138 Elf_Internal_Note i_note;
8139 Elf_External_Note e_note;
8140 asection *note_secp;
8141 int len;
8142
8143 /* Create the .note section. */
8144 note_secp = subseg_new (".note", 0);
8145 bfd_set_section_flags (stdoutput,
8146 note_secp,
8147 SEC_HAS_CONTENTS | SEC_READONLY);
8148
8149 /* Process the arch string. */
8150 len = strlen (cpu_arch_name);
8151
8152 i_note.namesz = len + 1;
8153 i_note.descsz = 0;
8154 i_note.type = NT_ARCH;
8155 p = frag_more (sizeof (e_note.namesz));
8156 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8157 p = frag_more (sizeof (e_note.descsz));
8158 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8159 p = frag_more (sizeof (e_note.type));
8160 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8161 p = frag_more (len + 1);
8162 strcpy (p, cpu_arch_name);
8163
8164 frag_align (2, 0, 0);
8165
8166 subseg_set (seg, subseg);
8167 }
8168}
8169#endif
252b5132 8170\f
252b5132
RH		 8171symbolS *
8172md_undefined_symbol (name)
8173 char *name;
8174{
18dc2407
ILT		 8175 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8176 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8177 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8178 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8179 {
8180 if (!GOT_symbol)
8181 {
8182 if (symbol_find (name))
8183 as_bad (_("GOT already in symbol table"));
8184 GOT_symbol = symbol_new (name, undefined_section,
8185 (valueT) 0, &zero_address_frag);
8186 };
8187 return GOT_symbol;
8188 }
252b5132
RH		 8189 return 0;
8190}
8191
8192/* Round up a section size to the appropriate boundary. */
47926f60 8193
252b5132
RH		 8194valueT
8195md_section_align (segment, size)
ab9da554 8196 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8197 valueT size;
8198{
4c63da97
AM		 8199#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8200 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8201 {
8202 /* For a.out, force the section size to be aligned. If we don't do
8203 this, BFD will align it for us, but it will not write out the
8204 final bytes of the section. This may be a bug in BFD, but it is
8205 easier to fix it here since that is how the other a.out targets
8206 work. */
8207 int align;
8208
8209 align = bfd_get_section_alignment (stdoutput, segment);
8210 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8211 }
252b5132
RH		 8212#endif
8213
8214 return size;
8215}
8216
8217/* On the i386, PC-relative offsets are relative to the start of the
8218 next instruction. That is, the address of the offset, plus its
8219 size, since the offset is always the last part of the insn. */
8220
8221long
e3bb37b5 8222md_pcrel_from (fixS *fixP)
252b5132
RH		 8223{
8224 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8225}
8226
8227#ifndef I386COFF
8228
8229static void
e3bb37b5 8230s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8231{
29b0f896 8232 int temp;
252b5132 8233
8a75718c
JB		 8234#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8235 if (IS_ELF)
8236 obj_elf_section_change_hook ();
8237#endif
252b5132
RH		 8238 temp = get_absolute_expression ();
8239 subseg_set (bss_section, (subsegT) temp);
8240 demand_empty_rest_of_line ();
8241}
8242
8243#endif
8244
252b5132 8245void
e3bb37b5 8246i386_validate_fix (fixS *fixp)
252b5132
RH		 8247{
8248 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8249 {
23df1078
JH		 8250 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8251 {
4fa24527 8252 if (!object_64bit)
23df1078
JH		 8253 abort ();
8254 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8255 }
8256 else
8257 {
4fa24527 8258 if (!object_64bit)
d6ab8113
JB		 8259 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8260 else
8261 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8262 }
252b5132
RH		 8263 fixp->fx_subsy = 0;
8264 }
8265}
8266
252b5132
RH		 8267arelent *
8268tc_gen_reloc (section, fixp)
ab9da554 8269 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8270 fixS *fixp;
8271{
8272 arelent *rel;
8273 bfd_reloc_code_real_type code;
8274
8275 switch (fixp->fx_r_type)
8276 {
3e73aa7c
JH		 8277 case BFD_RELOC_X86_64_PLT32:
8278 case BFD_RELOC_X86_64_GOT32:
8279 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8280 case BFD_RELOC_386_PLT32:
8281 case BFD_RELOC_386_GOT32:
8282 case BFD_RELOC_386_GOTOFF:
8283 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8284 case BFD_RELOC_386_TLS_GD:
8285 case BFD_RELOC_386_TLS_LDM:
8286 case BFD_RELOC_386_TLS_LDO_32:
8287 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8288 case BFD_RELOC_386_TLS_IE:
8289 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8290 case BFD_RELOC_386_TLS_LE_32:
8291 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8292 case BFD_RELOC_386_TLS_GOTDESC:
8293 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8294 case BFD_RELOC_X86_64_TLSGD:
8295 case BFD_RELOC_X86_64_TLSLD:
8296 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8297 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8298 case BFD_RELOC_X86_64_GOTTPOFF:
8299 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8300 case BFD_RELOC_X86_64_TPOFF64:
8301 case BFD_RELOC_X86_64_GOTOFF64:
8302 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8303 case BFD_RELOC_X86_64_GOT64:
8304 case BFD_RELOC_X86_64_GOTPCREL64:
8305 case BFD_RELOC_X86_64_GOTPC64:
8306 case BFD_RELOC_X86_64_GOTPLT64:
8307 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8308 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8309 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8310 case BFD_RELOC_RVA:
8311 case BFD_RELOC_VTABLE_ENTRY:
8312 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8313#ifdef TE_PE
8314 case BFD_RELOC_32_SECREL:
8315#endif
252b5132
RH		 8316 code = fixp->fx_r_type;
8317 break;
dbbaec26
L		 8318 case BFD_RELOC_X86_64_32S:
8319 if (!fixp->fx_pcrel)
8320 {
8321 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8322 code = fixp->fx_r_type;
8323 break;
8324 }
252b5132 8325 default:
93382f6d 8326 if (fixp->fx_pcrel)
252b5132 8327 {
93382f6d
AM		 8328 switch (fixp->fx_size)
8329 {
8330 default:
b091f402
AM		 8331 as_bad_where (fixp->fx_file, fixp->fx_line,
8332 _("can not do %d byte pc-relative relocation"),
8333 fixp->fx_size);
93382f6d
AM		 8334 code = BFD_RELOC_32_PCREL;
8335 break;
8336 case 1: code = BFD_RELOC_8_PCREL; break;
8337 case 2: code = BFD_RELOC_16_PCREL; break;
8338 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8339#ifdef BFD64
8340 case 8: code = BFD_RELOC_64_PCREL; break;
8341#endif
93382f6d
AM		 8342 }
8343 }
8344 else
8345 {
8346 switch (fixp->fx_size)
8347 {
8348 default:
b091f402
AM		 8349 as_bad_where (fixp->fx_file, fixp->fx_line,
8350 _("can not do %d byte relocation"),
8351 fixp->fx_size);
93382f6d
AM		 8352 code = BFD_RELOC_32;
8353 break;
8354 case 1: code = BFD_RELOC_8; break;
8355 case 2: code = BFD_RELOC_16; break;
8356 case 4: code = BFD_RELOC_32; break;
937149dd 8357#ifdef BFD64
3e73aa7c 8358 case 8: code = BFD_RELOC_64; break;
937149dd 8359#endif
93382f6d 8360 }
252b5132
RH		 8361 }
8362 break;
8363 }
252b5132 8364
d182319b
JB		 8365 if ((code == BFD_RELOC_32
8366 || code == BFD_RELOC_32_PCREL
8367 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8368 && GOT_symbol
8369 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8370 {
4fa24527 8371 if (!object_64bit)
d6ab8113
JB		 8372 code = BFD_RELOC_386_GOTPC;
8373 else
8374 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8375 }
7b81dfbb
AJ		 8376 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8377 && GOT_symbol
8378 && fixp->fx_addsy == GOT_symbol)
8379 {
8380 code = BFD_RELOC_X86_64_GOTPC64;
8381 }
252b5132
RH		 8382
8383 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8384 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8385 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8386
8387 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8388
3e73aa7c
JH		 8389 if (!use_rela_relocations)
8390 {
8391 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8392 vtable entry to be used in the relocation's section offset. */
8393 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8394 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8395#if defined (OBJ_COFF) && defined (TE_PE)
8396 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8397 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8398 else
8399#endif
c6682705 8400 rel->addend = 0;
3e73aa7c
JH		 8401 }
8402 /* Use the rela in 64bit mode. */
252b5132 8403 else
3e73aa7c 8404 {
062cd5e7
AS		 8405 if (!fixp->fx_pcrel)
8406 rel->addend = fixp->fx_offset;
8407 else
8408 switch (code)
8409 {
8410 case BFD_RELOC_X86_64_PLT32:
8411 case BFD_RELOC_X86_64_GOT32:
8412 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8413 case BFD_RELOC_X86_64_TLSGD:
8414 case BFD_RELOC_X86_64_TLSLD:
8415 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8416 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8417 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8418 rel->addend = fixp->fx_offset - fixp->fx_size;
8419 break;
8420 default:
8421 rel->addend = (section->vma
8422 - fixp->fx_size
8423 + fixp->fx_addnumber
8424 + md_pcrel_from (fixp));
8425 break;
8426 }
3e73aa7c
JH		 8427 }
8428
252b5132
RH		 8429 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8430 if (rel->howto == NULL)
8431 {
8432 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8433 _("cannot represent relocation type %s"),
252b5132
RH		 8434 bfd_get_reloc_code_name (code));
8435 /* Set howto to a garbage value so that we can keep going. */
8436 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8437 gas_assert (rel->howto != NULL);
252b5132
RH		 8438 }
8439
8440 return rel;
8441}
8442
ee86248c 8443#include "tc-i386-intel.c"
54cfded0 8444
a60de03c
JB		 8445void
8446tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8447{
a60de03c
JB		 8448 int saved_naked_reg;
8449 char saved_register_dot;
54cfded0 8450
a60de03c
JB		 8451 saved_naked_reg = allow_naked_reg;
8452 allow_naked_reg = 1;
8453 saved_register_dot = register_chars['.'];
8454 register_chars['.'] = '.';
8455 allow_pseudo_reg = 1;
8456 expression_and_evaluate (exp);
8457 allow_pseudo_reg = 0;
8458 register_chars['.'] = saved_register_dot;
8459 allow_naked_reg = saved_naked_reg;
8460
8461 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8462 {
a60de03c
JB		 8463 if ((addressT) exp->X_add_number < i386_regtab_size)
8464 {
8465 exp->X_op = O_constant;
8466 exp->X_add_number = i386_regtab[exp->X_add_number]
8467 .dw2_regnum[flag_code >> 1];
8468 }
8469 else
8470 exp->X_op = O_illegal;
54cfded0 8471 }
54cfded0
AM		 8472}
8473
8474void
8475tc_x86_frame_initial_instructions (void)
8476{
a60de03c
JB		 8477 static unsigned int sp_regno[2];
8478
8479 if (!sp_regno[flag_code >> 1])
8480 {
8481 char *saved_input = input_line_pointer;
8482 char sp[][4] = {"esp", "rsp"};
8483 expressionS exp;
a4447b93 8484
a60de03c
JB		 8485 input_line_pointer = sp[flag_code >> 1];
8486 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8487 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8488 sp_regno[flag_code >> 1] = exp.X_add_number;
8489 input_line_pointer = saved_input;
8490 }
a4447b93 8491
a60de03c 8492 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8493 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8494}
d2b2c203
DJ		 8495
8496int
8497i386_elf_section_type (const char *str, size_t len)
8498{
8499 if (flag_code == CODE_64BIT
8500 && len == sizeof ("unwind") - 1
8501 && strncmp (str, "unwind", 6) == 0)
8502 return SHT_X86_64_UNWIND;
8503
8504 return -1;
8505}
bb41ade5 8506
ad5fec3b
EB		 8507#ifdef TE_SOLARIS
8508void
8509i386_solaris_fix_up_eh_frame (segT sec)
8510{
8511 if (flag_code == CODE_64BIT)
8512 elf_section_type (sec) = SHT_X86_64_UNWIND;
8513}
8514#endif
8515
bb41ade5
AM		 8516#ifdef TE_PE
8517void
8518tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8519{
8520 expressionS expr;
8521
8522 expr.X_op = O_secrel;
8523 expr.X_add_symbol = symbol;
8524 expr.X_add_number = 0;
8525 emit_expr (&expr, size);
8526}
8527#endif
3b22753a
L		 8528
8529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8530/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8531
01e1a5bc 8532bfd_vma
3b22753a
L		 8533x86_64_section_letter (int letter, char **ptr_msg)
8534{
8535 if (flag_code == CODE_64BIT)
8536 {
8537 if (letter == 'l')
8538 return SHF_X86_64_LARGE;
8539
8540 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8541 }
3b22753a 8542 else
64e74474 8543 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8544 return -1;
8545}
8546
01e1a5bc 8547bfd_vma
3b22753a
L		 8548x86_64_section_word (char *str, size_t len)
8549{
8620418b 8550 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8551 return SHF_X86_64_LARGE;
8552
8553 return -1;
8554}
8555
8556static void
8557handle_large_common (int small ATTRIBUTE_UNUSED)
8558{
8559 if (flag_code != CODE_64BIT)
8560 {
8561 s_comm_internal (0, elf_common_parse);
8562 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8563 }
8564 else
8565 {
8566 static segT lbss_section;
8567 asection *saved_com_section_ptr = elf_com_section_ptr;
8568 asection *saved_bss_section = bss_section;
8569
8570 if (lbss_section == NULL)
8571 {
8572 flagword applicable;
8573 segT seg = now_seg;
8574 subsegT subseg = now_subseg;
8575
8576 /* The .lbss section is for local .largecomm symbols. */
8577 lbss_section = subseg_new (".lbss", 0);
8578 applicable = bfd_applicable_section_flags (stdoutput);
8579 bfd_set_section_flags (stdoutput, lbss_section,
8580 applicable & SEC_ALLOC);
8581 seg_info (lbss_section)->bss = 1;
8582
8583 subseg_set (seg, subseg);
8584 }
8585
8586 elf_com_section_ptr = &_bfd_elf_large_com_section;
8587 bss_section = lbss_section;
8588
8589 s_comm_internal (0, elf_common_parse);
8590
8591 elf_com_section_ptr = saved_com_section_ptr;
8592 bss_section = saved_bss_section;
8593 }
8594}
8595#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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