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S/390: ifunc: Redirect local function calls to the IPLT.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
8dcea932
L		 521#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522/* 1 if generating code for a shared library. */
523static int shared = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
7bab8ab5 555static enum check_kind
daf50ae7 556 {
7bab8ab5
JB		 557 check_none = 0,
558 check_warning,
559 check_error
daf50ae7 560 }
7bab8ab5 561sse_check, operand_check = check_warning;
daf50ae7 562
2ca3ace5
L		 563/* Register prefix used for error message. */
564static const char *register_prefix = "%";
565
47926f60
KH		 566/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569static char stackop_size = '\0';
eecb386c 570
12b55ccc
L		 571/* Non-zero to optimize code alignment. */
572int optimize_align_code = 1;
573
47926f60
KH		 574/* Non-zero to quieten some warnings. */
575static int quiet_warnings = 0;
a38cf1db 576
47926f60
KH		 577/* CPU name. */
578static const char *cpu_arch_name = NULL;
6305a203 579static char *cpu_sub_arch_name = NULL;
a38cf1db 580
47926f60 581/* CPU feature flags. */
40fb9820
L		 582static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
583
ccc9c027
L		 584/* If we have selected a cpu we are generating instructions for. */
585static int cpu_arch_tune_set = 0;
586
9103f4f4 587/* Cpu we are generating instructions for. */
fbf3f584 588enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 589
590/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 591static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 592
ccc9c027 593/* CPU instruction set architecture used. */
fbf3f584 594enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 595
9103f4f4 596/* CPU feature flags of instruction set architecture used. */
fbf3f584 597i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 598
fddf5b5b
AM		 599/* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601static unsigned int no_cond_jump_promotion = 0;
602
c0f3af97
L		 603/* Encode SSE instructions with VEX prefix. */
604static unsigned int sse2avx;
605
539f890d
L		 606/* Encode scalar AVX instructions with specific vector length. */
607static enum
608 {
609 vex128 = 0,
610 vex256
611 } avxscalar;
612
43234a1e
L		 613/* Encode scalar EVEX LIG instructions with specific vector length. */
614static enum
615 {
616 evexl128 = 0,
617 evexl256,
618 evexl512
619 } evexlig;
620
621/* Encode EVEX WIG instructions with specific evex.w. */
622static enum
623 {
624 evexw0 = 0,
625 evexw1
626 } evexwig;
627
d3d3c6db
IT		 628/* Value to encode in EVEX RC bits, for SAE-only instructions. */
629static enum rc_type evexrcig = rne;
630
29b0f896 631/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 632static symbolS *GOT_symbol;
29b0f896 633
a4447b93
RH		 634/* The dwarf2 return column, adjusted for 32 or 64 bit. */
635unsigned int x86_dwarf2_return_column;
636
637/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638int x86_cie_data_alignment;
639
252b5132 640/* Interface to relax_segment.
fddf5b5b
AM		 641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
252b5132 644
47926f60 645/* Types. */
93c2a809
AM		 646#define UNCOND_JUMP 0
647#define COND_JUMP 1
648#define COND_JUMP86 2
fddf5b5b 649
47926f60 650/* Sizes. */
252b5132
RH		 651#define CODE16 1
652#define SMALL 0
29b0f896 653#define SMALL16 (SMALL | CODE16)
252b5132 654#define BIG 2
29b0f896 655#define BIG16 (BIG | CODE16)
252b5132
RH		 656
657#ifndef INLINE
658#ifdef __GNUC__
659#define INLINE __inline__
660#else
661#define INLINE
662#endif
663#endif
664
fddf5b5b
AM		 665#define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667#define TYPE_FROM_RELAX_STATE(s) \
668 ((s) >> 2)
669#define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 671
672/* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
679
680const relax_typeS md_relax_table[] =
681{
24eab124
AM		 682 /* The fields are:
683 1) most positive reach of this state,
684 2) most negative reach of this state,
93c2a809 685 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 686 4) which index into the table to try if we can't fit into this one. */
252b5132 687
fddf5b5b 688 /* UNCOND_JUMP states. */
93c2a809
AM		 689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
252b5132 693 {0, 0, 4, 0},
93c2a809
AM		 694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 696 {0, 0, 2, 0},
697
93c2a809
AM		 698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
703 {0, 0, 5, 0},
fddf5b5b 704 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 705 1 extra opcode byte, 2 displacement bytes. */
706 {0, 0, 3, 0},
707
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
713 {0, 0, 5, 0},
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
716 {0, 0, 4, 0}
252b5132
RH		 717};
718
9103f4f4
L		 719static const arch_entry cpu_arch[] =
720{
89507696
JB		 721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
8a2c8fef 723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 724 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 726 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 728 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 730 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 732 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 734 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 736 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 738 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 740 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 742 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 748 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 750 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 752 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 754 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 756 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 760 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 762 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 764 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 766 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
770 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 772 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 774 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 776 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 778 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 780 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 782 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 784 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 786 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 788 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
790 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
792 CPU_BDVER4_FLAGS, 0, 0 },
029f3522 793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
3739860c 794 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
796 CPU_BTVER1_FLAGS, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
798 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 800 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 802 CPU_287_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 804 CPU_387_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 806 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 808 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 814 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 816 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 824 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 826 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
830 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
832 CPU_AVX512F_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
834 CPU_AVX512CD_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
836 CPU_AVX512ER_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
838 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
840 CPU_AVX512DQ_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
842 CPU_AVX512BW_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
844 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 846 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 848 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
850 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 852 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 856 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
858 CPU_XSAVEC_FLAGS, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
860 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 862 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 864 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 866 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 868 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 870 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 872 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
874 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 876 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 878 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 880 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 882 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 884 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
886 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 888 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
890 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
892 CPU_HLE_FLAGS, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
894 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
896 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 898 CPU_CLFLUSH_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
900 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 902 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 904 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 906 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 908 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 910 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 912 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 914 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 916 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 918 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
920 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
922 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
924 CPU_ADX_FLAGS, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
926 CPU_RDSEED_FLAGS, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
928 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
930 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
932 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
934 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
936 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
938 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
940 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
942 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
944 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
946 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
948 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
950 CPU_CLZERO_FLAGS, 0, 0 },
9916071f
AP		 951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
952 CPU_MWAITX_FLAGS, 0, 0 },
e413e4e9
AM		 953};
954
704209c0 955#ifdef I386COFF
a6c24e68
NC		 956/* Like s_lcomm_internal in gas/read.c but the alignment string
957 is allowed to be optional. */
958
959static symbolS *
960pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
961{
962 addressT align = 0;
963
964 SKIP_WHITESPACE ();
965
7ab9ffdd 966 if (needs_align
a6c24e68
NC		 967 && *input_line_pointer == ',')
968 {
969 align = parse_align (needs_align - 1);
7ab9ffdd 970
a6c24e68
NC		 971 if (align == (addressT) -1)
972 return NULL;
973 }
974 else
975 {
976 if (size >= 8)
977 align = 3;
978 else if (size >= 4)
979 align = 2;
980 else if (size >= 2)
981 align = 1;
982 else
983 align = 0;
984 }
985
986 bss_alloc (symbolP, size, align);
987 return symbolP;
988}
989
704209c0 990static void
a6c24e68
NC		 991pe_lcomm (int needs_align)
992{
993 s_comm_internal (needs_align * 2, pe_lcomm_internal);
994}
704209c0 995#endif
a6c24e68 996
29b0f896
AM		 997const pseudo_typeS md_pseudo_table[] =
998{
999#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1000 {"align", s_align_bytes, 0},
1001#else
1002 {"align", s_align_ptwo, 0},
1003#endif
1004 {"arch", set_cpu_arch, 0},
1005#ifndef I386COFF
1006 {"bss", s_bss, 0},
a6c24e68
NC		 1007#else
1008 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1009#endif
1010 {"ffloat", float_cons, 'f'},
1011 {"dfloat", float_cons, 'd'},
1012 {"tfloat", float_cons, 'x'},
1013 {"value", cons, 2},
d182319b 1014 {"slong", signed_cons, 4},
29b0f896
AM		 1015 {"noopt", s_ignore, 0},
1016 {"optim", s_ignore, 0},
1017 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1018 {"code16", set_code_flag, CODE_16BIT},
1019 {"code32", set_code_flag, CODE_32BIT},
1020 {"code64", set_code_flag, CODE_64BIT},
1021 {"intel_syntax", set_intel_syntax, 1},
1022 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1023 {"intel_mnemonic", set_intel_mnemonic, 1},
1024 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1025 {"allow_index_reg", set_allow_index_reg, 1},
1026 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1027 {"sse_check", set_check, 0},
1028 {"operand_check", set_check, 1},
3b22753a
L		 1029#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1030 {"largecomm", handle_large_common, 0},
07a53e5c 1031#else
e3bb37b5 1032 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1033 {"loc", dwarf2_directive_loc, 0},
1034 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1035#endif
6482c264
NC		 1036#ifdef TE_PE
1037 {"secrel32", pe_directive_secrel, 0},
1038#endif
29b0f896
AM		 1039 {0, 0, 0}
1040};
1041
1042/* For interface with expression (). */
1043extern char *input_line_pointer;
1044
1045/* Hash table for instruction mnemonic lookup. */
1046static struct hash_control *op_hash;
1047
1048/* Hash table for register lookup. */
1049static struct hash_control *reg_hash;
1050\f
252b5132 1051void
e3bb37b5 1052i386_align_code (fragS *fragP, int count)
252b5132 1053{
ce8a8b2f
AM		 1054 /* Various efficient no-op patterns for aligning code labels.
1055 Note: Don't try to assemble the instructions in the comments.
1056 0L and 0w are not legal. */
252b5132
RH		 1057 static const char f32_1[] =
1058 {0x90}; /* nop */
1059 static const char f32_2[] =
ccc9c027 1060 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1061 static const char f32_3[] =
1062 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1063 static const char f32_4[] =
1064 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_5[] =
1066 {0x90, /* nop */
1067 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1068 static const char f32_6[] =
1069 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1070 static const char f32_7[] =
1071 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_8[] =
1073 {0x90, /* nop */
1074 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1075 static const char f32_9[] =
1076 {0x89,0xf6, /* movl %esi,%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_10[] =
1079 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_11[] =
1082 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_12[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1087 static const char f32_13[] =
1088 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_14[] =
1091 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1092 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1093 static const char f16_3[] =
1094 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1095 static const char f16_4[] =
1096 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_5[] =
1098 {0x90, /* nop */
1099 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1100 static const char f16_6[] =
1101 {0x89,0xf6, /* mov %si,%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_7[] =
1104 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1106 static const char f16_8[] =
1107 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1109 static const char jump_31[] =
1110 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1111 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1112 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1114 static const char *const f32_patt[] = {
1115 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1116 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1117 };
1118 static const char *const f16_patt[] = {
76bc74dc 1119 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1120 };
ccc9c027
L		 1121 /* nopl (%[re]ax) */
1122 static const char alt_3[] =
1123 {0x0f,0x1f,0x00};
1124 /* nopl 0(%[re]ax) */
1125 static const char alt_4[] =
1126 {0x0f,0x1f,0x40,0x00};
1127 /* nopl 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_5[] =
1129 {0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopw 0(%[re]ax,%[re]ax,1) */
1131 static const char alt_6[] =
1132 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1133 /* nopl 0L(%[re]ax) */
1134 static const char alt_7[] =
1135 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1136 /* nopl 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_8[] =
1138 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw 0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_9[] =
1141 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_10[] =
1144 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1145 static const char *const alt_patt[] = {
ccc9c027 1146 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1147 alt_9, alt_10
ccc9c027 1148 };
252b5132 1149
76bc74dc
L		 1150 /* Only align for at least a positive non-zero boundary. */
1151 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1152 return;
3e73aa7c 1153
ccc9c027
L		 1154 /* We need to decide which NOP sequence to use for 32bit and
1155 64bit. When -mtune= is used:
4eed87de 1156
76bc74dc
L		 1157 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1158 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1159 2. For the rest, alt_patt will be used.
1160
1161 When -mtune= isn't used, alt_patt will be used if
22109423 1162 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1163 be used.
ccc9c027
L		 1164
1165 When -march= or .arch is used, we can't use anything beyond
1166 cpu_arch_isa_flags. */
1167
1168 if (flag_code == CODE_16BIT)
1169 {
ccc9c027 1170 if (count > 8)
33fef721 1171 {
76bc74dc
L		 1172 memcpy (fragP->fr_literal + fragP->fr_fix,
1173 jump_31, count);
1174 /* Adjust jump offset. */
1175 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1176 }
76bc74dc
L		 1177 else
1178 memcpy (fragP->fr_literal + fragP->fr_fix,
1179 f16_patt[count - 1], count);
252b5132 1180 }
33fef721 1181 else
ccc9c027
L		 1182 {
1183 const char *const *patt = NULL;
1184
fbf3f584 1185 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1186 {
1187 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1188 switch (cpu_arch_tune)
1189 {
1190 case PROCESSOR_UNKNOWN:
1191 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1192 optimize with nops. */
1193 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1194 patt = alt_patt;
ccc9c027
L		 1195 else
1196 patt = f32_patt;
1197 break;
ccc9c027
L		 1198 case PROCESSOR_PENTIUM4:
1199 case PROCESSOR_NOCONA:
ef05d495 1200 case PROCESSOR_CORE:
76bc74dc 1201 case PROCESSOR_CORE2:
bd5295b2 1202 case PROCESSOR_COREI7:
3632d14b 1203 case PROCESSOR_L1OM:
7a9068fe 1204 case PROCESSOR_K1OM:
76bc74dc 1205 case PROCESSOR_GENERIC64:
ccc9c027
L		 1206 case PROCESSOR_K6:
1207 case PROCESSOR_ATHLON:
1208 case PROCESSOR_K8:
4eed87de 1209 case PROCESSOR_AMDFAM10:
8aedb9fe 1210 case PROCESSOR_BD:
029f3522 1211 case PROCESSOR_ZNVER:
7b458c12 1212 case PROCESSOR_BT:
80b8656c 1213 patt = alt_patt;
ccc9c027 1214 break;
76bc74dc 1215 case PROCESSOR_I386:
ccc9c027
L		 1216 case PROCESSOR_I486:
1217 case PROCESSOR_PENTIUM:
2dde1948 1218 case PROCESSOR_PENTIUMPRO:
81486035 1219 case PROCESSOR_IAMCU:
ccc9c027
L		 1220 case PROCESSOR_GENERIC32:
1221 patt = f32_patt;
1222 break;
4eed87de 1223 }
ccc9c027
L		 1224 }
1225 else
1226 {
fbf3f584 1227 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1228 {
1229 case PROCESSOR_UNKNOWN:
e6a14101 1230 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1231 PROCESSOR_UNKNOWN. */
1232 abort ();
1233 break;
1234
76bc74dc 1235 case PROCESSOR_I386:
ccc9c027
L		 1236 case PROCESSOR_I486:
1237 case PROCESSOR_PENTIUM:
81486035 1238 case PROCESSOR_IAMCU:
ccc9c027
L		 1239 case PROCESSOR_K6:
1240 case PROCESSOR_ATHLON:
1241 case PROCESSOR_K8:
4eed87de 1242 case PROCESSOR_AMDFAM10:
8aedb9fe 1243 case PROCESSOR_BD:
029f3522 1244 case PROCESSOR_ZNVER:
7b458c12 1245 case PROCESSOR_BT:
ccc9c027
L		 1246 case PROCESSOR_GENERIC32:
1247 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1248 with nops. */
1249 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1250 patt = alt_patt;
ccc9c027
L		 1251 else
1252 patt = f32_patt;
1253 break;
76bc74dc
L		 1254 case PROCESSOR_PENTIUMPRO:
1255 case PROCESSOR_PENTIUM4:
1256 case PROCESSOR_NOCONA:
1257 case PROCESSOR_CORE:
ef05d495 1258 case PROCESSOR_CORE2:
bd5295b2 1259 case PROCESSOR_COREI7:
3632d14b 1260 case PROCESSOR_L1OM:
7a9068fe 1261 case PROCESSOR_K1OM:
22109423 1262 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1263 patt = alt_patt;
ccc9c027
L		 1264 else
1265 patt = f32_patt;
1266 break;
1267 case PROCESSOR_GENERIC64:
80b8656c 1268 patt = alt_patt;
ccc9c027 1269 break;
4eed87de 1270 }
ccc9c027
L		 1271 }
1272
76bc74dc
L		 1273 if (patt == f32_patt)
1274 {
1275 /* If the padding is less than 15 bytes, we use the normal
1276 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1277 its offset. */
1278 int limit;
76ba9986 1279
711eedef
L		 1280 /* For 64bit, the limit is 3 bytes. */
1281 if (flag_code == CODE_64BIT
1282 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1283 limit = 3;
1284 else
1285 limit = 15;
1286 if (count < limit)
76bc74dc
L		 1287 memcpy (fragP->fr_literal + fragP->fr_fix,
1288 patt[count - 1], count);
1289 else
1290 {
1291 memcpy (fragP->fr_literal + fragP->fr_fix,
1292 jump_31, count);
1293 /* Adjust jump offset. */
1294 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1295 }
1296 }
1297 else
1298 {
80b8656c
L		 1299 /* Maximum length of an instruction is 10 byte. If the
1300 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1301 we have to break it into smaller pieces. */
1302 int padding = count;
80b8656c 1303 while (padding > 10)
76bc74dc 1304 {
80b8656c 1305 padding -= 10;
76bc74dc 1306 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1307 patt [9], 10);
76bc74dc
L		 1308 }
1309
1310 if (padding)
1311 memcpy (fragP->fr_literal + fragP->fr_fix,
1312 patt [padding - 1], padding);
1313 }
ccc9c027 1314 }
33fef721 1315 fragP->fr_var = count;
252b5132
RH		 1316}
1317
c6fb90c8 1318static INLINE int
0dfbf9d7 1319operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1320{
0dfbf9d7 1321 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1322 {
1323 case 3:
0dfbf9d7 1324 if (x->array[2])
c6fb90c8
L		 1325 return 0;
1326 case 2:
0dfbf9d7 1327 if (x->array[1])
c6fb90c8
L		 1328 return 0;
1329 case 1:
0dfbf9d7 1330 return !x->array[0];
c6fb90c8
L		 1331 default:
1332 abort ();
1333 }
40fb9820
L		 1334}
1335
c6fb90c8 1336static INLINE void
0dfbf9d7 1337operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1338{
0dfbf9d7 1339 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1340 {
1341 case 3:
0dfbf9d7 1342 x->array[2] = v;
c6fb90c8 1343 case 2:
0dfbf9d7 1344 x->array[1] = v;
c6fb90c8 1345 case 1:
0dfbf9d7 1346 x->array[0] = v;
c6fb90c8
L		 1347 break;
1348 default:
1349 abort ();
1350 }
1351}
40fb9820 1352
c6fb90c8 1353static INLINE int
0dfbf9d7
L		 1354operand_type_equal (const union i386_operand_type *x,
1355 const union i386_operand_type *y)
c6fb90c8 1356{
0dfbf9d7 1357 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1358 {
1359 case 3:
0dfbf9d7 1360 if (x->array[2] != y->array[2])
c6fb90c8
L		 1361 return 0;
1362 case 2:
0dfbf9d7 1363 if (x->array[1] != y->array[1])
c6fb90c8
L		 1364 return 0;
1365 case 1:
0dfbf9d7 1366 return x->array[0] == y->array[0];
c6fb90c8
L		 1367 break;
1368 default:
1369 abort ();
1370 }
1371}
40fb9820 1372
0dfbf9d7
L		 1373static INLINE int
1374cpu_flags_all_zero (const union i386_cpu_flags *x)
1375{
1376 switch (ARRAY_SIZE(x->array))
1377 {
1378 case 3:
1379 if (x->array[2])
1380 return 0;
1381 case 2:
1382 if (x->array[1])
1383 return 0;
1384 case 1:
1385 return !x->array[0];
1386 default:
1387 abort ();
1388 }
1389}
1390
0dfbf9d7
L		 1391static INLINE int
1392cpu_flags_equal (const union i386_cpu_flags *x,
1393 const union i386_cpu_flags *y)
1394{
1395 switch (ARRAY_SIZE(x->array))
1396 {
1397 case 3:
1398 if (x->array[2] != y->array[2])
1399 return 0;
1400 case 2:
1401 if (x->array[1] != y->array[1])
1402 return 0;
1403 case 1:
1404 return x->array[0] == y->array[0];
1405 break;
1406 default:
1407 abort ();
1408 }
1409}
c6fb90c8
L		 1410
1411static INLINE int
1412cpu_flags_check_cpu64 (i386_cpu_flags f)
1413{
1414 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1415 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1416}
1417
c6fb90c8
L		 1418static INLINE i386_cpu_flags
1419cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1420{
c6fb90c8
L		 1421 switch (ARRAY_SIZE (x.array))
1422 {
1423 case 3:
1424 x.array [2] &= y.array [2];
1425 case 2:
1426 x.array [1] &= y.array [1];
1427 case 1:
1428 x.array [0] &= y.array [0];
1429 break;
1430 default:
1431 abort ();
1432 }
1433 return x;
1434}
40fb9820 1435
c6fb90c8
L		 1436static INLINE i386_cpu_flags
1437cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1438{
c6fb90c8 1439 switch (ARRAY_SIZE (x.array))
40fb9820 1440 {
c6fb90c8
L		 1441 case 3:
1442 x.array [2] |= y.array [2];
1443 case 2:
1444 x.array [1] |= y.array [1];
1445 case 1:
1446 x.array [0] |= y.array [0];
40fb9820
L		 1447 break;
1448 default:
1449 abort ();
1450 }
40fb9820
L		 1451 return x;
1452}
1453
309d3373
JB		 1454static INLINE i386_cpu_flags
1455cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1456{
1457 switch (ARRAY_SIZE (x.array))
1458 {
1459 case 3:
1460 x.array [2] &= ~y.array [2];
1461 case 2:
1462 x.array [1] &= ~y.array [1];
1463 case 1:
1464 x.array [0] &= ~y.array [0];
1465 break;
1466 default:
1467 abort ();
1468 }
1469 return x;
1470}
1471
81486035
L		 1472static int
1473valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1474{
1475 if (cpu_arch_isa == PROCESSOR_IAMCU)
1476 {
1477 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1478 i386_cpu_flags compat_flags;
1479 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1480 return cpu_flags_all_zero (&compat_flags);
1481 }
1482 else
1483 return 1;
1484}
1485
c0f3af97
L		 1486#define CPU_FLAGS_ARCH_MATCH 0x1
1487#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1488#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1489#define CPU_FLAGS_PCLMUL_MATCH 0x8
1490#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1491
a5ff0eb2 1492#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1493 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1494 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1495#define CPU_FLAGS_PERFECT_MATCH \
1496 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1497
1498/* Return CPU flags match bits. */
3629bb00 1499
40fb9820 1500static int
d3ce72d0 1501cpu_flags_match (const insn_template *t)
40fb9820 1502{
c0f3af97
L		 1503 i386_cpu_flags x = t->cpu_flags;
1504 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1505
1506 x.bitfield.cpu64 = 0;
1507 x.bitfield.cpuno64 = 0;
1508
0dfbf9d7 1509 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1510 {
1511 /* This instruction is available on all archs. */
1512 match |= CPU_FLAGS_32BIT_MATCH;
1513 }
3629bb00
L		 1514 else
1515 {
c0f3af97 1516 /* This instruction is available only on some archs. */
3629bb00
L		 1517 i386_cpu_flags cpu = cpu_arch_flags;
1518
1519 cpu.bitfield.cpu64 = 0;
1520 cpu.bitfield.cpuno64 = 0;
1521 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1522 if (!cpu_flags_all_zero (&cpu))
1523 {
a5ff0eb2
L		 1524 if (x.bitfield.cpuavx)
1525 {
ce2f5b3c 1526 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1527 if (cpu.bitfield.cpuavx)
1528 {
1529 /* Check SSE2AVX. */
1530 if (!t->opcode_modifier.sse2avx|| sse2avx)
1531 {
1532 match |= (CPU_FLAGS_ARCH_MATCH
1533 | CPU_FLAGS_AVX_MATCH);
1534 /* Check AES. */
1535 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1536 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1537 /* Check PCLMUL. */
1538 if (!x.bitfield.cpupclmul
1539 || cpu.bitfield.cpupclmul)
1540 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1541 }
1542 }
1543 else
1544 match |= CPU_FLAGS_ARCH_MATCH;
1545 }
1546 else
c0f3af97
L		 1547 match |= CPU_FLAGS_32BIT_MATCH;
1548 }
3629bb00 1549 }
c0f3af97 1550 return match;
40fb9820
L		 1551}
1552
c6fb90c8
L		 1553static INLINE i386_operand_type
1554operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1555{
c6fb90c8
L		 1556 switch (ARRAY_SIZE (x.array))
1557 {
1558 case 3:
1559 x.array [2] &= y.array [2];
1560 case 2:
1561 x.array [1] &= y.array [1];
1562 case 1:
1563 x.array [0] &= y.array [0];
1564 break;
1565 default:
1566 abort ();
1567 }
1568 return x;
40fb9820
L		 1569}
1570
c6fb90c8
L		 1571static INLINE i386_operand_type
1572operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1573{
c6fb90c8 1574 switch (ARRAY_SIZE (x.array))
40fb9820 1575 {
c6fb90c8
L		 1576 case 3:
1577 x.array [2] |= y.array [2];
1578 case 2:
1579 x.array [1] |= y.array [1];
1580 case 1:
1581 x.array [0] |= y.array [0];
40fb9820
L		 1582 break;
1583 default:
1584 abort ();
1585 }
c6fb90c8
L		 1586 return x;
1587}
40fb9820 1588
c6fb90c8
L		 1589static INLINE i386_operand_type
1590operand_type_xor (i386_operand_type x, i386_operand_type y)
1591{
1592 switch (ARRAY_SIZE (x.array))
1593 {
1594 case 3:
1595 x.array [2] ^= y.array [2];
1596 case 2:
1597 x.array [1] ^= y.array [1];
1598 case 1:
1599 x.array [0] ^= y.array [0];
1600 break;
1601 default:
1602 abort ();
1603 }
40fb9820
L		 1604 return x;
1605}
1606
1607static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1608static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1609static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1610static const i386_operand_type inoutportreg
1611 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1612static const i386_operand_type reg16_inoutportreg
1613 = OPERAND_TYPE_REG16_INOUTPORTREG;
1614static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1615static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1616static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1617static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1618static const i386_operand_type anydisp
1619 = OPERAND_TYPE_ANYDISP;
40fb9820 1620static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1621static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1622static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1623static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1624static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1625static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1626static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1627static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1628static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1629static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1630static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1631static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1632static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1633static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1634
1635enum operand_type
1636{
1637 reg,
40fb9820
L		 1638 imm,
1639 disp,
1640 anymem
1641};
1642
c6fb90c8 1643static INLINE int
40fb9820
L		 1644operand_type_check (i386_operand_type t, enum operand_type c)
1645{
1646 switch (c)
1647 {
1648 case reg:
1649 return (t.bitfield.reg8
1650 || t.bitfield.reg16
1651 || t.bitfield.reg32
1652 || t.bitfield.reg64);
1653
40fb9820
L		 1654 case imm:
1655 return (t.bitfield.imm8
1656 || t.bitfield.imm8s
1657 || t.bitfield.imm16
1658 || t.bitfield.imm32
1659 || t.bitfield.imm32s
1660 || t.bitfield.imm64);
1661
1662 case disp:
1663 return (t.bitfield.disp8
1664 || t.bitfield.disp16
1665 || t.bitfield.disp32
1666 || t.bitfield.disp32s
1667 || t.bitfield.disp64);
1668
1669 case anymem:
1670 return (t.bitfield.disp8
1671 || t.bitfield.disp16
1672 || t.bitfield.disp32
1673 || t.bitfield.disp32s
1674 || t.bitfield.disp64
1675 || t.bitfield.baseindex);
1676
1677 default:
1678 abort ();
1679 }
2cfe26b6
AM		 1680
1681 return 0;
40fb9820
L		 1682}
1683
5c07affc
L		 1684/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1685 operand J for instruction template T. */
1686
1687static INLINE int
d3ce72d0 1688match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1689{
1690 return !((i.types[j].bitfield.byte
1691 && !t->operand_types[j].bitfield.byte)
1692 || (i.types[j].bitfield.word
1693 && !t->operand_types[j].bitfield.word)
1694 || (i.types[j].bitfield.dword
1695 && !t->operand_types[j].bitfield.dword)
1696 || (i.types[j].bitfield.qword
1697 && !t->operand_types[j].bitfield.qword));
1698}
1699
1700/* Return 1 if there is no conflict in any size on operand J for
1701 instruction template T. */
1702
1703static INLINE int
d3ce72d0 1704match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1705{
1706 return (match_reg_size (t, j)
1707 && !((i.types[j].bitfield.unspecified
af508cb9 1708 && !i.broadcast
5c07affc
L		 1709 && !t->operand_types[j].bitfield.unspecified)
1710 || (i.types[j].bitfield.fword
1711 && !t->operand_types[j].bitfield.fword)
1712 || (i.types[j].bitfield.tbyte
1713 && !t->operand_types[j].bitfield.tbyte)
1714 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1715 && !t->operand_types[j].bitfield.xmmword)
1716 || (i.types[j].bitfield.ymmword
43234a1e
L		 1717 && !t->operand_types[j].bitfield.ymmword)
1718 || (i.types[j].bitfield.zmmword
1719 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1720}
1721
1722/* Return 1 if there is no size conflict on any operands for
1723 instruction template T. */
1724
1725static INLINE int
d3ce72d0 1726operand_size_match (const insn_template *t)
5c07affc
L		 1727{
1728 unsigned int j;
1729 int match = 1;
1730
1731 /* Don't check jump instructions. */
1732 if (t->opcode_modifier.jump
1733 || t->opcode_modifier.jumpbyte
1734 || t->opcode_modifier.jumpdword
1735 || t->opcode_modifier.jumpintersegment)
1736 return match;
1737
1738 /* Check memory and accumulator operand size. */
1739 for (j = 0; j < i.operands; j++)
1740 {
1741 if (t->operand_types[j].bitfield.anysize)
1742 continue;
1743
1744 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1745 {
1746 match = 0;
1747 break;
1748 }
1749
1750 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1751 {
1752 match = 0;
1753 break;
1754 }
1755 }
1756
891edac4 1757 if (match)
5c07affc 1758 return match;
891edac4
L		 1759 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1760 {
1761mismatch:
86e026a4 1762 i.error = operand_size_mismatch;
891edac4
L		 1763 return 0;
1764 }
5c07affc
L		 1765
1766 /* Check reverse. */
9c2799c2 1767 gas_assert (i.operands == 2);
5c07affc
L		 1768
1769 match = 1;
1770 for (j = 0; j < 2; j++)
1771 {
1772 if (t->operand_types[j].bitfield.acc
1773 && !match_reg_size (t, j ? 0 : 1))
891edac4 1774 goto mismatch;
5c07affc
L		 1775
1776 if (i.types[j].bitfield.mem
1777 && !match_mem_size (t, j ? 0 : 1))
891edac4 1778 goto mismatch;
5c07affc
L		 1779 }
1780
1781 return match;
1782}
1783
c6fb90c8 1784static INLINE int
40fb9820
L		 1785operand_type_match (i386_operand_type overlap,
1786 i386_operand_type given)
1787{
1788 i386_operand_type temp = overlap;
1789
1790 temp.bitfield.jumpabsolute = 0;
7d5e4556 1791 temp.bitfield.unspecified = 0;
5c07affc
L		 1792 temp.bitfield.byte = 0;
1793 temp.bitfield.word = 0;
1794 temp.bitfield.dword = 0;
1795 temp.bitfield.fword = 0;
1796 temp.bitfield.qword = 0;
1797 temp.bitfield.tbyte = 0;
1798 temp.bitfield.xmmword = 0;
c0f3af97 1799 temp.bitfield.ymmword = 0;
43234a1e 1800 temp.bitfield.zmmword = 0;
0dfbf9d7 1801 if (operand_type_all_zero (&temp))
891edac4 1802 goto mismatch;
40fb9820 1803
891edac4
L		 1804 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1805 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1806 return 1;
1807
1808mismatch:
a65babc9 1809 i.error = operand_type_mismatch;
891edac4 1810 return 0;
40fb9820
L		 1811}
1812
7d5e4556 1813/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1814 unless the expected operand type register overlap is null.
1815 Note that Acc in a template matches every size of reg. */
1816
c6fb90c8 1817static INLINE int
40fb9820
L		 1818operand_type_register_match (i386_operand_type m0,
1819 i386_operand_type g0,
1820 i386_operand_type t0,
1821 i386_operand_type m1,
1822 i386_operand_type g1,
1823 i386_operand_type t1)
1824{
1825 if (!operand_type_check (g0, reg))
1826 return 1;
1827
1828 if (!operand_type_check (g1, reg))
1829 return 1;
1830
1831 if (g0.bitfield.reg8 == g1.bitfield.reg8
1832 && g0.bitfield.reg16 == g1.bitfield.reg16
1833 && g0.bitfield.reg32 == g1.bitfield.reg32
1834 && g0.bitfield.reg64 == g1.bitfield.reg64)
1835 return 1;
1836
1837 if (m0.bitfield.acc)
1838 {
1839 t0.bitfield.reg8 = 1;
1840 t0.bitfield.reg16 = 1;
1841 t0.bitfield.reg32 = 1;
1842 t0.bitfield.reg64 = 1;
1843 }
1844
1845 if (m1.bitfield.acc)
1846 {
1847 t1.bitfield.reg8 = 1;
1848 t1.bitfield.reg16 = 1;
1849 t1.bitfield.reg32 = 1;
1850 t1.bitfield.reg64 = 1;
1851 }
1852
891edac4
L		 1853 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1854 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1855 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1856 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1857 return 1;
1858
a65babc9 1859 i.error = register_type_mismatch;
891edac4
L		 1860
1861 return 0;
40fb9820
L		 1862}
1863
4c692bc7
JB		 1864static INLINE unsigned int
1865register_number (const reg_entry *r)
1866{
1867 unsigned int nr = r->reg_num;
1868
1869 if (r->reg_flags & RegRex)
1870 nr += 8;
1871
1872 return nr;
1873}
1874
252b5132 1875static INLINE unsigned int
40fb9820 1876mode_from_disp_size (i386_operand_type t)
252b5132 1877{
43234a1e 1878 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1879 return 1;
1880 else if (t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s)
1883 return 2;
1884 else
1885 return 0;
252b5132
RH		 1886}
1887
1888static INLINE int
65879393 1889fits_in_signed_byte (addressT num)
252b5132 1890{
65879393 1891 return num + 0x80 <= 0xff;
47926f60 1892}
252b5132
RH		 1893
1894static INLINE int
65879393 1895fits_in_unsigned_byte (addressT num)
252b5132 1896{
65879393 1897 return num <= 0xff;
47926f60 1898}
252b5132
RH		 1899
1900static INLINE int
65879393 1901fits_in_unsigned_word (addressT num)
252b5132 1902{
65879393 1903 return num <= 0xffff;
47926f60 1904}
252b5132
RH		 1905
1906static INLINE int
65879393 1907fits_in_signed_word (addressT num)
252b5132 1908{
65879393 1909 return num + 0x8000 <= 0xffff;
47926f60 1910}
2a962e6d 1911
3e73aa7c 1912static INLINE int
65879393 1913fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1914{
1915#ifndef BFD64
1916 return 1;
1917#else
65879393 1918 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1919#endif
1920} /* fits_in_signed_long() */
2a962e6d 1921
3e73aa7c 1922static INLINE int
65879393 1923fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1924{
1925#ifndef BFD64
1926 return 1;
1927#else
65879393 1928 return num <= 0xffffffff;
3e73aa7c
JH		 1929#endif
1930} /* fits_in_unsigned_long() */
252b5132 1931
43234a1e
L		 1932static INLINE int
1933fits_in_vec_disp8 (offsetT num)
1934{
1935 int shift = i.memshift;
1936 unsigned int mask;
1937
1938 if (shift == -1)
1939 abort ();
1940
1941 mask = (1 << shift) - 1;
1942
1943 /* Return 0 if NUM isn't properly aligned. */
1944 if ((num & mask))
1945 return 0;
1946
1947 /* Check if NUM will fit in 8bit after shift. */
1948 return fits_in_signed_byte (num >> shift);
1949}
1950
a683cc34
SP		 1951static INLINE int
1952fits_in_imm4 (offsetT num)
1953{
1954 return (num & 0xf) == num;
1955}
1956
40fb9820 1957static i386_operand_type
e3bb37b5 1958smallest_imm_type (offsetT num)
252b5132 1959{
40fb9820 1960 i386_operand_type t;
7ab9ffdd 1961
0dfbf9d7 1962 operand_type_set (&t, 0);
40fb9820
L		 1963 t.bitfield.imm64 = 1;
1964
1965 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1966 {
1967 /* This code is disabled on the 486 because all the Imm1 forms
1968 in the opcode table are slower on the i486. They're the
1969 versions with the implicitly specified single-position
1970 displacement, which has another syntax if you really want to
1971 use that form. */
40fb9820
L		 1972 t.bitfield.imm1 = 1;
1973 t.bitfield.imm8 = 1;
1974 t.bitfield.imm8s = 1;
1975 t.bitfield.imm16 = 1;
1976 t.bitfield.imm32 = 1;
1977 t.bitfield.imm32s = 1;
1978 }
1979 else if (fits_in_signed_byte (num))
1980 {
1981 t.bitfield.imm8 = 1;
1982 t.bitfield.imm8s = 1;
1983 t.bitfield.imm16 = 1;
1984 t.bitfield.imm32 = 1;
1985 t.bitfield.imm32s = 1;
1986 }
1987 else if (fits_in_unsigned_byte (num))
1988 {
1989 t.bitfield.imm8 = 1;
1990 t.bitfield.imm16 = 1;
1991 t.bitfield.imm32 = 1;
1992 t.bitfield.imm32s = 1;
1993 }
1994 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1995 {
1996 t.bitfield.imm16 = 1;
1997 t.bitfield.imm32 = 1;
1998 t.bitfield.imm32s = 1;
1999 }
2000 else if (fits_in_signed_long (num))
2001 {
2002 t.bitfield.imm32 = 1;
2003 t.bitfield.imm32s = 1;
2004 }
2005 else if (fits_in_unsigned_long (num))
2006 t.bitfield.imm32 = 1;
2007
2008 return t;
47926f60 2009}
252b5132 2010
847f7ad4 2011static offsetT
e3bb37b5 2012offset_in_range (offsetT val, int size)
847f7ad4 2013{
508866be 2014 addressT mask;
ba2adb93 2015
847f7ad4
AM		 2016 switch (size)
2017 {
508866be
L		 2018 case 1: mask = ((addressT) 1 << 8) - 1; break;
2019 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2020 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2021#ifdef BFD64
2022 case 8: mask = ((addressT) 2 << 63) - 1; break;
2023#endif
47926f60 2024 default: abort ();
847f7ad4
AM		 2025 }
2026
9de868bf
L		 2027#ifdef BFD64
2028 /* If BFD64, sign extend val for 32bit address mode. */
2029 if (flag_code != CODE_64BIT
2030 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2031 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2032 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2033#endif
ba2adb93 2034
47926f60 2035 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2036 {
2037 char buf1[40], buf2[40];
2038
2039 sprint_value (buf1, val);
2040 sprint_value (buf2, val & mask);
2041 as_warn (_("%s shortened to %s"), buf1, buf2);
2042 }
2043 return val & mask;
2044}
2045
c32fa91d
L		 2046enum PREFIX_GROUP
2047{
2048 PREFIX_EXIST = 0,
2049 PREFIX_LOCK,
2050 PREFIX_REP,
2051 PREFIX_OTHER
2052};
2053
2054/* Returns
2055 a. PREFIX_EXIST if attempting to add a prefix where one from the
2056 same class already exists.
2057 b. PREFIX_LOCK if lock prefix is added.
2058 c. PREFIX_REP if rep/repne prefix is added.
2059 d. PREFIX_OTHER if other prefix is added.
2060 */
2061
2062static enum PREFIX_GROUP
e3bb37b5 2063add_prefix (unsigned int prefix)
252b5132 2064{
c32fa91d 2065 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2066 unsigned int q;
252b5132 2067
29b0f896
AM		 2068 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2069 && flag_code == CODE_64BIT)
b1905489 2070 {
161a04f6
L		 2071 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2072 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2073 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2074 ret = PREFIX_EXIST;
b1905489
JB		 2075 q = REX_PREFIX;
2076 }
3e73aa7c 2077 else
b1905489
JB		 2078 {
2079 switch (prefix)
2080 {
2081 default:
2082 abort ();
2083
2084 case CS_PREFIX_OPCODE:
2085 case DS_PREFIX_OPCODE:
2086 case ES_PREFIX_OPCODE:
2087 case FS_PREFIX_OPCODE:
2088 case GS_PREFIX_OPCODE:
2089 case SS_PREFIX_OPCODE:
2090 q = SEG_PREFIX;
2091 break;
2092
2093 case REPNE_PREFIX_OPCODE:
2094 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2095 q = REP_PREFIX;
2096 ret = PREFIX_REP;
2097 break;
2098
b1905489 2099 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2100 q = LOCK_PREFIX;
2101 ret = PREFIX_LOCK;
b1905489
JB		 2102 break;
2103
2104 case FWAIT_OPCODE:
2105 q = WAIT_PREFIX;
2106 break;
2107
2108 case ADDR_PREFIX_OPCODE:
2109 q = ADDR_PREFIX;
2110 break;
2111
2112 case DATA_PREFIX_OPCODE:
2113 q = DATA_PREFIX;
2114 break;
2115 }
2116 if (i.prefix[q] != 0)
c32fa91d 2117 ret = PREFIX_EXIST;
b1905489 2118 }
252b5132 2119
b1905489 2120 if (ret)
252b5132 2121 {
b1905489
JB		 2122 if (!i.prefix[q])
2123 ++i.prefixes;
2124 i.prefix[q] |= prefix;
252b5132 2125 }
b1905489
JB		 2126 else
2127 as_bad (_("same type of prefix used twice"));
252b5132 2128
252b5132
RH		 2129 return ret;
2130}
2131
2132static void
78f12dd3 2133update_code_flag (int value, int check)
eecb386c 2134{
78f12dd3
L		 2135 PRINTF_LIKE ((*as_error));
2136
1e9cc1c2 2137 flag_code = (enum flag_code) value;
40fb9820
L		 2138 if (flag_code == CODE_64BIT)
2139 {
2140 cpu_arch_flags.bitfield.cpu64 = 1;
2141 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2142 }
2143 else
2144 {
2145 cpu_arch_flags.bitfield.cpu64 = 0;
2146 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2147 }
2148 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2149 {
78f12dd3
L		 2150 if (check)
2151 as_error = as_fatal;
2152 else
2153 as_error = as_bad;
2154 (*as_error) (_("64bit mode not supported on `%s'."),
2155 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2156 }
40fb9820 2157 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2158 {
78f12dd3
L		 2159 if (check)
2160 as_error = as_fatal;
2161 else
2162 as_error = as_bad;
2163 (*as_error) (_("32bit mode not supported on `%s'."),
2164 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2165 }
eecb386c
AM		 2166 stackop_size = '\0';
2167}
2168
78f12dd3
L		 2169static void
2170set_code_flag (int value)
2171{
2172 update_code_flag (value, 0);
2173}
2174
eecb386c 2175static void
e3bb37b5 2176set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2177{
1e9cc1c2 2178 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2179 if (flag_code != CODE_16BIT)
2180 abort ();
2181 cpu_arch_flags.bitfield.cpu64 = 0;
2182 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2183 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2184}
2185
2186static void
e3bb37b5 2187set_intel_syntax (int syntax_flag)
252b5132
RH		 2188{
2189 /* Find out if register prefixing is specified. */
2190 int ask_naked_reg = 0;
2191
2192 SKIP_WHITESPACE ();
29b0f896 2193 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2194 {
d02603dc
NC		 2195 char *string;
2196 int e = get_symbol_name (&string);
252b5132 2197
47926f60 2198 if (strcmp (string, "prefix") == 0)
252b5132 2199 ask_naked_reg = 1;
47926f60 2200 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2201 ask_naked_reg = -1;
2202 else
d0b47220 2203 as_bad (_("bad argument to syntax directive."));
d02603dc 2204 (void) restore_line_pointer (e);
252b5132
RH		 2205 }
2206 demand_empty_rest_of_line ();
c3332e24 2207
252b5132
RH		 2208 intel_syntax = syntax_flag;
2209
2210 if (ask_naked_reg == 0)
f86103b7
AM		 2211 allow_naked_reg = (intel_syntax
2212 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2213 else
2214 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2215
ee86248c 2216 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2217
e4a3b5a4 2218 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2219 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2220 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2221}
2222
1efbbeb4
L		 2223static void
2224set_intel_mnemonic (int mnemonic_flag)
2225{
e1d4d893 2226 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2227}
2228
db51cc60
L		 2229static void
2230set_allow_index_reg (int flag)
2231{
2232 allow_index_reg = flag;
2233}
2234
cb19c032 2235static void
7bab8ab5 2236set_check (int what)
cb19c032 2237{
7bab8ab5
JB		 2238 enum check_kind *kind;
2239 const char *str;
2240
2241 if (what)
2242 {
2243 kind = &operand_check;
2244 str = "operand";
2245 }
2246 else
2247 {
2248 kind = &sse_check;
2249 str = "sse";
2250 }
2251
cb19c032
L		 2252 SKIP_WHITESPACE ();
2253
2254 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2255 {
d02603dc
NC		 2256 char *string;
2257 int e = get_symbol_name (&string);
cb19c032
L		 2258
2259 if (strcmp (string, "none") == 0)
7bab8ab5 2260 *kind = check_none;
cb19c032 2261 else if (strcmp (string, "warning") == 0)
7bab8ab5 2262 *kind = check_warning;
cb19c032 2263 else if (strcmp (string, "error") == 0)
7bab8ab5 2264 *kind = check_error;
cb19c032 2265 else
7bab8ab5 2266 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2267 (void) restore_line_pointer (e);
cb19c032
L		 2268 }
2269 else
7bab8ab5 2270 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2271
2272 demand_empty_rest_of_line ();
2273}
2274
8a9036a4
L		 2275static void
2276check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2277 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2278{
2279#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2280 static const char *arch;
2281
2282 /* Intel LIOM is only supported on ELF. */
2283 if (!IS_ELF)
2284 return;
2285
2286 if (!arch)
2287 {
2288 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2289 use default_arch. */
2290 arch = cpu_arch_name;
2291 if (!arch)
2292 arch = default_arch;
2293 }
2294
81486035
L		 2295 /* If we are targeting Intel MCU, we must enable it. */
2296 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2297 || new_flag.bitfield.cpuiamcu)
2298 return;
2299
3632d14b 2300 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2301 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2302 || new_flag.bitfield.cpul1om)
8a9036a4 2303 return;
76ba9986 2304
7a9068fe
L		 2305 /* If we are targeting Intel K1OM, we must enable it. */
2306 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2307 || new_flag.bitfield.cpuk1om)
2308 return;
2309
8a9036a4
L		 2310 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2311#endif
2312}
2313
e413e4e9 2314static void
e3bb37b5 2315set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2316{
47926f60 2317 SKIP_WHITESPACE ();
e413e4e9 2318
29b0f896 2319 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2320 {
d02603dc
NC		 2321 char *string;
2322 int e = get_symbol_name (&string);
91d6fa6a 2323 unsigned int j;
40fb9820 2324 i386_cpu_flags flags;
e413e4e9 2325
91d6fa6a 2326 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2327 {
91d6fa6a 2328 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2329 {
91d6fa6a 2330 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2331
5c6af06e
JB		 2332 if (*string != '.')
2333 {
91d6fa6a 2334 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2335 cpu_sub_arch_name = NULL;
91d6fa6a 2336 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2337 if (flag_code == CODE_64BIT)
2338 {
2339 cpu_arch_flags.bitfield.cpu64 = 1;
2340 cpu_arch_flags.bitfield.cpuno64 = 0;
2341 }
2342 else
2343 {
2344 cpu_arch_flags.bitfield.cpu64 = 0;
2345 cpu_arch_flags.bitfield.cpuno64 = 1;
2346 }
91d6fa6a
NC		 2347 cpu_arch_isa = cpu_arch[j].type;
2348 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2349 if (!cpu_arch_tune_set)
2350 {
2351 cpu_arch_tune = cpu_arch_isa;
2352 cpu_arch_tune_flags = cpu_arch_isa_flags;
2353 }
5c6af06e
JB		 2354 break;
2355 }
40fb9820 2356
22109423 2357 if (!cpu_arch[j].negated)
309d3373 2358 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2359 cpu_arch[j].flags);
309d3373
JB		 2360 else
2361 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2362 cpu_arch[j].flags);
81486035
L		 2363
2364 if (!valid_iamcu_cpu_flags (&flags))
2365 as_fatal (_("`%s' isn't valid for Intel MCU"),
2366 cpu_arch[j].name);
2367 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2368 {
6305a203
L		 2369 if (cpu_sub_arch_name)
2370 {
2371 char *name = cpu_sub_arch_name;
2372 cpu_sub_arch_name = concat (name,
91d6fa6a 2373 cpu_arch[j].name,
1bf57e9f 2374 (const char *) NULL);
6305a203
L		 2375 free (name);
2376 }
2377 else
91d6fa6a 2378 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2379 cpu_arch_flags = flags;
a586129e 2380 cpu_arch_isa_flags = flags;
5c6af06e 2381 }
d02603dc 2382 (void) restore_line_pointer (e);
5c6af06e
JB		 2383 demand_empty_rest_of_line ();
2384 return;
e413e4e9
AM		 2385 }
2386 }
91d6fa6a 2387 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2388 as_bad (_("no such architecture: `%s'"), string);
2389
2390 *input_line_pointer = e;
2391 }
2392 else
2393 as_bad (_("missing cpu architecture"));
2394
fddf5b5b
AM		 2395 no_cond_jump_promotion = 0;
2396 if (*input_line_pointer == ','
29b0f896 2397 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2398 {
d02603dc
NC		 2399 char *string;
2400 char e;
2401
2402 ++input_line_pointer;
2403 e = get_symbol_name (&string);
fddf5b5b
AM		 2404
2405 if (strcmp (string, "nojumps") == 0)
2406 no_cond_jump_promotion = 1;
2407 else if (strcmp (string, "jumps") == 0)
2408 ;
2409 else
2410 as_bad (_("no such architecture modifier: `%s'"), string);
2411
d02603dc 2412 (void) restore_line_pointer (e);
fddf5b5b
AM		 2413 }
2414
e413e4e9
AM		 2415 demand_empty_rest_of_line ();
2416}
2417
8a9036a4
L		 2418enum bfd_architecture
2419i386_arch (void)
2420{
3632d14b 2421 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2422 {
2423 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2424 || flag_code != CODE_64BIT)
2425 as_fatal (_("Intel L1OM is 64bit ELF only"));
2426 return bfd_arch_l1om;
2427 }
7a9068fe
L		 2428 else if (cpu_arch_isa == PROCESSOR_K1OM)
2429 {
2430 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2431 || flag_code != CODE_64BIT)
2432 as_fatal (_("Intel K1OM is 64bit ELF only"));
2433 return bfd_arch_k1om;
2434 }
81486035
L		 2435 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2436 {
2437 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2438 || flag_code == CODE_64BIT)
2439 as_fatal (_("Intel MCU is 32bit ELF only"));
2440 return bfd_arch_iamcu;
2441 }
8a9036a4
L		 2442 else
2443 return bfd_arch_i386;
2444}
2445
b9d79e03 2446unsigned long
7016a5d5 2447i386_mach (void)
b9d79e03 2448{
351f65ca 2449 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2450 {
3632d14b 2451 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2452 {
351f65ca
L		 2453 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2454 || default_arch[6] != '\0')
8a9036a4
L		 2455 as_fatal (_("Intel L1OM is 64bit ELF only"));
2456 return bfd_mach_l1om;
2457 }
7a9068fe
L		 2458 else if (cpu_arch_isa == PROCESSOR_K1OM)
2459 {
2460 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2461 || default_arch[6] != '\0')
2462 as_fatal (_("Intel K1OM is 64bit ELF only"));
2463 return bfd_mach_k1om;
2464 }
351f65ca 2465 else if (default_arch[6] == '\0')
8a9036a4 2466 return bfd_mach_x86_64;
351f65ca
L		 2467 else
2468 return bfd_mach_x64_32;
8a9036a4 2469 }
5197d474
L		 2470 else if (!strcmp (default_arch, "i386")
2471 || !strcmp (default_arch, "iamcu"))
81486035
L		 2472 {
2473 if (cpu_arch_isa == PROCESSOR_IAMCU)
2474 {
2475 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2476 as_fatal (_("Intel MCU is 32bit ELF only"));
2477 return bfd_mach_i386_iamcu;
2478 }
2479 else
2480 return bfd_mach_i386_i386;
2481 }
b9d79e03 2482 else
2b5d6a91 2483 as_fatal (_("unknown architecture"));
b9d79e03 2484}
b9d79e03 2485\f
252b5132 2486void
7016a5d5 2487md_begin (void)
252b5132
RH		 2488{
2489 const char *hash_err;
2490
47926f60 2491 /* Initialize op_hash hash table. */
252b5132
RH		 2492 op_hash = hash_new ();
2493
2494 {
d3ce72d0 2495 const insn_template *optab;
29b0f896 2496 templates *core_optab;
252b5132 2497
47926f60
KH		 2498 /* Setup for loop. */
2499 optab = i386_optab;
252b5132
RH		 2500 core_optab = (templates *) xmalloc (sizeof (templates));
2501 core_optab->start = optab;
2502
2503 while (1)
2504 {
2505 ++optab;
2506 if (optab->name == NULL
2507 || strcmp (optab->name, (optab - 1)->name) != 0)
2508 {
2509 /* different name --> ship out current template list;
47926f60 2510 add to hash table; & begin anew. */
252b5132
RH		 2511 core_optab->end = optab;
2512 hash_err = hash_insert (op_hash,
2513 (optab - 1)->name,
5a49b8ac 2514 (void *) core_optab);
252b5132
RH		 2515 if (hash_err)
2516 {
b37df7c4 2517 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2518 (optab - 1)->name,
2519 hash_err);
2520 }
2521 if (optab->name == NULL)
2522 break;
2523 core_optab = (templates *) xmalloc (sizeof (templates));
2524 core_optab->start = optab;
2525 }
2526 }
2527 }
2528
47926f60 2529 /* Initialize reg_hash hash table. */
252b5132
RH		 2530 reg_hash = hash_new ();
2531 {
29b0f896 2532 const reg_entry *regtab;
c3fe08fa 2533 unsigned int regtab_size = i386_regtab_size;
252b5132 2534
c3fe08fa 2535 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2536 {
5a49b8ac 2537 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2538 if (hash_err)
b37df7c4 2539 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2540 regtab->reg_name,
2541 hash_err);
252b5132
RH		 2542 }
2543 }
2544
47926f60 2545 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2546 {
29b0f896
AM		 2547 int c;
2548 char *p;
252b5132
RH		 2549
2550 for (c = 0; c < 256; c++)
2551 {
3882b010 2552 if (ISDIGIT (c))
252b5132
RH		 2553 {
2554 digit_chars[c] = c;
2555 mnemonic_chars[c] = c;
2556 register_chars[c] = c;
2557 operand_chars[c] = c;
2558 }
3882b010 2559 else if (ISLOWER (c))
252b5132
RH		 2560 {
2561 mnemonic_chars[c] = c;
2562 register_chars[c] = c;
2563 operand_chars[c] = c;
2564 }
3882b010 2565 else if (ISUPPER (c))
252b5132 2566 {
3882b010 2567 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2568 register_chars[c] = mnemonic_chars[c];
2569 operand_chars[c] = c;
2570 }
43234a1e
L		 2571 else if (c == '{' || c == '}')
2572 operand_chars[c] = c;
252b5132 2573
3882b010 2574 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2575 identifier_chars[c] = c;
2576 else if (c >= 128)
2577 {
2578 identifier_chars[c] = c;
2579 operand_chars[c] = c;
2580 }
2581 }
2582
2583#ifdef LEX_AT
2584 identifier_chars['@'] = '@';
32137342
NC		 2585#endif
2586#ifdef LEX_QM
2587 identifier_chars['?'] = '?';
2588 operand_chars['?'] = '?';
252b5132 2589#endif
252b5132 2590 digit_chars['-'] = '-';
c0f3af97 2591 mnemonic_chars['_'] = '_';
791fe849 2592 mnemonic_chars['-'] = '-';
0003779b 2593 mnemonic_chars['.'] = '.';
252b5132
RH		 2594 identifier_chars['_'] = '_';
2595 identifier_chars['.'] = '.';
2596
2597 for (p = operand_special_chars; *p != '\0'; p++)
2598 operand_chars[(unsigned char) *p] = *p;
2599 }
2600
a4447b93
RH		 2601 if (flag_code == CODE_64BIT)
2602 {
ca19b261
KT		 2603#if defined (OBJ_COFF) && defined (TE_PE)
2604 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2605 ? 32 : 16);
2606#else
a4447b93 2607 x86_dwarf2_return_column = 16;
ca19b261 2608#endif
61ff971f 2609 x86_cie_data_alignment = -8;
a4447b93
RH		 2610 }
2611 else
2612 {
2613 x86_dwarf2_return_column = 8;
2614 x86_cie_data_alignment = -4;
2615 }
252b5132
RH		 2616}
2617
2618void
e3bb37b5 2619i386_print_statistics (FILE *file)
252b5132
RH		 2620{
2621 hash_print_statistics (file, "i386 opcode", op_hash);
2622 hash_print_statistics (file, "i386 register", reg_hash);
2623}
2624\f
252b5132
RH		 2625#ifdef DEBUG386
2626
ce8a8b2f 2627/* Debugging routines for md_assemble. */
d3ce72d0 2628static void pte (insn_template *);
40fb9820 2629static void pt (i386_operand_type);
e3bb37b5
L		 2630static void pe (expressionS *);
2631static void ps (symbolS *);
252b5132
RH		 2632
2633static void
e3bb37b5 2634pi (char *line, i386_insn *x)
252b5132 2635{
09137c09 2636 unsigned int j;
252b5132
RH		 2637
2638 fprintf (stdout, "%s: template ", line);
2639 pte (&x->tm);
09f131f2
JH		 2640 fprintf (stdout, " address: base %s index %s scale %x\n",
2641 x->base_reg ? x->base_reg->reg_name : "none",
2642 x->index_reg ? x->index_reg->reg_name : "none",
2643 x->log2_scale_factor);
2644 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2645 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2646 fprintf (stdout, " sib: base %x index %x scale %x\n",
2647 x->sib.base, x->sib.index, x->sib.scale);
2648 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2649 (x->rex & REX_W) != 0,
2650 (x->rex & REX_R) != 0,
2651 (x->rex & REX_X) != 0,
2652 (x->rex & REX_B) != 0);
09137c09 2653 for (j = 0; j < x->operands; j++)
252b5132 2654 {
09137c09
SP		 2655 fprintf (stdout, " #%d: ", j + 1);
2656 pt (x->types[j]);
252b5132 2657 fprintf (stdout, "\n");
09137c09
SP		 2658 if (x->types[j].bitfield.reg8
2659 || x->types[j].bitfield.reg16
2660 || x->types[j].bitfield.reg32
2661 || x->types[j].bitfield.reg64
2662 || x->types[j].bitfield.regmmx
2663 || x->types[j].bitfield.regxmm
2664 || x->types[j].bitfield.regymm
43234a1e 2665 || x->types[j].bitfield.regzmm
09137c09
SP		 2666 || x->types[j].bitfield.sreg2
2667 || x->types[j].bitfield.sreg3
2668 || x->types[j].bitfield.control
2669 || x->types[j].bitfield.debug
2670 || x->types[j].bitfield.test)
2671 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2672 if (operand_type_check (x->types[j], imm))
2673 pe (x->op[j].imms);
2674 if (operand_type_check (x->types[j], disp))
2675 pe (x->op[j].disps);
252b5132
RH		 2676 }
2677}
2678
2679static void
d3ce72d0 2680pte (insn_template *t)
252b5132 2681{
09137c09 2682 unsigned int j;
252b5132 2683 fprintf (stdout, " %d operands ", t->operands);
47926f60 2684 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2685 if (t->extension_opcode != None)
2686 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2687 if (t->opcode_modifier.d)
252b5132 2688 fprintf (stdout, "D");
40fb9820 2689 if (t->opcode_modifier.w)
252b5132
RH		 2690 fprintf (stdout, "W");
2691 fprintf (stdout, "\n");
09137c09 2692 for (j = 0; j < t->operands; j++)
252b5132 2693 {
09137c09
SP		 2694 fprintf (stdout, " #%d type ", j + 1);
2695 pt (t->operand_types[j]);
252b5132
RH		 2696 fprintf (stdout, "\n");
2697 }
2698}
2699
2700static void
e3bb37b5 2701pe (expressionS *e)
252b5132 2702{
24eab124 2703 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2704 fprintf (stdout, " add_number %ld (%lx)\n",
2705 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2706 if (e->X_add_symbol)
2707 {
2708 fprintf (stdout, " add_symbol ");
2709 ps (e->X_add_symbol);
2710 fprintf (stdout, "\n");
2711 }
2712 if (e->X_op_symbol)
2713 {
2714 fprintf (stdout, " op_symbol ");
2715 ps (e->X_op_symbol);
2716 fprintf (stdout, "\n");
2717 }
2718}
2719
2720static void
e3bb37b5 2721ps (symbolS *s)
252b5132
RH		 2722{
2723 fprintf (stdout, "%s type %s%s",
2724 S_GET_NAME (s),
2725 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2726 segment_name (S_GET_SEGMENT (s)));
2727}
2728
7b81dfbb 2729static struct type_name
252b5132 2730 {
40fb9820
L		 2731 i386_operand_type mask;
2732 const char *name;
252b5132 2733 }
7b81dfbb 2734const type_names[] =
252b5132 2735{
40fb9820
L		 2736 { OPERAND_TYPE_REG8, "r8" },
2737 { OPERAND_TYPE_REG16, "r16" },
2738 { OPERAND_TYPE_REG32, "r32" },
2739 { OPERAND_TYPE_REG64, "r64" },
2740 { OPERAND_TYPE_IMM8, "i8" },
2741 { OPERAND_TYPE_IMM8, "i8s" },
2742 { OPERAND_TYPE_IMM16, "i16" },
2743 { OPERAND_TYPE_IMM32, "i32" },
2744 { OPERAND_TYPE_IMM32S, "i32s" },
2745 { OPERAND_TYPE_IMM64, "i64" },
2746 { OPERAND_TYPE_IMM1, "i1" },
2747 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2748 { OPERAND_TYPE_DISP8, "d8" },
2749 { OPERAND_TYPE_DISP16, "d16" },
2750 { OPERAND_TYPE_DISP32, "d32" },
2751 { OPERAND_TYPE_DISP32S, "d32s" },
2752 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2753 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2754 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2755 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2756 { OPERAND_TYPE_CONTROL, "control reg" },
2757 { OPERAND_TYPE_TEST, "test reg" },
2758 { OPERAND_TYPE_DEBUG, "debug reg" },
2759 { OPERAND_TYPE_FLOATREG, "FReg" },
2760 { OPERAND_TYPE_FLOATACC, "FAcc" },
2761 { OPERAND_TYPE_SREG2, "SReg2" },
2762 { OPERAND_TYPE_SREG3, "SReg3" },
2763 { OPERAND_TYPE_ACC, "Acc" },
2764 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2765 { OPERAND_TYPE_REGMMX, "rMMX" },
2766 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2767 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2768 { OPERAND_TYPE_REGZMM, "rZMM" },
2769 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2770 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2771};
2772
2773static void
40fb9820 2774pt (i386_operand_type t)
252b5132 2775{
40fb9820 2776 unsigned int j;
c6fb90c8 2777 i386_operand_type a;
252b5132 2778
40fb9820 2779 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2780 {
2781 a = operand_type_and (t, type_names[j].mask);
0349dc08 2782 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2783 fprintf (stdout, "%s, ", type_names[j].name);
2784 }
252b5132
RH		 2785 fflush (stdout);
2786}
2787
2788#endif /* DEBUG386 */
2789\f
252b5132 2790static bfd_reloc_code_real_type
3956db08 2791reloc (unsigned int size,
64e74474
AM		 2792 int pcrel,
2793 int sign,
2794 bfd_reloc_code_real_type other)
252b5132 2795{
47926f60 2796 if (other != NO_RELOC)
3956db08 2797 {
91d6fa6a 2798 reloc_howto_type *rel;
3956db08
JB		 2799
2800 if (size == 8)
2801 switch (other)
2802 {
64e74474
AM		 2803 case BFD_RELOC_X86_64_GOT32:
2804 return BFD_RELOC_X86_64_GOT64;
2805 break;
553d1284
L		 2806 case BFD_RELOC_X86_64_GOTPLT64:
2807 return BFD_RELOC_X86_64_GOTPLT64;
2808 break;
64e74474
AM		 2809 case BFD_RELOC_X86_64_PLTOFF64:
2810 return BFD_RELOC_X86_64_PLTOFF64;
2811 break;
2812 case BFD_RELOC_X86_64_GOTPC32:
2813 other = BFD_RELOC_X86_64_GOTPC64;
2814 break;
2815 case BFD_RELOC_X86_64_GOTPCREL:
2816 other = BFD_RELOC_X86_64_GOTPCREL64;
2817 break;
2818 case BFD_RELOC_X86_64_TPOFF32:
2819 other = BFD_RELOC_X86_64_TPOFF64;
2820 break;
2821 case BFD_RELOC_X86_64_DTPOFF32:
2822 other = BFD_RELOC_X86_64_DTPOFF64;
2823 break;
2824 default:
2825 break;
3956db08 2826 }
e05278af 2827
8ce3d284 2828#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2829 if (other == BFD_RELOC_SIZE32)
2830 {
2831 if (size == 8)
1ab668bf 2832 other = BFD_RELOC_SIZE64;
8fd4256d 2833 if (pcrel)
1ab668bf
AM		 2834 {
2835 as_bad (_("there are no pc-relative size relocations"));
2836 return NO_RELOC;
2837 }
8fd4256d 2838 }
8ce3d284 2839#endif
8fd4256d 2840
e05278af 2841 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2842 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2843 sign = -1;
2844
91d6fa6a
NC		 2845 rel = bfd_reloc_type_lookup (stdoutput, other);
2846 if (!rel)
3956db08 2847 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2848 else if (size != bfd_get_reloc_size (rel))
3956db08 2849 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2850 bfd_get_reloc_size (rel),
3956db08 2851 size);
91d6fa6a 2852 else if (pcrel && !rel->pc_relative)
3956db08 2853 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2854 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2855 && !sign)
91d6fa6a 2856 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2857 && sign > 0))
3956db08
JB		 2858 as_bad (_("relocated field and relocation type differ in signedness"));
2859 else
2860 return other;
2861 return NO_RELOC;
2862 }
252b5132
RH		 2863
2864 if (pcrel)
2865 {
3e73aa7c 2866 if (!sign)
3956db08 2867 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2868 switch (size)
2869 {
2870 case 1: return BFD_RELOC_8_PCREL;
2871 case 2: return BFD_RELOC_16_PCREL;
d258b828 2872 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2873 case 8: return BFD_RELOC_64_PCREL;
252b5132 2874 }
3956db08 2875 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2876 }
2877 else
2878 {
3956db08 2879 if (sign > 0)
e5cb08ac 2880 switch (size)
3e73aa7c
JH		 2881 {
2882 case 4: return BFD_RELOC_X86_64_32S;
2883 }
2884 else
2885 switch (size)
2886 {
2887 case 1: return BFD_RELOC_8;
2888 case 2: return BFD_RELOC_16;
2889 case 4: return BFD_RELOC_32;
2890 case 8: return BFD_RELOC_64;
2891 }
3956db08
JB		 2892 as_bad (_("cannot do %s %u byte relocation"),
2893 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2894 }
2895
0cc9e1d3 2896 return NO_RELOC;
252b5132
RH		 2897}
2898
47926f60
KH		 2899/* Here we decide which fixups can be adjusted to make them relative to
2900 the beginning of the section instead of the symbol. Basically we need
2901 to make sure that the dynamic relocations are done correctly, so in
2902 some cases we force the original symbol to be used. */
2903
252b5132 2904int
e3bb37b5 2905tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2906{
6d249963 2907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2908 if (!IS_ELF)
31312f95
AM		 2909 return 1;
2910
a161fe53
AM		 2911 /* Don't adjust pc-relative references to merge sections in 64-bit
2912 mode. */
2913 if (use_rela_relocations
2914 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2915 && fixP->fx_pcrel)
252b5132 2916 return 0;
31312f95 2917
8d01d9a9
AJ		 2918 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2919 and changed later by validate_fix. */
2920 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2921 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2922 return 0;
2923
8fd4256d
L		 2924 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2925 for size relocations. */
2926 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2927 || fixP->fx_r_type == BFD_RELOC_SIZE64
2928 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2929 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2930 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2931 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2932 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2933 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2941 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2942 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2943 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2944 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2945 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2946 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2948 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2952 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2954 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2955 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2956 return 0;
31312f95 2957#endif
252b5132
RH		 2958 return 1;
2959}
252b5132 2960
b4cac588 2961static int
e3bb37b5 2962intel_float_operand (const char *mnemonic)
252b5132 2963{
9306ca4a
JB		 2964 /* Note that the value returned is meaningful only for opcodes with (memory)
2965 operands, hence the code here is free to improperly handle opcodes that
2966 have no operands (for better performance and smaller code). */
2967
2968 if (mnemonic[0] != 'f')
2969 return 0; /* non-math */
2970
2971 switch (mnemonic[1])
2972 {
2973 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2974 the fs segment override prefix not currently handled because no
2975 call path can make opcodes without operands get here */
2976 case 'i':
2977 return 2 /* integer op */;
2978 case 'l':
2979 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2980 return 3; /* fldcw/fldenv */
2981 break;
2982 case 'n':
2983 if (mnemonic[2] != 'o' /* fnop */)
2984 return 3; /* non-waiting control op */
2985 break;
2986 case 'r':
2987 if (mnemonic[2] == 's')
2988 return 3; /* frstor/frstpm */
2989 break;
2990 case 's':
2991 if (mnemonic[2] == 'a')
2992 return 3; /* fsave */
2993 if (mnemonic[2] == 't')
2994 {
2995 switch (mnemonic[3])
2996 {
2997 case 'c': /* fstcw */
2998 case 'd': /* fstdw */
2999 case 'e': /* fstenv */
3000 case 's': /* fsts[gw] */
3001 return 3;
3002 }
3003 }
3004 break;
3005 case 'x':
3006 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3007 return 0; /* fxsave/fxrstor are not really math ops */
3008 break;
3009 }
252b5132 3010
9306ca4a 3011 return 1;
252b5132
RH		 3012}
3013
c0f3af97
L		 3014/* Build the VEX prefix. */
3015
3016static void
d3ce72d0 3017build_vex_prefix (const insn_template *t)
c0f3af97
L		 3018{
3019 unsigned int register_specifier;
3020 unsigned int implied_prefix;
3021 unsigned int vector_length;
3022
3023 /* Check register specifier. */
3024 if (i.vex.register_specifier)
43234a1e
L		 3025 {
3026 register_specifier =
3027 ~register_number (i.vex.register_specifier) & 0xf;
3028 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3029 }
c0f3af97
L		 3030 else
3031 register_specifier = 0xf;
3032
fa99fab2
L		 3033 /* Use 2-byte VEX prefix by swappping destination and source
3034 operand. */
3035 if (!i.swap_operand
3036 && i.operands == i.reg_operands
7f399153 3037 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3038 && i.tm.opcode_modifier.s
3039 && i.rex == REX_B)
3040 {
3041 unsigned int xchg = i.operands - 1;
3042 union i386_op temp_op;
3043 i386_operand_type temp_type;
3044
3045 temp_type = i.types[xchg];
3046 i.types[xchg] = i.types[0];
3047 i.types[0] = temp_type;
3048 temp_op = i.op[xchg];
3049 i.op[xchg] = i.op[0];
3050 i.op[0] = temp_op;
3051
9c2799c2 3052 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3053
3054 i.rex = REX_R;
3055 xchg = i.rm.regmem;
3056 i.rm.regmem = i.rm.reg;
3057 i.rm.reg = xchg;
3058
3059 /* Use the next insn. */
3060 i.tm = t[1];
3061 }
3062
539f890d
L		 3063 if (i.tm.opcode_modifier.vex == VEXScalar)
3064 vector_length = avxscalar;
3065 else
3066 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3067
3068 switch ((i.tm.base_opcode >> 8) & 0xff)
3069 {
3070 case 0:
3071 implied_prefix = 0;
3072 break;
3073 case DATA_PREFIX_OPCODE:
3074 implied_prefix = 1;
3075 break;
3076 case REPE_PREFIX_OPCODE:
3077 implied_prefix = 2;
3078 break;
3079 case REPNE_PREFIX_OPCODE:
3080 implied_prefix = 3;
3081 break;
3082 default:
3083 abort ();
3084 }
3085
3086 /* Use 2-byte VEX prefix if possible. */
7f399153 3087 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3088 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3089 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3090 {
3091 /* 2-byte VEX prefix. */
3092 unsigned int r;
3093
3094 i.vex.length = 2;
3095 i.vex.bytes[0] = 0xc5;
3096
3097 /* Check the REX.R bit. */
3098 r = (i.rex & REX_R) ? 0 : 1;
3099 i.vex.bytes[1] = (r << 7
3100 | register_specifier << 3
3101 | vector_length << 2
3102 | implied_prefix);
3103 }
3104 else
3105 {
3106 /* 3-byte VEX prefix. */
3107 unsigned int m, w;
3108
f88c9eb0 3109 i.vex.length = 3;
f88c9eb0 3110
7f399153 3111 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3112 {
7f399153
L		 3113 case VEX0F:
3114 m = 0x1;
80de6e00 3115 i.vex.bytes[0] = 0xc4;
7f399153
L		 3116 break;
3117 case VEX0F38:
3118 m = 0x2;
80de6e00 3119 i.vex.bytes[0] = 0xc4;
7f399153
L		 3120 break;
3121 case VEX0F3A:
3122 m = 0x3;
80de6e00 3123 i.vex.bytes[0] = 0xc4;
7f399153
L		 3124 break;
3125 case XOP08:
5dd85c99
SP		 3126 m = 0x8;
3127 i.vex.bytes[0] = 0x8f;
7f399153
L		 3128 break;
3129 case XOP09:
f88c9eb0
SP		 3130 m = 0x9;
3131 i.vex.bytes[0] = 0x8f;
7f399153
L		 3132 break;
3133 case XOP0A:
f88c9eb0
SP		 3134 m = 0xa;
3135 i.vex.bytes[0] = 0x8f;
7f399153
L		 3136 break;
3137 default:
3138 abort ();
f88c9eb0 3139 }
c0f3af97 3140
c0f3af97
L		 3141 /* The high 3 bits of the second VEX byte are 1's compliment
3142 of RXB bits from REX. */
3143 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3144
3145 /* Check the REX.W bit. */
3146 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3147 if (i.tm.opcode_modifier.vexw == VEXW1)
3148 w = 1;
c0f3af97
L		 3149
3150 i.vex.bytes[2] = (w << 7
3151 | register_specifier << 3
3152 | vector_length << 2
3153 | implied_prefix);
3154 }
3155}
3156
43234a1e
L		 3157/* Build the EVEX prefix. */
3158
3159static void
3160build_evex_prefix (void)
3161{
3162 unsigned int register_specifier;
3163 unsigned int implied_prefix;
3164 unsigned int m, w;
3165 rex_byte vrex_used = 0;
3166
3167 /* Check register specifier. */
3168 if (i.vex.register_specifier)
3169 {
3170 gas_assert ((i.vrex & REX_X) == 0);
3171
3172 register_specifier = i.vex.register_specifier->reg_num;
3173 if ((i.vex.register_specifier->reg_flags & RegRex))
3174 register_specifier += 8;
3175 /* The upper 16 registers are encoded in the fourth byte of the
3176 EVEX prefix. */
3177 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3178 i.vex.bytes[3] = 0x8;
3179 register_specifier = ~register_specifier & 0xf;
3180 }
3181 else
3182 {
3183 register_specifier = 0xf;
3184
3185 /* Encode upper 16 vector index register in the fourth byte of
3186 the EVEX prefix. */
3187 if (!(i.vrex & REX_X))
3188 i.vex.bytes[3] = 0x8;
3189 else
3190 vrex_used |= REX_X;
3191 }
3192
3193 switch ((i.tm.base_opcode >> 8) & 0xff)
3194 {
3195 case 0:
3196 implied_prefix = 0;
3197 break;
3198 case DATA_PREFIX_OPCODE:
3199 implied_prefix = 1;
3200 break;
3201 case REPE_PREFIX_OPCODE:
3202 implied_prefix = 2;
3203 break;
3204 case REPNE_PREFIX_OPCODE:
3205 implied_prefix = 3;
3206 break;
3207 default:
3208 abort ();
3209 }
3210
3211 /* 4 byte EVEX prefix. */
3212 i.vex.length = 4;
3213 i.vex.bytes[0] = 0x62;
3214
3215 /* mmmm bits. */
3216 switch (i.tm.opcode_modifier.vexopcode)
3217 {
3218 case VEX0F:
3219 m = 1;
3220 break;
3221 case VEX0F38:
3222 m = 2;
3223 break;
3224 case VEX0F3A:
3225 m = 3;
3226 break;
3227 default:
3228 abort ();
3229 break;
3230 }
3231
3232 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3233 bits from REX. */
3234 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3235
3236 /* The fifth bit of the second EVEX byte is 1's compliment of the
3237 REX_R bit in VREX. */
3238 if (!(i.vrex & REX_R))
3239 i.vex.bytes[1] |= 0x10;
3240 else
3241 vrex_used |= REX_R;
3242
3243 if ((i.reg_operands + i.imm_operands) == i.operands)
3244 {
3245 /* When all operands are registers, the REX_X bit in REX is not
3246 used. We reuse it to encode the upper 16 registers, which is
3247 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3248 as 1's compliment. */
3249 if ((i.vrex & REX_B))
3250 {
3251 vrex_used |= REX_B;
3252 i.vex.bytes[1] &= ~0x40;
3253 }
3254 }
3255
3256 /* EVEX instructions shouldn't need the REX prefix. */
3257 i.vrex &= ~vrex_used;
3258 gas_assert (i.vrex == 0);
3259
3260 /* Check the REX.W bit. */
3261 w = (i.rex & REX_W) ? 1 : 0;
3262 if (i.tm.opcode_modifier.vexw)
3263 {
3264 if (i.tm.opcode_modifier.vexw == VEXW1)
3265 w = 1;
3266 }
3267 /* If w is not set it means we are dealing with WIG instruction. */
3268 else if (!w)
3269 {
3270 if (evexwig == evexw1)
3271 w = 1;
3272 }
3273
3274 /* Encode the U bit. */
3275 implied_prefix |= 0x4;
3276
3277 /* The third byte of the EVEX prefix. */
3278 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3279
3280 /* The fourth byte of the EVEX prefix. */
3281 /* The zeroing-masking bit. */
3282 if (i.mask && i.mask->zeroing)
3283 i.vex.bytes[3] |= 0x80;
3284
3285 /* Don't always set the broadcast bit if there is no RC. */
3286 if (!i.rounding)
3287 {
3288 /* Encode the vector length. */
3289 unsigned int vec_length;
3290
3291 switch (i.tm.opcode_modifier.evex)
3292 {
3293 case EVEXLIG: /* LL' is ignored */
3294 vec_length = evexlig << 5;
3295 break;
3296 case EVEX128:
3297 vec_length = 0 << 5;
3298 break;
3299 case EVEX256:
3300 vec_length = 1 << 5;
3301 break;
3302 case EVEX512:
3303 vec_length = 2 << 5;
3304 break;
3305 default:
3306 abort ();
3307 break;
3308 }
3309 i.vex.bytes[3] |= vec_length;
3310 /* Encode the broadcast bit. */
3311 if (i.broadcast)
3312 i.vex.bytes[3] |= 0x10;
3313 }
3314 else
3315 {
3316 if (i.rounding->type != saeonly)
3317 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3318 else
d3d3c6db 3319 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3320 }
3321
3322 if (i.mask && i.mask->mask)
3323 i.vex.bytes[3] |= i.mask->mask->reg_num;
3324}
3325
65da13b5
L		 3326static void
3327process_immext (void)
3328{
3329 expressionS *exp;
3330
4c692bc7
JB		 3331 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3332 && i.operands > 0)
65da13b5 3333 {
4c692bc7
JB		 3334 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3335 with an opcode suffix which is coded in the same place as an
3336 8-bit immediate field would be.
3337 Here we check those operands and remove them afterwards. */
65da13b5
L		 3338 unsigned int x;
3339
3340 for (x = 0; x < i.operands; x++)
4c692bc7 3341 if (register_number (i.op[x].regs) != x)
65da13b5 3342 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3343 register_prefix, i.op[x].regs->reg_name, x + 1,
3344 i.tm.name);
3345
3346 i.operands = 0;
65da13b5
L		 3347 }
3348
9916071f
AP		 3349 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3350 {
3351 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3352 suffix which is coded in the same place as an 8-bit immediate
3353 field would be.
3354 Here we check those operands and remove them afterwards. */
3355 unsigned int x;
3356
3357 if (i.operands != 3)
3358 abort();
3359
3360 for (x = 0; x < 2; x++)
3361 if (register_number (i.op[x].regs) != x)
3362 goto bad_register_operand;
3363
3364 /* Check for third operand for mwaitx/monitorx insn. */
3365 if (register_number (i.op[x].regs)
3366 != (x + (i.tm.extension_opcode == 0xfb)))
3367 {
3368bad_register_operand:
3369 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3370 register_prefix, i.op[x].regs->reg_name, x+1,
3371 i.tm.name);
3372 }
3373
3374 i.operands = 0;
3375 }
3376
c0f3af97 3377 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3378 which is coded in the same place as an 8-bit immediate field
3379 would be. Here we fake an 8-bit immediate operand from the
3380 opcode suffix stored in tm.extension_opcode.
3381
c1e679ec 3382 AVX instructions also use this encoding, for some of
c0f3af97 3383 3 argument instructions. */
65da13b5 3384
43234a1e 3385 gas_assert (i.imm_operands <= 1
7ab9ffdd 3386 && (i.operands <= 2
43234a1e
L		 3387 || ((i.tm.opcode_modifier.vex
3388 || i.tm.opcode_modifier.evex)
7ab9ffdd 3389 && i.operands <= 4)));
65da13b5
L		 3390
3391 exp = &im_expressions[i.imm_operands++];
3392 i.op[i.operands].imms = exp;
3393 i.types[i.operands] = imm8;
3394 i.operands++;
3395 exp->X_op = O_constant;
3396 exp->X_add_number = i.tm.extension_opcode;
3397 i.tm.extension_opcode = None;
3398}
3399
42164a71
L		 3400
3401static int
3402check_hle (void)
3403{
3404 switch (i.tm.opcode_modifier.hleprefixok)
3405 {
3406 default:
3407 abort ();
82c2def5 3408 case HLEPrefixNone:
165de32a
L		 3409 as_bad (_("invalid instruction `%s' after `%s'"),
3410 i.tm.name, i.hle_prefix);
42164a71 3411 return 0;
82c2def5 3412 case HLEPrefixLock:
42164a71
L		 3413 if (i.prefix[LOCK_PREFIX])
3414 return 1;
165de32a 3415 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3416 return 0;
82c2def5 3417 case HLEPrefixAny:
42164a71 3418 return 1;
82c2def5 3419 case HLEPrefixRelease:
42164a71
L		 3420 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3421 {
3422 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3423 i.tm.name);
3424 return 0;
3425 }
3426 if (i.mem_operands == 0
3427 || !operand_type_check (i.types[i.operands - 1], anymem))
3428 {
3429 as_bad (_("memory destination needed for instruction `%s'"
3430 " after `xrelease'"), i.tm.name);
3431 return 0;
3432 }
3433 return 1;
3434 }
3435}
3436
252b5132
RH		 3437/* This is the guts of the machine-dependent assembler. LINE points to a
3438 machine dependent instruction. This function is supposed to emit
3439 the frags/bytes it assembles to. */
3440
3441void
65da13b5 3442md_assemble (char *line)
252b5132 3443{
40fb9820 3444 unsigned int j;
252b5132 3445 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3446 const insn_template *t;
252b5132 3447
47926f60 3448 /* Initialize globals. */
252b5132
RH		 3449 memset (&i, '\0', sizeof (i));
3450 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3451 i.reloc[j] = NO_RELOC;
252b5132
RH		 3452 memset (disp_expressions, '\0', sizeof (disp_expressions));
3453 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3454 save_stack_p = save_stack;
252b5132
RH		 3455
3456 /* First parse an instruction mnemonic & call i386_operand for the operands.
3457 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3458 start of a (possibly prefixed) mnemonic. */
252b5132 3459
29b0f896
AM		 3460 line = parse_insn (line, mnemonic);
3461 if (line == NULL)
3462 return;
252b5132 3463
29b0f896 3464 line = parse_operands (line, mnemonic);
ee86248c 3465 this_operand = -1;
29b0f896
AM		 3466 if (line == NULL)
3467 return;
252b5132 3468
29b0f896
AM		 3469 /* Now we've parsed the mnemonic into a set of templates, and have the
3470 operands at hand. */
3471
3472 /* All intel opcodes have reversed operands except for "bound" and
3473 "enter". We also don't reverse intersegment "jmp" and "call"
3474 instructions with 2 immediate operands so that the immediate segment
050dfa73 3475 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3476 if (intel_syntax
3477 && i.operands > 1
29b0f896 3478 && (strcmp (mnemonic, "bound") != 0)
30123838 3479 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3480 && !(operand_type_check (i.types[0], imm)
3481 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3482 swap_operands ();
3483
ec56d5c0
JB		 3484 /* The order of the immediates should be reversed
3485 for 2 immediates extrq and insertq instructions */
3486 if (i.imm_operands == 2
3487 && (strcmp (mnemonic, "extrq") == 0
3488 || strcmp (mnemonic, "insertq") == 0))
3489 swap_2_operands (0, 1);
3490
29b0f896
AM		 3491 if (i.imm_operands)
3492 optimize_imm ();
3493
b300c311
L		 3494 /* Don't optimize displacement for movabs since it only takes 64bit
3495 displacement. */
3496 if (i.disp_operands
a501d77e 3497 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3498 && (flag_code != CODE_64BIT
3499 || strcmp (mnemonic, "movabs") != 0))
3500 optimize_disp ();
29b0f896
AM		 3501
3502 /* Next, we find a template that matches the given insn,
3503 making sure the overlap of the given operands types is consistent
3504 with the template operand types. */
252b5132 3505
fa99fab2 3506 if (!(t = match_template ()))
29b0f896 3507 return;
252b5132 3508
7bab8ab5 3509 if (sse_check != check_none
81f8a913 3510 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3511 && (i.tm.cpu_flags.bitfield.cpusse
3512 || i.tm.cpu_flags.bitfield.cpusse2
3513 || i.tm.cpu_flags.bitfield.cpusse3
3514 || i.tm.cpu_flags.bitfield.cpussse3
3515 || i.tm.cpu_flags.bitfield.cpusse4_1
3516 || i.tm.cpu_flags.bitfield.cpusse4_2))
3517 {
7bab8ab5 3518 (sse_check == check_warning
daf50ae7
L		 3519 ? as_warn
3520 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3521 }
3522
321fd21e
L		 3523 /* Zap movzx and movsx suffix. The suffix has been set from
3524 "word ptr" or "byte ptr" on the source operand in Intel syntax
3525 or extracted from mnemonic in AT&T syntax. But we'll use
3526 the destination register to choose the suffix for encoding. */
3527 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3528 {
321fd21e
L		 3529 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3530 there is no suffix, the default will be byte extension. */
3531 if (i.reg_operands != 2
3532 && !i.suffix
7ab9ffdd 3533 && intel_syntax)
321fd21e
L		 3534 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3535
3536 i.suffix = 0;
cd61ebfe 3537 }
24eab124 3538
40fb9820 3539 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3540 if (!add_prefix (FWAIT_OPCODE))
3541 return;
252b5132 3542
d5de92cf
L		 3543 /* Check if REP prefix is OK. */
3544 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3545 {
3546 as_bad (_("invalid instruction `%s' after `%s'"),
3547 i.tm.name, i.rep_prefix);
3548 return;
3549 }
3550
c1ba0266
L		 3551 /* Check for lock without a lockable instruction. Destination operand
3552 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3553 if (i.prefix[LOCK_PREFIX]
3554 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3555 || i.mem_operands == 0
3556 || (i.tm.base_opcode != 0x86
3557 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3558 {
3559 as_bad (_("expecting lockable instruction after `lock'"));
3560 return;
3561 }
3562
42164a71 3563 /* Check if HLE prefix is OK. */
165de32a 3564 if (i.hle_prefix && !check_hle ())
42164a71
L		 3565 return;
3566
7e8b059b
L		 3567 /* Check BND prefix. */
3568 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3569 as_bad (_("expecting valid branch instruction after `bnd'"));
3570
3571 if (i.tm.cpu_flags.bitfield.cpumpx
3572 && flag_code == CODE_64BIT
3573 && i.prefix[ADDR_PREFIX])
3574 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3575
3576 /* Insert BND prefix. */
3577 if (add_bnd_prefix
3578 && i.tm.opcode_modifier.bndprefixok
3579 && !i.prefix[BND_PREFIX])
3580 add_prefix (BND_PREFIX_OPCODE);
3581
29b0f896 3582 /* Check string instruction segment overrides. */
40fb9820 3583 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3584 {
3585 if (!check_string ())
5dd0794d 3586 return;
fc0763e6 3587 i.disp_operands = 0;
29b0f896 3588 }
5dd0794d 3589
29b0f896
AM		 3590 if (!process_suffix ())
3591 return;
e413e4e9 3592
bc0844ae
L		 3593 /* Update operand types. */
3594 for (j = 0; j < i.operands; j++)
3595 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3596
29b0f896
AM		 3597 /* Make still unresolved immediate matches conform to size of immediate
3598 given in i.suffix. */
3599 if (!finalize_imm ())
3600 return;
252b5132 3601
40fb9820 3602 if (i.types[0].bitfield.imm1)
29b0f896 3603 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3604
9afe6eb8
L		 3605 /* We only need to check those implicit registers for instructions
3606 with 3 operands or less. */
3607 if (i.operands <= 3)
3608 for (j = 0; j < i.operands; j++)
3609 if (i.types[j].bitfield.inoutportreg
3610 || i.types[j].bitfield.shiftcount
3611 || i.types[j].bitfield.acc
3612 || i.types[j].bitfield.floatacc)
3613 i.reg_operands--;
40fb9820 3614
c0f3af97
L		 3615 /* ImmExt should be processed after SSE2AVX. */
3616 if (!i.tm.opcode_modifier.sse2avx
3617 && i.tm.opcode_modifier.immext)
65da13b5 3618 process_immext ();
252b5132 3619
29b0f896
AM		 3620 /* For insns with operands there are more diddles to do to the opcode. */
3621 if (i.operands)
3622 {
3623 if (!process_operands ())
3624 return;
3625 }
40fb9820 3626 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3627 {
3628 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3629 as_warn (_("translating to `%sp'"), i.tm.name);
3630 }
252b5132 3631
9e5e5283
L		 3632 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3633 {
3634 if (flag_code == CODE_16BIT)
3635 {
3636 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3637 i.tm.name);
3638 return;
3639 }
c0f3af97 3640
9e5e5283
L		 3641 if (i.tm.opcode_modifier.vex)
3642 build_vex_prefix (t);
3643 else
3644 build_evex_prefix ();
3645 }
43234a1e 3646
5dd85c99
SP		 3647 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3648 instructions may define INT_OPCODE as well, so avoid this corner
3649 case for those instructions that use MODRM. */
3650 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3651 && !i.tm.opcode_modifier.modrm
3652 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3653 {
3654 i.tm.base_opcode = INT3_OPCODE;
3655 i.imm_operands = 0;
3656 }
252b5132 3657
40fb9820
L		 3658 if ((i.tm.opcode_modifier.jump
3659 || i.tm.opcode_modifier.jumpbyte
3660 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3661 && i.op[0].disps->X_op == O_constant)
3662 {
3663 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3664 the absolute address given by the constant. Since ix86 jumps and
3665 calls are pc relative, we need to generate a reloc. */
3666 i.op[0].disps->X_add_symbol = &abs_symbol;
3667 i.op[0].disps->X_op = O_symbol;
3668 }
252b5132 3669
40fb9820 3670 if (i.tm.opcode_modifier.rex64)
161a04f6 3671 i.rex |= REX_W;
252b5132 3672
29b0f896
AM		 3673 /* For 8 bit registers we need an empty rex prefix. Also if the
3674 instruction already has a prefix, we need to convert old
3675 registers to new ones. */
773f551c 3676
40fb9820 3677 if ((i.types[0].bitfield.reg8
29b0f896 3678 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3679 || (i.types[1].bitfield.reg8
29b0f896 3680 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3681 || ((i.types[0].bitfield.reg8
3682 || i.types[1].bitfield.reg8)
29b0f896
AM		 3683 && i.rex != 0))
3684 {
3685 int x;
726c5dcd 3686
29b0f896
AM		 3687 i.rex |= REX_OPCODE;
3688 for (x = 0; x < 2; x++)
3689 {
3690 /* Look for 8 bit operand that uses old registers. */
40fb9820 3691 if (i.types[x].bitfield.reg8
29b0f896 3692 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3693 {
29b0f896
AM		 3694 /* In case it is "hi" register, give up. */
3695 if (i.op[x].regs->reg_num > 3)
a540244d 3696 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3697 "instruction requiring REX prefix."),
a540244d 3698 register_prefix, i.op[x].regs->reg_name);
773f551c 3699
29b0f896
AM		 3700 /* Otherwise it is equivalent to the extended register.
3701 Since the encoding doesn't change this is merely
3702 cosmetic cleanup for debug output. */
3703
3704 i.op[x].regs = i.op[x].regs + 8;
773f551c 3705 }
29b0f896
AM		 3706 }
3707 }
773f551c 3708
7ab9ffdd 3709 if (i.rex != 0)
29b0f896
AM		 3710 add_prefix (REX_OPCODE | i.rex);
3711
3712 /* We are ready to output the insn. */
3713 output_insn ();
3714}
3715
3716static char *
e3bb37b5 3717parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3718{
3719 char *l = line;
3720 char *token_start = l;
3721 char *mnem_p;
5c6af06e 3722 int supported;
d3ce72d0 3723 const insn_template *t;
b6169b20 3724 char *dot_p = NULL;
29b0f896 3725
29b0f896
AM		 3726 while (1)
3727 {
3728 mnem_p = mnemonic;
3729 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3730 {
b6169b20
L		 3731 if (*mnem_p == '.')
3732 dot_p = mnem_p;
29b0f896
AM		 3733 mnem_p++;
3734 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3735 {
29b0f896
AM		 3736 as_bad (_("no such instruction: `%s'"), token_start);
3737 return NULL;
3738 }
3739 l++;
3740 }
3741 if (!is_space_char (*l)
3742 && *l != END_OF_INSN
e44823cf
JB		 3743 && (intel_syntax
3744 || (*l != PREFIX_SEPARATOR
3745 && *l != ',')))
29b0f896
AM		 3746 {
3747 as_bad (_("invalid character %s in mnemonic"),
3748 output_invalid (*l));
3749 return NULL;
3750 }
3751 if (token_start == l)
3752 {
e44823cf 3753 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3754 as_bad (_("expecting prefix; got nothing"));
3755 else
3756 as_bad (_("expecting mnemonic; got nothing"));
3757 return NULL;
3758 }
45288df1 3759
29b0f896 3760 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3761 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3762
29b0f896
AM		 3763 if (*l != END_OF_INSN
3764 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3765 && current_templates
40fb9820 3766 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3767 {
c6fb90c8 3768 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3769 {
3770 as_bad ((flag_code != CODE_64BIT
3771 ? _("`%s' is only supported in 64-bit mode")
3772 : _("`%s' is not supported in 64-bit mode")),
3773 current_templates->start->name);
3774 return NULL;
3775 }
29b0f896
AM		 3776 /* If we are in 16-bit mode, do not allow addr16 or data16.
3777 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3778 if ((current_templates->start->opcode_modifier.size16
3779 || current_templates->start->opcode_modifier.size32)
29b0f896 3780 && flag_code != CODE_64BIT
40fb9820 3781 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3782 ^ (flag_code == CODE_16BIT)))
3783 {
3784 as_bad (_("redundant %s prefix"),
3785 current_templates->start->name);
3786 return NULL;
45288df1 3787 }
29b0f896
AM		 3788 /* Add prefix, checking for repeated prefixes. */
3789 switch (add_prefix (current_templates->start->base_opcode))
3790 {
c32fa91d 3791 case PREFIX_EXIST:
29b0f896 3792 return NULL;
c32fa91d 3793 case PREFIX_REP:
42164a71 3794 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3795 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3796 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3797 i.bnd_prefix = current_templates->start->name;
42164a71 3798 else
d5de92cf 3799 i.rep_prefix = current_templates->start->name;
29b0f896 3800 break;
c32fa91d
L		 3801 default:
3802 break;
29b0f896
AM		 3803 }
3804 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3805 token_start = ++l;
3806 }
3807 else
3808 break;
3809 }
45288df1 3810
30a55f88 3811 if (!current_templates)
b6169b20 3812 {
f8a5c266
L		 3813 /* Check if we should swap operand or force 32bit displacement in
3814 encoding. */
30a55f88
L		 3815 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3816 i.swap_operand = 1;
8d63c93e 3817 else if (mnem_p - 3 == dot_p
a501d77e
L		 3818 && dot_p[1] == 'd'
3819 && dot_p[2] == '8')
3820 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3821 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3822 && dot_p[1] == 'd'
3823 && dot_p[2] == '3'
3824 && dot_p[3] == '2')
a501d77e 3825 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3826 else
3827 goto check_suffix;
3828 mnem_p = dot_p;
3829 *dot_p = '\0';
d3ce72d0 3830 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3831 }
3832
29b0f896
AM		 3833 if (!current_templates)
3834 {
b6169b20 3835check_suffix:
29b0f896
AM		 3836 /* See if we can get a match by trimming off a suffix. */
3837 switch (mnem_p[-1])
3838 {
3839 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3840 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3841 i.suffix = SHORT_MNEM_SUFFIX;
3842 else
29b0f896
AM		 3843 case BYTE_MNEM_SUFFIX:
3844 case QWORD_MNEM_SUFFIX:
3845 i.suffix = mnem_p[-1];
3846 mnem_p[-1] = '\0';
d3ce72d0
NC		 3847 current_templates = (const templates *) hash_find (op_hash,
3848 mnemonic);
29b0f896
AM		 3849 break;
3850 case SHORT_MNEM_SUFFIX:
3851 case LONG_MNEM_SUFFIX:
3852 if (!intel_syntax)
3853 {
3854 i.suffix = mnem_p[-1];
3855 mnem_p[-1] = '\0';
d3ce72d0
NC		 3856 current_templates = (const templates *) hash_find (op_hash,
3857 mnemonic);
29b0f896
AM		 3858 }
3859 break;
252b5132 3860
29b0f896
AM		 3861 /* Intel Syntax. */
3862 case 'd':
3863 if (intel_syntax)
3864 {
9306ca4a 3865 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3866 i.suffix = SHORT_MNEM_SUFFIX;
3867 else
3868 i.suffix = LONG_MNEM_SUFFIX;
3869 mnem_p[-1] = '\0';
d3ce72d0
NC		 3870 current_templates = (const templates *) hash_find (op_hash,
3871 mnemonic);
29b0f896
AM		 3872 }
3873 break;
3874 }
3875 if (!current_templates)
3876 {
3877 as_bad (_("no such instruction: `%s'"), token_start);
3878 return NULL;
3879 }
3880 }
252b5132 3881
40fb9820
L		 3882 if (current_templates->start->opcode_modifier.jump
3883 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3884 {
3885 /* Check for a branch hint. We allow ",pt" and ",pn" for
3886 predict taken and predict not taken respectively.
3887 I'm not sure that branch hints actually do anything on loop
3888 and jcxz insns (JumpByte) for current Pentium4 chips. They
3889 may work in the future and it doesn't hurt to accept them
3890 now. */
3891 if (l[0] == ',' && l[1] == 'p')
3892 {
3893 if (l[2] == 't')
3894 {
3895 if (!add_prefix (DS_PREFIX_OPCODE))
3896 return NULL;
3897 l += 3;
3898 }
3899 else if (l[2] == 'n')
3900 {
3901 if (!add_prefix (CS_PREFIX_OPCODE))
3902 return NULL;
3903 l += 3;
3904 }
3905 }
3906 }
3907 /* Any other comma loses. */
3908 if (*l == ',')
3909 {
3910 as_bad (_("invalid character %s in mnemonic"),
3911 output_invalid (*l));
3912 return NULL;
3913 }
252b5132 3914
29b0f896 3915 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3916 supported = 0;
3917 for (t = current_templates->start; t < current_templates->end; ++t)
3918 {
c0f3af97
L		 3919 supported |= cpu_flags_match (t);
3920 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3921 goto skip;
5c6af06e 3922 }
3629bb00 3923
c0f3af97 3924 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3925 {
3926 as_bad (flag_code == CODE_64BIT
3927 ? _("`%s' is not supported in 64-bit mode")
3928 : _("`%s' is only supported in 64-bit mode"),
3929 current_templates->start->name);
3930 return NULL;
3931 }
c0f3af97 3932 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3933 {
3629bb00 3934 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3935 current_templates->start->name,
41aacd83 3936 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3937 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3938 return NULL;
29b0f896 3939 }
3629bb00
L		 3940
3941skip:
3942 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3943 && (flag_code != CODE_16BIT))
29b0f896
AM		 3944 {
3945 as_warn (_("use .code16 to ensure correct addressing mode"));
3946 }
252b5132 3947
29b0f896
AM		 3948 return l;
3949}
252b5132 3950
29b0f896 3951static char *
e3bb37b5 3952parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3953{
3954 char *token_start;
3138f287 3955
29b0f896
AM		 3956 /* 1 if operand is pending after ','. */
3957 unsigned int expecting_operand = 0;
252b5132 3958
29b0f896
AM		 3959 /* Non-zero if operand parens not balanced. */
3960 unsigned int paren_not_balanced;
3961
3962 while (*l != END_OF_INSN)
3963 {
3964 /* Skip optional white space before operand. */
3965 if (is_space_char (*l))
3966 ++l;
d02603dc 3967 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 3968 {
3969 as_bad (_("invalid character %s before operand %d"),
3970 output_invalid (*l),
3971 i.operands + 1);
3972 return NULL;
3973 }
d02603dc 3974 token_start = l; /* After white space. */
29b0f896
AM		 3975 paren_not_balanced = 0;
3976 while (paren_not_balanced || *l != ',')
3977 {
3978 if (*l == END_OF_INSN)
3979 {
3980 if (paren_not_balanced)
3981 {
3982 if (!intel_syntax)
3983 as_bad (_("unbalanced parenthesis in operand %d."),
3984 i.operands + 1);
3985 else
3986 as_bad (_("unbalanced brackets in operand %d."),
3987 i.operands + 1);
3988 return NULL;
3989 }
3990 else
3991 break; /* we are done */
3992 }
d02603dc 3993 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 3994 {
3995 as_bad (_("invalid character %s in operand %d"),
3996 output_invalid (*l),
3997 i.operands + 1);
3998 return NULL;
3999 }
4000 if (!intel_syntax)
4001 {
4002 if (*l == '(')
4003 ++paren_not_balanced;
4004 if (*l == ')')
4005 --paren_not_balanced;
4006 }
4007 else
4008 {
4009 if (*l == '[')
4010 ++paren_not_balanced;
4011 if (*l == ']')
4012 --paren_not_balanced;
4013 }
4014 l++;
4015 }
4016 if (l != token_start)
4017 { /* Yes, we've read in another operand. */
4018 unsigned int operand_ok;
4019 this_operand = i.operands++;
7d5e4556 4020 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4021 if (i.operands > MAX_OPERANDS)
4022 {
4023 as_bad (_("spurious operands; (%d operands/instruction max)"),
4024 MAX_OPERANDS);
4025 return NULL;
4026 }
4027 /* Now parse operand adding info to 'i' as we go along. */
4028 END_STRING_AND_SAVE (l);
4029
4030 if (intel_syntax)
4031 operand_ok =
4032 i386_intel_operand (token_start,
4033 intel_float_operand (mnemonic));
4034 else
a7619375 4035 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4036
4037 RESTORE_END_STRING (l);
4038 if (!operand_ok)
4039 return NULL;
4040 }
4041 else
4042 {
4043 if (expecting_operand)
4044 {
4045 expecting_operand_after_comma:
4046 as_bad (_("expecting operand after ','; got nothing"));
4047 return NULL;
4048 }
4049 if (*l == ',')
4050 {
4051 as_bad (_("expecting operand before ','; got nothing"));
4052 return NULL;
4053 }
4054 }
7f3f1ea2 4055
29b0f896
AM		 4056 /* Now *l must be either ',' or END_OF_INSN. */
4057 if (*l == ',')
4058 {
4059 if (*++l == END_OF_INSN)
4060 {
4061 /* Just skip it, if it's \n complain. */
4062 goto expecting_operand_after_comma;
4063 }
4064 expecting_operand = 1;
4065 }
4066 }
4067 return l;
4068}
7f3f1ea2 4069
050dfa73 4070static void
4d456e3d 4071swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4072{
4073 union i386_op temp_op;
40fb9820 4074 i386_operand_type temp_type;
050dfa73 4075 enum bfd_reloc_code_real temp_reloc;
4eed87de 4076
050dfa73
MM		 4077 temp_type = i.types[xchg2];
4078 i.types[xchg2] = i.types[xchg1];
4079 i.types[xchg1] = temp_type;
4080 temp_op = i.op[xchg2];
4081 i.op[xchg2] = i.op[xchg1];
4082 i.op[xchg1] = temp_op;
4083 temp_reloc = i.reloc[xchg2];
4084 i.reloc[xchg2] = i.reloc[xchg1];
4085 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4086
4087 if (i.mask)
4088 {
4089 if (i.mask->operand == xchg1)
4090 i.mask->operand = xchg2;
4091 else if (i.mask->operand == xchg2)
4092 i.mask->operand = xchg1;
4093 }
4094 if (i.broadcast)
4095 {
4096 if (i.broadcast->operand == xchg1)
4097 i.broadcast->operand = xchg2;
4098 else if (i.broadcast->operand == xchg2)
4099 i.broadcast->operand = xchg1;
4100 }
4101 if (i.rounding)
4102 {
4103 if (i.rounding->operand == xchg1)
4104 i.rounding->operand = xchg2;
4105 else if (i.rounding->operand == xchg2)
4106 i.rounding->operand = xchg1;
4107 }
050dfa73
MM		 4108}
4109
29b0f896 4110static void
e3bb37b5 4111swap_operands (void)
29b0f896 4112{
b7c61d9a 4113 switch (i.operands)
050dfa73 4114 {
c0f3af97 4115 case 5:
b7c61d9a 4116 case 4:
4d456e3d 4117 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4118 case 3:
4119 case 2:
4d456e3d 4120 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4121 break;
4122 default:
4123 abort ();
29b0f896 4124 }
29b0f896
AM		 4125
4126 if (i.mem_operands == 2)
4127 {
4128 const seg_entry *temp_seg;
4129 temp_seg = i.seg[0];
4130 i.seg[0] = i.seg[1];
4131 i.seg[1] = temp_seg;
4132 }
4133}
252b5132 4134
29b0f896
AM		 4135/* Try to ensure constant immediates are represented in the smallest
4136 opcode possible. */
4137static void
e3bb37b5 4138optimize_imm (void)
29b0f896
AM		 4139{
4140 char guess_suffix = 0;
4141 int op;
252b5132 4142
29b0f896
AM		 4143 if (i.suffix)
4144 guess_suffix = i.suffix;
4145 else if (i.reg_operands)
4146 {
4147 /* Figure out a suffix from the last register operand specified.
4148 We can't do this properly yet, ie. excluding InOutPortReg,
4149 but the following works for instructions with immediates.
4150 In any case, we can't set i.suffix yet. */
4151 for (op = i.operands; --op >= 0;)
40fb9820 4152 if (i.types[op].bitfield.reg8)
7ab9ffdd 4153 {
40fb9820
L		 4154 guess_suffix = BYTE_MNEM_SUFFIX;
4155 break;
4156 }
4157 else if (i.types[op].bitfield.reg16)
252b5132 4158 {
40fb9820
L		 4159 guess_suffix = WORD_MNEM_SUFFIX;
4160 break;
4161 }
4162 else if (i.types[op].bitfield.reg32)
4163 {
4164 guess_suffix = LONG_MNEM_SUFFIX;
4165 break;
4166 }
4167 else if (i.types[op].bitfield.reg64)
4168 {
4169 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4170 break;
252b5132 4171 }
29b0f896
AM		 4172 }
4173 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4174 guess_suffix = WORD_MNEM_SUFFIX;
4175
4176 for (op = i.operands; --op >= 0;)
40fb9820 4177 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4178 {
4179 switch (i.op[op].imms->X_op)
252b5132 4180 {
29b0f896
AM		 4181 case O_constant:
4182 /* If a suffix is given, this operand may be shortened. */
4183 switch (guess_suffix)
252b5132 4184 {
29b0f896 4185 case LONG_MNEM_SUFFIX:
40fb9820
L		 4186 i.types[op].bitfield.imm32 = 1;
4187 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4188 break;
4189 case WORD_MNEM_SUFFIX:
40fb9820
L		 4190 i.types[op].bitfield.imm16 = 1;
4191 i.types[op].bitfield.imm32 = 1;
4192 i.types[op].bitfield.imm32s = 1;
4193 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4194 break;
4195 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4196 i.types[op].bitfield.imm8 = 1;
4197 i.types[op].bitfield.imm8s = 1;
4198 i.types[op].bitfield.imm16 = 1;
4199 i.types[op].bitfield.imm32 = 1;
4200 i.types[op].bitfield.imm32s = 1;
4201 i.types[op].bitfield.imm64 = 1;
29b0f896 4202 break;
252b5132 4203 }
252b5132 4204
29b0f896
AM		 4205 /* If this operand is at most 16 bits, convert it
4206 to a signed 16 bit number before trying to see
4207 whether it will fit in an even smaller size.
4208 This allows a 16-bit operand such as $0xffe0 to
4209 be recognised as within Imm8S range. */
40fb9820 4210 if ((i.types[op].bitfield.imm16)
29b0f896 4211 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4212 {
29b0f896
AM		 4213 i.op[op].imms->X_add_number =
4214 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4215 }
40fb9820 4216 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4217 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4218 == 0))
4219 {
4220 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4221 ^ ((offsetT) 1 << 31))
4222 - ((offsetT) 1 << 31));
4223 }
40fb9820 4224 i.types[op]
c6fb90c8
L		 4225 = operand_type_or (i.types[op],
4226 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4227
29b0f896
AM		 4228 /* We must avoid matching of Imm32 templates when 64bit
4229 only immediate is available. */
4230 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4231 i.types[op].bitfield.imm32 = 0;
29b0f896 4232 break;
252b5132 4233
29b0f896
AM		 4234 case O_absent:
4235 case O_register:
4236 abort ();
4237
4238 /* Symbols and expressions. */
4239 default:
9cd96992
JB		 4240 /* Convert symbolic operand to proper sizes for matching, but don't
4241 prevent matching a set of insns that only supports sizes other
4242 than those matching the insn suffix. */
4243 {
40fb9820 4244 i386_operand_type mask, allowed;
d3ce72d0 4245 const insn_template *t;
9cd96992 4246
0dfbf9d7
L		 4247 operand_type_set (&mask, 0);
4248 operand_type_set (&allowed, 0);
40fb9820 4249
4eed87de
AM		 4250 for (t = current_templates->start;
4251 t < current_templates->end;
4252 ++t)
c6fb90c8
L		 4253 allowed = operand_type_or (allowed,
4254 t->operand_types[op]);
9cd96992
JB		 4255 switch (guess_suffix)
4256 {
4257 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4258 mask.bitfield.imm64 = 1;
4259 mask.bitfield.imm32s = 1;
9cd96992
JB		 4260 break;
4261 case LONG_MNEM_SUFFIX:
40fb9820 4262 mask.bitfield.imm32 = 1;
9cd96992
JB		 4263 break;
4264 case WORD_MNEM_SUFFIX:
40fb9820 4265 mask.bitfield.imm16 = 1;
9cd96992
JB		 4266 break;
4267 case BYTE_MNEM_SUFFIX:
40fb9820 4268 mask.bitfield.imm8 = 1;
9cd96992
JB		 4269 break;
4270 default:
9cd96992
JB		 4271 break;
4272 }
c6fb90c8 4273 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4274 if (!operand_type_all_zero (&allowed))
c6fb90c8 4275 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4276 }
29b0f896 4277 break;
252b5132 4278 }
29b0f896
AM		 4279 }
4280}
47926f60 4281
29b0f896
AM		 4282/* Try to use the smallest displacement type too. */
4283static void
e3bb37b5 4284optimize_disp (void)
29b0f896
AM		 4285{
4286 int op;
3e73aa7c 4287
29b0f896 4288 for (op = i.operands; --op >= 0;)
40fb9820 4289 if (operand_type_check (i.types[op], disp))
252b5132 4290 {
b300c311 4291 if (i.op[op].disps->X_op == O_constant)
252b5132 4292 {
91d6fa6a 4293 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4294
40fb9820 4295 if (i.types[op].bitfield.disp16
91d6fa6a 4296 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4297 {
4298 /* If this operand is at most 16 bits, convert
4299 to a signed 16 bit number and don't use 64bit
4300 displacement. */
91d6fa6a 4301 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4302 i.types[op].bitfield.disp64 = 0;
b300c311 4303 }
40fb9820 4304 if (i.types[op].bitfield.disp32
91d6fa6a 4305 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4306 {
4307 /* If this operand is at most 32 bits, convert
4308 to a signed 32 bit number and don't use 64bit
4309 displacement. */
91d6fa6a
NC		 4310 op_disp &= (((offsetT) 2 << 31) - 1);
4311 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4312 i.types[op].bitfield.disp64 = 0;
b300c311 4313 }
91d6fa6a 4314 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4315 {
40fb9820
L		 4316 i.types[op].bitfield.disp8 = 0;
4317 i.types[op].bitfield.disp16 = 0;
4318 i.types[op].bitfield.disp32 = 0;
4319 i.types[op].bitfield.disp32s = 0;
4320 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4321 i.op[op].disps = 0;
4322 i.disp_operands--;
4323 }
4324 else if (flag_code == CODE_64BIT)
4325 {
91d6fa6a 4326 if (fits_in_signed_long (op_disp))
28a9d8f5 4327 {
40fb9820
L		 4328 i.types[op].bitfield.disp64 = 0;
4329 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4330 }
0e1147d9 4331 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4332 && fits_in_unsigned_long (op_disp))
40fb9820 4333 i.types[op].bitfield.disp32 = 1;
b300c311 4334 }
40fb9820
L		 4335 if ((i.types[op].bitfield.disp32
4336 || i.types[op].bitfield.disp32s
4337 || i.types[op].bitfield.disp16)
91d6fa6a 4338 && fits_in_signed_byte (op_disp))
40fb9820 4339 i.types[op].bitfield.disp8 = 1;
252b5132 4340 }
67a4f2b7
AO		 4341 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4342 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4343 {
4344 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4345 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4346 i.types[op].bitfield.disp8 = 0;
4347 i.types[op].bitfield.disp16 = 0;
4348 i.types[op].bitfield.disp32 = 0;
4349 i.types[op].bitfield.disp32s = 0;
4350 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4351 }
4352 else
b300c311 4353 /* We only support 64bit displacement on constants. */
40fb9820 4354 i.types[op].bitfield.disp64 = 0;
252b5132 4355 }
29b0f896
AM		 4356}
4357
6c30d220
L		 4358/* Check if operands are valid for the instruction. */
4359
4360static int
4361check_VecOperands (const insn_template *t)
4362{
43234a1e
L		 4363 unsigned int op;
4364
6c30d220
L		 4365 /* Without VSIB byte, we can't have a vector register for index. */
4366 if (!t->opcode_modifier.vecsib
4367 && i.index_reg
4368 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4369 || i.index_reg->reg_type.bitfield.regymm
4370 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4371 {
4372 i.error = unsupported_vector_index_register;
4373 return 1;
4374 }
4375
ad8ecc81
MZ		 4376 /* Check if default mask is allowed. */
4377 if (t->opcode_modifier.nodefmask
4378 && (!i.mask || i.mask->mask->reg_num == 0))
4379 {
4380 i.error = no_default_mask;
4381 return 1;
4382 }
4383
7bab8ab5
JB		 4384 /* For VSIB byte, we need a vector register for index, and all vector
4385 registers must be distinct. */
4386 if (t->opcode_modifier.vecsib)
4387 {
4388 if (!i.index_reg
6c30d220
L		 4389 || !((t->opcode_modifier.vecsib == VecSIB128
4390 && i.index_reg->reg_type.bitfield.regxmm)
4391 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4392 && i.index_reg->reg_type.bitfield.regymm)
4393 || (t->opcode_modifier.vecsib == VecSIB512
4394 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4395 {
4396 i.error = invalid_vsib_address;
4397 return 1;
4398 }
4399
43234a1e
L		 4400 gas_assert (i.reg_operands == 2 || i.mask);
4401 if (i.reg_operands == 2 && !i.mask)
4402 {
4403 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4404 || i.types[0].bitfield.regymm);
43234a1e 4405 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4406 || i.types[2].bitfield.regymm);
43234a1e
L		 4407 if (operand_check == check_none)
4408 return 0;
4409 if (register_number (i.op[0].regs)
4410 != register_number (i.index_reg)
4411 && register_number (i.op[2].regs)
4412 != register_number (i.index_reg)
4413 && register_number (i.op[0].regs)
4414 != register_number (i.op[2].regs))
4415 return 0;
4416 if (operand_check == check_error)
4417 {
4418 i.error = invalid_vector_register_set;
4419 return 1;
4420 }
4421 as_warn (_("mask, index, and destination registers should be distinct"));
4422 }
8444f82a
MZ		 4423 else if (i.reg_operands == 1 && i.mask)
4424 {
4425 if ((i.types[1].bitfield.regymm
4426 || i.types[1].bitfield.regzmm)
4427 && (register_number (i.op[1].regs)
4428 == register_number (i.index_reg)))
4429 {
4430 if (operand_check == check_error)
4431 {
4432 i.error = invalid_vector_register_set;
4433 return 1;
4434 }
4435 if (operand_check != check_none)
4436 as_warn (_("index and destination registers should be distinct"));
4437 }
4438 }
43234a1e 4439 }
7bab8ab5 4440
43234a1e
L		 4441 /* Check if broadcast is supported by the instruction and is applied
4442 to the memory operand. */
4443 if (i.broadcast)
4444 {
4445 int broadcasted_opnd_size;
4446
4447 /* Check if specified broadcast is supported in this instruction,
4448 and it's applied to memory operand of DWORD or QWORD type,
4449 depending on VecESize. */
4450 if (i.broadcast->type != t->opcode_modifier.broadcast
4451 || !i.types[i.broadcast->operand].bitfield.mem
4452 || (t->opcode_modifier.vecesize == 0
4453 && !i.types[i.broadcast->operand].bitfield.dword
4454 && !i.types[i.broadcast->operand].bitfield.unspecified)
4455 || (t->opcode_modifier.vecesize == 1
4456 && !i.types[i.broadcast->operand].bitfield.qword
4457 && !i.types[i.broadcast->operand].bitfield.unspecified))
4458 goto bad_broadcast;
4459
4460 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4461 if (i.broadcast->type == BROADCAST_1TO16)
4462 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4463 else if (i.broadcast->type == BROADCAST_1TO8)
4464 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4465 else if (i.broadcast->type == BROADCAST_1TO4)
4466 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4467 else if (i.broadcast->type == BROADCAST_1TO2)
4468 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4469 else
4470 goto bad_broadcast;
4471
4472 if ((broadcasted_opnd_size == 256
4473 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4474 || (broadcasted_opnd_size == 512
4475 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4476 {
4477 bad_broadcast:
4478 i.error = unsupported_broadcast;
4479 return 1;
4480 }
4481 }
4482 /* If broadcast is supported in this instruction, we need to check if
4483 operand of one-element size isn't specified without broadcast. */
4484 else if (t->opcode_modifier.broadcast && i.mem_operands)
4485 {
4486 /* Find memory operand. */
4487 for (op = 0; op < i.operands; op++)
4488 if (operand_type_check (i.types[op], anymem))
4489 break;
4490 gas_assert (op < i.operands);
4491 /* Check size of the memory operand. */
4492 if ((t->opcode_modifier.vecesize == 0
4493 && i.types[op].bitfield.dword)
4494 || (t->opcode_modifier.vecesize == 1
4495 && i.types[op].bitfield.qword))
4496 {
4497 i.error = broadcast_needed;
4498 return 1;
4499 }
4500 }
4501
4502 /* Check if requested masking is supported. */
4503 if (i.mask
4504 && (!t->opcode_modifier.masking
4505 || (i.mask->zeroing
4506 && t->opcode_modifier.masking == MERGING_MASKING)))
4507 {
4508 i.error = unsupported_masking;
4509 return 1;
4510 }
4511
4512 /* Check if masking is applied to dest operand. */
4513 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4514 {
4515 i.error = mask_not_on_destination;
4516 return 1;
4517 }
4518
43234a1e
L		 4519 /* Check RC/SAE. */
4520 if (i.rounding)
4521 {
4522 if ((i.rounding->type != saeonly
4523 && !t->opcode_modifier.staticrounding)
4524 || (i.rounding->type == saeonly
4525 && (t->opcode_modifier.staticrounding
4526 || !t->opcode_modifier.sae)))
4527 {
4528 i.error = unsupported_rc_sae;
4529 return 1;
4530 }
4531 /* If the instruction has several immediate operands and one of
4532 them is rounding, the rounding operand should be the last
4533 immediate operand. */
4534 if (i.imm_operands > 1
4535 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4536 {
43234a1e 4537 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4538 return 1;
4539 }
6c30d220
L		 4540 }
4541
43234a1e
L		 4542 /* Check vector Disp8 operand. */
4543 if (t->opcode_modifier.disp8memshift)
4544 {
4545 if (i.broadcast)
4546 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4547 else
4548 i.memshift = t->opcode_modifier.disp8memshift;
4549
4550 for (op = 0; op < i.operands; op++)
4551 if (operand_type_check (i.types[op], disp)
4552 && i.op[op].disps->X_op == O_constant)
4553 {
4554 offsetT value = i.op[op].disps->X_add_number;
4555 int vec_disp8_ok = fits_in_vec_disp8 (value);
4556 if (t->operand_types [op].bitfield.vec_disp8)
4557 {
4558 if (vec_disp8_ok)
4559 i.types[op].bitfield.vec_disp8 = 1;
4560 else
4561 {
4562 /* Vector insn can only have Vec_Disp8/Disp32 in
4563 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4564 mode. */
4565 i.types[op].bitfield.disp8 = 0;
4566 if (flag_code != CODE_16BIT)
4567 i.types[op].bitfield.disp16 = 0;
4568 }
4569 }
4570 else if (flag_code != CODE_16BIT)
4571 {
4572 /* One form of this instruction supports vector Disp8.
4573 Try vector Disp8 if we need to use Disp32. */
4574 if (vec_disp8_ok && !fits_in_signed_byte (value))
4575 {
4576 i.error = try_vector_disp8;
4577 return 1;
4578 }
4579 }
4580 }
4581 }
4582 else
4583 i.memshift = -1;
4584
6c30d220
L		 4585 return 0;
4586}
4587
43f3e2ee 4588/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4589 operand types. */
4590
4591static int
4592VEX_check_operands (const insn_template *t)
4593{
43234a1e
L		 4594 /* VREX is only valid with EVEX prefix. */
4595 if (i.need_vrex && !t->opcode_modifier.evex)
4596 {
4597 i.error = invalid_register_operand;
4598 return 1;
4599 }
4600
a683cc34
SP		 4601 if (!t->opcode_modifier.vex)
4602 return 0;
4603
4604 /* Only check VEX_Imm4, which must be the first operand. */
4605 if (t->operand_types[0].bitfield.vec_imm4)
4606 {
4607 if (i.op[0].imms->X_op != O_constant
4608 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4609 {
a65babc9 4610 i.error = bad_imm4;
891edac4
L		 4611 return 1;
4612 }
a683cc34
SP		 4613
4614 /* Turn off Imm8 so that update_imm won't complain. */
4615 i.types[0] = vec_imm4;
4616 }
4617
4618 return 0;
4619}
4620
d3ce72d0 4621static const insn_template *
e3bb37b5 4622match_template (void)
29b0f896
AM		 4623{
4624 /* Points to template once we've found it. */
d3ce72d0 4625 const insn_template *t;
40fb9820 4626 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4627 i386_operand_type overlap4;
29b0f896 4628 unsigned int found_reverse_match;
40fb9820
L		 4629 i386_opcode_modifier suffix_check;
4630 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4631 int addr_prefix_disp;
a5c311ca 4632 unsigned int j;
3629bb00 4633 unsigned int found_cpu_match;
45664ddb 4634 unsigned int check_register;
5614d22c 4635 enum i386_error specific_error = 0;
29b0f896 4636
c0f3af97
L		 4637#if MAX_OPERANDS != 5
4638# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4639#endif
4640
29b0f896 4641 found_reverse_match = 0;
539e75ad 4642 addr_prefix_disp = -1;
40fb9820
L		 4643
4644 memset (&suffix_check, 0, sizeof (suffix_check));
4645 if (i.suffix == BYTE_MNEM_SUFFIX)
4646 suffix_check.no_bsuf = 1;
4647 else if (i.suffix == WORD_MNEM_SUFFIX)
4648 suffix_check.no_wsuf = 1;
4649 else if (i.suffix == SHORT_MNEM_SUFFIX)
4650 suffix_check.no_ssuf = 1;
4651 else if (i.suffix == LONG_MNEM_SUFFIX)
4652 suffix_check.no_lsuf = 1;
4653 else if (i.suffix == QWORD_MNEM_SUFFIX)
4654 suffix_check.no_qsuf = 1;
4655 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4656 suffix_check.no_ldsuf = 1;
29b0f896 4657
01559ecc
L		 4658 /* Must have right number of operands. */
4659 i.error = number_of_operands_mismatch;
4660
45aa61fe 4661 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4662 {
539e75ad
L		 4663 addr_prefix_disp = -1;
4664
29b0f896
AM		 4665 if (i.operands != t->operands)
4666 continue;
4667
50aecf8c 4668 /* Check processor support. */
a65babc9 4669 i.error = unsupported;
c0f3af97
L		 4670 found_cpu_match = (cpu_flags_match (t)
4671 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4672 if (!found_cpu_match)
4673 continue;
4674
e1d4d893 4675 /* Check old gcc support. */
a65babc9 4676 i.error = old_gcc_only;
e1d4d893
L		 4677 if (!old_gcc && t->opcode_modifier.oldgcc)
4678 continue;
4679
4680 /* Check AT&T mnemonic. */
a65babc9 4681 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4682 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4683 continue;
4684
891edac4 4685 /* Check AT&T/Intel syntax. */
a65babc9 4686 i.error = unsupported_syntax;
5c07affc
L		 4687 if ((intel_syntax && t->opcode_modifier.attsyntax)
4688 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4689 continue;
4690
20592a94 4691 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4692 i.error = invalid_instruction_suffix;
567e4e96
L		 4693 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4694 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4695 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4696 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4697 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4698 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4699 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4700 continue;
4701
5c07affc 4702 if (!operand_size_match (t))
7d5e4556 4703 continue;
539e75ad 4704
5c07affc
L		 4705 for (j = 0; j < MAX_OPERANDS; j++)
4706 operand_types[j] = t->operand_types[j];
4707
45aa61fe
AM		 4708 /* In general, don't allow 64-bit operands in 32-bit mode. */
4709 if (i.suffix == QWORD_MNEM_SUFFIX
4710 && flag_code != CODE_64BIT
4711 && (intel_syntax
40fb9820 4712 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4713 && !intel_float_operand (t->name))
4714 : intel_float_operand (t->name) != 2)
40fb9820 4715 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4716 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4717 && !operand_types[0].bitfield.regymm
4718 && !operand_types[0].bitfield.regzmm)
40fb9820 4719 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4720 && operand_types[t->operands > 1].bitfield.regxmm
4721 && operand_types[t->operands > 1].bitfield.regymm
4722 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4723 && (t->base_opcode != 0x0fc7
4724 || t->extension_opcode != 1 /* cmpxchg8b */))
4725 continue;
4726
192dc9c6
JB		 4727 /* In general, don't allow 32-bit operands on pre-386. */
4728 else if (i.suffix == LONG_MNEM_SUFFIX
4729 && !cpu_arch_flags.bitfield.cpui386
4730 && (intel_syntax
4731 ? (!t->opcode_modifier.ignoresize
4732 && !intel_float_operand (t->name))
4733 : intel_float_operand (t->name) != 2)
4734 && ((!operand_types[0].bitfield.regmmx
4735 && !operand_types[0].bitfield.regxmm)
4736 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4737 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4738 continue;
4739
29b0f896 4740 /* Do not verify operands when there are none. */
50aecf8c 4741 else
29b0f896 4742 {
c6fb90c8 4743 if (!t->operands)
2dbab7d5
L		 4744 /* We've found a match; break out of loop. */
4745 break;
29b0f896 4746 }
252b5132 4747
539e75ad
L		 4748 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4749 into Disp32/Disp16/Disp32 operand. */
4750 if (i.prefix[ADDR_PREFIX] != 0)
4751 {
40fb9820 4752 /* There should be only one Disp operand. */
539e75ad
L		 4753 switch (flag_code)
4754 {
4755 case CODE_16BIT:
40fb9820
L		 4756 for (j = 0; j < MAX_OPERANDS; j++)
4757 {
4758 if (operand_types[j].bitfield.disp16)
4759 {
4760 addr_prefix_disp = j;
4761 operand_types[j].bitfield.disp32 = 1;
4762 operand_types[j].bitfield.disp16 = 0;
4763 break;
4764 }
4765 }
539e75ad
L		 4766 break;
4767 case CODE_32BIT:
40fb9820
L		 4768 for (j = 0; j < MAX_OPERANDS; j++)
4769 {
4770 if (operand_types[j].bitfield.disp32)
4771 {
4772 addr_prefix_disp = j;
4773 operand_types[j].bitfield.disp32 = 0;
4774 operand_types[j].bitfield.disp16 = 1;
4775 break;
4776 }
4777 }
539e75ad
L		 4778 break;
4779 case CODE_64BIT:
40fb9820
L		 4780 for (j = 0; j < MAX_OPERANDS; j++)
4781 {
4782 if (operand_types[j].bitfield.disp64)
4783 {
4784 addr_prefix_disp = j;
4785 operand_types[j].bitfield.disp64 = 0;
4786 operand_types[j].bitfield.disp32 = 1;
4787 break;
4788 }
4789 }
539e75ad
L		 4790 break;
4791 }
539e75ad
L		 4792 }
4793
56ffb741
L		 4794 /* We check register size if needed. */
4795 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4796 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4797 switch (t->operands)
4798 {
4799 case 1:
40fb9820 4800 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4801 continue;
4802 break;
4803 case 2:
8b38ad71
L		 4804 /* xchg %eax, %eax is a special case. It is an aliase for nop
4805 only in 32bit mode and we can use opcode 0x90. In 64bit
4806 mode, we can't use 0x90 for xchg %eax, %eax since it should
4807 zero-extend %eax to %rax. */
4808 if (flag_code == CODE_64BIT
4809 && t->base_opcode == 0x90
0dfbf9d7
L		 4810 && operand_type_equal (&i.types [0], &acc32)
4811 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4812 continue;
b6169b20
L		 4813 if (i.swap_operand)
4814 {
4815 /* If we swap operand in encoding, we either match
4816 the next one or reverse direction of operands. */
4817 if (t->opcode_modifier.s)
4818 continue;
4819 else if (t->opcode_modifier.d)
4820 goto check_reverse;
4821 }
4822
29b0f896 4823 case 3:
fa99fab2
L		 4824 /* If we swap operand in encoding, we match the next one. */
4825 if (i.swap_operand && t->opcode_modifier.s)
4826 continue;
f48ff2ae 4827 case 4:
c0f3af97 4828 case 5:
c6fb90c8 4829 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4830 if (!operand_type_match (overlap0, i.types[0])
4831 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4832 || (check_register
4833 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4834 operand_types[0],
4835 overlap1, i.types[1],
4836 operand_types[1])))
29b0f896
AM		 4837 {
4838 /* Check if other direction is valid ... */
40fb9820 4839 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4840 continue;
4841
b6169b20 4842check_reverse:
29b0f896 4843 /* Try reversing direction of operands. */
c6fb90c8
L		 4844 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4845 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4846 if (!operand_type_match (overlap0, i.types[0])
4847 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4848 || (check_register
4849 && !operand_type_register_match (overlap0,
4850 i.types[0],
4851 operand_types[1],
4852 overlap1,
4853 i.types[1],
4854 operand_types[0])))
29b0f896
AM		 4855 {
4856 /* Does not match either direction. */
4857 continue;
4858 }
4859 /* found_reverse_match holds which of D or FloatDR
4860 we've found. */
40fb9820 4861 if (t->opcode_modifier.d)
8a2ed489 4862 found_reverse_match = Opcode_D;
40fb9820 4863 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4864 found_reverse_match = Opcode_FloatD;
4865 else
4866 found_reverse_match = 0;
40fb9820 4867 if (t->opcode_modifier.floatr)
8a2ed489 4868 found_reverse_match |= Opcode_FloatR;
29b0f896 4869 }
f48ff2ae 4870 else
29b0f896 4871 {
f48ff2ae 4872 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4873 switch (t->operands)
4874 {
c0f3af97
L		 4875 case 5:
4876 overlap4 = operand_type_and (i.types[4],
4877 operand_types[4]);
d1cbb4db 4878 case 4:
c6fb90c8
L		 4879 overlap3 = operand_type_and (i.types[3],
4880 operand_types[3]);
d1cbb4db 4881 case 3:
c6fb90c8
L		 4882 overlap2 = operand_type_and (i.types[2],
4883 operand_types[2]);
d1cbb4db
L		 4884 break;
4885 }
29b0f896 4886
f48ff2ae
L		 4887 switch (t->operands)
4888 {
c0f3af97
L		 4889 case 5:
4890 if (!operand_type_match (overlap4, i.types[4])
4891 || !operand_type_register_match (overlap3,
4892 i.types[3],
4893 operand_types[3],
4894 overlap4,
4895 i.types[4],
4896 operand_types[4]))
4897 continue;
f48ff2ae 4898 case 4:
40fb9820 4899 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4900 || (check_register
4901 && !operand_type_register_match (overlap2,
4902 i.types[2],
4903 operand_types[2],
4904 overlap3,
4905 i.types[3],
4906 operand_types[3])))
f48ff2ae
L		 4907 continue;
4908 case 3:
4909 /* Here we make use of the fact that there are no
4910 reverse match 3 operand instructions, and all 3
4911 operand instructions only need to be checked for
4912 register consistency between operands 2 and 3. */
40fb9820 4913 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4914 || (check_register
4915 && !operand_type_register_match (overlap1,
4916 i.types[1],
4917 operand_types[1],
4918 overlap2,
4919 i.types[2],
4920 operand_types[2])))
f48ff2ae
L		 4921 continue;
4922 break;
4923 }
29b0f896 4924 }
f48ff2ae 4925 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4926 slip through to break. */
4927 }
3629bb00 4928 if (!found_cpu_match)
29b0f896
AM		 4929 {
4930 found_reverse_match = 0;
4931 continue;
4932 }
c0f3af97 4933
5614d22c
JB		 4934 /* Check if vector and VEX operands are valid. */
4935 if (check_VecOperands (t) || VEX_check_operands (t))
4936 {
4937 specific_error = i.error;
4938 continue;
4939 }
a683cc34 4940
29b0f896
AM		 4941 /* We've found a match; break out of loop. */
4942 break;
4943 }
4944
4945 if (t == current_templates->end)
4946 {
4947 /* We found no match. */
a65babc9 4948 const char *err_msg;
5614d22c 4949 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4950 {
4951 default:
4952 abort ();
86e026a4 4953 case operand_size_mismatch:
a65babc9
L		 4954 err_msg = _("operand size mismatch");
4955 break;
4956 case operand_type_mismatch:
4957 err_msg = _("operand type mismatch");
4958 break;
4959 case register_type_mismatch:
4960 err_msg = _("register type mismatch");
4961 break;
4962 case number_of_operands_mismatch:
4963 err_msg = _("number of operands mismatch");
4964 break;
4965 case invalid_instruction_suffix:
4966 err_msg = _("invalid instruction suffix");
4967 break;
4968 case bad_imm4:
4a2608e3 4969 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4970 break;
4971 case old_gcc_only:
4972 err_msg = _("only supported with old gcc");
4973 break;
4974 case unsupported_with_intel_mnemonic:
4975 err_msg = _("unsupported with Intel mnemonic");
4976 break;
4977 case unsupported_syntax:
4978 err_msg = _("unsupported syntax");
4979 break;
4980 case unsupported:
35262a23 4981 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4982 current_templates->start->name);
4983 return NULL;
6c30d220
L		 4984 case invalid_vsib_address:
4985 err_msg = _("invalid VSIB address");
4986 break;
7bab8ab5
JB		 4987 case invalid_vector_register_set:
4988 err_msg = _("mask, index, and destination registers must be distinct");
4989 break;
6c30d220
L		 4990 case unsupported_vector_index_register:
4991 err_msg = _("unsupported vector index register");
4992 break;
43234a1e
L		 4993 case unsupported_broadcast:
4994 err_msg = _("unsupported broadcast");
4995 break;
4996 case broadcast_not_on_src_operand:
4997 err_msg = _("broadcast not on source memory operand");
4998 break;
4999 case broadcast_needed:
5000 err_msg = _("broadcast is needed for operand of such type");
5001 break;
5002 case unsupported_masking:
5003 err_msg = _("unsupported masking");
5004 break;
5005 case mask_not_on_destination:
5006 err_msg = _("mask not on destination operand");
5007 break;
5008 case no_default_mask:
5009 err_msg = _("default mask isn't allowed");
5010 break;
5011 case unsupported_rc_sae:
5012 err_msg = _("unsupported static rounding/sae");
5013 break;
5014 case rc_sae_operand_not_last_imm:
5015 if (intel_syntax)
5016 err_msg = _("RC/SAE operand must precede immediate operands");
5017 else
5018 err_msg = _("RC/SAE operand must follow immediate operands");
5019 break;
5020 case invalid_register_operand:
5021 err_msg = _("invalid register operand");
5022 break;
a65babc9
L		 5023 }
5024 as_bad (_("%s for `%s'"), err_msg,
891edac4 5025 current_templates->start->name);
fa99fab2 5026 return NULL;
29b0f896 5027 }
252b5132 5028
29b0f896
AM		 5029 if (!quiet_warnings)
5030 {
5031 if (!intel_syntax
40fb9820
L		 5032 && (i.types[0].bitfield.jumpabsolute
5033 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5034 {
5035 as_warn (_("indirect %s without `*'"), t->name);
5036 }
5037
40fb9820
L		 5038 if (t->opcode_modifier.isprefix
5039 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5040 {
5041 /* Warn them that a data or address size prefix doesn't
5042 affect assembly of the next line of code. */
5043 as_warn (_("stand-alone `%s' prefix"), t->name);
5044 }
5045 }
5046
5047 /* Copy the template we found. */
5048 i.tm = *t;
539e75ad
L		 5049
5050 if (addr_prefix_disp != -1)
5051 i.tm.operand_types[addr_prefix_disp]
5052 = operand_types[addr_prefix_disp];
5053
29b0f896
AM		 5054 if (found_reverse_match)
5055 {
5056 /* If we found a reverse match we must alter the opcode
5057 direction bit. found_reverse_match holds bits to change
5058 (different for int & float insns). */
5059
5060 i.tm.base_opcode ^= found_reverse_match;
5061
539e75ad
L		 5062 i.tm.operand_types[0] = operand_types[1];
5063 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5064 }
5065
fa99fab2 5066 return t;
29b0f896
AM		 5067}
5068
5069static int
e3bb37b5 5070check_string (void)
29b0f896 5071{
40fb9820
L		 5072 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5073 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5074 {
5075 if (i.seg[0] != NULL && i.seg[0] != &es)
5076 {
a87af027 5077 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5078 i.tm.name,
a87af027
JB		 5079 mem_op + 1,
5080 register_prefix);
29b0f896
AM		 5081 return 0;
5082 }
5083 /* There's only ever one segment override allowed per instruction.
5084 This instruction possibly has a legal segment override on the
5085 second operand, so copy the segment to where non-string
5086 instructions store it, allowing common code. */
5087 i.seg[0] = i.seg[1];
5088 }
40fb9820 5089 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5090 {
5091 if (i.seg[1] != NULL && i.seg[1] != &es)
5092 {
a87af027 5093 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5094 i.tm.name,
a87af027
JB		 5095 mem_op + 2,
5096 register_prefix);
29b0f896
AM		 5097 return 0;
5098 }
5099 }
5100 return 1;
5101}
5102
5103static int
543613e9 5104process_suffix (void)
29b0f896
AM		 5105{
5106 /* If matched instruction specifies an explicit instruction mnemonic
5107 suffix, use it. */
40fb9820
L		 5108 if (i.tm.opcode_modifier.size16)
5109 i.suffix = WORD_MNEM_SUFFIX;
5110 else if (i.tm.opcode_modifier.size32)
5111 i.suffix = LONG_MNEM_SUFFIX;
5112 else if (i.tm.opcode_modifier.size64)
5113 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5114 else if (i.reg_operands)
5115 {
5116 /* If there's no instruction mnemonic suffix we try to invent one
5117 based on register operands. */
5118 if (!i.suffix)
5119 {
5120 /* We take i.suffix from the last register operand specified,
5121 Destination register type is more significant than source
381d071f
L		 5122 register type. crc32 in SSE4.2 prefers source register
5123 type. */
5124 if (i.tm.base_opcode == 0xf20f38f1)
5125 {
40fb9820
L		 5126 if (i.types[0].bitfield.reg16)
5127 i.suffix = WORD_MNEM_SUFFIX;
5128 else if (i.types[0].bitfield.reg32)
5129 i.suffix = LONG_MNEM_SUFFIX;
5130 else if (i.types[0].bitfield.reg64)
5131 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5132 }
9344ff29 5133 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5134 {
40fb9820 5135 if (i.types[0].bitfield.reg8)
20592a94
L		 5136 i.suffix = BYTE_MNEM_SUFFIX;
5137 }
381d071f
L		 5138
5139 if (!i.suffix)
5140 {
5141 int op;
5142
20592a94
L		 5143 if (i.tm.base_opcode == 0xf20f38f1
5144 || i.tm.base_opcode == 0xf20f38f0)
5145 {
5146 /* We have to know the operand size for crc32. */
5147 as_bad (_("ambiguous memory operand size for `%s`"),
5148 i.tm.name);
5149 return 0;
5150 }
5151
381d071f 5152 for (op = i.operands; --op >= 0;)
40fb9820 5153 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5154 {
40fb9820
L		 5155 if (i.types[op].bitfield.reg8)
5156 {
5157 i.suffix = BYTE_MNEM_SUFFIX;
5158 break;
5159 }
5160 else if (i.types[op].bitfield.reg16)
5161 {
5162 i.suffix = WORD_MNEM_SUFFIX;
5163 break;
5164 }
5165 else if (i.types[op].bitfield.reg32)
5166 {
5167 i.suffix = LONG_MNEM_SUFFIX;
5168 break;
5169 }
5170 else if (i.types[op].bitfield.reg64)
5171 {
5172 i.suffix = QWORD_MNEM_SUFFIX;
5173 break;
5174 }
381d071f
L		 5175 }
5176 }
29b0f896
AM		 5177 }
5178 else if (i.suffix == BYTE_MNEM_SUFFIX)
5179 {
2eb952a4
L		 5180 if (intel_syntax
5181 && i.tm.opcode_modifier.ignoresize
5182 && i.tm.opcode_modifier.no_bsuf)
5183 i.suffix = 0;
5184 else if (!check_byte_reg ())
29b0f896
AM		 5185 return 0;
5186 }
5187 else if (i.suffix == LONG_MNEM_SUFFIX)
5188 {
2eb952a4
L		 5189 if (intel_syntax
5190 && i.tm.opcode_modifier.ignoresize
5191 && i.tm.opcode_modifier.no_lsuf)
5192 i.suffix = 0;
5193 else if (!check_long_reg ())
29b0f896
AM		 5194 return 0;
5195 }
5196 else if (i.suffix == QWORD_MNEM_SUFFIX)
5197 {
955e1e6a
L		 5198 if (intel_syntax
5199 && i.tm.opcode_modifier.ignoresize
5200 && i.tm.opcode_modifier.no_qsuf)
5201 i.suffix = 0;
5202 else if (!check_qword_reg ())
29b0f896
AM		 5203 return 0;
5204 }
5205 else if (i.suffix == WORD_MNEM_SUFFIX)
5206 {
2eb952a4
L		 5207 if (intel_syntax
5208 && i.tm.opcode_modifier.ignoresize
5209 && i.tm.opcode_modifier.no_wsuf)
5210 i.suffix = 0;
5211 else if (!check_word_reg ())
29b0f896
AM		 5212 return 0;
5213 }
c0f3af97 5214 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5215 || i.suffix == YMMWORD_MNEM_SUFFIX
5216 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5217 {
43234a1e 5218 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5219 should check if it is a valid suffix. */
5220 }
40fb9820 5221 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5222 /* Do nothing if the instruction is going to ignore the prefix. */
5223 ;
5224 else
5225 abort ();
5226 }
40fb9820 5227 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5228 && !i.suffix
5229 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5230 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5231 {
5232 i.suffix = stackop_size;
5233 }
9306ca4a
JB		 5234 else if (intel_syntax
5235 && !i.suffix
40fb9820
L		 5236 && (i.tm.operand_types[0].bitfield.jumpabsolute
5237 || i.tm.opcode_modifier.jumpbyte
5238 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5239 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5240 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5241 {
5242 switch (flag_code)
5243 {
5244 case CODE_64BIT:
40fb9820 5245 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5246 {
5247 i.suffix = QWORD_MNEM_SUFFIX;
5248 break;
5249 }
5250 case CODE_32BIT:
40fb9820 5251 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5252 i.suffix = LONG_MNEM_SUFFIX;
5253 break;
5254 case CODE_16BIT:
40fb9820 5255 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5256 i.suffix = WORD_MNEM_SUFFIX;
5257 break;
5258 }
5259 }
252b5132 5260
9306ca4a 5261 if (!i.suffix)
29b0f896 5262 {
9306ca4a
JB		 5263 if (!intel_syntax)
5264 {
40fb9820 5265 if (i.tm.opcode_modifier.w)
9306ca4a 5266 {
4eed87de
AM		 5267 as_bad (_("no instruction mnemonic suffix given and "
5268 "no register operands; can't size instruction"));
9306ca4a
JB		 5269 return 0;
5270 }
5271 }
5272 else
5273 {
40fb9820 5274 unsigned int suffixes;
7ab9ffdd 5275
40fb9820
L		 5276 suffixes = !i.tm.opcode_modifier.no_bsuf;
5277 if (!i.tm.opcode_modifier.no_wsuf)
5278 suffixes |= 1 << 1;
5279 if (!i.tm.opcode_modifier.no_lsuf)
5280 suffixes |= 1 << 2;
fc4adea1 5281 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5282 suffixes |= 1 << 3;
5283 if (!i.tm.opcode_modifier.no_ssuf)
5284 suffixes |= 1 << 4;
5285 if (!i.tm.opcode_modifier.no_qsuf)
5286 suffixes |= 1 << 5;
5287
5288 /* There are more than suffix matches. */
5289 if (i.tm.opcode_modifier.w
9306ca4a 5290 || ((suffixes & (suffixes - 1))
40fb9820
L		 5291 && !i.tm.opcode_modifier.defaultsize
5292 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5293 {
5294 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5295 return 0;
5296 }
5297 }
29b0f896 5298 }
252b5132 5299
9306ca4a
JB		 5300 /* Change the opcode based on the operand size given by i.suffix;
5301 We don't need to change things for byte insns. */
5302
582d5edd
L		 5303 if (i.suffix
5304 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5305 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5306 && i.suffix != YMMWORD_MNEM_SUFFIX
5307 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5308 {
5309 /* It's not a byte, select word/dword operation. */
40fb9820 5310 if (i.tm.opcode_modifier.w)
29b0f896 5311 {
40fb9820 5312 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5313 i.tm.base_opcode |= 8;
5314 else
5315 i.tm.base_opcode |= 1;
5316 }
0f3f3d8b 5317
29b0f896
AM		 5318 /* Now select between word & dword operations via the operand
5319 size prefix, except for instructions that will ignore this
5320 prefix anyway. */
ca61edf2 5321 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5322 {
ca61edf2
L		 5323 /* The address size override prefix changes the size of the
5324 first operand. */
40fb9820
L		 5325 if ((flag_code == CODE_32BIT
5326 && i.op->regs[0].reg_type.bitfield.reg16)
5327 || (flag_code != CODE_32BIT
5328 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5329 if (!add_prefix (ADDR_PREFIX_OPCODE))
5330 return 0;
5331 }
5332 else if (i.suffix != QWORD_MNEM_SUFFIX
5333 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5334 && !i.tm.opcode_modifier.ignoresize
5335 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5336 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5337 || (flag_code == CODE_64BIT
40fb9820 5338 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5339 {
5340 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5341
40fb9820 5342 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5343 prefix = ADDR_PREFIX_OPCODE;
252b5132 5344
29b0f896
AM		 5345 if (!add_prefix (prefix))
5346 return 0;
24eab124 5347 }
252b5132 5348
29b0f896
AM		 5349 /* Set mode64 for an operand. */
5350 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5351 && flag_code == CODE_64BIT
40fb9820 5352 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5353 {
5354 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5355 need rex64. cmpxchg8b is also a special case. */
5356 if (! (i.operands == 2
5357 && i.tm.base_opcode == 0x90
5358 && i.tm.extension_opcode == None
0dfbf9d7
L		 5359 && operand_type_equal (&i.types [0], &acc64)
5360 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5361 && ! (i.operands == 1
5362 && i.tm.base_opcode == 0xfc7
5363 && i.tm.extension_opcode == 1
40fb9820
L		 5364 && !operand_type_check (i.types [0], reg)
5365 && operand_type_check (i.types [0], anymem)))
f6bee062 5366 i.rex |= REX_W;
46e883c5 5367 }
3e73aa7c 5368
29b0f896
AM		 5369 /* Size floating point instruction. */
5370 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5371 if (i.tm.opcode_modifier.floatmf)
543613e9 5372 i.tm.base_opcode ^= 4;
29b0f896 5373 }
7ecd2f8b 5374
29b0f896
AM		 5375 return 1;
5376}
3e73aa7c 5377
29b0f896 5378static int
543613e9 5379check_byte_reg (void)
29b0f896
AM		 5380{
5381 int op;
543613e9 5382
29b0f896
AM		 5383 for (op = i.operands; --op >= 0;)
5384 {
5385 /* If this is an eight bit register, it's OK. If it's the 16 or
5386 32 bit version of an eight bit register, we will just use the
5387 low portion, and that's OK too. */
40fb9820 5388 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5389 continue;
5390
5a819eb9
JB		 5391 /* I/O port address operands are OK too. */
5392 if (i.tm.operand_types[op].bitfield.inoutportreg)
5393 continue;
5394
9344ff29
L		 5395 /* crc32 doesn't generate this warning. */
5396 if (i.tm.base_opcode == 0xf20f38f0)
5397 continue;
5398
40fb9820
L		 5399 if ((i.types[op].bitfield.reg16
5400 || i.types[op].bitfield.reg32
5401 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5402 && i.op[op].regs->reg_num < 4
5403 /* Prohibit these changes in 64bit mode, since the lowering
5404 would be more complicated. */
5405 && flag_code != CODE_64BIT)
29b0f896 5406 {
29b0f896 5407#if REGISTER_WARNINGS
5a819eb9 5408 if (!quiet_warnings)
a540244d
L		 5409 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5410 register_prefix,
40fb9820 5411 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5412 ? REGNAM_AL - REGNAM_AX
5413 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5414 register_prefix,
29b0f896
AM		 5415 i.op[op].regs->reg_name,
5416 i.suffix);
5417#endif
5418 continue;
5419 }
5420 /* Any other register is bad. */
40fb9820
L		 5421 if (i.types[op].bitfield.reg16
5422 || i.types[op].bitfield.reg32
5423 || i.types[op].bitfield.reg64
5424 || i.types[op].bitfield.regmmx
5425 || i.types[op].bitfield.regxmm
c0f3af97 5426 || i.types[op].bitfield.regymm
43234a1e 5427 || i.types[op].bitfield.regzmm
40fb9820
L		 5428 || i.types[op].bitfield.sreg2
5429 || i.types[op].bitfield.sreg3
5430 || i.types[op].bitfield.control
5431 || i.types[op].bitfield.debug
5432 || i.types[op].bitfield.test
5433 || i.types[op].bitfield.floatreg
5434 || i.types[op].bitfield.floatacc)
29b0f896 5435 {
a540244d
L		 5436 as_bad (_("`%s%s' not allowed with `%s%c'"),
5437 register_prefix,
29b0f896
AM		 5438 i.op[op].regs->reg_name,
5439 i.tm.name,
5440 i.suffix);
5441 return 0;
5442 }
5443 }
5444 return 1;
5445}
5446
5447static int
e3bb37b5 5448check_long_reg (void)
29b0f896
AM		 5449{
5450 int op;
5451
5452 for (op = i.operands; --op >= 0;)
5453 /* Reject eight bit registers, except where the template requires
5454 them. (eg. movzb) */
40fb9820
L		 5455 if (i.types[op].bitfield.reg8
5456 && (i.tm.operand_types[op].bitfield.reg16
5457 || i.tm.operand_types[op].bitfield.reg32
5458 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5459 {
a540244d
L		 5460 as_bad (_("`%s%s' not allowed with `%s%c'"),
5461 register_prefix,
29b0f896
AM		 5462 i.op[op].regs->reg_name,
5463 i.tm.name,
5464 i.suffix);
5465 return 0;
5466 }
e4630f71 5467 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5468 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5469 && i.types[op].bitfield.reg16
5470 && (i.tm.operand_types[op].bitfield.reg32
5471 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5472 {
5473 /* Prohibit these changes in the 64bit mode, since the
5474 lowering is more complicated. */
5475 if (flag_code == CODE_64BIT)
252b5132 5476 {
2b5d6a91 5477 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5478 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5479 i.suffix);
5480 return 0;
252b5132 5481 }
29b0f896 5482#if REGISTER_WARNINGS
cecf1424
JB		 5483 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5484 register_prefix,
5485 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5486 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5487#endif
252b5132 5488 }
e4630f71 5489 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5490 else if (i.types[op].bitfield.reg64
5491 && (i.tm.operand_types[op].bitfield.reg32
5492 || i.tm.operand_types[op].bitfield.acc))
252b5132 5493 {
34828aad 5494 if (intel_syntax
ca61edf2 5495 && i.tm.opcode_modifier.toqword
40fb9820 5496 && !i.types[0].bitfield.regxmm)
34828aad 5497 {
ca61edf2 5498 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5499 i.suffix = QWORD_MNEM_SUFFIX;
5500 }
5501 else
5502 {
2b5d6a91 5503 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5504 register_prefix, i.op[op].regs->reg_name,
5505 i.suffix);
5506 return 0;
5507 }
29b0f896
AM		 5508 }
5509 return 1;
5510}
252b5132 5511
29b0f896 5512static int
e3bb37b5 5513check_qword_reg (void)
29b0f896
AM		 5514{
5515 int op;
252b5132 5516
29b0f896
AM		 5517 for (op = i.operands; --op >= 0; )
5518 /* Reject eight bit registers, except where the template requires
5519 them. (eg. movzb) */
40fb9820
L		 5520 if (i.types[op].bitfield.reg8
5521 && (i.tm.operand_types[op].bitfield.reg16
5522 || i.tm.operand_types[op].bitfield.reg32
5523 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5524 {
a540244d
L		 5525 as_bad (_("`%s%s' not allowed with `%s%c'"),
5526 register_prefix,
29b0f896
AM		 5527 i.op[op].regs->reg_name,
5528 i.tm.name,
5529 i.suffix);
5530 return 0;
5531 }
e4630f71 5532 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5533 else if ((i.types[op].bitfield.reg16
5534 || i.types[op].bitfield.reg32)
5535 && (i.tm.operand_types[op].bitfield.reg32
5536 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5537 {
5538 /* Prohibit these changes in the 64bit mode, since the
5539 lowering is more complicated. */
34828aad 5540 if (intel_syntax
ca61edf2 5541 && i.tm.opcode_modifier.todword
40fb9820 5542 && !i.types[0].bitfield.regxmm)
34828aad 5543 {
ca61edf2 5544 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5545 i.suffix = LONG_MNEM_SUFFIX;
5546 }
5547 else
5548 {
2b5d6a91 5549 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5550 register_prefix, i.op[op].regs->reg_name,
5551 i.suffix);
5552 return 0;
5553 }
252b5132 5554 }
29b0f896
AM		 5555 return 1;
5556}
252b5132 5557
29b0f896 5558static int
e3bb37b5 5559check_word_reg (void)
29b0f896
AM		 5560{
5561 int op;
5562 for (op = i.operands; --op >= 0;)
5563 /* Reject eight bit registers, except where the template requires
5564 them. (eg. movzb) */
40fb9820
L		 5565 if (i.types[op].bitfield.reg8
5566 && (i.tm.operand_types[op].bitfield.reg16
5567 || i.tm.operand_types[op].bitfield.reg32
5568 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5569 {
a540244d
L		 5570 as_bad (_("`%s%s' not allowed with `%s%c'"),
5571 register_prefix,
29b0f896
AM		 5572 i.op[op].regs->reg_name,
5573 i.tm.name,
5574 i.suffix);
5575 return 0;
5576 }
e4630f71 5577 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5578 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5579 && (i.types[op].bitfield.reg32
5580 || i.types[op].bitfield.reg64)
40fb9820
L		 5581 && (i.tm.operand_types[op].bitfield.reg16
5582 || i.tm.operand_types[op].bitfield.acc))
252b5132 5583 {
29b0f896
AM		 5584 /* Prohibit these changes in the 64bit mode, since the
5585 lowering is more complicated. */
5586 if (flag_code == CODE_64BIT)
252b5132 5587 {
2b5d6a91 5588 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5589 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5590 i.suffix);
5591 return 0;
252b5132 5592 }
29b0f896 5593#if REGISTER_WARNINGS
cecf1424
JB		 5594 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5595 register_prefix,
5596 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5597 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5598#endif
5599 }
5600 return 1;
5601}
252b5132 5602
29b0f896 5603static int
40fb9820 5604update_imm (unsigned int j)
29b0f896 5605{
bc0844ae 5606 i386_operand_type overlap = i.types[j];
40fb9820
L		 5607 if ((overlap.bitfield.imm8
5608 || overlap.bitfield.imm8s
5609 || overlap.bitfield.imm16
5610 || overlap.bitfield.imm32
5611 || overlap.bitfield.imm32s
5612 || overlap.bitfield.imm64)
0dfbf9d7
L		 5613 && !operand_type_equal (&overlap, &imm8)
5614 && !operand_type_equal (&overlap, &imm8s)
5615 && !operand_type_equal (&overlap, &imm16)
5616 && !operand_type_equal (&overlap, &imm32)
5617 && !operand_type_equal (&overlap, &imm32s)
5618 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5619 {
5620 if (i.suffix)
5621 {
40fb9820
L		 5622 i386_operand_type temp;
5623
0dfbf9d7 5624 operand_type_set (&temp, 0);
7ab9ffdd 5625 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5626 {
5627 temp.bitfield.imm8 = overlap.bitfield.imm8;
5628 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5629 }
5630 else if (i.suffix == WORD_MNEM_SUFFIX)
5631 temp.bitfield.imm16 = overlap.bitfield.imm16;
5632 else if (i.suffix == QWORD_MNEM_SUFFIX)
5633 {
5634 temp.bitfield.imm64 = overlap.bitfield.imm64;
5635 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5636 }
5637 else
5638 temp.bitfield.imm32 = overlap.bitfield.imm32;
5639 overlap = temp;
29b0f896 5640 }
0dfbf9d7
L		 5641 else if (operand_type_equal (&overlap, &imm16_32_32s)
5642 || operand_type_equal (&overlap, &imm16_32)
5643 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5644 {
40fb9820 5645 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5646 overlap = imm16;
40fb9820 5647 else
65da13b5 5648 overlap = imm32s;
29b0f896 5649 }
0dfbf9d7
L		 5650 if (!operand_type_equal (&overlap, &imm8)
5651 && !operand_type_equal (&overlap, &imm8s)
5652 && !operand_type_equal (&overlap, &imm16)
5653 && !operand_type_equal (&overlap, &imm32)
5654 && !operand_type_equal (&overlap, &imm32s)
5655 && !operand_type_equal (&overlap, &imm64))
29b0f896 5656 {
4eed87de
AM		 5657 as_bad (_("no instruction mnemonic suffix given; "
5658 "can't determine immediate size"));
29b0f896
AM		 5659 return 0;
5660 }
5661 }
40fb9820 5662 i.types[j] = overlap;
29b0f896 5663
40fb9820
L		 5664 return 1;
5665}
5666
5667static int
5668finalize_imm (void)
5669{
bc0844ae 5670 unsigned int j, n;
29b0f896 5671
bc0844ae
L		 5672 /* Update the first 2 immediate operands. */
5673 n = i.operands > 2 ? 2 : i.operands;
5674 if (n)
5675 {
5676 for (j = 0; j < n; j++)
5677 if (update_imm (j) == 0)
5678 return 0;
40fb9820 5679
bc0844ae
L		 5680 /* The 3rd operand can't be immediate operand. */
5681 gas_assert (operand_type_check (i.types[2], imm) == 0);
5682 }
29b0f896
AM		 5683
5684 return 1;
5685}
5686
c0f3af97
L		 5687static int
5688bad_implicit_operand (int xmm)
5689{
91d6fa6a
NC		 5690 const char *ireg = xmm ? "xmm0" : "ymm0";
5691
c0f3af97
L		 5692 if (intel_syntax)
5693 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5694 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5695 else
5696 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5697 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5698 return 0;
5699}
5700
29b0f896 5701static int
e3bb37b5 5702process_operands (void)
29b0f896
AM		 5703{
5704 /* Default segment register this instruction will use for memory
5705 accesses. 0 means unknown. This is only for optimizing out
5706 unnecessary segment overrides. */
5707 const seg_entry *default_seg = 0;
5708
2426c15f 5709 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5710 {
91d6fa6a
NC		 5711 unsigned int dupl = i.operands;
5712 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5713 unsigned int j;
5714
c0f3af97 5715 /* The destination must be an xmm register. */
9c2799c2 5716 gas_assert (i.reg_operands
91d6fa6a 5717 && MAX_OPERANDS > dupl
7ab9ffdd 5718 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5719
5720 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5721 {
c0f3af97 5722 /* The first operand is implicit and must be xmm0. */
9c2799c2 5723 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5724 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5725 return bad_implicit_operand (1);
5726
8cd7925b 5727 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5728 {
5729 /* Keep xmm0 for instructions with VEX prefix and 3
5730 sources. */
5731 goto duplicate;
5732 }
e2ec9d29 5733 else
c0f3af97
L		 5734 {
5735 /* We remove the first xmm0 and keep the number of
5736 operands unchanged, which in fact duplicates the
5737 destination. */
5738 for (j = 1; j < i.operands; j++)
5739 {
5740 i.op[j - 1] = i.op[j];
5741 i.types[j - 1] = i.types[j];
5742 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5743 }
5744 }
5745 }
5746 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5747 {
91d6fa6a 5748 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5749 && (i.tm.opcode_modifier.vexsources
5750 == VEX3SOURCES));
c0f3af97
L		 5751
5752 /* Add the implicit xmm0 for instructions with VEX prefix
5753 and 3 sources. */
5754 for (j = i.operands; j > 0; j--)
5755 {
5756 i.op[j] = i.op[j - 1];
5757 i.types[j] = i.types[j - 1];
5758 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5759 }
5760 i.op[0].regs
5761 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5762 i.types[0] = regxmm;
c0f3af97
L		 5763 i.tm.operand_types[0] = regxmm;
5764
5765 i.operands += 2;
5766 i.reg_operands += 2;
5767 i.tm.operands += 2;
5768
91d6fa6a 5769 dupl++;
c0f3af97 5770 dest++;
91d6fa6a
NC		 5771 i.op[dupl] = i.op[dest];
5772 i.types[dupl] = i.types[dest];
5773 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5774 }
c0f3af97
L		 5775 else
5776 {
5777duplicate:
5778 i.operands++;
5779 i.reg_operands++;
5780 i.tm.operands++;
5781
91d6fa6a
NC		 5782 i.op[dupl] = i.op[dest];
5783 i.types[dupl] = i.types[dest];
5784 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5785 }
5786
5787 if (i.tm.opcode_modifier.immext)
5788 process_immext ();
5789 }
5790 else if (i.tm.opcode_modifier.firstxmm0)
5791 {
5792 unsigned int j;
5793
43234a1e 5794 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5795 gas_assert (i.reg_operands
7ab9ffdd 5796 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5797 || operand_type_equal (&i.types[0], &regymm)
5798 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5799 if (register_number (i.op[0].regs) != 0)
c0f3af97 5800 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5801
5802 for (j = 1; j < i.operands; j++)
5803 {
5804 i.op[j - 1] = i.op[j];
5805 i.types[j - 1] = i.types[j];
5806
5807 /* We need to adjust fields in i.tm since they are used by
5808 build_modrm_byte. */
5809 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5810 }
5811
e2ec9d29
L		 5812 i.operands--;
5813 i.reg_operands--;
e2ec9d29
L		 5814 i.tm.operands--;
5815 }
5816 else if (i.tm.opcode_modifier.regkludge)
5817 {
5818 /* The imul $imm, %reg instruction is converted into
5819 imul $imm, %reg, %reg, and the clr %reg instruction
5820 is converted into xor %reg, %reg. */
5821
5822 unsigned int first_reg_op;
5823
5824 if (operand_type_check (i.types[0], reg))
5825 first_reg_op = 0;
5826 else
5827 first_reg_op = 1;
5828 /* Pretend we saw the extra register operand. */
9c2799c2 5829 gas_assert (i.reg_operands == 1
7ab9ffdd 5830 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5831 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5832 i.types[first_reg_op + 1] = i.types[first_reg_op];
5833 i.operands++;
5834 i.reg_operands++;
29b0f896
AM		 5835 }
5836
40fb9820 5837 if (i.tm.opcode_modifier.shortform)
29b0f896 5838 {
40fb9820
L		 5839 if (i.types[0].bitfield.sreg2
5840 || i.types[0].bitfield.sreg3)
29b0f896 5841 {
4eed87de
AM		 5842 if (i.tm.base_opcode == POP_SEG_SHORT
5843 && i.op[0].regs->reg_num == 1)
29b0f896 5844 {
a87af027 5845 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5846 return 0;
29b0f896 5847 }
4eed87de
AM		 5848 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5849 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5850 i.rex |= REX_B;
4eed87de
AM		 5851 }
5852 else
5853 {
7ab9ffdd 5854 /* The register or float register operand is in operand
85f10a01 5855 0 or 1. */
40fb9820 5856 unsigned int op;
7ab9ffdd
L		 5857
5858 if (i.types[0].bitfield.floatreg
5859 || operand_type_check (i.types[0], reg))
5860 op = 0;
5861 else
5862 op = 1;
4eed87de
AM		 5863 /* Register goes in low 3 bits of opcode. */
5864 i.tm.base_opcode |= i.op[op].regs->reg_num;
5865 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5866 i.rex |= REX_B;
40fb9820 5867 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5868 {
4eed87de
AM		 5869 /* Warn about some common errors, but press on regardless.
5870 The first case can be generated by gcc (<= 2.8.1). */
5871 if (i.operands == 2)
5872 {
5873 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5874 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5875 register_prefix, i.op[!intel_syntax].regs->reg_name,
5876 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5877 }
5878 else
5879 {
5880 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5881 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5882 register_prefix, i.op[0].regs->reg_name);
4eed87de 5883 }
29b0f896
AM		 5884 }
5885 }
5886 }
40fb9820 5887 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5888 {
5889 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5890 must be put into the modrm byte). Now, we make the modrm and
5891 index base bytes based on all the info we've collected. */
29b0f896
AM		 5892
5893 default_seg = build_modrm_byte ();
5894 }
8a2ed489 5895 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5896 {
5897 default_seg = &ds;
5898 }
40fb9820 5899 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5900 {
5901 /* For the string instructions that allow a segment override
5902 on one of their operands, the default segment is ds. */
5903 default_seg = &ds;
5904 }
5905
75178d9d
L		 5906 if (i.tm.base_opcode == 0x8d /* lea */
5907 && i.seg[0]
5908 && !quiet_warnings)
30123838 5909 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5910
5911 /* If a segment was explicitly specified, and the specified segment
5912 is not the default, use an opcode prefix to select it. If we
5913 never figured out what the default segment is, then default_seg
5914 will be zero at this point, and the specified segment prefix will
5915 always be used. */
29b0f896
AM		 5916 if ((i.seg[0]) && (i.seg[0] != default_seg))
5917 {
5918 if (!add_prefix (i.seg[0]->seg_prefix))
5919 return 0;
5920 }
5921 return 1;
5922}
5923
5924static const seg_entry *
e3bb37b5 5925build_modrm_byte (void)
29b0f896
AM		 5926{
5927 const seg_entry *default_seg = 0;
c0f3af97 5928 unsigned int source, dest;
8cd7925b 5929 int vex_3_sources;
c0f3af97
L		 5930
5931 /* The first operand of instructions with VEX prefix and 3 sources
5932 must be VEX_Imm4. */
8cd7925b 5933 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5934 if (vex_3_sources)
5935 {
91d6fa6a 5936 unsigned int nds, reg_slot;
4c2c6516 5937 expressionS *exp;
c0f3af97 5938
922d8de8 5939 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5940 && i.tm.opcode_modifier.immext)
5941 {
5942 dest = i.operands - 2;
5943 gas_assert (dest == 3);
5944 }
922d8de8 5945 else
a683cc34 5946 dest = i.operands - 1;
c0f3af97 5947 nds = dest - 1;
922d8de8 5948
a683cc34
SP		 5949 /* There are 2 kinds of instructions:
5950 1. 5 operands: 4 register operands or 3 register operands
5951 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5952 VexW0 or VexW1. The destination must be either XMM, YMM or
5953 ZMM register.
a683cc34
SP		 5954 2. 4 operands: 4 register operands or 3 register operands
5955 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5956 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5957 || (i.reg_operands == 3 && i.mem_operands == 1))
5958 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5959 && (i.tm.opcode_modifier.veximmext
5960 || (i.imm_operands == 1
5961 && i.types[0].bitfield.vec_imm4
5962 && (i.tm.opcode_modifier.vexw == VEXW0
5963 || i.tm.opcode_modifier.vexw == VEXW1)
5964 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5965 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5966 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5967
5968 if (i.imm_operands == 0)
5969 {
5970 /* When there is no immediate operand, generate an 8bit
5971 immediate operand to encode the first operand. */
5972 exp = &im_expressions[i.imm_operands++];
5973 i.op[i.operands].imms = exp;
5974 i.types[i.operands] = imm8;
5975 i.operands++;
5976 /* If VexW1 is set, the first operand is the source and
5977 the second operand is encoded in the immediate operand. */
5978 if (i.tm.opcode_modifier.vexw == VEXW1)
5979 {
5980 source = 0;
5981 reg_slot = 1;
5982 }
5983 else
5984 {
5985 source = 1;
5986 reg_slot = 0;
5987 }
5988
5989 /* FMA swaps REG and NDS. */
5990 if (i.tm.cpu_flags.bitfield.cpufma)
5991 {
5992 unsigned int tmp;
5993 tmp = reg_slot;
5994 reg_slot = nds;
5995 nds = tmp;
5996 }
5997
24981e7b
L		 5998 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5999 &regxmm)
a683cc34 6000 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6001 &regymm)
6002 || operand_type_equal (&i.tm.operand_types[reg_slot],
6003 &regzmm));
a683cc34 6004 exp->X_op = O_constant;
4c692bc7 6005 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6006 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6007 }
922d8de8 6008 else
a683cc34
SP		 6009 {
6010 unsigned int imm_slot;
6011
6012 if (i.tm.opcode_modifier.vexw == VEXW0)
6013 {
6014 /* If VexW0 is set, the third operand is the source and
6015 the second operand is encoded in the immediate
6016 operand. */
6017 source = 2;
6018 reg_slot = 1;
6019 }
6020 else
6021 {
6022 /* VexW1 is set, the second operand is the source and
6023 the third operand is encoded in the immediate
6024 operand. */
6025 source = 1;
6026 reg_slot = 2;
6027 }
6028
6029 if (i.tm.opcode_modifier.immext)
6030 {
6031 /* When ImmExt is set, the immdiate byte is the last
6032 operand. */
6033 imm_slot = i.operands - 1;
6034 source--;
6035 reg_slot--;
6036 }
6037 else
6038 {
6039 imm_slot = 0;
6040
6041 /* Turn on Imm8 so that output_imm will generate it. */
6042 i.types[imm_slot].bitfield.imm8 = 1;
6043 }
6044
24981e7b
L		 6045 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6046 &regxmm)
6047 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6048 &regymm)
6049 || operand_type_equal (&i.tm.operand_types[reg_slot],
6050 &regzmm));
a683cc34 6051 i.op[imm_slot].imms->X_add_number
4c692bc7 6052 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6053 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6054 }
6055
6056 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6057 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6058 &regymm)
6059 || operand_type_equal (&i.tm.operand_types[nds],
6060 &regzmm));
dae39acc 6061 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6062 }
6063 else
6064 source = dest = 0;
29b0f896
AM		 6065
6066 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6067 implicit registers do not count. If there are 3 register
6068 operands, it must be a instruction with VexNDS. For a
6069 instruction with VexNDD, the destination register is encoded
6070 in VEX prefix. If there are 4 register operands, it must be
6071 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6072 if (i.mem_operands == 0
6073 && ((i.reg_operands == 2
2426c15f 6074 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6075 || (i.reg_operands == 3
2426c15f 6076 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6077 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6078 {
cab737b9
L		 6079 switch (i.operands)
6080 {
6081 case 2:
6082 source = 0;
6083 break;
6084 case 3:
c81128dc
L		 6085 /* When there are 3 operands, one of them may be immediate,
6086 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6087 the first operand must be shift count register (cl) or it
6088 is an instruction with VexNDS. */
9c2799c2 6089 gas_assert (i.imm_operands == 1
7ab9ffdd 6090 || (i.imm_operands == 0
2426c15f 6091 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6092 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6093 if (operand_type_check (i.types[0], imm)
6094 || i.types[0].bitfield.shiftcount)
6095 source = 1;
6096 else
6097 source = 0;
cab737b9
L		 6098 break;
6099 case 4:
368d64cc
L		 6100 /* When there are 4 operands, the first two must be 8bit
6101 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6102 one.
6103
6104 For instructions with VexNDS, if the first operand
6105 an imm8, the source operand is the 2nd one. If the last
6106 operand is imm8, the source operand is the first one. */
9c2799c2 6107 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6108 && i.types[0].bitfield.imm8
6109 && i.types[1].bitfield.imm8)
2426c15f 6110 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6111 && i.imm_operands == 1
6112 && (i.types[0].bitfield.imm8
43234a1e
L		 6113 || i.types[i.operands - 1].bitfield.imm8
6114 || i.rounding)));
9f2670f2
L		 6115 if (i.imm_operands == 2)
6116 source = 2;
6117 else
c0f3af97
L		 6118 {
6119 if (i.types[0].bitfield.imm8)
6120 source = 1;
6121 else
6122 source = 0;
6123 }
c0f3af97
L		 6124 break;
6125 case 5:
43234a1e
L		 6126 if (i.tm.opcode_modifier.evex)
6127 {
6128 /* For EVEX instructions, when there are 5 operands, the
6129 first one must be immediate operand. If the second one
6130 is immediate operand, the source operand is the 3th
6131 one. If the last one is immediate operand, the source
6132 operand is the 2nd one. */
6133 gas_assert (i.imm_operands == 2
6134 && i.tm.opcode_modifier.sae
6135 && operand_type_check (i.types[0], imm));
6136 if (operand_type_check (i.types[1], imm))
6137 source = 2;
6138 else if (operand_type_check (i.types[4], imm))
6139 source = 1;
6140 else
6141 abort ();
6142 }
cab737b9
L		 6143 break;
6144 default:
6145 abort ();
6146 }
6147
c0f3af97
L		 6148 if (!vex_3_sources)
6149 {
6150 dest = source + 1;
6151
43234a1e
L		 6152 /* RC/SAE operand could be between DEST and SRC. That happens
6153 when one operand is GPR and the other one is XMM/YMM/ZMM
6154 register. */
6155 if (i.rounding && i.rounding->operand == (int) dest)
6156 dest++;
6157
2426c15f 6158 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6159 {
43234a1e
L		 6160 /* For instructions with VexNDS, the register-only source
6161 operand must be 32/64bit integer, XMM, YMM or ZMM
6162 register. It is encoded in VEX prefix. We need to
6163 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6164
6165 i386_operand_type op;
6166 unsigned int vvvv;
6167
6168 /* Check register-only source operand when two source
6169 operands are swapped. */
6170 if (!i.tm.operand_types[source].bitfield.baseindex
6171 && i.tm.operand_types[dest].bitfield.baseindex)
6172 {
6173 vvvv = source;
6174 source = dest;
6175 }
6176 else
6177 vvvv = dest;
6178
6179 op = i.tm.operand_types[vvvv];
fa99fab2 6180 op.bitfield.regmem = 0;
c0f3af97 6181 if ((dest + 1) >= i.operands
ac4eb736
AM		 6182 || (!op.bitfield.reg32
6183 && op.bitfield.reg64
f12dc422 6184 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6185 && !operand_type_equal (&op, &regymm)
6186 && !operand_type_equal (&op, &regzmm)
6187 && !operand_type_equal (&op, &regmask)))
c0f3af97 6188 abort ();
f12dc422 6189 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6190 dest++;
6191 }
6192 }
29b0f896
AM		 6193
6194 i.rm.mode = 3;
6195 /* One of the register operands will be encoded in the i.tm.reg
6196 field, the other in the combined i.tm.mode and i.tm.regmem
6197 fields. If no form of this instruction supports a memory
6198 destination operand, then we assume the source operand may
6199 sometimes be a memory operand and so we need to store the
6200 destination in the i.rm.reg field. */
40fb9820
L		 6201 if (!i.tm.operand_types[dest].bitfield.regmem
6202 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6203 {
6204 i.rm.reg = i.op[dest].regs->reg_num;
6205 i.rm.regmem = i.op[source].regs->reg_num;
6206 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6207 i.rex |= REX_R;
43234a1e
L		 6208 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6209 i.vrex |= REX_R;
29b0f896 6210 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6211 i.rex |= REX_B;
43234a1e
L		 6212 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6213 i.vrex |= REX_B;
29b0f896
AM		 6214 }
6215 else
6216 {
6217 i.rm.reg = i.op[source].regs->reg_num;
6218 i.rm.regmem = i.op[dest].regs->reg_num;
6219 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6220 i.rex |= REX_B;
43234a1e
L		 6221 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6222 i.vrex |= REX_B;
29b0f896 6223 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6224 i.rex |= REX_R;
43234a1e
L		 6225 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6226 i.vrex |= REX_R;
29b0f896 6227 }
161a04f6 6228 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6229 {
40fb9820
L		 6230 if (!i.types[0].bitfield.control
6231 && !i.types[1].bitfield.control)
c4a530c5 6232 abort ();
161a04f6 6233 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6234 add_prefix (LOCK_PREFIX_OPCODE);
6235 }
29b0f896
AM		 6236 }
6237 else
6238 { /* If it's not 2 reg operands... */
c0f3af97
L		 6239 unsigned int mem;
6240
29b0f896
AM		 6241 if (i.mem_operands)
6242 {
6243 unsigned int fake_zero_displacement = 0;
99018f42 6244 unsigned int op;
4eed87de 6245
7ab9ffdd
L		 6246 for (op = 0; op < i.operands; op++)
6247 if (operand_type_check (i.types[op], anymem))
6248 break;
7ab9ffdd 6249 gas_assert (op < i.operands);
29b0f896 6250
6c30d220
L		 6251 if (i.tm.opcode_modifier.vecsib)
6252 {
6253 if (i.index_reg->reg_num == RegEiz
6254 || i.index_reg->reg_num == RegRiz)
6255 abort ();
6256
6257 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6258 if (!i.base_reg)
6259 {
6260 i.sib.base = NO_BASE_REGISTER;
6261 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6262 /* No Vec_Disp8 if there is no base. */
6263 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6264 i.types[op].bitfield.disp8 = 0;
6265 i.types[op].bitfield.disp16 = 0;
6266 i.types[op].bitfield.disp64 = 0;
6267 if (flag_code != CODE_64BIT)
6268 {
6269 /* Must be 32 bit */
6270 i.types[op].bitfield.disp32 = 1;
6271 i.types[op].bitfield.disp32s = 0;
6272 }
6273 else
6274 {
6275 i.types[op].bitfield.disp32 = 0;
6276 i.types[op].bitfield.disp32s = 1;
6277 }
6278 }
6279 i.sib.index = i.index_reg->reg_num;
6280 if ((i.index_reg->reg_flags & RegRex) != 0)
6281 i.rex |= REX_X;
43234a1e
L		 6282 if ((i.index_reg->reg_flags & RegVRex) != 0)
6283 i.vrex |= REX_X;
6c30d220
L		 6284 }
6285
29b0f896
AM		 6286 default_seg = &ds;
6287
6288 if (i.base_reg == 0)
6289 {
6290 i.rm.mode = 0;
6291 if (!i.disp_operands)
6c30d220
L		 6292 {
6293 fake_zero_displacement = 1;
6294 /* Instructions with VSIB byte need 32bit displacement
6295 if there is no base register. */
6296 if (i.tm.opcode_modifier.vecsib)
6297 i.types[op].bitfield.disp32 = 1;
6298 }
29b0f896
AM		 6299 if (i.index_reg == 0)
6300 {
6c30d220 6301 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6302 /* Operand is just <disp> */
20f0a1fc 6303 if (flag_code == CODE_64BIT)
29b0f896
AM		 6304 {
6305 /* 64bit mode overwrites the 32bit absolute
6306 addressing by RIP relative addressing and
6307 absolute addressing is encoded by one of the
6308 redundant SIB forms. */
6309 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6310 i.sib.base = NO_BASE_REGISTER;
6311 i.sib.index = NO_INDEX_REGISTER;
fc225355 6312 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6313 ? disp32s : disp32);
20f0a1fc 6314 }
fc225355
L		 6315 else if ((flag_code == CODE_16BIT)
6316 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6317 {
6318 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6319 i.types[op] = disp16;
20f0a1fc
NC		 6320 }
6321 else
6322 {
6323 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6324 i.types[op] = disp32;
29b0f896
AM		 6325 }
6326 }
6c30d220 6327 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6328 {
6c30d220 6329 /* !i.base_reg && i.index_reg */
db51cc60
L		 6330 if (i.index_reg->reg_num == RegEiz
6331 || i.index_reg->reg_num == RegRiz)
6332 i.sib.index = NO_INDEX_REGISTER;
6333 else
6334 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6335 i.sib.base = NO_BASE_REGISTER;
6336 i.sib.scale = i.log2_scale_factor;
6337 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6338 /* No Vec_Disp8 if there is no base. */
6339 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6340 i.types[op].bitfield.disp8 = 0;
6341 i.types[op].bitfield.disp16 = 0;
6342 i.types[op].bitfield.disp64 = 0;
29b0f896 6343 if (flag_code != CODE_64BIT)
40fb9820
L		 6344 {
6345 /* Must be 32 bit */
6346 i.types[op].bitfield.disp32 = 1;
6347 i.types[op].bitfield.disp32s = 0;
6348 }
29b0f896 6349 else
40fb9820
L		 6350 {
6351 i.types[op].bitfield.disp32 = 0;
6352 i.types[op].bitfield.disp32s = 1;
6353 }
29b0f896 6354 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6355 i.rex |= REX_X;
29b0f896
AM		 6356 }
6357 }
6358 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6359 else if (i.base_reg->reg_num == RegRip ||
6360 i.base_reg->reg_num == RegEip)
29b0f896 6361 {
6c30d220 6362 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6363 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6364 i.types[op].bitfield.disp8 = 0;
6365 i.types[op].bitfield.disp16 = 0;
6366 i.types[op].bitfield.disp32 = 0;
6367 i.types[op].bitfield.disp32s = 1;
6368 i.types[op].bitfield.disp64 = 0;
43234a1e 6369 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6370 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6371 if (! i.disp_operands)
6372 fake_zero_displacement = 1;
29b0f896 6373 }
40fb9820 6374 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6375 {
6c30d220 6376 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6377 switch (i.base_reg->reg_num)
6378 {
6379 case 3: /* (%bx) */
6380 if (i.index_reg == 0)
6381 i.rm.regmem = 7;
6382 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6383 i.rm.regmem = i.index_reg->reg_num - 6;
6384 break;
6385 case 5: /* (%bp) */
6386 default_seg = &ss;
6387 if (i.index_reg == 0)
6388 {
6389 i.rm.regmem = 6;
40fb9820 6390 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6391 {
6392 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6393 if (i.tm.operand_types[op].bitfield.vec_disp8)
6394 i.types[op].bitfield.vec_disp8 = 1;
6395 else
6396 i.types[op].bitfield.disp8 = 1;
252b5132 6397 fake_zero_displacement = 1;
29b0f896
AM		 6398 }
6399 }
6400 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6401 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6402 break;
6403 default: /* (%si) -> 4 or (%di) -> 5 */
6404 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6405 }
6406 i.rm.mode = mode_from_disp_size (i.types[op]);
6407 }
6408 else /* i.base_reg and 32/64 bit mode */
6409 {
6410 if (flag_code == CODE_64BIT
40fb9820
L		 6411 && operand_type_check (i.types[op], disp))
6412 {
6413 i386_operand_type temp;
0dfbf9d7 6414 operand_type_set (&temp, 0);
40fb9820 6415 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6416 temp.bitfield.vec_disp8
6417 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6418 i.types[op] = temp;
6419 if (i.prefix[ADDR_PREFIX] == 0)
6420 i.types[op].bitfield.disp32s = 1;
6421 else
6422 i.types[op].bitfield.disp32 = 1;
6423 }
20f0a1fc 6424
6c30d220
L		 6425 if (!i.tm.opcode_modifier.vecsib)
6426 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6427 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6428 i.rex |= REX_B;
29b0f896
AM		 6429 i.sib.base = i.base_reg->reg_num;
6430 /* x86-64 ignores REX prefix bit here to avoid decoder
6431 complications. */
848930b2
JB		 6432 if (!(i.base_reg->reg_flags & RegRex)
6433 && (i.base_reg->reg_num == EBP_REG_NUM
6434 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6435 default_seg = &ss;
848930b2 6436 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6437 {
848930b2 6438 fake_zero_displacement = 1;
43234a1e
L		 6439 if (i.tm.operand_types [op].bitfield.vec_disp8)
6440 i.types[op].bitfield.vec_disp8 = 1;
6441 else
6442 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6443 }
6444 i.sib.scale = i.log2_scale_factor;
6445 if (i.index_reg == 0)
6446 {
6c30d220 6447 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6448 /* <disp>(%esp) becomes two byte modrm with no index
6449 register. We've already stored the code for esp
6450 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6451 Any base register besides %esp will not use the
6452 extra modrm byte. */
6453 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6454 }
6c30d220 6455 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6456 {
db51cc60
L		 6457 if (i.index_reg->reg_num == RegEiz
6458 || i.index_reg->reg_num == RegRiz)
6459 i.sib.index = NO_INDEX_REGISTER;
6460 else
6461 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6462 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6463 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6464 i.rex |= REX_X;
29b0f896 6465 }
67a4f2b7
AO		 6466
6467 if (i.disp_operands
6468 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6469 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6470 i.rm.mode = 0;
6471 else
a501d77e
L		 6472 {
6473 if (!fake_zero_displacement
6474 && !i.disp_operands
6475 && i.disp_encoding)
6476 {
6477 fake_zero_displacement = 1;
6478 if (i.disp_encoding == disp_encoding_8bit)
6479 i.types[op].bitfield.disp8 = 1;
6480 else
6481 i.types[op].bitfield.disp32 = 1;
6482 }
6483 i.rm.mode = mode_from_disp_size (i.types[op]);
6484 }
29b0f896 6485 }
252b5132 6486
29b0f896
AM		 6487 if (fake_zero_displacement)
6488 {
6489 /* Fakes a zero displacement assuming that i.types[op]
6490 holds the correct displacement size. */
6491 expressionS *exp;
6492
9c2799c2 6493 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6494 exp = &disp_expressions[i.disp_operands++];
6495 i.op[op].disps = exp;
6496 exp->X_op = O_constant;
6497 exp->X_add_number = 0;
6498 exp->X_add_symbol = (symbolS *) 0;
6499 exp->X_op_symbol = (symbolS *) 0;
6500 }
c0f3af97
L		 6501
6502 mem = op;
29b0f896 6503 }
c0f3af97
L		 6504 else
6505 mem = ~0;
252b5132 6506
8c43a48b 6507 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6508 {
6509 if (operand_type_check (i.types[0], imm))
6510 i.vex.register_specifier = NULL;
6511 else
6512 {
6513 /* VEX.vvvv encodes one of the sources when the first
6514 operand is not an immediate. */
1ef99a7b 6515 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6516 i.vex.register_specifier = i.op[0].regs;
6517 else
6518 i.vex.register_specifier = i.op[1].regs;
6519 }
6520
6521 /* Destination is a XMM register encoded in the ModRM.reg
6522 and VEX.R bit. */
6523 i.rm.reg = i.op[2].regs->reg_num;
6524 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6525 i.rex |= REX_R;
6526
6527 /* ModRM.rm and VEX.B encodes the other source. */
6528 if (!i.mem_operands)
6529 {
6530 i.rm.mode = 3;
6531
1ef99a7b 6532 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6533 i.rm.regmem = i.op[1].regs->reg_num;
6534 else
6535 i.rm.regmem = i.op[0].regs->reg_num;
6536
6537 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6538 i.rex |= REX_B;
6539 }
6540 }
2426c15f 6541 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6542 {
6543 i.vex.register_specifier = i.op[2].regs;
6544 if (!i.mem_operands)
6545 {
6546 i.rm.mode = 3;
6547 i.rm.regmem = i.op[1].regs->reg_num;
6548 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6549 i.rex |= REX_B;
6550 }
6551 }
29b0f896
AM		 6552 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6553 (if any) based on i.tm.extension_opcode. Again, we must be
6554 careful to make sure that segment/control/debug/test/MMX
6555 registers are coded into the i.rm.reg field. */
f88c9eb0 6556 else if (i.reg_operands)
29b0f896 6557 {
99018f42 6558 unsigned int op;
7ab9ffdd
L		 6559 unsigned int vex_reg = ~0;
6560
6561 for (op = 0; op < i.operands; op++)
6562 if (i.types[op].bitfield.reg8
6563 || i.types[op].bitfield.reg16
6564 || i.types[op].bitfield.reg32
6565 || i.types[op].bitfield.reg64
6566 || i.types[op].bitfield.regmmx
6567 || i.types[op].bitfield.regxmm
6568 || i.types[op].bitfield.regymm
7e8b059b 6569 || i.types[op].bitfield.regbnd
43234a1e
L		 6570 || i.types[op].bitfield.regzmm
6571 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6572 || i.types[op].bitfield.sreg2
6573 || i.types[op].bitfield.sreg3
6574 || i.types[op].bitfield.control
6575 || i.types[op].bitfield.debug
6576 || i.types[op].bitfield.test)
6577 break;
c0209578 6578
7ab9ffdd
L		 6579 if (vex_3_sources)
6580 op = dest;
2426c15f 6581 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6582 {
6583 /* For instructions with VexNDS, the register-only
6584 source operand is encoded in VEX prefix. */
6585 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6586
7ab9ffdd 6587 if (op > mem)
c0f3af97 6588 {
7ab9ffdd
L		 6589 vex_reg = op++;
6590 gas_assert (op < i.operands);
c0f3af97
L		 6591 }
6592 else
c0f3af97 6593 {
f12dc422
L		 6594 /* Check register-only source operand when two source
6595 operands are swapped. */
6596 if (!i.tm.operand_types[op].bitfield.baseindex
6597 && i.tm.operand_types[op + 1].bitfield.baseindex)
6598 {
6599 vex_reg = op;
6600 op += 2;
6601 gas_assert (mem == (vex_reg + 1)
6602 && op < i.operands);
6603 }
6604 else
6605 {
6606 vex_reg = op + 1;
6607 gas_assert (vex_reg < i.operands);
6608 }
c0f3af97 6609 }
7ab9ffdd 6610 }
2426c15f 6611 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6612 {
f12dc422 6613 /* For instructions with VexNDD, the register destination
7ab9ffdd 6614 is encoded in VEX prefix. */
f12dc422
L		 6615 if (i.mem_operands == 0)
6616 {
6617 /* There is no memory operand. */
6618 gas_assert ((op + 2) == i.operands);
6619 vex_reg = op + 1;
6620 }
6621 else
8d63c93e 6622 {
f12dc422
L		 6623 /* There are only 2 operands. */
6624 gas_assert (op < 2 && i.operands == 2);
6625 vex_reg = 1;
6626 }
7ab9ffdd
L		 6627 }
6628 else
6629 gas_assert (op < i.operands);
99018f42 6630
7ab9ffdd
L		 6631 if (vex_reg != (unsigned int) ~0)
6632 {
f12dc422 6633 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6634
f12dc422
L		 6635 if (type->bitfield.reg32 != 1
6636 && type->bitfield.reg64 != 1
6637 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6638 && !operand_type_equal (type, &regymm)
6639 && !operand_type_equal (type, &regzmm)
6640 && !operand_type_equal (type, &regmask))
7ab9ffdd 6641 abort ();
f88c9eb0 6642
7ab9ffdd
L		 6643 i.vex.register_specifier = i.op[vex_reg].regs;
6644 }
6645
1b9f0c97
L		 6646 /* Don't set OP operand twice. */
6647 if (vex_reg != op)
7ab9ffdd 6648 {
1b9f0c97
L		 6649 /* If there is an extension opcode to put here, the
6650 register number must be put into the regmem field. */
6651 if (i.tm.extension_opcode != None)
6652 {
6653 i.rm.regmem = i.op[op].regs->reg_num;
6654 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6655 i.rex |= REX_B;
43234a1e
L		 6656 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6657 i.vrex |= REX_B;
1b9f0c97
L		 6658 }
6659 else
6660 {
6661 i.rm.reg = i.op[op].regs->reg_num;
6662 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6663 i.rex |= REX_R;
43234a1e
L		 6664 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6665 i.vrex |= REX_R;
1b9f0c97 6666 }
7ab9ffdd 6667 }
252b5132 6668
29b0f896
AM		 6669 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6670 must set it to 3 to indicate this is a register operand
6671 in the regmem field. */
6672 if (!i.mem_operands)
6673 i.rm.mode = 3;
6674 }
252b5132 6675
29b0f896 6676 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6677 if (i.tm.extension_opcode != None)
29b0f896
AM		 6678 i.rm.reg = i.tm.extension_opcode;
6679 }
6680 return default_seg;
6681}
252b5132 6682
29b0f896 6683static void
e3bb37b5 6684output_branch (void)
29b0f896
AM		 6685{
6686 char *p;
f8a5c266 6687 int size;
29b0f896
AM		 6688 int code16;
6689 int prefix;
6690 relax_substateT subtype;
6691 symbolS *sym;
6692 offsetT off;
6693
f8a5c266 6694 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6695 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6696
6697 prefix = 0;
6698 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6699 {
29b0f896
AM		 6700 prefix = 1;
6701 i.prefixes -= 1;
6702 code16 ^= CODE16;
252b5132 6703 }
29b0f896
AM		 6704 /* Pentium4 branch hints. */
6705 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6706 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6707 {
29b0f896
AM		 6708 prefix++;
6709 i.prefixes--;
6710 }
6711 if (i.prefix[REX_PREFIX] != 0)
6712 {
6713 prefix++;
6714 i.prefixes--;
2f66722d
AM		 6715 }
6716
7e8b059b
L		 6717 /* BND prefixed jump. */
6718 if (i.prefix[BND_PREFIX] != 0)
6719 {
6720 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6721 i.prefixes -= 1;
6722 }
6723
29b0f896
AM		 6724 if (i.prefixes != 0 && !intel_syntax)
6725 as_warn (_("skipping prefixes on this instruction"));
6726
6727 /* It's always a symbol; End frag & setup for relax.
6728 Make sure there is enough room in this frag for the largest
6729 instruction we may generate in md_convert_frag. This is 2
6730 bytes for the opcode and room for the prefix and largest
6731 displacement. */
6732 frag_grow (prefix + 2 + 4);
6733 /* Prefix and 1 opcode byte go in fr_fix. */
6734 p = frag_more (prefix + 1);
6735 if (i.prefix[DATA_PREFIX] != 0)
6736 *p++ = DATA_PREFIX_OPCODE;
6737 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6738 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6739 *p++ = i.prefix[SEG_PREFIX];
6740 if (i.prefix[REX_PREFIX] != 0)
6741 *p++ = i.prefix[REX_PREFIX];
6742 *p = i.tm.base_opcode;
6743
6744 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6745 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6746 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6747 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6748 else
f8a5c266 6749 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6750 subtype |= code16;
3e73aa7c 6751
29b0f896
AM		 6752 sym = i.op[0].disps->X_add_symbol;
6753 off = i.op[0].disps->X_add_number;
3e73aa7c 6754
29b0f896
AM		 6755 if (i.op[0].disps->X_op != O_constant
6756 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6757 {
29b0f896
AM		 6758 /* Handle complex expressions. */
6759 sym = make_expr_symbol (i.op[0].disps);
6760 off = 0;
6761 }
3e73aa7c 6762
29b0f896
AM		 6763 /* 1 possible extra opcode + 4 byte displacement go in var part.
6764 Pass reloc in fr_var. */
d258b828 6765 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6766}
3e73aa7c 6767
29b0f896 6768static void
e3bb37b5 6769output_jump (void)
29b0f896
AM		 6770{
6771 char *p;
6772 int size;
3e02c1cc 6773 fixS *fixP;
29b0f896 6774
40fb9820 6775 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6776 {
6777 /* This is a loop or jecxz type instruction. */
6778 size = 1;
6779 if (i.prefix[ADDR_PREFIX] != 0)
6780 {
6781 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6782 i.prefixes -= 1;
6783 }
6784 /* Pentium4 branch hints. */
6785 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6786 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6787 {
6788 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6789 i.prefixes--;
3e73aa7c
JH		 6790 }
6791 }
29b0f896
AM		 6792 else
6793 {
6794 int code16;
3e73aa7c 6795
29b0f896
AM		 6796 code16 = 0;
6797 if (flag_code == CODE_16BIT)
6798 code16 = CODE16;
3e73aa7c 6799
29b0f896
AM		 6800 if (i.prefix[DATA_PREFIX] != 0)
6801 {
6802 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6803 i.prefixes -= 1;
6804 code16 ^= CODE16;
6805 }
252b5132 6806
29b0f896
AM		 6807 size = 4;
6808 if (code16)
6809 size = 2;
6810 }
9fcc94b6 6811
29b0f896
AM		 6812 if (i.prefix[REX_PREFIX] != 0)
6813 {
6814 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6815 i.prefixes -= 1;
6816 }
252b5132 6817
7e8b059b
L		 6818 /* BND prefixed jump. */
6819 if (i.prefix[BND_PREFIX] != 0)
6820 {
6821 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6822 i.prefixes -= 1;
6823 }
6824
29b0f896
AM		 6825 if (i.prefixes != 0 && !intel_syntax)
6826 as_warn (_("skipping prefixes on this instruction"));
e0890092 6827
42164a71
L		 6828 p = frag_more (i.tm.opcode_length + size);
6829 switch (i.tm.opcode_length)
6830 {
6831 case 2:
6832 *p++ = i.tm.base_opcode >> 8;
6833 case 1:
6834 *p++ = i.tm.base_opcode;
6835 break;
6836 default:
6837 abort ();
6838 }
e0890092 6839
3e02c1cc 6840 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6841 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6842
6843 /* All jumps handled here are signed, but don't use a signed limit
6844 check for 32 and 16 bit jumps as we want to allow wrap around at
6845 4G and 64k respectively. */
6846 if (size == 1)
6847 fixP->fx_signed = 1;
29b0f896 6848}
e0890092 6849
29b0f896 6850static void
e3bb37b5 6851output_interseg_jump (void)
29b0f896
AM		 6852{
6853 char *p;
6854 int size;
6855 int prefix;
6856 int code16;
252b5132 6857
29b0f896
AM		 6858 code16 = 0;
6859 if (flag_code == CODE_16BIT)
6860 code16 = CODE16;
a217f122 6861
29b0f896
AM		 6862 prefix = 0;
6863 if (i.prefix[DATA_PREFIX] != 0)
6864 {
6865 prefix = 1;
6866 i.prefixes -= 1;
6867 code16 ^= CODE16;
6868 }
6869 if (i.prefix[REX_PREFIX] != 0)
6870 {
6871 prefix++;
6872 i.prefixes -= 1;
6873 }
252b5132 6874
29b0f896
AM		 6875 size = 4;
6876 if (code16)
6877 size = 2;
252b5132 6878
29b0f896
AM		 6879 if (i.prefixes != 0 && !intel_syntax)
6880 as_warn (_("skipping prefixes on this instruction"));
252b5132 6881
29b0f896
AM		 6882 /* 1 opcode; 2 segment; offset */
6883 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6884
29b0f896
AM		 6885 if (i.prefix[DATA_PREFIX] != 0)
6886 *p++ = DATA_PREFIX_OPCODE;
252b5132 6887
29b0f896
AM		 6888 if (i.prefix[REX_PREFIX] != 0)
6889 *p++ = i.prefix[REX_PREFIX];
252b5132 6890
29b0f896
AM		 6891 *p++ = i.tm.base_opcode;
6892 if (i.op[1].imms->X_op == O_constant)
6893 {
6894 offsetT n = i.op[1].imms->X_add_number;
252b5132 6895
29b0f896
AM		 6896 if (size == 2
6897 && !fits_in_unsigned_word (n)
6898 && !fits_in_signed_word (n))
6899 {
6900 as_bad (_("16-bit jump out of range"));
6901 return;
6902 }
6903 md_number_to_chars (p, n, size);
6904 }
6905 else
6906 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6907 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6908 if (i.op[0].imms->X_op != O_constant)
6909 as_bad (_("can't handle non absolute segment in `%s'"),
6910 i.tm.name);
6911 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6912}
a217f122 6913
29b0f896 6914static void
e3bb37b5 6915output_insn (void)
29b0f896 6916{
2bbd9c25
JJ		 6917 fragS *insn_start_frag;
6918 offsetT insn_start_off;
6919
29b0f896
AM		 6920 /* Tie dwarf2 debug info to the address at the start of the insn.
6921 We can't do this after the insn has been output as the current
6922 frag may have been closed off. eg. by frag_var. */
6923 dwarf2_emit_insn (0);
6924
2bbd9c25
JJ		 6925 insn_start_frag = frag_now;
6926 insn_start_off = frag_now_fix ();
6927
29b0f896 6928 /* Output jumps. */
40fb9820 6929 if (i.tm.opcode_modifier.jump)
29b0f896 6930 output_branch ();
40fb9820
L		 6931 else if (i.tm.opcode_modifier.jumpbyte
6932 || i.tm.opcode_modifier.jumpdword)
29b0f896 6933 output_jump ();
40fb9820 6934 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6935 output_interseg_jump ();
6936 else
6937 {
6938 /* Output normal instructions here. */
6939 char *p;
6940 unsigned char *q;
47465058 6941 unsigned int j;
331d2d0d 6942 unsigned int prefix;
4dffcebc 6943
d022bddd
IT		 6944 /* Some processors fail on LOCK prefix. This options makes
6945 assembler ignore LOCK prefix and serves as a workaround. */
6946 if (omit_lock_prefix)
6947 {
6948 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6949 return;
6950 i.prefix[LOCK_PREFIX] = 0;
6951 }
6952
43234a1e
L		 6953 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6954 don't need the explicit prefix. */
6955 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6956 {
c0f3af97 6957 switch (i.tm.opcode_length)
bc4bd9ab 6958 {
c0f3af97
L		 6959 case 3:
6960 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6961 {
c0f3af97
L		 6962 prefix = (i.tm.base_opcode >> 24) & 0xff;
6963 goto check_prefix;
6964 }
6965 break;
6966 case 2:
6967 if ((i.tm.base_opcode & 0xff0000) != 0)
6968 {
6969 prefix = (i.tm.base_opcode >> 16) & 0xff;
6970 if (i.tm.cpu_flags.bitfield.cpupadlock)
6971 {
4dffcebc 6972check_prefix:
c0f3af97 6973 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6974 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6975 != REPE_PREFIX_OPCODE))
6976 add_prefix (prefix);
6977 }
6978 else
4dffcebc
L		 6979 add_prefix (prefix);
6980 }
c0f3af97
L		 6981 break;
6982 case 1:
6983 break;
6984 default:
6985 abort ();
bc4bd9ab 6986 }
c0f3af97 6987
6d19a37a 6988#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6989 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6990 R_X86_64_GOTTPOFF relocation so that linker can safely
6991 perform IE->LE optimization. */
6992 if (x86_elf_abi == X86_64_X32_ABI
6993 && i.operands == 2
6994 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
6995 && i.prefix[REX_PREFIX] == 0)
6996 add_prefix (REX_OPCODE);
6d19a37a 6997#endif
cf61b747 6998
c0f3af97
L		 6999 /* The prefix bytes. */
7000 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7001 if (*q)
7002 FRAG_APPEND_1_CHAR (*q);
0f10071e 7003 }
ae5c1c7b 7004 else
c0f3af97
L		 7005 {
7006 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7007 if (*q)
7008 switch (j)
7009 {
7010 case REX_PREFIX:
7011 /* REX byte is encoded in VEX prefix. */
7012 break;
7013 case SEG_PREFIX:
7014 case ADDR_PREFIX:
7015 FRAG_APPEND_1_CHAR (*q);
7016 break;
7017 default:
7018 /* There should be no other prefixes for instructions
7019 with VEX prefix. */
7020 abort ();
7021 }
7022
43234a1e
L		 7023 /* For EVEX instructions i.vrex should become 0 after
7024 build_evex_prefix. For VEX instructions upper 16 registers
7025 aren't available, so VREX should be 0. */
7026 if (i.vrex)
7027 abort ();
c0f3af97
L		 7028 /* Now the VEX prefix. */
7029 p = frag_more (i.vex.length);
7030 for (j = 0; j < i.vex.length; j++)
7031 p[j] = i.vex.bytes[j];
7032 }
252b5132 7033
29b0f896 7034 /* Now the opcode; be careful about word order here! */
4dffcebc 7035 if (i.tm.opcode_length == 1)
29b0f896
AM		 7036 {
7037 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7038 }
7039 else
7040 {
4dffcebc 7041 switch (i.tm.opcode_length)
331d2d0d 7042 {
43234a1e
L		 7043 case 4:
7044 p = frag_more (4);
7045 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7046 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7047 break;
4dffcebc 7048 case 3:
331d2d0d
L		 7049 p = frag_more (3);
7050 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7051 break;
7052 case 2:
7053 p = frag_more (2);
7054 break;
7055 default:
7056 abort ();
7057 break;
331d2d0d 7058 }
0f10071e 7059
29b0f896
AM		 7060 /* Put out high byte first: can't use md_number_to_chars! */
7061 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7062 *p = i.tm.base_opcode & 0xff;
7063 }
3e73aa7c 7064
29b0f896 7065 /* Now the modrm byte and sib byte (if present). */
40fb9820 7066 if (i.tm.opcode_modifier.modrm)
29b0f896 7067 {
4a3523fa
L		 7068 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7069 | i.rm.reg << 3
7070 | i.rm.mode << 6));
29b0f896
AM		 7071 /* If i.rm.regmem == ESP (4)
7072 && i.rm.mode != (Register mode)
7073 && not 16 bit
7074 ==> need second modrm byte. */
7075 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7076 && i.rm.mode != 3
40fb9820 7077 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7078 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7079 | i.sib.index << 3
7080 | i.sib.scale << 6));
29b0f896 7081 }
3e73aa7c 7082
29b0f896 7083 if (i.disp_operands)
2bbd9c25 7084 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7085
29b0f896 7086 if (i.imm_operands)
2bbd9c25 7087 output_imm (insn_start_frag, insn_start_off);
29b0f896 7088 }
252b5132 7089
29b0f896
AM		 7090#ifdef DEBUG386
7091 if (flag_debug)
7092 {
7b81dfbb 7093 pi ("" /*line*/, &i);
29b0f896
AM		 7094 }
7095#endif /* DEBUG386 */
7096}
252b5132 7097
e205caa7
L		 7098/* Return the size of the displacement operand N. */
7099
7100static int
7101disp_size (unsigned int n)
7102{
7103 int size = 4;
43234a1e
L		 7104
7105 /* Vec_Disp8 has to be 8bit. */
7106 if (i.types[n].bitfield.vec_disp8)
7107 size = 1;
7108 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7109 size = 8;
7110 else if (i.types[n].bitfield.disp8)
7111 size = 1;
7112 else if (i.types[n].bitfield.disp16)
7113 size = 2;
e205caa7
L		 7114 return size;
7115}
7116
7117/* Return the size of the immediate operand N. */
7118
7119static int
7120imm_size (unsigned int n)
7121{
7122 int size = 4;
40fb9820
L		 7123 if (i.types[n].bitfield.imm64)
7124 size = 8;
7125 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7126 size = 1;
7127 else if (i.types[n].bitfield.imm16)
7128 size = 2;
e205caa7
L		 7129 return size;
7130}
7131
29b0f896 7132static void
64e74474 7133output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7134{
7135 char *p;
7136 unsigned int n;
252b5132 7137
29b0f896
AM		 7138 for (n = 0; n < i.operands; n++)
7139 {
43234a1e
L		 7140 if (i.types[n].bitfield.vec_disp8
7141 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7142 {
7143 if (i.op[n].disps->X_op == O_constant)
7144 {
e205caa7 7145 int size = disp_size (n);
43234a1e 7146 offsetT val = i.op[n].disps->X_add_number;
252b5132 7147
43234a1e
L		 7148 if (i.types[n].bitfield.vec_disp8)
7149 val >>= i.memshift;
7150 val = offset_in_range (val, size);
29b0f896
AM		 7151 p = frag_more (size);
7152 md_number_to_chars (p, val, size);
7153 }
7154 else
7155 {
f86103b7 7156 enum bfd_reloc_code_real reloc_type;
e205caa7 7157 int size = disp_size (n);
40fb9820 7158 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7159 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7160
e205caa7 7161 /* We can't have 8 bit displacement here. */
9c2799c2 7162 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7163
29b0f896
AM		 7164 /* The PC relative address is computed relative
7165 to the instruction boundary, so in case immediate
7166 fields follows, we need to adjust the value. */
7167 if (pcrel && i.imm_operands)
7168 {
29b0f896 7169 unsigned int n1;
e205caa7 7170 int sz = 0;
252b5132 7171
29b0f896 7172 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7173 if (operand_type_check (i.types[n1], imm))
252b5132 7174 {
e205caa7
L		 7175 /* Only one immediate is allowed for PC
7176 relative address. */
9c2799c2 7177 gas_assert (sz == 0);
e205caa7
L		 7178 sz = imm_size (n1);
7179 i.op[n].disps->X_add_number -= sz;
252b5132 7180 }
29b0f896 7181 /* We should find the immediate. */
9c2799c2 7182 gas_assert (sz != 0);
29b0f896 7183 }
520dc8e8 7184
29b0f896 7185 p = frag_more (size);
d258b828 7186 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7187 if (GOT_symbol
2bbd9c25 7188 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7189 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7190 || reloc_type == BFD_RELOC_X86_64_32S
7191 || (reloc_type == BFD_RELOC_64
7192 && object_64bit))
d6ab8113
JB		 7193 && (i.op[n].disps->X_op == O_symbol
7194 || (i.op[n].disps->X_op == O_add
7195 && ((symbol_get_value_expression
7196 (i.op[n].disps->X_op_symbol)->X_op)
7197 == O_subtract))))
7198 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7199 {
7200 offsetT add;
7201
7202 if (insn_start_frag == frag_now)
7203 add = (p - frag_now->fr_literal) - insn_start_off;
7204 else
7205 {
7206 fragS *fr;
7207
7208 add = insn_start_frag->fr_fix - insn_start_off;
7209 for (fr = insn_start_frag->fr_next;
7210 fr && fr != frag_now; fr = fr->fr_next)
7211 add += fr->fr_fix;
7212 add += p - frag_now->fr_literal;
7213 }
7214
4fa24527 7215 if (!object_64bit)
7b81dfbb
AJ		 7216 {
7217 reloc_type = BFD_RELOC_386_GOTPC;
7218 i.op[n].imms->X_add_number += add;
7219 }
7220 else if (reloc_type == BFD_RELOC_64)
7221 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7222 else
7b81dfbb
AJ		 7223 /* Don't do the adjustment for x86-64, as there
7224 the pcrel addressing is relative to the _next_
7225 insn, and that is taken care of in other code. */
d6ab8113 7226 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7227 }
062cd5e7 7228 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7229 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7230 }
7231 }
7232 }
7233}
252b5132 7234
29b0f896 7235static void
64e74474 7236output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7237{
7238 char *p;
7239 unsigned int n;
252b5132 7240
29b0f896
AM		 7241 for (n = 0; n < i.operands; n++)
7242 {
43234a1e
L		 7243 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7244 if (i.rounding && (int) n == i.rounding->operand)
7245 continue;
7246
40fb9820 7247 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7248 {
7249 if (i.op[n].imms->X_op == O_constant)
7250 {
e205caa7 7251 int size = imm_size (n);
29b0f896 7252 offsetT val;
b4cac588 7253
29b0f896
AM		 7254 val = offset_in_range (i.op[n].imms->X_add_number,
7255 size);
7256 p = frag_more (size);
7257 md_number_to_chars (p, val, size);
7258 }
7259 else
7260 {
7261 /* Not absolute_section.
7262 Need a 32-bit fixup (don't support 8bit
7263 non-absolute imms). Try to support other
7264 sizes ... */
f86103b7 7265 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7266 int size = imm_size (n);
7267 int sign;
29b0f896 7268
40fb9820 7269 if (i.types[n].bitfield.imm32s
a7d61044 7270 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7271 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7272 sign = 1;
e205caa7
L		 7273 else
7274 sign = 0;
520dc8e8 7275
29b0f896 7276 p = frag_more (size);
d258b828 7277 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7278
2bbd9c25
JJ		 7279 /* This is tough to explain. We end up with this one if we
7280 * have operands that look like
7281 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7282 * obtain the absolute address of the GOT, and it is strongly
7283 * preferable from a performance point of view to avoid using
7284 * a runtime relocation for this. The actual sequence of
7285 * instructions often look something like:
7286 *
7287 * call .L66
7288 * .L66:
7289 * popl %ebx
7290 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7291 *
7292 * The call and pop essentially return the absolute address
7293 * of the label .L66 and store it in %ebx. The linker itself
7294 * will ultimately change the first operand of the addl so
7295 * that %ebx points to the GOT, but to keep things simple, the
7296 * .o file must have this operand set so that it generates not
7297 * the absolute address of .L66, but the absolute address of
7298 * itself. This allows the linker itself simply treat a GOTPC
7299 * relocation as asking for a pcrel offset to the GOT to be
7300 * added in, and the addend of the relocation is stored in the
7301 * operand field for the instruction itself.
7302 *
7303 * Our job here is to fix the operand so that it would add
7304 * the correct offset so that %ebx would point to itself. The
7305 * thing that is tricky is that .-.L66 will point to the
7306 * beginning of the instruction, so we need to further modify
7307 * the operand so that it will point to itself. There are
7308 * other cases where you have something like:
7309 *
7310 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7311 *
7312 * and here no correction would be required. Internally in
7313 * the assembler we treat operands of this form as not being
7314 * pcrel since the '.' is explicitly mentioned, and I wonder
7315 * whether it would simplify matters to do it this way. Who
7316 * knows. In earlier versions of the PIC patches, the
7317 * pcrel_adjust field was used to store the correction, but
7318 * since the expression is not pcrel, I felt it would be
7319 * confusing to do it this way. */
7320
d6ab8113 7321 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7322 || reloc_type == BFD_RELOC_X86_64_32S
7323 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7324 && GOT_symbol
7325 && GOT_symbol == i.op[n].imms->X_add_symbol
7326 && (i.op[n].imms->X_op == O_symbol
7327 || (i.op[n].imms->X_op == O_add
7328 && ((symbol_get_value_expression
7329 (i.op[n].imms->X_op_symbol)->X_op)
7330 == O_subtract))))
7331 {
2bbd9c25
JJ		 7332 offsetT add;
7333
7334 if (insn_start_frag == frag_now)
7335 add = (p - frag_now->fr_literal) - insn_start_off;
7336 else
7337 {
7338 fragS *fr;
7339
7340 add = insn_start_frag->fr_fix - insn_start_off;
7341 for (fr = insn_start_frag->fr_next;
7342 fr && fr != frag_now; fr = fr->fr_next)
7343 add += fr->fr_fix;
7344 add += p - frag_now->fr_literal;
7345 }
7346
4fa24527 7347 if (!object_64bit)
d6ab8113 7348 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7349 else if (size == 4)
d6ab8113 7350 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7351 else if (size == 8)
7352 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7353 i.op[n].imms->X_add_number += add;
29b0f896 7354 }
29b0f896
AM		 7355 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7356 i.op[n].imms, 0, reloc_type);
7357 }
7358 }
7359 }
252b5132
RH		 7360}
7361\f
d182319b
JB		 7362/* x86_cons_fix_new is called via the expression parsing code when a
7363 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7364static int cons_sign = -1;
7365
7366void
e3bb37b5 7367x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7368 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7369{
d258b828 7370 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7371
7372#ifdef TE_PE
7373 if (exp->X_op == O_secrel)
7374 {
7375 exp->X_op = O_symbol;
7376 r = BFD_RELOC_32_SECREL;
7377 }
7378#endif
7379
7380 fix_new_exp (frag, off, len, exp, 0, r);
7381}
7382
357d1bd8
L		 7383/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7384 purpose of the `.dc.a' internal pseudo-op. */
7385
7386int
7387x86_address_bytes (void)
7388{
7389 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7390 return 4;
7391 return stdoutput->arch_info->bits_per_address / 8;
7392}
7393
d382c579
TG		 7394#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7395 || defined (LEX_AT)
d258b828 7396# define lex_got(reloc, adjust, types) NULL
718ddfc0 7397#else
f3c180ae
AM		 7398/* Parse operands of the form
7399 <symbol>@GOTOFF+<nnn>
7400 and similar .plt or .got references.
7401
7402 If we find one, set up the correct relocation in RELOC and copy the
7403 input string, minus the `@GOTOFF' into a malloc'd buffer for
7404 parsing by the calling routine. Return this buffer, and if ADJUST
7405 is non-null set it to the length of the string we removed from the
7406 input line. Otherwise return NULL. */
7407static char *
91d6fa6a 7408lex_got (enum bfd_reloc_code_real *rel,
64e74474 7409 int *adjust,
d258b828 7410 i386_operand_type *types)
f3c180ae 7411{
7b81dfbb
AJ		 7412 /* Some of the relocations depend on the size of what field is to
7413 be relocated. But in our callers i386_immediate and i386_displacement
7414 we don't yet know the operand size (this will be set by insn
7415 matching). Hence we record the word32 relocation here,
7416 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7417 static const struct {
7418 const char *str;
cff8d58a 7419 int len;
4fa24527 7420 const enum bfd_reloc_code_real rel[2];
40fb9820 7421 const i386_operand_type types64;
f3c180ae 7422 } gotrel[] = {
8ce3d284 7423#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7424 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7425 BFD_RELOC_SIZE32 },
7426 OPERAND_TYPE_IMM32_64 },
8ce3d284 7427#endif
cff8d58a
L		 7428 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7429 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7430 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7431 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7432 BFD_RELOC_X86_64_PLT32 },
40fb9820 7433 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7434 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7435 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7436 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7437 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7438 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7439 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7440 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7441 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7442 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7443 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7444 BFD_RELOC_X86_64_TLSGD },
40fb9820 7445 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7446 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7447 _dummy_first_bfd_reloc_code_real },
40fb9820 7448 OPERAND_TYPE_NONE },
cff8d58a
L		 7449 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7450 BFD_RELOC_X86_64_TLSLD },
40fb9820 7451 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7452 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7453 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7454 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7455 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7456 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7457 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7458 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7459 _dummy_first_bfd_reloc_code_real },
40fb9820 7460 OPERAND_TYPE_NONE },
cff8d58a
L		 7461 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7462 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7463 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7464 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7465 _dummy_first_bfd_reloc_code_real },
40fb9820 7466 OPERAND_TYPE_NONE },
cff8d58a
L		 7467 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7468 _dummy_first_bfd_reloc_code_real },
40fb9820 7469 OPERAND_TYPE_NONE },
cff8d58a
L		 7470 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7471 BFD_RELOC_X86_64_GOT32 },
40fb9820 7472 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7473 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7474 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7475 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7476 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7477 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7478 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7479 };
7480 char *cp;
7481 unsigned int j;
7482
d382c579 7483#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7484 if (!IS_ELF)
7485 return NULL;
d382c579 7486#endif
718ddfc0 7487
f3c180ae 7488 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7489 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7490 return NULL;
7491
47465058 7492 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7493 {
cff8d58a 7494 int len = gotrel[j].len;
28f81592 7495 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7496 {
4fa24527 7497 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7498 {
28f81592
AM		 7499 int first, second;
7500 char *tmpbuf, *past_reloc;
f3c180ae 7501
91d6fa6a 7502 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7503
3956db08
JB		 7504 if (types)
7505 {
7506 if (flag_code != CODE_64BIT)
40fb9820
L		 7507 {
7508 types->bitfield.imm32 = 1;
7509 types->bitfield.disp32 = 1;
7510 }
3956db08
JB		 7511 else
7512 *types = gotrel[j].types64;
7513 }
7514
8fd4256d 7515 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7516 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7517
28f81592 7518 /* The length of the first part of our input line. */
f3c180ae 7519 first = cp - input_line_pointer;
28f81592
AM		 7520
7521 /* The second part goes from after the reloc token until
67c11a9b 7522 (and including) an end_of_line char or comma. */
28f81592 7523 past_reloc = cp + 1 + len;
67c11a9b
AM		 7524 cp = past_reloc;
7525 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7526 ++cp;
7527 second = cp + 1 - past_reloc;
28f81592
AM		 7528
7529 /* Allocate and copy string. The trailing NUL shouldn't
7530 be necessary, but be safe. */
1e9cc1c2 7531 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7532 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7533 if (second != 0 && *past_reloc != ' ')
7534 /* Replace the relocation token with ' ', so that
7535 errors like foo@GOTOFF1 will be detected. */
7536 tmpbuf[first++] = ' ';
af89796a
L		 7537 else
7538 /* Increment length by 1 if the relocation token is
7539 removed. */
7540 len++;
7541 if (adjust)
7542 *adjust = len;
0787a12d
AM		 7543 memcpy (tmpbuf + first, past_reloc, second);
7544 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7545 return tmpbuf;
7546 }
7547
4fa24527
JB		 7548 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7549 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7550 return NULL;
7551 }
7552 }
7553
7554 /* Might be a symbol version string. Don't as_bad here. */
7555 return NULL;
7556}
4e4f7c87 7557#endif
f3c180ae 7558
a988325c
NC		 7559#ifdef TE_PE
7560#ifdef lex_got
7561#undef lex_got
7562#endif
7563/* Parse operands of the form
7564 <symbol>@SECREL32+<nnn>
7565
7566 If we find one, set up the correct relocation in RELOC and copy the
7567 input string, minus the `@SECREL32' into a malloc'd buffer for
7568 parsing by the calling routine. Return this buffer, and if ADJUST
7569 is non-null set it to the length of the string we removed from the
34bca508
L		 7570 input line. Otherwise return NULL.
7571
a988325c
NC		 7572 This function is copied from the ELF version above adjusted for PE targets. */
7573
7574static char *
7575lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7576 int *adjust ATTRIBUTE_UNUSED,
d258b828 7577 i386_operand_type *types)
a988325c
NC		 7578{
7579 static const struct
7580 {
7581 const char *str;
7582 int len;
7583 const enum bfd_reloc_code_real rel[2];
7584 const i386_operand_type types64;
7585 }
7586 gotrel[] =
7587 {
7588 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7589 BFD_RELOC_32_SECREL },
7590 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7591 };
7592
7593 char *cp;
7594 unsigned j;
7595
7596 for (cp = input_line_pointer; *cp != '@'; cp++)
7597 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7598 return NULL;
7599
7600 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7601 {
7602 int len = gotrel[j].len;
7603
7604 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7605 {
7606 if (gotrel[j].rel[object_64bit] != 0)
7607 {
7608 int first, second;
7609 char *tmpbuf, *past_reloc;
7610
7611 *rel = gotrel[j].rel[object_64bit];
7612 if (adjust)
7613 *adjust = len;
7614
7615 if (types)
7616 {
7617 if (flag_code != CODE_64BIT)
7618 {
7619 types->bitfield.imm32 = 1;
7620 types->bitfield.disp32 = 1;
7621 }
7622 else
7623 *types = gotrel[j].types64;
7624 }
7625
7626 /* The length of the first part of our input line. */
7627 first = cp - input_line_pointer;
7628
7629 /* The second part goes from after the reloc token until
7630 (and including) an end_of_line char or comma. */
7631 past_reloc = cp + 1 + len;
7632 cp = past_reloc;
7633 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7634 ++cp;
7635 second = cp + 1 - past_reloc;
7636
7637 /* Allocate and copy string. The trailing NUL shouldn't
7638 be necessary, but be safe. */
7639 tmpbuf = (char *) xmalloc (first + second + 2);
7640 memcpy (tmpbuf, input_line_pointer, first);
7641 if (second != 0 && *past_reloc != ' ')
7642 /* Replace the relocation token with ' ', so that
7643 errors like foo@SECLREL321 will be detected. */
7644 tmpbuf[first++] = ' ';
7645 memcpy (tmpbuf + first, past_reloc, second);
7646 tmpbuf[first + second] = '\0';
7647 return tmpbuf;
7648 }
7649
7650 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7651 gotrel[j].str, 1 << (5 + object_64bit));
7652 return NULL;
7653 }
7654 }
7655
7656 /* Might be a symbol version string. Don't as_bad here. */
7657 return NULL;
7658}
7659
7660#endif /* TE_PE */
7661
62ebcb5c 7662bfd_reloc_code_real_type
e3bb37b5 7663x86_cons (expressionS *exp, int size)
f3c180ae 7664{
62ebcb5c
AM		 7665 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7666
ee86248c
JB		 7667 intel_syntax = -intel_syntax;
7668
3c7b9c2c 7669 exp->X_md = 0;
4fa24527 7670 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7671 {
7672 /* Handle @GOTOFF and the like in an expression. */
7673 char *save;
7674 char *gotfree_input_line;
4a57f2cf 7675 int adjust = 0;
f3c180ae
AM		 7676
7677 save = input_line_pointer;
d258b828 7678 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7679 if (gotfree_input_line)
7680 input_line_pointer = gotfree_input_line;
7681
7682 expression (exp);
7683
7684 if (gotfree_input_line)
7685 {
7686 /* expression () has merrily parsed up to the end of line,
7687 or a comma - in the wrong buffer. Transfer how far
7688 input_line_pointer has moved to the right buffer. */
7689 input_line_pointer = (save
7690 + (input_line_pointer - gotfree_input_line)
7691 + adjust);
7692 free (gotfree_input_line);
3992d3b7
AM		 7693 if (exp->X_op == O_constant
7694 || exp->X_op == O_absent
7695 || exp->X_op == O_illegal
0398aac5 7696 || exp->X_op == O_register
3992d3b7
AM		 7697 || exp->X_op == O_big)
7698 {
7699 char c = *input_line_pointer;
7700 *input_line_pointer = 0;
7701 as_bad (_("missing or invalid expression `%s'"), save);
7702 *input_line_pointer = c;
7703 }
f3c180ae
AM		 7704 }
7705 }
7706 else
7707 expression (exp);
ee86248c
JB		 7708
7709 intel_syntax = -intel_syntax;
7710
7711 if (intel_syntax)
7712 i386_intel_simplify (exp);
62ebcb5c
AM		 7713
7714 return got_reloc;
f3c180ae 7715}
f3c180ae 7716
9f32dd5b
L		 7717static void
7718signed_cons (int size)
6482c264 7719{
d182319b
JB		 7720 if (flag_code == CODE_64BIT)
7721 cons_sign = 1;
7722 cons (size);
7723 cons_sign = -1;
6482c264
NC		 7724}
7725
d182319b 7726#ifdef TE_PE
6482c264 7727static void
7016a5d5 7728pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7729{
7730 expressionS exp;
7731
7732 do
7733 {
7734 expression (&exp);
7735 if (exp.X_op == O_symbol)
7736 exp.X_op = O_secrel;
7737
7738 emit_expr (&exp, 4);
7739 }
7740 while (*input_line_pointer++ == ',');
7741
7742 input_line_pointer--;
7743 demand_empty_rest_of_line ();
7744}
6482c264
NC		 7745#endif
7746
43234a1e
L		 7747/* Handle Vector operations. */
7748
7749static char *
7750check_VecOperations (char *op_string, char *op_end)
7751{
7752 const reg_entry *mask;
7753 const char *saved;
7754 char *end_op;
7755
7756 while (*op_string
7757 && (op_end == NULL || op_string < op_end))
7758 {
7759 saved = op_string;
7760 if (*op_string == '{')
7761 {
7762 op_string++;
7763
7764 /* Check broadcasts. */
7765 if (strncmp (op_string, "1to", 3) == 0)
7766 {
7767 int bcst_type;
7768
7769 if (i.broadcast)
7770 goto duplicated_vec_op;
7771
7772 op_string += 3;
7773 if (*op_string == '8')
7774 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7775 else if (*op_string == '4')
7776 bcst_type = BROADCAST_1TO4;
7777 else if (*op_string == '2')
7778 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7779 else if (*op_string == '1'
7780 && *(op_string+1) == '6')
7781 {
7782 bcst_type = BROADCAST_1TO16;
7783 op_string++;
7784 }
7785 else
7786 {
7787 as_bad (_("Unsupported broadcast: `%s'"), saved);
7788 return NULL;
7789 }
7790 op_string++;
7791
7792 broadcast_op.type = bcst_type;
7793 broadcast_op.operand = this_operand;
7794 i.broadcast = &broadcast_op;
7795 }
7796 /* Check masking operation. */
7797 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7798 {
7799 /* k0 can't be used for write mask. */
7800 if (mask->reg_num == 0)
7801 {
7802 as_bad (_("`%s' can't be used for write mask"),
7803 op_string);
7804 return NULL;
7805 }
7806
7807 if (!i.mask)
7808 {
7809 mask_op.mask = mask;
7810 mask_op.zeroing = 0;
7811 mask_op.operand = this_operand;
7812 i.mask = &mask_op;
7813 }
7814 else
7815 {
7816 if (i.mask->mask)
7817 goto duplicated_vec_op;
7818
7819 i.mask->mask = mask;
7820
7821 /* Only "{z}" is allowed here. No need to check
7822 zeroing mask explicitly. */
7823 if (i.mask->operand != this_operand)
7824 {
7825 as_bad (_("invalid write mask `%s'"), saved);
7826 return NULL;
7827 }
7828 }
7829
7830 op_string = end_op;
7831 }
7832 /* Check zeroing-flag for masking operation. */
7833 else if (*op_string == 'z')
7834 {
7835 if (!i.mask)
7836 {
7837 mask_op.mask = NULL;
7838 mask_op.zeroing = 1;
7839 mask_op.operand = this_operand;
7840 i.mask = &mask_op;
7841 }
7842 else
7843 {
7844 if (i.mask->zeroing)
7845 {
7846 duplicated_vec_op:
7847 as_bad (_("duplicated `%s'"), saved);
7848 return NULL;
7849 }
7850
7851 i.mask->zeroing = 1;
7852
7853 /* Only "{%k}" is allowed here. No need to check mask
7854 register explicitly. */
7855 if (i.mask->operand != this_operand)
7856 {
7857 as_bad (_("invalid zeroing-masking `%s'"),
7858 saved);
7859 return NULL;
7860 }
7861 }
7862
7863 op_string++;
7864 }
7865 else
7866 goto unknown_vec_op;
7867
7868 if (*op_string != '}')
7869 {
7870 as_bad (_("missing `}' in `%s'"), saved);
7871 return NULL;
7872 }
7873 op_string++;
7874 continue;
7875 }
7876 unknown_vec_op:
7877 /* We don't know this one. */
7878 as_bad (_("unknown vector operation: `%s'"), saved);
7879 return NULL;
7880 }
7881
7882 return op_string;
7883}
7884
252b5132 7885static int
70e41ade 7886i386_immediate (char *imm_start)
252b5132
RH		 7887{
7888 char *save_input_line_pointer;
f3c180ae 7889 char *gotfree_input_line;
252b5132 7890 segT exp_seg = 0;
47926f60 7891 expressionS *exp;
40fb9820
L		 7892 i386_operand_type types;
7893
0dfbf9d7 7894 operand_type_set (&types, ~0);
252b5132
RH		 7895
7896 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7897 {
31b2323c
L		 7898 as_bad (_("at most %d immediate operands are allowed"),
7899 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7900 return 0;
7901 }
7902
7903 exp = &im_expressions[i.imm_operands++];
520dc8e8 7904 i.op[this_operand].imms = exp;
252b5132
RH		 7905
7906 if (is_space_char (*imm_start))
7907 ++imm_start;
7908
7909 save_input_line_pointer = input_line_pointer;
7910 input_line_pointer = imm_start;
7911
d258b828 7912 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7913 if (gotfree_input_line)
7914 input_line_pointer = gotfree_input_line;
252b5132
RH		 7915
7916 exp_seg = expression (exp);
7917
83183c0c 7918 SKIP_WHITESPACE ();
43234a1e
L		 7919
7920 /* Handle vector operations. */
7921 if (*input_line_pointer == '{')
7922 {
7923 input_line_pointer = check_VecOperations (input_line_pointer,
7924 NULL);
7925 if (input_line_pointer == NULL)
7926 return 0;
7927 }
7928
252b5132 7929 if (*input_line_pointer)
f3c180ae 7930 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7931
7932 input_line_pointer = save_input_line_pointer;
f3c180ae 7933 if (gotfree_input_line)
ee86248c
JB		 7934 {
7935 free (gotfree_input_line);
7936
7937 if (exp->X_op == O_constant || exp->X_op == O_register)
7938 exp->X_op = O_illegal;
7939 }
7940
7941 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7942}
252b5132 7943
ee86248c
JB		 7944static int
7945i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7946 i386_operand_type types, const char *imm_start)
7947{
7948 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7949 {
313c53d1
L		 7950 if (imm_start)
7951 as_bad (_("missing or invalid immediate expression `%s'"),
7952 imm_start);
3992d3b7 7953 return 0;
252b5132 7954 }
3e73aa7c 7955 else if (exp->X_op == O_constant)
252b5132 7956 {
47926f60 7957 /* Size it properly later. */
40fb9820 7958 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7959 /* If not 64bit, sign extend val. */
7960 if (flag_code != CODE_64BIT
4eed87de
AM		 7961 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7962 exp->X_add_number
7963 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7964 }
4c63da97 7965#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7966 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7967 && exp_seg != absolute_section
47926f60 7968 && exp_seg != text_section
24eab124
AM		 7969 && exp_seg != data_section
7970 && exp_seg != bss_section
7971 && exp_seg != undefined_section
f86103b7 7972 && !bfd_is_com_section (exp_seg))
252b5132 7973 {
d0b47220 7974 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7975 return 0;
7976 }
7977#endif
a841bdf5 7978 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7979 {
313c53d1
L		 7980 if (imm_start)
7981 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7982 return 0;
7983 }
252b5132
RH		 7984 else
7985 {
7986 /* This is an address. The size of the address will be
24eab124 7987 determined later, depending on destination register,
3e73aa7c 7988 suffix, or the default for the section. */
40fb9820
L		 7989 i.types[this_operand].bitfield.imm8 = 1;
7990 i.types[this_operand].bitfield.imm16 = 1;
7991 i.types[this_operand].bitfield.imm32 = 1;
7992 i.types[this_operand].bitfield.imm32s = 1;
7993 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7994 i.types[this_operand] = operand_type_and (i.types[this_operand],
7995 types);
252b5132
RH		 7996 }
7997
7998 return 1;
7999}
8000
551c1ca1 8001static char *
e3bb37b5 8002i386_scale (char *scale)
252b5132 8003{
551c1ca1
AM		 8004 offsetT val;
8005 char *save = input_line_pointer;
252b5132 8006
551c1ca1
AM		 8007 input_line_pointer = scale;
8008 val = get_absolute_expression ();
8009
8010 switch (val)
252b5132 8011 {
551c1ca1 8012 case 1:
252b5132
RH		 8013 i.log2_scale_factor = 0;
8014 break;
551c1ca1 8015 case 2:
252b5132
RH		 8016 i.log2_scale_factor = 1;
8017 break;
551c1ca1 8018 case 4:
252b5132
RH		 8019 i.log2_scale_factor = 2;
8020 break;
551c1ca1 8021 case 8:
252b5132
RH		 8022 i.log2_scale_factor = 3;
8023 break;
8024 default:
a724f0f4
JB		 8025 {
8026 char sep = *input_line_pointer;
8027
8028 *input_line_pointer = '\0';
8029 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8030 scale);
8031 *input_line_pointer = sep;
8032 input_line_pointer = save;
8033 return NULL;
8034 }
252b5132 8035 }
29b0f896 8036 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8037 {
8038 as_warn (_("scale factor of %d without an index register"),
24eab124 8039 1 << i.log2_scale_factor);
252b5132 8040 i.log2_scale_factor = 0;
252b5132 8041 }
551c1ca1
AM		 8042 scale = input_line_pointer;
8043 input_line_pointer = save;
8044 return scale;
252b5132
RH		 8045}
8046
252b5132 8047static int
e3bb37b5 8048i386_displacement (char *disp_start, char *disp_end)
252b5132 8049{
29b0f896 8050 expressionS *exp;
252b5132
RH		 8051 segT exp_seg = 0;
8052 char *save_input_line_pointer;
f3c180ae 8053 char *gotfree_input_line;
40fb9820
L		 8054 int override;
8055 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8056 int ret;
252b5132 8057
31b2323c
L		 8058 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8059 {
8060 as_bad (_("at most %d displacement operands are allowed"),
8061 MAX_MEMORY_OPERANDS);
8062 return 0;
8063 }
8064
0dfbf9d7 8065 operand_type_set (&bigdisp, 0);
40fb9820
L		 8066 if ((i.types[this_operand].bitfield.jumpabsolute)
8067 || (!current_templates->start->opcode_modifier.jump
8068 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8069 {
40fb9820 8070 bigdisp.bitfield.disp32 = 1;
e05278af 8071 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8072 if (flag_code == CODE_64BIT)
8073 {
8074 if (!override)
8075 {
8076 bigdisp.bitfield.disp32s = 1;
8077 bigdisp.bitfield.disp64 = 1;
8078 }
8079 }
8080 else if ((flag_code == CODE_16BIT) ^ override)
8081 {
8082 bigdisp.bitfield.disp32 = 0;
8083 bigdisp.bitfield.disp16 = 1;
8084 }
e05278af
JB		 8085 }
8086 else
8087 {
8088 /* For PC-relative branches, the width of the displacement
8089 is dependent upon data size, not address size. */
e05278af 8090 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8091 if (flag_code == CODE_64BIT)
8092 {
8093 if (override || i.suffix == WORD_MNEM_SUFFIX)
8094 bigdisp.bitfield.disp16 = 1;
8095 else
8096 {
8097 bigdisp.bitfield.disp32 = 1;
8098 bigdisp.bitfield.disp32s = 1;
8099 }
8100 }
8101 else
e05278af
JB		 8102 {
8103 if (!override)
8104 override = (i.suffix == (flag_code != CODE_16BIT
8105 ? WORD_MNEM_SUFFIX
8106 : LONG_MNEM_SUFFIX));
40fb9820
L		 8107 bigdisp.bitfield.disp32 = 1;
8108 if ((flag_code == CODE_16BIT) ^ override)
8109 {
8110 bigdisp.bitfield.disp32 = 0;
8111 bigdisp.bitfield.disp16 = 1;
8112 }
e05278af 8113 }
e05278af 8114 }
c6fb90c8
L		 8115 i.types[this_operand] = operand_type_or (i.types[this_operand],
8116 bigdisp);
252b5132
RH		 8117
8118 exp = &disp_expressions[i.disp_operands];
520dc8e8 8119 i.op[this_operand].disps = exp;
252b5132
RH		 8120 i.disp_operands++;
8121 save_input_line_pointer = input_line_pointer;
8122 input_line_pointer = disp_start;
8123 END_STRING_AND_SAVE (disp_end);
8124
8125#ifndef GCC_ASM_O_HACK
8126#define GCC_ASM_O_HACK 0
8127#endif
8128#if GCC_ASM_O_HACK
8129 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8130 if (i.types[this_operand].bitfield.baseIndex
24eab124 8131 && displacement_string_end[-1] == '+')
252b5132
RH		 8132 {
8133 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8134 constraint within gcc asm statements.
8135 For instance:
8136
8137 #define _set_tssldt_desc(n,addr,limit,type) \
8138 __asm__ __volatile__ ( \
8139 "movw %w2,%0\n\t" \
8140 "movw %w1,2+%0\n\t" \
8141 "rorl $16,%1\n\t" \
8142 "movb %b1,4+%0\n\t" \
8143 "movb %4,5+%0\n\t" \
8144 "movb $0,6+%0\n\t" \
8145 "movb %h1,7+%0\n\t" \
8146 "rorl $16,%1" \
8147 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8148
8149 This works great except that the output assembler ends
8150 up looking a bit weird if it turns out that there is
8151 no offset. You end up producing code that looks like:
8152
8153 #APP
8154 movw $235,(%eax)
8155 movw %dx,2+(%eax)
8156 rorl $16,%edx
8157 movb %dl,4+(%eax)
8158 movb $137,5+(%eax)
8159 movb $0,6+(%eax)
8160 movb %dh,7+(%eax)
8161 rorl $16,%edx
8162 #NO_APP
8163
47926f60 8164 So here we provide the missing zero. */
24eab124
AM		 8165
8166 *displacement_string_end = '0';
252b5132
RH		 8167 }
8168#endif
d258b828 8169 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8170 if (gotfree_input_line)
8171 input_line_pointer = gotfree_input_line;
252b5132 8172
24eab124 8173 exp_seg = expression (exp);
252b5132 8174
636c26b0
AM		 8175 SKIP_WHITESPACE ();
8176 if (*input_line_pointer)
8177 as_bad (_("junk `%s' after expression"), input_line_pointer);
8178#if GCC_ASM_O_HACK
8179 RESTORE_END_STRING (disp_end + 1);
8180#endif
636c26b0 8181 input_line_pointer = save_input_line_pointer;
636c26b0 8182 if (gotfree_input_line)
ee86248c
JB		 8183 {
8184 free (gotfree_input_line);
8185
8186 if (exp->X_op == O_constant || exp->X_op == O_register)
8187 exp->X_op = O_illegal;
8188 }
8189
8190 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8191
8192 RESTORE_END_STRING (disp_end);
8193
8194 return ret;
8195}
8196
8197static int
8198i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8199 i386_operand_type types, const char *disp_start)
8200{
8201 i386_operand_type bigdisp;
8202 int ret = 1;
636c26b0 8203
24eab124
AM		 8204 /* We do this to make sure that the section symbol is in
8205 the symbol table. We will ultimately change the relocation
47926f60 8206 to be relative to the beginning of the section. */
1ae12ab7 8207 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8208 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8209 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8210 {
636c26b0 8211 if (exp->X_op != O_symbol)
3992d3b7 8212 goto inv_disp;
636c26b0 8213
e5cb08ac 8214 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8215 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8216 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8217 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8218 exp->X_op = O_subtract;
8219 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8220 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8221 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8222 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8223 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8224 else
29b0f896 8225 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8226 }
252b5132 8227
3992d3b7
AM		 8228 else if (exp->X_op == O_absent
8229 || exp->X_op == O_illegal
ee86248c 8230 || exp->X_op == O_big)
2daf4fd8 8231 {
3992d3b7
AM		 8232 inv_disp:
8233 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8234 disp_start);
3992d3b7 8235 ret = 0;
2daf4fd8
AM		 8236 }
8237
0e1147d9
L		 8238 else if (flag_code == CODE_64BIT
8239 && !i.prefix[ADDR_PREFIX]
8240 && exp->X_op == O_constant)
8241 {
8242 /* Since displacement is signed extended to 64bit, don't allow
8243 disp32 and turn off disp32s if they are out of range. */
8244 i.types[this_operand].bitfield.disp32 = 0;
8245 if (!fits_in_signed_long (exp->X_add_number))
8246 {
8247 i.types[this_operand].bitfield.disp32s = 0;
8248 if (i.types[this_operand].bitfield.baseindex)
8249 {
8250 as_bad (_("0x%lx out range of signed 32bit displacement"),
8251 (long) exp->X_add_number);
8252 ret = 0;
8253 }
8254 }
8255 }
8256
4c63da97 8257#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8258 else if (exp->X_op != O_constant
8259 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8260 && exp_seg != absolute_section
8261 && exp_seg != text_section
8262 && exp_seg != data_section
8263 && exp_seg != bss_section
8264 && exp_seg != undefined_section
8265 && !bfd_is_com_section (exp_seg))
24eab124 8266 {
d0b47220 8267 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8268 ret = 0;
24eab124 8269 }
252b5132 8270#endif
3956db08 8271
40fb9820
L		 8272 /* Check if this is a displacement only operand. */
8273 bigdisp = i.types[this_operand];
8274 bigdisp.bitfield.disp8 = 0;
8275 bigdisp.bitfield.disp16 = 0;
8276 bigdisp.bitfield.disp32 = 0;
8277 bigdisp.bitfield.disp32s = 0;
8278 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8279 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8280 i.types[this_operand] = operand_type_and (i.types[this_operand],
8281 types);
3956db08 8282
3992d3b7 8283 return ret;
252b5132
RH		 8284}
8285
eecb386c 8286/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8287 Return 1 on success, 0 on a failure. */
8288
252b5132 8289static int
e3bb37b5 8290i386_index_check (const char *operand_string)
252b5132 8291{
fc0763e6 8292 const char *kind = "base/index";
be05d201
L		 8293 enum flag_code addr_mode;
8294
8295 if (i.prefix[ADDR_PREFIX])
8296 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8297 else
8298 {
8299 addr_mode = flag_code;
8300
24eab124 8301#if INFER_ADDR_PREFIX
be05d201
L		 8302 if (i.mem_operands == 0)
8303 {
8304 /* Infer address prefix from the first memory operand. */
8305 const reg_entry *addr_reg = i.base_reg;
8306
8307 if (addr_reg == NULL)
8308 addr_reg = i.index_reg;
eecb386c 8309
be05d201
L		 8310 if (addr_reg)
8311 {
8312 if (addr_reg->reg_num == RegEip
8313 || addr_reg->reg_num == RegEiz
8314 || addr_reg->reg_type.bitfield.reg32)
8315 addr_mode = CODE_32BIT;
8316 else if (flag_code != CODE_64BIT
8317 && addr_reg->reg_type.bitfield.reg16)
8318 addr_mode = CODE_16BIT;
8319
8320 if (addr_mode != flag_code)
8321 {
8322 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8323 i.prefixes += 1;
8324 /* Change the size of any displacement too. At most one
8325 of Disp16 or Disp32 is set.
8326 FIXME. There doesn't seem to be any real need for
8327 separate Disp16 and Disp32 flags. The same goes for
8328 Imm16 and Imm32. Removing them would probably clean
8329 up the code quite a lot. */
8330 if (flag_code != CODE_64BIT
8331 && (i.types[this_operand].bitfield.disp16
8332 || i.types[this_operand].bitfield.disp32))
8333 i.types[this_operand]
8334 = operand_type_xor (i.types[this_operand], disp16_32);
8335 }
8336 }
8337 }
24eab124 8338#endif
be05d201
L		 8339 }
8340
fc0763e6
JB		 8341 if (current_templates->start->opcode_modifier.isstring
8342 && !current_templates->start->opcode_modifier.immext
8343 && (current_templates->end[-1].opcode_modifier.isstring
8344 || i.mem_operands))
8345 {
8346 /* Memory operands of string insns are special in that they only allow
8347 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8348 const reg_entry *expected_reg;
8349 static const char *di_si[][2] =
8350 {
8351 { "esi", "edi" },
8352 { "si", "di" },
8353 { "rsi", "rdi" }
8354 };
8355 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8356
8357 kind = "string address";
8358
8359 if (current_templates->start->opcode_modifier.w)
8360 {
8361 i386_operand_type type = current_templates->end[-1].operand_types[0];
8362
8363 if (!type.bitfield.baseindex
8364 || ((!i.mem_operands != !intel_syntax)
8365 && current_templates->end[-1].operand_types[1]
8366 .bitfield.baseindex))
8367 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8368 expected_reg = hash_find (reg_hash,
8369 di_si[addr_mode][type.bitfield.esseg]);
8370
fc0763e6
JB		 8371 }
8372 else
be05d201 8373 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8374
be05d201
L		 8375 if (i.base_reg != expected_reg
8376 || i.index_reg
fc0763e6 8377 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8378 {
be05d201
L		 8379 /* The second memory operand must have the same size as
8380 the first one. */
8381 if (i.mem_operands
8382 && i.base_reg
8383 && !((addr_mode == CODE_64BIT
8384 && i.base_reg->reg_type.bitfield.reg64)
8385 || (addr_mode == CODE_32BIT
8386 ? i.base_reg->reg_type.bitfield.reg32
8387 : i.base_reg->reg_type.bitfield.reg16)))
8388 goto bad_address;
8389
fc0763e6
JB		 8390 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8391 operand_string,
8392 intel_syntax ? '[' : '(',
8393 register_prefix,
be05d201 8394 expected_reg->reg_name,
fc0763e6 8395 intel_syntax ? ']' : ')');
be05d201 8396 return 1;
fc0763e6 8397 }
be05d201
L		 8398 else
8399 return 1;
8400
8401bad_address:
8402 as_bad (_("`%s' is not a valid %s expression"),
8403 operand_string, kind);
8404 return 0;
3e73aa7c
JH		 8405 }
8406 else
8407 {
be05d201
L		 8408 if (addr_mode != CODE_16BIT)
8409 {
8410 /* 32-bit/64-bit checks. */
8411 if ((i.base_reg
8412 && (addr_mode == CODE_64BIT
8413 ? !i.base_reg->reg_type.bitfield.reg64
8414 : !i.base_reg->reg_type.bitfield.reg32)
8415 && (i.index_reg
8416 || (i.base_reg->reg_num
8417 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8418 || (i.index_reg
8419 && !i.index_reg->reg_type.bitfield.regxmm
8420 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8421 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8422 && ((addr_mode == CODE_64BIT
8423 ? !(i.index_reg->reg_type.bitfield.reg64
8424 || i.index_reg->reg_num == RegRiz)
8425 : !(i.index_reg->reg_type.bitfield.reg32
8426 || i.index_reg->reg_num == RegEiz))
8427 || !i.index_reg->reg_type.bitfield.baseindex)))
8428 goto bad_address;
8429 }
8430 else
3e73aa7c 8431 {
be05d201 8432 /* 16-bit checks. */
3e73aa7c 8433 if ((i.base_reg
40fb9820
L		 8434 && (!i.base_reg->reg_type.bitfield.reg16
8435 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8436 || (i.index_reg
40fb9820
L		 8437 && (!i.index_reg->reg_type.bitfield.reg16
8438 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8439 || !(i.base_reg
8440 && i.base_reg->reg_num < 6
8441 && i.index_reg->reg_num >= 6
8442 && i.log2_scale_factor == 0))))
be05d201 8443 goto bad_address;
3e73aa7c
JH		 8444 }
8445 }
be05d201 8446 return 1;
24eab124 8447}
252b5132 8448
43234a1e
L		 8449/* Handle vector immediates. */
8450
8451static int
8452RC_SAE_immediate (const char *imm_start)
8453{
8454 unsigned int match_found, j;
8455 const char *pstr = imm_start;
8456 expressionS *exp;
8457
8458 if (*pstr != '{')
8459 return 0;
8460
8461 pstr++;
8462 match_found = 0;
8463 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8464 {
8465 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8466 {
8467 if (!i.rounding)
8468 {
8469 rc_op.type = RC_NamesTable[j].type;
8470 rc_op.operand = this_operand;
8471 i.rounding = &rc_op;
8472 }
8473 else
8474 {
8475 as_bad (_("duplicated `%s'"), imm_start);
8476 return 0;
8477 }
8478 pstr += RC_NamesTable[j].len;
8479 match_found = 1;
8480 break;
8481 }
8482 }
8483 if (!match_found)
8484 return 0;
8485
8486 if (*pstr++ != '}')
8487 {
8488 as_bad (_("Missing '}': '%s'"), imm_start);
8489 return 0;
8490 }
8491 /* RC/SAE immediate string should contain nothing more. */;
8492 if (*pstr != 0)
8493 {
8494 as_bad (_("Junk after '}': '%s'"), imm_start);
8495 return 0;
8496 }
8497
8498 exp = &im_expressions[i.imm_operands++];
8499 i.op[this_operand].imms = exp;
8500
8501 exp->X_op = O_constant;
8502 exp->X_add_number = 0;
8503 exp->X_add_symbol = (symbolS *) 0;
8504 exp->X_op_symbol = (symbolS *) 0;
8505
8506 i.types[this_operand].bitfield.imm8 = 1;
8507 return 1;
8508}
8509
fc0763e6 8510/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8511 on error. */
252b5132 8512
252b5132 8513static int
a7619375 8514i386_att_operand (char *operand_string)
252b5132 8515{
af6bdddf
AM		 8516 const reg_entry *r;
8517 char *end_op;
24eab124 8518 char *op_string = operand_string;
252b5132 8519
24eab124 8520 if (is_space_char (*op_string))
252b5132
RH		 8521 ++op_string;
8522
24eab124 8523 /* We check for an absolute prefix (differentiating,
47926f60 8524 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8525 if (*op_string == ABSOLUTE_PREFIX)
8526 {
8527 ++op_string;
8528 if (is_space_char (*op_string))
8529 ++op_string;
40fb9820 8530 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8531 }
252b5132 8532
47926f60 8533 /* Check if operand is a register. */
4d1bb795 8534 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8535 {
40fb9820
L		 8536 i386_operand_type temp;
8537
24eab124
AM		 8538 /* Check for a segment override by searching for ':' after a
8539 segment register. */
8540 op_string = end_op;
8541 if (is_space_char (*op_string))
8542 ++op_string;
40fb9820
L		 8543 if (*op_string == ':'
8544 && (r->reg_type.bitfield.sreg2
8545 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8546 {
8547 switch (r->reg_num)
8548 {
8549 case 0:
8550 i.seg[i.mem_operands] = &es;
8551 break;
8552 case 1:
8553 i.seg[i.mem_operands] = &cs;
8554 break;
8555 case 2:
8556 i.seg[i.mem_operands] = &ss;
8557 break;
8558 case 3:
8559 i.seg[i.mem_operands] = &ds;
8560 break;
8561 case 4:
8562 i.seg[i.mem_operands] = &fs;
8563 break;
8564 case 5:
8565 i.seg[i.mem_operands] = &gs;
8566 break;
8567 }
252b5132 8568
24eab124 8569 /* Skip the ':' and whitespace. */
252b5132
RH		 8570 ++op_string;
8571 if (is_space_char (*op_string))
24eab124 8572 ++op_string;
252b5132 8573
24eab124
AM		 8574 if (!is_digit_char (*op_string)
8575 && !is_identifier_char (*op_string)
8576 && *op_string != '('
8577 && *op_string != ABSOLUTE_PREFIX)
8578 {
8579 as_bad (_("bad memory operand `%s'"), op_string);
8580 return 0;
8581 }
47926f60 8582 /* Handle case of %es:*foo. */
24eab124
AM		 8583 if (*op_string == ABSOLUTE_PREFIX)
8584 {
8585 ++op_string;
8586 if (is_space_char (*op_string))
8587 ++op_string;
40fb9820 8588 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8589 }
8590 goto do_memory_reference;
8591 }
43234a1e
L		 8592
8593 /* Handle vector operations. */
8594 if (*op_string == '{')
8595 {
8596 op_string = check_VecOperations (op_string, NULL);
8597 if (op_string == NULL)
8598 return 0;
8599 }
8600
24eab124
AM		 8601 if (*op_string)
8602 {
d0b47220 8603 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8604 return 0;
8605 }
40fb9820
L		 8606 temp = r->reg_type;
8607 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8608 i.types[this_operand] = operand_type_or (i.types[this_operand],
8609 temp);
7d5e4556 8610 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8611 i.op[this_operand].regs = r;
24eab124
AM		 8612 i.reg_operands++;
8613 }
af6bdddf
AM		 8614 else if (*op_string == REGISTER_PREFIX)
8615 {
8616 as_bad (_("bad register name `%s'"), op_string);
8617 return 0;
8618 }
24eab124 8619 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8620 {
24eab124 8621 ++op_string;
40fb9820 8622 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8623 {
d0b47220 8624 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8625 return 0;
8626 }
8627 if (!i386_immediate (op_string))
8628 return 0;
8629 }
43234a1e
L		 8630 else if (RC_SAE_immediate (operand_string))
8631 {
8632 /* If it is a RC or SAE immediate, do nothing. */
8633 ;
8634 }
24eab124
AM		 8635 else if (is_digit_char (*op_string)
8636 || is_identifier_char (*op_string)
d02603dc 8637 || *op_string == '"'
e5cb08ac 8638 || *op_string == '(')
24eab124 8639 {
47926f60 8640 /* This is a memory reference of some sort. */
af6bdddf 8641 char *base_string;
252b5132 8642
47926f60 8643 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8644 char *displacement_string_start;
8645 char *displacement_string_end;
43234a1e 8646 char *vop_start;
252b5132 8647
24eab124 8648 do_memory_reference:
24eab124 8649 if ((i.mem_operands == 1
40fb9820 8650 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8651 || i.mem_operands == 2)
8652 {
8653 as_bad (_("too many memory references for `%s'"),
8654 current_templates->start->name);
8655 return 0;
8656 }
252b5132 8657
24eab124
AM		 8658 /* Check for base index form. We detect the base index form by
8659 looking for an ')' at the end of the operand, searching
8660 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8661 after the '('. */
af6bdddf 8662 base_string = op_string + strlen (op_string);
c3332e24 8663
43234a1e
L		 8664 /* Handle vector operations. */
8665 vop_start = strchr (op_string, '{');
8666 if (vop_start && vop_start < base_string)
8667 {
8668 if (check_VecOperations (vop_start, base_string) == NULL)
8669 return 0;
8670 base_string = vop_start;
8671 }
8672
af6bdddf
AM		 8673 --base_string;
8674 if (is_space_char (*base_string))
8675 --base_string;
252b5132 8676
47926f60 8677 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8678 displacement_string_start = op_string;
8679 displacement_string_end = base_string + 1;
252b5132 8680
24eab124
AM		 8681 if (*base_string == ')')
8682 {
af6bdddf 8683 char *temp_string;
24eab124
AM		 8684 unsigned int parens_balanced = 1;
8685 /* We've already checked that the number of left & right ()'s are
47926f60 8686 equal, so this loop will not be infinite. */
24eab124
AM		 8687 do
8688 {
8689 base_string--;
8690 if (*base_string == ')')
8691 parens_balanced++;
8692 if (*base_string == '(')
8693 parens_balanced--;
8694 }
8695 while (parens_balanced);
c3332e24 8696
af6bdddf 8697 temp_string = base_string;
c3332e24 8698
24eab124 8699 /* Skip past '(' and whitespace. */
252b5132
RH		 8700 ++base_string;
8701 if (is_space_char (*base_string))
24eab124 8702 ++base_string;
252b5132 8703
af6bdddf 8704 if (*base_string == ','
4eed87de
AM		 8705 || ((i.base_reg = parse_register (base_string, &end_op))
8706 != NULL))
252b5132 8707 {
af6bdddf 8708 displacement_string_end = temp_string;
252b5132 8709
40fb9820 8710 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8711
af6bdddf 8712 if (i.base_reg)
24eab124 8713 {
24eab124
AM		 8714 base_string = end_op;
8715 if (is_space_char (*base_string))
8716 ++base_string;
af6bdddf
AM		 8717 }
8718
8719 /* There may be an index reg or scale factor here. */
8720 if (*base_string == ',')
8721 {
8722 ++base_string;
8723 if (is_space_char (*base_string))
8724 ++base_string;
8725
4eed87de
AM		 8726 if ((i.index_reg = parse_register (base_string, &end_op))
8727 != NULL)
24eab124 8728 {
af6bdddf 8729 base_string = end_op;
24eab124
AM		 8730 if (is_space_char (*base_string))
8731 ++base_string;
af6bdddf
AM		 8732 if (*base_string == ',')
8733 {
8734 ++base_string;
8735 if (is_space_char (*base_string))
8736 ++base_string;
8737 }
e5cb08ac 8738 else if (*base_string != ')')
af6bdddf 8739 {
4eed87de
AM		 8740 as_bad (_("expecting `,' or `)' "
8741 "after index register in `%s'"),
af6bdddf
AM		 8742 operand_string);
8743 return 0;
8744 }
24eab124 8745 }
af6bdddf 8746 else if (*base_string == REGISTER_PREFIX)
24eab124 8747 {
f76bf5e0
L		 8748 end_op = strchr (base_string, ',');
8749 if (end_op)
8750 *end_op = '\0';
af6bdddf 8751 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8752 return 0;
8753 }
252b5132 8754
47926f60 8755 /* Check for scale factor. */
551c1ca1 8756 if (*base_string != ')')
af6bdddf 8757 {
551c1ca1
AM		 8758 char *end_scale = i386_scale (base_string);
8759
8760 if (!end_scale)
af6bdddf 8761 return 0;
24eab124 8762
551c1ca1 8763 base_string = end_scale;
af6bdddf
AM		 8764 if (is_space_char (*base_string))
8765 ++base_string;
8766 if (*base_string != ')')
8767 {
4eed87de
AM		 8768 as_bad (_("expecting `)' "
8769 "after scale factor in `%s'"),
af6bdddf
AM		 8770 operand_string);
8771 return 0;
8772 }
8773 }
8774 else if (!i.index_reg)
24eab124 8775 {
4eed87de
AM		 8776 as_bad (_("expecting index register or scale factor "
8777 "after `,'; got '%c'"),
af6bdddf 8778 *base_string);
24eab124
AM		 8779 return 0;
8780 }
8781 }
af6bdddf 8782 else if (*base_string != ')')
24eab124 8783 {
4eed87de
AM		 8784 as_bad (_("expecting `,' or `)' "
8785 "after base register in `%s'"),
af6bdddf 8786 operand_string);
24eab124
AM		 8787 return 0;
8788 }
c3332e24 8789 }
af6bdddf 8790 else if (*base_string == REGISTER_PREFIX)
c3332e24 8791 {
f76bf5e0
L		 8792 end_op = strchr (base_string, ',');
8793 if (end_op)
8794 *end_op = '\0';
af6bdddf 8795 as_bad (_("bad register name `%s'"), base_string);
24eab124 8796 return 0;
c3332e24 8797 }
24eab124
AM		 8798 }
8799
8800 /* If there's an expression beginning the operand, parse it,
8801 assuming displacement_string_start and
8802 displacement_string_end are meaningful. */
8803 if (displacement_string_start != displacement_string_end)
8804 {
8805 if (!i386_displacement (displacement_string_start,
8806 displacement_string_end))
8807 return 0;
8808 }
8809
8810 /* Special case for (%dx) while doing input/output op. */
8811 if (i.base_reg
0dfbf9d7
L		 8812 && operand_type_equal (&i.base_reg->reg_type,
8813 &reg16_inoutportreg)
24eab124
AM		 8814 && i.index_reg == 0
8815 && i.log2_scale_factor == 0
8816 && i.seg[i.mem_operands] == 0
40fb9820 8817 && !operand_type_check (i.types[this_operand], disp))
24eab124 8818 {
65da13b5 8819 i.types[this_operand] = inoutportreg;
24eab124
AM		 8820 return 1;
8821 }
8822
eecb386c
AM		 8823 if (i386_index_check (operand_string) == 0)
8824 return 0;
5c07affc 8825 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8826 i.mem_operands++;
8827 }
8828 else
ce8a8b2f
AM		 8829 {
8830 /* It's not a memory operand; argh! */
24eab124
AM		 8831 as_bad (_("invalid char %s beginning operand %d `%s'"),
8832 output_invalid (*op_string),
8833 this_operand + 1,
8834 op_string);
8835 return 0;
8836 }
47926f60 8837 return 1; /* Normal return. */
252b5132
RH		 8838}
8839\f
fa94de6b
RM		 8840/* Calculate the maximum variable size (i.e., excluding fr_fix)
8841 that an rs_machine_dependent frag may reach. */
8842
8843unsigned int
8844i386_frag_max_var (fragS *frag)
8845{
8846 /* The only relaxable frags are for jumps.
8847 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8848 gas_assert (frag->fr_type == rs_machine_dependent);
8849 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8850}
8851
b084df0b
L		 8852#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8853static int
8dcea932 8854elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8855{
8856 /* STT_GNU_IFUNC symbol must go through PLT. */
8857 if ((symbol_get_bfdsym (fr_symbol)->flags
8858 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8859 return 0;
8860
8861 if (!S_IS_EXTERNAL (fr_symbol))
8862 /* Symbol may be weak or local. */
8863 return !S_IS_WEAK (fr_symbol);
8864
8dcea932
L		 8865 /* Global symbols with non-default visibility can't be preempted. */
8866 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8867 return 1;
8868
8869 if (fr_var != NO_RELOC)
8870 switch ((enum bfd_reloc_code_real) fr_var)
8871 {
8872 case BFD_RELOC_386_PLT32:
8873 case BFD_RELOC_X86_64_PLT32:
8874 /* Symbol with PLT relocatin may be preempted. */
8875 return 0;
8876 default:
8877 abort ();
8878 }
8879
b084df0b
L		 8880 /* Global symbols with default visibility in a shared library may be
8881 preempted by another definition. */
8dcea932 8882 return !shared;
b084df0b
L		 8883}
8884#endif
8885
ee7fcc42
AM		 8886/* md_estimate_size_before_relax()
8887
8888 Called just before relax() for rs_machine_dependent frags. The x86
8889 assembler uses these frags to handle variable size jump
8890 instructions.
8891
8892 Any symbol that is now undefined will not become defined.
8893 Return the correct fr_subtype in the frag.
8894 Return the initial "guess for variable size of frag" to caller.
8895 The guess is actually the growth beyond the fixed part. Whatever
8896 we do to grow the fixed or variable part contributes to our
8897 returned value. */
8898
252b5132 8899int
7016a5d5 8900md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8901{
252b5132 8902 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8903 check for un-relaxable symbols. On an ELF system, we can't relax
8904 an externally visible symbol, because it may be overridden by a
8905 shared library. */
8906 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8908 || (IS_ELF
8dcea932
L		 8909 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8910 fragP->fr_var))
fbeb56a4
DK		 8911#endif
8912#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8913 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8914 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8915#endif
8916 )
252b5132 8917 {
b98ef147
AM		 8918 /* Symbol is undefined in this segment, or we need to keep a
8919 reloc so that weak symbols can be overridden. */
8920 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8921 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8922 unsigned char *opcode;
8923 int old_fr_fix;
f6af82bd 8924
ee7fcc42 8925 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8926 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8927 else if (size == 2)
f6af82bd
AM		 8928 reloc_type = BFD_RELOC_16_PCREL;
8929 else
8930 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8931
ee7fcc42
AM		 8932 old_fr_fix = fragP->fr_fix;
8933 opcode = (unsigned char *) fragP->fr_opcode;
8934
fddf5b5b 8935 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8936 {
fddf5b5b
AM		 8937 case UNCOND_JUMP:
8938 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8939 opcode[0] = 0xe9;
252b5132 8940 fragP->fr_fix += size;
062cd5e7
AS		 8941 fix_new (fragP, old_fr_fix, size,
8942 fragP->fr_symbol,
8943 fragP->fr_offset, 1,
8944 reloc_type);
252b5132
RH		 8945 break;
8946
fddf5b5b 8947 case COND_JUMP86:
412167cb
AM		 8948 if (size == 2
8949 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8950 {
8951 /* Negate the condition, and branch past an
8952 unconditional jump. */
8953 opcode[0] ^= 1;
8954 opcode[1] = 3;
8955 /* Insert an unconditional jump. */
8956 opcode[2] = 0xe9;
8957 /* We added two extra opcode bytes, and have a two byte
8958 offset. */
8959 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8960 fix_new (fragP, old_fr_fix + 2, 2,
8961 fragP->fr_symbol,
8962 fragP->fr_offset, 1,
8963 reloc_type);
fddf5b5b
AM		 8964 break;
8965 }
8966 /* Fall through. */
8967
8968 case COND_JUMP:
412167cb
AM		 8969 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8970 {
3e02c1cc
AM		 8971 fixS *fixP;
8972
412167cb 8973 fragP->fr_fix += 1;
3e02c1cc
AM		 8974 fixP = fix_new (fragP, old_fr_fix, 1,
8975 fragP->fr_symbol,
8976 fragP->fr_offset, 1,
8977 BFD_RELOC_8_PCREL);
8978 fixP->fx_signed = 1;
412167cb
AM		 8979 break;
8980 }
93c2a809 8981
24eab124 8982 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8983 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8984 opcode[1] = opcode[0] + 0x10;
f6af82bd 8985 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8986 /* We've added an opcode byte. */
8987 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8988 fix_new (fragP, old_fr_fix + 1, size,
8989 fragP->fr_symbol,
8990 fragP->fr_offset, 1,
8991 reloc_type);
252b5132 8992 break;
fddf5b5b
AM		 8993
8994 default:
8995 BAD_CASE (fragP->fr_subtype);
8996 break;
252b5132
RH		 8997 }
8998 frag_wane (fragP);
ee7fcc42 8999 return fragP->fr_fix - old_fr_fix;
252b5132 9000 }
93c2a809 9001
93c2a809
AM		 9002 /* Guess size depending on current relax state. Initially the relax
9003 state will correspond to a short jump and we return 1, because
9004 the variable part of the frag (the branch offset) is one byte
9005 long. However, we can relax a section more than once and in that
9006 case we must either set fr_subtype back to the unrelaxed state,
9007 or return the value for the appropriate branch. */
9008 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9009}
9010
47926f60
KH		 9011/* Called after relax() is finished.
9012
9013 In: Address of frag.
9014 fr_type == rs_machine_dependent.
9015 fr_subtype is what the address relaxed to.
9016
9017 Out: Any fixSs and constants are set up.
9018 Caller will turn frag into a ".space 0". */
9019
252b5132 9020void
7016a5d5
TG		 9021md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9022 fragS *fragP)
252b5132 9023{
29b0f896 9024 unsigned char *opcode;
252b5132 9025 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9026 offsetT target_address;
9027 offsetT opcode_address;
252b5132 9028 unsigned int extension = 0;
847f7ad4 9029 offsetT displacement_from_opcode_start;
252b5132
RH		 9030
9031 opcode = (unsigned char *) fragP->fr_opcode;
9032
47926f60 9033 /* Address we want to reach in file space. */
252b5132 9034 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9035
47926f60 9036 /* Address opcode resides at in file space. */
252b5132
RH		 9037 opcode_address = fragP->fr_address + fragP->fr_fix;
9038
47926f60 9039 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9040 displacement_from_opcode_start = target_address - opcode_address;
9041
fddf5b5b 9042 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9043 {
47926f60
KH		 9044 /* Don't have to change opcode. */
9045 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9046 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9047 }
9048 else
9049 {
9050 if (no_cond_jump_promotion
9051 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9052 as_warn_where (fragP->fr_file, fragP->fr_line,
9053 _("long jump required"));
252b5132 9054
fddf5b5b
AM		 9055 switch (fragP->fr_subtype)
9056 {
9057 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9058 extension = 4; /* 1 opcode + 4 displacement */
9059 opcode[0] = 0xe9;
9060 where_to_put_displacement = &opcode[1];
9061 break;
252b5132 9062
fddf5b5b
AM		 9063 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9064 extension = 2; /* 1 opcode + 2 displacement */
9065 opcode[0] = 0xe9;
9066 where_to_put_displacement = &opcode[1];
9067 break;
252b5132 9068
fddf5b5b
AM		 9069 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9070 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9071 extension = 5; /* 2 opcode + 4 displacement */
9072 opcode[1] = opcode[0] + 0x10;
9073 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9074 where_to_put_displacement = &opcode[2];
9075 break;
252b5132 9076
fddf5b5b
AM		 9077 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9078 extension = 3; /* 2 opcode + 2 displacement */
9079 opcode[1] = opcode[0] + 0x10;
9080 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9081 where_to_put_displacement = &opcode[2];
9082 break;
252b5132 9083
fddf5b5b
AM		 9084 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9085 extension = 4;
9086 opcode[0] ^= 1;
9087 opcode[1] = 3;
9088 opcode[2] = 0xe9;
9089 where_to_put_displacement = &opcode[3];
9090 break;
9091
9092 default:
9093 BAD_CASE (fragP->fr_subtype);
9094 break;
9095 }
252b5132 9096 }
fddf5b5b 9097
7b81dfbb
AJ		 9098 /* If size if less then four we are sure that the operand fits,
9099 but if it's 4, then it could be that the displacement is larger
9100 then -/+ 2GB. */
9101 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9102 && object_64bit
9103 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9104 + ((addressT) 1 << 31))
9105 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9106 {
9107 as_bad_where (fragP->fr_file, fragP->fr_line,
9108 _("jump target out of range"));
9109 /* Make us emit 0. */
9110 displacement_from_opcode_start = extension;
9111 }
47926f60 9112 /* Now put displacement after opcode. */
252b5132
RH		 9113 md_number_to_chars ((char *) where_to_put_displacement,
9114 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9115 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9116 fragP->fr_fix += extension;
9117}
9118\f
7016a5d5 9119/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9120 by our caller that we have all the info we need to fix it up.
9121
7016a5d5
TG		 9122 Parameter valP is the pointer to the value of the bits.
9123
252b5132
RH		 9124 On the 386, immediates, displacements, and data pointers are all in
9125 the same (little-endian) format, so we don't need to care about which
9126 we are handling. */
9127
94f592af 9128void
7016a5d5 9129md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9130{
94f592af 9131 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9132 valueT value = *valP;
252b5132 9133
f86103b7 9134#if !defined (TE_Mach)
93382f6d
AM		 9135 if (fixP->fx_pcrel)
9136 {
9137 switch (fixP->fx_r_type)
9138 {
5865bb77
ILT		 9139 default:
9140 break;
9141
d6ab8113
JB		 9142 case BFD_RELOC_64:
9143 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9144 break;
93382f6d 9145 case BFD_RELOC_32:
ae8887b5 9146 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9147 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9148 break;
9149 case BFD_RELOC_16:
9150 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9151 break;
9152 case BFD_RELOC_8:
9153 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9154 break;
9155 }
9156 }
252b5132 9157
a161fe53 9158 if (fixP->fx_addsy != NULL
31312f95 9159 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9160 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9161 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9162 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9163 && !use_rela_relocations)
252b5132 9164 {
31312f95
AM		 9165 /* This is a hack. There should be a better way to handle this.
9166 This covers for the fact that bfd_install_relocation will
9167 subtract the current location (for partial_inplace, PC relative
9168 relocations); see more below. */
252b5132 9169#ifndef OBJ_AOUT
718ddfc0 9170 if (IS_ELF
252b5132
RH		 9171#ifdef TE_PE
9172 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9173#endif
9174 )
9175 value += fixP->fx_where + fixP->fx_frag->fr_address;
9176#endif
9177#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9178 if (IS_ELF)
252b5132 9179 {
6539b54b 9180 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9181
6539b54b 9182 if ((sym_seg == seg
2f66722d 9183 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9184 && sym_seg != absolute_section))
af65af87 9185 && !generic_force_reloc (fixP))
2f66722d
AM		 9186 {
9187 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9188 bfd_install_relocation subtracts them out again. I think
9189 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9190 it. FIXME. */
9191 value += fixP->fx_where + fixP->fx_frag->fr_address;
9192 }
252b5132
RH		 9193 }
9194#endif
9195#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9196 /* For some reason, the PE format does not store a
9197 section address offset for a PC relative symbol. */
9198 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9199 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9200 value += md_pcrel_from (fixP);
9201#endif
9202 }
fbeb56a4 9203#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9204 if (fixP->fx_addsy != NULL
9205 && S_IS_WEAK (fixP->fx_addsy)
9206 /* PR 16858: Do not modify weak function references. */
9207 && ! fixP->fx_pcrel)
fbeb56a4 9208 {
296a8689
NC		 9209#if !defined (TE_PEP)
9210 /* For x86 PE weak function symbols are neither PC-relative
9211 nor do they set S_IS_FUNCTION. So the only reliable way
9212 to detect them is to check the flags of their containing
9213 section. */
9214 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9215 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9216 ;
9217 else
9218#endif
fbeb56a4
DK		 9219 value -= S_GET_VALUE (fixP->fx_addsy);
9220 }
9221#endif
252b5132
RH		 9222
9223 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9224 and we must not disappoint it. */
252b5132 9225#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9226 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9227 switch (fixP->fx_r_type)
9228 {
9229 case BFD_RELOC_386_PLT32:
3e73aa7c 9230 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9231 /* Make the jump instruction point to the address of the operand. At
9232 runtime we merely add the offset to the actual PLT entry. */
9233 value = -4;
9234 break;
31312f95 9235
13ae64f3
JJ		 9236 case BFD_RELOC_386_TLS_GD:
9237 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9238 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9239 case BFD_RELOC_386_TLS_IE:
9240 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9241 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9242 case BFD_RELOC_X86_64_TLSGD:
9243 case BFD_RELOC_X86_64_TLSLD:
9244 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9245 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9246 value = 0; /* Fully resolved at runtime. No addend. */
9247 /* Fallthrough */
9248 case BFD_RELOC_386_TLS_LE:
9249 case BFD_RELOC_386_TLS_LDO_32:
9250 case BFD_RELOC_386_TLS_LE_32:
9251 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9252 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9253 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9254 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9255 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9256 break;
9257
67a4f2b7
AO		 9258 case BFD_RELOC_386_TLS_DESC_CALL:
9259 case BFD_RELOC_X86_64_TLSDESC_CALL:
9260 value = 0; /* Fully resolved at runtime. No addend. */
9261 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9262 fixP->fx_done = 0;
9263 return;
9264
00f7efb6
JJ		 9265 case BFD_RELOC_386_GOT32:
9266 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9267 value = 0; /* Fully resolved at runtime. No addend. */
9268 break;
47926f60
KH		 9269
9270 case BFD_RELOC_VTABLE_INHERIT:
9271 case BFD_RELOC_VTABLE_ENTRY:
9272 fixP->fx_done = 0;
94f592af 9273 return;
47926f60
KH		 9274
9275 default:
9276 break;
9277 }
9278#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9279 *valP = value;
f86103b7 9280#endif /* !defined (TE_Mach) */
3e73aa7c 9281
3e73aa7c 9282 /* Are we finished with this relocation now? */
c6682705 9283 if (fixP->fx_addsy == NULL)
3e73aa7c 9284 fixP->fx_done = 1;
fbeb56a4
DK		 9285#if defined (OBJ_COFF) && defined (TE_PE)
9286 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9287 {
9288 fixP->fx_done = 0;
9289 /* Remember value for tc_gen_reloc. */
9290 fixP->fx_addnumber = value;
9291 /* Clear out the frag for now. */
9292 value = 0;
9293 }
9294#endif
3e73aa7c
JH		 9295 else if (use_rela_relocations)
9296 {
9297 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9298 /* Remember value for tc_gen_reloc. */
9299 fixP->fx_addnumber = value;
3e73aa7c
JH		 9300 value = 0;
9301 }
f86103b7 9302
94f592af 9303 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9304}
252b5132 9305\f
252b5132 9306char *
499ac353 9307md_atof (int type, char *litP, int *sizeP)
252b5132 9308{
499ac353
NC		 9309 /* This outputs the LITTLENUMs in REVERSE order;
9310 in accord with the bigendian 386. */
9311 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9312}
9313\f
2d545b82 9314static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9315
252b5132 9316static char *
e3bb37b5 9317output_invalid (int c)
252b5132 9318{
3882b010 9319 if (ISPRINT (c))
f9f21a03
L		 9320 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9321 "'%c'", c);
252b5132 9322 else
f9f21a03 9323 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9324 "(0x%x)", (unsigned char) c);
252b5132
RH		 9325 return output_invalid_buf;
9326}
9327
af6bdddf 9328/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9329
9330static const reg_entry *
4d1bb795 9331parse_real_register (char *reg_string, char **end_op)
252b5132 9332{
af6bdddf
AM		 9333 char *s = reg_string;
9334 char *p;
252b5132
RH		 9335 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9336 const reg_entry *r;
9337
9338 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9339 if (*s == REGISTER_PREFIX)
9340 ++s;
9341
9342 if (is_space_char (*s))
9343 ++s;
9344
9345 p = reg_name_given;
af6bdddf 9346 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9347 {
9348 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9349 return (const reg_entry *) NULL;
9350 s++;
252b5132
RH		 9351 }
9352
6588847e
DN		 9353 /* For naked regs, make sure that we are not dealing with an identifier.
9354 This prevents confusing an identifier like `eax_var' with register
9355 `eax'. */
9356 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9357 return (const reg_entry *) NULL;
9358
af6bdddf 9359 *end_op = s;
252b5132
RH		 9360
9361 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9362
5f47d35b 9363 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9364 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9365 {
5f47d35b
AM		 9366 if (is_space_char (*s))
9367 ++s;
9368 if (*s == '(')
9369 {
af6bdddf 9370 ++s;
5f47d35b
AM		 9371 if (is_space_char (*s))
9372 ++s;
9373 if (*s >= '0' && *s <= '7')
9374 {
db557034 9375 int fpr = *s - '0';
af6bdddf 9376 ++s;
5f47d35b
AM		 9377 if (is_space_char (*s))
9378 ++s;
9379 if (*s == ')')
9380 {
9381 *end_op = s + 1;
1e9cc1c2 9382 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9383 know (r);
9384 return r + fpr;
5f47d35b 9385 }
5f47d35b 9386 }
47926f60 9387 /* We have "%st(" then garbage. */
5f47d35b
AM		 9388 return (const reg_entry *) NULL;
9389 }
9390 }
9391
a60de03c
JB		 9392 if (r == NULL || allow_pseudo_reg)
9393 return r;
9394
0dfbf9d7 9395 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9396 return (const reg_entry *) NULL;
9397
192dc9c6
JB		 9398 if ((r->reg_type.bitfield.reg32
9399 || r->reg_type.bitfield.sreg3
9400 || r->reg_type.bitfield.control
9401 || r->reg_type.bitfield.debug
9402 || r->reg_type.bitfield.test)
9403 && !cpu_arch_flags.bitfield.cpui386)
9404 return (const reg_entry *) NULL;
9405
309d3373
JB		 9406 if (r->reg_type.bitfield.floatreg
9407 && !cpu_arch_flags.bitfield.cpu8087
9408 && !cpu_arch_flags.bitfield.cpu287
9409 && !cpu_arch_flags.bitfield.cpu387)
9410 return (const reg_entry *) NULL;
9411
192dc9c6
JB		 9412 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9413 return (const reg_entry *) NULL;
9414
9415 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9416 return (const reg_entry *) NULL;
9417
40f12533
L		 9418 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9419 return (const reg_entry *) NULL;
9420
43234a1e
L		 9421 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9422 && !cpu_arch_flags.bitfield.cpuavx512f)
9423 return (const reg_entry *) NULL;
9424
db51cc60 9425 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9426 if (!allow_index_reg
db51cc60
L		 9427 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9428 return (const reg_entry *) NULL;
9429
43234a1e
L		 9430 /* Upper 16 vector register is only available with VREX in 64bit
9431 mode. */
9432 if ((r->reg_flags & RegVRex))
9433 {
9434 if (!cpu_arch_flags.bitfield.cpuvrex
9435 || flag_code != CODE_64BIT)
9436 return (const reg_entry *) NULL;
9437
9438 i.need_vrex = 1;
9439 }
9440
a60de03c
JB		 9441 if (((r->reg_flags & (RegRex64 | RegRex))
9442 || r->reg_type.bitfield.reg64)
40fb9820 9443 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9444 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9445 && flag_code != CODE_64BIT)
20f0a1fc 9446 return (const reg_entry *) NULL;
1ae00879 9447
b7240065
JB		 9448 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9449 return (const reg_entry *) NULL;
9450
252b5132
RH		 9451 return r;
9452}
4d1bb795
JB		 9453
9454/* REG_STRING starts *before* REGISTER_PREFIX. */
9455
9456static const reg_entry *
9457parse_register (char *reg_string, char **end_op)
9458{
9459 const reg_entry *r;
9460
9461 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9462 r = parse_real_register (reg_string, end_op);
9463 else
9464 r = NULL;
9465 if (!r)
9466 {
9467 char *save = input_line_pointer;
9468 char c;
9469 symbolS *symbolP;
9470
9471 input_line_pointer = reg_string;
d02603dc 9472 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9473 symbolP = symbol_find (reg_string);
9474 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9475 {
9476 const expressionS *e = symbol_get_value_expression (symbolP);
9477
0398aac5 9478 know (e->X_op == O_register);
4eed87de 9479 know (e->X_add_number >= 0
c3fe08fa 9480 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9481 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9482 if ((r->reg_flags & RegVRex))
9483 i.need_vrex = 1;
4d1bb795
JB		 9484 *end_op = input_line_pointer;
9485 }
9486 *input_line_pointer = c;
9487 input_line_pointer = save;
9488 }
9489 return r;
9490}
9491
9492int
9493i386_parse_name (char *name, expressionS *e, char *nextcharP)
9494{
9495 const reg_entry *r;
9496 char *end = input_line_pointer;
9497
9498 *end = *nextcharP;
9499 r = parse_register (name, &input_line_pointer);
9500 if (r && end <= input_line_pointer)
9501 {
9502 *nextcharP = *input_line_pointer;
9503 *input_line_pointer = 0;
9504 e->X_op = O_register;
9505 e->X_add_number = r - i386_regtab;
9506 return 1;
9507 }
9508 input_line_pointer = end;
9509 *end = 0;
ee86248c 9510 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9511}
9512
9513void
9514md_operand (expressionS *e)
9515{
ee86248c
JB		 9516 char *end;
9517 const reg_entry *r;
4d1bb795 9518
ee86248c
JB		 9519 switch (*input_line_pointer)
9520 {
9521 case REGISTER_PREFIX:
9522 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9523 if (r)
9524 {
9525 e->X_op = O_register;
9526 e->X_add_number = r - i386_regtab;
9527 input_line_pointer = end;
9528 }
ee86248c
JB		 9529 break;
9530
9531 case '[':
9c2799c2 9532 gas_assert (intel_syntax);
ee86248c
JB		 9533 end = input_line_pointer++;
9534 expression (e);
9535 if (*input_line_pointer == ']')
9536 {
9537 ++input_line_pointer;
9538 e->X_op_symbol = make_expr_symbol (e);
9539 e->X_add_symbol = NULL;
9540 e->X_add_number = 0;
9541 e->X_op = O_index;
9542 }
9543 else
9544 {
9545 e->X_op = O_absent;
9546 input_line_pointer = end;
9547 }
9548 break;
4d1bb795
JB		 9549 }
9550}
9551
252b5132 9552\f
4cc782b5 9553#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9554const char *md_shortopts = "kVQ:sqn";
252b5132 9555#else
12b55ccc 9556const char *md_shortopts = "qn";
252b5132 9557#endif
6e0b89ee 9558
3e73aa7c 9559#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9560#define OPTION_64 (OPTION_MD_BASE + 1)
9561#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9562#define OPTION_MARCH (OPTION_MD_BASE + 3)
9563#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9564#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9565#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9566#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9567#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9568#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9569#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9570#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9571#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9572#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9573#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9574#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9575#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9576#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9577#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9578#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9579#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9580#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9581#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9582#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
b3b91714 9583
99ad8390
NC		 9584struct option md_longopts[] =
9585{
3e73aa7c 9586 {"32", no_argument, NULL, OPTION_32},
321098a5 9587#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9588 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9589 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9590#endif
9591#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9592 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9593 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9594#endif
b3b91714 9595 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9596 {"march", required_argument, NULL, OPTION_MARCH},
9597 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9598 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9599 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9600 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9601 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9602 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9603 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9604 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9605 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9606 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9607 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9608 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9609 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9610# if defined (TE_PE) || defined (TE_PEP)
9611 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9612#endif
a5094208 9613 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9614 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9615 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9616 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9617 {NULL, no_argument, NULL, 0}
9618};
9619size_t md_longopts_size = sizeof (md_longopts);
9620
9621int
9103f4f4 9622md_parse_option (int c, char *arg)
252b5132 9623{
91d6fa6a 9624 unsigned int j;
6305a203 9625 char *arch, *next;
9103f4f4 9626
252b5132
RH		 9627 switch (c)
9628 {
12b55ccc
L		 9629 case 'n':
9630 optimize_align_code = 0;
9631 break;
9632
a38cf1db
AM		 9633 case 'q':
9634 quiet_warnings = 1;
252b5132
RH		 9635 break;
9636
9637#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9638 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9639 should be emitted or not. FIXME: Not implemented. */
9640 case 'Q':
252b5132
RH		 9641 break;
9642
9643 /* -V: SVR4 argument to print version ID. */
9644 case 'V':
9645 print_version_id ();
9646 break;
9647
a38cf1db
AM		 9648 /* -k: Ignore for FreeBSD compatibility. */
9649 case 'k':
252b5132 9650 break;
4cc782b5
ILT		 9651
9652 case 's':
9653 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9654 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9655 break;
8dcea932
L		 9656
9657 case OPTION_MSHARED:
9658 shared = 1;
9659 break;
99ad8390 9660#endif
321098a5 9661#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9662 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9663 case OPTION_64:
9664 {
9665 const char **list, **l;
9666
3e73aa7c
JH		 9667 list = bfd_target_list ();
9668 for (l = list; *l != NULL; l++)
8620418b 9669 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9670 || strcmp (*l, "coff-x86-64") == 0
9671 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9672 || strcmp (*l, "pei-x86-64") == 0
9673 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9674 {
9675 default_arch = "x86_64";
9676 break;
9677 }
3e73aa7c 9678 if (*l == NULL)
2b5d6a91 9679 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9680 free (list);
9681 }
9682 break;
9683#endif
252b5132 9684
351f65ca 9685#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9686 case OPTION_X32:
351f65ca
L		 9687 if (IS_ELF)
9688 {
9689 const char **list, **l;
9690
9691 list = bfd_target_list ();
9692 for (l = list; *l != NULL; l++)
9693 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9694 {
9695 default_arch = "x86_64:32";
9696 break;
9697 }
9698 if (*l == NULL)
2b5d6a91 9699 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9700 free (list);
9701 }
9702 else
9703 as_fatal (_("32bit x86_64 is only supported for ELF"));
9704 break;
9705#endif
9706
6e0b89ee
AM		 9707 case OPTION_32:
9708 default_arch = "i386";
9709 break;
9710
b3b91714
AM		 9711 case OPTION_DIVIDE:
9712#ifdef SVR4_COMMENT_CHARS
9713 {
9714 char *n, *t;
9715 const char *s;
9716
9717 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9718 t = n;
9719 for (s = i386_comment_chars; *s != '\0'; s++)
9720 if (*s != '/')
9721 *t++ = *s;
9722 *t = '\0';
9723 i386_comment_chars = n;
9724 }
9725#endif
9726 break;
9727
9103f4f4 9728 case OPTION_MARCH:
6305a203
L		 9729 arch = xstrdup (arg);
9730 do
9103f4f4 9731 {
6305a203 9732 if (*arch == '.')
2b5d6a91 9733 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9734 next = strchr (arch, '+');
9735 if (next)
9736 *next++ = '\0';
91d6fa6a 9737 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9738 {
91d6fa6a 9739 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9740 {
6305a203 9741 /* Processor. */
1ded5609
JB		 9742 if (! cpu_arch[j].flags.bitfield.cpui386)
9743 continue;
9744
91d6fa6a 9745 cpu_arch_name = cpu_arch[j].name;
6305a203 9746 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9747 cpu_arch_flags = cpu_arch[j].flags;
9748 cpu_arch_isa = cpu_arch[j].type;
9749 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9750 if (!cpu_arch_tune_set)
9751 {
9752 cpu_arch_tune = cpu_arch_isa;
9753 cpu_arch_tune_flags = cpu_arch_isa_flags;
9754 }
9755 break;
9756 }
91d6fa6a
NC		 9757 else if (*cpu_arch [j].name == '.'
9758 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9759 {
9760 /* ISA entension. */
9761 i386_cpu_flags flags;
309d3373 9762
49021df2 9763 if (!cpu_arch[j].negated)
309d3373 9764 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9765 cpu_arch[j].flags);
309d3373
JB		 9766 else
9767 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9768 cpu_arch[j].flags);
81486035
L		 9769
9770 if (!valid_iamcu_cpu_flags (&flags))
9771 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9772 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9773 {
9774 if (cpu_sub_arch_name)
9775 {
9776 char *name = cpu_sub_arch_name;
9777 cpu_sub_arch_name = concat (name,
91d6fa6a 9778 cpu_arch[j].name,
1bf57e9f 9779 (const char *) NULL);
6305a203
L		 9780 free (name);
9781 }
9782 else
91d6fa6a 9783 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9784 cpu_arch_flags = flags;
a586129e 9785 cpu_arch_isa_flags = flags;
6305a203
L		 9786 }
9787 break;
ccc9c027 9788 }
9103f4f4 9789 }
6305a203 9790
91d6fa6a 9791 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9792 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9793
9794 arch = next;
9103f4f4 9795 }
6305a203 9796 while (next != NULL );
9103f4f4
L		 9797 break;
9798
9799 case OPTION_MTUNE:
9800 if (*arg == '.')
2b5d6a91 9801 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9802 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9803 {
91d6fa6a 9804 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9805 {
ccc9c027 9806 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9807 cpu_arch_tune = cpu_arch [j].type;
9808 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9809 break;
9810 }
9811 }
91d6fa6a 9812 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9813 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9814 break;
9815
1efbbeb4
L		 9816 case OPTION_MMNEMONIC:
9817 if (strcasecmp (arg, "att") == 0)
9818 intel_mnemonic = 0;
9819 else if (strcasecmp (arg, "intel") == 0)
9820 intel_mnemonic = 1;
9821 else
2b5d6a91 9822 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9823 break;
9824
9825 case OPTION_MSYNTAX:
9826 if (strcasecmp (arg, "att") == 0)
9827 intel_syntax = 0;
9828 else if (strcasecmp (arg, "intel") == 0)
9829 intel_syntax = 1;
9830 else
2b5d6a91 9831 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9832 break;
9833
9834 case OPTION_MINDEX_REG:
9835 allow_index_reg = 1;
9836 break;
9837
9838 case OPTION_MNAKED_REG:
9839 allow_naked_reg = 1;
9840 break;
9841
9842 case OPTION_MOLD_GCC:
9843 old_gcc = 1;
1efbbeb4
L		 9844 break;
9845
c0f3af97
L		 9846 case OPTION_MSSE2AVX:
9847 sse2avx = 1;
9848 break;
9849
daf50ae7
L		 9850 case OPTION_MSSE_CHECK:
9851 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9852 sse_check = check_error;
daf50ae7 9853 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9854 sse_check = check_warning;
daf50ae7 9855 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9856 sse_check = check_none;
daf50ae7 9857 else
2b5d6a91 9858 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9859 break;
9860
7bab8ab5
JB		 9861 case OPTION_MOPERAND_CHECK:
9862 if (strcasecmp (arg, "error") == 0)
9863 operand_check = check_error;
9864 else if (strcasecmp (arg, "warning") == 0)
9865 operand_check = check_warning;
9866 else if (strcasecmp (arg, "none") == 0)
9867 operand_check = check_none;
9868 else
9869 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9870 break;
9871
539f890d
L		 9872 case OPTION_MAVXSCALAR:
9873 if (strcasecmp (arg, "128") == 0)
9874 avxscalar = vex128;
9875 else if (strcasecmp (arg, "256") == 0)
9876 avxscalar = vex256;
9877 else
2b5d6a91 9878 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9879 break;
9880
7e8b059b
L		 9881 case OPTION_MADD_BND_PREFIX:
9882 add_bnd_prefix = 1;
9883 break;
9884
43234a1e
L		 9885 case OPTION_MEVEXLIG:
9886 if (strcmp (arg, "128") == 0)
9887 evexlig = evexl128;
9888 else if (strcmp (arg, "256") == 0)
9889 evexlig = evexl256;
9890 else if (strcmp (arg, "512") == 0)
9891 evexlig = evexl512;
9892 else
9893 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9894 break;
9895
d3d3c6db
IT		 9896 case OPTION_MEVEXRCIG:
9897 if (strcmp (arg, "rne") == 0)
9898 evexrcig = rne;
9899 else if (strcmp (arg, "rd") == 0)
9900 evexrcig = rd;
9901 else if (strcmp (arg, "ru") == 0)
9902 evexrcig = ru;
9903 else if (strcmp (arg, "rz") == 0)
9904 evexrcig = rz;
9905 else
9906 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9907 break;
9908
43234a1e
L		 9909 case OPTION_MEVEXWIG:
9910 if (strcmp (arg, "0") == 0)
9911 evexwig = evexw0;
9912 else if (strcmp (arg, "1") == 0)
9913 evexwig = evexw1;
9914 else
9915 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9916 break;
9917
167ad85b
TG		 9918# if defined (TE_PE) || defined (TE_PEP)
9919 case OPTION_MBIG_OBJ:
9920 use_big_obj = 1;
9921 break;
9922#endif
9923
a5094208 9924 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9925 if (strcasecmp (arg, "yes") == 0)
9926 omit_lock_prefix = 1;
9927 else if (strcasecmp (arg, "no") == 0)
9928 omit_lock_prefix = 0;
9929 else
9930 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9931 break;
9932
5db04b09
L		 9933 case OPTION_MAMD64:
9934 cpu_arch_flags.bitfield.cpuamd64 = 1;
9935 cpu_arch_flags.bitfield.cpuintel64 = 0;
9936 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
9937 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
9938 break;
9939
9940 case OPTION_MINTEL64:
9941 cpu_arch_flags.bitfield.cpuamd64 = 0;
9942 cpu_arch_flags.bitfield.cpuintel64 = 1;
9943 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
9944 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
9945 break;
9946
252b5132
RH		 9947 default:
9948 return 0;
9949 }
9950 return 1;
9951}
9952
8a2c8fef
L		 9953#define MESSAGE_TEMPLATE \
9954" "
9955
9956static void
1ded5609 9957show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9958{
9959 static char message[] = MESSAGE_TEMPLATE;
9960 char *start = message + 27;
9961 char *p;
9962 int size = sizeof (MESSAGE_TEMPLATE);
9963 int left;
9964 const char *name;
9965 int len;
9966 unsigned int j;
9967
9968 p = start;
9969 left = size - (start - message);
9970 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9971 {
9972 /* Should it be skipped? */
9973 if (cpu_arch [j].skip)
9974 continue;
9975
9976 name = cpu_arch [j].name;
9977 len = cpu_arch [j].len;
9978 if (*name == '.')
9979 {
9980 /* It is an extension. Skip if we aren't asked to show it. */
9981 if (ext)
9982 {
9983 name++;
9984 len--;
9985 }
9986 else
9987 continue;
9988 }
9989 else if (ext)
9990 {
9991 /* It is an processor. Skip if we show only extension. */
9992 continue;
9993 }
1ded5609
JB		 9994 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9995 {
9996 /* It is an impossible processor - skip. */
9997 continue;
9998 }
8a2c8fef
L		 9999
10000 /* Reserve 2 spaces for ", " or ",\0" */
10001 left -= len + 2;
10002
10003 /* Check if there is any room. */
10004 if (left >= 0)
10005 {
10006 if (p != start)
10007 {
10008 *p++ = ',';
10009 *p++ = ' ';
10010 }
10011 p = mempcpy (p, name, len);
10012 }
10013 else
10014 {
10015 /* Output the current message now and start a new one. */
10016 *p++ = ',';
10017 *p = '\0';
10018 fprintf (stream, "%s\n", message);
10019 p = start;
10020 left = size - (start - message) - len - 2;
8d63c93e 10021
8a2c8fef
L		 10022 gas_assert (left >= 0);
10023
10024 p = mempcpy (p, name, len);
10025 }
10026 }
10027
10028 *p = '\0';
10029 fprintf (stream, "%s\n", message);
10030}
10031
252b5132 10032void
8a2c8fef 10033md_show_usage (FILE *stream)
252b5132 10034{
4cc782b5
ILT		 10035#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10036 fprintf (stream, _("\
a38cf1db
AM		 10037 -Q ignored\n\
10038 -V print assembler version number\n\
b3b91714
AM		 10039 -k ignored\n"));
10040#endif
10041 fprintf (stream, _("\
12b55ccc 10042 -n Do not optimize code alignment\n\
b3b91714
AM		 10043 -q quieten some warnings\n"));
10044#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10045 fprintf (stream, _("\
a38cf1db 10046 -s ignored\n"));
b3b91714 10047#endif
321098a5
L		 10048#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10049 || defined (TE_PE) || defined (TE_PEP))
751d281c 10050 fprintf (stream, _("\
570561f7 10051 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10052#endif
b3b91714
AM		 10053#ifdef SVR4_COMMENT_CHARS
10054 fprintf (stream, _("\
10055 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10056#else
10057 fprintf (stream, _("\
b3b91714 10058 --divide ignored\n"));
4cc782b5 10059#endif
9103f4f4 10060 fprintf (stream, _("\
6305a203 10061 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10062 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10063 show_arch (stream, 0, 1);
8a2c8fef
L		 10064 fprintf (stream, _("\
10065 EXTENSION is combination of:\n"));
1ded5609 10066 show_arch (stream, 1, 0);
6305a203 10067 fprintf (stream, _("\
8a2c8fef 10068 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10069 show_arch (stream, 0, 0);
ba104c83 10070 fprintf (stream, _("\
c0f3af97
L		 10071 -msse2avx encode SSE instructions with VEX prefix\n"));
10072 fprintf (stream, _("\
daf50ae7
L		 10073 -msse-check=[none|error|warning]\n\
10074 check SSE instructions\n"));
10075 fprintf (stream, _("\
7bab8ab5
JB		 10076 -moperand-check=[none|error|warning]\n\
10077 check operand combinations for validity\n"));
10078 fprintf (stream, _("\
539f890d
L		 10079 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10080 length\n"));
10081 fprintf (stream, _("\
43234a1e
L		 10082 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10083 length\n"));
10084 fprintf (stream, _("\
10085 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10086 for EVEX.W bit ignored instructions\n"));
10087 fprintf (stream, _("\
d3d3c6db
IT		 10088 -mevexrcig=[rne|rd|ru|rz]\n\
10089 encode EVEX instructions with specific EVEX.RC value\n\
10090 for SAE-only ignored instructions\n"));
10091 fprintf (stream, _("\
ba104c83
L		 10092 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10093 fprintf (stream, _("\
10094 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10095 fprintf (stream, _("\
10096 -mindex-reg support pseudo index registers\n"));
10097 fprintf (stream, _("\
10098 -mnaked-reg don't require `%%' prefix for registers\n"));
10099 fprintf (stream, _("\
10100 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10101 fprintf (stream, _("\
10102 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10103 fprintf (stream, _("\
10104 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10105# if defined (TE_PE) || defined (TE_PEP)
10106 fprintf (stream, _("\
10107 -mbig-obj generate big object files\n"));
10108#endif
d022bddd
IT		 10109 fprintf (stream, _("\
10110 -momit-lock-prefix=[no|yes]\n\
10111 strip all lock prefixes\n"));
5db04b09
L		 10112 fprintf (stream, _("\
10113 -mamd64 accept only AMD64 ISA\n"));
10114 fprintf (stream, _("\
10115 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10116}
10117
3e73aa7c 10118#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10119 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10120 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10121
10122/* Pick the target format to use. */
10123
47926f60 10124const char *
e3bb37b5 10125i386_target_format (void)
252b5132 10126{
351f65ca
L		 10127 if (!strncmp (default_arch, "x86_64", 6))
10128 {
10129 update_code_flag (CODE_64BIT, 1);
10130 if (default_arch[6] == '\0')
7f56bc95 10131 x86_elf_abi = X86_64_ABI;
351f65ca 10132 else
7f56bc95 10133 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10134 }
3e73aa7c 10135 else if (!strcmp (default_arch, "i386"))
78f12dd3 10136 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10137 else if (!strcmp (default_arch, "iamcu"))
10138 {
10139 update_code_flag (CODE_32BIT, 1);
10140 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10141 {
10142 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10143 cpu_arch_name = "iamcu";
10144 cpu_sub_arch_name = NULL;
10145 cpu_arch_flags = iamcu_flags;
10146 cpu_arch_isa = PROCESSOR_IAMCU;
10147 cpu_arch_isa_flags = iamcu_flags;
10148 if (!cpu_arch_tune_set)
10149 {
10150 cpu_arch_tune = cpu_arch_isa;
10151 cpu_arch_tune_flags = cpu_arch_isa_flags;
10152 }
10153 }
10154 else
10155 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10156 cpu_arch_name);
10157 }
3e73aa7c 10158 else
2b5d6a91 10159 as_fatal (_("unknown architecture"));
89507696
JB		 10160
10161 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10162 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10163 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10164 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10165
252b5132
RH		 10166 switch (OUTPUT_FLAVOR)
10167 {
9384f2ff 10168#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10169 case bfd_target_aout_flavour:
47926f60 10170 return AOUT_TARGET_FORMAT;
4c63da97 10171#endif
9384f2ff
AM		 10172#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10173# if defined (TE_PE) || defined (TE_PEP)
10174 case bfd_target_coff_flavour:
167ad85b
TG		 10175 if (flag_code == CODE_64BIT)
10176 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10177 else
10178 return "pe-i386";
9384f2ff 10179# elif defined (TE_GO32)
0561d57c
JK		 10180 case bfd_target_coff_flavour:
10181 return "coff-go32";
9384f2ff 10182# else
252b5132
RH		 10183 case bfd_target_coff_flavour:
10184 return "coff-i386";
9384f2ff 10185# endif
4c63da97 10186#endif
3e73aa7c 10187#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10188 case bfd_target_elf_flavour:
3e73aa7c 10189 {
351f65ca
L		 10190 const char *format;
10191
10192 switch (x86_elf_abi)
4fa24527 10193 {
351f65ca
L		 10194 default:
10195 format = ELF_TARGET_FORMAT;
10196 break;
7f56bc95 10197 case X86_64_ABI:
351f65ca 10198 use_rela_relocations = 1;
4fa24527 10199 object_64bit = 1;
351f65ca
L		 10200 format = ELF_TARGET_FORMAT64;
10201 break;
7f56bc95 10202 case X86_64_X32_ABI:
4fa24527 10203 use_rela_relocations = 1;
351f65ca 10204 object_64bit = 1;
862be3fb 10205 disallow_64bit_reloc = 1;
351f65ca
L		 10206 format = ELF_TARGET_FORMAT32;
10207 break;
4fa24527 10208 }
3632d14b 10209 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10210 {
7f56bc95 10211 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10212 as_fatal (_("Intel L1OM is 64bit only"));
10213 return ELF_TARGET_L1OM_FORMAT;
10214 }
b49f93f6 10215 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10216 {
10217 if (x86_elf_abi != X86_64_ABI)
10218 as_fatal (_("Intel K1OM is 64bit only"));
10219 return ELF_TARGET_K1OM_FORMAT;
10220 }
81486035
L		 10221 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10222 {
10223 if (x86_elf_abi != I386_ABI)
10224 as_fatal (_("Intel MCU is 32bit only"));
10225 return ELF_TARGET_IAMCU_FORMAT;
10226 }
8a9036a4 10227 else
351f65ca 10228 return format;
3e73aa7c 10229 }
e57f8c65
TG		 10230#endif
10231#if defined (OBJ_MACH_O)
10232 case bfd_target_mach_o_flavour:
d382c579
TG		 10233 if (flag_code == CODE_64BIT)
10234 {
10235 use_rela_relocations = 1;
10236 object_64bit = 1;
10237 return "mach-o-x86-64";
10238 }
10239 else
10240 return "mach-o-i386";
4c63da97 10241#endif
252b5132
RH		 10242 default:
10243 abort ();
10244 return NULL;
10245 }
10246}
10247
47926f60 10248#endif /* OBJ_MAYBE_ more than one */
252b5132 10249\f
252b5132 10250symbolS *
7016a5d5 10251md_undefined_symbol (char *name)
252b5132 10252{
18dc2407
ILT		 10253 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10254 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10255 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10256 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10257 {
10258 if (!GOT_symbol)
10259 {
10260 if (symbol_find (name))
10261 as_bad (_("GOT already in symbol table"));
10262 GOT_symbol = symbol_new (name, undefined_section,
10263 (valueT) 0, &zero_address_frag);
10264 };
10265 return GOT_symbol;
10266 }
252b5132
RH		 10267 return 0;
10268}
10269
10270/* Round up a section size to the appropriate boundary. */
47926f60 10271
252b5132 10272valueT
7016a5d5 10273md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10274{
4c63da97
AM		 10275#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10276 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10277 {
10278 /* For a.out, force the section size to be aligned. If we don't do
10279 this, BFD will align it for us, but it will not write out the
10280 final bytes of the section. This may be a bug in BFD, but it is
10281 easier to fix it here since that is how the other a.out targets
10282 work. */
10283 int align;
10284
10285 align = bfd_get_section_alignment (stdoutput, segment);
10286 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10287 }
252b5132
RH		 10288#endif
10289
10290 return size;
10291}
10292
10293/* On the i386, PC-relative offsets are relative to the start of the
10294 next instruction. That is, the address of the offset, plus its
10295 size, since the offset is always the last part of the insn. */
10296
10297long
e3bb37b5 10298md_pcrel_from (fixS *fixP)
252b5132
RH		 10299{
10300 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10301}
10302
10303#ifndef I386COFF
10304
10305static void
e3bb37b5 10306s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10307{
29b0f896 10308 int temp;
252b5132 10309
8a75718c
JB		 10310#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10311 if (IS_ELF)
10312 obj_elf_section_change_hook ();
10313#endif
252b5132
RH		 10314 temp = get_absolute_expression ();
10315 subseg_set (bss_section, (subsegT) temp);
10316 demand_empty_rest_of_line ();
10317}
10318
10319#endif
10320
252b5132 10321void
e3bb37b5 10322i386_validate_fix (fixS *fixp)
252b5132
RH		 10323{
10324 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10325 {
23df1078
JH		 10326 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10327 {
4fa24527 10328 if (!object_64bit)
23df1078
JH		 10329 abort ();
10330 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10331 }
10332 else
10333 {
4fa24527 10334 if (!object_64bit)
d6ab8113
JB		 10335 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10336 else
10337 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10338 }
252b5132
RH		 10339 fixp->fx_subsy = 0;
10340 }
10341}
10342
252b5132 10343arelent *
7016a5d5 10344tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10345{
10346 arelent *rel;
10347 bfd_reloc_code_real_type code;
10348
10349 switch (fixp->fx_r_type)
10350 {
8ce3d284 10351#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10352 case BFD_RELOC_SIZE32:
10353 case BFD_RELOC_SIZE64:
10354 if (S_IS_DEFINED (fixp->fx_addsy)
10355 && !S_IS_EXTERNAL (fixp->fx_addsy))
10356 {
10357 /* Resolve size relocation against local symbol to size of
10358 the symbol plus addend. */
10359 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10360 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10361 && !fits_in_unsigned_long (value))
10362 as_bad_where (fixp->fx_file, fixp->fx_line,
10363 _("symbol size computation overflow"));
10364 fixp->fx_addsy = NULL;
10365 fixp->fx_subsy = NULL;
10366 md_apply_fix (fixp, (valueT *) &value, NULL);
10367 return NULL;
10368 }
8ce3d284 10369#endif
8fd4256d 10370
3e73aa7c
JH		 10371 case BFD_RELOC_X86_64_PLT32:
10372 case BFD_RELOC_X86_64_GOT32:
10373 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10374 case BFD_RELOC_386_PLT32:
10375 case BFD_RELOC_386_GOT32:
10376 case BFD_RELOC_386_GOTOFF:
10377 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10378 case BFD_RELOC_386_TLS_GD:
10379 case BFD_RELOC_386_TLS_LDM:
10380 case BFD_RELOC_386_TLS_LDO_32:
10381 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10382 case BFD_RELOC_386_TLS_IE:
10383 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10384 case BFD_RELOC_386_TLS_LE_32:
10385 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10386 case BFD_RELOC_386_TLS_GOTDESC:
10387 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10388 case BFD_RELOC_X86_64_TLSGD:
10389 case BFD_RELOC_X86_64_TLSLD:
10390 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10391 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10392 case BFD_RELOC_X86_64_GOTTPOFF:
10393 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10394 case BFD_RELOC_X86_64_TPOFF64:
10395 case BFD_RELOC_X86_64_GOTOFF64:
10396 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10397 case BFD_RELOC_X86_64_GOT64:
10398 case BFD_RELOC_X86_64_GOTPCREL64:
10399 case BFD_RELOC_X86_64_GOTPC64:
10400 case BFD_RELOC_X86_64_GOTPLT64:
10401 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10402 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10403 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10404 case BFD_RELOC_RVA:
10405 case BFD_RELOC_VTABLE_ENTRY:
10406 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10407#ifdef TE_PE
10408 case BFD_RELOC_32_SECREL:
10409#endif
252b5132
RH		 10410 code = fixp->fx_r_type;
10411 break;
dbbaec26
L		 10412 case BFD_RELOC_X86_64_32S:
10413 if (!fixp->fx_pcrel)
10414 {
10415 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10416 code = fixp->fx_r_type;
10417 break;
10418 }
252b5132 10419 default:
93382f6d 10420 if (fixp->fx_pcrel)
252b5132 10421 {
93382f6d
AM		 10422 switch (fixp->fx_size)
10423 {
10424 default:
b091f402
AM		 10425 as_bad_where (fixp->fx_file, fixp->fx_line,
10426 _("can not do %d byte pc-relative relocation"),
10427 fixp->fx_size);
93382f6d
AM		 10428 code = BFD_RELOC_32_PCREL;
10429 break;
10430 case 1: code = BFD_RELOC_8_PCREL; break;
10431 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10432 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10433#ifdef BFD64
10434 case 8: code = BFD_RELOC_64_PCREL; break;
10435#endif
93382f6d
AM		 10436 }
10437 }
10438 else
10439 {
10440 switch (fixp->fx_size)
10441 {
10442 default:
b091f402
AM		 10443 as_bad_where (fixp->fx_file, fixp->fx_line,
10444 _("can not do %d byte relocation"),
10445 fixp->fx_size);
93382f6d
AM		 10446 code = BFD_RELOC_32;
10447 break;
10448 case 1: code = BFD_RELOC_8; break;
10449 case 2: code = BFD_RELOC_16; break;
10450 case 4: code = BFD_RELOC_32; break;
937149dd 10451#ifdef BFD64
3e73aa7c 10452 case 8: code = BFD_RELOC_64; break;
937149dd 10453#endif
93382f6d 10454 }
252b5132
RH		 10455 }
10456 break;
10457 }
252b5132 10458
d182319b
JB		 10459 if ((code == BFD_RELOC_32
10460 || code == BFD_RELOC_32_PCREL
10461 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10462 && GOT_symbol
10463 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10464 {
4fa24527 10465 if (!object_64bit)
d6ab8113
JB		 10466 code = BFD_RELOC_386_GOTPC;
10467 else
10468 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10469 }
7b81dfbb
AJ		 10470 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10471 && GOT_symbol
10472 && fixp->fx_addsy == GOT_symbol)
10473 {
10474 code = BFD_RELOC_X86_64_GOTPC64;
10475 }
252b5132
RH		 10476
10477 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10478 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10479 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10480
10481 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10482
3e73aa7c
JH		 10483 if (!use_rela_relocations)
10484 {
10485 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10486 vtable entry to be used in the relocation's section offset. */
10487 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10488 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10489#if defined (OBJ_COFF) && defined (TE_PE)
10490 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10491 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10492 else
10493#endif
c6682705 10494 rel->addend = 0;
3e73aa7c
JH		 10495 }
10496 /* Use the rela in 64bit mode. */
252b5132 10497 else
3e73aa7c 10498 {
862be3fb
L		 10499 if (disallow_64bit_reloc)
10500 switch (code)
10501 {
862be3fb
L		 10502 case BFD_RELOC_X86_64_DTPOFF64:
10503 case BFD_RELOC_X86_64_TPOFF64:
10504 case BFD_RELOC_64_PCREL:
10505 case BFD_RELOC_X86_64_GOTOFF64:
10506 case BFD_RELOC_X86_64_GOT64:
10507 case BFD_RELOC_X86_64_GOTPCREL64:
10508 case BFD_RELOC_X86_64_GOTPC64:
10509 case BFD_RELOC_X86_64_GOTPLT64:
10510 case BFD_RELOC_X86_64_PLTOFF64:
10511 as_bad_where (fixp->fx_file, fixp->fx_line,
10512 _("cannot represent relocation type %s in x32 mode"),
10513 bfd_get_reloc_code_name (code));
10514 break;
10515 default:
10516 break;
10517 }
10518
062cd5e7
AS		 10519 if (!fixp->fx_pcrel)
10520 rel->addend = fixp->fx_offset;
10521 else
10522 switch (code)
10523 {
10524 case BFD_RELOC_X86_64_PLT32:
10525 case BFD_RELOC_X86_64_GOT32:
10526 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10527 case BFD_RELOC_X86_64_TLSGD:
10528 case BFD_RELOC_X86_64_TLSLD:
10529 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10530 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10531 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10532 rel->addend = fixp->fx_offset - fixp->fx_size;
10533 break;
10534 default:
10535 rel->addend = (section->vma
10536 - fixp->fx_size
10537 + fixp->fx_addnumber
10538 + md_pcrel_from (fixp));
10539 break;
10540 }
3e73aa7c
JH		 10541 }
10542
252b5132
RH		 10543 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10544 if (rel->howto == NULL)
10545 {
10546 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10547 _("cannot represent relocation type %s"),
252b5132
RH		 10548 bfd_get_reloc_code_name (code));
10549 /* Set howto to a garbage value so that we can keep going. */
10550 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10551 gas_assert (rel->howto != NULL);
252b5132
RH		 10552 }
10553
10554 return rel;
10555}
10556
ee86248c 10557#include "tc-i386-intel.c"
54cfded0 10558
a60de03c
JB		 10559void
10560tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10561{
a60de03c
JB		 10562 int saved_naked_reg;
10563 char saved_register_dot;
54cfded0 10564
a60de03c
JB		 10565 saved_naked_reg = allow_naked_reg;
10566 allow_naked_reg = 1;
10567 saved_register_dot = register_chars['.'];
10568 register_chars['.'] = '.';
10569 allow_pseudo_reg = 1;
10570 expression_and_evaluate (exp);
10571 allow_pseudo_reg = 0;
10572 register_chars['.'] = saved_register_dot;
10573 allow_naked_reg = saved_naked_reg;
10574
e96d56a1 10575 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10576 {
a60de03c
JB		 10577 if ((addressT) exp->X_add_number < i386_regtab_size)
10578 {
10579 exp->X_op = O_constant;
10580 exp->X_add_number = i386_regtab[exp->X_add_number]
10581 .dw2_regnum[flag_code >> 1];
10582 }
10583 else
10584 exp->X_op = O_illegal;
54cfded0 10585 }
54cfded0
AM		 10586}
10587
10588void
10589tc_x86_frame_initial_instructions (void)
10590{
a60de03c
JB		 10591 static unsigned int sp_regno[2];
10592
10593 if (!sp_regno[flag_code >> 1])
10594 {
10595 char *saved_input = input_line_pointer;
10596 char sp[][4] = {"esp", "rsp"};
10597 expressionS exp;
a4447b93 10598
a60de03c
JB		 10599 input_line_pointer = sp[flag_code >> 1];
10600 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10601 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10602 sp_regno[flag_code >> 1] = exp.X_add_number;
10603 input_line_pointer = saved_input;
10604 }
a4447b93 10605
61ff971f
L		 10606 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10607 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10608}
d2b2c203 10609
d7921315
L		 10610int
10611x86_dwarf2_addr_size (void)
10612{
10613#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10614 if (x86_elf_abi == X86_64_X32_ABI)
10615 return 4;
10616#endif
10617 return bfd_arch_bits_per_address (stdoutput) / 8;
10618}
10619
d2b2c203
DJ		 10620int
10621i386_elf_section_type (const char *str, size_t len)
10622{
10623 if (flag_code == CODE_64BIT
10624 && len == sizeof ("unwind") - 1
10625 && strncmp (str, "unwind", 6) == 0)
10626 return SHT_X86_64_UNWIND;
10627
10628 return -1;
10629}
bb41ade5 10630
ad5fec3b
EB		 10631#ifdef TE_SOLARIS
10632void
10633i386_solaris_fix_up_eh_frame (segT sec)
10634{
10635 if (flag_code == CODE_64BIT)
10636 elf_section_type (sec) = SHT_X86_64_UNWIND;
10637}
10638#endif
10639
bb41ade5
AM		 10640#ifdef TE_PE
10641void
10642tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10643{
91d6fa6a 10644 expressionS exp;
bb41ade5 10645
91d6fa6a
NC		 10646 exp.X_op = O_secrel;
10647 exp.X_add_symbol = symbol;
10648 exp.X_add_number = 0;
10649 emit_expr (&exp, size);
bb41ade5
AM		 10650}
10651#endif
3b22753a
L		 10652
10653#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10654/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10655
01e1a5bc 10656bfd_vma
3b22753a
L		 10657x86_64_section_letter (int letter, char **ptr_msg)
10658{
10659 if (flag_code == CODE_64BIT)
10660 {
10661 if (letter == 'l')
10662 return SHF_X86_64_LARGE;
10663
8f3bae45 10664 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10665 }
3b22753a 10666 else
8f3bae45 10667 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10668 return -1;
10669}
10670
01e1a5bc 10671bfd_vma
3b22753a
L		 10672x86_64_section_word (char *str, size_t len)
10673{
8620418b 10674 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10675 return SHF_X86_64_LARGE;
10676
10677 return -1;
10678}
10679
10680static void
10681handle_large_common (int small ATTRIBUTE_UNUSED)
10682{
10683 if (flag_code != CODE_64BIT)
10684 {
10685 s_comm_internal (0, elf_common_parse);
10686 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10687 }
10688 else
10689 {
10690 static segT lbss_section;
10691 asection *saved_com_section_ptr = elf_com_section_ptr;
10692 asection *saved_bss_section = bss_section;
10693
10694 if (lbss_section == NULL)
10695 {
10696 flagword applicable;
10697 segT seg = now_seg;
10698 subsegT subseg = now_subseg;
10699
10700 /* The .lbss section is for local .largecomm symbols. */
10701 lbss_section = subseg_new (".lbss", 0);
10702 applicable = bfd_applicable_section_flags (stdoutput);
10703 bfd_set_section_flags (stdoutput, lbss_section,
10704 applicable & SEC_ALLOC);
10705 seg_info (lbss_section)->bss = 1;
10706
10707 subseg_set (seg, subseg);
10708 }
10709
10710 elf_com_section_ptr = &_bfd_elf_large_com_section;
10711 bss_section = lbss_section;
10712
10713 s_comm_internal (0, elf_common_parse);
10714
10715 elf_com_section_ptr = saved_com_section_ptr;
10716 bss_section = saved_bss_section;
10717 }
10718}
10719#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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