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* gas/m68k/all.exp: Add support for fido.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
ccc9c027
L		 327/* If we have selected a cpu we are generating instructions for. */
328static int cpu_arch_tune_set = 0;
329
9103f4f4
L		 330/* Cpu we are generating instructions for. */
331static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332
333/* CPU feature flags of cpu we are generating instructions for. */
334static unsigned int cpu_arch_tune_flags = 0;
335
ccc9c027
L		 336/* CPU instruction set architecture used. */
337static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338
9103f4f4
L		 339/* CPU feature flags of instruction set architecture used. */
340static unsigned int cpu_arch_isa_flags = 0;
341
fddf5b5b
AM		 342/* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344static unsigned int no_cond_jump_promotion = 0;
345
29b0f896 346/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 347static symbolS *GOT_symbol;
29b0f896 348
a4447b93
RH		 349/* The dwarf2 return column, adjusted for 32 or 64 bit. */
350unsigned int x86_dwarf2_return_column;
351
352/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353int x86_cie_data_alignment;
354
252b5132 355/* Interface to relax_segment.
fddf5b5b
AM		 356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
252b5132 359
47926f60 360/* Types. */
93c2a809
AM		 361#define UNCOND_JUMP 0
362#define COND_JUMP 1
363#define COND_JUMP86 2
fddf5b5b 364
47926f60 365/* Sizes. */
252b5132
RH		 366#define CODE16 1
367#define SMALL 0
29b0f896 368#define SMALL16 (SMALL | CODE16)
252b5132 369#define BIG 2
29b0f896 370#define BIG16 (BIG | CODE16)
252b5132
RH		 371
372#ifndef INLINE
373#ifdef __GNUC__
374#define INLINE __inline__
375#else
376#define INLINE
377#endif
378#endif
379
fddf5b5b
AM		 380#define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382#define TYPE_FROM_RELAX_STATE(s) \
383 ((s) >> 2)
384#define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 386
387/* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
394
395const relax_typeS md_relax_table[] =
396{
24eab124
AM		 397 /* The fields are:
398 1) most positive reach of this state,
399 2) most negative reach of this state,
93c2a809 400 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 401 4) which index into the table to try if we can't fit into this one. */
252b5132 402
fddf5b5b 403 /* UNCOND_JUMP states. */
93c2a809
AM		 404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
252b5132 408 {0, 0, 4, 0},
93c2a809
AM		 409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 411 {0, 0, 2, 0},
412
93c2a809
AM		 413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
fddf5b5b 419 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 420 1 extra opcode byte, 2 displacement bytes. */
421 {0, 0, 3, 0},
422
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
428 {0, 0, 5, 0},
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
431 {0, 0, 4, 0}
252b5132
RH		 432};
433
9103f4f4
L		 434static const arch_entry cpu_arch[] =
435{
436 {"generic32", PROCESSOR_GENERIC32,
d32cad65 437 Cpu186|Cpu286|Cpu386},
9103f4f4 438 {"generic64", PROCESSOR_GENERIC64,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 442 0},
9103f4f4 443 {"i186", PROCESSOR_UNKNOWN,
d32cad65 444 Cpu186},
9103f4f4 445 {"i286", PROCESSOR_UNKNOWN,
d32cad65 446 Cpu186|Cpu286},
9103f4f4 447 {"i386", PROCESSOR_GENERIC32,
d32cad65 448 Cpu186|Cpu286|Cpu386},
9103f4f4 449 {"i486", PROCESSOR_I486,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 451 {"i586", PROCESSOR_PENTIUM,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 453 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 455 {"pentium", PROCESSOR_PENTIUM,
d32cad65 456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 459 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 463 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
d32cad65 467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
d32cad65 470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 472 {"yonah", PROCESSOR_CORE,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 475 {"core", PROCESSOR_CORE,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
478 {"merom", PROCESSOR_CORE2,
479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
480 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
481 {"core2", PROCESSOR_CORE2,
482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
483 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 484 {"k6", PROCESSOR_K6,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 486 {"k6_2", PROCESSOR_K6,
d32cad65 487 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 488 {"athlon", PROCESSOR_ATHLON,
d32cad65 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 490 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
491 {"sledgehammer", PROCESSOR_K8,
d32cad65 492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
494 {"opteron", PROCESSOR_K8,
d32cad65 495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 496 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
497 {"k8", PROCESSOR_K8,
d32cad65 498 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 499 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 500 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 501 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
502 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
503 |CpuABM},
9103f4f4
L		 504 {".mmx", PROCESSOR_UNKNOWN,
505 CpuMMX},
506 {".sse", PROCESSOR_UNKNOWN,
507 CpuMMX|CpuMMX2|CpuSSE},
508 {".sse2", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
510 {".sse3", PROCESSOR_UNKNOWN,
511 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 512 {".ssse3", PROCESSOR_UNKNOWN,
513 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 514 {".3dnow", PROCESSOR_UNKNOWN,
515 CpuMMX|Cpu3dnow},
516 {".3dnowa", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
518 {".padlock", PROCESSOR_UNKNOWN,
519 CpuPadLock},
520 {".pacifica", PROCESSOR_UNKNOWN,
521 CpuSVME},
522 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 523 CpuSVME},
524 {".sse4a", PROCESSOR_UNKNOWN,
525 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
526 {".abm", PROCESSOR_UNKNOWN,
527 CpuABM}
e413e4e9
AM		 528};
529
29b0f896
AM		 530const pseudo_typeS md_pseudo_table[] =
531{
532#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
533 {"align", s_align_bytes, 0},
534#else
535 {"align", s_align_ptwo, 0},
536#endif
537 {"arch", set_cpu_arch, 0},
538#ifndef I386COFF
539 {"bss", s_bss, 0},
540#endif
541 {"ffloat", float_cons, 'f'},
542 {"dfloat", float_cons, 'd'},
543 {"tfloat", float_cons, 'x'},
544 {"value", cons, 2},
d182319b 545 {"slong", signed_cons, 4},
29b0f896
AM		 546 {"noopt", s_ignore, 0},
547 {"optim", s_ignore, 0},
548 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
549 {"code16", set_code_flag, CODE_16BIT},
550 {"code32", set_code_flag, CODE_32BIT},
551 {"code64", set_code_flag, CODE_64BIT},
552 {"intel_syntax", set_intel_syntax, 1},
553 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 554#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
555 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 556#else
557 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
558 {"loc", dwarf2_directive_loc, 0},
559 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 560#endif
6482c264
NC		 561#ifdef TE_PE
562 {"secrel32", pe_directive_secrel, 0},
563#endif
29b0f896
AM		 564 {0, 0, 0}
565};
566
567/* For interface with expression (). */
568extern char *input_line_pointer;
569
570/* Hash table for instruction mnemonic lookup. */
571static struct hash_control *op_hash;
572
573/* Hash table for register lookup. */
574static struct hash_control *reg_hash;
575\f
252b5132
RH		 576void
577i386_align_code (fragP, count)
578 fragS *fragP;
579 int count;
580{
ce8a8b2f
AM		 581 /* Various efficient no-op patterns for aligning code labels.
582 Note: Don't try to assemble the instructions in the comments.
583 0L and 0w are not legal. */
252b5132
RH		 584 static const char f32_1[] =
585 {0x90}; /* nop */
586 static const char f32_2[] =
ccc9c027 587 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 588 static const char f32_3[] =
589 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
590 static const char f32_4[] =
591 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
592 static const char f32_5[] =
593 {0x90, /* nop */
594 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
595 static const char f32_6[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
597 static const char f32_7[] =
598 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
599 static const char f32_8[] =
600 {0x90, /* nop */
601 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
602 static const char f32_9[] =
603 {0x89,0xf6, /* movl %esi,%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_10[] =
606 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_11[] =
609 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_12[] =
612 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
613 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
614 static const char f32_13[] =
615 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
616 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
617 static const char f32_14[] =
618 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
619 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
620 static const char f32_15[] =
621 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 623 static const char f16_3[] =
624 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 625 static const char f16_4[] =
626 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
627 static const char f16_5[] =
628 {0x90, /* nop */
629 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
630 static const char f16_6[] =
631 {0x89,0xf6, /* mov %si,%si */
632 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
633 static const char f16_7[] =
634 {0x8d,0x74,0x00, /* lea 0(%si),%si */
635 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
636 static const char f16_8[] =
637 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
638 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
639 static const char *const f32_patt[] = {
640 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
641 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
642 };
643 static const char *const f16_patt[] = {
c3332e24 644 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 645 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
646 };
ccc9c027
L		 647 /* nopl (%[re]ax) */
648 static const char alt_3[] =
649 {0x0f,0x1f,0x00};
650 /* nopl 0(%[re]ax) */
651 static const char alt_4[] =
652 {0x0f,0x1f,0x40,0x00};
653 /* nopl 0(%[re]ax,%[re]ax,1) */
654 static const char alt_5[] =
655 {0x0f,0x1f,0x44,0x00,0x00};
656 /* nopw 0(%[re]ax,%[re]ax,1) */
657 static const char alt_6[] =
658 {0x66,0x0f,0x1f,0x44,0x00,0x00};
659 /* nopl 0L(%[re]ax) */
660 static const char alt_7[] =
661 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
662 /* nopl 0L(%[re]ax,%[re]ax,1) */
663 static const char alt_8[] =
664 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* nopw 0L(%[re]ax,%[re]ax,1) */
666 static const char alt_9[] =
667 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_10[] =
670 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
671 /* data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_11[] =
674 {0x66,
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
676 /* data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_12[] =
680 {0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 nopw %cs:0L(%[re]ax,%[re]ax,1) */
687 static const char alt_long_13[] =
688 {0x66,
689 0x66,
690 0x66,
691 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
692 /* data16
693 data16
694 data16
695 data16
696 nopw %cs:0L(%[re]ax,%[re]ax,1) */
697 static const char alt_long_14[] =
698 {0x66,
699 0x66,
700 0x66,
701 0x66,
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* data16
704 data16
705 data16
706 data16
707 data16
708 nopw %cs:0L(%[re]ax,%[re]ax,1) */
709 static const char alt_long_15[] =
710 {0x66,
711 0x66,
712 0x66,
713 0x66,
714 0x66,
715 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
716 /* nopl 0(%[re]ax,%[re]ax,1)
717 nopw 0(%[re]ax,%[re]ax,1) */
718 static const char alt_short_11[] =
719 {0x0f,0x1f,0x44,0x00,0x00,
720 0x66,0x0f,0x1f,0x44,0x00,0x00};
721 /* nopw 0(%[re]ax,%[re]ax,1)
722 nopw 0(%[re]ax,%[re]ax,1) */
723 static const char alt_short_12[] =
724 {0x66,0x0f,0x1f,0x44,0x00,0x00,
725 0x66,0x0f,0x1f,0x44,0x00,0x00};
726 /* nopw 0(%[re]ax,%[re]ax,1)
727 nopl 0L(%[re]ax) */
728 static const char alt_short_13[] =
729 {0x66,0x0f,0x1f,0x44,0x00,0x00,
730 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
731 /* nopl 0L(%[re]ax)
732 nopl 0L(%[re]ax) */
733 static const char alt_short_14[] =
734 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
735 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
736 /* nopl 0L(%[re]ax)
737 nopl 0L(%[re]ax,%[re]ax,1) */
738 static const char alt_short_15[] =
739 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
740 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
741 static const char *const alt_short_patt[] = {
742 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
743 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
744 alt_short_14, alt_short_15
745 };
746 static const char *const alt_long_patt[] = {
747 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
748 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
749 alt_long_14, alt_long_15
750 };
252b5132 751
33fef721
JH		 752 if (count <= 0 || count > 15)
753 return;
3e73aa7c 754
ccc9c027
L		 755 /* We need to decide which NOP sequence to use for 32bit and
756 64bit. When -mtune= is used:
757
758 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
759 f32_patt will be used.
050dfa73 760 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 761 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 762 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 763 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 764 and PROCESSOR_GENERIC64, alt_short_patt will be used.
765
766 When -mtune= isn't used, alt_short_patt will be used if
767 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
768
769 When -march= or .arch is used, we can't use anything beyond
770 cpu_arch_isa_flags. */
771
772 if (flag_code == CODE_16BIT)
773 {
774 memcpy (fragP->fr_literal + fragP->fr_fix,
775 f16_patt[count - 1], count);
776 if (count > 8)
777 /* Adjust jump offset. */
778 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
779 }
780 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 781 {
33fef721
JH		 782 int i;
783 int nnops = (count + 3) / 4;
784 int len = count / nnops;
785 int remains = count - nnops * len;
786 int pos = 0;
787
ccc9c027
L		 788 /* The recommended way to pad 64bit code is to use NOPs preceded
789 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 790 for (i = 0; i < remains; i++)
252b5132 791 {
33fef721
JH		 792 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
793 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
794 pos += len + 1;
795 }
796 for (; i < nnops; i++)
797 {
798 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
799 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
800 pos += len;
252b5132 801 }
252b5132 802 }
33fef721 803 else
ccc9c027
L		 804 {
805 const char *const *patt = NULL;
806
807 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
808 {
809 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
810 switch (cpu_arch_tune)
811 {
812 case PROCESSOR_UNKNOWN:
813 /* We use cpu_arch_isa_flags to check if we SHOULD
814 optimize for Cpu686. */
815 if ((cpu_arch_isa_flags & Cpu686) != 0)
816 patt = alt_short_patt;
817 else
818 patt = f32_patt;
819 break;
ef05d495 820 case PROCESSOR_CORE2:
ccc9c027
L		 821 patt = alt_long_patt;
822 break;
823 case PROCESSOR_PENTIUMPRO:
824 case PROCESSOR_PENTIUM4:
825 case PROCESSOR_NOCONA:
ef05d495 826 case PROCESSOR_CORE:
ccc9c027
L		 827 case PROCESSOR_K6:
828 case PROCESSOR_ATHLON:
829 case PROCESSOR_K8:
830 case PROCESSOR_GENERIC64:
050dfa73 831 case PROCESSOR_AMDFAM10:
ccc9c027
L		 832 patt = alt_short_patt;
833 break;
834 case PROCESSOR_I486:
835 case PROCESSOR_PENTIUM:
836 case PROCESSOR_GENERIC32:
837 patt = f32_patt;
838 break;
839 }
840 }
841 else
842 {
843 switch (cpu_arch_tune)
844 {
845 case PROCESSOR_UNKNOWN:
846 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
847 PROCESSOR_UNKNOWN. */
848 abort ();
849 break;
850
851 case PROCESSOR_I486:
852 case PROCESSOR_PENTIUM:
853 case PROCESSOR_PENTIUMPRO:
854 case PROCESSOR_PENTIUM4:
855 case PROCESSOR_NOCONA:
ef05d495 856 case PROCESSOR_CORE:
ccc9c027
L		 857 case PROCESSOR_K6:
858 case PROCESSOR_ATHLON:
859 case PROCESSOR_K8:
050dfa73 860 case PROCESSOR_AMDFAM10:
ccc9c027
L		 861 case PROCESSOR_GENERIC32:
862 /* We use cpu_arch_isa_flags to check if we CAN optimize
863 for Cpu686. */
864 if ((cpu_arch_isa_flags & Cpu686) != 0)
865 patt = alt_short_patt;
866 else
867 patt = f32_patt;
868 break;
ef05d495 869 case PROCESSOR_CORE2:
ccc9c027
L		 870 if ((cpu_arch_isa_flags & Cpu686) != 0)
871 patt = alt_long_patt;
872 else
873 patt = f32_patt;
874 break;
875 case PROCESSOR_GENERIC64:
876 patt = alt_short_patt;
877 break;
878 }
879 }
880
33fef721 881 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 882 patt[count - 1], count);
883 }
33fef721 884 fragP->fr_var = count;
252b5132
RH		 885}
886
252b5132
RH		 887static INLINE unsigned int
888mode_from_disp_size (t)
889 unsigned int t;
890{
3e73aa7c 891 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 892}
893
894static INLINE int
895fits_in_signed_byte (num)
847f7ad4 896 offsetT num;
252b5132
RH		 897{
898 return (num >= -128) && (num <= 127);
47926f60 899}
252b5132
RH		 900
901static INLINE int
902fits_in_unsigned_byte (num)
847f7ad4 903 offsetT num;
252b5132
RH		 904{
905 return (num & 0xff) == num;
47926f60 906}
252b5132
RH		 907
908static INLINE int
909fits_in_unsigned_word (num)
847f7ad4 910 offsetT num;
252b5132
RH		 911{
912 return (num & 0xffff) == num;
47926f60 913}
252b5132
RH		 914
915static INLINE int
916fits_in_signed_word (num)
847f7ad4 917 offsetT num;
252b5132
RH		 918{
919 return (-32768 <= num) && (num <= 32767);
47926f60 920}
2a962e6d 921
3e73aa7c
JH		 922static INLINE int
923fits_in_signed_long (num)
924 offsetT num ATTRIBUTE_UNUSED;
925{
926#ifndef BFD64
927 return 1;
928#else
929 return (!(((offsetT) -1 << 31) & num)
930 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
931#endif
932} /* fits_in_signed_long() */
2a962e6d 933
3e73aa7c
JH		 934static INLINE int
935fits_in_unsigned_long (num)
936 offsetT num ATTRIBUTE_UNUSED;
937{
938#ifndef BFD64
939 return 1;
940#else
941 return (num & (((offsetT) 2 << 31) - 1)) == num;
942#endif
943} /* fits_in_unsigned_long() */
252b5132
RH		 944
945static int
946smallest_imm_type (num)
847f7ad4 947 offsetT num;
252b5132 948{
d32cad65 949 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 950 {
951 /* This code is disabled on the 486 because all the Imm1 forms
952 in the opcode table are slower on the i486. They're the
953 versions with the implicitly specified single-position
954 displacement, which has another syntax if you really want to
955 use that form. */
956 if (num == 1)
3e73aa7c 957 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 958 }
252b5132 959 return (fits_in_signed_byte (num)
3e73aa7c 960 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 961 : fits_in_unsigned_byte (num)
3e73aa7c 962 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 963 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 964 ? (Imm16 | Imm32 | Imm32S | Imm64)
965 : fits_in_signed_long (num)
966 ? (Imm32 | Imm32S | Imm64)
967 : fits_in_unsigned_long (num)
968 ? (Imm32 | Imm64)
969 : Imm64);
47926f60 970}
252b5132 971
847f7ad4
AM		 972static offsetT
973offset_in_range (val, size)
974 offsetT val;
975 int size;
976{
508866be 977 addressT mask;
ba2adb93 978
847f7ad4
AM		 979 switch (size)
980 {
508866be
L		 981 case 1: mask = ((addressT) 1 << 8) - 1; break;
982 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 983 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 984#ifdef BFD64
985 case 8: mask = ((addressT) 2 << 63) - 1; break;
986#endif
47926f60 987 default: abort ();
847f7ad4
AM		 988 }
989
ba2adb93 990 /* If BFD64, sign extend val. */
3e73aa7c
JH		 991 if (!use_rela_relocations)
992 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
993 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 994
47926f60 995 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 996 {
997 char buf1[40], buf2[40];
998
999 sprint_value (buf1, val);
1000 sprint_value (buf2, val & mask);
1001 as_warn (_("%s shortened to %s"), buf1, buf2);
1002 }
1003 return val & mask;
1004}
1005
252b5132
RH		 1006/* Returns 0 if attempting to add a prefix where one from the same
1007 class already exists, 1 if non rep/repne added, 2 if rep/repne
1008 added. */
1009static int
1010add_prefix (prefix)
1011 unsigned int prefix;
1012{
1013 int ret = 1;
b1905489 1014 unsigned int q;
252b5132 1015
29b0f896
AM		 1016 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1017 && flag_code == CODE_64BIT)
b1905489
JB		 1018 {
1019 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1020 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1021 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1022 ret = 0;
1023 q = REX_PREFIX;
1024 }
3e73aa7c 1025 else
b1905489
JB		 1026 {
1027 switch (prefix)
1028 {
1029 default:
1030 abort ();
1031
1032 case CS_PREFIX_OPCODE:
1033 case DS_PREFIX_OPCODE:
1034 case ES_PREFIX_OPCODE:
1035 case FS_PREFIX_OPCODE:
1036 case GS_PREFIX_OPCODE:
1037 case SS_PREFIX_OPCODE:
1038 q = SEG_PREFIX;
1039 break;
1040
1041 case REPNE_PREFIX_OPCODE:
1042 case REPE_PREFIX_OPCODE:
1043 ret = 2;
1044 /* fall thru */
1045 case LOCK_PREFIX_OPCODE:
1046 q = LOCKREP_PREFIX;
1047 break;
1048
1049 case FWAIT_OPCODE:
1050 q = WAIT_PREFIX;
1051 break;
1052
1053 case ADDR_PREFIX_OPCODE:
1054 q = ADDR_PREFIX;
1055 break;
1056
1057 case DATA_PREFIX_OPCODE:
1058 q = DATA_PREFIX;
1059 break;
1060 }
1061 if (i.prefix[q] != 0)
1062 ret = 0;
1063 }
252b5132 1064
b1905489 1065 if (ret)
252b5132 1066 {
b1905489
JB		 1067 if (!i.prefix[q])
1068 ++i.prefixes;
1069 i.prefix[q] |= prefix;
252b5132 1070 }
b1905489
JB		 1071 else
1072 as_bad (_("same type of prefix used twice"));
252b5132 1073
252b5132
RH		 1074 return ret;
1075}
1076
1077static void
3e73aa7c 1078set_code_flag (value)
e5cb08ac 1079 int value;
eecb386c 1080{
3e73aa7c
JH		 1081 flag_code = value;
1082 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1083 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1084 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1085 {
1086 as_bad (_("64bit mode not supported on this CPU."));
1087 }
1088 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1089 {
1090 as_bad (_("32bit mode not supported on this CPU."));
1091 }
eecb386c
AM		 1092 stackop_size = '\0';
1093}
1094
1095static void
3e73aa7c
JH		 1096set_16bit_gcc_code_flag (new_code_flag)
1097 int new_code_flag;
252b5132 1098{
3e73aa7c
JH		 1099 flag_code = new_code_flag;
1100 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1101 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1102 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1103}
1104
1105static void
1106set_intel_syntax (syntax_flag)
eecb386c 1107 int syntax_flag;
252b5132
RH		 1108{
1109 /* Find out if register prefixing is specified. */
1110 int ask_naked_reg = 0;
1111
1112 SKIP_WHITESPACE ();
29b0f896 1113 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1114 {
1115 char *string = input_line_pointer;
1116 int e = get_symbol_end ();
1117
47926f60 1118 if (strcmp (string, "prefix") == 0)
252b5132 1119 ask_naked_reg = 1;
47926f60 1120 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1121 ask_naked_reg = -1;
1122 else
d0b47220 1123 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1124 *input_line_pointer = e;
1125 }
1126 demand_empty_rest_of_line ();
c3332e24 1127
252b5132
RH		 1128 intel_syntax = syntax_flag;
1129
1130 if (ask_naked_reg == 0)
f86103b7
AM		 1131 allow_naked_reg = (intel_syntax
1132 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1133 else
1134 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1135
1136 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1137 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1138}
1139
e413e4e9
AM		 1140static void
1141set_cpu_arch (dummy)
47926f60 1142 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1143{
47926f60 1144 SKIP_WHITESPACE ();
e413e4e9 1145
29b0f896 1146 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1147 {
1148 char *string = input_line_pointer;
1149 int e = get_symbol_end ();
9103f4f4 1150 unsigned int i;
e413e4e9 1151
9103f4f4 1152 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1153 {
1154 if (strcmp (string, cpu_arch[i].name) == 0)
1155 {
5c6af06e
JB		 1156 if (*string != '.')
1157 {
1158 cpu_arch_name = cpu_arch[i].name;
1159 cpu_sub_arch_name = NULL;
1160 cpu_arch_flags = (cpu_arch[i].flags
1161 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1162 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1163 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1164 if (!cpu_arch_tune_set)
1165 {
1166 cpu_arch_tune = cpu_arch_isa;
1167 cpu_arch_tune_flags = cpu_arch_isa_flags;
1168 }
5c6af06e
JB		 1169 break;
1170 }
1171 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1172 {
1173 cpu_sub_arch_name = cpu_arch[i].name;
1174 cpu_arch_flags |= cpu_arch[i].flags;
1175 }
1176 *input_line_pointer = e;
1177 demand_empty_rest_of_line ();
1178 return;
e413e4e9
AM		 1179 }
1180 }
9103f4f4 1181 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1182 as_bad (_("no such architecture: `%s'"), string);
1183
1184 *input_line_pointer = e;
1185 }
1186 else
1187 as_bad (_("missing cpu architecture"));
1188
fddf5b5b
AM		 1189 no_cond_jump_promotion = 0;
1190 if (*input_line_pointer == ','
29b0f896 1191 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1192 {
1193 char *string = ++input_line_pointer;
1194 int e = get_symbol_end ();
1195
1196 if (strcmp (string, "nojumps") == 0)
1197 no_cond_jump_promotion = 1;
1198 else if (strcmp (string, "jumps") == 0)
1199 ;
1200 else
1201 as_bad (_("no such architecture modifier: `%s'"), string);
1202
1203 *input_line_pointer = e;
1204 }
1205
e413e4e9
AM		 1206 demand_empty_rest_of_line ();
1207}
1208
b9d79e03
JH		 1209unsigned long
1210i386_mach ()
1211{
1212 if (!strcmp (default_arch, "x86_64"))
1213 return bfd_mach_x86_64;
1214 else if (!strcmp (default_arch, "i386"))
1215 return bfd_mach_i386_i386;
1216 else
1217 as_fatal (_("Unknown architecture"));
1218}
b9d79e03 1219\f
252b5132
RH		 1220void
1221md_begin ()
1222{
1223 const char *hash_err;
1224
47926f60 1225 /* Initialize op_hash hash table. */
252b5132
RH		 1226 op_hash = hash_new ();
1227
1228 {
29b0f896
AM		 1229 const template *optab;
1230 templates *core_optab;
252b5132 1231
47926f60
KH		 1232 /* Setup for loop. */
1233 optab = i386_optab;
252b5132
RH		 1234 core_optab = (templates *) xmalloc (sizeof (templates));
1235 core_optab->start = optab;
1236
1237 while (1)
1238 {
1239 ++optab;
1240 if (optab->name == NULL
1241 || strcmp (optab->name, (optab - 1)->name) != 0)
1242 {
1243 /* different name --> ship out current template list;
47926f60 1244 add to hash table; & begin anew. */
252b5132
RH		 1245 core_optab->end = optab;
1246 hash_err = hash_insert (op_hash,
1247 (optab - 1)->name,
1248 (PTR) core_optab);
1249 if (hash_err)
1250 {
252b5132
RH		 1251 as_fatal (_("Internal Error: Can't hash %s: %s"),
1252 (optab - 1)->name,
1253 hash_err);
1254 }
1255 if (optab->name == NULL)
1256 break;
1257 core_optab = (templates *) xmalloc (sizeof (templates));
1258 core_optab->start = optab;
1259 }
1260 }
1261 }
1262
47926f60 1263 /* Initialize reg_hash hash table. */
252b5132
RH		 1264 reg_hash = hash_new ();
1265 {
29b0f896 1266 const reg_entry *regtab;
252b5132
RH		 1267
1268 for (regtab = i386_regtab;
1269 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1270 regtab++)
1271 {
1272 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1273 if (hash_err)
3e73aa7c
JH		 1274 as_fatal (_("Internal Error: Can't hash %s: %s"),
1275 regtab->reg_name,
1276 hash_err);
252b5132
RH		 1277 }
1278 }
1279
47926f60 1280 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1281 {
29b0f896
AM		 1282 int c;
1283 char *p;
252b5132
RH		 1284
1285 for (c = 0; c < 256; c++)
1286 {
3882b010 1287 if (ISDIGIT (c))
252b5132
RH		 1288 {
1289 digit_chars[c] = c;
1290 mnemonic_chars[c] = c;
1291 register_chars[c] = c;
1292 operand_chars[c] = c;
1293 }
3882b010 1294 else if (ISLOWER (c))
252b5132
RH		 1295 {
1296 mnemonic_chars[c] = c;
1297 register_chars[c] = c;
1298 operand_chars[c] = c;
1299 }
3882b010 1300 else if (ISUPPER (c))
252b5132 1301 {
3882b010 1302 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1303 register_chars[c] = mnemonic_chars[c];
1304 operand_chars[c] = c;
1305 }
1306
3882b010 1307 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1308 identifier_chars[c] = c;
1309 else if (c >= 128)
1310 {
1311 identifier_chars[c] = c;
1312 operand_chars[c] = c;
1313 }
1314 }
1315
1316#ifdef LEX_AT
1317 identifier_chars['@'] = '@';
32137342
NC		 1318#endif
1319#ifdef LEX_QM
1320 identifier_chars['?'] = '?';
1321 operand_chars['?'] = '?';
252b5132 1322#endif
252b5132 1323 digit_chars['-'] = '-';
791fe849 1324 mnemonic_chars['-'] = '-';
252b5132
RH		 1325 identifier_chars['_'] = '_';
1326 identifier_chars['.'] = '.';
1327
1328 for (p = operand_special_chars; *p != '\0'; p++)
1329 operand_chars[(unsigned char) *p] = *p;
1330 }
1331
1332#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1333 if (IS_ELF)
252b5132
RH		 1334 {
1335 record_alignment (text_section, 2);
1336 record_alignment (data_section, 2);
1337 record_alignment (bss_section, 2);
1338 }
1339#endif
a4447b93
RH		 1340
1341 if (flag_code == CODE_64BIT)
1342 {
1343 x86_dwarf2_return_column = 16;
1344 x86_cie_data_alignment = -8;
1345 }
1346 else
1347 {
1348 x86_dwarf2_return_column = 8;
1349 x86_cie_data_alignment = -4;
1350 }
252b5132
RH		 1351}
1352
1353void
1354i386_print_statistics (file)
1355 FILE *file;
1356{
1357 hash_print_statistics (file, "i386 opcode", op_hash);
1358 hash_print_statistics (file, "i386 register", reg_hash);
1359}
1360\f
252b5132
RH		 1361#ifdef DEBUG386
1362
ce8a8b2f 1363/* Debugging routines for md_assemble. */
252b5132
RH		 1364static void pi PARAMS ((char *, i386_insn *));
1365static void pte PARAMS ((template *));
1366static void pt PARAMS ((unsigned int));
1367static void pe PARAMS ((expressionS *));
1368static void ps PARAMS ((symbolS *));
1369
1370static void
1371pi (line, x)
1372 char *line;
1373 i386_insn *x;
1374{
09f131f2 1375 unsigned int i;
252b5132
RH		 1376
1377 fprintf (stdout, "%s: template ", line);
1378 pte (&x->tm);
09f131f2
JH		 1379 fprintf (stdout, " address: base %s index %s scale %x\n",
1380 x->base_reg ? x->base_reg->reg_name : "none",
1381 x->index_reg ? x->index_reg->reg_name : "none",
1382 x->log2_scale_factor);
1383 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1384 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1385 fprintf (stdout, " sib: base %x index %x scale %x\n",
1386 x->sib.base, x->sib.index, x->sib.scale);
1387 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1388 (x->rex & REX_MODE64) != 0,
1389 (x->rex & REX_EXTX) != 0,
1390 (x->rex & REX_EXTY) != 0,
1391 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1392 for (i = 0; i < x->operands; i++)
1393 {
1394 fprintf (stdout, " #%d: ", i + 1);
1395 pt (x->types[i]);
1396 fprintf (stdout, "\n");
1397 if (x->types[i]
3f4438ab 1398 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1399 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1400 if (x->types[i] & Imm)
520dc8e8 1401 pe (x->op[i].imms);
252b5132 1402 if (x->types[i] & Disp)
520dc8e8 1403 pe (x->op[i].disps);
252b5132
RH		 1404 }
1405}
1406
1407static void
1408pte (t)
1409 template *t;
1410{
09f131f2 1411 unsigned int i;
252b5132 1412 fprintf (stdout, " %d operands ", t->operands);
47926f60 1413 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1414 if (t->extension_opcode != None)
1415 fprintf (stdout, "ext %x ", t->extension_opcode);
1416 if (t->opcode_modifier & D)
1417 fprintf (stdout, "D");
1418 if (t->opcode_modifier & W)
1419 fprintf (stdout, "W");
1420 fprintf (stdout, "\n");
1421 for (i = 0; i < t->operands; i++)
1422 {
1423 fprintf (stdout, " #%d type ", i + 1);
1424 pt (t->operand_types[i]);
1425 fprintf (stdout, "\n");
1426 }
1427}
1428
1429static void
1430pe (e)
1431 expressionS *e;
1432{
24eab124 1433 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1434 fprintf (stdout, " add_number %ld (%lx)\n",
1435 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1436 if (e->X_add_symbol)
1437 {
1438 fprintf (stdout, " add_symbol ");
1439 ps (e->X_add_symbol);
1440 fprintf (stdout, "\n");
1441 }
1442 if (e->X_op_symbol)
1443 {
1444 fprintf (stdout, " op_symbol ");
1445 ps (e->X_op_symbol);
1446 fprintf (stdout, "\n");
1447 }
1448}
1449
1450static void
1451ps (s)
1452 symbolS *s;
1453{
1454 fprintf (stdout, "%s type %s%s",
1455 S_GET_NAME (s),
1456 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1457 segment_name (S_GET_SEGMENT (s)));
1458}
1459
7b81dfbb 1460static struct type_name
252b5132
RH		 1461 {
1462 unsigned int mask;
1463 char *tname;
1464 }
7b81dfbb 1465const type_names[] =
252b5132
RH		 1466{
1467 { Reg8, "r8" },
1468 { Reg16, "r16" },
1469 { Reg32, "r32" },
09f131f2 1470 { Reg64, "r64" },
252b5132
RH		 1471 { Imm8, "i8" },
1472 { Imm8S, "i8s" },
1473 { Imm16, "i16" },
1474 { Imm32, "i32" },
09f131f2
JH		 1475 { Imm32S, "i32s" },
1476 { Imm64, "i64" },
252b5132
RH		 1477 { Imm1, "i1" },
1478 { BaseIndex, "BaseIndex" },
1479 { Disp8, "d8" },
1480 { Disp16, "d16" },
1481 { Disp32, "d32" },
09f131f2
JH		 1482 { Disp32S, "d32s" },
1483 { Disp64, "d64" },
252b5132
RH		 1484 { InOutPortReg, "InOutPortReg" },
1485 { ShiftCount, "ShiftCount" },
1486 { Control, "control reg" },
1487 { Test, "test reg" },
1488 { Debug, "debug reg" },
1489 { FloatReg, "FReg" },
1490 { FloatAcc, "FAcc" },
1491 { SReg2, "SReg2" },
1492 { SReg3, "SReg3" },
1493 { Acc, "Acc" },
1494 { JumpAbsolute, "Jump Absolute" },
1495 { RegMMX, "rMMX" },
3f4438ab 1496 { RegXMM, "rXMM" },
252b5132
RH		 1497 { EsSeg, "es" },
1498 { 0, "" }
1499};
1500
1501static void
1502pt (t)
1503 unsigned int t;
1504{
29b0f896 1505 const struct type_name *ty;
252b5132 1506
09f131f2
JH		 1507 for (ty = type_names; ty->mask; ty++)
1508 if (t & ty->mask)
1509 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1510 fflush (stdout);
1511}
1512
1513#endif /* DEBUG386 */
1514\f
252b5132 1515static bfd_reloc_code_real_type
3956db08 1516reloc (unsigned int size,
64e74474
AM		 1517 int pcrel,
1518 int sign,
1519 bfd_reloc_code_real_type other)
252b5132 1520{
47926f60 1521 if (other != NO_RELOC)
3956db08
JB		 1522 {
1523 reloc_howto_type *reloc;
1524
1525 if (size == 8)
1526 switch (other)
1527 {
64e74474
AM		 1528 case BFD_RELOC_X86_64_GOT32:
1529 return BFD_RELOC_X86_64_GOT64;
1530 break;
1531 case BFD_RELOC_X86_64_PLTOFF64:
1532 return BFD_RELOC_X86_64_PLTOFF64;
1533 break;
1534 case BFD_RELOC_X86_64_GOTPC32:
1535 other = BFD_RELOC_X86_64_GOTPC64;
1536 break;
1537 case BFD_RELOC_X86_64_GOTPCREL:
1538 other = BFD_RELOC_X86_64_GOTPCREL64;
1539 break;
1540 case BFD_RELOC_X86_64_TPOFF32:
1541 other = BFD_RELOC_X86_64_TPOFF64;
1542 break;
1543 case BFD_RELOC_X86_64_DTPOFF32:
1544 other = BFD_RELOC_X86_64_DTPOFF64;
1545 break;
1546 default:
1547 break;
3956db08 1548 }
e05278af
JB		 1549
1550 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1551 if (size == 4 && flag_code != CODE_64BIT)
1552 sign = -1;
1553
3956db08
JB		 1554 reloc = bfd_reloc_type_lookup (stdoutput, other);
1555 if (!reloc)
1556 as_bad (_("unknown relocation (%u)"), other);
1557 else if (size != bfd_get_reloc_size (reloc))
1558 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1559 bfd_get_reloc_size (reloc),
1560 size);
1561 else if (pcrel && !reloc->pc_relative)
1562 as_bad (_("non-pc-relative relocation for pc-relative field"));
1563 else if ((reloc->complain_on_overflow == complain_overflow_signed
1564 && !sign)
1565 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1566 && sign > 0))
3956db08
JB		 1567 as_bad (_("relocated field and relocation type differ in signedness"));
1568 else
1569 return other;
1570 return NO_RELOC;
1571 }
252b5132
RH		 1572
1573 if (pcrel)
1574 {
3e73aa7c 1575 if (!sign)
3956db08 1576 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1577 switch (size)
1578 {
1579 case 1: return BFD_RELOC_8_PCREL;
1580 case 2: return BFD_RELOC_16_PCREL;
1581 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1582 case 8: return BFD_RELOC_64_PCREL;
252b5132 1583 }
3956db08 1584 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1585 }
1586 else
1587 {
3956db08 1588 if (sign > 0)
e5cb08ac 1589 switch (size)
3e73aa7c
JH		 1590 {
1591 case 4: return BFD_RELOC_X86_64_32S;
1592 }
1593 else
1594 switch (size)
1595 {
1596 case 1: return BFD_RELOC_8;
1597 case 2: return BFD_RELOC_16;
1598 case 4: return BFD_RELOC_32;
1599 case 8: return BFD_RELOC_64;
1600 }
3956db08
JB		 1601 as_bad (_("cannot do %s %u byte relocation"),
1602 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1603 }
1604
bfb32b52 1605 abort ();
252b5132
RH		 1606 return BFD_RELOC_NONE;
1607}
1608
47926f60
KH		 1609/* Here we decide which fixups can be adjusted to make them relative to
1610 the beginning of the section instead of the symbol. Basically we need
1611 to make sure that the dynamic relocations are done correctly, so in
1612 some cases we force the original symbol to be used. */
1613
252b5132 1614int
c0c949c7 1615tc_i386_fix_adjustable (fixP)
31312f95 1616 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1617{
6d249963 1618#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1619 if (!IS_ELF)
31312f95
AM		 1620 return 1;
1621
a161fe53
AM		 1622 /* Don't adjust pc-relative references to merge sections in 64-bit
1623 mode. */
1624 if (use_rela_relocations
1625 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1626 && fixP->fx_pcrel)
252b5132 1627 return 0;
31312f95 1628
8d01d9a9
AJ		 1629 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1630 and changed later by validate_fix. */
1631 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1632 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1633 return 0;
1634
ce8a8b2f 1635 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1636 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1637 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1638 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1639 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1647 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1648 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1649 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1650 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1651 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1652 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1653 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1654 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1655 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1656 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1657 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1658 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1659 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1660 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1661 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1662 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1663 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1664 return 0;
31312f95 1665#endif
252b5132
RH		 1666 return 1;
1667}
252b5132 1668
29b0f896 1669static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1670
1671static int
252b5132 1672intel_float_operand (mnemonic)
29b0f896 1673 const char *mnemonic;
252b5132 1674{
9306ca4a
JB		 1675 /* Note that the value returned is meaningful only for opcodes with (memory)
1676 operands, hence the code here is free to improperly handle opcodes that
1677 have no operands (for better performance and smaller code). */
1678
1679 if (mnemonic[0] != 'f')
1680 return 0; /* non-math */
1681
1682 switch (mnemonic[1])
1683 {
1684 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1685 the fs segment override prefix not currently handled because no
1686 call path can make opcodes without operands get here */
1687 case 'i':
1688 return 2 /* integer op */;
1689 case 'l':
1690 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1691 return 3; /* fldcw/fldenv */
1692 break;
1693 case 'n':
1694 if (mnemonic[2] != 'o' /* fnop */)
1695 return 3; /* non-waiting control op */
1696 break;
1697 case 'r':
1698 if (mnemonic[2] == 's')
1699 return 3; /* frstor/frstpm */
1700 break;
1701 case 's':
1702 if (mnemonic[2] == 'a')
1703 return 3; /* fsave */
1704 if (mnemonic[2] == 't')
1705 {
1706 switch (mnemonic[3])
1707 {
1708 case 'c': /* fstcw */
1709 case 'd': /* fstdw */
1710 case 'e': /* fstenv */
1711 case 's': /* fsts[gw] */
1712 return 3;
1713 }
1714 }
1715 break;
1716 case 'x':
1717 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1718 return 0; /* fxsave/fxrstor are not really math ops */
1719 break;
1720 }
252b5132 1721
9306ca4a 1722 return 1;
252b5132
RH		 1723}
1724
1725/* This is the guts of the machine-dependent assembler. LINE points to a
1726 machine dependent instruction. This function is supposed to emit
1727 the frags/bytes it assembles to. */
1728
1729void
1730md_assemble (line)
1731 char *line;
1732{
252b5132 1733 int j;
252b5132
RH		 1734 char mnemonic[MAX_MNEM_SIZE];
1735
47926f60 1736 /* Initialize globals. */
252b5132
RH		 1737 memset (&i, '\0', sizeof (i));
1738 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1739 i.reloc[j] = NO_RELOC;
252b5132
RH		 1740 memset (disp_expressions, '\0', sizeof (disp_expressions));
1741 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1742 save_stack_p = save_stack;
252b5132
RH		 1743
1744 /* First parse an instruction mnemonic & call i386_operand for the operands.
1745 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1746 start of a (possibly prefixed) mnemonic. */
252b5132 1747
29b0f896
AM		 1748 line = parse_insn (line, mnemonic);
1749 if (line == NULL)
1750 return;
252b5132 1751
29b0f896
AM		 1752 line = parse_operands (line, mnemonic);
1753 if (line == NULL)
1754 return;
252b5132 1755
050dfa73
MM		 1756 /* The order of the immediates should be reversed
1757 for 2 immediates extrq and insertq instructions */
1758 if ((i.imm_operands == 2) &&
1759 ((strcmp (mnemonic, "extrq") == 0)
1760 || (strcmp (mnemonic, "insertq") == 0)))
1761 {
1762 swap_imm_operands ();
1763 /* "extrq" and insertq" are the only two instructions whose operands
1764 have to be reversed even though they have two immediate operands.
1765 */
1766 if (intel_syntax)
1767 swap_operands ();
1768 }
1769
29b0f896
AM		 1770 /* Now we've parsed the mnemonic into a set of templates, and have the
1771 operands at hand. */
1772
1773 /* All intel opcodes have reversed operands except for "bound" and
1774 "enter". We also don't reverse intersegment "jmp" and "call"
1775 instructions with 2 immediate operands so that the immediate segment
050dfa73 1776 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1777 if (intel_syntax && i.operands > 1
1778 && (strcmp (mnemonic, "bound") != 0)
30123838 1779 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1780 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1781 swap_operands ();
1782
1783 if (i.imm_operands)
1784 optimize_imm ();
1785
b300c311
L		 1786 /* Don't optimize displacement for movabs since it only takes 64bit
1787 displacement. */
1788 if (i.disp_operands
1789 && (flag_code != CODE_64BIT
1790 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1791 optimize_disp ();
1792
1793 /* Next, we find a template that matches the given insn,
1794 making sure the overlap of the given operands types is consistent
1795 with the template operand types. */
252b5132 1796
29b0f896
AM		 1797 if (!match_template ())
1798 return;
252b5132 1799
cd61ebfe
AM		 1800 if (intel_syntax)
1801 {
1802 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1803 if (SYSV386_COMPAT
1804 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1805 i.tm.base_opcode ^= FloatR;
1806
1807 /* Zap movzx and movsx suffix. The suffix may have been set from
1808 "word ptr" or "byte ptr" on the source operand, but we'll use
1809 the suffix later to choose the destination register. */
1810 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1811 {
1812 if (i.reg_operands < 2
1813 && !i.suffix
1814 && (~i.tm.opcode_modifier
1815 & (No_bSuf
1816 | No_wSuf
1817 | No_lSuf
1818 | No_sSuf
1819 | No_xSuf
1820 | No_qSuf)))
1821 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1822
1823 i.suffix = 0;
1824 }
cd61ebfe 1825 }
24eab124 1826
29b0f896
AM		 1827 if (i.tm.opcode_modifier & FWait)
1828 if (!add_prefix (FWAIT_OPCODE))
1829 return;
252b5132 1830
29b0f896
AM		 1831 /* Check string instruction segment overrides. */
1832 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1833 {
1834 if (!check_string ())
5dd0794d 1835 return;
29b0f896 1836 }
5dd0794d 1837
29b0f896
AM		 1838 if (!process_suffix ())
1839 return;
e413e4e9 1840
29b0f896
AM		 1841 /* Make still unresolved immediate matches conform to size of immediate
1842 given in i.suffix. */
1843 if (!finalize_imm ())
1844 return;
252b5132 1845
29b0f896
AM		 1846 if (i.types[0] & Imm1)
1847 i.imm_operands = 0; /* kludge for shift insns. */
1848 if (i.types[0] & ImplicitRegister)
1849 i.reg_operands--;
1850 if (i.types[1] & ImplicitRegister)
1851 i.reg_operands--;
1852 if (i.types[2] & ImplicitRegister)
1853 i.reg_operands--;
252b5132 1854
29b0f896
AM		 1855 if (i.tm.opcode_modifier & ImmExt)
1856 {
02fc3089
L		 1857 expressionS *exp;
1858
b7d9ef37 1859 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1860 {
b7d9ef37 1861 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1862 operands with an opcode suffix which is coded in the same
1863 place as an 8-bit immediate field would be. Here we check
1864 those operands and remove them afterwards. */
1865 unsigned int x;
1866
a4622f40 1867 for (x = 0; x < i.operands; x++)
ca164297
L		 1868 if (i.op[x].regs->reg_num != x)
1869 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1870 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1871 i.operands = 0;
1872 }
1873
29b0f896
AM		 1874 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1875 opcode suffix which is coded in the same place as an 8-bit
1876 immediate field would be. Here we fake an 8-bit immediate
1877 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1878
29b0f896 1879 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1880
29b0f896
AM		 1881 exp = &im_expressions[i.imm_operands++];
1882 i.op[i.operands].imms = exp;
1883 i.types[i.operands++] = Imm8;
1884 exp->X_op = O_constant;
1885 exp->X_add_number = i.tm.extension_opcode;
1886 i.tm.extension_opcode = None;
1887 }
252b5132 1888
29b0f896
AM		 1889 /* For insns with operands there are more diddles to do to the opcode. */
1890 if (i.operands)
1891 {
1892 if (!process_operands ())
1893 return;
1894 }
1895 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1896 {
1897 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1898 as_warn (_("translating to `%sp'"), i.tm.name);
1899 }
252b5132 1900
29b0f896
AM		 1901 /* Handle conversion of 'int $3' --> special int3 insn. */
1902 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1903 {
1904 i.tm.base_opcode = INT3_OPCODE;
1905 i.imm_operands = 0;
1906 }
252b5132 1907
29b0f896
AM		 1908 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1909 && i.op[0].disps->X_op == O_constant)
1910 {
1911 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1912 the absolute address given by the constant. Since ix86 jumps and
1913 calls are pc relative, we need to generate a reloc. */
1914 i.op[0].disps->X_add_symbol = &abs_symbol;
1915 i.op[0].disps->X_op = O_symbol;
1916 }
252b5132 1917
29b0f896
AM		 1918 if ((i.tm.opcode_modifier & Rex64) != 0)
1919 i.rex |= REX_MODE64;
252b5132 1920
29b0f896
AM		 1921 /* For 8 bit registers we need an empty rex prefix. Also if the
1922 instruction already has a prefix, we need to convert old
1923 registers to new ones. */
773f551c 1924
29b0f896
AM		 1925 if (((i.types[0] & Reg8) != 0
1926 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1927 || ((i.types[1] & Reg8) != 0
1928 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1929 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1930 && i.rex != 0))
1931 {
1932 int x;
726c5dcd 1933
29b0f896
AM		 1934 i.rex |= REX_OPCODE;
1935 for (x = 0; x < 2; x++)
1936 {
1937 /* Look for 8 bit operand that uses old registers. */
1938 if ((i.types[x] & Reg8) != 0
1939 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1940 {
29b0f896
AM		 1941 /* In case it is "hi" register, give up. */
1942 if (i.op[x].regs->reg_num > 3)
0477af35 1943 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1944 i.op[x].regs->reg_name);
773f551c 1945
29b0f896
AM		 1946 /* Otherwise it is equivalent to the extended register.
1947 Since the encoding doesn't change this is merely
1948 cosmetic cleanup for debug output. */
1949
1950 i.op[x].regs = i.op[x].regs + 8;
773f551c 1951 }
29b0f896
AM		 1952 }
1953 }
773f551c 1954
29b0f896
AM		 1955 if (i.rex != 0)
1956 add_prefix (REX_OPCODE | i.rex);
1957
1958 /* We are ready to output the insn. */
1959 output_insn ();
1960}
1961
1962static char *
1963parse_insn (line, mnemonic)
1964 char *line;
1965 char *mnemonic;
1966{
1967 char *l = line;
1968 char *token_start = l;
1969 char *mnem_p;
5c6af06e
JB		 1970 int supported;
1971 const template *t;
29b0f896
AM		 1972
1973 /* Non-zero if we found a prefix only acceptable with string insns. */
1974 const char *expecting_string_instruction = NULL;
45288df1 1975
29b0f896
AM		 1976 while (1)
1977 {
1978 mnem_p = mnemonic;
1979 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1980 {
1981 mnem_p++;
1982 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1983 {
29b0f896
AM		 1984 as_bad (_("no such instruction: `%s'"), token_start);
1985 return NULL;
1986 }
1987 l++;
1988 }
1989 if (!is_space_char (*l)
1990 && *l != END_OF_INSN
e44823cf
JB		 1991 && (intel_syntax
1992 || (*l != PREFIX_SEPARATOR
1993 && *l != ',')))
29b0f896
AM		 1994 {
1995 as_bad (_("invalid character %s in mnemonic"),
1996 output_invalid (*l));
1997 return NULL;
1998 }
1999 if (token_start == l)
2000 {
e44823cf 2001 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2002 as_bad (_("expecting prefix; got nothing"));
2003 else
2004 as_bad (_("expecting mnemonic; got nothing"));
2005 return NULL;
2006 }
45288df1 2007
29b0f896
AM		 2008 /* Look up instruction (or prefix) via hash table. */
2009 current_templates = hash_find (op_hash, mnemonic);
47926f60 2010
29b0f896
AM		 2011 if (*l != END_OF_INSN
2012 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2013 && current_templates
2014 && (current_templates->start->opcode_modifier & IsPrefix))
2015 {
2dd88dca
JB		 2016 if (current_templates->start->cpu_flags
2017 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2018 {
2019 as_bad ((flag_code != CODE_64BIT
2020 ? _("`%s' is only supported in 64-bit mode")
2021 : _("`%s' is not supported in 64-bit mode")),
2022 current_templates->start->name);
2023 return NULL;
2024 }
29b0f896
AM		 2025 /* If we are in 16-bit mode, do not allow addr16 or data16.
2026 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2027 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2028 && flag_code != CODE_64BIT
2029 && (((current_templates->start->opcode_modifier & Size32) != 0)
2030 ^ (flag_code == CODE_16BIT)))
2031 {
2032 as_bad (_("redundant %s prefix"),
2033 current_templates->start->name);
2034 return NULL;
45288df1 2035 }
29b0f896
AM		 2036 /* Add prefix, checking for repeated prefixes. */
2037 switch (add_prefix (current_templates->start->base_opcode))
2038 {
2039 case 0:
2040 return NULL;
2041 case 2:
2042 expecting_string_instruction = current_templates->start->name;
2043 break;
2044 }
2045 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2046 token_start = ++l;
2047 }
2048 else
2049 break;
2050 }
45288df1 2051
29b0f896
AM		 2052 if (!current_templates)
2053 {
2054 /* See if we can get a match by trimming off a suffix. */
2055 switch (mnem_p[-1])
2056 {
2057 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2058 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2059 i.suffix = SHORT_MNEM_SUFFIX;
2060 else
29b0f896
AM		 2061 case BYTE_MNEM_SUFFIX:
2062 case QWORD_MNEM_SUFFIX:
2063 i.suffix = mnem_p[-1];
2064 mnem_p[-1] = '\0';
2065 current_templates = hash_find (op_hash, mnemonic);
2066 break;
2067 case SHORT_MNEM_SUFFIX:
2068 case LONG_MNEM_SUFFIX:
2069 if (!intel_syntax)
2070 {
2071 i.suffix = mnem_p[-1];
2072 mnem_p[-1] = '\0';
2073 current_templates = hash_find (op_hash, mnemonic);
2074 }
2075 break;
252b5132 2076
29b0f896
AM		 2077 /* Intel Syntax. */
2078 case 'd':
2079 if (intel_syntax)
2080 {
9306ca4a 2081 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2082 i.suffix = SHORT_MNEM_SUFFIX;
2083 else
2084 i.suffix = LONG_MNEM_SUFFIX;
2085 mnem_p[-1] = '\0';
2086 current_templates = hash_find (op_hash, mnemonic);
2087 }
2088 break;
2089 }
2090 if (!current_templates)
2091 {
2092 as_bad (_("no such instruction: `%s'"), token_start);
2093 return NULL;
2094 }
2095 }
252b5132 2096
29b0f896
AM		 2097 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2098 {
2099 /* Check for a branch hint. We allow ",pt" and ",pn" for
2100 predict taken and predict not taken respectively.
2101 I'm not sure that branch hints actually do anything on loop
2102 and jcxz insns (JumpByte) for current Pentium4 chips. They
2103 may work in the future and it doesn't hurt to accept them
2104 now. */
2105 if (l[0] == ',' && l[1] == 'p')
2106 {
2107 if (l[2] == 't')
2108 {
2109 if (!add_prefix (DS_PREFIX_OPCODE))
2110 return NULL;
2111 l += 3;
2112 }
2113 else if (l[2] == 'n')
2114 {
2115 if (!add_prefix (CS_PREFIX_OPCODE))
2116 return NULL;
2117 l += 3;
2118 }
2119 }
2120 }
2121 /* Any other comma loses. */
2122 if (*l == ',')
2123 {
2124 as_bad (_("invalid character %s in mnemonic"),
2125 output_invalid (*l));
2126 return NULL;
2127 }
252b5132 2128
29b0f896 2129 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2130 supported = 0;
2131 for (t = current_templates->start; t < current_templates->end; ++t)
2132 {
2133 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2134 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2135 supported |= 1;
5c6af06e 2136 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2137 supported |= 2;
5c6af06e
JB		 2138 }
2139 if (!(supported & 2))
2140 {
2141 as_bad (flag_code == CODE_64BIT
2142 ? _("`%s' is not supported in 64-bit mode")
2143 : _("`%s' is only supported in 64-bit mode"),
2144 current_templates->start->name);
2145 return NULL;
2146 }
2147 if (!(supported & 1))
29b0f896 2148 {
5c6af06e
JB		 2149 as_warn (_("`%s' is not supported on `%s%s'"),
2150 current_templates->start->name,
2151 cpu_arch_name,
2152 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2153 }
2154 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2155 {
2156 as_warn (_("use .code16 to ensure correct addressing mode"));
2157 }
252b5132 2158
29b0f896 2159 /* Check for rep/repne without a string instruction. */
f41bbced 2160 if (expecting_string_instruction)
29b0f896 2161 {
f41bbced
JB		 2162 static templates override;
2163
2164 for (t = current_templates->start; t < current_templates->end; ++t)
2165 if (t->opcode_modifier & IsString)
2166 break;
2167 if (t >= current_templates->end)
2168 {
2169 as_bad (_("expecting string instruction after `%s'"),
64e74474 2170 expecting_string_instruction);
f41bbced
JB		 2171 return NULL;
2172 }
2173 for (override.start = t; t < current_templates->end; ++t)
2174 if (!(t->opcode_modifier & IsString))
2175 break;
2176 override.end = t;
2177 current_templates = &override;
29b0f896 2178 }
252b5132 2179
29b0f896
AM		 2180 return l;
2181}
252b5132 2182
29b0f896
AM		 2183static char *
2184parse_operands (l, mnemonic)
2185 char *l;
2186 const char *mnemonic;
2187{
2188 char *token_start;
3138f287 2189
29b0f896
AM		 2190 /* 1 if operand is pending after ','. */
2191 unsigned int expecting_operand = 0;
252b5132 2192
29b0f896
AM		 2193 /* Non-zero if operand parens not balanced. */
2194 unsigned int paren_not_balanced;
2195
2196 while (*l != END_OF_INSN)
2197 {
2198 /* Skip optional white space before operand. */
2199 if (is_space_char (*l))
2200 ++l;
2201 if (!is_operand_char (*l) && *l != END_OF_INSN)
2202 {
2203 as_bad (_("invalid character %s before operand %d"),
2204 output_invalid (*l),
2205 i.operands + 1);
2206 return NULL;
2207 }
2208 token_start = l; /* after white space */
2209 paren_not_balanced = 0;
2210 while (paren_not_balanced || *l != ',')
2211 {
2212 if (*l == END_OF_INSN)
2213 {
2214 if (paren_not_balanced)
2215 {
2216 if (!intel_syntax)
2217 as_bad (_("unbalanced parenthesis in operand %d."),
2218 i.operands + 1);
2219 else
2220 as_bad (_("unbalanced brackets in operand %d."),
2221 i.operands + 1);
2222 return NULL;
2223 }
2224 else
2225 break; /* we are done */
2226 }
2227 else if (!is_operand_char (*l) && !is_space_char (*l))
2228 {
2229 as_bad (_("invalid character %s in operand %d"),
2230 output_invalid (*l),
2231 i.operands + 1);
2232 return NULL;
2233 }
2234 if (!intel_syntax)
2235 {
2236 if (*l == '(')
2237 ++paren_not_balanced;
2238 if (*l == ')')
2239 --paren_not_balanced;
2240 }
2241 else
2242 {
2243 if (*l == '[')
2244 ++paren_not_balanced;
2245 if (*l == ']')
2246 --paren_not_balanced;
2247 }
2248 l++;
2249 }
2250 if (l != token_start)
2251 { /* Yes, we've read in another operand. */
2252 unsigned int operand_ok;
2253 this_operand = i.operands++;
2254 if (i.operands > MAX_OPERANDS)
2255 {
2256 as_bad (_("spurious operands; (%d operands/instruction max)"),
2257 MAX_OPERANDS);
2258 return NULL;
2259 }
2260 /* Now parse operand adding info to 'i' as we go along. */
2261 END_STRING_AND_SAVE (l);
2262
2263 if (intel_syntax)
2264 operand_ok =
2265 i386_intel_operand (token_start,
2266 intel_float_operand (mnemonic));
2267 else
2268 operand_ok = i386_operand (token_start);
2269
2270 RESTORE_END_STRING (l);
2271 if (!operand_ok)
2272 return NULL;
2273 }
2274 else
2275 {
2276 if (expecting_operand)
2277 {
2278 expecting_operand_after_comma:
2279 as_bad (_("expecting operand after ','; got nothing"));
2280 return NULL;
2281 }
2282 if (*l == ',')
2283 {
2284 as_bad (_("expecting operand before ','; got nothing"));
2285 return NULL;
2286 }
2287 }
7f3f1ea2 2288
29b0f896
AM		 2289 /* Now *l must be either ',' or END_OF_INSN. */
2290 if (*l == ',')
2291 {
2292 if (*++l == END_OF_INSN)
2293 {
2294 /* Just skip it, if it's \n complain. */
2295 goto expecting_operand_after_comma;
2296 }
2297 expecting_operand = 1;
2298 }
2299 }
2300 return l;
2301}
7f3f1ea2 2302
050dfa73
MM		 2303static void
2304swap_imm_operands ()
2305{
2306 union i386_op temp_op;
2307 unsigned int temp_type;
2308 enum bfd_reloc_code_real temp_reloc;
2309 int xchg1 = 0;
2310 int xchg2 = 1;
2311
2312 temp_type = i.types[xchg2];
2313 i.types[xchg2] = i.types[xchg1];
2314 i.types[xchg1] = temp_type;
2315 temp_op = i.op[xchg2];
2316 i.op[xchg2] = i.op[xchg1];
2317 i.op[xchg1] = temp_op;
2318 temp_reloc = i.reloc[xchg2];
2319 i.reloc[xchg2] = i.reloc[xchg1];
2320 i.reloc[xchg1] = temp_reloc;
2321}
2322
2323
29b0f896
AM		 2324static void
2325swap_operands ()
2326{
2327 union i386_op temp_op;
2328 unsigned int temp_type;
f86103b7 2329 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2330 int xchg1 = 0;
2331 int xchg2 = 0;
252b5132 2332
050dfa73
MM		 2333 if (i.operands == 4)
2334 /* There will be two exchanges in a 4 operand instruction.
2335 First exchange is the done inside this block.(1st and 4rth operand)
2336 The next exchange is done outside this block.(2nd and 3rd operand) */
2337 {
2338 xchg1 = 0;
2339 xchg2 = 3;
2340 temp_type = i.types[xchg2];
2341 i.types[xchg2] = i.types[xchg1];
2342 i.types[xchg1] = temp_type;
2343 temp_op = i.op[xchg2];
2344 i.op[xchg2] = i.op[xchg1];
2345 i.op[xchg1] = temp_op;
2346 temp_reloc = i.reloc[xchg2];
2347 i.reloc[xchg2] = i.reloc[xchg1];
2348 i.reloc[xchg1] = temp_reloc;
2349 xchg1 = 1;
2350 xchg2 = 2;
2351 }
2352
29b0f896
AM		 2353 if (i.operands == 2)
2354 {
2355 xchg1 = 0;
2356 xchg2 = 1;
2357 }
2358 else if (i.operands == 3)
2359 {
2360 xchg1 = 0;
2361 xchg2 = 2;
2362 }
2363 temp_type = i.types[xchg2];
2364 i.types[xchg2] = i.types[xchg1];
2365 i.types[xchg1] = temp_type;
2366 temp_op = i.op[xchg2];
2367 i.op[xchg2] = i.op[xchg1];
2368 i.op[xchg1] = temp_op;
2369 temp_reloc = i.reloc[xchg2];
2370 i.reloc[xchg2] = i.reloc[xchg1];
2371 i.reloc[xchg1] = temp_reloc;
2372
2373 if (i.mem_operands == 2)
2374 {
2375 const seg_entry *temp_seg;
2376 temp_seg = i.seg[0];
2377 i.seg[0] = i.seg[1];
2378 i.seg[1] = temp_seg;
2379 }
2380}
252b5132 2381
29b0f896
AM		 2382/* Try to ensure constant immediates are represented in the smallest
2383 opcode possible. */
2384static void
2385optimize_imm ()
2386{
2387 char guess_suffix = 0;
2388 int op;
252b5132 2389
29b0f896
AM		 2390 if (i.suffix)
2391 guess_suffix = i.suffix;
2392 else if (i.reg_operands)
2393 {
2394 /* Figure out a suffix from the last register operand specified.
2395 We can't do this properly yet, ie. excluding InOutPortReg,
2396 but the following works for instructions with immediates.
2397 In any case, we can't set i.suffix yet. */
2398 for (op = i.operands; --op >= 0;)
2399 if (i.types[op] & Reg)
252b5132 2400 {
29b0f896
AM		 2401 if (i.types[op] & Reg8)
2402 guess_suffix = BYTE_MNEM_SUFFIX;
2403 else if (i.types[op] & Reg16)
2404 guess_suffix = WORD_MNEM_SUFFIX;
2405 else if (i.types[op] & Reg32)
2406 guess_suffix = LONG_MNEM_SUFFIX;
2407 else if (i.types[op] & Reg64)
2408 guess_suffix = QWORD_MNEM_SUFFIX;
2409 break;
252b5132 2410 }
29b0f896
AM		 2411 }
2412 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2413 guess_suffix = WORD_MNEM_SUFFIX;
2414
2415 for (op = i.operands; --op >= 0;)
2416 if (i.types[op] & Imm)
2417 {
2418 switch (i.op[op].imms->X_op)
252b5132 2419 {
29b0f896
AM		 2420 case O_constant:
2421 /* If a suffix is given, this operand may be shortened. */
2422 switch (guess_suffix)
252b5132 2423 {
29b0f896
AM		 2424 case LONG_MNEM_SUFFIX:
2425 i.types[op] |= Imm32 | Imm64;
2426 break;
2427 case WORD_MNEM_SUFFIX:
2428 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2429 break;
2430 case BYTE_MNEM_SUFFIX:
2431 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2432 break;
252b5132 2433 }
252b5132 2434
29b0f896
AM		 2435 /* If this operand is at most 16 bits, convert it
2436 to a signed 16 bit number before trying to see
2437 whether it will fit in an even smaller size.
2438 This allows a 16-bit operand such as $0xffe0 to
2439 be recognised as within Imm8S range. */
2440 if ((i.types[op] & Imm16)
2441 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2442 {
29b0f896
AM		 2443 i.op[op].imms->X_add_number =
2444 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2445 }
2446 if ((i.types[op] & Imm32)
2447 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2448 == 0))
2449 {
2450 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2451 ^ ((offsetT) 1 << 31))
2452 - ((offsetT) 1 << 31));
2453 }
2454 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2455
29b0f896
AM		 2456 /* We must avoid matching of Imm32 templates when 64bit
2457 only immediate is available. */
2458 if (guess_suffix == QWORD_MNEM_SUFFIX)
2459 i.types[op] &= ~Imm32;
2460 break;
252b5132 2461
29b0f896
AM		 2462 case O_absent:
2463 case O_register:
2464 abort ();
2465
2466 /* Symbols and expressions. */
2467 default:
9cd96992
JB		 2468 /* Convert symbolic operand to proper sizes for matching, but don't
2469 prevent matching a set of insns that only supports sizes other
2470 than those matching the insn suffix. */
2471 {
2472 unsigned int mask, allowed = 0;
2473 const template *t;
2474
2475 for (t = current_templates->start; t < current_templates->end; ++t)
2476 allowed |= t->operand_types[op];
2477 switch (guess_suffix)
2478 {
2479 case QWORD_MNEM_SUFFIX:
2480 mask = Imm64 | Imm32S;
2481 break;
2482 case LONG_MNEM_SUFFIX:
2483 mask = Imm32;
2484 break;
2485 case WORD_MNEM_SUFFIX:
2486 mask = Imm16;
2487 break;
2488 case BYTE_MNEM_SUFFIX:
2489 mask = Imm8;
2490 break;
2491 default:
2492 mask = 0;
2493 break;
2494 }
64e74474
AM		 2495 if (mask & allowed)
2496 i.types[op] &= mask;
9cd96992 2497 }
29b0f896 2498 break;
252b5132 2499 }
29b0f896
AM		 2500 }
2501}
47926f60 2502
29b0f896
AM		 2503/* Try to use the smallest displacement type too. */
2504static void
2505optimize_disp ()
2506{
2507 int op;
3e73aa7c 2508
29b0f896 2509 for (op = i.operands; --op >= 0;)
b300c311 2510 if (i.types[op] & Disp)
252b5132 2511 {
b300c311 2512 if (i.op[op].disps->X_op == O_constant)
252b5132 2513 {
b300c311 2514 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2515
b300c311
L		 2516 if ((i.types[op] & Disp16)
2517 && (disp & ~(offsetT) 0xffff) == 0)
2518 {
2519 /* If this operand is at most 16 bits, convert
2520 to a signed 16 bit number and don't use 64bit
2521 displacement. */
2522 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2523 i.types[op] &= ~Disp64;
2524 }
2525 if ((i.types[op] & Disp32)
2526 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2527 {
2528 /* If this operand is at most 32 bits, convert
2529 to a signed 32 bit number and don't use 64bit
2530 displacement. */
2531 disp &= (((offsetT) 2 << 31) - 1);
2532 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2533 i.types[op] &= ~Disp64;
2534 }
2535 if (!disp && (i.types[op] & BaseIndex))
2536 {
2537 i.types[op] &= ~Disp;
2538 i.op[op].disps = 0;
2539 i.disp_operands--;
2540 }
2541 else if (flag_code == CODE_64BIT)
2542 {
2543 if (fits_in_signed_long (disp))
28a9d8f5
L		 2544 {
2545 i.types[op] &= ~Disp64;
2546 i.types[op] |= Disp32S;
2547 }
b300c311
L		 2548 if (fits_in_unsigned_long (disp))
2549 i.types[op] |= Disp32;
2550 }
2551 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2552 && fits_in_signed_byte (disp))
2553 i.types[op] |= Disp8;
252b5132 2554 }
67a4f2b7
AO		 2555 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2556 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2557 {
2558 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2559 i.op[op].disps, 0, i.reloc[op]);
2560 i.types[op] &= ~Disp;
2561 }
2562 else
b300c311
L		 2563 /* We only support 64bit displacement on constants. */
2564 i.types[op] &= ~Disp64;
252b5132 2565 }
29b0f896
AM		 2566}
2567
2568static int
2569match_template ()
2570{
2571 /* Points to template once we've found it. */
2572 const template *t;
f48ff2ae 2573 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2574 unsigned int found_reverse_match;
2575 int suffix_check;
f48ff2ae 2576 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2577 int addr_prefix_disp;
a5c311ca 2578 unsigned int j;
29b0f896 2579
f48ff2ae
L		 2580#if MAX_OPERANDS != 4
2581# error "MAX_OPERANDS must be 4."
2582#endif
2583
29b0f896
AM		 2584#define MATCH(overlap, given, template) \
2585 ((overlap & ~JumpAbsolute) \
2586 && (((given) & (BaseIndex | JumpAbsolute)) \
2587 == ((overlap) & (BaseIndex | JumpAbsolute))))
2588
2589 /* If given types r0 and r1 are registers they must be of the same type
2590 unless the expected operand type register overlap is null.
2591 Note that Acc in a template matches every size of reg. */
2592#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2593 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2594 || ((g0) & Reg) == ((g1) & Reg) \
2595 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2596
2597 overlap0 = 0;
2598 overlap1 = 0;
2599 overlap2 = 0;
f48ff2ae 2600 overlap3 = 0;
29b0f896 2601 found_reverse_match = 0;
a5c311ca
L		 2602 for (j = 0; j < MAX_OPERANDS; j++)
2603 operand_types [j] = 0;
539e75ad 2604 addr_prefix_disp = -1;
29b0f896
AM		 2605 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2606 ? No_bSuf
2607 : (i.suffix == WORD_MNEM_SUFFIX
2608 ? No_wSuf
2609 : (i.suffix == SHORT_MNEM_SUFFIX
2610 ? No_sSuf
2611 : (i.suffix == LONG_MNEM_SUFFIX
2612 ? No_lSuf
2613 : (i.suffix == QWORD_MNEM_SUFFIX
2614 ? No_qSuf
2615 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2616 ? No_xSuf : 0))))));
2617
45aa61fe 2618 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2619 {
539e75ad
L		 2620 addr_prefix_disp = -1;
2621
29b0f896
AM		 2622 /* Must have right number of operands. */
2623 if (i.operands != t->operands)
2624 continue;
2625
2626 /* Check the suffix, except for some instructions in intel mode. */
2627 if ((t->opcode_modifier & suffix_check)
2628 && !(intel_syntax
9306ca4a 2629 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2630 continue;
2631
a5c311ca
L		 2632 for (j = 0; j < MAX_OPERANDS; j++)
2633 operand_types [j] = t->operand_types [j];
539e75ad 2634
45aa61fe
AM		 2635 /* In general, don't allow 64-bit operands in 32-bit mode. */
2636 if (i.suffix == QWORD_MNEM_SUFFIX
2637 && flag_code != CODE_64BIT
2638 && (intel_syntax
2639 ? (!(t->opcode_modifier & IgnoreSize)
2640 && !intel_float_operand (t->name))
2641 : intel_float_operand (t->name) != 2)
539e75ad
L		 2642 && (!(operand_types[0] & (RegMMX | RegXMM))
2643 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2644 && (t->base_opcode != 0x0fc7
2645 || t->extension_opcode != 1 /* cmpxchg8b */))
2646 continue;
2647
29b0f896
AM		 2648 /* Do not verify operands when there are none. */
2649 else if (!t->operands)
2650 {
2651 if (t->cpu_flags & ~cpu_arch_flags)
2652 continue;
2653 /* We've found a match; break out of loop. */
2654 break;
2655 }
252b5132 2656
539e75ad
L		 2657 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2658 into Disp32/Disp16/Disp32 operand. */
2659 if (i.prefix[ADDR_PREFIX] != 0)
2660 {
a5c311ca 2661 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2662
2663 switch (flag_code)
2664 {
2665 case CODE_16BIT:
2666 DispOn = Disp32;
2667 DispOff = Disp16;
2668 break;
2669 case CODE_32BIT:
2670 DispOn = Disp16;
2671 DispOff = Disp32;
2672 break;
2673 case CODE_64BIT:
2674 DispOn = Disp32;
2675 DispOff = Disp64;
2676 break;
2677 }
2678
f48ff2ae 2679 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2680 {
2681 /* There should be only one Disp operand. */
2682 if ((operand_types[j] & DispOff))
2683 {
2684 addr_prefix_disp = j;
2685 operand_types[j] |= DispOn;
2686 operand_types[j] &= ~DispOff;
2687 break;
2688 }
2689 }
2690 }
2691
2692 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2693 switch (t->operands)
2694 {
2695 case 1:
539e75ad 2696 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2697 continue;
2698 break;
2699 case 2:
2700 case 3:
f48ff2ae 2701 case 4:
539e75ad
L		 2702 overlap1 = i.types[1] & operand_types[1];
2703 if (!MATCH (overlap0, i.types[0], operand_types[0])
2704 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2705 /* monitor in SSE3 is a very special case. The first
708587a4 2706 register and the second register may have different
cb712a9e
L		 2707 sizes. */
2708 || !((t->base_opcode == 0x0f01
2709 && t->extension_opcode == 0xc8)
2710 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2711 operand_types[0],
cb712a9e 2712 overlap1, i.types[1],
539e75ad 2713 operand_types[1])))
29b0f896
AM		 2714 {
2715 /* Check if other direction is valid ... */
2716 if ((t->opcode_modifier & (D | FloatD)) == 0)
2717 continue;
2718
2719 /* Try reversing direction of operands. */
539e75ad
L		 2720 overlap0 = i.types[0] & operand_types[1];
2721 overlap1 = i.types[1] & operand_types[0];
2722 if (!MATCH (overlap0, i.types[0], operand_types[1])
2723 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2724 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2725 operand_types[1],
29b0f896 2726 overlap1, i.types[1],
539e75ad 2727 operand_types[0]))
29b0f896
AM		 2728 {
2729 /* Does not match either direction. */
2730 continue;
2731 }
2732 /* found_reverse_match holds which of D or FloatDR
2733 we've found. */
2734 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2735 }
f48ff2ae 2736 else
29b0f896 2737 {
f48ff2ae 2738 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2739 switch (t->operands)
2740 {
2741 case 4:
2742 overlap3 = i.types[3] & operand_types[3];
2743 case 3:
2744 overlap2 = i.types[2] & operand_types[2];
2745 break;
2746 }
29b0f896 2747
f48ff2ae
L		 2748 switch (t->operands)
2749 {
2750 case 4:
2751 if (!MATCH (overlap3, i.types[3], operand_types[3])
2752 || !CONSISTENT_REGISTER_MATCH (overlap2,
2753 i.types[2],
2754 operand_types[2],
2755 overlap3,
2756 i.types[3],
2757 operand_types[3]))
2758 continue;
2759 case 3:
2760 /* Here we make use of the fact that there are no
2761 reverse match 3 operand instructions, and all 3
2762 operand instructions only need to be checked for
2763 register consistency between operands 2 and 3. */
2764 if (!MATCH (overlap2, i.types[2], operand_types[2])
2765 || !CONSISTENT_REGISTER_MATCH (overlap1,
2766 i.types[1],
2767 operand_types[1],
2768 overlap2,
2769 i.types[2],
2770 operand_types[2]))
2771 continue;
2772 break;
2773 }
29b0f896 2774 }
f48ff2ae 2775 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2776 slip through to break. */
2777 }
2778 if (t->cpu_flags & ~cpu_arch_flags)
2779 {
2780 found_reverse_match = 0;
2781 continue;
2782 }
2783 /* We've found a match; break out of loop. */
2784 break;
2785 }
2786
2787 if (t == current_templates->end)
2788 {
2789 /* We found no match. */
2790 as_bad (_("suffix or operands invalid for `%s'"),
2791 current_templates->start->name);
2792 return 0;
2793 }
252b5132 2794
29b0f896
AM		 2795 if (!quiet_warnings)
2796 {
2797 if (!intel_syntax
2798 && ((i.types[0] & JumpAbsolute)
539e75ad 2799 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2800 {
2801 as_warn (_("indirect %s without `*'"), t->name);
2802 }
2803
2804 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2805 == (IsPrefix | IgnoreSize))
2806 {
2807 /* Warn them that a data or address size prefix doesn't
2808 affect assembly of the next line of code. */
2809 as_warn (_("stand-alone `%s' prefix"), t->name);
2810 }
2811 }
2812
2813 /* Copy the template we found. */
2814 i.tm = *t;
539e75ad
L		 2815
2816 if (addr_prefix_disp != -1)
2817 i.tm.operand_types[addr_prefix_disp]
2818 = operand_types[addr_prefix_disp];
2819
29b0f896
AM		 2820 if (found_reverse_match)
2821 {
2822 /* If we found a reverse match we must alter the opcode
2823 direction bit. found_reverse_match holds bits to change
2824 (different for int & float insns). */
2825
2826 i.tm.base_opcode ^= found_reverse_match;
2827
539e75ad
L		 2828 i.tm.operand_types[0] = operand_types[1];
2829 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2830 }
2831
2832 return 1;
2833}
2834
2835static int
2836check_string ()
2837{
2838 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2839 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2840 {
2841 if (i.seg[0] != NULL && i.seg[0] != &es)
2842 {
2843 as_bad (_("`%s' operand %d must use `%%es' segment"),
2844 i.tm.name,
2845 mem_op + 1);
2846 return 0;
2847 }
2848 /* There's only ever one segment override allowed per instruction.
2849 This instruction possibly has a legal segment override on the
2850 second operand, so copy the segment to where non-string
2851 instructions store it, allowing common code. */
2852 i.seg[0] = i.seg[1];
2853 }
2854 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2855 {
2856 if (i.seg[1] != NULL && i.seg[1] != &es)
2857 {
2858 as_bad (_("`%s' operand %d must use `%%es' segment"),
2859 i.tm.name,
2860 mem_op + 2);
2861 return 0;
2862 }
2863 }
2864 return 1;
2865}
2866
2867static int
543613e9 2868process_suffix (void)
29b0f896
AM		 2869{
2870 /* If matched instruction specifies an explicit instruction mnemonic
2871 suffix, use it. */
2872 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2873 {
2874 if (i.tm.opcode_modifier & Size16)
2875 i.suffix = WORD_MNEM_SUFFIX;
2876 else if (i.tm.opcode_modifier & Size64)
2877 i.suffix = QWORD_MNEM_SUFFIX;
2878 else
2879 i.suffix = LONG_MNEM_SUFFIX;
2880 }
2881 else if (i.reg_operands)
2882 {
2883 /* If there's no instruction mnemonic suffix we try to invent one
2884 based on register operands. */
2885 if (!i.suffix)
2886 {
2887 /* We take i.suffix from the last register operand specified,
2888 Destination register type is more significant than source
2889 register type. */
2890 int op;
543613e9 2891
29b0f896
AM		 2892 for (op = i.operands; --op >= 0;)
2893 if ((i.types[op] & Reg)
2894 && !(i.tm.operand_types[op] & InOutPortReg))
2895 {
2896 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2897 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2898 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2899 LONG_MNEM_SUFFIX);
2900 break;
2901 }
2902 }
2903 else if (i.suffix == BYTE_MNEM_SUFFIX)
2904 {
2905 if (!check_byte_reg ())
2906 return 0;
2907 }
2908 else if (i.suffix == LONG_MNEM_SUFFIX)
2909 {
2910 if (!check_long_reg ())
2911 return 0;
2912 }
2913 else if (i.suffix == QWORD_MNEM_SUFFIX)
2914 {
2915 if (!check_qword_reg ())
2916 return 0;
2917 }
2918 else if (i.suffix == WORD_MNEM_SUFFIX)
2919 {
2920 if (!check_word_reg ())
2921 return 0;
2922 }
2923 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2924 /* Do nothing if the instruction is going to ignore the prefix. */
2925 ;
2926 else
2927 abort ();
2928 }
9306ca4a
JB		 2929 else if ((i.tm.opcode_modifier & DefaultSize)
2930 && !i.suffix
2931 /* exclude fldenv/frstor/fsave/fstenv */
2932 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2933 {
2934 i.suffix = stackop_size;
2935 }
9306ca4a
JB		 2936 else if (intel_syntax
2937 && !i.suffix
2938 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2939 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2940 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2941 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2942 {
2943 switch (flag_code)
2944 {
2945 case CODE_64BIT:
2946 if (!(i.tm.opcode_modifier & No_qSuf))
2947 {
2948 i.suffix = QWORD_MNEM_SUFFIX;
2949 break;
2950 }
2951 case CODE_32BIT:
2952 if (!(i.tm.opcode_modifier & No_lSuf))
2953 i.suffix = LONG_MNEM_SUFFIX;
2954 break;
2955 case CODE_16BIT:
2956 if (!(i.tm.opcode_modifier & No_wSuf))
2957 i.suffix = WORD_MNEM_SUFFIX;
2958 break;
2959 }
2960 }
252b5132 2961
9306ca4a 2962 if (!i.suffix)
29b0f896 2963 {
9306ca4a
JB		 2964 if (!intel_syntax)
2965 {
2966 if (i.tm.opcode_modifier & W)
2967 {
2968 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2969 return 0;
2970 }
2971 }
2972 else
2973 {
64e74474
AM		 2974 unsigned int suffixes = (~i.tm.opcode_modifier
2975 & (No_bSuf
2976 | No_wSuf
2977 | No_lSuf
2978 | No_sSuf
2979 | No_xSuf
2980 | No_qSuf));
9306ca4a
JB		 2981
2982 if ((i.tm.opcode_modifier & W)
2983 || ((suffixes & (suffixes - 1))
2984 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2985 {
2986 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2987 return 0;
2988 }
2989 }
29b0f896 2990 }
252b5132 2991
9306ca4a
JB		 2992 /* Change the opcode based on the operand size given by i.suffix;
2993 We don't need to change things for byte insns. */
2994
29b0f896
AM		 2995 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2996 {
2997 /* It's not a byte, select word/dword operation. */
2998 if (i.tm.opcode_modifier & W)
2999 {
3000 if (i.tm.opcode_modifier & ShortForm)
3001 i.tm.base_opcode |= 8;
3002 else
3003 i.tm.base_opcode |= 1;
3004 }
0f3f3d8b 3005
29b0f896
AM		 3006 /* Now select between word & dword operations via the operand
3007 size prefix, except for instructions that will ignore this
3008 prefix anyway. */
cb712a9e
L		 3009 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3010 {
3011 /* monitor in SSE3 is a very special case. The default size
3012 of AX is the size of mode. The address size override
3013 prefix will change the size of AX. */
3014 if (i.op->regs[0].reg_type &
3015 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3016 if (!add_prefix (ADDR_PREFIX_OPCODE))
3017 return 0;
3018 }
3019 else if (i.suffix != QWORD_MNEM_SUFFIX
3020 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3021 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3022 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3023 || (flag_code == CODE_64BIT
3024 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3025 {
3026 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3027
29b0f896
AM		 3028 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3029 prefix = ADDR_PREFIX_OPCODE;
252b5132 3030
29b0f896
AM		 3031 if (!add_prefix (prefix))
3032 return 0;
24eab124 3033 }
252b5132 3034
29b0f896
AM		 3035 /* Set mode64 for an operand. */
3036 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3037 && flag_code == CODE_64BIT
29b0f896 3038 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3039 {
3040 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3041 need rex64. */
3042 if (i.operands != 2
3043 || i.types [0] != (Acc | Reg64)
3044 || i.types [1] != (Acc | Reg64)
3045 || strcmp (i.tm.name, "xchg") != 0)
3046 i.rex |= REX_MODE64;
3047 }
3e73aa7c 3048
29b0f896
AM		 3049 /* Size floating point instruction. */
3050 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3051 if (i.tm.opcode_modifier & FloatMF)
3052 i.tm.base_opcode ^= 4;
29b0f896 3053 }
7ecd2f8b 3054
29b0f896
AM		 3055 return 1;
3056}
3e73aa7c 3057
29b0f896 3058static int
543613e9 3059check_byte_reg (void)
29b0f896
AM		 3060{
3061 int op;
543613e9 3062
29b0f896
AM		 3063 for (op = i.operands; --op >= 0;)
3064 {
3065 /* If this is an eight bit register, it's OK. If it's the 16 or
3066 32 bit version of an eight bit register, we will just use the
3067 low portion, and that's OK too. */
3068 if (i.types[op] & Reg8)
3069 continue;
3070
3071 /* movzx and movsx should not generate this warning. */
3072 if (intel_syntax
3073 && (i.tm.base_opcode == 0xfb7
3074 || i.tm.base_opcode == 0xfb6
3075 || i.tm.base_opcode == 0x63
3076 || i.tm.base_opcode == 0xfbe
3077 || i.tm.base_opcode == 0xfbf))
3078 continue;
3079
65ec77d2 3080 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3081 {
3082 /* Prohibit these changes in the 64bit mode, since the
3083 lowering is more complicated. */
3084 if (flag_code == CODE_64BIT
3085 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3086 {
0f3f3d8b 3087 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3088 i.op[op].regs->reg_name,
3089 i.suffix);
3090 return 0;
3091 }
3092#if REGISTER_WARNINGS
3093 if (!quiet_warnings
3094 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3095 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3096 (i.op[op].regs + (i.types[op] & Reg16
3097 ? REGNAM_AL - REGNAM_AX
3098 : REGNAM_AL - REGNAM_EAX))->reg_name,
3099 i.op[op].regs->reg_name,
3100 i.suffix);
3101#endif
3102 continue;
3103 }
3104 /* Any other register is bad. */
3105 if (i.types[op] & (Reg | RegMMX | RegXMM
3106 | SReg2 | SReg3
3107 | Control | Debug | Test
3108 | FloatReg | FloatAcc))
3109 {
3110 as_bad (_("`%%%s' not allowed with `%s%c'"),
3111 i.op[op].regs->reg_name,
3112 i.tm.name,
3113 i.suffix);
3114 return 0;
3115 }
3116 }
3117 return 1;
3118}
3119
3120static int
3121check_long_reg ()
3122{
3123 int op;
3124
3125 for (op = i.operands; --op >= 0;)
3126 /* Reject eight bit registers, except where the template requires
3127 them. (eg. movzb) */
3128 if ((i.types[op] & Reg8) != 0
3129 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3130 {
3131 as_bad (_("`%%%s' not allowed with `%s%c'"),
3132 i.op[op].regs->reg_name,
3133 i.tm.name,
3134 i.suffix);
3135 return 0;
3136 }
3137 /* Warn if the e prefix on a general reg is missing. */
3138 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3139 && (i.types[op] & Reg16) != 0
3140 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3141 {
3142 /* Prohibit these changes in the 64bit mode, since the
3143 lowering is more complicated. */
3144 if (flag_code == CODE_64BIT)
252b5132 3145 {
0f3f3d8b 3146 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3147 i.op[op].regs->reg_name,
3148 i.suffix);
3149 return 0;
252b5132 3150 }
29b0f896
AM		 3151#if REGISTER_WARNINGS
3152 else
3153 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3154 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3155 i.op[op].regs->reg_name,
3156 i.suffix);
3157#endif
252b5132 3158 }
29b0f896
AM		 3159 /* Warn if the r prefix on a general reg is missing. */
3160 else if ((i.types[op] & Reg64) != 0
3161 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3162 {
0f3f3d8b 3163 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3164 i.op[op].regs->reg_name,
3165 i.suffix);
3166 return 0;
3167 }
3168 return 1;
3169}
252b5132 3170
29b0f896
AM		 3171static int
3172check_qword_reg ()
3173{
3174 int op;
252b5132 3175
29b0f896
AM		 3176 for (op = i.operands; --op >= 0; )
3177 /* Reject eight bit registers, except where the template requires
3178 them. (eg. movzb) */
3179 if ((i.types[op] & Reg8) != 0
3180 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3181 {
3182 as_bad (_("`%%%s' not allowed with `%s%c'"),
3183 i.op[op].regs->reg_name,
3184 i.tm.name,
3185 i.suffix);
3186 return 0;
3187 }
3188 /* Warn if the e prefix on a general reg is missing. */
3189 else if (((i.types[op] & Reg16) != 0
3190 || (i.types[op] & Reg32) != 0)
3191 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3192 {
3193 /* Prohibit these changes in the 64bit mode, since the
3194 lowering is more complicated. */
0f3f3d8b 3195 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3196 i.op[op].regs->reg_name,
3197 i.suffix);
3198 return 0;
252b5132 3199 }
29b0f896
AM		 3200 return 1;
3201}
252b5132 3202
29b0f896
AM		 3203static int
3204check_word_reg ()
3205{
3206 int op;
3207 for (op = i.operands; --op >= 0;)
3208 /* Reject eight bit registers, except where the template requires
3209 them. (eg. movzb) */
3210 if ((i.types[op] & Reg8) != 0
3211 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3212 {
3213 as_bad (_("`%%%s' not allowed with `%s%c'"),
3214 i.op[op].regs->reg_name,
3215 i.tm.name,
3216 i.suffix);
3217 return 0;
3218 }
3219 /* Warn if the e prefix on a general reg is present. */
3220 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3221 && (i.types[op] & Reg32) != 0
3222 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3223 {
29b0f896
AM		 3224 /* Prohibit these changes in the 64bit mode, since the
3225 lowering is more complicated. */
3226 if (flag_code == CODE_64BIT)
252b5132 3227 {
0f3f3d8b 3228 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3229 i.op[op].regs->reg_name,
3230 i.suffix);
3231 return 0;
252b5132 3232 }
29b0f896
AM		 3233 else
3234#if REGISTER_WARNINGS
3235 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3236 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3237 i.op[op].regs->reg_name,
3238 i.suffix);
3239#endif
3240 }
3241 return 1;
3242}
252b5132 3243
29b0f896
AM		 3244static int
3245finalize_imm ()
3246{
3247 unsigned int overlap0, overlap1, overlap2;
3248
3249 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3250 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3251 && overlap0 != Imm8 && overlap0 != Imm8S
3252 && overlap0 != Imm16 && overlap0 != Imm32S
3253 && overlap0 != Imm32 && overlap0 != Imm64)
3254 {
3255 if (i.suffix)
3256 {
3257 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3258 ? Imm8 | Imm8S
3259 : (i.suffix == WORD_MNEM_SUFFIX
3260 ? Imm16
3261 : (i.suffix == QWORD_MNEM_SUFFIX
3262 ? Imm64 | Imm32S
3263 : Imm32)));
3264 }
3265 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3266 || overlap0 == (Imm16 | Imm32)
3267 || overlap0 == (Imm16 | Imm32S))
3268 {
3269 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3270 ? Imm16 : Imm32S);
3271 }
3272 if (overlap0 != Imm8 && overlap0 != Imm8S
3273 && overlap0 != Imm16 && overlap0 != Imm32S
3274 && overlap0 != Imm32 && overlap0 != Imm64)
3275 {
3276 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3277 return 0;
3278 }
3279 }
3280 i.types[0] = overlap0;
3281
3282 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3283 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3284 && overlap1 != Imm8 && overlap1 != Imm8S
3285 && overlap1 != Imm16 && overlap1 != Imm32S
3286 && overlap1 != Imm32 && overlap1 != Imm64)
3287 {
3288 if (i.suffix)
3289 {
3290 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3291 ? Imm8 | Imm8S
3292 : (i.suffix == WORD_MNEM_SUFFIX
3293 ? Imm16
3294 : (i.suffix == QWORD_MNEM_SUFFIX
3295 ? Imm64 | Imm32S
3296 : Imm32)));
3297 }
3298 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3299 || overlap1 == (Imm16 | Imm32)
3300 || overlap1 == (Imm16 | Imm32S))
3301 {
3302 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3303 ? Imm16 : Imm32S);
3304 }
3305 if (overlap1 != Imm8 && overlap1 != Imm8S
3306 && overlap1 != Imm16 && overlap1 != Imm32S
3307 && overlap1 != Imm32 && overlap1 != Imm64)
3308 {
3309 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3310 return 0;
3311 }
3312 }
3313 i.types[1] = overlap1;
3314
3315 overlap2 = i.types[2] & i.tm.operand_types[2];
3316 assert ((overlap2 & Imm) == 0);
3317 i.types[2] = overlap2;
3318
3319 return 1;
3320}
3321
3322static int
3323process_operands ()
3324{
3325 /* Default segment register this instruction will use for memory
3326 accesses. 0 means unknown. This is only for optimizing out
3327 unnecessary segment overrides. */
3328 const seg_entry *default_seg = 0;
3329
3330 /* The imul $imm, %reg instruction is converted into
3331 imul $imm, %reg, %reg, and the clr %reg instruction
3332 is converted into xor %reg, %reg. */
3333 if (i.tm.opcode_modifier & regKludge)
3334 {
3335 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3336 /* Pretend we saw the extra register operand. */
3337 assert (i.op[first_reg_op + 1].regs == 0);
3338 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3339 i.types[first_reg_op + 1] = i.types[first_reg_op];
3340 i.reg_operands = 2;
3341 }
3342
3343 if (i.tm.opcode_modifier & ShortForm)
3344 {
3345 /* The register or float register operand is in operand 0 or 1. */
3346 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3347 /* Register goes in low 3 bits of opcode. */
3348 i.tm.base_opcode |= i.op[op].regs->reg_num;
3349 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3350 i.rex |= REX_EXTZ;
3351 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3352 {
3353 /* Warn about some common errors, but press on regardless.
3354 The first case can be generated by gcc (<= 2.8.1). */
3355 if (i.operands == 2)
3356 {
3357 /* Reversed arguments on faddp, fsubp, etc. */
3358 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3359 i.op[1].regs->reg_name,
3360 i.op[0].regs->reg_name);
3361 }
3362 else
3363 {
3364 /* Extraneous `l' suffix on fp insn. */
3365 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3366 i.op[0].regs->reg_name);
3367 }
3368 }
3369 }
3370 else if (i.tm.opcode_modifier & Modrm)
3371 {
3372 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3373 must be put into the modrm byte). Now, we make the modrm and
3374 index base bytes based on all the info we've collected. */
29b0f896
AM		 3375
3376 default_seg = build_modrm_byte ();
3377 }
3378 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3379 {
3380 if (i.tm.base_opcode == POP_SEG_SHORT
3381 && i.op[0].regs->reg_num == 1)
3382 {
3383 as_bad (_("you can't `pop %%cs'"));
3384 return 0;
3385 }
3386 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3387 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3388 i.rex |= REX_EXTZ;
3389 }
3390 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3391 {
3392 default_seg = &ds;
3393 }
3394 else if ((i.tm.opcode_modifier & IsString) != 0)
3395 {
3396 /* For the string instructions that allow a segment override
3397 on one of their operands, the default segment is ds. */
3398 default_seg = &ds;
3399 }
3400
30123838
JB		 3401 if ((i.tm.base_opcode == 0x8d /* lea */
3402 || (i.tm.cpu_flags & CpuSVME))
3403 && i.seg[0] && !quiet_warnings)
3404 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3405
3406 /* If a segment was explicitly specified, and the specified segment
3407 is not the default, use an opcode prefix to select it. If we
3408 never figured out what the default segment is, then default_seg
3409 will be zero at this point, and the specified segment prefix will
3410 always be used. */
29b0f896
AM		 3411 if ((i.seg[0]) && (i.seg[0] != default_seg))
3412 {
3413 if (!add_prefix (i.seg[0]->seg_prefix))
3414 return 0;
3415 }
3416 return 1;
3417}
3418
3419static const seg_entry *
3420build_modrm_byte ()
3421{
3422 const seg_entry *default_seg = 0;
3423
3424 /* i.reg_operands MUST be the number of real register operands;
3425 implicit registers do not count. */
3426 if (i.reg_operands == 2)
3427 {
3428 unsigned int source, dest;
3429 source = ((i.types[0]
3430 & (Reg | RegMMX | RegXMM
3431 | SReg2 | SReg3
3432 | Control | Debug | Test))
3433 ? 0 : 1);
050dfa73 3434
fc225355
L		 3435 /* In 4 operands instructions with 2 immediate operands, the first
3436 two are immediate bytes and hence source operand will be in the
3437 next byte after the immediates */
050dfa73 3438 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3439 dest = source + 1;
3440
3441 i.rm.mode = 3;
3442 /* One of the register operands will be encoded in the i.tm.reg
3443 field, the other in the combined i.tm.mode and i.tm.regmem
3444 fields. If no form of this instruction supports a memory
3445 destination operand, then we assume the source operand may
3446 sometimes be a memory operand and so we need to store the
3447 destination in the i.rm.reg field. */
3448 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3449 {
3450 i.rm.reg = i.op[dest].regs->reg_num;
3451 i.rm.regmem = i.op[source].regs->reg_num;
3452 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3453 i.rex |= REX_EXTX;
3454 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3455 i.rex |= REX_EXTZ;
3456 }
3457 else
3458 {
3459 i.rm.reg = i.op[source].regs->reg_num;
3460 i.rm.regmem = i.op[dest].regs->reg_num;
3461 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3462 i.rex |= REX_EXTZ;
3463 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3464 i.rex |= REX_EXTX;
3465 }
c4a530c5
JB		 3466 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3467 {
3468 if (!((i.types[0] | i.types[1]) & Control))
3469 abort ();
3470 i.rex &= ~(REX_EXTX | REX_EXTZ);
3471 add_prefix (LOCK_PREFIX_OPCODE);
3472 }
29b0f896
AM		 3473 }
3474 else
3475 { /* If it's not 2 reg operands... */
3476 if (i.mem_operands)
3477 {
3478 unsigned int fake_zero_displacement = 0;
3479 unsigned int op = ((i.types[0] & AnyMem)
3480 ? 0
3481 : (i.types[1] & AnyMem) ? 1 : 2);
3482
3483 default_seg = &ds;
3484
3485 if (i.base_reg == 0)
3486 {
3487 i.rm.mode = 0;
3488 if (!i.disp_operands)
3489 fake_zero_displacement = 1;
3490 if (i.index_reg == 0)
3491 {
3492 /* Operand is just <disp> */
20f0a1fc 3493 if (flag_code == CODE_64BIT)
29b0f896
AM		 3494 {
3495 /* 64bit mode overwrites the 32bit absolute
3496 addressing by RIP relative addressing and
3497 absolute addressing is encoded by one of the
3498 redundant SIB forms. */
3499 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3500 i.sib.base = NO_BASE_REGISTER;
3501 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3502 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3503 ? Disp32S : Disp32);
20f0a1fc 3504 }
fc225355
L		 3505 else if ((flag_code == CODE_16BIT)
3506 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3507 {
3508 i.rm.regmem = NO_BASE_REGISTER_16;
3509 i.types[op] = Disp16;
3510 }
3511 else
3512 {
3513 i.rm.regmem = NO_BASE_REGISTER;
3514 i.types[op] = Disp32;
29b0f896
AM		 3515 }
3516 }
3517 else /* !i.base_reg && i.index_reg */
3518 {
3519 i.sib.index = i.index_reg->reg_num;
3520 i.sib.base = NO_BASE_REGISTER;
3521 i.sib.scale = i.log2_scale_factor;
3522 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3523 i.types[op] &= ~Disp;
3524 if (flag_code != CODE_64BIT)
3525 i.types[op] |= Disp32; /* Must be 32 bit */
3526 else
3527 i.types[op] |= Disp32S;
3528 if ((i.index_reg->reg_flags & RegRex) != 0)
3529 i.rex |= REX_EXTY;
3530 }
3531 }
3532 /* RIP addressing for 64bit mode. */
3533 else if (i.base_reg->reg_type == BaseIndex)
3534 {
3535 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3536 i.types[op] &= ~ Disp;
29b0f896 3537 i.types[op] |= Disp32S;
71903a11 3538 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3539 if (! i.disp_operands)
3540 fake_zero_displacement = 1;
29b0f896
AM		 3541 }
3542 else if (i.base_reg->reg_type & Reg16)
3543 {
3544 switch (i.base_reg->reg_num)
3545 {
3546 case 3: /* (%bx) */
3547 if (i.index_reg == 0)
3548 i.rm.regmem = 7;
3549 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3550 i.rm.regmem = i.index_reg->reg_num - 6;
3551 break;
3552 case 5: /* (%bp) */
3553 default_seg = &ss;
3554 if (i.index_reg == 0)
3555 {
3556 i.rm.regmem = 6;
3557 if ((i.types[op] & Disp) == 0)
3558 {
3559 /* fake (%bp) into 0(%bp) */
3560 i.types[op] |= Disp8;
252b5132 3561 fake_zero_displacement = 1;
29b0f896
AM		 3562 }
3563 }
3564 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3565 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3566 break;
3567 default: /* (%si) -> 4 or (%di) -> 5 */
3568 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3569 }
3570 i.rm.mode = mode_from_disp_size (i.types[op]);
3571 }
3572 else /* i.base_reg and 32/64 bit mode */
3573 {
3574 if (flag_code == CODE_64BIT
3575 && (i.types[op] & Disp))
fc225355
L		 3576 i.types[op] = ((i.types[op] & Disp8)
3577 | (i.prefix[ADDR_PREFIX] == 0
3578 ? Disp32S : Disp32));
20f0a1fc 3579
29b0f896
AM		 3580 i.rm.regmem = i.base_reg->reg_num;
3581 if ((i.base_reg->reg_flags & RegRex) != 0)
3582 i.rex |= REX_EXTZ;
3583 i.sib.base = i.base_reg->reg_num;
3584 /* x86-64 ignores REX prefix bit here to avoid decoder
3585 complications. */
3586 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3587 {
3588 default_seg = &ss;
3589 if (i.disp_operands == 0)
3590 {
3591 fake_zero_displacement = 1;
3592 i.types[op] |= Disp8;
3593 }
3594 }
3595 else if (i.base_reg->reg_num == ESP_REG_NUM)
3596 {
3597 default_seg = &ss;
3598 }
3599 i.sib.scale = i.log2_scale_factor;
3600 if (i.index_reg == 0)
3601 {
3602 /* <disp>(%esp) becomes two byte modrm with no index
3603 register. We've already stored the code for esp
3604 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3605 Any base register besides %esp will not use the
3606 extra modrm byte. */
3607 i.sib.index = NO_INDEX_REGISTER;
3608#if !SCALE1_WHEN_NO_INDEX
3609 /* Another case where we force the second modrm byte. */
3610 if (i.log2_scale_factor)
3611 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3612#endif
29b0f896
AM		 3613 }
3614 else
3615 {
3616 i.sib.index = i.index_reg->reg_num;
3617 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3618 if ((i.index_reg->reg_flags & RegRex) != 0)
3619 i.rex |= REX_EXTY;
3620 }
67a4f2b7
AO		 3621
3622 if (i.disp_operands
3623 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3624 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3625 i.rm.mode = 0;
3626 else
3627 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3628 }
252b5132 3629
29b0f896
AM		 3630 if (fake_zero_displacement)
3631 {
3632 /* Fakes a zero displacement assuming that i.types[op]
3633 holds the correct displacement size. */
3634 expressionS *exp;
3635
3636 assert (i.op[op].disps == 0);
3637 exp = &disp_expressions[i.disp_operands++];
3638 i.op[op].disps = exp;
3639 exp->X_op = O_constant;
3640 exp->X_add_number = 0;
3641 exp->X_add_symbol = (symbolS *) 0;
3642 exp->X_op_symbol = (symbolS *) 0;
3643 }
3644 }
252b5132 3645
29b0f896
AM		 3646 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3647 (if any) based on i.tm.extension_opcode. Again, we must be
3648 careful to make sure that segment/control/debug/test/MMX
3649 registers are coded into the i.rm.reg field. */
3650 if (i.reg_operands)
3651 {
3652 unsigned int op =
3653 ((i.types[0]
3654 & (Reg | RegMMX | RegXMM
3655 | SReg2 | SReg3
3656 | Control | Debug | Test))
3657 ? 0
3658 : ((i.types[1]
3659 & (Reg | RegMMX | RegXMM
3660 | SReg2 | SReg3
3661 | Control | Debug | Test))
3662 ? 1
3663 : 2));
3664 /* If there is an extension opcode to put here, the register
3665 number must be put into the regmem field. */
3666 if (i.tm.extension_opcode != None)
3667 {
3668 i.rm.regmem = i.op[op].regs->reg_num;
3669 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3670 i.rex |= REX_EXTZ;
3671 }
3672 else
3673 {
3674 i.rm.reg = i.op[op].regs->reg_num;
3675 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3676 i.rex |= REX_EXTX;
3677 }
252b5132 3678
29b0f896
AM		 3679 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3680 must set it to 3 to indicate this is a register operand
3681 in the regmem field. */
3682 if (!i.mem_operands)
3683 i.rm.mode = 3;
3684 }
252b5132 3685
29b0f896
AM		 3686 /* Fill in i.rm.reg field with extension opcode (if any). */
3687 if (i.tm.extension_opcode != None)
3688 i.rm.reg = i.tm.extension_opcode;
3689 }
3690 return default_seg;
3691}
252b5132 3692
29b0f896
AM		 3693static void
3694output_branch ()
3695{
3696 char *p;
3697 int code16;
3698 int prefix;
3699 relax_substateT subtype;
3700 symbolS *sym;
3701 offsetT off;
3702
3703 code16 = 0;
3704 if (flag_code == CODE_16BIT)
3705 code16 = CODE16;
3706
3707 prefix = 0;
3708 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3709 {
29b0f896
AM		 3710 prefix = 1;
3711 i.prefixes -= 1;
3712 code16 ^= CODE16;
252b5132 3713 }
29b0f896
AM		 3714 /* Pentium4 branch hints. */
3715 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3716 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3717 {
29b0f896
AM		 3718 prefix++;
3719 i.prefixes--;
3720 }
3721 if (i.prefix[REX_PREFIX] != 0)
3722 {
3723 prefix++;
3724 i.prefixes--;
2f66722d
AM		 3725 }
3726
29b0f896
AM		 3727 if (i.prefixes != 0 && !intel_syntax)
3728 as_warn (_("skipping prefixes on this instruction"));
3729
3730 /* It's always a symbol; End frag & setup for relax.
3731 Make sure there is enough room in this frag for the largest
3732 instruction we may generate in md_convert_frag. This is 2
3733 bytes for the opcode and room for the prefix and largest
3734 displacement. */
3735 frag_grow (prefix + 2 + 4);
3736 /* Prefix and 1 opcode byte go in fr_fix. */
3737 p = frag_more (prefix + 1);
3738 if (i.prefix[DATA_PREFIX] != 0)
3739 *p++ = DATA_PREFIX_OPCODE;
3740 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3741 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3742 *p++ = i.prefix[SEG_PREFIX];
3743 if (i.prefix[REX_PREFIX] != 0)
3744 *p++ = i.prefix[REX_PREFIX];
3745 *p = i.tm.base_opcode;
3746
3747 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3748 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3749 else if ((cpu_arch_flags & Cpu386) != 0)
3750 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3751 else
3752 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3753 subtype |= code16;
3e73aa7c 3754
29b0f896
AM		 3755 sym = i.op[0].disps->X_add_symbol;
3756 off = i.op[0].disps->X_add_number;
3e73aa7c 3757
29b0f896
AM		 3758 if (i.op[0].disps->X_op != O_constant
3759 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3760 {
29b0f896
AM		 3761 /* Handle complex expressions. */
3762 sym = make_expr_symbol (i.op[0].disps);
3763 off = 0;
3764 }
3e73aa7c 3765
29b0f896
AM		 3766 /* 1 possible extra opcode + 4 byte displacement go in var part.
3767 Pass reloc in fr_var. */
3768 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3769}
3e73aa7c 3770
29b0f896
AM		 3771static void
3772output_jump ()
3773{
3774 char *p;
3775 int size;
3e02c1cc 3776 fixS *fixP;
29b0f896
AM		 3777
3778 if (i.tm.opcode_modifier & JumpByte)
3779 {
3780 /* This is a loop or jecxz type instruction. */
3781 size = 1;
3782 if (i.prefix[ADDR_PREFIX] != 0)
3783 {
3784 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3785 i.prefixes -= 1;
3786 }
3787 /* Pentium4 branch hints. */
3788 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3789 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3790 {
3791 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3792 i.prefixes--;
3e73aa7c
JH		 3793 }
3794 }
29b0f896
AM		 3795 else
3796 {
3797 int code16;
3e73aa7c 3798
29b0f896
AM		 3799 code16 = 0;
3800 if (flag_code == CODE_16BIT)
3801 code16 = CODE16;
3e73aa7c 3802
29b0f896
AM		 3803 if (i.prefix[DATA_PREFIX] != 0)
3804 {
3805 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3806 i.prefixes -= 1;
3807 code16 ^= CODE16;
3808 }
252b5132 3809
29b0f896
AM		 3810 size = 4;
3811 if (code16)
3812 size = 2;
3813 }
9fcc94b6 3814
29b0f896
AM		 3815 if (i.prefix[REX_PREFIX] != 0)
3816 {
3817 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3818 i.prefixes -= 1;
3819 }
252b5132 3820
29b0f896
AM		 3821 if (i.prefixes != 0 && !intel_syntax)
3822 as_warn (_("skipping prefixes on this instruction"));
e0890092 3823
29b0f896
AM		 3824 p = frag_more (1 + size);
3825 *p++ = i.tm.base_opcode;
e0890092 3826
3e02c1cc
AM		 3827 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3828 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3829
3830 /* All jumps handled here are signed, but don't use a signed limit
3831 check for 32 and 16 bit jumps as we want to allow wrap around at
3832 4G and 64k respectively. */
3833 if (size == 1)
3834 fixP->fx_signed = 1;
29b0f896 3835}
e0890092 3836
29b0f896
AM		 3837static void
3838output_interseg_jump ()
3839{
3840 char *p;
3841 int size;
3842 int prefix;
3843 int code16;
252b5132 3844
29b0f896
AM		 3845 code16 = 0;
3846 if (flag_code == CODE_16BIT)
3847 code16 = CODE16;
a217f122 3848
29b0f896
AM		 3849 prefix = 0;
3850 if (i.prefix[DATA_PREFIX] != 0)
3851 {
3852 prefix = 1;
3853 i.prefixes -= 1;
3854 code16 ^= CODE16;
3855 }
3856 if (i.prefix[REX_PREFIX] != 0)
3857 {
3858 prefix++;
3859 i.prefixes -= 1;
3860 }
252b5132 3861
29b0f896
AM		 3862 size = 4;
3863 if (code16)
3864 size = 2;
252b5132 3865
29b0f896
AM		 3866 if (i.prefixes != 0 && !intel_syntax)
3867 as_warn (_("skipping prefixes on this instruction"));
252b5132 3868
29b0f896
AM		 3869 /* 1 opcode; 2 segment; offset */
3870 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3871
29b0f896
AM		 3872 if (i.prefix[DATA_PREFIX] != 0)
3873 *p++ = DATA_PREFIX_OPCODE;
252b5132 3874
29b0f896
AM		 3875 if (i.prefix[REX_PREFIX] != 0)
3876 *p++ = i.prefix[REX_PREFIX];
252b5132 3877
29b0f896
AM		 3878 *p++ = i.tm.base_opcode;
3879 if (i.op[1].imms->X_op == O_constant)
3880 {
3881 offsetT n = i.op[1].imms->X_add_number;
252b5132 3882
29b0f896
AM		 3883 if (size == 2
3884 && !fits_in_unsigned_word (n)
3885 && !fits_in_signed_word (n))
3886 {
3887 as_bad (_("16-bit jump out of range"));
3888 return;
3889 }
3890 md_number_to_chars (p, n, size);
3891 }
3892 else
3893 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3894 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3895 if (i.op[0].imms->X_op != O_constant)
3896 as_bad (_("can't handle non absolute segment in `%s'"),
3897 i.tm.name);
3898 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3899}
a217f122 3900
29b0f896
AM		 3901static void
3902output_insn ()
3903{
2bbd9c25
JJ		 3904 fragS *insn_start_frag;
3905 offsetT insn_start_off;
3906
29b0f896
AM		 3907 /* Tie dwarf2 debug info to the address at the start of the insn.
3908 We can't do this after the insn has been output as the current
3909 frag may have been closed off. eg. by frag_var. */
3910 dwarf2_emit_insn (0);
3911
2bbd9c25
JJ		 3912 insn_start_frag = frag_now;
3913 insn_start_off = frag_now_fix ();
3914
29b0f896
AM		 3915 /* Output jumps. */
3916 if (i.tm.opcode_modifier & Jump)
3917 output_branch ();
3918 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3919 output_jump ();
3920 else if (i.tm.opcode_modifier & JumpInterSegment)
3921 output_interseg_jump ();
3922 else
3923 {
3924 /* Output normal instructions here. */
3925 char *p;
3926 unsigned char *q;
331d2d0d 3927 unsigned int prefix;
252b5132 3928
ef05d495
L		 3929 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3930 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3931 use one more higher byte to specify a prefix the instruction
3932 requires. */
3933 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3934 {
331d2d0d
L		 3935 if (i.tm.base_opcode & 0xff000000)
3936 {
3937 prefix = (i.tm.base_opcode >> 24) & 0xff;
3938 goto check_prefix;
3939 }
3940 }
3941 else if ((i.tm.base_opcode & 0xff0000) != 0)
3942 {
3943 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3944 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3945 {
64e74474 3946 check_prefix:
bc4bd9ab
MK		 3947 if (prefix != REPE_PREFIX_OPCODE
3948 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3949 add_prefix (prefix);
3950 }
3951 else
331d2d0d 3952 add_prefix (prefix);
0f10071e 3953 }
252b5132 3954
29b0f896
AM		 3955 /* The prefix bytes. */
3956 for (q = i.prefix;
3957 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3958 q++)
3959 {
3960 if (*q)
3961 {
3962 p = frag_more (1);
3963 md_number_to_chars (p, (valueT) *q, 1);
3964 }
3965 }
252b5132 3966
29b0f896
AM		 3967 /* Now the opcode; be careful about word order here! */
3968 if (fits_in_unsigned_byte (i.tm.base_opcode))
3969 {
3970 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3971 }
3972 else
3973 {
ef05d495 3974 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3975 {
3976 p = frag_more (3);
3977 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3978 }
3979 else
3980 p = frag_more (2);
0f10071e 3981
29b0f896
AM		 3982 /* Put out high byte first: can't use md_number_to_chars! */
3983 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3984 *p = i.tm.base_opcode & 0xff;
3985 }
3e73aa7c 3986
29b0f896
AM		 3987 /* Now the modrm byte and sib byte (if present). */
3988 if (i.tm.opcode_modifier & Modrm)
3989 {
3990 p = frag_more (1);
3991 md_number_to_chars (p,
3992 (valueT) (i.rm.regmem << 0
3993 | i.rm.reg << 3
3994 | i.rm.mode << 6),
3995 1);
3996 /* If i.rm.regmem == ESP (4)
3997 && i.rm.mode != (Register mode)
3998 && not 16 bit
3999 ==> need second modrm byte. */
4000 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4001 && i.rm.mode != 3
4002 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4003 {
4004 p = frag_more (1);
4005 md_number_to_chars (p,
4006 (valueT) (i.sib.base << 0
4007 | i.sib.index << 3
4008 | i.sib.scale << 6),
4009 1);
4010 }
4011 }
3e73aa7c 4012
29b0f896 4013 if (i.disp_operands)
2bbd9c25 4014 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4015
29b0f896 4016 if (i.imm_operands)
2bbd9c25 4017 output_imm (insn_start_frag, insn_start_off);
29b0f896 4018 }
252b5132 4019
29b0f896
AM		 4020#ifdef DEBUG386
4021 if (flag_debug)
4022 {
7b81dfbb 4023 pi ("" /*line*/, &i);
29b0f896
AM		 4024 }
4025#endif /* DEBUG386 */
4026}
252b5132 4027
29b0f896 4028static void
64e74474 4029output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4030{
4031 char *p;
4032 unsigned int n;
252b5132 4033
29b0f896
AM		 4034 for (n = 0; n < i.operands; n++)
4035 {
4036 if (i.types[n] & Disp)
4037 {
4038 if (i.op[n].disps->X_op == O_constant)
4039 {
4040 int size;
4041 offsetT val;
252b5132 4042
29b0f896
AM		 4043 size = 4;
4044 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4045 {
4046 size = 2;
4047 if (i.types[n] & Disp8)
4048 size = 1;
4049 if (i.types[n] & Disp64)
4050 size = 8;
4051 }
4052 val = offset_in_range (i.op[n].disps->X_add_number,
4053 size);
4054 p = frag_more (size);
4055 md_number_to_chars (p, val, size);
4056 }
4057 else
4058 {
f86103b7 4059 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4060 int size = 4;
4061 int sign = 0;
4062 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4063
4064 /* The PC relative address is computed relative
4065 to the instruction boundary, so in case immediate
4066 fields follows, we need to adjust the value. */
4067 if (pcrel && i.imm_operands)
4068 {
4069 int imm_size = 4;
4070 unsigned int n1;
252b5132 4071
29b0f896
AM		 4072 for (n1 = 0; n1 < i.operands; n1++)
4073 if (i.types[n1] & Imm)
252b5132 4074 {
29b0f896 4075 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4076 {
29b0f896
AM		 4077 imm_size = 2;
4078 if (i.types[n1] & (Imm8 | Imm8S))
4079 imm_size = 1;
4080 if (i.types[n1] & Imm64)
4081 imm_size = 8;
252b5132 4082 }
29b0f896 4083 break;
252b5132 4084 }
29b0f896
AM		 4085 /* We should find the immediate. */
4086 if (n1 == i.operands)
4087 abort ();
4088 i.op[n].disps->X_add_number -= imm_size;
4089 }
520dc8e8 4090
29b0f896
AM		 4091 if (i.types[n] & Disp32S)
4092 sign = 1;
3e73aa7c 4093
29b0f896
AM		 4094 if (i.types[n] & (Disp16 | Disp64))
4095 {
4096 size = 2;
4097 if (i.types[n] & Disp64)
4098 size = 8;
4099 }
520dc8e8 4100
29b0f896 4101 p = frag_more (size);
2bbd9c25 4102 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4103 if (GOT_symbol
2bbd9c25 4104 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4105 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4106 || reloc_type == BFD_RELOC_X86_64_32S
4107 || (reloc_type == BFD_RELOC_64
4108 && object_64bit))
d6ab8113
JB		 4109 && (i.op[n].disps->X_op == O_symbol
4110 || (i.op[n].disps->X_op == O_add
4111 && ((symbol_get_value_expression
4112 (i.op[n].disps->X_op_symbol)->X_op)
4113 == O_subtract))))
4114 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4115 {
4116 offsetT add;
4117
4118 if (insn_start_frag == frag_now)
4119 add = (p - frag_now->fr_literal) - insn_start_off;
4120 else
4121 {
4122 fragS *fr;
4123
4124 add = insn_start_frag->fr_fix - insn_start_off;
4125 for (fr = insn_start_frag->fr_next;
4126 fr && fr != frag_now; fr = fr->fr_next)
4127 add += fr->fr_fix;
4128 add += p - frag_now->fr_literal;
4129 }
4130
4fa24527 4131 if (!object_64bit)
7b81dfbb
AJ		 4132 {
4133 reloc_type = BFD_RELOC_386_GOTPC;
4134 i.op[n].imms->X_add_number += add;
4135 }
4136 else if (reloc_type == BFD_RELOC_64)
4137 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4138 else
7b81dfbb
AJ		 4139 /* Don't do the adjustment for x86-64, as there
4140 the pcrel addressing is relative to the _next_
4141 insn, and that is taken care of in other code. */
d6ab8113 4142 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4143 }
062cd5e7 4144 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4145 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4146 }
4147 }
4148 }
4149}
252b5132 4150
29b0f896 4151static void
64e74474 4152output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4153{
4154 char *p;
4155 unsigned int n;
252b5132 4156
29b0f896
AM		 4157 for (n = 0; n < i.operands; n++)
4158 {
4159 if (i.types[n] & Imm)
4160 {
4161 if (i.op[n].imms->X_op == O_constant)
4162 {
4163 int size;
4164 offsetT val;
b4cac588 4165
29b0f896
AM		 4166 size = 4;
4167 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4168 {
4169 size = 2;
4170 if (i.types[n] & (Imm8 | Imm8S))
4171 size = 1;
4172 else if (i.types[n] & Imm64)
4173 size = 8;
4174 }
4175 val = offset_in_range (i.op[n].imms->X_add_number,
4176 size);
4177 p = frag_more (size);
4178 md_number_to_chars (p, val, size);
4179 }
4180 else
4181 {
4182 /* Not absolute_section.
4183 Need a 32-bit fixup (don't support 8bit
4184 non-absolute imms). Try to support other
4185 sizes ... */
f86103b7 4186 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4187 int size = 4;
4188 int sign = 0;
4189
4190 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4191 && (i.suffix == QWORD_MNEM_SUFFIX
4192 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4193 sign = 1;
4194 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4195 {
4196 size = 2;
4197 if (i.types[n] & (Imm8 | Imm8S))
4198 size = 1;
4199 if (i.types[n] & Imm64)
4200 size = 8;
4201 }
520dc8e8 4202
29b0f896
AM		 4203 p = frag_more (size);
4204 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4205
2bbd9c25
JJ		 4206 /* This is tough to explain. We end up with this one if we
4207 * have operands that look like
4208 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4209 * obtain the absolute address of the GOT, and it is strongly
4210 * preferable from a performance point of view to avoid using
4211 * a runtime relocation for this. The actual sequence of
4212 * instructions often look something like:
4213 *
4214 * call .L66
4215 * .L66:
4216 * popl %ebx
4217 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4218 *
4219 * The call and pop essentially return the absolute address
4220 * of the label .L66 and store it in %ebx. The linker itself
4221 * will ultimately change the first operand of the addl so
4222 * that %ebx points to the GOT, but to keep things simple, the
4223 * .o file must have this operand set so that it generates not
4224 * the absolute address of .L66, but the absolute address of
4225 * itself. This allows the linker itself simply treat a GOTPC
4226 * relocation as asking for a pcrel offset to the GOT to be
4227 * added in, and the addend of the relocation is stored in the
4228 * operand field for the instruction itself.
4229 *
4230 * Our job here is to fix the operand so that it would add
4231 * the correct offset so that %ebx would point to itself. The
4232 * thing that is tricky is that .-.L66 will point to the
4233 * beginning of the instruction, so we need to further modify
4234 * the operand so that it will point to itself. There are
4235 * other cases where you have something like:
4236 *
4237 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4238 *
4239 * and here no correction would be required. Internally in
4240 * the assembler we treat operands of this form as not being
4241 * pcrel since the '.' is explicitly mentioned, and I wonder
4242 * whether it would simplify matters to do it this way. Who
4243 * knows. In earlier versions of the PIC patches, the
4244 * pcrel_adjust field was used to store the correction, but
4245 * since the expression is not pcrel, I felt it would be
4246 * confusing to do it this way. */
4247
d6ab8113 4248 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4249 || reloc_type == BFD_RELOC_X86_64_32S
4250 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4251 && GOT_symbol
4252 && GOT_symbol == i.op[n].imms->X_add_symbol
4253 && (i.op[n].imms->X_op == O_symbol
4254 || (i.op[n].imms->X_op == O_add
4255 && ((symbol_get_value_expression
4256 (i.op[n].imms->X_op_symbol)->X_op)
4257 == O_subtract))))
4258 {
2bbd9c25
JJ		 4259 offsetT add;
4260
4261 if (insn_start_frag == frag_now)
4262 add = (p - frag_now->fr_literal) - insn_start_off;
4263 else
4264 {
4265 fragS *fr;
4266
4267 add = insn_start_frag->fr_fix - insn_start_off;
4268 for (fr = insn_start_frag->fr_next;
4269 fr && fr != frag_now; fr = fr->fr_next)
4270 add += fr->fr_fix;
4271 add += p - frag_now->fr_literal;
4272 }
4273
4fa24527 4274 if (!object_64bit)
d6ab8113 4275 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4276 else if (size == 4)
d6ab8113 4277 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4278 else if (size == 8)
4279 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4280 i.op[n].imms->X_add_number += add;
29b0f896 4281 }
29b0f896
AM		 4282 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4283 i.op[n].imms, 0, reloc_type);
4284 }
4285 }
4286 }
252b5132
RH		 4287}
4288\f
d182319b
JB		 4289/* x86_cons_fix_new is called via the expression parsing code when a
4290 reloc is needed. We use this hook to get the correct .got reloc. */
4291static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4292static int cons_sign = -1;
4293
4294void
4295x86_cons_fix_new (fragS *frag,
64e74474
AM		 4296 unsigned int off,
4297 unsigned int len,
4298 expressionS *exp)
d182319b
JB		 4299{
4300 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4301
4302 got_reloc = NO_RELOC;
4303
4304#ifdef TE_PE
4305 if (exp->X_op == O_secrel)
4306 {
4307 exp->X_op = O_symbol;
4308 r = BFD_RELOC_32_SECREL;
4309 }
4310#endif
4311
4312 fix_new_exp (frag, off, len, exp, 0, r);
4313}
4314
718ddfc0
JB		 4315#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4316# define lex_got(reloc, adjust, types) NULL
4317#else
f3c180ae
AM		 4318/* Parse operands of the form
4319 <symbol>@GOTOFF+<nnn>
4320 and similar .plt or .got references.
4321
4322 If we find one, set up the correct relocation in RELOC and copy the
4323 input string, minus the `@GOTOFF' into a malloc'd buffer for
4324 parsing by the calling routine. Return this buffer, and if ADJUST
4325 is non-null set it to the length of the string we removed from the
4326 input line. Otherwise return NULL. */
4327static char *
3956db08 4328lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4329 int *adjust,
4330 unsigned int *types)
f3c180ae 4331{
7b81dfbb
AJ		 4332 /* Some of the relocations depend on the size of what field is to
4333 be relocated. But in our callers i386_immediate and i386_displacement
4334 we don't yet know the operand size (this will be set by insn
4335 matching). Hence we record the word32 relocation here,
4336 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4337 static const struct {
4338 const char *str;
4fa24527 4339 const enum bfd_reloc_code_real rel[2];
3956db08 4340 const unsigned int types64;
f3c180ae 4341 } gotrel[] = {
7b81dfbb 4342 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4343 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4344 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4345 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4346 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4347 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4348 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4349 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4350 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4351 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4352 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4353 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4354 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4355 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4356 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4357 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4358 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4359 };
4360 char *cp;
4361 unsigned int j;
4362
718ddfc0
JB		 4363 if (!IS_ELF)
4364 return NULL;
4365
f3c180ae
AM		 4366 for (cp = input_line_pointer; *cp != '@'; cp++)
4367 if (is_end_of_line[(unsigned char) *cp])
4368 return NULL;
4369
4370 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4371 {
4372 int len;
4373
4374 len = strlen (gotrel[j].str);
28f81592 4375 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4376 {
4fa24527 4377 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4378 {
28f81592
AM		 4379 int first, second;
4380 char *tmpbuf, *past_reloc;
f3c180ae 4381
4fa24527 4382 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4383 if (adjust)
4384 *adjust = len;
f3c180ae 4385
3956db08
JB		 4386 if (types)
4387 {
4388 if (flag_code != CODE_64BIT)
4389 *types = Imm32|Disp32;
4390 else
4391 *types = gotrel[j].types64;
4392 }
4393
f3c180ae
AM		 4394 if (GOT_symbol == NULL)
4395 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4396
4397 /* Replace the relocation token with ' ', so that
4398 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4399
4400 /* The length of the first part of our input line. */
f3c180ae 4401 first = cp - input_line_pointer;
28f81592
AM		 4402
4403 /* The second part goes from after the reloc token until
4404 (and including) an end_of_line char. Don't use strlen
4405 here as the end_of_line char may not be a NUL. */
4406 past_reloc = cp + 1 + len;
4407 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4408 ;
4409 second = cp - past_reloc;
4410
4411 /* Allocate and copy string. The trailing NUL shouldn't
4412 be necessary, but be safe. */
4413 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4414 memcpy (tmpbuf, input_line_pointer, first);
4415 tmpbuf[first] = ' ';
28f81592
AM		 4416 memcpy (tmpbuf + first + 1, past_reloc, second);
4417 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4418 return tmpbuf;
4419 }
4420
4fa24527
JB		 4421 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4422 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4423 return NULL;
4424 }
4425 }
4426
4427 /* Might be a symbol version string. Don't as_bad here. */
4428 return NULL;
4429}
4430
f3c180ae
AM		 4431void
4432x86_cons (exp, size)
4433 expressionS *exp;
4434 int size;
4435{
4fa24527 4436 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4437 {
4438 /* Handle @GOTOFF and the like in an expression. */
4439 char *save;
4440 char *gotfree_input_line;
4441 int adjust;
4442
4443 save = input_line_pointer;
3956db08 4444 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4445 if (gotfree_input_line)
4446 input_line_pointer = gotfree_input_line;
4447
4448 expression (exp);
4449
4450 if (gotfree_input_line)
4451 {
4452 /* expression () has merrily parsed up to the end of line,
4453 or a comma - in the wrong buffer. Transfer how far
4454 input_line_pointer has moved to the right buffer. */
4455 input_line_pointer = (save
4456 + (input_line_pointer - gotfree_input_line)
4457 + adjust);
4458 free (gotfree_input_line);
4459 }
4460 }
4461 else
4462 expression (exp);
4463}
4464#endif
4465
d182319b 4466static void signed_cons (int size)
6482c264 4467{
d182319b
JB		 4468 if (flag_code == CODE_64BIT)
4469 cons_sign = 1;
4470 cons (size);
4471 cons_sign = -1;
6482c264
NC		 4472}
4473
d182319b 4474#ifdef TE_PE
6482c264
NC		 4475static void
4476pe_directive_secrel (dummy)
4477 int dummy ATTRIBUTE_UNUSED;
4478{
4479 expressionS exp;
4480
4481 do
4482 {
4483 expression (&exp);
4484 if (exp.X_op == O_symbol)
4485 exp.X_op = O_secrel;
4486
4487 emit_expr (&exp, 4);
4488 }
4489 while (*input_line_pointer++ == ',');
4490
4491 input_line_pointer--;
4492 demand_empty_rest_of_line ();
4493}
6482c264
NC		 4494#endif
4495
252b5132 4496static int
70e41ade 4497i386_immediate (char *imm_start)
252b5132
RH		 4498{
4499 char *save_input_line_pointer;
f3c180ae 4500 char *gotfree_input_line;
252b5132 4501 segT exp_seg = 0;
47926f60 4502 expressionS *exp;
3956db08 4503 unsigned int types = ~0U;
252b5132
RH		 4504
4505 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4506 {
d0b47220 4507 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4508 return 0;
4509 }
4510
4511 exp = &im_expressions[i.imm_operands++];
520dc8e8 4512 i.op[this_operand].imms = exp;
252b5132
RH		 4513
4514 if (is_space_char (*imm_start))
4515 ++imm_start;
4516
4517 save_input_line_pointer = input_line_pointer;
4518 input_line_pointer = imm_start;
4519
3956db08 4520 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4521 if (gotfree_input_line)
4522 input_line_pointer = gotfree_input_line;
252b5132
RH		 4523
4524 exp_seg = expression (exp);
4525
83183c0c 4526 SKIP_WHITESPACE ();
252b5132 4527 if (*input_line_pointer)
f3c180ae 4528 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4529
4530 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4531 if (gotfree_input_line)
4532 free (gotfree_input_line);
252b5132 4533
2daf4fd8 4534 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4535 {
47926f60 4536 /* Missing or bad expr becomes absolute 0. */
d0b47220 4537 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4538 imm_start);
252b5132
RH		 4539 exp->X_op = O_constant;
4540 exp->X_add_number = 0;
4541 exp->X_add_symbol = (symbolS *) 0;
4542 exp->X_op_symbol = (symbolS *) 0;
252b5132 4543 }
3e73aa7c 4544 else if (exp->X_op == O_constant)
252b5132 4545 {
47926f60 4546 /* Size it properly later. */
3e73aa7c
JH		 4547 i.types[this_operand] |= Imm64;
4548 /* If BFD64, sign extend val. */
4549 if (!use_rela_relocations)
4550 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4551 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4552 }
4c63da97 4553#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4554 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4555 && exp_seg != absolute_section
47926f60 4556 && exp_seg != text_section
24eab124
AM		 4557 && exp_seg != data_section
4558 && exp_seg != bss_section
4559 && exp_seg != undefined_section
f86103b7 4560 && !bfd_is_com_section (exp_seg))
252b5132 4561 {
d0b47220 4562 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4563 return 0;
4564 }
4565#endif
bb8f5920
L		 4566 else if (!intel_syntax && exp->X_op == O_register)
4567 {
4568 as_bad (_("illegal immediate register operand %s"), imm_start);
4569 return 0;
4570 }
252b5132
RH		 4571 else
4572 {
4573 /* This is an address. The size of the address will be
24eab124 4574 determined later, depending on destination register,
3e73aa7c
JH		 4575 suffix, or the default for the section. */
4576 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4577 i.types[this_operand] &= types;
252b5132
RH		 4578 }
4579
4580 return 1;
4581}
4582
551c1ca1 4583static char *i386_scale PARAMS ((char *));
252b5132 4584
551c1ca1 4585static char *
252b5132
RH		 4586i386_scale (scale)
4587 char *scale;
4588{
551c1ca1
AM		 4589 offsetT val;
4590 char *save = input_line_pointer;
252b5132 4591
551c1ca1
AM		 4592 input_line_pointer = scale;
4593 val = get_absolute_expression ();
4594
4595 switch (val)
252b5132 4596 {
551c1ca1 4597 case 1:
252b5132
RH		 4598 i.log2_scale_factor = 0;
4599 break;
551c1ca1 4600 case 2:
252b5132
RH		 4601 i.log2_scale_factor = 1;
4602 break;
551c1ca1 4603 case 4:
252b5132
RH		 4604 i.log2_scale_factor = 2;
4605 break;
551c1ca1 4606 case 8:
252b5132
RH		 4607 i.log2_scale_factor = 3;
4608 break;
4609 default:
a724f0f4
JB		 4610 {
4611 char sep = *input_line_pointer;
4612
4613 *input_line_pointer = '\0';
4614 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4615 scale);
4616 *input_line_pointer = sep;
4617 input_line_pointer = save;
4618 return NULL;
4619 }
252b5132 4620 }
29b0f896 4621 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4622 {
4623 as_warn (_("scale factor of %d without an index register"),
24eab124 4624 1 << i.log2_scale_factor);
252b5132
RH		 4625#if SCALE1_WHEN_NO_INDEX
4626 i.log2_scale_factor = 0;
4627#endif
4628 }
551c1ca1
AM		 4629 scale = input_line_pointer;
4630 input_line_pointer = save;
4631 return scale;
252b5132
RH		 4632}
4633
4634static int i386_displacement PARAMS ((char *, char *));
4635
4636static int
4637i386_displacement (disp_start, disp_end)
4638 char *disp_start;
4639 char *disp_end;
4640{
29b0f896 4641 expressionS *exp;
252b5132
RH		 4642 segT exp_seg = 0;
4643 char *save_input_line_pointer;
f3c180ae 4644 char *gotfree_input_line;
e05278af 4645 int bigdisp, override;
3956db08 4646 unsigned int types = Disp;
252b5132 4647
e05278af
JB		 4648 if ((i.types[this_operand] & JumpAbsolute)
4649 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4650 {
4651 bigdisp = Disp32;
4652 override = (i.prefix[ADDR_PREFIX] != 0);
4653 }
4654 else
4655 {
4656 /* For PC-relative branches, the width of the displacement
4657 is dependent upon data size, not address size. */
4658 bigdisp = 0;
4659 override = (i.prefix[DATA_PREFIX] != 0);
4660 }
3e73aa7c 4661 if (flag_code == CODE_64BIT)
7ecd2f8b 4662 {
e05278af 4663 if (!bigdisp)
64e74474
AM		 4664 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4665 ? Disp16
4666 : Disp32S | Disp32);
e05278af 4667 else if (!override)
3956db08 4668 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4669 }
e05278af
JB		 4670 else
4671 {
4672 if (!bigdisp)
4673 {
4674 if (!override)
4675 override = (i.suffix == (flag_code != CODE_16BIT
4676 ? WORD_MNEM_SUFFIX
4677 : LONG_MNEM_SUFFIX));
4678 bigdisp = Disp32;
4679 }
4680 if ((flag_code == CODE_16BIT) ^ override)
4681 bigdisp = Disp16;
4682 }
252b5132
RH		 4683 i.types[this_operand] |= bigdisp;
4684
4685 exp = &disp_expressions[i.disp_operands];
520dc8e8 4686 i.op[this_operand].disps = exp;
252b5132
RH		 4687 i.disp_operands++;
4688 save_input_line_pointer = input_line_pointer;
4689 input_line_pointer = disp_start;
4690 END_STRING_AND_SAVE (disp_end);
4691
4692#ifndef GCC_ASM_O_HACK
4693#define GCC_ASM_O_HACK 0
4694#endif
4695#if GCC_ASM_O_HACK
4696 END_STRING_AND_SAVE (disp_end + 1);
4697 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4698 && displacement_string_end[-1] == '+')
252b5132
RH		 4699 {
4700 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4701 constraint within gcc asm statements.
4702 For instance:
4703
4704 #define _set_tssldt_desc(n,addr,limit,type) \
4705 __asm__ __volatile__ ( \
4706 "movw %w2,%0\n\t" \
4707 "movw %w1,2+%0\n\t" \
4708 "rorl $16,%1\n\t" \
4709 "movb %b1,4+%0\n\t" \
4710 "movb %4,5+%0\n\t" \
4711 "movb $0,6+%0\n\t" \
4712 "movb %h1,7+%0\n\t" \
4713 "rorl $16,%1" \
4714 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4715
4716 This works great except that the output assembler ends
4717 up looking a bit weird if it turns out that there is
4718 no offset. You end up producing code that looks like:
4719
4720 #APP
4721 movw $235,(%eax)
4722 movw %dx,2+(%eax)
4723 rorl $16,%edx
4724 movb %dl,4+(%eax)
4725 movb $137,5+(%eax)
4726 movb $0,6+(%eax)
4727 movb %dh,7+(%eax)
4728 rorl $16,%edx
4729 #NO_APP
4730
47926f60 4731 So here we provide the missing zero. */
24eab124
AM		 4732
4733 *displacement_string_end = '0';
252b5132
RH		 4734 }
4735#endif
3956db08 4736 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4737 if (gotfree_input_line)
4738 input_line_pointer = gotfree_input_line;
252b5132 4739
24eab124 4740 exp_seg = expression (exp);
252b5132 4741
636c26b0
AM		 4742 SKIP_WHITESPACE ();
4743 if (*input_line_pointer)
4744 as_bad (_("junk `%s' after expression"), input_line_pointer);
4745#if GCC_ASM_O_HACK
4746 RESTORE_END_STRING (disp_end + 1);
4747#endif
4748 RESTORE_END_STRING (disp_end);
4749 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4750 if (gotfree_input_line)
4751 free (gotfree_input_line);
636c26b0 4752
24eab124
AM		 4753 /* We do this to make sure that the section symbol is in
4754 the symbol table. We will ultimately change the relocation
47926f60 4755 to be relative to the beginning of the section. */
1ae12ab7 4756 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4757 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4758 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4759 {
636c26b0
AM		 4760 if (exp->X_op != O_symbol)
4761 {
4762 as_bad (_("bad expression used with @%s"),
4763 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4764 ? "GOTPCREL"
4765 : "GOTOFF"));
4766 return 0;
4767 }
4768
e5cb08ac 4769 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4770 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4771 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4772 exp->X_op = O_subtract;
4773 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4774 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4775 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4776 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4777 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4778 else
29b0f896 4779 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4780 }
252b5132 4781
2daf4fd8
AM		 4782 if (exp->X_op == O_absent || exp->X_op == O_big)
4783 {
47926f60 4784 /* Missing or bad expr becomes absolute 0. */
d0b47220 4785 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4786 disp_start);
4787 exp->X_op = O_constant;
4788 exp->X_add_number = 0;
4789 exp->X_add_symbol = (symbolS *) 0;
4790 exp->X_op_symbol = (symbolS *) 0;
4791 }
4792
4c63da97 4793#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4794 if (exp->X_op != O_constant
45288df1 4795 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4796 && exp_seg != absolute_section
45288df1
AM		 4797 && exp_seg != text_section
4798 && exp_seg != data_section
4799 && exp_seg != bss_section
31312f95 4800 && exp_seg != undefined_section
f86103b7 4801 && !bfd_is_com_section (exp_seg))
24eab124 4802 {
d0b47220 4803 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4804 return 0;
4805 }
252b5132 4806#endif
3956db08
JB		 4807
4808 if (!(i.types[this_operand] & ~Disp))
4809 i.types[this_operand] &= types;
4810
252b5132
RH		 4811 return 1;
4812}
4813
e5cb08ac 4814static int i386_index_check PARAMS ((const char *));
252b5132 4815
eecb386c 4816/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4817 Return 1 on success, 0 on a failure. */
4818
252b5132 4819static int
eecb386c
AM		 4820i386_index_check (operand_string)
4821 const char *operand_string;
252b5132 4822{
3e73aa7c 4823 int ok;
24eab124 4824#if INFER_ADDR_PREFIX
eecb386c
AM		 4825 int fudged = 0;
4826
24eab124
AM		 4827 tryprefix:
4828#endif
3e73aa7c 4829 ok = 1;
30123838
JB		 4830 if ((current_templates->start->cpu_flags & CpuSVME)
4831 && current_templates->end[-1].operand_types[0] == AnyMem)
4832 {
4833 /* Memory operands of SVME insns are special in that they only allow
4834 rAX as their memory address and ignore any segment override. */
4835 unsigned RegXX;
4836
4837 /* SKINIT is even more restrictive: it always requires EAX. */
4838 if (strcmp (current_templates->start->name, "skinit") == 0)
4839 RegXX = Reg32;
4840 else if (flag_code == CODE_64BIT)
4841 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4842 else
64e74474
AM		 4843 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4844 ? Reg16
4845 : Reg32);
30123838
JB		 4846 if (!i.base_reg
4847 || !(i.base_reg->reg_type & Acc)
4848 || !(i.base_reg->reg_type & RegXX)
4849 || i.index_reg
4850 || (i.types[0] & Disp))
4851 ok = 0;
4852 }
4853 else if (flag_code == CODE_64BIT)
64e74474
AM		 4854 {
4855 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4856
4857 if ((i.base_reg
4858 && ((i.base_reg->reg_type & RegXX) == 0)
4859 && (i.base_reg->reg_type != BaseIndex
4860 || i.index_reg))
4861 || (i.index_reg
4862 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4863 != (RegXX | BaseIndex))))
4864 ok = 0;
3e73aa7c
JH		 4865 }
4866 else
4867 {
4868 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4869 {
4870 /* 16bit checks. */
4871 if ((i.base_reg
29b0f896
AM		 4872 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4873 != (Reg16 | BaseIndex)))
3e73aa7c 4874 || (i.index_reg
29b0f896
AM		 4875 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4876 != (Reg16 | BaseIndex))
4877 || !(i.base_reg
4878 && i.base_reg->reg_num < 6
4879 && i.index_reg->reg_num >= 6
4880 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4881 ok = 0;
4882 }
4883 else
e5cb08ac 4884 {
3e73aa7c
JH		 4885 /* 32bit checks. */
4886 if ((i.base_reg
4887 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4888 || (i.index_reg
29b0f896
AM		 4889 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4890 != (Reg32 | BaseIndex))))
e5cb08ac 4891 ok = 0;
3e73aa7c
JH		 4892 }
4893 }
4894 if (!ok)
24eab124
AM		 4895 {
4896#if INFER_ADDR_PREFIX
20f0a1fc 4897 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4898 {
4899 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4900 i.prefixes += 1;
b23bac36
AM		 4901 /* Change the size of any displacement too. At most one of
4902 Disp16 or Disp32 is set.
4903 FIXME. There doesn't seem to be any real need for separate
4904 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4905 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4906 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4907 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4908 fudged = 1;
24eab124
AM		 4909 goto tryprefix;
4910 }
eecb386c
AM		 4911 if (fudged)
4912 as_bad (_("`%s' is not a valid base/index expression"),
4913 operand_string);
4914 else
c388dee8 4915#endif
eecb386c
AM		 4916 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4917 operand_string,
3e73aa7c 4918 flag_code_names[flag_code]);
24eab124 4919 }
20f0a1fc 4920 return ok;
24eab124 4921}
252b5132 4922
252b5132 4923/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4924 on error. */
252b5132 4925
252b5132
RH		 4926static int
4927i386_operand (operand_string)
4928 char *operand_string;
4929{
af6bdddf
AM		 4930 const reg_entry *r;
4931 char *end_op;
24eab124 4932 char *op_string = operand_string;
252b5132 4933
24eab124 4934 if (is_space_char (*op_string))
252b5132
RH		 4935 ++op_string;
4936
24eab124 4937 /* We check for an absolute prefix (differentiating,
47926f60 4938 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4939 if (*op_string == ABSOLUTE_PREFIX)
4940 {
4941 ++op_string;
4942 if (is_space_char (*op_string))
4943 ++op_string;
4944 i.types[this_operand] |= JumpAbsolute;
4945 }
252b5132 4946
47926f60 4947 /* Check if operand is a register. */
4d1bb795 4948 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4949 {
24eab124
AM		 4950 /* Check for a segment override by searching for ':' after a
4951 segment register. */
4952 op_string = end_op;
4953 if (is_space_char (*op_string))
4954 ++op_string;
4955 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4956 {
4957 switch (r->reg_num)
4958 {
4959 case 0:
4960 i.seg[i.mem_operands] = &es;
4961 break;
4962 case 1:
4963 i.seg[i.mem_operands] = &cs;
4964 break;
4965 case 2:
4966 i.seg[i.mem_operands] = &ss;
4967 break;
4968 case 3:
4969 i.seg[i.mem_operands] = &ds;
4970 break;
4971 case 4:
4972 i.seg[i.mem_operands] = &fs;
4973 break;
4974 case 5:
4975 i.seg[i.mem_operands] = &gs;
4976 break;
4977 }
252b5132 4978
24eab124 4979 /* Skip the ':' and whitespace. */
252b5132
RH		 4980 ++op_string;
4981 if (is_space_char (*op_string))
24eab124 4982 ++op_string;
252b5132 4983
24eab124
AM		 4984 if (!is_digit_char (*op_string)
4985 && !is_identifier_char (*op_string)
4986 && *op_string != '('
4987 && *op_string != ABSOLUTE_PREFIX)
4988 {
4989 as_bad (_("bad memory operand `%s'"), op_string);
4990 return 0;
4991 }
47926f60 4992 /* Handle case of %es:*foo. */
24eab124
AM		 4993 if (*op_string == ABSOLUTE_PREFIX)
4994 {
4995 ++op_string;
4996 if (is_space_char (*op_string))
4997 ++op_string;
4998 i.types[this_operand] |= JumpAbsolute;
4999 }
5000 goto do_memory_reference;
5001 }
5002 if (*op_string)
5003 {
d0b47220 5004 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5005 return 0;
5006 }
5007 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5008 i.op[this_operand].regs = r;
24eab124
AM		 5009 i.reg_operands++;
5010 }
af6bdddf
AM		 5011 else if (*op_string == REGISTER_PREFIX)
5012 {
5013 as_bad (_("bad register name `%s'"), op_string);
5014 return 0;
5015 }
24eab124 5016 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5017 {
24eab124
AM		 5018 ++op_string;
5019 if (i.types[this_operand] & JumpAbsolute)
5020 {
d0b47220 5021 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5022 return 0;
5023 }
5024 if (!i386_immediate (op_string))
5025 return 0;
5026 }
5027 else if (is_digit_char (*op_string)
5028 || is_identifier_char (*op_string)
e5cb08ac 5029 || *op_string == '(')
24eab124 5030 {
47926f60 5031 /* This is a memory reference of some sort. */
af6bdddf 5032 char *base_string;
252b5132 5033
47926f60 5034 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5035 char *displacement_string_start;
5036 char *displacement_string_end;
252b5132 5037
24eab124 5038 do_memory_reference:
24eab124
AM		 5039 if ((i.mem_operands == 1
5040 && (current_templates->start->opcode_modifier & IsString) == 0)
5041 || i.mem_operands == 2)
5042 {
5043 as_bad (_("too many memory references for `%s'"),
5044 current_templates->start->name);
5045 return 0;
5046 }
252b5132 5047
24eab124
AM		 5048 /* Check for base index form. We detect the base index form by
5049 looking for an ')' at the end of the operand, searching
5050 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5051 after the '('. */
af6bdddf 5052 base_string = op_string + strlen (op_string);
c3332e24 5053
af6bdddf
AM		 5054 --base_string;
5055 if (is_space_char (*base_string))
5056 --base_string;
252b5132 5057
47926f60 5058 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5059 displacement_string_start = op_string;
5060 displacement_string_end = base_string + 1;
252b5132 5061
24eab124
AM		 5062 if (*base_string == ')')
5063 {
af6bdddf 5064 char *temp_string;
24eab124
AM		 5065 unsigned int parens_balanced = 1;
5066 /* We've already checked that the number of left & right ()'s are
47926f60 5067 equal, so this loop will not be infinite. */
24eab124
AM		 5068 do
5069 {
5070 base_string--;
5071 if (*base_string == ')')
5072 parens_balanced++;
5073 if (*base_string == '(')
5074 parens_balanced--;
5075 }
5076 while (parens_balanced);
c3332e24 5077
af6bdddf 5078 temp_string = base_string;
c3332e24 5079
24eab124 5080 /* Skip past '(' and whitespace. */
252b5132
RH		 5081 ++base_string;
5082 if (is_space_char (*base_string))
24eab124 5083 ++base_string;
252b5132 5084
af6bdddf 5085 if (*base_string == ','
4d1bb795 5086 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5087 {
af6bdddf 5088 displacement_string_end = temp_string;
252b5132 5089
af6bdddf 5090 i.types[this_operand] |= BaseIndex;
252b5132 5091
af6bdddf 5092 if (i.base_reg)
24eab124 5093 {
24eab124
AM		 5094 base_string = end_op;
5095 if (is_space_char (*base_string))
5096 ++base_string;
af6bdddf
AM		 5097 }
5098
5099 /* There may be an index reg or scale factor here. */
5100 if (*base_string == ',')
5101 {
5102 ++base_string;
5103 if (is_space_char (*base_string))
5104 ++base_string;
5105
4d1bb795 5106 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5107 {
af6bdddf 5108 base_string = end_op;
24eab124
AM		 5109 if (is_space_char (*base_string))
5110 ++base_string;
af6bdddf
AM		 5111 if (*base_string == ',')
5112 {
5113 ++base_string;
5114 if (is_space_char (*base_string))
5115 ++base_string;
5116 }
e5cb08ac 5117 else if (*base_string != ')')
af6bdddf
AM		 5118 {
5119 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5120 operand_string);
5121 return 0;
5122 }
24eab124 5123 }
af6bdddf 5124 else if (*base_string == REGISTER_PREFIX)
24eab124 5125 {
af6bdddf 5126 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5127 return 0;
5128 }
252b5132 5129
47926f60 5130 /* Check for scale factor. */
551c1ca1 5131 if (*base_string != ')')
af6bdddf 5132 {
551c1ca1
AM		 5133 char *end_scale = i386_scale (base_string);
5134
5135 if (!end_scale)
af6bdddf 5136 return 0;
24eab124 5137
551c1ca1 5138 base_string = end_scale;
af6bdddf
AM		 5139 if (is_space_char (*base_string))
5140 ++base_string;
5141 if (*base_string != ')')
5142 {
5143 as_bad (_("expecting `)' after scale factor in `%s'"),
5144 operand_string);
5145 return 0;
5146 }
5147 }
5148 else if (!i.index_reg)
24eab124 5149 {
af6bdddf
AM		 5150 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5151 *base_string);
24eab124
AM		 5152 return 0;
5153 }
5154 }
af6bdddf 5155 else if (*base_string != ')')
24eab124 5156 {
af6bdddf
AM		 5157 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5158 operand_string);
24eab124
AM		 5159 return 0;
5160 }
c3332e24 5161 }
af6bdddf 5162 else if (*base_string == REGISTER_PREFIX)
c3332e24 5163 {
af6bdddf 5164 as_bad (_("bad register name `%s'"), base_string);
24eab124 5165 return 0;
c3332e24 5166 }
24eab124
AM		 5167 }
5168
5169 /* If there's an expression beginning the operand, parse it,
5170 assuming displacement_string_start and
5171 displacement_string_end are meaningful. */
5172 if (displacement_string_start != displacement_string_end)
5173 {
5174 if (!i386_displacement (displacement_string_start,
5175 displacement_string_end))
5176 return 0;
5177 }
5178
5179 /* Special case for (%dx) while doing input/output op. */
5180 if (i.base_reg
5181 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5182 && i.index_reg == 0
5183 && i.log2_scale_factor == 0
5184 && i.seg[i.mem_operands] == 0
5185 && (i.types[this_operand] & Disp) == 0)
5186 {
5187 i.types[this_operand] = InOutPortReg;
5188 return 1;
5189 }
5190
eecb386c
AM		 5191 if (i386_index_check (operand_string) == 0)
5192 return 0;
24eab124
AM		 5193 i.mem_operands++;
5194 }
5195 else
ce8a8b2f
AM		 5196 {
5197 /* It's not a memory operand; argh! */
24eab124
AM		 5198 as_bad (_("invalid char %s beginning operand %d `%s'"),
5199 output_invalid (*op_string),
5200 this_operand + 1,
5201 op_string);
5202 return 0;
5203 }
47926f60 5204 return 1; /* Normal return. */
252b5132
RH		 5205}
5206\f
ee7fcc42
AM		 5207/* md_estimate_size_before_relax()
5208
5209 Called just before relax() for rs_machine_dependent frags. The x86
5210 assembler uses these frags to handle variable size jump
5211 instructions.
5212
5213 Any symbol that is now undefined will not become defined.
5214 Return the correct fr_subtype in the frag.
5215 Return the initial "guess for variable size of frag" to caller.
5216 The guess is actually the growth beyond the fixed part. Whatever
5217 we do to grow the fixed or variable part contributes to our
5218 returned value. */
5219
252b5132
RH		 5220int
5221md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5222 fragS *fragP;
5223 segT segment;
252b5132 5224{
252b5132 5225 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5226 check for un-relaxable symbols. On an ELF system, we can't relax
5227 an externally visible symbol, because it may be overridden by a
5228 shared library. */
5229 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5230#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5231 || (IS_ELF
31312f95
AM		 5232 && (S_IS_EXTERNAL (fragP->fr_symbol)
5233 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5234#endif
5235 )
252b5132 5236 {
b98ef147
AM		 5237 /* Symbol is undefined in this segment, or we need to keep a
5238 reloc so that weak symbols can be overridden. */
5239 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5240 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5241 unsigned char *opcode;
5242 int old_fr_fix;
f6af82bd 5243
ee7fcc42
AM		 5244 if (fragP->fr_var != NO_RELOC)
5245 reloc_type = fragP->fr_var;
b98ef147 5246 else if (size == 2)
f6af82bd
AM		 5247 reloc_type = BFD_RELOC_16_PCREL;
5248 else
5249 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5250
ee7fcc42
AM		 5251 old_fr_fix = fragP->fr_fix;
5252 opcode = (unsigned char *) fragP->fr_opcode;
5253
fddf5b5b 5254 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5255 {
fddf5b5b
AM		 5256 case UNCOND_JUMP:
5257 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5258 opcode[0] = 0xe9;
252b5132 5259 fragP->fr_fix += size;
062cd5e7
AS		 5260 fix_new (fragP, old_fr_fix, size,
5261 fragP->fr_symbol,
5262 fragP->fr_offset, 1,
5263 reloc_type);
252b5132
RH		 5264 break;
5265
fddf5b5b 5266 case COND_JUMP86:
412167cb
AM		 5267 if (size == 2
5268 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5269 {
5270 /* Negate the condition, and branch past an
5271 unconditional jump. */
5272 opcode[0] ^= 1;
5273 opcode[1] = 3;
5274 /* Insert an unconditional jump. */
5275 opcode[2] = 0xe9;
5276 /* We added two extra opcode bytes, and have a two byte
5277 offset. */
5278 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5279 fix_new (fragP, old_fr_fix + 2, 2,
5280 fragP->fr_symbol,
5281 fragP->fr_offset, 1,
5282 reloc_type);
fddf5b5b
AM		 5283 break;
5284 }
5285 /* Fall through. */
5286
5287 case COND_JUMP:
412167cb
AM		 5288 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5289 {
3e02c1cc
AM		 5290 fixS *fixP;
5291
412167cb 5292 fragP->fr_fix += 1;
3e02c1cc
AM		 5293 fixP = fix_new (fragP, old_fr_fix, 1,
5294 fragP->fr_symbol,
5295 fragP->fr_offset, 1,
5296 BFD_RELOC_8_PCREL);
5297 fixP->fx_signed = 1;
412167cb
AM		 5298 break;
5299 }
93c2a809 5300
24eab124 5301 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5302 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5303 opcode[1] = opcode[0] + 0x10;
f6af82bd 5304 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5305 /* We've added an opcode byte. */
5306 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5307 fix_new (fragP, old_fr_fix + 1, size,
5308 fragP->fr_symbol,
5309 fragP->fr_offset, 1,
5310 reloc_type);
252b5132 5311 break;
fddf5b5b
AM		 5312
5313 default:
5314 BAD_CASE (fragP->fr_subtype);
5315 break;
252b5132
RH		 5316 }
5317 frag_wane (fragP);
ee7fcc42 5318 return fragP->fr_fix - old_fr_fix;
252b5132 5319 }
93c2a809 5320
93c2a809
AM		 5321 /* Guess size depending on current relax state. Initially the relax
5322 state will correspond to a short jump and we return 1, because
5323 the variable part of the frag (the branch offset) is one byte
5324 long. However, we can relax a section more than once and in that
5325 case we must either set fr_subtype back to the unrelaxed state,
5326 or return the value for the appropriate branch. */
5327 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5328}
5329
47926f60
KH		 5330/* Called after relax() is finished.
5331
5332 In: Address of frag.
5333 fr_type == rs_machine_dependent.
5334 fr_subtype is what the address relaxed to.
5335
5336 Out: Any fixSs and constants are set up.
5337 Caller will turn frag into a ".space 0". */
5338
252b5132
RH		 5339void
5340md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5341 bfd *abfd ATTRIBUTE_UNUSED;
5342 segT sec ATTRIBUTE_UNUSED;
29b0f896 5343 fragS *fragP;
252b5132 5344{
29b0f896 5345 unsigned char *opcode;
252b5132 5346 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5347 offsetT target_address;
5348 offsetT opcode_address;
252b5132 5349 unsigned int extension = 0;
847f7ad4 5350 offsetT displacement_from_opcode_start;
252b5132
RH		 5351
5352 opcode = (unsigned char *) fragP->fr_opcode;
5353
47926f60 5354 /* Address we want to reach in file space. */
252b5132 5355 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5356
47926f60 5357 /* Address opcode resides at in file space. */
252b5132
RH		 5358 opcode_address = fragP->fr_address + fragP->fr_fix;
5359
47926f60 5360 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5361 displacement_from_opcode_start = target_address - opcode_address;
5362
fddf5b5b 5363 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5364 {
47926f60
KH		 5365 /* Don't have to change opcode. */
5366 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5367 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5368 }
5369 else
5370 {
5371 if (no_cond_jump_promotion
5372 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5373 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5374
fddf5b5b
AM		 5375 switch (fragP->fr_subtype)
5376 {
5377 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5378 extension = 4; /* 1 opcode + 4 displacement */
5379 opcode[0] = 0xe9;
5380 where_to_put_displacement = &opcode[1];
5381 break;
252b5132 5382
fddf5b5b
AM		 5383 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5384 extension = 2; /* 1 opcode + 2 displacement */
5385 opcode[0] = 0xe9;
5386 where_to_put_displacement = &opcode[1];
5387 break;
252b5132 5388
fddf5b5b
AM		 5389 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5390 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5391 extension = 5; /* 2 opcode + 4 displacement */
5392 opcode[1] = opcode[0] + 0x10;
5393 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5394 where_to_put_displacement = &opcode[2];
5395 break;
252b5132 5396
fddf5b5b
AM		 5397 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5398 extension = 3; /* 2 opcode + 2 displacement */
5399 opcode[1] = opcode[0] + 0x10;
5400 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5401 where_to_put_displacement = &opcode[2];
5402 break;
252b5132 5403
fddf5b5b
AM		 5404 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5405 extension = 4;
5406 opcode[0] ^= 1;
5407 opcode[1] = 3;
5408 opcode[2] = 0xe9;
5409 where_to_put_displacement = &opcode[3];
5410 break;
5411
5412 default:
5413 BAD_CASE (fragP->fr_subtype);
5414 break;
5415 }
252b5132 5416 }
fddf5b5b 5417
7b81dfbb
AJ		 5418 /* If size if less then four we are sure that the operand fits,
5419 but if it's 4, then it could be that the displacement is larger
5420 then -/+ 2GB. */
5421 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5422 && object_64bit
5423 && ((addressT) (displacement_from_opcode_start - extension
5424 + ((addressT) 1 << 31))
5425 > (((addressT) 2 << 31) - 1)))
5426 {
5427 as_bad_where (fragP->fr_file, fragP->fr_line,
5428 _("jump target out of range"));
5429 /* Make us emit 0. */
5430 displacement_from_opcode_start = extension;
5431 }
47926f60 5432 /* Now put displacement after opcode. */
252b5132
RH		 5433 md_number_to_chars ((char *) where_to_put_displacement,
5434 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5435 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5436 fragP->fr_fix += extension;
5437}
5438\f
47926f60
KH		 5439/* Size of byte displacement jmp. */
5440int md_short_jump_size = 2;
5441
5442/* Size of dword displacement jmp. */
5443int md_long_jump_size = 5;
252b5132 5444
252b5132
RH		 5445void
5446md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5447 char *ptr;
5448 addressT from_addr, to_addr;
ab9da554
ILT		 5449 fragS *frag ATTRIBUTE_UNUSED;
5450 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5451{
847f7ad4 5452 offsetT offset;
252b5132
RH		 5453
5454 offset = to_addr - (from_addr + 2);
47926f60
KH		 5455 /* Opcode for byte-disp jump. */
5456 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5457 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5458}
5459
5460void
5461md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5462 char *ptr;
5463 addressT from_addr, to_addr;
a38cf1db
AM		 5464 fragS *frag ATTRIBUTE_UNUSED;
5465 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5466{
847f7ad4 5467 offsetT offset;
252b5132 5468
a38cf1db
AM		 5469 offset = to_addr - (from_addr + 5);
5470 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5471 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5472}
5473\f
5474/* Apply a fixup (fixS) to segment data, once it has been determined
5475 by our caller that we have all the info we need to fix it up.
5476
5477 On the 386, immediates, displacements, and data pointers are all in
5478 the same (little-endian) format, so we don't need to care about which
5479 we are handling. */
5480
94f592af 5481void
55cf6793 5482md_apply_fix (fixP, valP, seg)
47926f60
KH		 5483 /* The fix we're to put in. */
5484 fixS *fixP;
47926f60 5485 /* Pointer to the value of the bits. */
c6682705 5486 valueT *valP;
47926f60
KH		 5487 /* Segment fix is from. */
5488 segT seg ATTRIBUTE_UNUSED;
252b5132 5489{
94f592af 5490 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5491 valueT value = *valP;
252b5132 5492
f86103b7 5493#if !defined (TE_Mach)
93382f6d
AM		 5494 if (fixP->fx_pcrel)
5495 {
5496 switch (fixP->fx_r_type)
5497 {
5865bb77
ILT		 5498 default:
5499 break;
5500
d6ab8113
JB		 5501 case BFD_RELOC_64:
5502 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5503 break;
93382f6d 5504 case BFD_RELOC_32:
ae8887b5 5505 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5506 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5507 break;
5508 case BFD_RELOC_16:
5509 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5510 break;
5511 case BFD_RELOC_8:
5512 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5513 break;
5514 }
5515 }
252b5132 5516
a161fe53 5517 if (fixP->fx_addsy != NULL
31312f95 5518 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5519 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5520 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5521 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5522 && !use_rela_relocations)
252b5132 5523 {
31312f95
AM		 5524 /* This is a hack. There should be a better way to handle this.
5525 This covers for the fact that bfd_install_relocation will
5526 subtract the current location (for partial_inplace, PC relative
5527 relocations); see more below. */
252b5132 5528#ifndef OBJ_AOUT
718ddfc0 5529 if (IS_ELF
252b5132
RH		 5530#ifdef TE_PE
5531 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5532#endif
5533 )
5534 value += fixP->fx_where + fixP->fx_frag->fr_address;
5535#endif
5536#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5537 if (IS_ELF)
252b5132 5538 {
6539b54b 5539 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5540
6539b54b 5541 if ((sym_seg == seg
2f66722d 5542 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5543 && sym_seg != absolute_section))
ae6063d4 5544 && !generic_force_reloc (fixP))
2f66722d
AM		 5545 {
5546 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5547 bfd_install_relocation subtracts them out again. I think
5548 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5549 it. FIXME. */
5550 value += fixP->fx_where + fixP->fx_frag->fr_address;
5551 }
252b5132
RH		 5552 }
5553#endif
5554#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5555 /* For some reason, the PE format does not store a
5556 section address offset for a PC relative symbol. */
5557 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5558 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5559 value += md_pcrel_from (fixP);
5560#endif
5561 }
5562
5563 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5564 and we must not disappoint it. */
252b5132 5565#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5566 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5567 switch (fixP->fx_r_type)
5568 {
5569 case BFD_RELOC_386_PLT32:
3e73aa7c 5570 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5571 /* Make the jump instruction point to the address of the operand. At
5572 runtime we merely add the offset to the actual PLT entry. */
5573 value = -4;
5574 break;
31312f95 5575
13ae64f3
JJ		 5576 case BFD_RELOC_386_TLS_GD:
5577 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5578 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5579 case BFD_RELOC_386_TLS_IE:
5580 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5581 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5582 case BFD_RELOC_X86_64_TLSGD:
5583 case BFD_RELOC_X86_64_TLSLD:
5584 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5585 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5586 value = 0; /* Fully resolved at runtime. No addend. */
5587 /* Fallthrough */
5588 case BFD_RELOC_386_TLS_LE:
5589 case BFD_RELOC_386_TLS_LDO_32:
5590 case BFD_RELOC_386_TLS_LE_32:
5591 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5592 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5593 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5594 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5595 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5596 break;
5597
67a4f2b7
AO		 5598 case BFD_RELOC_386_TLS_DESC_CALL:
5599 case BFD_RELOC_X86_64_TLSDESC_CALL:
5600 value = 0; /* Fully resolved at runtime. No addend. */
5601 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5602 fixP->fx_done = 0;
5603 return;
5604
00f7efb6
JJ		 5605 case BFD_RELOC_386_GOT32:
5606 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5607 value = 0; /* Fully resolved at runtime. No addend. */
5608 break;
47926f60
KH		 5609
5610 case BFD_RELOC_VTABLE_INHERIT:
5611 case BFD_RELOC_VTABLE_ENTRY:
5612 fixP->fx_done = 0;
94f592af 5613 return;
47926f60
KH		 5614
5615 default:
5616 break;
5617 }
5618#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5619 *valP = value;
f86103b7 5620#endif /* !defined (TE_Mach) */
3e73aa7c 5621
3e73aa7c 5622 /* Are we finished with this relocation now? */
c6682705 5623 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5624 fixP->fx_done = 1;
5625 else if (use_rela_relocations)
5626 {
5627 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5628 /* Remember value for tc_gen_reloc. */
5629 fixP->fx_addnumber = value;
3e73aa7c
JH		 5630 value = 0;
5631 }
f86103b7 5632
94f592af 5633 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5634}
252b5132 5635\f
252b5132
RH		 5636#define MAX_LITTLENUMS 6
5637
47926f60
KH		 5638/* Turn the string pointed to by litP into a floating point constant
5639 of type TYPE, and emit the appropriate bytes. The number of
5640 LITTLENUMS emitted is stored in *SIZEP. An error message is
5641 returned, or NULL on OK. */
5642
252b5132
RH		 5643char *
5644md_atof (type, litP, sizeP)
2ab9b79e 5645 int type;
252b5132
RH		 5646 char *litP;
5647 int *sizeP;
5648{
5649 int prec;
5650 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5651 LITTLENUM_TYPE *wordP;
5652 char *t;
5653
5654 switch (type)
5655 {
5656 case 'f':
5657 case 'F':
5658 prec = 2;
5659 break;
5660
5661 case 'd':
5662 case 'D':
5663 prec = 4;
5664 break;
5665
5666 case 'x':
5667 case 'X':
5668 prec = 5;
5669 break;
5670
5671 default:
5672 *sizeP = 0;
5673 return _("Bad call to md_atof ()");
5674 }
5675 t = atof_ieee (input_line_pointer, type, words);
5676 if (t)
5677 input_line_pointer = t;
5678
5679 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5680 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5681 the bigendian 386. */
5682 for (wordP = words + prec - 1; prec--;)
5683 {
5684 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5685 litP += sizeof (LITTLENUM_TYPE);
5686 }
5687 return 0;
5688}
5689\f
2d545b82 5690static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5691
252b5132
RH		 5692static char *
5693output_invalid (c)
5694 int c;
5695{
3882b010 5696 if (ISPRINT (c))
f9f21a03
L		 5697 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5698 "'%c'", c);
252b5132 5699 else
f9f21a03 5700 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5701 "(0x%x)", (unsigned char) c);
252b5132
RH		 5702 return output_invalid_buf;
5703}
5704
af6bdddf 5705/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5706
5707static const reg_entry *
4d1bb795 5708parse_real_register (char *reg_string, char **end_op)
252b5132 5709{
af6bdddf
AM		 5710 char *s = reg_string;
5711 char *p;
252b5132
RH		 5712 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5713 const reg_entry *r;
5714
5715 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5716 if (*s == REGISTER_PREFIX)
5717 ++s;
5718
5719 if (is_space_char (*s))
5720 ++s;
5721
5722 p = reg_name_given;
af6bdddf 5723 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5724 {
5725 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5726 return (const reg_entry *) NULL;
5727 s++;
252b5132
RH		 5728 }
5729
6588847e
DN		 5730 /* For naked regs, make sure that we are not dealing with an identifier.
5731 This prevents confusing an identifier like `eax_var' with register
5732 `eax'. */
5733 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5734 return (const reg_entry *) NULL;
5735
af6bdddf 5736 *end_op = s;
252b5132
RH		 5737
5738 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5739
5f47d35b 5740 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5741 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5742 {
5f47d35b
AM		 5743 if (is_space_char (*s))
5744 ++s;
5745 if (*s == '(')
5746 {
af6bdddf 5747 ++s;
5f47d35b
AM		 5748 if (is_space_char (*s))
5749 ++s;
5750 if (*s >= '0' && *s <= '7')
5751 {
5752 r = &i386_float_regtab[*s - '0'];
af6bdddf 5753 ++s;
5f47d35b
AM		 5754 if (is_space_char (*s))
5755 ++s;
5756 if (*s == ')')
5757 {
5758 *end_op = s + 1;
5759 return r;
5760 }
5f47d35b 5761 }
47926f60 5762 /* We have "%st(" then garbage. */
5f47d35b
AM		 5763 return (const reg_entry *) NULL;
5764 }
5765 }
5766
1ae00879 5767 if (r != NULL
20f0a1fc 5768 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5769 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5770 && flag_code != CODE_64BIT)
20f0a1fc 5771 return (const reg_entry *) NULL;
1ae00879 5772
252b5132
RH		 5773 return r;
5774}
4d1bb795
JB		 5775
5776/* REG_STRING starts *before* REGISTER_PREFIX. */
5777
5778static const reg_entry *
5779parse_register (char *reg_string, char **end_op)
5780{
5781 const reg_entry *r;
5782
5783 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5784 r = parse_real_register (reg_string, end_op);
5785 else
5786 r = NULL;
5787 if (!r)
5788 {
5789 char *save = input_line_pointer;
5790 char c;
5791 symbolS *symbolP;
5792
5793 input_line_pointer = reg_string;
5794 c = get_symbol_end ();
5795 symbolP = symbol_find (reg_string);
5796 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5797 {
5798 const expressionS *e = symbol_get_value_expression (symbolP);
5799
5800 know (e->X_op == O_register);
5801 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5802 r = i386_regtab + e->X_add_number;
5803 *end_op = input_line_pointer;
5804 }
5805 *input_line_pointer = c;
5806 input_line_pointer = save;
5807 }
5808 return r;
5809}
5810
5811int
5812i386_parse_name (char *name, expressionS *e, char *nextcharP)
5813{
5814 const reg_entry *r;
5815 char *end = input_line_pointer;
5816
5817 *end = *nextcharP;
5818 r = parse_register (name, &input_line_pointer);
5819 if (r && end <= input_line_pointer)
5820 {
5821 *nextcharP = *input_line_pointer;
5822 *input_line_pointer = 0;
5823 e->X_op = O_register;
5824 e->X_add_number = r - i386_regtab;
5825 return 1;
5826 }
5827 input_line_pointer = end;
5828 *end = 0;
5829 return 0;
5830}
5831
5832void
5833md_operand (expressionS *e)
5834{
5835 if (*input_line_pointer == REGISTER_PREFIX)
5836 {
5837 char *end;
5838 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5839
5840 if (r)
5841 {
5842 e->X_op = O_register;
5843 e->X_add_number = r - i386_regtab;
5844 input_line_pointer = end;
5845 }
5846 }
5847}
5848
252b5132 5849\f
4cc782b5 5850#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5851const char *md_shortopts = "kVQ:sqn";
252b5132 5852#else
12b55ccc 5853const char *md_shortopts = "qn";
252b5132 5854#endif
6e0b89ee 5855
3e73aa7c 5856#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5857#define OPTION_64 (OPTION_MD_BASE + 1)
5858#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5859#define OPTION_MARCH (OPTION_MD_BASE + 3)
5860#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5861
99ad8390
NC		 5862struct option md_longopts[] =
5863{
3e73aa7c 5864 {"32", no_argument, NULL, OPTION_32},
99ad8390 5865#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5866 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5867#endif
b3b91714 5868 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5869 {"march", required_argument, NULL, OPTION_MARCH},
5870 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5871 {NULL, no_argument, NULL, 0}
5872};
5873size_t md_longopts_size = sizeof (md_longopts);
5874
5875int
9103f4f4 5876md_parse_option (int c, char *arg)
252b5132 5877{
9103f4f4
L		 5878 unsigned int i;
5879
252b5132
RH		 5880 switch (c)
5881 {
12b55ccc
L		 5882 case 'n':
5883 optimize_align_code = 0;
5884 break;
5885
a38cf1db
AM		 5886 case 'q':
5887 quiet_warnings = 1;
252b5132
RH		 5888 break;
5889
5890#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5891 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5892 should be emitted or not. FIXME: Not implemented. */
5893 case 'Q':
252b5132
RH		 5894 break;
5895
5896 /* -V: SVR4 argument to print version ID. */
5897 case 'V':
5898 print_version_id ();
5899 break;
5900
a38cf1db
AM		 5901 /* -k: Ignore for FreeBSD compatibility. */
5902 case 'k':
252b5132 5903 break;
4cc782b5
ILT		 5904
5905 case 's':
5906 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5907 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5908 break;
99ad8390
NC		 5909#endif
5910#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5911 case OPTION_64:
5912 {
5913 const char **list, **l;
5914
3e73aa7c
JH		 5915 list = bfd_target_list ();
5916 for (l = list; *l != NULL; l++)
8620418b 5917 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5918 || strcmp (*l, "coff-x86-64") == 0
5919 || strcmp (*l, "pe-x86-64") == 0
5920 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5921 {
5922 default_arch = "x86_64";
5923 break;
5924 }
3e73aa7c 5925 if (*l == NULL)
6e0b89ee 5926 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5927 free (list);
5928 }
5929 break;
5930#endif
252b5132 5931
6e0b89ee
AM		 5932 case OPTION_32:
5933 default_arch = "i386";
5934 break;
5935
b3b91714
AM		 5936 case OPTION_DIVIDE:
5937#ifdef SVR4_COMMENT_CHARS
5938 {
5939 char *n, *t;
5940 const char *s;
5941
5942 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5943 t = n;
5944 for (s = i386_comment_chars; *s != '\0'; s++)
5945 if (*s != '/')
5946 *t++ = *s;
5947 *t = '\0';
5948 i386_comment_chars = n;
5949 }
5950#endif
5951 break;
5952
9103f4f4
L		 5953 case OPTION_MARCH:
5954 if (*arg == '.')
5955 as_fatal (_("Invalid -march= option: `%s'"), arg);
5956 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5957 {
5958 if (strcmp (arg, cpu_arch [i].name) == 0)
5959 {
ccc9c027 5960 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5961 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5962 if (!cpu_arch_tune_set)
5963 {
5964 cpu_arch_tune = cpu_arch_isa;
5965 cpu_arch_tune_flags = cpu_arch_isa_flags;
5966 }
9103f4f4
L		 5967 break;
5968 }
5969 }
5970 if (i >= ARRAY_SIZE (cpu_arch))
5971 as_fatal (_("Invalid -march= option: `%s'"), arg);
5972 break;
5973
5974 case OPTION_MTUNE:
5975 if (*arg == '.')
5976 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5977 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5978 {
5979 if (strcmp (arg, cpu_arch [i].name) == 0)
5980 {
ccc9c027 5981 cpu_arch_tune_set = 1;
9103f4f4
L		 5982 cpu_arch_tune = cpu_arch [i].type;
5983 cpu_arch_tune_flags = cpu_arch[i].flags;
5984 break;
5985 }
5986 }
5987 if (i >= ARRAY_SIZE (cpu_arch))
5988 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5989 break;
5990
252b5132
RH		 5991 default:
5992 return 0;
5993 }
5994 return 1;
5995}
5996
5997void
5998md_show_usage (stream)
5999 FILE *stream;
6000{
4cc782b5
ILT		 6001#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6002 fprintf (stream, _("\
a38cf1db
AM		 6003 -Q ignored\n\
6004 -V print assembler version number\n\
b3b91714
AM		 6005 -k ignored\n"));
6006#endif
6007 fprintf (stream, _("\
12b55ccc 6008 -n Do not optimize code alignment\n\
b3b91714
AM		 6009 -q quieten some warnings\n"));
6010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6011 fprintf (stream, _("\
a38cf1db 6012 -s ignored\n"));
b3b91714
AM		 6013#endif
6014#ifdef SVR4_COMMENT_CHARS
6015 fprintf (stream, _("\
6016 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6017#else
6018 fprintf (stream, _("\
b3b91714 6019 --divide ignored\n"));
4cc782b5 6020#endif
9103f4f4
L		 6021 fprintf (stream, _("\
6022 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6023 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 6024 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6025
252b5132
RH		 6026}
6027
99ad8390
NC		 6028#if defined(TE_PEP)
6029const char *
6030x86_64_target_format (void)
6031{
6032 if (strcmp (default_arch, "x86_64") == 0)
6033 {
6034 set_code_flag (CODE_64BIT);
6035 return COFF_TARGET_FORMAT;
6036 }
6037 else if (strcmp (default_arch, "i386") == 0)
6038 {
6039 set_code_flag (CODE_32BIT);
6040 return "coff-i386";
6041 }
6042
6043 as_fatal (_("Unknown architecture"));
6044 return NULL;
6045}
6046#endif
6047
3e73aa7c
JH		 6048#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6049 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6050
6051/* Pick the target format to use. */
6052
47926f60 6053const char *
252b5132
RH		 6054i386_target_format ()
6055{
3e73aa7c 6056 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6057 {
6058 set_code_flag (CODE_64BIT);
6059 if (cpu_arch_isa_flags == 0)
d32cad65 6060 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6061 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6062 |CpuSSE|CpuSSE2;
ccc9c027 6063 if (cpu_arch_tune_flags == 0)
d32cad65 6064 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6065 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6066 |CpuSSE|CpuSSE2;
9103f4f4 6067 }
3e73aa7c 6068 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6069 {
6070 set_code_flag (CODE_32BIT);
6071 if (cpu_arch_isa_flags == 0)
d32cad65 6072 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6073 if (cpu_arch_tune_flags == 0)
d32cad65 6074 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6075 }
3e73aa7c
JH		 6076 else
6077 as_fatal (_("Unknown architecture"));
252b5132
RH		 6078 switch (OUTPUT_FLAVOR)
6079 {
4c63da97
AM		 6080#ifdef OBJ_MAYBE_AOUT
6081 case bfd_target_aout_flavour:
47926f60 6082 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6083#endif
6084#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6085 case bfd_target_coff_flavour:
6086 return "coff-i386";
4c63da97 6087#endif
3e73aa7c 6088#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6089 case bfd_target_elf_flavour:
3e73aa7c 6090 {
e5cb08ac 6091 if (flag_code == CODE_64BIT)
4fa24527
JB		 6092 {
6093 object_64bit = 1;
6094 use_rela_relocations = 1;
6095 }
9d7cbccd 6096 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6097 }
4c63da97 6098#endif
252b5132
RH		 6099 default:
6100 abort ();
6101 return NULL;
6102 }
6103}
6104
47926f60 6105#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6106
6107#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6108void i386_elf_emit_arch_note ()
6109{
718ddfc0 6110 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6111 {
6112 char *p;
6113 asection *seg = now_seg;
6114 subsegT subseg = now_subseg;
6115 Elf_Internal_Note i_note;
6116 Elf_External_Note e_note;
6117 asection *note_secp;
6118 int len;
6119
6120 /* Create the .note section. */
6121 note_secp = subseg_new (".note", 0);
6122 bfd_set_section_flags (stdoutput,
6123 note_secp,
6124 SEC_HAS_CONTENTS | SEC_READONLY);
6125
6126 /* Process the arch string. */
6127 len = strlen (cpu_arch_name);
6128
6129 i_note.namesz = len + 1;
6130 i_note.descsz = 0;
6131 i_note.type = NT_ARCH;
6132 p = frag_more (sizeof (e_note.namesz));
6133 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6134 p = frag_more (sizeof (e_note.descsz));
6135 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6136 p = frag_more (sizeof (e_note.type));
6137 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6138 p = frag_more (len + 1);
6139 strcpy (p, cpu_arch_name);
6140
6141 frag_align (2, 0, 0);
6142
6143 subseg_set (seg, subseg);
6144 }
6145}
6146#endif
252b5132 6147\f
252b5132
RH		 6148symbolS *
6149md_undefined_symbol (name)
6150 char *name;
6151{
18dc2407
ILT		 6152 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6153 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6154 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6155 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6156 {
6157 if (!GOT_symbol)
6158 {
6159 if (symbol_find (name))
6160 as_bad (_("GOT already in symbol table"));
6161 GOT_symbol = symbol_new (name, undefined_section,
6162 (valueT) 0, &zero_address_frag);
6163 };
6164 return GOT_symbol;
6165 }
252b5132
RH		 6166 return 0;
6167}
6168
6169/* Round up a section size to the appropriate boundary. */
47926f60 6170
252b5132
RH		 6171valueT
6172md_section_align (segment, size)
ab9da554 6173 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6174 valueT size;
6175{
4c63da97
AM		 6176#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6177 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6178 {
6179 /* For a.out, force the section size to be aligned. If we don't do
6180 this, BFD will align it for us, but it will not write out the
6181 final bytes of the section. This may be a bug in BFD, but it is
6182 easier to fix it here since that is how the other a.out targets
6183 work. */
6184 int align;
6185
6186 align = bfd_get_section_alignment (stdoutput, segment);
6187 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6188 }
252b5132
RH		 6189#endif
6190
6191 return size;
6192}
6193
6194/* On the i386, PC-relative offsets are relative to the start of the
6195 next instruction. That is, the address of the offset, plus its
6196 size, since the offset is always the last part of the insn. */
6197
6198long
6199md_pcrel_from (fixP)
6200 fixS *fixP;
6201{
6202 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6203}
6204
6205#ifndef I386COFF
6206
6207static void
6208s_bss (ignore)
ab9da554 6209 int ignore ATTRIBUTE_UNUSED;
252b5132 6210{
29b0f896 6211 int temp;
252b5132 6212
8a75718c
JB		 6213#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6214 if (IS_ELF)
6215 obj_elf_section_change_hook ();
6216#endif
252b5132
RH		 6217 temp = get_absolute_expression ();
6218 subseg_set (bss_section, (subsegT) temp);
6219 demand_empty_rest_of_line ();
6220}
6221
6222#endif
6223
252b5132
RH		 6224void
6225i386_validate_fix (fixp)
6226 fixS *fixp;
6227{
6228 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6229 {
23df1078
JH		 6230 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6231 {
4fa24527 6232 if (!object_64bit)
23df1078
JH		 6233 abort ();
6234 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6235 }
6236 else
6237 {
4fa24527 6238 if (!object_64bit)
d6ab8113
JB		 6239 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6240 else
6241 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6242 }
252b5132
RH		 6243 fixp->fx_subsy = 0;
6244 }
6245}
6246
252b5132
RH		 6247arelent *
6248tc_gen_reloc (section, fixp)
ab9da554 6249 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6250 fixS *fixp;
6251{
6252 arelent *rel;
6253 bfd_reloc_code_real_type code;
6254
6255 switch (fixp->fx_r_type)
6256 {
3e73aa7c
JH		 6257 case BFD_RELOC_X86_64_PLT32:
6258 case BFD_RELOC_X86_64_GOT32:
6259 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6260 case BFD_RELOC_386_PLT32:
6261 case BFD_RELOC_386_GOT32:
6262 case BFD_RELOC_386_GOTOFF:
6263 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6264 case BFD_RELOC_386_TLS_GD:
6265 case BFD_RELOC_386_TLS_LDM:
6266 case BFD_RELOC_386_TLS_LDO_32:
6267 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6268 case BFD_RELOC_386_TLS_IE:
6269 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6270 case BFD_RELOC_386_TLS_LE_32:
6271 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6272 case BFD_RELOC_386_TLS_GOTDESC:
6273 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6274 case BFD_RELOC_X86_64_TLSGD:
6275 case BFD_RELOC_X86_64_TLSLD:
6276 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6277 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6278 case BFD_RELOC_X86_64_GOTTPOFF:
6279 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6280 case BFD_RELOC_X86_64_TPOFF64:
6281 case BFD_RELOC_X86_64_GOTOFF64:
6282 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6283 case BFD_RELOC_X86_64_GOT64:
6284 case BFD_RELOC_X86_64_GOTPCREL64:
6285 case BFD_RELOC_X86_64_GOTPC64:
6286 case BFD_RELOC_X86_64_GOTPLT64:
6287 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6288 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6289 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6290 case BFD_RELOC_RVA:
6291 case BFD_RELOC_VTABLE_ENTRY:
6292 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6293#ifdef TE_PE
6294 case BFD_RELOC_32_SECREL:
6295#endif
252b5132
RH		 6296 code = fixp->fx_r_type;
6297 break;
dbbaec26
L		 6298 case BFD_RELOC_X86_64_32S:
6299 if (!fixp->fx_pcrel)
6300 {
6301 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6302 code = fixp->fx_r_type;
6303 break;
6304 }
252b5132 6305 default:
93382f6d 6306 if (fixp->fx_pcrel)
252b5132 6307 {
93382f6d
AM		 6308 switch (fixp->fx_size)
6309 {
6310 default:
b091f402
AM		 6311 as_bad_where (fixp->fx_file, fixp->fx_line,
6312 _("can not do %d byte pc-relative relocation"),
6313 fixp->fx_size);
93382f6d
AM		 6314 code = BFD_RELOC_32_PCREL;
6315 break;
6316 case 1: code = BFD_RELOC_8_PCREL; break;
6317 case 2: code = BFD_RELOC_16_PCREL; break;
6318 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6319#ifdef BFD64
6320 case 8: code = BFD_RELOC_64_PCREL; break;
6321#endif
93382f6d
AM		 6322 }
6323 }
6324 else
6325 {
6326 switch (fixp->fx_size)
6327 {
6328 default:
b091f402
AM		 6329 as_bad_where (fixp->fx_file, fixp->fx_line,
6330 _("can not do %d byte relocation"),
6331 fixp->fx_size);
93382f6d
AM		 6332 code = BFD_RELOC_32;
6333 break;
6334 case 1: code = BFD_RELOC_8; break;
6335 case 2: code = BFD_RELOC_16; break;
6336 case 4: code = BFD_RELOC_32; break;
937149dd 6337#ifdef BFD64
3e73aa7c 6338 case 8: code = BFD_RELOC_64; break;
937149dd 6339#endif
93382f6d 6340 }
252b5132
RH		 6341 }
6342 break;
6343 }
252b5132 6344
d182319b
JB		 6345 if ((code == BFD_RELOC_32
6346 || code == BFD_RELOC_32_PCREL
6347 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6348 && GOT_symbol
6349 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6350 {
4fa24527 6351 if (!object_64bit)
d6ab8113
JB		 6352 code = BFD_RELOC_386_GOTPC;
6353 else
6354 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6355 }
7b81dfbb
AJ		 6356 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6357 && GOT_symbol
6358 && fixp->fx_addsy == GOT_symbol)
6359 {
6360 code = BFD_RELOC_X86_64_GOTPC64;
6361 }
252b5132
RH		 6362
6363 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6364 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6365 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6366
6367 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6368
3e73aa7c
JH		 6369 if (!use_rela_relocations)
6370 {
6371 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6372 vtable entry to be used in the relocation's section offset. */
6373 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6374 rel->address = fixp->fx_offset;
252b5132 6375
c6682705 6376 rel->addend = 0;
3e73aa7c
JH		 6377 }
6378 /* Use the rela in 64bit mode. */
252b5132 6379 else
3e73aa7c 6380 {
062cd5e7
AS		 6381 if (!fixp->fx_pcrel)
6382 rel->addend = fixp->fx_offset;
6383 else
6384 switch (code)
6385 {
6386 case BFD_RELOC_X86_64_PLT32:
6387 case BFD_RELOC_X86_64_GOT32:
6388 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6389 case BFD_RELOC_X86_64_TLSGD:
6390 case BFD_RELOC_X86_64_TLSLD:
6391 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6392 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6393 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6394 rel->addend = fixp->fx_offset - fixp->fx_size;
6395 break;
6396 default:
6397 rel->addend = (section->vma
6398 - fixp->fx_size
6399 + fixp->fx_addnumber
6400 + md_pcrel_from (fixp));
6401 break;
6402 }
3e73aa7c
JH		 6403 }
6404
252b5132
RH		 6405 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6406 if (rel->howto == NULL)
6407 {
6408 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6409 _("cannot represent relocation type %s"),
252b5132
RH		 6410 bfd_get_reloc_code_name (code));
6411 /* Set howto to a garbage value so that we can keep going. */
6412 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6413 assert (rel->howto != NULL);
6414 }
6415
6416 return rel;
6417}
6418
64a0c779
DN		 6419\f
6420/* Parse operands using Intel syntax. This implements a recursive descent
6421 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6422 Programmer's Guide.
6423
6424 FIXME: We do not recognize the full operand grammar defined in the MASM
6425 documentation. In particular, all the structure/union and
6426 high-level macro operands are missing.
6427
6428 Uppercase words are terminals, lower case words are non-terminals.
6429 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6430 bars '|' denote choices. Most grammar productions are implemented in
6431 functions called 'intel_<production>'.
6432
6433 Initial production is 'expr'.
6434
9306ca4a 6435 addOp + | -
64a0c779
DN		 6436
6437 alpha [a-zA-Z]
6438
9306ca4a
JB		 6439 binOp & | AND | \| | OR | ^ | XOR
6440
64a0c779
DN		 6441 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6442
6443 constant digits [[ radixOverride ]]
6444
9306ca4a 6445 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6446
6447 digits decdigit
b77a7acd
AJ		 6448 | digits decdigit
6449 | digits hexdigit
64a0c779
DN		 6450
6451 decdigit [0-9]
6452
9306ca4a
JB		 6453 e04 e04 addOp e05
6454 | e05
6455
6456 e05 e05 binOp e06
b77a7acd 6457 | e06
64a0c779
DN		 6458
6459 e06 e06 mulOp e09
b77a7acd 6460 | e09
64a0c779
DN		 6461
6462 e09 OFFSET e10
a724f0f4
JB		 6463 | SHORT e10
6464 | + e10
6465 | - e10
9306ca4a
JB		 6466 | ~ e10
6467 | NOT e10
64a0c779
DN		 6468 | e09 PTR e10
6469 | e09 : e10
6470 | e10
6471
6472 e10 e10 [ expr ]
b77a7acd 6473 | e11
64a0c779
DN		 6474
6475 e11 ( expr )
b77a7acd 6476 | [ expr ]
64a0c779
DN		 6477 | constant
6478 | dataType
6479 | id
6480 | $
6481 | register
6482
a724f0f4 6483 => expr expr cmpOp e04
9306ca4a 6484 | e04
64a0c779
DN		 6485
6486 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6487 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6488
6489 hexdigit a | b | c | d | e | f
b77a7acd 6490 | A | B | C | D | E | F
64a0c779
DN		 6491
6492 id alpha
b77a7acd 6493 | id alpha
64a0c779
DN		 6494 | id decdigit
6495
9306ca4a 6496 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6497
6498 quote " | '
6499
6500 register specialRegister
b77a7acd 6501 | gpRegister
64a0c779
DN		 6502 | byteRegister
6503
6504 segmentRegister CS | DS | ES | FS | GS | SS
6505
9306ca4a 6506 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6507 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6508 | TR3 | TR4 | TR5 | TR6 | TR7
6509
64a0c779
DN		 6510 We simplify the grammar in obvious places (e.g., register parsing is
6511 done by calling parse_register) and eliminate immediate left recursion
6512 to implement a recursive-descent parser.
6513
a724f0f4
JB		 6514 expr e04 expr'
6515
6516 expr' cmpOp e04 expr'
6517 | Empty
9306ca4a
JB		 6518
6519 e04 e05 e04'
6520
6521 e04' addOp e05 e04'
6522 | Empty
64a0c779
DN		 6523
6524 e05 e06 e05'
6525
9306ca4a 6526 e05' binOp e06 e05'
b77a7acd 6527 | Empty
64a0c779
DN		 6528
6529 e06 e09 e06'
6530
6531 e06' mulOp e09 e06'
b77a7acd 6532 | Empty
64a0c779
DN		 6533
6534 e09 OFFSET e10 e09'
a724f0f4
JB		 6535 | SHORT e10'
6536 | + e10'
6537 | - e10'
6538 | ~ e10'
6539 | NOT e10'
b77a7acd 6540 | e10 e09'
64a0c779
DN		 6541
6542 e09' PTR e10 e09'
b77a7acd 6543 | : e10 e09'
64a0c779
DN		 6544 | Empty
6545
6546 e10 e11 e10'
6547
6548 e10' [ expr ] e10'
b77a7acd 6549 | Empty
64a0c779
DN		 6550
6551 e11 ( expr )
b77a7acd 6552 | [ expr ]
64a0c779
DN		 6553 | BYTE
6554 | WORD
6555 | DWORD
9306ca4a 6556 | FWORD
64a0c779 6557 | QWORD
9306ca4a
JB		 6558 | TBYTE
6559 | OWORD
6560 | XMMWORD
64a0c779
DN		 6561 | .
6562 | $
6563 | register
6564 | id
6565 | constant */
6566
6567/* Parsing structure for the intel syntax parser. Used to implement the
6568 semantic actions for the operand grammar. */
6569struct intel_parser_s
6570 {
6571 char *op_string; /* The string being parsed. */
6572 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6573 int op_modifier; /* Operand modifier. */
64a0c779 6574 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6575 int in_offset; /* >=1 if parsing operand of offset. */
6576 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6577 const reg_entry *reg; /* Last register reference found. */
6578 char *disp; /* Displacement string being built. */
a724f0f4 6579 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6580 };
6581
6582static struct intel_parser_s intel_parser;
6583
6584/* Token structure for parsing intel syntax. */
6585struct intel_token
6586 {
6587 int code; /* Token code. */
6588 const reg_entry *reg; /* Register entry for register tokens. */
6589 char *str; /* String representation. */
6590 };
6591
6592static struct intel_token cur_token, prev_token;
6593
50705ef4
AM		 6594/* Token codes for the intel parser. Since T_SHORT is already used
6595 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6596#define T_NIL -1
6597#define T_CONST 1
6598#define T_REG 2
6599#define T_BYTE 3
6600#define T_WORD 4
9306ca4a
JB		 6601#define T_DWORD 5
6602#define T_FWORD 6
6603#define T_QWORD 7
6604#define T_TBYTE 8
6605#define T_XMMWORD 9
50705ef4 6606#undef T_SHORT
9306ca4a
JB		 6607#define T_SHORT 10
6608#define T_OFFSET 11
6609#define T_PTR 12
6610#define T_ID 13
6611#define T_SHL 14
6612#define T_SHR 15
64a0c779
DN		 6613
6614/* Prototypes for intel parser functions. */
6615static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6616static void intel_get_token PARAMS ((void));
6617static void intel_putback_token PARAMS ((void));
6618static int intel_expr PARAMS ((void));
9306ca4a 6619static int intel_e04 PARAMS ((void));
cce0cbdc 6620static int intel_e05 PARAMS ((void));
cce0cbdc 6621static int intel_e06 PARAMS ((void));
cce0cbdc 6622static int intel_e09 PARAMS ((void));
a724f0f4 6623static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6624static int intel_e10 PARAMS ((void));
cce0cbdc 6625static int intel_e11 PARAMS ((void));
64a0c779 6626
64a0c779
DN		 6627static int
6628i386_intel_operand (operand_string, got_a_float)
6629 char *operand_string;
6630 int got_a_float;
6631{
6632 int ret;
6633 char *p;
6634
a724f0f4
JB		 6635 p = intel_parser.op_string = xstrdup (operand_string);
6636 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6637
6638 for (;;)
64a0c779 6639 {
a724f0f4
JB		 6640 /* Initialize token holders. */
6641 cur_token.code = prev_token.code = T_NIL;
6642 cur_token.reg = prev_token.reg = NULL;
6643 cur_token.str = prev_token.str = NULL;
6644
6645 /* Initialize parser structure. */
6646 intel_parser.got_a_float = got_a_float;
6647 intel_parser.op_modifier = 0;
6648 intel_parser.is_mem = 0;
6649 intel_parser.in_offset = 0;
6650 intel_parser.in_bracket = 0;
6651 intel_parser.reg = NULL;
6652 intel_parser.disp[0] = '\0';
6653 intel_parser.next_operand = NULL;
6654
6655 /* Read the first token and start the parser. */
6656 intel_get_token ();
6657 ret = intel_expr ();
6658
6659 if (!ret)
6660 break;
6661
9306ca4a
JB		 6662 if (cur_token.code != T_NIL)
6663 {
6664 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6665 current_templates->start->name, cur_token.str);
6666 ret = 0;
6667 }
64a0c779
DN		 6668 /* If we found a memory reference, hand it over to i386_displacement
6669 to fill in the rest of the operand fields. */
9306ca4a 6670 else if (intel_parser.is_mem)
64a0c779
DN		 6671 {
6672 if ((i.mem_operands == 1
6673 && (current_templates->start->opcode_modifier & IsString) == 0)
6674 || i.mem_operands == 2)
6675 {
6676 as_bad (_("too many memory references for '%s'"),
6677 current_templates->start->name);
6678 ret = 0;
6679 }
6680 else
6681 {
6682 char *s = intel_parser.disp;
6683 i.mem_operands++;
6684
a724f0f4
JB		 6685 if (!quiet_warnings && intel_parser.is_mem < 0)
6686 /* See the comments in intel_bracket_expr. */
6687 as_warn (_("Treating `%s' as memory reference"), operand_string);
6688
64a0c779
DN		 6689 /* Add the displacement expression. */
6690 if (*s != '\0')
a4622f40
AM		 6691 ret = i386_displacement (s, s + strlen (s));
6692 if (ret)
a724f0f4
JB		 6693 {
6694 /* Swap base and index in 16-bit memory operands like
6695 [si+bx]. Since i386_index_check is also used in AT&T
6696 mode we have to do that here. */
6697 if (i.base_reg
6698 && i.index_reg
6699 && (i.base_reg->reg_type & Reg16)
6700 && (i.index_reg->reg_type & Reg16)
6701 && i.base_reg->reg_num >= 6
6702 && i.index_reg->reg_num < 6)
6703 {
6704 const reg_entry *base = i.index_reg;
6705
6706 i.index_reg = i.base_reg;
6707 i.base_reg = base;
6708 }
6709 ret = i386_index_check (operand_string);
6710 }
64a0c779
DN		 6711 }
6712 }
6713
6714 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6715 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6716 || intel_parser.reg == NULL)
6717 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6718
6719 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6720 ret = 0;
6721 if (!ret || !intel_parser.next_operand)
6722 break;
6723 intel_parser.op_string = intel_parser.next_operand;
6724 this_operand = i.operands++;
64a0c779
DN		 6725 }
6726
6727 free (p);
6728 free (intel_parser.disp);
6729
6730 return ret;
6731}
6732
a724f0f4
JB		 6733#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6734
6735/* expr e04 expr'
6736
6737 expr' cmpOp e04 expr'
6738 | Empty */
64a0c779
DN		 6739static int
6740intel_expr ()
6741{
a724f0f4
JB		 6742 /* XXX Implement the comparison operators. */
6743 return intel_e04 ();
9306ca4a
JB		 6744}
6745
a724f0f4 6746/* e04 e05 e04'
9306ca4a 6747
a724f0f4 6748 e04' addOp e05 e04'
9306ca4a
JB		 6749 | Empty */
6750static int
6751intel_e04 ()
6752{
a724f0f4 6753 int nregs = -1;
9306ca4a 6754
a724f0f4 6755 for (;;)
9306ca4a 6756 {
a724f0f4
JB		 6757 if (!intel_e05())
6758 return 0;
9306ca4a 6759
a724f0f4
JB		 6760 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6761 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6762
a724f0f4
JB		 6763 if (cur_token.code == '+')
6764 nregs = -1;
6765 else if (cur_token.code == '-')
6766 nregs = NUM_ADDRESS_REGS;
6767 else
6768 return 1;
64a0c779 6769
a724f0f4
JB		 6770 strcat (intel_parser.disp, cur_token.str);
6771 intel_match_token (cur_token.code);
6772 }
64a0c779
DN		 6773}
6774
64a0c779
DN		 6775/* e05 e06 e05'
6776
9306ca4a 6777 e05' binOp e06 e05'
64a0c779
DN		 6778 | Empty */
6779static int
6780intel_e05 ()
6781{
a724f0f4 6782 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6783
a724f0f4 6784 for (;;)
64a0c779 6785 {
a724f0f4
JB		 6786 if (!intel_e06())
6787 return 0;
6788
6789 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6790 {
6791 char str[2];
6792
6793 str[0] = cur_token.code;
6794 str[1] = 0;
6795 strcat (intel_parser.disp, str);
6796 }
6797 else
6798 break;
9306ca4a 6799
64a0c779
DN		 6800 intel_match_token (cur_token.code);
6801
a724f0f4
JB		 6802 if (nregs < 0)
6803 nregs = ~nregs;
64a0c779 6804 }
a724f0f4
JB		 6805 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6806 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6807 return 1;
4a1805b1 6808}
64a0c779
DN		 6809
6810/* e06 e09 e06'
6811
6812 e06' mulOp e09 e06'
b77a7acd 6813 | Empty */
64a0c779
DN		 6814static int
6815intel_e06 ()
6816{
a724f0f4 6817 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6818
a724f0f4 6819 for (;;)
64a0c779 6820 {
a724f0f4
JB		 6821 if (!intel_e09())
6822 return 0;
9306ca4a 6823
a724f0f4
JB		 6824 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6825 {
6826 char str[2];
9306ca4a 6827
a724f0f4
JB		 6828 str[0] = cur_token.code;
6829 str[1] = 0;
6830 strcat (intel_parser.disp, str);
6831 }
6832 else if (cur_token.code == T_SHL)
6833 strcat (intel_parser.disp, "<<");
6834 else if (cur_token.code == T_SHR)
6835 strcat (intel_parser.disp, ">>");
6836 else
6837 break;
9306ca4a 6838
64e74474 6839 intel_match_token (cur_token.code);
64a0c779 6840
a724f0f4
JB		 6841 if (nregs < 0)
6842 nregs = ~nregs;
64a0c779 6843 }
a724f0f4
JB		 6844 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6845 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6846 return 1;
64a0c779
DN		 6847}
6848
a724f0f4
JB		 6849/* e09 OFFSET e09
6850 | SHORT e09
6851 | + e09
6852 | - e09
6853 | ~ e09
6854 | NOT e09
9306ca4a
JB		 6855 | e10 e09'
6856
64a0c779 6857 e09' PTR e10 e09'
b77a7acd 6858 | : e10 e09'
64a0c779
DN		 6859 | Empty */
6860static int
6861intel_e09 ()
6862{
a724f0f4
JB		 6863 int nregs = ~NUM_ADDRESS_REGS;
6864 int in_offset = 0;
6865
6866 for (;;)
64a0c779 6867 {
a724f0f4
JB		 6868 /* Don't consume constants here. */
6869 if (cur_token.code == '+' || cur_token.code == '-')
6870 {
6871 /* Need to look one token ahead - if the next token
6872 is a constant, the current token is its sign. */
6873 int next_code;
6874
6875 intel_match_token (cur_token.code);
6876 next_code = cur_token.code;
6877 intel_putback_token ();
6878 if (next_code == T_CONST)
6879 break;
6880 }
6881
6882 /* e09 OFFSET e09 */
6883 if (cur_token.code == T_OFFSET)
6884 {
6885 if (!in_offset++)
6886 ++intel_parser.in_offset;
6887 }
6888
6889 /* e09 SHORT e09 */
6890 else if (cur_token.code == T_SHORT)
6891 intel_parser.op_modifier |= 1 << T_SHORT;
6892
6893 /* e09 + e09 */
6894 else if (cur_token.code == '+')
6895 strcat (intel_parser.disp, "+");
6896
6897 /* e09 - e09
6898 | ~ e09
6899 | NOT e09 */
6900 else if (cur_token.code == '-' || cur_token.code == '~')
6901 {
6902 char str[2];
64a0c779 6903
a724f0f4
JB		 6904 if (nregs < 0)
6905 nregs = ~nregs;
6906 str[0] = cur_token.code;
6907 str[1] = 0;
6908 strcat (intel_parser.disp, str);
6909 }
6910
6911 /* e09 e10 e09' */
6912 else
6913 break;
6914
6915 intel_match_token (cur_token.code);
64a0c779
DN		 6916 }
6917
a724f0f4 6918 for (;;)
9306ca4a 6919 {
a724f0f4
JB		 6920 if (!intel_e10 ())
6921 return 0;
9306ca4a 6922
a724f0f4
JB		 6923 /* e09' PTR e10 e09' */
6924 if (cur_token.code == T_PTR)
6925 {
6926 char suffix;
9306ca4a 6927
a724f0f4
JB		 6928 if (prev_token.code == T_BYTE)
6929 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6930
a724f0f4
JB		 6931 else if (prev_token.code == T_WORD)
6932 {
6933 if (current_templates->start->name[0] == 'l'
6934 && current_templates->start->name[2] == 's'
6935 && current_templates->start->name[3] == 0)
6936 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6937 else if (intel_parser.got_a_float == 2) /* "fi..." */
6938 suffix = SHORT_MNEM_SUFFIX;
6939 else
6940 suffix = WORD_MNEM_SUFFIX;
6941 }
64a0c779 6942
a724f0f4
JB		 6943 else if (prev_token.code == T_DWORD)
6944 {
6945 if (current_templates->start->name[0] == 'l'
6946 && current_templates->start->name[2] == 's'
6947 && current_templates->start->name[3] == 0)
6948 suffix = WORD_MNEM_SUFFIX;
6949 else if (flag_code == CODE_16BIT
6950 && (current_templates->start->opcode_modifier
435acd52 6951 & (Jump | JumpDword)))
a724f0f4
JB		 6952 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6953 else if (intel_parser.got_a_float == 1) /* "f..." */
6954 suffix = SHORT_MNEM_SUFFIX;
6955 else
6956 suffix = LONG_MNEM_SUFFIX;
6957 }
9306ca4a 6958
a724f0f4
JB		 6959 else if (prev_token.code == T_FWORD)
6960 {
6961 if (current_templates->start->name[0] == 'l'
6962 && current_templates->start->name[2] == 's'
6963 && current_templates->start->name[3] == 0)
6964 suffix = LONG_MNEM_SUFFIX;
6965 else if (!intel_parser.got_a_float)
6966 {
6967 if (flag_code == CODE_16BIT)
6968 add_prefix (DATA_PREFIX_OPCODE);
6969 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6970 }
6971 else
6972 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6973 }
64a0c779 6974
a724f0f4
JB		 6975 else if (prev_token.code == T_QWORD)
6976 {
6977 if (intel_parser.got_a_float == 1) /* "f..." */
6978 suffix = LONG_MNEM_SUFFIX;
6979 else
6980 suffix = QWORD_MNEM_SUFFIX;
6981 }
64a0c779 6982
a724f0f4
JB		 6983 else if (prev_token.code == T_TBYTE)
6984 {
6985 if (intel_parser.got_a_float == 1)
6986 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6987 else
6988 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6989 }
9306ca4a 6990
a724f0f4 6991 else if (prev_token.code == T_XMMWORD)
9306ca4a 6992 {
a724f0f4
JB		 6993 /* XXX ignored for now, but accepted since gcc uses it */
6994 suffix = 0;
9306ca4a 6995 }
64a0c779 6996
f16b83df 6997 else
a724f0f4
JB		 6998 {
6999 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7000 return 0;
7001 }
7002
435acd52
JB		 7003 /* Operands for jump/call using 'ptr' notation denote absolute
7004 addresses. */
7005 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7006 i.types[this_operand] |= JumpAbsolute;
7007
a724f0f4
JB		 7008 if (current_templates->start->base_opcode == 0x8d /* lea */)
7009 ;
7010 else if (!i.suffix)
7011 i.suffix = suffix;
7012 else if (i.suffix != suffix)
7013 {
7014 as_bad (_("Conflicting operand modifiers"));
7015 return 0;
7016 }
64a0c779 7017
9306ca4a
JB		 7018 }
7019
a724f0f4
JB		 7020 /* e09' : e10 e09' */
7021 else if (cur_token.code == ':')
9306ca4a 7022 {
a724f0f4
JB		 7023 if (prev_token.code != T_REG)
7024 {
7025 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7026 segment/group identifier (which we don't have), using comma
7027 as the operand separator there is even less consistent, since
7028 there all branches only have a single operand. */
7029 if (this_operand != 0
7030 || intel_parser.in_offset
7031 || intel_parser.in_bracket
7032 || (!(current_templates->start->opcode_modifier
7033 & (Jump|JumpDword|JumpInterSegment))
7034 && !(current_templates->start->operand_types[0]
7035 & JumpAbsolute)))
7036 return intel_match_token (T_NIL);
7037 /* Remember the start of the 2nd operand and terminate 1st
7038 operand here.
7039 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7040 another expression), but it gets at least the simplest case
7041 (a plain number or symbol on the left side) right. */
7042 intel_parser.next_operand = intel_parser.op_string;
7043 *--intel_parser.op_string = '\0';
7044 return intel_match_token (':');
7045 }
9306ca4a 7046 }
64a0c779 7047
a724f0f4 7048 /* e09' Empty */
64a0c779 7049 else
a724f0f4 7050 break;
64a0c779 7051
a724f0f4
JB		 7052 intel_match_token (cur_token.code);
7053
7054 }
7055
7056 if (in_offset)
7057 {
7058 --intel_parser.in_offset;
7059 if (nregs < 0)
7060 nregs = ~nregs;
7061 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7062 {
a724f0f4 7063 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7064 return 0;
7065 }
a724f0f4
JB		 7066 intel_parser.op_modifier |= 1 << T_OFFSET;
7067 }
9306ca4a 7068
a724f0f4
JB		 7069 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7070 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7071 return 1;
7072}
64a0c779 7073
a724f0f4
JB		 7074static int
7075intel_bracket_expr ()
7076{
7077 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7078 const char *start = intel_parser.op_string;
7079 int len;
7080
7081 if (i.op[this_operand].regs)
7082 return intel_match_token (T_NIL);
7083
7084 intel_match_token ('[');
7085
7086 /* Mark as a memory operand only if it's not already known to be an
7087 offset expression. If it's an offset expression, we need to keep
7088 the brace in. */
7089 if (!intel_parser.in_offset)
7090 {
7091 ++intel_parser.in_bracket;
435acd52
JB		 7092
7093 /* Operands for jump/call inside brackets denote absolute addresses. */
7094 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7095 i.types[this_operand] |= JumpAbsolute;
7096
a724f0f4
JB		 7097 /* Unfortunately gas always diverged from MASM in a respect that can't
7098 be easily fixed without risking to break code sequences likely to be
7099 encountered (the testsuite even check for this): MASM doesn't consider
7100 an expression inside brackets unconditionally as a memory reference.
7101 When that is e.g. a constant, an offset expression, or the sum of the
7102 two, this is still taken as a constant load. gas, however, always
7103 treated these as memory references. As a compromise, we'll try to make
7104 offset expressions inside brackets work the MASM way (since that's
7105 less likely to be found in real world code), but make constants alone
7106 continue to work the traditional gas way. In either case, issue a
7107 warning. */
7108 intel_parser.op_modifier &= ~was_offset;
64a0c779 7109 }
a724f0f4 7110 else
64e74474 7111 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7112
7113 /* Add a '+' to the displacement string if necessary. */
7114 if (*intel_parser.disp != '\0'
7115 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7116 strcat (intel_parser.disp, "+");
64a0c779 7117
a724f0f4
JB		 7118 if (intel_expr ()
7119 && (len = intel_parser.op_string - start - 1,
7120 intel_match_token (']')))
64a0c779 7121 {
a724f0f4
JB		 7122 /* Preserve brackets when the operand is an offset expression. */
7123 if (intel_parser.in_offset)
7124 strcat (intel_parser.disp, "]");
7125 else
7126 {
7127 --intel_parser.in_bracket;
7128 if (i.base_reg || i.index_reg)
7129 intel_parser.is_mem = 1;
7130 if (!intel_parser.is_mem)
7131 {
7132 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7133 /* Defer the warning until all of the operand was parsed. */
7134 intel_parser.is_mem = -1;
7135 else if (!quiet_warnings)
7136 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7137 }
7138 }
7139 intel_parser.op_modifier |= was_offset;
64a0c779 7140
a724f0f4 7141 return 1;
64a0c779 7142 }
a724f0f4 7143 return 0;
64a0c779
DN		 7144}
7145
7146/* e10 e11 e10'
7147
7148 e10' [ expr ] e10'
b77a7acd 7149 | Empty */
64a0c779
DN		 7150static int
7151intel_e10 ()
7152{
a724f0f4
JB		 7153 if (!intel_e11 ())
7154 return 0;
64a0c779 7155
a724f0f4 7156 while (cur_token.code == '[')
64a0c779 7157 {
a724f0f4 7158 if (!intel_bracket_expr ())
21d6c4af 7159 return 0;
64a0c779
DN		 7160 }
7161
a724f0f4 7162 return 1;
64a0c779
DN		 7163}
7164
64a0c779 7165/* e11 ( expr )
b77a7acd 7166 | [ expr ]
64a0c779
DN		 7167 | BYTE
7168 | WORD
7169 | DWORD
9306ca4a 7170 | FWORD
64a0c779 7171 | QWORD
9306ca4a
JB		 7172 | TBYTE
7173 | OWORD
7174 | XMMWORD
4a1805b1 7175 | $
64a0c779
DN		 7176 | .
7177 | register
7178 | id
7179 | constant */
7180static int
7181intel_e11 ()
7182{
a724f0f4 7183 switch (cur_token.code)
64a0c779 7184 {
a724f0f4
JB		 7185 /* e11 ( expr ) */
7186 case '(':
64a0c779
DN		 7187 intel_match_token ('(');
7188 strcat (intel_parser.disp, "(");
7189
7190 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7191 {
7192 strcat (intel_parser.disp, ")");
7193 return 1;
7194 }
a724f0f4 7195 return 0;
4a1805b1 7196
a724f0f4
JB		 7197 /* e11 [ expr ] */
7198 case '[':
a724f0f4 7199 return intel_bracket_expr ();
64a0c779 7200
a724f0f4
JB		 7201 /* e11 $
7202 | . */
7203 case '.':
64a0c779
DN		 7204 strcat (intel_parser.disp, cur_token.str);
7205 intel_match_token (cur_token.code);
21d6c4af
DN		 7206
7207 /* Mark as a memory operand only if it's not already known to be an
7208 offset expression. */
a724f0f4 7209 if (!intel_parser.in_offset)
21d6c4af 7210 intel_parser.is_mem = 1;
64a0c779
DN		 7211
7212 return 1;
64a0c779 7213
a724f0f4
JB		 7214 /* e11 register */
7215 case T_REG:
7216 {
7217 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7218
a724f0f4 7219 intel_match_token (T_REG);
64a0c779 7220
a724f0f4
JB		 7221 /* Check for segment change. */
7222 if (cur_token.code == ':')
7223 {
7224 if (!(reg->reg_type & (SReg2 | SReg3)))
7225 {
7226 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7227 return 0;
7228 }
7229 else if (i.seg[i.mem_operands])
7230 as_warn (_("Extra segment override ignored"));
7231 else
7232 {
7233 if (!intel_parser.in_offset)
7234 intel_parser.is_mem = 1;
7235 switch (reg->reg_num)
7236 {
7237 case 0:
7238 i.seg[i.mem_operands] = &es;
7239 break;
7240 case 1:
7241 i.seg[i.mem_operands] = &cs;
7242 break;
7243 case 2:
7244 i.seg[i.mem_operands] = &ss;
7245 break;
7246 case 3:
7247 i.seg[i.mem_operands] = &ds;
7248 break;
7249 case 4:
7250 i.seg[i.mem_operands] = &fs;
7251 break;
7252 case 5:
7253 i.seg[i.mem_operands] = &gs;
7254 break;
7255 }
7256 }
7257 }
64a0c779 7258
a724f0f4
JB		 7259 /* Not a segment register. Check for register scaling. */
7260 else if (cur_token.code == '*')
7261 {
7262 if (!intel_parser.in_bracket)
7263 {
7264 as_bad (_("Register scaling only allowed in memory operands"));
7265 return 0;
7266 }
64a0c779 7267
a724f0f4
JB		 7268 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7269 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7270 else if (i.index_reg)
7271 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7272
a724f0f4
JB		 7273 /* What follows must be a valid scale. */
7274 intel_match_token ('*');
7275 i.index_reg = reg;
7276 i.types[this_operand] |= BaseIndex;
64a0c779 7277
a724f0f4
JB		 7278 /* Set the scale after setting the register (otherwise,
7279 i386_scale will complain) */
7280 if (cur_token.code == '+' || cur_token.code == '-')
7281 {
7282 char *str, sign = cur_token.code;
7283 intel_match_token (cur_token.code);
7284 if (cur_token.code != T_CONST)
7285 {
7286 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7287 cur_token.str);
7288 return 0;
7289 }
7290 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7291 strcpy (str + 1, cur_token.str);
7292 *str = sign;
7293 if (!i386_scale (str))
7294 return 0;
7295 free (str);
7296 }
7297 else if (!i386_scale (cur_token.str))
64a0c779 7298 return 0;
a724f0f4
JB		 7299 intel_match_token (cur_token.code);
7300 }
64a0c779 7301
a724f0f4
JB		 7302 /* No scaling. If this is a memory operand, the register is either a
7303 base register (first occurrence) or an index register (second
7304 occurrence). */
7b0441f6 7305 else if (intel_parser.in_bracket)
a724f0f4 7306 {
64a0c779 7307
a724f0f4
JB		 7308 if (!i.base_reg)
7309 i.base_reg = reg;
7310 else if (!i.index_reg)
7311 i.index_reg = reg;
7312 else
7313 {
7314 as_bad (_("Too many register references in memory operand"));
7315 return 0;
7316 }
64a0c779 7317
a724f0f4
JB		 7318 i.types[this_operand] |= BaseIndex;
7319 }
4a1805b1 7320
4d1bb795
JB		 7321 /* It's neither base nor index. */
7322 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7323 {
7324 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7325 i.op[this_operand].regs = reg;
7326 i.reg_operands++;
7327 }
7328 else
7329 {
7330 as_bad (_("Invalid use of register"));
7331 return 0;
7332 }
64a0c779 7333
a724f0f4
JB		 7334 /* Since registers are not part of the displacement string (except
7335 when we're parsing offset operands), we may need to remove any
7336 preceding '+' from the displacement string. */
7337 if (*intel_parser.disp != '\0'
7338 && !intel_parser.in_offset)
7339 {
7340 char *s = intel_parser.disp;
7341 s += strlen (s) - 1;
7342 if (*s == '+')
7343 *s = '\0';
7344 }
4a1805b1 7345
a724f0f4
JB		 7346 return 1;
7347 }
7348
7349 /* e11 BYTE
7350 | WORD
7351 | DWORD
7352 | FWORD
7353 | QWORD
7354 | TBYTE
7355 | OWORD
7356 | XMMWORD */
7357 case T_BYTE:
7358 case T_WORD:
7359 case T_DWORD:
7360 case T_FWORD:
7361 case T_QWORD:
7362 case T_TBYTE:
7363 case T_XMMWORD:
7364 intel_match_token (cur_token.code);
64a0c779 7365
a724f0f4
JB		 7366 if (cur_token.code == T_PTR)
7367 return 1;
7368
7369 /* It must have been an identifier. */
7370 intel_putback_token ();
7371 cur_token.code = T_ID;
7372 /* FALLTHRU */
7373
7374 /* e11 id
7375 | constant */
7376 case T_ID:
7377 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7378 {
7379 symbolS *symbolP;
7380
a724f0f4
JB		 7381 /* The identifier represents a memory reference only if it's not
7382 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7383 symbolP = symbol_find(cur_token.str);
7384 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7385 intel_parser.is_mem = 1;
7386 }
a724f0f4 7387 /* FALLTHRU */
64a0c779 7388
a724f0f4
JB		 7389 case T_CONST:
7390 case '-':
7391 case '+':
7392 {
7393 char *save_str, sign = 0;
64a0c779 7394
a724f0f4
JB		 7395 /* Allow constants that start with `+' or `-'. */
7396 if (cur_token.code == '-' || cur_token.code == '+')
7397 {
7398 sign = cur_token.code;
7399 intel_match_token (cur_token.code);
7400 if (cur_token.code != T_CONST)
7401 {
7402 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7403 cur_token.str);
7404 return 0;
7405 }
7406 }
64a0c779 7407
a724f0f4
JB		 7408 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7409 strcpy (save_str + !!sign, cur_token.str);
7410 if (sign)
7411 *save_str = sign;
64a0c779 7412
a724f0f4
JB		 7413 /* Get the next token to check for register scaling. */
7414 intel_match_token (cur_token.code);
64a0c779 7415
a724f0f4
JB		 7416 /* Check if this constant is a scaling factor for an index register. */
7417 if (cur_token.code == '*')
7418 {
7419 if (intel_match_token ('*') && cur_token.code == T_REG)
7420 {
7421 const reg_entry *reg = cur_token.reg;
7422
7423 if (!intel_parser.in_bracket)
7424 {
7425 as_bad (_("Register scaling only allowed in memory operands"));
7426 return 0;
7427 }
7428
7429 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7430 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7431 else if (i.index_reg)
7432 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7433
7434 /* The constant is followed by `* reg', so it must be
7435 a valid scale. */
7436 i.index_reg = reg;
7437 i.types[this_operand] |= BaseIndex;
7438
7439 /* Set the scale after setting the register (otherwise,
7440 i386_scale will complain) */
7441 if (!i386_scale (save_str))
64a0c779 7442 return 0;
a724f0f4
JB		 7443 intel_match_token (T_REG);
7444
7445 /* Since registers are not part of the displacement
7446 string, we may need to remove any preceding '+' from
7447 the displacement string. */
7448 if (*intel_parser.disp != '\0')
7449 {
7450 char *s = intel_parser.disp;
7451 s += strlen (s) - 1;
7452 if (*s == '+')
7453 *s = '\0';
7454 }
7455
7456 free (save_str);
7457
7458 return 1;
7459 }
64a0c779 7460
a724f0f4
JB		 7461 /* The constant was not used for register scaling. Since we have
7462 already consumed the token following `*' we now need to put it
7463 back in the stream. */
64a0c779 7464 intel_putback_token ();
a724f0f4 7465 }
64a0c779 7466
a724f0f4
JB		 7467 /* Add the constant to the displacement string. */
7468 strcat (intel_parser.disp, save_str);
7469 free (save_str);
64a0c779 7470
a724f0f4
JB		 7471 return 1;
7472 }
64a0c779
DN		 7473 }
7474
64a0c779
DN		 7475 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7476 return 0;
7477}
7478
64a0c779
DN		 7479/* Match the given token against cur_token. If they match, read the next
7480 token from the operand string. */
7481static int
7482intel_match_token (code)
e5cb08ac 7483 int code;
64a0c779
DN		 7484{
7485 if (cur_token.code == code)
7486 {
7487 intel_get_token ();
7488 return 1;
7489 }
7490 else
7491 {
0477af35 7492 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7493 return 0;
7494 }
7495}
7496
64a0c779
DN		 7497/* Read a new token from intel_parser.op_string and store it in cur_token. */
7498static void
7499intel_get_token ()
7500{
7501 char *end_op;
7502 const reg_entry *reg;
7503 struct intel_token new_token;
7504
7505 new_token.code = T_NIL;
7506 new_token.reg = NULL;
7507 new_token.str = NULL;
7508
4a1805b1 7509 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7510 cur_token to prev_token. */
7511 if (prev_token.str)
7512 free (prev_token.str);
7513
7514 prev_token = cur_token;
7515
7516 /* Skip whitespace. */
7517 while (is_space_char (*intel_parser.op_string))
7518 intel_parser.op_string++;
7519
7520 /* Return an empty token if we find nothing else on the line. */
7521 if (*intel_parser.op_string == '\0')
7522 {
7523 cur_token = new_token;
7524 return;
7525 }
7526
7527 /* The new token cannot be larger than the remainder of the operand
7528 string. */
a724f0f4 7529 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7530 new_token.str[0] = '\0';
7531
7532 if (strchr ("0123456789", *intel_parser.op_string))
7533 {
7534 char *p = new_token.str;
7535 char *q = intel_parser.op_string;
7536 new_token.code = T_CONST;
7537
7538 /* Allow any kind of identifier char to encompass floating point and
7539 hexadecimal numbers. */
7540 while (is_identifier_char (*q))
7541 *p++ = *q++;
7542 *p = '\0';
7543
7544 /* Recognize special symbol names [0-9][bf]. */
7545 if (strlen (intel_parser.op_string) == 2
4a1805b1 7546 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7547 || intel_parser.op_string[1] == 'f'))
7548 new_token.code = T_ID;
7549 }
7550
4d1bb795 7551 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7552 {
4d1bb795
JB		 7553 size_t len = end_op - intel_parser.op_string;
7554
64a0c779
DN		 7555 new_token.code = T_REG;
7556 new_token.reg = reg;
7557
4d1bb795
JB		 7558 memcpy (new_token.str, intel_parser.op_string, len);
7559 new_token.str[len] = '\0';
64a0c779
DN		 7560 }
7561
7562 else if (is_identifier_char (*intel_parser.op_string))
7563 {
7564 char *p = new_token.str;
7565 char *q = intel_parser.op_string;
7566
7567 /* A '.' or '$' followed by an identifier char is an identifier.
7568 Otherwise, it's operator '.' followed by an expression. */
7569 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7570 {
9306ca4a
JB		 7571 new_token.code = '.';
7572 new_token.str[0] = '.';
64a0c779
DN		 7573 new_token.str[1] = '\0';
7574 }
7575 else
7576 {
7577 while (is_identifier_char (*q) || *q == '@')
7578 *p++ = *q++;
7579 *p = '\0';
7580
9306ca4a
JB		 7581 if (strcasecmp (new_token.str, "NOT") == 0)
7582 new_token.code = '~';
7583
7584 else if (strcasecmp (new_token.str, "MOD") == 0)
7585 new_token.code = '%';
7586
7587 else if (strcasecmp (new_token.str, "AND") == 0)
7588 new_token.code = '&';
7589
7590 else if (strcasecmp (new_token.str, "OR") == 0)
7591 new_token.code = '|';
7592
7593 else if (strcasecmp (new_token.str, "XOR") == 0)
7594 new_token.code = '^';
7595
7596 else if (strcasecmp (new_token.str, "SHL") == 0)
7597 new_token.code = T_SHL;
7598
7599 else if (strcasecmp (new_token.str, "SHR") == 0)
7600 new_token.code = T_SHR;
7601
7602 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7603 new_token.code = T_BYTE;
7604
7605 else if (strcasecmp (new_token.str, "WORD") == 0)
7606 new_token.code = T_WORD;
7607
7608 else if (strcasecmp (new_token.str, "DWORD") == 0)
7609 new_token.code = T_DWORD;
7610
9306ca4a
JB		 7611 else if (strcasecmp (new_token.str, "FWORD") == 0)
7612 new_token.code = T_FWORD;
7613
64a0c779
DN		 7614 else if (strcasecmp (new_token.str, "QWORD") == 0)
7615 new_token.code = T_QWORD;
7616
9306ca4a
JB		 7617 else if (strcasecmp (new_token.str, "TBYTE") == 0
7618 /* XXX remove (gcc still uses it) */
7619 || strcasecmp (new_token.str, "XWORD") == 0)
7620 new_token.code = T_TBYTE;
7621
7622 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7623 || strcasecmp (new_token.str, "OWORD") == 0)
7624 new_token.code = T_XMMWORD;
64a0c779
DN		 7625
7626 else if (strcasecmp (new_token.str, "PTR") == 0)
7627 new_token.code = T_PTR;
7628
7629 else if (strcasecmp (new_token.str, "SHORT") == 0)
7630 new_token.code = T_SHORT;
7631
7632 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7633 {
7634 new_token.code = T_OFFSET;
7635
7636 /* ??? This is not mentioned in the MASM grammar but gcc
7637 makes use of it with -mintel-syntax. OFFSET may be
7638 followed by FLAT: */
7639 if (strncasecmp (q, " FLAT:", 6) == 0)
7640 strcat (new_token.str, " FLAT:");
7641 }
7642
7643 /* ??? This is not mentioned in the MASM grammar. */
7644 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7645 {
7646 new_token.code = T_OFFSET;
7647 if (*q == ':')
7648 strcat (new_token.str, ":");
7649 else
7650 as_bad (_("`:' expected"));
7651 }
64a0c779
DN		 7652
7653 else
7654 new_token.code = T_ID;
7655 }
7656 }
7657
9306ca4a
JB		 7658 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7659 {
7660 new_token.code = *intel_parser.op_string;
7661 new_token.str[0] = *intel_parser.op_string;
7662 new_token.str[1] = '\0';
7663 }
7664
7665 else if (strchr ("<>", *intel_parser.op_string)
7666 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7667 {
7668 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7669 new_token.str[0] = *intel_parser.op_string;
7670 new_token.str[1] = *intel_parser.op_string;
7671 new_token.str[2] = '\0';
7672 }
7673
64a0c779 7674 else
0477af35 7675 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7676
7677 intel_parser.op_string += strlen (new_token.str);
7678 cur_token = new_token;
7679}
7680
64a0c779
DN		 7681/* Put cur_token back into the token stream and make cur_token point to
7682 prev_token. */
7683static void
7684intel_putback_token ()
7685{
a724f0f4
JB		 7686 if (cur_token.code != T_NIL)
7687 {
7688 intel_parser.op_string -= strlen (cur_token.str);
7689 free (cur_token.str);
7690 }
64a0c779 7691 cur_token = prev_token;
4a1805b1 7692
64a0c779
DN		 7693 /* Forget prev_token. */
7694 prev_token.code = T_NIL;
7695 prev_token.reg = NULL;
7696 prev_token.str = NULL;
7697}
54cfded0 7698
a4447b93 7699int
1df69f4f 7700tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7701{
7702 unsigned int regnum;
7703 unsigned int regnames_count;
089dfecd 7704 static const char *const regnames_32[] =
54cfded0 7705 {
a4447b93
RH		 7706 "eax", "ecx", "edx", "ebx",
7707 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7708 "eip", "eflags", NULL,
7709 "st0", "st1", "st2", "st3",
7710 "st4", "st5", "st6", "st7",
7711 NULL, NULL,
7712 "xmm0", "xmm1", "xmm2", "xmm3",
7713 "xmm4", "xmm5", "xmm6", "xmm7",
7714 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7715 "mm4", "mm5", "mm6", "mm7",
7716 "fcw", "fsw", "mxcsr",
7717 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7718 "tr", "ldtr"
54cfded0 7719 };
089dfecd 7720 static const char *const regnames_64[] =
54cfded0 7721 {
089dfecd
JB		 7722 "rax", "rdx", "rcx", "rbx",
7723 "rsi", "rdi", "rbp", "rsp",
7724 "r8", "r9", "r10", "r11",
54cfded0 7725 "r12", "r13", "r14", "r15",
089dfecd
JB		 7726 "rip",
7727 "xmm0", "xmm1", "xmm2", "xmm3",
7728 "xmm4", "xmm5", "xmm6", "xmm7",
7729 "xmm8", "xmm9", "xmm10", "xmm11",
7730 "xmm12", "xmm13", "xmm14", "xmm15",
7731 "st0", "st1", "st2", "st3",
7732 "st4", "st5", "st6", "st7",
7733 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7734 "mm4", "mm5", "mm6", "mm7",
7735 "rflags",
7736 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7737 "fs.base", "gs.base", NULL, NULL,
7738 "tr", "ldtr",
7739 "mxcsr", "fcw", "fsw"
54cfded0 7740 };
089dfecd 7741 const char *const *regnames;
54cfded0
AM		 7742
7743 if (flag_code == CODE_64BIT)
7744 {
7745 regnames = regnames_64;
0cea6190 7746 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7747 }
7748 else
7749 {
7750 regnames = regnames_32;
0cea6190 7751 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7752 }
7753
7754 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7755 if (regnames[regnum] != NULL
7756 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7757 return regnum;
7758
54cfded0
AM		 7759 return -1;
7760}
7761
7762void
7763tc_x86_frame_initial_instructions (void)
7764{
a4447b93
RH		 7765 static unsigned int sp_regno;
7766
7767 if (!sp_regno)
7768 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7769 ? "rsp" : "esp");
7770
7771 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7772 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7773}
d2b2c203
DJ		 7774
7775int
7776i386_elf_section_type (const char *str, size_t len)
7777{
7778 if (flag_code == CODE_64BIT
7779 && len == sizeof ("unwind") - 1
7780 && strncmp (str, "unwind", 6) == 0)
7781 return SHT_X86_64_UNWIND;
7782
7783 return -1;
7784}
bb41ade5
AM		 7785
7786#ifdef TE_PE
7787void
7788tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7789{
7790 expressionS expr;
7791
7792 expr.X_op = O_secrel;
7793 expr.X_add_symbol = symbol;
7794 expr.X_add_number = 0;
7795 emit_expr (&expr, size);
7796}
7797#endif
3b22753a
L		 7798
7799#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7800/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7801
7802int
7803x86_64_section_letter (int letter, char **ptr_msg)
7804{
7805 if (flag_code == CODE_64BIT)
7806 {
7807 if (letter == 'l')
7808 return SHF_X86_64_LARGE;
7809
7810 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7811 }
3b22753a 7812 else
64e74474 7813 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7814 return -1;
7815}
7816
7817int
7818x86_64_section_word (char *str, size_t len)
7819{
8620418b 7820 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7821 return SHF_X86_64_LARGE;
7822
7823 return -1;
7824}
7825
7826static void
7827handle_large_common (int small ATTRIBUTE_UNUSED)
7828{
7829 if (flag_code != CODE_64BIT)
7830 {
7831 s_comm_internal (0, elf_common_parse);
7832 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7833 }
7834 else
7835 {
7836 static segT lbss_section;
7837 asection *saved_com_section_ptr = elf_com_section_ptr;
7838 asection *saved_bss_section = bss_section;
7839
7840 if (lbss_section == NULL)
7841 {
7842 flagword applicable;
7843 segT seg = now_seg;
7844 subsegT subseg = now_subseg;
7845
7846 /* The .lbss section is for local .largecomm symbols. */
7847 lbss_section = subseg_new (".lbss", 0);
7848 applicable = bfd_applicable_section_flags (stdoutput);
7849 bfd_set_section_flags (stdoutput, lbss_section,
7850 applicable & SEC_ALLOC);
7851 seg_info (lbss_section)->bss = 1;
7852
7853 subseg_set (seg, subseg);
7854 }
7855
7856 elf_com_section_ptr = &_bfd_elf_large_com_section;
7857 bss_section = lbss_section;
7858
7859 s_comm_internal (0, elf_common_parse);
7860
7861 elf_com_section_ptr = saved_com_section_ptr;
7862 bss_section = saved_bss_section;
7863 }
7864}
7865#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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