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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
185#endif
252b5132 186
a847613f 187static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 188
c0f3af97
L		 189/* VEX prefix. */
190typedef struct
191{
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197} vex_prefix;
198
252b5132 199/* 'md_assemble ()' gathers together information and puts it into a
47926f60 200 i386_insn. */
252b5132 201
520dc8e8
AM		 202union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
a65babc9
L		 209enum i386_error
210 {
86e026a4 211 operand_size_mismatch,
a65babc9
L		 212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
252b5132
RH		 223struct _i386_insn
224 {
47926f60 225 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 226 insn_template tm;
252b5132 227
7d5e4556
L		 228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
252b5132
RH		 230 char suffix;
231
47926f60 232 /* OPERANDS gives the number of given operands. */
252b5132
RH		 233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
47926f60 237 operands. */
252b5132
RH		 238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 241 use OP[i] for the corresponding operand. */
40fb9820 242 i386_operand_type types[MAX_OPERANDS];
252b5132 243
520dc8e8
AM		 244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
252b5132 247
3e73aa7c
JH		 248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250#define Operand_PCrel 1
251
252b5132 252 /* Relocation type for operand */
f86103b7 253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 254
252b5132
RH		 255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 262 explicit segment overrides are given. */
ce8a8b2f 263 const seg_entry *seg[2];
252b5132
RH		 264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 271 addressing modes of this insn are encoded. */
252b5132 272 modrm_byte rm;
3e73aa7c 273 rex_byte rex;
252b5132 274 sib_byte sib;
c0f3af97 275 vex_prefix vex;
b6169b20
L		 276
277 /* Swap operand in encoding. */
4473e004 278 unsigned int swap_operand;
891edac4 279
f8a5c266
L		 280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding;
282
891edac4 283 /* Error message. */
a65babc9 284 enum i386_error error;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60 379/* Current operand we are working on. */
ee86248c 380static int this_operand = -1;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
7af8ed2d
NC		 394#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
395 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
396 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
397
351f65ca
L		 398/* The ELF ABI to use. */
399enum x86_elf_abi
400{
401 I386_ABI,
402 X86_64_LP64_ABI,
403 X86_64_ILP32_ABI
404};
405
406static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 407#endif
351f65ca 408
3e73aa7c 409/* The names used to print error messages. */
b77a7acd 410static const char *flag_code_names[] =
3e73aa7c
JH		 411 {
412 "32",
413 "16",
414 "64"
415 };
252b5132 416
47926f60
KH		 417/* 1 for intel syntax,
418 0 if att syntax. */
419static int intel_syntax = 0;
252b5132 420
1efbbeb4
L		 421/* 1 for intel mnemonic,
422 0 if att mnemonic. */
423static int intel_mnemonic = !SYSV386_COMPAT;
424
5209009a 425/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 426static int old_gcc = OLDGCC_COMPAT;
427
a60de03c
JB		 428/* 1 if pseudo registers are permitted. */
429static int allow_pseudo_reg = 0;
430
47926f60
KH		 431/* 1 if register prefix % not required. */
432static int allow_naked_reg = 0;
252b5132 433
ba104c83 434/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 435static int allow_index_reg = 0;
436
daf50ae7
L		 437static enum
438 {
439 sse_check_none = 0,
440 sse_check_warning,
441 sse_check_error
442 }
443sse_check;
444
2ca3ace5
L		 445/* Register prefix used for error message. */
446static const char *register_prefix = "%";
447
47926f60
KH		 448/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
449 leave, push, and pop instructions so that gcc has the same stack
450 frame as in 32 bit mode. */
451static char stackop_size = '\0';
eecb386c 452
12b55ccc
L		 453/* Non-zero to optimize code alignment. */
454int optimize_align_code = 1;
455
47926f60
KH		 456/* Non-zero to quieten some warnings. */
457static int quiet_warnings = 0;
a38cf1db 458
47926f60
KH		 459/* CPU name. */
460static const char *cpu_arch_name = NULL;
6305a203 461static char *cpu_sub_arch_name = NULL;
a38cf1db 462
47926f60 463/* CPU feature flags. */
40fb9820
L		 464static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
465
ccc9c027
L		 466/* If we have selected a cpu we are generating instructions for. */
467static int cpu_arch_tune_set = 0;
468
9103f4f4 469/* Cpu we are generating instructions for. */
fbf3f584 470enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 471
472/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 473static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 474
ccc9c027 475/* CPU instruction set architecture used. */
fbf3f584 476enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 477
9103f4f4 478/* CPU feature flags of instruction set architecture used. */
fbf3f584 479i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 480
fddf5b5b
AM		 481/* If set, conditional jumps are not automatically promoted to handle
482 larger than a byte offset. */
483static unsigned int no_cond_jump_promotion = 0;
484
c0f3af97
L		 485/* Encode SSE instructions with VEX prefix. */
486static unsigned int sse2avx;
487
539f890d
L		 488/* Encode scalar AVX instructions with specific vector length. */
489static enum
490 {
491 vex128 = 0,
492 vex256
493 } avxscalar;
494
29b0f896 495/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 496static symbolS *GOT_symbol;
29b0f896 497
a4447b93
RH		 498/* The dwarf2 return column, adjusted for 32 or 64 bit. */
499unsigned int x86_dwarf2_return_column;
500
501/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
502int x86_cie_data_alignment;
503
252b5132 504/* Interface to relax_segment.
fddf5b5b
AM		 505 There are 3 major relax states for 386 jump insns because the
506 different types of jumps add different sizes to frags when we're
507 figuring out what sort of jump to choose to reach a given label. */
252b5132 508
47926f60 509/* Types. */
93c2a809
AM		 510#define UNCOND_JUMP 0
511#define COND_JUMP 1
512#define COND_JUMP86 2
fddf5b5b 513
47926f60 514/* Sizes. */
252b5132
RH		 515#define CODE16 1
516#define SMALL 0
29b0f896 517#define SMALL16 (SMALL | CODE16)
252b5132 518#define BIG 2
29b0f896 519#define BIG16 (BIG | CODE16)
252b5132
RH		 520
521#ifndef INLINE
522#ifdef __GNUC__
523#define INLINE __inline__
524#else
525#define INLINE
526#endif
527#endif
528
fddf5b5b
AM		 529#define ENCODE_RELAX_STATE(type, size) \
530 ((relax_substateT) (((type) << 2) | (size)))
531#define TYPE_FROM_RELAX_STATE(s) \
532 ((s) >> 2)
533#define DISP_SIZE_FROM_RELAX_STATE(s) \
534 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 535
536/* This table is used by relax_frag to promote short jumps to long
537 ones where necessary. SMALL (short) jumps may be promoted to BIG
538 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
539 don't allow a short jump in a 32 bit code segment to be promoted to
540 a 16 bit offset jump because it's slower (requires data size
541 prefix), and doesn't work, unless the destination is in the bottom
542 64k of the code segment (The top 16 bits of eip are zeroed). */
543
544const relax_typeS md_relax_table[] =
545{
24eab124
AM		 546 /* The fields are:
547 1) most positive reach of this state,
548 2) most negative reach of this state,
93c2a809 549 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 550 4) which index into the table to try if we can't fit into this one. */
252b5132 551
fddf5b5b 552 /* UNCOND_JUMP states. */
93c2a809
AM		 553 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
555 /* dword jmp adds 4 bytes to frag:
556 0 extra opcode bytes, 4 displacement bytes. */
252b5132 557 {0, 0, 4, 0},
93c2a809
AM		 558 /* word jmp adds 2 byte2 to frag:
559 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 560 {0, 0, 2, 0},
561
93c2a809
AM		 562 /* COND_JUMP states. */
563 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
564 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
565 /* dword conditionals adds 5 bytes to frag:
566 1 extra opcode byte, 4 displacement bytes. */
567 {0, 0, 5, 0},
fddf5b5b 568 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 569 1 extra opcode byte, 2 displacement bytes. */
570 {0, 0, 3, 0},
571
572 /* COND_JUMP86 states. */
573 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
574 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
575 /* dword conditionals adds 5 bytes to frag:
576 1 extra opcode byte, 4 displacement bytes. */
577 {0, 0, 5, 0},
578 /* word conditionals add 4 bytes to frag:
579 1 displacement byte and a 3 byte long branch insn. */
580 {0, 0, 4, 0}
252b5132
RH		 581};
582
9103f4f4
L		 583static const arch_entry cpu_arch[] =
584{
89507696
JB		 585 /* Do not replace the first two entries - i386_target_format()
586 relies on them being there in this order. */
8a2c8fef 587 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 588 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 589 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 590 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 591 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 592 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 593 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 594 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 595 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 596 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 597 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 598 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 599 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 600 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 601 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 602 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 603 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 604 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 605 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 606 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 607 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 608 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 609 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 610 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 611 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 612 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 613 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 614 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 615 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 616 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 617 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 618 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 619 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 620 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 621 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 622 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 623 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 624 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 625 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 626 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 627 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 628 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 629 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 630 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 631 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 632 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 633 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 634 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 635 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 636 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 637 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 638 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 639 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 640 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 641 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 642 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 643 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 644 CPU_AMDFAM10_FLAGS, 0, 0 },
68339fdf 645 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
22109423 646 CPU_BDVER1_FLAGS, 0, 0 },
8a2c8fef 647 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 648 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 649 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 650 CPU_287_FLAGS, 0, 0 },
8a2c8fef 651 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 652 CPU_387_FLAGS, 0, 0 },
8a2c8fef 653 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 654 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 655 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 656 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 657 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 658 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 659 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 660 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 661 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 662 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 663 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 664 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 665 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 666 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 667 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 668 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 669 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 670 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 671 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 672 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 673 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 674 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 675 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 676 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 677 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 678 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 679 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 680 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 681 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 682 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 683 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 684 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 685 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 686 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 687 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 688 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 689 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 690 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 691 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 692 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 693 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 694 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 695 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 696 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 697 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 698 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 699 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 700 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 701 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 702 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 703 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 704 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 705 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 706 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 707 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 708 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 709 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 710 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 712 CPU_CLFLUSH_FLAGS, 0, 0 },
713 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
714 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 716 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 718 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 720 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 722 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 724 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 726 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 727 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 728 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 730 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 732 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 733 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
734 CPU_BMI_FLAGS, 0, 0 },
e413e4e9
AM		 735};
736
704209c0 737#ifdef I386COFF
a6c24e68
NC		 738/* Like s_lcomm_internal in gas/read.c but the alignment string
739 is allowed to be optional. */
740
741static symbolS *
742pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
743{
744 addressT align = 0;
745
746 SKIP_WHITESPACE ();
747
7ab9ffdd 748 if (needs_align
a6c24e68
NC		 749 && *input_line_pointer == ',')
750 {
751 align = parse_align (needs_align - 1);
7ab9ffdd 752
a6c24e68
NC		 753 if (align == (addressT) -1)
754 return NULL;
755 }
756 else
757 {
758 if (size >= 8)
759 align = 3;
760 else if (size >= 4)
761 align = 2;
762 else if (size >= 2)
763 align = 1;
764 else
765 align = 0;
766 }
767
768 bss_alloc (symbolP, size, align);
769 return symbolP;
770}
771
704209c0 772static void
a6c24e68
NC		 773pe_lcomm (int needs_align)
774{
775 s_comm_internal (needs_align * 2, pe_lcomm_internal);
776}
704209c0 777#endif
a6c24e68 778
29b0f896
AM		 779const pseudo_typeS md_pseudo_table[] =
780{
781#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
782 {"align", s_align_bytes, 0},
783#else
784 {"align", s_align_ptwo, 0},
785#endif
786 {"arch", set_cpu_arch, 0},
787#ifndef I386COFF
788 {"bss", s_bss, 0},
a6c24e68
NC		 789#else
790 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 791#endif
792 {"ffloat", float_cons, 'f'},
793 {"dfloat", float_cons, 'd'},
794 {"tfloat", float_cons, 'x'},
795 {"value", cons, 2},
d182319b 796 {"slong", signed_cons, 4},
29b0f896
AM		 797 {"noopt", s_ignore, 0},
798 {"optim", s_ignore, 0},
799 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
800 {"code16", set_code_flag, CODE_16BIT},
801 {"code32", set_code_flag, CODE_32BIT},
802 {"code64", set_code_flag, CODE_64BIT},
803 {"intel_syntax", set_intel_syntax, 1},
804 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 805 {"intel_mnemonic", set_intel_mnemonic, 1},
806 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 807 {"allow_index_reg", set_allow_index_reg, 1},
808 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 809 {"sse_check", set_sse_check, 0},
3b22753a
L		 810#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
811 {"largecomm", handle_large_common, 0},
07a53e5c 812#else
e3bb37b5 813 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 814 {"loc", dwarf2_directive_loc, 0},
815 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 816#endif
6482c264
NC		 817#ifdef TE_PE
818 {"secrel32", pe_directive_secrel, 0},
819#endif
29b0f896
AM		 820 {0, 0, 0}
821};
822
823/* For interface with expression (). */
824extern char *input_line_pointer;
825
826/* Hash table for instruction mnemonic lookup. */
827static struct hash_control *op_hash;
828
829/* Hash table for register lookup. */
830static struct hash_control *reg_hash;
831\f
252b5132 832void
e3bb37b5 833i386_align_code (fragS *fragP, int count)
252b5132 834{
ce8a8b2f
AM		 835 /* Various efficient no-op patterns for aligning code labels.
836 Note: Don't try to assemble the instructions in the comments.
837 0L and 0w are not legal. */
252b5132
RH		 838 static const char f32_1[] =
839 {0x90}; /* nop */
840 static const char f32_2[] =
ccc9c027 841 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 842 static const char f32_3[] =
843 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
844 static const char f32_4[] =
845 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
846 static const char f32_5[] =
847 {0x90, /* nop */
848 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
849 static const char f32_6[] =
850 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
851 static const char f32_7[] =
852 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
853 static const char f32_8[] =
854 {0x90, /* nop */
855 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
856 static const char f32_9[] =
857 {0x89,0xf6, /* movl %esi,%esi */
858 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
859 static const char f32_10[] =
860 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
861 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
862 static const char f32_11[] =
863 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
864 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
865 static const char f32_12[] =
866 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
867 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
868 static const char f32_13[] =
869 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
870 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
871 static const char f32_14[] =
872 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
873 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 874 static const char f16_3[] =
875 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 876 static const char f16_4[] =
877 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
878 static const char f16_5[] =
879 {0x90, /* nop */
880 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
881 static const char f16_6[] =
882 {0x89,0xf6, /* mov %si,%si */
883 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
884 static const char f16_7[] =
885 {0x8d,0x74,0x00, /* lea 0(%si),%si */
886 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
887 static const char f16_8[] =
888 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
889 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 890 static const char jump_31[] =
891 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
892 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
893 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
894 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 895 static const char *const f32_patt[] = {
896 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 897 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 898 };
899 static const char *const f16_patt[] = {
76bc74dc 900 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 901 };
ccc9c027
L		 902 /* nopl (%[re]ax) */
903 static const char alt_3[] =
904 {0x0f,0x1f,0x00};
905 /* nopl 0(%[re]ax) */
906 static const char alt_4[] =
907 {0x0f,0x1f,0x40,0x00};
908 /* nopl 0(%[re]ax,%[re]ax,1) */
909 static const char alt_5[] =
910 {0x0f,0x1f,0x44,0x00,0x00};
911 /* nopw 0(%[re]ax,%[re]ax,1) */
912 static const char alt_6[] =
913 {0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopl 0L(%[re]ax) */
915 static const char alt_7[] =
916 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
917 /* nopl 0L(%[re]ax,%[re]ax,1) */
918 static const char alt_8[] =
919 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
920 /* nopw 0L(%[re]ax,%[re]ax,1) */
921 static const char alt_9[] =
922 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
923 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
924 static const char alt_10[] =
925 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
926 /* data16
927 nopw %cs:0L(%[re]ax,%[re]ax,1) */
928 static const char alt_long_11[] =
929 {0x66,
930 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 /* data16
932 data16
933 nopw %cs:0L(%[re]ax,%[re]ax,1) */
934 static const char alt_long_12[] =
935 {0x66,
936 0x66,
937 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 /* data16
939 data16
940 data16
941 nopw %cs:0L(%[re]ax,%[re]ax,1) */
942 static const char alt_long_13[] =
943 {0x66,
944 0x66,
945 0x66,
946 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
947 /* data16
948 data16
949 data16
950 data16
951 nopw %cs:0L(%[re]ax,%[re]ax,1) */
952 static const char alt_long_14[] =
953 {0x66,
954 0x66,
955 0x66,
956 0x66,
957 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
958 /* data16
959 data16
960 data16
961 data16
962 data16
963 nopw %cs:0L(%[re]ax,%[re]ax,1) */
964 static const char alt_long_15[] =
965 {0x66,
966 0x66,
967 0x66,
968 0x66,
969 0x66,
970 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 /* nopl 0(%[re]ax,%[re]ax,1)
972 nopw 0(%[re]ax,%[re]ax,1) */
973 static const char alt_short_11[] =
974 {0x0f,0x1f,0x44,0x00,0x00,
975 0x66,0x0f,0x1f,0x44,0x00,0x00};
976 /* nopw 0(%[re]ax,%[re]ax,1)
977 nopw 0(%[re]ax,%[re]ax,1) */
978 static const char alt_short_12[] =
979 {0x66,0x0f,0x1f,0x44,0x00,0x00,
980 0x66,0x0f,0x1f,0x44,0x00,0x00};
981 /* nopw 0(%[re]ax,%[re]ax,1)
982 nopl 0L(%[re]ax) */
983 static const char alt_short_13[] =
984 {0x66,0x0f,0x1f,0x44,0x00,0x00,
985 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
986 /* nopl 0L(%[re]ax)
987 nopl 0L(%[re]ax) */
988 static const char alt_short_14[] =
989 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
990 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
991 /* nopl 0L(%[re]ax)
992 nopl 0L(%[re]ax,%[re]ax,1) */
993 static const char alt_short_15[] =
994 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
995 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
996 static const char *const alt_short_patt[] = {
997 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
998 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
999 alt_short_14, alt_short_15
1000 };
1001 static const char *const alt_long_patt[] = {
1002 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1003 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1004 alt_long_14, alt_long_15
1005 };
252b5132 1006
76bc74dc
L		 1007 /* Only align for at least a positive non-zero boundary. */
1008 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1009 return;
3e73aa7c 1010
ccc9c027
L		 1011 /* We need to decide which NOP sequence to use for 32bit and
1012 64bit. When -mtune= is used:
4eed87de 1013
76bc74dc
L		 1014 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1015 PROCESSOR_GENERIC32, f32_patt will be used.
1016 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1017 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1018 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1019 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 1020 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 1021 will be used.
ccc9c027 1022
76bc74dc 1023 When -mtune= isn't used, alt_long_patt will be used if
22109423 1024 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1025 be used.
ccc9c027
L		 1026
1027 When -march= or .arch is used, we can't use anything beyond
1028 cpu_arch_isa_flags. */
1029
1030 if (flag_code == CODE_16BIT)
1031 {
ccc9c027 1032 if (count > 8)
33fef721 1033 {
76bc74dc
L		 1034 memcpy (fragP->fr_literal + fragP->fr_fix,
1035 jump_31, count);
1036 /* Adjust jump offset. */
1037 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1038 }
76bc74dc
L		 1039 else
1040 memcpy (fragP->fr_literal + fragP->fr_fix,
1041 f16_patt[count - 1], count);
252b5132 1042 }
33fef721 1043 else
ccc9c027
L		 1044 {
1045 const char *const *patt = NULL;
1046
fbf3f584 1047 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1048 {
1049 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1050 switch (cpu_arch_tune)
1051 {
1052 case PROCESSOR_UNKNOWN:
1053 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1054 optimize with nops. */
1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1056 patt = alt_long_patt;
ccc9c027
L		 1057 else
1058 patt = f32_patt;
1059 break;
ccc9c027
L		 1060 case PROCESSOR_PENTIUMPRO:
1061 case PROCESSOR_PENTIUM4:
1062 case PROCESSOR_NOCONA:
ef05d495 1063 case PROCESSOR_CORE:
76bc74dc 1064 case PROCESSOR_CORE2:
bd5295b2 1065 case PROCESSOR_COREI7:
3632d14b 1066 case PROCESSOR_L1OM:
76bc74dc
L		 1067 case PROCESSOR_GENERIC64:
1068 patt = alt_long_patt;
1069 break;
ccc9c027
L		 1070 case PROCESSOR_K6:
1071 case PROCESSOR_ATHLON:
1072 case PROCESSOR_K8:
4eed87de 1073 case PROCESSOR_AMDFAM10:
68339fdf 1074 case PROCESSOR_BDVER1:
ccc9c027
L		 1075 patt = alt_short_patt;
1076 break;
76bc74dc 1077 case PROCESSOR_I386:
ccc9c027
L		 1078 case PROCESSOR_I486:
1079 case PROCESSOR_PENTIUM:
1080 case PROCESSOR_GENERIC32:
1081 patt = f32_patt;
1082 break;
4eed87de 1083 }
ccc9c027
L		 1084 }
1085 else
1086 {
fbf3f584 1087 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1088 {
1089 case PROCESSOR_UNKNOWN:
e6a14101 1090 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1091 PROCESSOR_UNKNOWN. */
1092 abort ();
1093 break;
1094
76bc74dc 1095 case PROCESSOR_I386:
ccc9c027
L		 1096 case PROCESSOR_I486:
1097 case PROCESSOR_PENTIUM:
ccc9c027
L		 1098 case PROCESSOR_K6:
1099 case PROCESSOR_ATHLON:
1100 case PROCESSOR_K8:
4eed87de 1101 case PROCESSOR_AMDFAM10:
68339fdf 1102 case PROCESSOR_BDVER1:
ccc9c027
L		 1103 case PROCESSOR_GENERIC32:
1104 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1105 with nops. */
1106 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1107 patt = alt_short_patt;
1108 else
1109 patt = f32_patt;
1110 break;
76bc74dc
L		 1111 case PROCESSOR_PENTIUMPRO:
1112 case PROCESSOR_PENTIUM4:
1113 case PROCESSOR_NOCONA:
1114 case PROCESSOR_CORE:
ef05d495 1115 case PROCESSOR_CORE2:
bd5295b2 1116 case PROCESSOR_COREI7:
3632d14b 1117 case PROCESSOR_L1OM:
22109423 1118 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1119 patt = alt_long_patt;
1120 else
1121 patt = f32_patt;
1122 break;
1123 case PROCESSOR_GENERIC64:
76bc74dc 1124 patt = alt_long_patt;
ccc9c027 1125 break;
4eed87de 1126 }
ccc9c027
L		 1127 }
1128
76bc74dc
L		 1129 if (patt == f32_patt)
1130 {
1131 /* If the padding is less than 15 bytes, we use the normal
1132 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1133 its offset. */
1134 int limit;
76ba9986 1135
711eedef
L		 1136 /* For 64bit, the limit is 3 bytes. */
1137 if (flag_code == CODE_64BIT
1138 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1139 limit = 3;
1140 else
1141 limit = 15;
1142 if (count < limit)
76bc74dc
L		 1143 memcpy (fragP->fr_literal + fragP->fr_fix,
1144 patt[count - 1], count);
1145 else
1146 {
1147 memcpy (fragP->fr_literal + fragP->fr_fix,
1148 jump_31, count);
1149 /* Adjust jump offset. */
1150 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1151 }
1152 }
1153 else
1154 {
1155 /* Maximum length of an instruction is 15 byte. If the
1156 padding is greater than 15 bytes and we don't use jump,
1157 we have to break it into smaller pieces. */
1158 int padding = count;
1159 while (padding > 15)
1160 {
1161 padding -= 15;
1162 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1163 patt [14], 15);
1164 }
1165
1166 if (padding)
1167 memcpy (fragP->fr_literal + fragP->fr_fix,
1168 patt [padding - 1], padding);
1169 }
ccc9c027 1170 }
33fef721 1171 fragP->fr_var = count;
252b5132
RH		 1172}
1173
c6fb90c8 1174static INLINE int
0dfbf9d7 1175operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1176{
0dfbf9d7 1177 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1178 {
1179 case 3:
0dfbf9d7 1180 if (x->array[2])
c6fb90c8
L		 1181 return 0;
1182 case 2:
0dfbf9d7 1183 if (x->array[1])
c6fb90c8
L		 1184 return 0;
1185 case 1:
0dfbf9d7 1186 return !x->array[0];
c6fb90c8
L		 1187 default:
1188 abort ();
1189 }
40fb9820
L		 1190}
1191
c6fb90c8 1192static INLINE void
0dfbf9d7 1193operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1194{
0dfbf9d7 1195 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1196 {
1197 case 3:
0dfbf9d7 1198 x->array[2] = v;
c6fb90c8 1199 case 2:
0dfbf9d7 1200 x->array[1] = v;
c6fb90c8 1201 case 1:
0dfbf9d7 1202 x->array[0] = v;
c6fb90c8
L		 1203 break;
1204 default:
1205 abort ();
1206 }
1207}
40fb9820 1208
c6fb90c8 1209static INLINE int
0dfbf9d7
L		 1210operand_type_equal (const union i386_operand_type *x,
1211 const union i386_operand_type *y)
c6fb90c8 1212{
0dfbf9d7 1213 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1214 {
1215 case 3:
0dfbf9d7 1216 if (x->array[2] != y->array[2])
c6fb90c8
L		 1217 return 0;
1218 case 2:
0dfbf9d7 1219 if (x->array[1] != y->array[1])
c6fb90c8
L		 1220 return 0;
1221 case 1:
0dfbf9d7 1222 return x->array[0] == y->array[0];
c6fb90c8
L		 1223 break;
1224 default:
1225 abort ();
1226 }
1227}
40fb9820 1228
0dfbf9d7
L		 1229static INLINE int
1230cpu_flags_all_zero (const union i386_cpu_flags *x)
1231{
1232 switch (ARRAY_SIZE(x->array))
1233 {
1234 case 3:
1235 if (x->array[2])
1236 return 0;
1237 case 2:
1238 if (x->array[1])
1239 return 0;
1240 case 1:
1241 return !x->array[0];
1242 default:
1243 abort ();
1244 }
1245}
1246
1247static INLINE void
1248cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1249{
1250 switch (ARRAY_SIZE(x->array))
1251 {
1252 case 3:
1253 x->array[2] = v;
1254 case 2:
1255 x->array[1] = v;
1256 case 1:
1257 x->array[0] = v;
1258 break;
1259 default:
1260 abort ();
1261 }
1262}
1263
1264static INLINE int
1265cpu_flags_equal (const union i386_cpu_flags *x,
1266 const union i386_cpu_flags *y)
1267{
1268 switch (ARRAY_SIZE(x->array))
1269 {
1270 case 3:
1271 if (x->array[2] != y->array[2])
1272 return 0;
1273 case 2:
1274 if (x->array[1] != y->array[1])
1275 return 0;
1276 case 1:
1277 return x->array[0] == y->array[0];
1278 break;
1279 default:
1280 abort ();
1281 }
1282}
c6fb90c8
L		 1283
1284static INLINE int
1285cpu_flags_check_cpu64 (i386_cpu_flags f)
1286{
1287 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1288 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1289}
1290
c6fb90c8
L		 1291static INLINE i386_cpu_flags
1292cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1293{
c6fb90c8
L		 1294 switch (ARRAY_SIZE (x.array))
1295 {
1296 case 3:
1297 x.array [2] &= y.array [2];
1298 case 2:
1299 x.array [1] &= y.array [1];
1300 case 1:
1301 x.array [0] &= y.array [0];
1302 break;
1303 default:
1304 abort ();
1305 }
1306 return x;
1307}
40fb9820 1308
c6fb90c8
L		 1309static INLINE i386_cpu_flags
1310cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1311{
c6fb90c8 1312 switch (ARRAY_SIZE (x.array))
40fb9820 1313 {
c6fb90c8
L		 1314 case 3:
1315 x.array [2] |= y.array [2];
1316 case 2:
1317 x.array [1] |= y.array [1];
1318 case 1:
1319 x.array [0] |= y.array [0];
40fb9820
L		 1320 break;
1321 default:
1322 abort ();
1323 }
40fb9820
L		 1324 return x;
1325}
1326
309d3373
JB		 1327static INLINE i386_cpu_flags
1328cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1329{
1330 switch (ARRAY_SIZE (x.array))
1331 {
1332 case 3:
1333 x.array [2] &= ~y.array [2];
1334 case 2:
1335 x.array [1] &= ~y.array [1];
1336 case 1:
1337 x.array [0] &= ~y.array [0];
1338 break;
1339 default:
1340 abort ();
1341 }
1342 return x;
1343}
1344
c0f3af97
L		 1345#define CPU_FLAGS_ARCH_MATCH 0x1
1346#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1347#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1348#define CPU_FLAGS_PCLMUL_MATCH 0x8
1349#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1350
a5ff0eb2 1351#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1352 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1353 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1354#define CPU_FLAGS_PERFECT_MATCH \
1355 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1356
1357/* Return CPU flags match bits. */
3629bb00 1358
40fb9820 1359static int
d3ce72d0 1360cpu_flags_match (const insn_template *t)
40fb9820 1361{
c0f3af97
L		 1362 i386_cpu_flags x = t->cpu_flags;
1363 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1364
1365 x.bitfield.cpu64 = 0;
1366 x.bitfield.cpuno64 = 0;
1367
0dfbf9d7 1368 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1369 {
1370 /* This instruction is available on all archs. */
1371 match |= CPU_FLAGS_32BIT_MATCH;
1372 }
3629bb00
L		 1373 else
1374 {
c0f3af97 1375 /* This instruction is available only on some archs. */
3629bb00
L		 1376 i386_cpu_flags cpu = cpu_arch_flags;
1377
1378 cpu.bitfield.cpu64 = 0;
1379 cpu.bitfield.cpuno64 = 0;
1380 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1381 if (!cpu_flags_all_zero (&cpu))
1382 {
a5ff0eb2
L		 1383 if (x.bitfield.cpuavx)
1384 {
ce2f5b3c 1385 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1386 if (cpu.bitfield.cpuavx)
1387 {
1388 /* Check SSE2AVX. */
1389 if (!t->opcode_modifier.sse2avx|| sse2avx)
1390 {
1391 match |= (CPU_FLAGS_ARCH_MATCH
1392 | CPU_FLAGS_AVX_MATCH);
1393 /* Check AES. */
1394 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1395 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1396 /* Check PCLMUL. */
1397 if (!x.bitfield.cpupclmul
1398 || cpu.bitfield.cpupclmul)
1399 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1400 }
1401 }
1402 else
1403 match |= CPU_FLAGS_ARCH_MATCH;
1404 }
1405 else
c0f3af97
L		 1406 match |= CPU_FLAGS_32BIT_MATCH;
1407 }
3629bb00 1408 }
c0f3af97 1409 return match;
40fb9820
L		 1410}
1411
c6fb90c8
L		 1412static INLINE i386_operand_type
1413operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1414{
c6fb90c8
L		 1415 switch (ARRAY_SIZE (x.array))
1416 {
1417 case 3:
1418 x.array [2] &= y.array [2];
1419 case 2:
1420 x.array [1] &= y.array [1];
1421 case 1:
1422 x.array [0] &= y.array [0];
1423 break;
1424 default:
1425 abort ();
1426 }
1427 return x;
40fb9820
L		 1428}
1429
c6fb90c8
L		 1430static INLINE i386_operand_type
1431operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1432{
c6fb90c8 1433 switch (ARRAY_SIZE (x.array))
40fb9820 1434 {
c6fb90c8
L		 1435 case 3:
1436 x.array [2] |= y.array [2];
1437 case 2:
1438 x.array [1] |= y.array [1];
1439 case 1:
1440 x.array [0] |= y.array [0];
40fb9820
L		 1441 break;
1442 default:
1443 abort ();
1444 }
c6fb90c8
L		 1445 return x;
1446}
40fb9820 1447
c6fb90c8
L		 1448static INLINE i386_operand_type
1449operand_type_xor (i386_operand_type x, i386_operand_type y)
1450{
1451 switch (ARRAY_SIZE (x.array))
1452 {
1453 case 3:
1454 x.array [2] ^= y.array [2];
1455 case 2:
1456 x.array [1] ^= y.array [1];
1457 case 1:
1458 x.array [0] ^= y.array [0];
1459 break;
1460 default:
1461 abort ();
1462 }
40fb9820
L		 1463 return x;
1464}
1465
1466static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1467static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1468static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1469static const i386_operand_type inoutportreg
1470 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1471static const i386_operand_type reg16_inoutportreg
1472 = OPERAND_TYPE_REG16_INOUTPORTREG;
1473static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1474static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1475static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1476static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1477static const i386_operand_type anydisp
1478 = OPERAND_TYPE_ANYDISP;
40fb9820 1479static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1480static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1481static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1482static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1483static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1484static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1485static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1486static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1487static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1488static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1489static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1490static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1491
1492enum operand_type
1493{
1494 reg,
40fb9820
L		 1495 imm,
1496 disp,
1497 anymem
1498};
1499
c6fb90c8 1500static INLINE int
40fb9820
L		 1501operand_type_check (i386_operand_type t, enum operand_type c)
1502{
1503 switch (c)
1504 {
1505 case reg:
1506 return (t.bitfield.reg8
1507 || t.bitfield.reg16
1508 || t.bitfield.reg32
1509 || t.bitfield.reg64);
1510
40fb9820
L		 1511 case imm:
1512 return (t.bitfield.imm8
1513 || t.bitfield.imm8s
1514 || t.bitfield.imm16
1515 || t.bitfield.imm32
1516 || t.bitfield.imm32s
1517 || t.bitfield.imm64);
1518
1519 case disp:
1520 return (t.bitfield.disp8
1521 || t.bitfield.disp16
1522 || t.bitfield.disp32
1523 || t.bitfield.disp32s
1524 || t.bitfield.disp64);
1525
1526 case anymem:
1527 return (t.bitfield.disp8
1528 || t.bitfield.disp16
1529 || t.bitfield.disp32
1530 || t.bitfield.disp32s
1531 || t.bitfield.disp64
1532 || t.bitfield.baseindex);
1533
1534 default:
1535 abort ();
1536 }
2cfe26b6
AM		 1537
1538 return 0;
40fb9820
L		 1539}
1540
5c07affc
L		 1541/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1542 operand J for instruction template T. */
1543
1544static INLINE int
d3ce72d0 1545match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1546{
1547 return !((i.types[j].bitfield.byte
1548 && !t->operand_types[j].bitfield.byte)
1549 || (i.types[j].bitfield.word
1550 && !t->operand_types[j].bitfield.word)
1551 || (i.types[j].bitfield.dword
1552 && !t->operand_types[j].bitfield.dword)
1553 || (i.types[j].bitfield.qword
1554 && !t->operand_types[j].bitfield.qword));
1555}
1556
1557/* Return 1 if there is no conflict in any size on operand J for
1558 instruction template T. */
1559
1560static INLINE int
d3ce72d0 1561match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1562{
1563 return (match_reg_size (t, j)
1564 && !((i.types[j].bitfield.unspecified
1565 && !t->operand_types[j].bitfield.unspecified)
1566 || (i.types[j].bitfield.fword
1567 && !t->operand_types[j].bitfield.fword)
1568 || (i.types[j].bitfield.tbyte
1569 && !t->operand_types[j].bitfield.tbyte)
1570 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1571 && !t->operand_types[j].bitfield.xmmword)
1572 || (i.types[j].bitfield.ymmword
1573 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1574}
1575
1576/* Return 1 if there is no size conflict on any operands for
1577 instruction template T. */
1578
1579static INLINE int
d3ce72d0 1580operand_size_match (const insn_template *t)
5c07affc
L		 1581{
1582 unsigned int j;
1583 int match = 1;
1584
1585 /* Don't check jump instructions. */
1586 if (t->opcode_modifier.jump
1587 || t->opcode_modifier.jumpbyte
1588 || t->opcode_modifier.jumpdword
1589 || t->opcode_modifier.jumpintersegment)
1590 return match;
1591
1592 /* Check memory and accumulator operand size. */
1593 for (j = 0; j < i.operands; j++)
1594 {
1595 if (t->operand_types[j].bitfield.anysize)
1596 continue;
1597
1598 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1599 {
1600 match = 0;
1601 break;
1602 }
1603
1604 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1605 {
1606 match = 0;
1607 break;
1608 }
1609 }
1610
891edac4 1611 if (match)
5c07affc 1612 return match;
891edac4
L		 1613 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1614 {
1615mismatch:
86e026a4 1616 i.error = operand_size_mismatch;
891edac4
L		 1617 return 0;
1618 }
5c07affc
L		 1619
1620 /* Check reverse. */
9c2799c2 1621 gas_assert (i.operands == 2);
5c07affc
L		 1622
1623 match = 1;
1624 for (j = 0; j < 2; j++)
1625 {
1626 if (t->operand_types[j].bitfield.acc
1627 && !match_reg_size (t, j ? 0 : 1))
891edac4 1628 goto mismatch;
5c07affc
L		 1629
1630 if (i.types[j].bitfield.mem
1631 && !match_mem_size (t, j ? 0 : 1))
891edac4 1632 goto mismatch;
5c07affc
L		 1633 }
1634
1635 return match;
1636}
1637
c6fb90c8 1638static INLINE int
40fb9820
L		 1639operand_type_match (i386_operand_type overlap,
1640 i386_operand_type given)
1641{
1642 i386_operand_type temp = overlap;
1643
1644 temp.bitfield.jumpabsolute = 0;
7d5e4556 1645 temp.bitfield.unspecified = 0;
5c07affc
L		 1646 temp.bitfield.byte = 0;
1647 temp.bitfield.word = 0;
1648 temp.bitfield.dword = 0;
1649 temp.bitfield.fword = 0;
1650 temp.bitfield.qword = 0;
1651 temp.bitfield.tbyte = 0;
1652 temp.bitfield.xmmword = 0;
c0f3af97 1653 temp.bitfield.ymmword = 0;
0dfbf9d7 1654 if (operand_type_all_zero (&temp))
891edac4 1655 goto mismatch;
40fb9820 1656
891edac4
L		 1657 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1658 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1659 return 1;
1660
1661mismatch:
a65babc9 1662 i.error = operand_type_mismatch;
891edac4 1663 return 0;
40fb9820
L		 1664}
1665
7d5e4556 1666/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1667 unless the expected operand type register overlap is null.
1668 Note that Acc in a template matches every size of reg. */
1669
c6fb90c8 1670static INLINE int
40fb9820
L		 1671operand_type_register_match (i386_operand_type m0,
1672 i386_operand_type g0,
1673 i386_operand_type t0,
1674 i386_operand_type m1,
1675 i386_operand_type g1,
1676 i386_operand_type t1)
1677{
1678 if (!operand_type_check (g0, reg))
1679 return 1;
1680
1681 if (!operand_type_check (g1, reg))
1682 return 1;
1683
1684 if (g0.bitfield.reg8 == g1.bitfield.reg8
1685 && g0.bitfield.reg16 == g1.bitfield.reg16
1686 && g0.bitfield.reg32 == g1.bitfield.reg32
1687 && g0.bitfield.reg64 == g1.bitfield.reg64)
1688 return 1;
1689
1690 if (m0.bitfield.acc)
1691 {
1692 t0.bitfield.reg8 = 1;
1693 t0.bitfield.reg16 = 1;
1694 t0.bitfield.reg32 = 1;
1695 t0.bitfield.reg64 = 1;
1696 }
1697
1698 if (m1.bitfield.acc)
1699 {
1700 t1.bitfield.reg8 = 1;
1701 t1.bitfield.reg16 = 1;
1702 t1.bitfield.reg32 = 1;
1703 t1.bitfield.reg64 = 1;
1704 }
1705
891edac4
L		 1706 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1707 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1708 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1709 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1710 return 1;
1711
a65babc9 1712 i.error = register_type_mismatch;
891edac4
L		 1713
1714 return 0;
40fb9820
L		 1715}
1716
252b5132 1717static INLINE unsigned int
40fb9820 1718mode_from_disp_size (i386_operand_type t)
252b5132 1719{
40fb9820
L		 1720 if (t.bitfield.disp8)
1721 return 1;
1722 else if (t.bitfield.disp16
1723 || t.bitfield.disp32
1724 || t.bitfield.disp32s)
1725 return 2;
1726 else
1727 return 0;
252b5132
RH		 1728}
1729
1730static INLINE int
e3bb37b5 1731fits_in_signed_byte (offsetT num)
252b5132
RH		 1732{
1733 return (num >= -128) && (num <= 127);
47926f60 1734}
252b5132
RH		 1735
1736static INLINE int
e3bb37b5 1737fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1738{
1739 return (num & 0xff) == num;
47926f60 1740}
252b5132
RH		 1741
1742static INLINE int
e3bb37b5 1743fits_in_unsigned_word (offsetT num)
252b5132
RH		 1744{
1745 return (num & 0xffff) == num;
47926f60 1746}
252b5132
RH		 1747
1748static INLINE int
e3bb37b5 1749fits_in_signed_word (offsetT num)
252b5132
RH		 1750{
1751 return (-32768 <= num) && (num <= 32767);
47926f60 1752}
2a962e6d 1753
3e73aa7c 1754static INLINE int
e3bb37b5 1755fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1756{
1757#ifndef BFD64
1758 return 1;
1759#else
1760 return (!(((offsetT) -1 << 31) & num)
1761 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1762#endif
1763} /* fits_in_signed_long() */
2a962e6d 1764
3e73aa7c 1765static INLINE int
e3bb37b5 1766fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1767{
1768#ifndef BFD64
1769 return 1;
1770#else
1771 return (num & (((offsetT) 2 << 31) - 1)) == num;
1772#endif
1773} /* fits_in_unsigned_long() */
252b5132 1774
a683cc34
SP		 1775static INLINE int
1776fits_in_imm4 (offsetT num)
1777{
1778 return (num & 0xf) == num;
1779}
1780
40fb9820 1781static i386_operand_type
e3bb37b5 1782smallest_imm_type (offsetT num)
252b5132 1783{
40fb9820 1784 i386_operand_type t;
7ab9ffdd 1785
0dfbf9d7 1786 operand_type_set (&t, 0);
40fb9820
L		 1787 t.bitfield.imm64 = 1;
1788
1789 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1790 {
1791 /* This code is disabled on the 486 because all the Imm1 forms
1792 in the opcode table are slower on the i486. They're the
1793 versions with the implicitly specified single-position
1794 displacement, which has another syntax if you really want to
1795 use that form. */
40fb9820
L		 1796 t.bitfield.imm1 = 1;
1797 t.bitfield.imm8 = 1;
1798 t.bitfield.imm8s = 1;
1799 t.bitfield.imm16 = 1;
1800 t.bitfield.imm32 = 1;
1801 t.bitfield.imm32s = 1;
1802 }
1803 else if (fits_in_signed_byte (num))
1804 {
1805 t.bitfield.imm8 = 1;
1806 t.bitfield.imm8s = 1;
1807 t.bitfield.imm16 = 1;
1808 t.bitfield.imm32 = 1;
1809 t.bitfield.imm32s = 1;
1810 }
1811 else if (fits_in_unsigned_byte (num))
1812 {
1813 t.bitfield.imm8 = 1;
1814 t.bitfield.imm16 = 1;
1815 t.bitfield.imm32 = 1;
1816 t.bitfield.imm32s = 1;
1817 }
1818 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1819 {
1820 t.bitfield.imm16 = 1;
1821 t.bitfield.imm32 = 1;
1822 t.bitfield.imm32s = 1;
1823 }
1824 else if (fits_in_signed_long (num))
1825 {
1826 t.bitfield.imm32 = 1;
1827 t.bitfield.imm32s = 1;
1828 }
1829 else if (fits_in_unsigned_long (num))
1830 t.bitfield.imm32 = 1;
1831
1832 return t;
47926f60 1833}
252b5132 1834
847f7ad4 1835static offsetT
e3bb37b5 1836offset_in_range (offsetT val, int size)
847f7ad4 1837{
508866be 1838 addressT mask;
ba2adb93 1839
847f7ad4
AM		 1840 switch (size)
1841 {
508866be
L		 1842 case 1: mask = ((addressT) 1 << 8) - 1; break;
1843 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1844 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1845#ifdef BFD64
1846 case 8: mask = ((addressT) 2 << 63) - 1; break;
1847#endif
47926f60 1848 default: abort ();
847f7ad4
AM		 1849 }
1850
9de868bf
L		 1851#ifdef BFD64
1852 /* If BFD64, sign extend val for 32bit address mode. */
1853 if (flag_code != CODE_64BIT
1854 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1855 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1856 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1857#endif
ba2adb93 1858
47926f60 1859 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1860 {
1861 char buf1[40], buf2[40];
1862
1863 sprint_value (buf1, val);
1864 sprint_value (buf2, val & mask);
1865 as_warn (_("%s shortened to %s"), buf1, buf2);
1866 }
1867 return val & mask;
1868}
1869
c32fa91d
L		 1870enum PREFIX_GROUP
1871{
1872 PREFIX_EXIST = 0,
1873 PREFIX_LOCK,
1874 PREFIX_REP,
1875 PREFIX_OTHER
1876};
1877
1878/* Returns
1879 a. PREFIX_EXIST if attempting to add a prefix where one from the
1880 same class already exists.
1881 b. PREFIX_LOCK if lock prefix is added.
1882 c. PREFIX_REP if rep/repne prefix is added.
1883 d. PREFIX_OTHER if other prefix is added.
1884 */
1885
1886static enum PREFIX_GROUP
e3bb37b5 1887add_prefix (unsigned int prefix)
252b5132 1888{
c32fa91d 1889 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1890 unsigned int q;
252b5132 1891
29b0f896
AM		 1892 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1893 && flag_code == CODE_64BIT)
b1905489 1894 {
161a04f6
L		 1895 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1896 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1897 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1898 ret = PREFIX_EXIST;
b1905489
JB		 1899 q = REX_PREFIX;
1900 }
3e73aa7c 1901 else
b1905489
JB		 1902 {
1903 switch (prefix)
1904 {
1905 default:
1906 abort ();
1907
1908 case CS_PREFIX_OPCODE:
1909 case DS_PREFIX_OPCODE:
1910 case ES_PREFIX_OPCODE:
1911 case FS_PREFIX_OPCODE:
1912 case GS_PREFIX_OPCODE:
1913 case SS_PREFIX_OPCODE:
1914 q = SEG_PREFIX;
1915 break;
1916
1917 case REPNE_PREFIX_OPCODE:
1918 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1919 q = REP_PREFIX;
1920 ret = PREFIX_REP;
1921 break;
1922
b1905489 1923 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1924 q = LOCK_PREFIX;
1925 ret = PREFIX_LOCK;
b1905489
JB		 1926 break;
1927
1928 case FWAIT_OPCODE:
1929 q = WAIT_PREFIX;
1930 break;
1931
1932 case ADDR_PREFIX_OPCODE:
1933 q = ADDR_PREFIX;
1934 break;
1935
1936 case DATA_PREFIX_OPCODE:
1937 q = DATA_PREFIX;
1938 break;
1939 }
1940 if (i.prefix[q] != 0)
c32fa91d 1941 ret = PREFIX_EXIST;
b1905489 1942 }
252b5132 1943
b1905489 1944 if (ret)
252b5132 1945 {
b1905489
JB		 1946 if (!i.prefix[q])
1947 ++i.prefixes;
1948 i.prefix[q] |= prefix;
252b5132 1949 }
b1905489
JB		 1950 else
1951 as_bad (_("same type of prefix used twice"));
252b5132 1952
252b5132
RH		 1953 return ret;
1954}
1955
1956static void
78f12dd3 1957update_code_flag (int value, int check)
eecb386c 1958{
78f12dd3
L		 1959 PRINTF_LIKE ((*as_error));
1960
1e9cc1c2 1961 flag_code = (enum flag_code) value;
40fb9820
L		 1962 if (flag_code == CODE_64BIT)
1963 {
1964 cpu_arch_flags.bitfield.cpu64 = 1;
1965 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1966 }
1967 else
1968 {
1969 cpu_arch_flags.bitfield.cpu64 = 0;
1970 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1971 }
1972 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1973 {
78f12dd3
L		 1974 if (check)
1975 as_error = as_fatal;
1976 else
1977 as_error = as_bad;
1978 (*as_error) (_("64bit mode not supported on `%s'."),
1979 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1980 }
40fb9820 1981 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1982 {
78f12dd3
L		 1983 if (check)
1984 as_error = as_fatal;
1985 else
1986 as_error = as_bad;
1987 (*as_error) (_("32bit mode not supported on `%s'."),
1988 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1989 }
eecb386c
AM		 1990 stackop_size = '\0';
1991}
1992
78f12dd3
L		 1993static void
1994set_code_flag (int value)
1995{
1996 update_code_flag (value, 0);
1997}
1998
eecb386c 1999static void
e3bb37b5 2000set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2001{
1e9cc1c2 2002 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2003 if (flag_code != CODE_16BIT)
2004 abort ();
2005 cpu_arch_flags.bitfield.cpu64 = 0;
2006 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2007 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2008}
2009
2010static void
e3bb37b5 2011set_intel_syntax (int syntax_flag)
252b5132
RH		 2012{
2013 /* Find out if register prefixing is specified. */
2014 int ask_naked_reg = 0;
2015
2016 SKIP_WHITESPACE ();
29b0f896 2017 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2018 {
2019 char *string = input_line_pointer;
2020 int e = get_symbol_end ();
2021
47926f60 2022 if (strcmp (string, "prefix") == 0)
252b5132 2023 ask_naked_reg = 1;
47926f60 2024 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2025 ask_naked_reg = -1;
2026 else
d0b47220 2027 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2028 *input_line_pointer = e;
2029 }
2030 demand_empty_rest_of_line ();
c3332e24 2031
252b5132
RH		 2032 intel_syntax = syntax_flag;
2033
2034 if (ask_naked_reg == 0)
f86103b7
AM		 2035 allow_naked_reg = (intel_syntax
2036 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2037 else
2038 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2039
ee86248c 2040 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2041
e4a3b5a4 2042 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2043 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2044 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2045}
2046
1efbbeb4
L		 2047static void
2048set_intel_mnemonic (int mnemonic_flag)
2049{
e1d4d893 2050 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2051}
2052
db51cc60
L		 2053static void
2054set_allow_index_reg (int flag)
2055{
2056 allow_index_reg = flag;
2057}
2058
cb19c032
L		 2059static void
2060set_sse_check (int dummy ATTRIBUTE_UNUSED)
2061{
2062 SKIP_WHITESPACE ();
2063
2064 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2065 {
2066 char *string = input_line_pointer;
2067 int e = get_symbol_end ();
2068
2069 if (strcmp (string, "none") == 0)
2070 sse_check = sse_check_none;
2071 else if (strcmp (string, "warning") == 0)
2072 sse_check = sse_check_warning;
2073 else if (strcmp (string, "error") == 0)
2074 sse_check = sse_check_error;
2075 else
2076 as_bad (_("bad argument to sse_check directive."));
2077 *input_line_pointer = e;
2078 }
2079 else
2080 as_bad (_("missing argument for sse_check directive"));
2081
2082 demand_empty_rest_of_line ();
2083}
2084
8a9036a4
L		 2085static void
2086check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2087 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2088{
2089#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2090 static const char *arch;
2091
2092 /* Intel LIOM is only supported on ELF. */
2093 if (!IS_ELF)
2094 return;
2095
2096 if (!arch)
2097 {
2098 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2099 use default_arch. */
2100 arch = cpu_arch_name;
2101 if (!arch)
2102 arch = default_arch;
2103 }
2104
3632d14b 2105 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2106 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2107 || new_flag.bitfield.cpul1om)
8a9036a4 2108 return;
76ba9986 2109
8a9036a4
L		 2110 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2111#endif
2112}
2113
e413e4e9 2114static void
e3bb37b5 2115set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2116{
47926f60 2117 SKIP_WHITESPACE ();
e413e4e9 2118
29b0f896 2119 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2120 {
2121 char *string = input_line_pointer;
2122 int e = get_symbol_end ();
91d6fa6a 2123 unsigned int j;
40fb9820 2124 i386_cpu_flags flags;
e413e4e9 2125
91d6fa6a 2126 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2127 {
91d6fa6a 2128 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2129 {
91d6fa6a 2130 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2131
5c6af06e
JB		 2132 if (*string != '.')
2133 {
91d6fa6a 2134 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2135 cpu_sub_arch_name = NULL;
91d6fa6a 2136 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2137 if (flag_code == CODE_64BIT)
2138 {
2139 cpu_arch_flags.bitfield.cpu64 = 1;
2140 cpu_arch_flags.bitfield.cpuno64 = 0;
2141 }
2142 else
2143 {
2144 cpu_arch_flags.bitfield.cpu64 = 0;
2145 cpu_arch_flags.bitfield.cpuno64 = 1;
2146 }
91d6fa6a
NC		 2147 cpu_arch_isa = cpu_arch[j].type;
2148 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2149 if (!cpu_arch_tune_set)
2150 {
2151 cpu_arch_tune = cpu_arch_isa;
2152 cpu_arch_tune_flags = cpu_arch_isa_flags;
2153 }
5c6af06e
JB		 2154 break;
2155 }
40fb9820 2156
22109423 2157 if (!cpu_arch[j].negated)
309d3373 2158 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2159 cpu_arch[j].flags);
309d3373
JB		 2160 else
2161 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2162 cpu_arch[j].flags);
0dfbf9d7 2163 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2164 {
6305a203
L		 2165 if (cpu_sub_arch_name)
2166 {
2167 char *name = cpu_sub_arch_name;
2168 cpu_sub_arch_name = concat (name,
91d6fa6a 2169 cpu_arch[j].name,
1bf57e9f 2170 (const char *) NULL);
6305a203
L		 2171 free (name);
2172 }
2173 else
91d6fa6a 2174 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2175 cpu_arch_flags = flags;
5c6af06e
JB		 2176 }
2177 *input_line_pointer = e;
2178 demand_empty_rest_of_line ();
2179 return;
e413e4e9
AM		 2180 }
2181 }
91d6fa6a 2182 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2183 as_bad (_("no such architecture: `%s'"), string);
2184
2185 *input_line_pointer = e;
2186 }
2187 else
2188 as_bad (_("missing cpu architecture"));
2189
fddf5b5b
AM		 2190 no_cond_jump_promotion = 0;
2191 if (*input_line_pointer == ','
29b0f896 2192 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2193 {
2194 char *string = ++input_line_pointer;
2195 int e = get_symbol_end ();
2196
2197 if (strcmp (string, "nojumps") == 0)
2198 no_cond_jump_promotion = 1;
2199 else if (strcmp (string, "jumps") == 0)
2200 ;
2201 else
2202 as_bad (_("no such architecture modifier: `%s'"), string);
2203
2204 *input_line_pointer = e;
2205 }
2206
e413e4e9
AM		 2207 demand_empty_rest_of_line ();
2208}
2209
8a9036a4
L		 2210enum bfd_architecture
2211i386_arch (void)
2212{
3632d14b 2213 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2214 {
2215 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2216 || flag_code != CODE_64BIT)
2217 as_fatal (_("Intel L1OM is 64bit ELF only"));
2218 return bfd_arch_l1om;
2219 }
2220 else
2221 return bfd_arch_i386;
2222}
2223
b9d79e03
JH		 2224unsigned long
2225i386_mach ()
2226{
351f65ca 2227 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2228 {
3632d14b 2229 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2230 {
351f65ca
L		 2231 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2232 || default_arch[6] != '\0')
8a9036a4
L		 2233 as_fatal (_("Intel L1OM is 64bit ELF only"));
2234 return bfd_mach_l1om;
2235 }
351f65ca 2236 else if (default_arch[6] == '\0')
8a9036a4 2237 return bfd_mach_x86_64;
351f65ca
L		 2238 else
2239 return bfd_mach_x64_32;
8a9036a4 2240 }
b9d79e03
JH		 2241 else if (!strcmp (default_arch, "i386"))
2242 return bfd_mach_i386_i386;
2243 else
2244 as_fatal (_("Unknown architecture"));
2245}
b9d79e03 2246\f
252b5132
RH		 2247void
2248md_begin ()
2249{
2250 const char *hash_err;
2251
47926f60 2252 /* Initialize op_hash hash table. */
252b5132
RH		 2253 op_hash = hash_new ();
2254
2255 {
d3ce72d0 2256 const insn_template *optab;
29b0f896 2257 templates *core_optab;
252b5132 2258
47926f60
KH		 2259 /* Setup for loop. */
2260 optab = i386_optab;
252b5132
RH		 2261 core_optab = (templates *) xmalloc (sizeof (templates));
2262 core_optab->start = optab;
2263
2264 while (1)
2265 {
2266 ++optab;
2267 if (optab->name == NULL
2268 || strcmp (optab->name, (optab - 1)->name) != 0)
2269 {
2270 /* different name --> ship out current template list;
47926f60 2271 add to hash table; & begin anew. */
252b5132
RH		 2272 core_optab->end = optab;
2273 hash_err = hash_insert (op_hash,
2274 (optab - 1)->name,
5a49b8ac 2275 (void *) core_optab);
252b5132
RH		 2276 if (hash_err)
2277 {
252b5132
RH		 2278 as_fatal (_("Internal Error: Can't hash %s: %s"),
2279 (optab - 1)->name,
2280 hash_err);
2281 }
2282 if (optab->name == NULL)
2283 break;
2284 core_optab = (templates *) xmalloc (sizeof (templates));
2285 core_optab->start = optab;
2286 }
2287 }
2288 }
2289
47926f60 2290 /* Initialize reg_hash hash table. */
252b5132
RH		 2291 reg_hash = hash_new ();
2292 {
29b0f896 2293 const reg_entry *regtab;
c3fe08fa 2294 unsigned int regtab_size = i386_regtab_size;
252b5132 2295
c3fe08fa 2296 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2297 {
5a49b8ac 2298 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2299 if (hash_err)
3e73aa7c
JH		 2300 as_fatal (_("Internal Error: Can't hash %s: %s"),
2301 regtab->reg_name,
2302 hash_err);
252b5132
RH		 2303 }
2304 }
2305
47926f60 2306 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2307 {
29b0f896
AM		 2308 int c;
2309 char *p;
252b5132
RH		 2310
2311 for (c = 0; c < 256; c++)
2312 {
3882b010 2313 if (ISDIGIT (c))
252b5132
RH		 2314 {
2315 digit_chars[c] = c;
2316 mnemonic_chars[c] = c;
2317 register_chars[c] = c;
2318 operand_chars[c] = c;
2319 }
3882b010 2320 else if (ISLOWER (c))
252b5132
RH		 2321 {
2322 mnemonic_chars[c] = c;
2323 register_chars[c] = c;
2324 operand_chars[c] = c;
2325 }
3882b010 2326 else if (ISUPPER (c))
252b5132 2327 {
3882b010 2328 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2329 register_chars[c] = mnemonic_chars[c];
2330 operand_chars[c] = c;
2331 }
2332
3882b010 2333 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2334 identifier_chars[c] = c;
2335 else if (c >= 128)
2336 {
2337 identifier_chars[c] = c;
2338 operand_chars[c] = c;
2339 }
2340 }
2341
2342#ifdef LEX_AT
2343 identifier_chars['@'] = '@';
32137342
NC		 2344#endif
2345#ifdef LEX_QM
2346 identifier_chars['?'] = '?';
2347 operand_chars['?'] = '?';
252b5132 2348#endif
252b5132 2349 digit_chars['-'] = '-';
c0f3af97 2350 mnemonic_chars['_'] = '_';
791fe849 2351 mnemonic_chars['-'] = '-';
0003779b 2352 mnemonic_chars['.'] = '.';
252b5132
RH		 2353 identifier_chars['_'] = '_';
2354 identifier_chars['.'] = '.';
2355
2356 for (p = operand_special_chars; *p != '\0'; p++)
2357 operand_chars[(unsigned char) *p] = *p;
2358 }
2359
2360#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2361 if (IS_ELF)
252b5132
RH		 2362 {
2363 record_alignment (text_section, 2);
2364 record_alignment (data_section, 2);
2365 record_alignment (bss_section, 2);
2366 }
2367#endif
a4447b93
RH		 2368
2369 if (flag_code == CODE_64BIT)
2370 {
2371 x86_dwarf2_return_column = 16;
2372 x86_cie_data_alignment = -8;
2373 }
2374 else
2375 {
2376 x86_dwarf2_return_column = 8;
2377 x86_cie_data_alignment = -4;
2378 }
252b5132
RH		 2379}
2380
2381void
e3bb37b5 2382i386_print_statistics (FILE *file)
252b5132
RH		 2383{
2384 hash_print_statistics (file, "i386 opcode", op_hash);
2385 hash_print_statistics (file, "i386 register", reg_hash);
2386}
2387\f
252b5132
RH		 2388#ifdef DEBUG386
2389
ce8a8b2f 2390/* Debugging routines for md_assemble. */
d3ce72d0 2391static void pte (insn_template *);
40fb9820 2392static void pt (i386_operand_type);
e3bb37b5
L		 2393static void pe (expressionS *);
2394static void ps (symbolS *);
252b5132
RH		 2395
2396static void
e3bb37b5 2397pi (char *line, i386_insn *x)
252b5132 2398{
09137c09 2399 unsigned int j;
252b5132
RH		 2400
2401 fprintf (stdout, "%s: template ", line);
2402 pte (&x->tm);
09f131f2
JH		 2403 fprintf (stdout, " address: base %s index %s scale %x\n",
2404 x->base_reg ? x->base_reg->reg_name : "none",
2405 x->index_reg ? x->index_reg->reg_name : "none",
2406 x->log2_scale_factor);
2407 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2408 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2409 fprintf (stdout, " sib: base %x index %x scale %x\n",
2410 x->sib.base, x->sib.index, x->sib.scale);
2411 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2412 (x->rex & REX_W) != 0,
2413 (x->rex & REX_R) != 0,
2414 (x->rex & REX_X) != 0,
2415 (x->rex & REX_B) != 0);
09137c09 2416 for (j = 0; j < x->operands; j++)
252b5132 2417 {
09137c09
SP		 2418 fprintf (stdout, " #%d: ", j + 1);
2419 pt (x->types[j]);
252b5132 2420 fprintf (stdout, "\n");
09137c09
SP		 2421 if (x->types[j].bitfield.reg8
2422 || x->types[j].bitfield.reg16
2423 || x->types[j].bitfield.reg32
2424 || x->types[j].bitfield.reg64
2425 || x->types[j].bitfield.regmmx
2426 || x->types[j].bitfield.regxmm
2427 || x->types[j].bitfield.regymm
2428 || x->types[j].bitfield.sreg2
2429 || x->types[j].bitfield.sreg3
2430 || x->types[j].bitfield.control
2431 || x->types[j].bitfield.debug
2432 || x->types[j].bitfield.test)
2433 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2434 if (operand_type_check (x->types[j], imm))
2435 pe (x->op[j].imms);
2436 if (operand_type_check (x->types[j], disp))
2437 pe (x->op[j].disps);
252b5132
RH		 2438 }
2439}
2440
2441static void
d3ce72d0 2442pte (insn_template *t)
252b5132 2443{
09137c09 2444 unsigned int j;
252b5132 2445 fprintf (stdout, " %d operands ", t->operands);
47926f60 2446 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2447 if (t->extension_opcode != None)
2448 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2449 if (t->opcode_modifier.d)
252b5132 2450 fprintf (stdout, "D");
40fb9820 2451 if (t->opcode_modifier.w)
252b5132
RH		 2452 fprintf (stdout, "W");
2453 fprintf (stdout, "\n");
09137c09 2454 for (j = 0; j < t->operands; j++)
252b5132 2455 {
09137c09
SP		 2456 fprintf (stdout, " #%d type ", j + 1);
2457 pt (t->operand_types[j]);
252b5132
RH		 2458 fprintf (stdout, "\n");
2459 }
2460}
2461
2462static void
e3bb37b5 2463pe (expressionS *e)
252b5132 2464{
24eab124 2465 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2466 fprintf (stdout, " add_number %ld (%lx)\n",
2467 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2468 if (e->X_add_symbol)
2469 {
2470 fprintf (stdout, " add_symbol ");
2471 ps (e->X_add_symbol);
2472 fprintf (stdout, "\n");
2473 }
2474 if (e->X_op_symbol)
2475 {
2476 fprintf (stdout, " op_symbol ");
2477 ps (e->X_op_symbol);
2478 fprintf (stdout, "\n");
2479 }
2480}
2481
2482static void
e3bb37b5 2483ps (symbolS *s)
252b5132
RH		 2484{
2485 fprintf (stdout, "%s type %s%s",
2486 S_GET_NAME (s),
2487 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2488 segment_name (S_GET_SEGMENT (s)));
2489}
2490
7b81dfbb 2491static struct type_name
252b5132 2492 {
40fb9820
L		 2493 i386_operand_type mask;
2494 const char *name;
252b5132 2495 }
7b81dfbb 2496const type_names[] =
252b5132 2497{
40fb9820
L		 2498 { OPERAND_TYPE_REG8, "r8" },
2499 { OPERAND_TYPE_REG16, "r16" },
2500 { OPERAND_TYPE_REG32, "r32" },
2501 { OPERAND_TYPE_REG64, "r64" },
2502 { OPERAND_TYPE_IMM8, "i8" },
2503 { OPERAND_TYPE_IMM8, "i8s" },
2504 { OPERAND_TYPE_IMM16, "i16" },
2505 { OPERAND_TYPE_IMM32, "i32" },
2506 { OPERAND_TYPE_IMM32S, "i32s" },
2507 { OPERAND_TYPE_IMM64, "i64" },
2508 { OPERAND_TYPE_IMM1, "i1" },
2509 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2510 { OPERAND_TYPE_DISP8, "d8" },
2511 { OPERAND_TYPE_DISP16, "d16" },
2512 { OPERAND_TYPE_DISP32, "d32" },
2513 { OPERAND_TYPE_DISP32S, "d32s" },
2514 { OPERAND_TYPE_DISP64, "d64" },
2515 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2516 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2517 { OPERAND_TYPE_CONTROL, "control reg" },
2518 { OPERAND_TYPE_TEST, "test reg" },
2519 { OPERAND_TYPE_DEBUG, "debug reg" },
2520 { OPERAND_TYPE_FLOATREG, "FReg" },
2521 { OPERAND_TYPE_FLOATACC, "FAcc" },
2522 { OPERAND_TYPE_SREG2, "SReg2" },
2523 { OPERAND_TYPE_SREG3, "SReg3" },
2524 { OPERAND_TYPE_ACC, "Acc" },
2525 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2526 { OPERAND_TYPE_REGMMX, "rMMX" },
2527 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2528 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2529 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2530};
2531
2532static void
40fb9820 2533pt (i386_operand_type t)
252b5132 2534{
40fb9820 2535 unsigned int j;
c6fb90c8 2536 i386_operand_type a;
252b5132 2537
40fb9820 2538 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2539 {
2540 a = operand_type_and (t, type_names[j].mask);
0349dc08 2541 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2542 fprintf (stdout, "%s, ", type_names[j].name);
2543 }
252b5132
RH		 2544 fflush (stdout);
2545}
2546
2547#endif /* DEBUG386 */
2548\f
252b5132 2549static bfd_reloc_code_real_type
3956db08 2550reloc (unsigned int size,
64e74474
AM		 2551 int pcrel,
2552 int sign,
2553 bfd_reloc_code_real_type other)
252b5132 2554{
47926f60 2555 if (other != NO_RELOC)
3956db08 2556 {
91d6fa6a 2557 reloc_howto_type *rel;
3956db08
JB		 2558
2559 if (size == 8)
2560 switch (other)
2561 {
64e74474
AM		 2562 case BFD_RELOC_X86_64_GOT32:
2563 return BFD_RELOC_X86_64_GOT64;
2564 break;
2565 case BFD_RELOC_X86_64_PLTOFF64:
2566 return BFD_RELOC_X86_64_PLTOFF64;
2567 break;
2568 case BFD_RELOC_X86_64_GOTPC32:
2569 other = BFD_RELOC_X86_64_GOTPC64;
2570 break;
2571 case BFD_RELOC_X86_64_GOTPCREL:
2572 other = BFD_RELOC_X86_64_GOTPCREL64;
2573 break;
2574 case BFD_RELOC_X86_64_TPOFF32:
2575 other = BFD_RELOC_X86_64_TPOFF64;
2576 break;
2577 case BFD_RELOC_X86_64_DTPOFF32:
2578 other = BFD_RELOC_X86_64_DTPOFF64;
2579 break;
2580 default:
2581 break;
3956db08 2582 }
e05278af
JB		 2583
2584 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2585 if (size == 4 && flag_code != CODE_64BIT)
2586 sign = -1;
2587
91d6fa6a
NC		 2588 rel = bfd_reloc_type_lookup (stdoutput, other);
2589 if (!rel)
3956db08 2590 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2591 else if (size != bfd_get_reloc_size (rel))
3956db08 2592 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2593 bfd_get_reloc_size (rel),
3956db08 2594 size);
91d6fa6a 2595 else if (pcrel && !rel->pc_relative)
3956db08 2596 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2597 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2598 && !sign)
91d6fa6a 2599 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2600 && sign > 0))
3956db08
JB		 2601 as_bad (_("relocated field and relocation type differ in signedness"));
2602 else
2603 return other;
2604 return NO_RELOC;
2605 }
252b5132
RH		 2606
2607 if (pcrel)
2608 {
3e73aa7c 2609 if (!sign)
3956db08 2610 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2611 switch (size)
2612 {
2613 case 1: return BFD_RELOC_8_PCREL;
2614 case 2: return BFD_RELOC_16_PCREL;
2615 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2616 case 8: return BFD_RELOC_64_PCREL;
252b5132 2617 }
3956db08 2618 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2619 }
2620 else
2621 {
3956db08 2622 if (sign > 0)
e5cb08ac 2623 switch (size)
3e73aa7c
JH		 2624 {
2625 case 4: return BFD_RELOC_X86_64_32S;
2626 }
2627 else
2628 switch (size)
2629 {
2630 case 1: return BFD_RELOC_8;
2631 case 2: return BFD_RELOC_16;
2632 case 4: return BFD_RELOC_32;
2633 case 8: return BFD_RELOC_64;
2634 }
3956db08
JB		 2635 as_bad (_("cannot do %s %u byte relocation"),
2636 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2637 }
2638
0cc9e1d3 2639 return NO_RELOC;
252b5132
RH		 2640}
2641
47926f60
KH		 2642/* Here we decide which fixups can be adjusted to make them relative to
2643 the beginning of the section instead of the symbol. Basically we need
2644 to make sure that the dynamic relocations are done correctly, so in
2645 some cases we force the original symbol to be used. */
2646
252b5132 2647int
e3bb37b5 2648tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2649{
6d249963 2650#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2651 if (!IS_ELF)
31312f95
AM		 2652 return 1;
2653
a161fe53
AM		 2654 /* Don't adjust pc-relative references to merge sections in 64-bit
2655 mode. */
2656 if (use_rela_relocations
2657 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2658 && fixP->fx_pcrel)
252b5132 2659 return 0;
31312f95 2660
8d01d9a9
AJ		 2661 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2662 and changed later by validate_fix. */
2663 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2664 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2665 return 0;
2666
ce8a8b2f 2667 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2668 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2669 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2670 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2671 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2672 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2673 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2674 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2675 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2676 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2677 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2678 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2679 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2680 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2681 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2682 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2683 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2684 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2685 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2686 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2687 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2688 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2689 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2690 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2691 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2692 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2693 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2694 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2695 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2696 return 0;
31312f95 2697#endif
252b5132
RH		 2698 return 1;
2699}
252b5132 2700
b4cac588 2701static int
e3bb37b5 2702intel_float_operand (const char *mnemonic)
252b5132 2703{
9306ca4a
JB		 2704 /* Note that the value returned is meaningful only for opcodes with (memory)
2705 operands, hence the code here is free to improperly handle opcodes that
2706 have no operands (for better performance and smaller code). */
2707
2708 if (mnemonic[0] != 'f')
2709 return 0; /* non-math */
2710
2711 switch (mnemonic[1])
2712 {
2713 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2714 the fs segment override prefix not currently handled because no
2715 call path can make opcodes without operands get here */
2716 case 'i':
2717 return 2 /* integer op */;
2718 case 'l':
2719 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2720 return 3; /* fldcw/fldenv */
2721 break;
2722 case 'n':
2723 if (mnemonic[2] != 'o' /* fnop */)
2724 return 3; /* non-waiting control op */
2725 break;
2726 case 'r':
2727 if (mnemonic[2] == 's')
2728 return 3; /* frstor/frstpm */
2729 break;
2730 case 's':
2731 if (mnemonic[2] == 'a')
2732 return 3; /* fsave */
2733 if (mnemonic[2] == 't')
2734 {
2735 switch (mnemonic[3])
2736 {
2737 case 'c': /* fstcw */
2738 case 'd': /* fstdw */
2739 case 'e': /* fstenv */
2740 case 's': /* fsts[gw] */
2741 return 3;
2742 }
2743 }
2744 break;
2745 case 'x':
2746 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2747 return 0; /* fxsave/fxrstor are not really math ops */
2748 break;
2749 }
252b5132 2750
9306ca4a 2751 return 1;
252b5132
RH		 2752}
2753
c0f3af97
L		 2754/* Build the VEX prefix. */
2755
2756static void
d3ce72d0 2757build_vex_prefix (const insn_template *t)
c0f3af97
L		 2758{
2759 unsigned int register_specifier;
2760 unsigned int implied_prefix;
2761 unsigned int vector_length;
2762
2763 /* Check register specifier. */
2764 if (i.vex.register_specifier)
2765 {
2766 register_specifier = i.vex.register_specifier->reg_num;
2767 if ((i.vex.register_specifier->reg_flags & RegRex))
2768 register_specifier += 8;
2769 register_specifier = ~register_specifier & 0xf;
2770 }
2771 else
2772 register_specifier = 0xf;
2773
fa99fab2
L		 2774 /* Use 2-byte VEX prefix by swappping destination and source
2775 operand. */
2776 if (!i.swap_operand
2777 && i.operands == i.reg_operands
7f399153 2778 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2779 && i.tm.opcode_modifier.s
2780 && i.rex == REX_B)
2781 {
2782 unsigned int xchg = i.operands - 1;
2783 union i386_op temp_op;
2784 i386_operand_type temp_type;
2785
2786 temp_type = i.types[xchg];
2787 i.types[xchg] = i.types[0];
2788 i.types[0] = temp_type;
2789 temp_op = i.op[xchg];
2790 i.op[xchg] = i.op[0];
2791 i.op[0] = temp_op;
2792
9c2799c2 2793 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2794
2795 i.rex = REX_R;
2796 xchg = i.rm.regmem;
2797 i.rm.regmem = i.rm.reg;
2798 i.rm.reg = xchg;
2799
2800 /* Use the next insn. */
2801 i.tm = t[1];
2802 }
2803
539f890d
L		 2804 if (i.tm.opcode_modifier.vex == VEXScalar)
2805 vector_length = avxscalar;
2806 else
2807 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2808
2809 switch ((i.tm.base_opcode >> 8) & 0xff)
2810 {
2811 case 0:
2812 implied_prefix = 0;
2813 break;
2814 case DATA_PREFIX_OPCODE:
2815 implied_prefix = 1;
2816 break;
2817 case REPE_PREFIX_OPCODE:
2818 implied_prefix = 2;
2819 break;
2820 case REPNE_PREFIX_OPCODE:
2821 implied_prefix = 3;
2822 break;
2823 default:
2824 abort ();
2825 }
2826
2827 /* Use 2-byte VEX prefix if possible. */
7f399153 2828 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2829 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2830 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2831 {
2832 /* 2-byte VEX prefix. */
2833 unsigned int r;
2834
2835 i.vex.length = 2;
2836 i.vex.bytes[0] = 0xc5;
2837
2838 /* Check the REX.R bit. */
2839 r = (i.rex & REX_R) ? 0 : 1;
2840 i.vex.bytes[1] = (r << 7
2841 | register_specifier << 3
2842 | vector_length << 2
2843 | implied_prefix);
2844 }
2845 else
2846 {
2847 /* 3-byte VEX prefix. */
2848 unsigned int m, w;
2849
f88c9eb0 2850 i.vex.length = 3;
f88c9eb0 2851
7f399153 2852 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2853 {
7f399153
L		 2854 case VEX0F:
2855 m = 0x1;
80de6e00 2856 i.vex.bytes[0] = 0xc4;
7f399153
L		 2857 break;
2858 case VEX0F38:
2859 m = 0x2;
80de6e00 2860 i.vex.bytes[0] = 0xc4;
7f399153
L		 2861 break;
2862 case VEX0F3A:
2863 m = 0x3;
80de6e00 2864 i.vex.bytes[0] = 0xc4;
7f399153
L		 2865 break;
2866 case XOP08:
5dd85c99
SP		 2867 m = 0x8;
2868 i.vex.bytes[0] = 0x8f;
7f399153
L		 2869 break;
2870 case XOP09:
f88c9eb0
SP		 2871 m = 0x9;
2872 i.vex.bytes[0] = 0x8f;
7f399153
L		 2873 break;
2874 case XOP0A:
f88c9eb0
SP		 2875 m = 0xa;
2876 i.vex.bytes[0] = 0x8f;
7f399153
L		 2877 break;
2878 default:
2879 abort ();
f88c9eb0 2880 }
c0f3af97 2881
c0f3af97
L		 2882 /* The high 3 bits of the second VEX byte are 1's compliment
2883 of RXB bits from REX. */
2884 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2885
2886 /* Check the REX.W bit. */
2887 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2888 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2889 {
2890 if (w)
2891 abort ();
2892
1ef99a7b 2893 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2894 w = 1;
2895 }
2896
2897 i.vex.bytes[2] = (w << 7
2898 | register_specifier << 3
2899 | vector_length << 2
2900 | implied_prefix);
2901 }
2902}
2903
65da13b5
L		 2904static void
2905process_immext (void)
2906{
2907 expressionS *exp;
2908
2909 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2910 {
1fed0ba1
L		 2911 /* SSE3 Instructions have the fixed operands with an opcode
2912 suffix which is coded in the same place as an 8-bit immediate
2913 field would be. Here we check those operands and remove them
2914 afterwards. */
65da13b5
L		 2915 unsigned int x;
2916
2917 for (x = 0; x < i.operands; x++)
2918 if (i.op[x].regs->reg_num != x)
2919 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2920 register_prefix, i.op[x].regs->reg_name, x + 1,
2921 i.tm.name);
2922
2923 i.operands = 0;
65da13b5
L		 2924 }
2925
c0f3af97 2926 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2927 which is coded in the same place as an 8-bit immediate field
2928 would be. Here we fake an 8-bit immediate operand from the
2929 opcode suffix stored in tm.extension_opcode.
2930
c1e679ec 2931 AVX instructions also use this encoding, for some of
c0f3af97 2932 3 argument instructions. */
65da13b5 2933
9c2799c2 2934 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2935 && (i.operands <= 2
2936 || (i.tm.opcode_modifier.vex
2937 && i.operands <= 4)));
65da13b5
L		 2938
2939 exp = &im_expressions[i.imm_operands++];
2940 i.op[i.operands].imms = exp;
2941 i.types[i.operands] = imm8;
2942 i.operands++;
2943 exp->X_op = O_constant;
2944 exp->X_add_number = i.tm.extension_opcode;
2945 i.tm.extension_opcode = None;
2946}
2947
252b5132
RH		 2948/* This is the guts of the machine-dependent assembler. LINE points to a
2949 machine dependent instruction. This function is supposed to emit
2950 the frags/bytes it assembles to. */
2951
2952void
65da13b5 2953md_assemble (char *line)
252b5132 2954{
40fb9820 2955 unsigned int j;
252b5132 2956 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2957 const insn_template *t;
252b5132 2958
47926f60 2959 /* Initialize globals. */
252b5132
RH		 2960 memset (&i, '\0', sizeof (i));
2961 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2962 i.reloc[j] = NO_RELOC;
252b5132
RH		 2963 memset (disp_expressions, '\0', sizeof (disp_expressions));
2964 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2965 save_stack_p = save_stack;
252b5132
RH		 2966
2967 /* First parse an instruction mnemonic & call i386_operand for the operands.
2968 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2969 start of a (possibly prefixed) mnemonic. */
252b5132 2970
29b0f896
AM		 2971 line = parse_insn (line, mnemonic);
2972 if (line == NULL)
2973 return;
252b5132 2974
29b0f896 2975 line = parse_operands (line, mnemonic);
ee86248c 2976 this_operand = -1;
29b0f896
AM		 2977 if (line == NULL)
2978 return;
252b5132 2979
29b0f896
AM		 2980 /* Now we've parsed the mnemonic into a set of templates, and have the
2981 operands at hand. */
2982
2983 /* All intel opcodes have reversed operands except for "bound" and
2984 "enter". We also don't reverse intersegment "jmp" and "call"
2985 instructions with 2 immediate operands so that the immediate segment
050dfa73 2986 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2987 if (intel_syntax
2988 && i.operands > 1
29b0f896 2989 && (strcmp (mnemonic, "bound") != 0)
30123838 2990 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2991 && !(operand_type_check (i.types[0], imm)
2992 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2993 swap_operands ();
2994
ec56d5c0
JB		 2995 /* The order of the immediates should be reversed
2996 for 2 immediates extrq and insertq instructions */
2997 if (i.imm_operands == 2
2998 && (strcmp (mnemonic, "extrq") == 0
2999 || strcmp (mnemonic, "insertq") == 0))
3000 swap_2_operands (0, 1);
3001
29b0f896
AM		 3002 if (i.imm_operands)
3003 optimize_imm ();
3004
b300c311
L		 3005 /* Don't optimize displacement for movabs since it only takes 64bit
3006 displacement. */
3007 if (i.disp_operands
f8a5c266 3008 && !i.disp32_encoding
b300c311
L		 3009 && (flag_code != CODE_64BIT
3010 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 3011 optimize_disp ();
3012
3013 /* Next, we find a template that matches the given insn,
3014 making sure the overlap of the given operands types is consistent
3015 with the template operand types. */
252b5132 3016
fa99fab2 3017 if (!(t = match_template ()))
29b0f896 3018 return;
252b5132 3019
daf50ae7 3020 if (sse_check != sse_check_none
81f8a913 3021 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3022 && (i.tm.cpu_flags.bitfield.cpusse
3023 || i.tm.cpu_flags.bitfield.cpusse2
3024 || i.tm.cpu_flags.bitfield.cpusse3
3025 || i.tm.cpu_flags.bitfield.cpussse3
3026 || i.tm.cpu_flags.bitfield.cpusse4_1
3027 || i.tm.cpu_flags.bitfield.cpusse4_2))
3028 {
3029 (sse_check == sse_check_warning
3030 ? as_warn
3031 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3032 }
3033
321fd21e
L		 3034 /* Zap movzx and movsx suffix. The suffix has been set from
3035 "word ptr" or "byte ptr" on the source operand in Intel syntax
3036 or extracted from mnemonic in AT&T syntax. But we'll use
3037 the destination register to choose the suffix for encoding. */
3038 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3039 {
321fd21e
L		 3040 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3041 there is no suffix, the default will be byte extension. */
3042 if (i.reg_operands != 2
3043 && !i.suffix
7ab9ffdd 3044 && intel_syntax)
321fd21e
L		 3045 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3046
3047 i.suffix = 0;
cd61ebfe 3048 }
24eab124 3049
40fb9820 3050 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3051 if (!add_prefix (FWAIT_OPCODE))
3052 return;
252b5132 3053
c1ba0266
L		 3054 /* Check for lock without a lockable instruction. Destination operand
3055 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3056 if (i.prefix[LOCK_PREFIX]
3057 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3058 || i.mem_operands == 0
3059 || (i.tm.base_opcode != 0x86
3060 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3061 {
3062 as_bad (_("expecting lockable instruction after `lock'"));
3063 return;
3064 }
3065
29b0f896 3066 /* Check string instruction segment overrides. */
40fb9820 3067 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3068 {
3069 if (!check_string ())
5dd0794d 3070 return;
fc0763e6 3071 i.disp_operands = 0;
29b0f896 3072 }
5dd0794d 3073
29b0f896
AM		 3074 if (!process_suffix ())
3075 return;
e413e4e9 3076
bc0844ae
L		 3077 /* Update operand types. */
3078 for (j = 0; j < i.operands; j++)
3079 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3080
29b0f896
AM		 3081 /* Make still unresolved immediate matches conform to size of immediate
3082 given in i.suffix. */
3083 if (!finalize_imm ())
3084 return;
252b5132 3085
40fb9820 3086 if (i.types[0].bitfield.imm1)
29b0f896 3087 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3088
9afe6eb8
L		 3089 /* We only need to check those implicit registers for instructions
3090 with 3 operands or less. */
3091 if (i.operands <= 3)
3092 for (j = 0; j < i.operands; j++)
3093 if (i.types[j].bitfield.inoutportreg
3094 || i.types[j].bitfield.shiftcount
3095 || i.types[j].bitfield.acc
3096 || i.types[j].bitfield.floatacc)
3097 i.reg_operands--;
40fb9820 3098
c0f3af97
L		 3099 /* ImmExt should be processed after SSE2AVX. */
3100 if (!i.tm.opcode_modifier.sse2avx
3101 && i.tm.opcode_modifier.immext)
65da13b5 3102 process_immext ();
252b5132 3103
29b0f896
AM		 3104 /* For insns with operands there are more diddles to do to the opcode. */
3105 if (i.operands)
3106 {
3107 if (!process_operands ())
3108 return;
3109 }
40fb9820 3110 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3111 {
3112 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3113 as_warn (_("translating to `%sp'"), i.tm.name);
3114 }
252b5132 3115
c0f3af97 3116 if (i.tm.opcode_modifier.vex)
fa99fab2 3117 build_vex_prefix (t);
c0f3af97 3118
5dd85c99
SP		 3119 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3120 instructions may define INT_OPCODE as well, so avoid this corner
3121 case for those instructions that use MODRM. */
3122 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3123 && !i.tm.opcode_modifier.modrm
3124 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3125 {
3126 i.tm.base_opcode = INT3_OPCODE;
3127 i.imm_operands = 0;
3128 }
252b5132 3129
40fb9820
L		 3130 if ((i.tm.opcode_modifier.jump
3131 || i.tm.opcode_modifier.jumpbyte
3132 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3133 && i.op[0].disps->X_op == O_constant)
3134 {
3135 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3136 the absolute address given by the constant. Since ix86 jumps and
3137 calls are pc relative, we need to generate a reloc. */
3138 i.op[0].disps->X_add_symbol = &abs_symbol;
3139 i.op[0].disps->X_op = O_symbol;
3140 }
252b5132 3141
40fb9820 3142 if (i.tm.opcode_modifier.rex64)
161a04f6 3143 i.rex |= REX_W;
252b5132 3144
29b0f896
AM		 3145 /* For 8 bit registers we need an empty rex prefix. Also if the
3146 instruction already has a prefix, we need to convert old
3147 registers to new ones. */
773f551c 3148
40fb9820 3149 if ((i.types[0].bitfield.reg8
29b0f896 3150 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3151 || (i.types[1].bitfield.reg8
29b0f896 3152 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3153 || ((i.types[0].bitfield.reg8
3154 || i.types[1].bitfield.reg8)
29b0f896
AM		 3155 && i.rex != 0))
3156 {
3157 int x;
726c5dcd 3158
29b0f896
AM		 3159 i.rex |= REX_OPCODE;
3160 for (x = 0; x < 2; x++)
3161 {
3162 /* Look for 8 bit operand that uses old registers. */
40fb9820 3163 if (i.types[x].bitfield.reg8
29b0f896 3164 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3165 {
29b0f896
AM		 3166 /* In case it is "hi" register, give up. */
3167 if (i.op[x].regs->reg_num > 3)
a540244d 3168 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3169 "instruction requiring REX prefix."),
a540244d 3170 register_prefix, i.op[x].regs->reg_name);
773f551c 3171
29b0f896
AM		 3172 /* Otherwise it is equivalent to the extended register.
3173 Since the encoding doesn't change this is merely
3174 cosmetic cleanup for debug output. */
3175
3176 i.op[x].regs = i.op[x].regs + 8;
773f551c 3177 }
29b0f896
AM		 3178 }
3179 }
773f551c 3180
7ab9ffdd 3181 if (i.rex != 0)
29b0f896
AM		 3182 add_prefix (REX_OPCODE | i.rex);
3183
3184 /* We are ready to output the insn. */
3185 output_insn ();
3186}
3187
3188static char *
e3bb37b5 3189parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3190{
3191 char *l = line;
3192 char *token_start = l;
3193 char *mnem_p;
5c6af06e 3194 int supported;
d3ce72d0 3195 const insn_template *t;
b6169b20 3196 char *dot_p = NULL;
29b0f896
AM		 3197
3198 /* Non-zero if we found a prefix only acceptable with string insns. */
3199 const char *expecting_string_instruction = NULL;
45288df1 3200
29b0f896
AM		 3201 while (1)
3202 {
3203 mnem_p = mnemonic;
3204 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3205 {
b6169b20
L		 3206 if (*mnem_p == '.')
3207 dot_p = mnem_p;
29b0f896
AM		 3208 mnem_p++;
3209 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3210 {
29b0f896
AM		 3211 as_bad (_("no such instruction: `%s'"), token_start);
3212 return NULL;
3213 }
3214 l++;
3215 }
3216 if (!is_space_char (*l)
3217 && *l != END_OF_INSN
e44823cf
JB		 3218 && (intel_syntax
3219 || (*l != PREFIX_SEPARATOR
3220 && *l != ',')))
29b0f896
AM		 3221 {
3222 as_bad (_("invalid character %s in mnemonic"),
3223 output_invalid (*l));
3224 return NULL;
3225 }
3226 if (token_start == l)
3227 {
e44823cf 3228 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3229 as_bad (_("expecting prefix; got nothing"));
3230 else
3231 as_bad (_("expecting mnemonic; got nothing"));
3232 return NULL;
3233 }
45288df1 3234
29b0f896 3235 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3236 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3237
29b0f896
AM		 3238 if (*l != END_OF_INSN
3239 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3240 && current_templates
40fb9820 3241 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3242 {
c6fb90c8 3243 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3244 {
3245 as_bad ((flag_code != CODE_64BIT
3246 ? _("`%s' is only supported in 64-bit mode")
3247 : _("`%s' is not supported in 64-bit mode")),
3248 current_templates->start->name);
3249 return NULL;
3250 }
29b0f896
AM		 3251 /* If we are in 16-bit mode, do not allow addr16 or data16.
3252 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3253 if ((current_templates->start->opcode_modifier.size16
3254 || current_templates->start->opcode_modifier.size32)
29b0f896 3255 && flag_code != CODE_64BIT
40fb9820 3256 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3257 ^ (flag_code == CODE_16BIT)))
3258 {
3259 as_bad (_("redundant %s prefix"),
3260 current_templates->start->name);
3261 return NULL;
45288df1 3262 }
29b0f896
AM		 3263 /* Add prefix, checking for repeated prefixes. */
3264 switch (add_prefix (current_templates->start->base_opcode))
3265 {
c32fa91d 3266 case PREFIX_EXIST:
29b0f896 3267 return NULL;
c32fa91d 3268 case PREFIX_REP:
29b0f896
AM		 3269 expecting_string_instruction = current_templates->start->name;
3270 break;
c32fa91d
L		 3271 default:
3272 break;
29b0f896
AM		 3273 }
3274 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3275 token_start = ++l;
3276 }
3277 else
3278 break;
3279 }
45288df1 3280
30a55f88 3281 if (!current_templates)
b6169b20 3282 {
f8a5c266
L		 3283 /* Check if we should swap operand or force 32bit displacement in
3284 encoding. */
30a55f88
L		 3285 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3286 i.swap_operand = 1;
f8a5c266
L		 3287 else if (mnem_p - 4 == dot_p
3288 && dot_p[1] == 'd'
3289 && dot_p[2] == '3'
3290 && dot_p[3] == '2')
3291 i.disp32_encoding = 1;
30a55f88
L		 3292 else
3293 goto check_suffix;
3294 mnem_p = dot_p;
3295 *dot_p = '\0';
d3ce72d0 3296 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3297 }
3298
29b0f896
AM		 3299 if (!current_templates)
3300 {
b6169b20 3301check_suffix:
29b0f896
AM		 3302 /* See if we can get a match by trimming off a suffix. */
3303 switch (mnem_p[-1])
3304 {
3305 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3306 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3307 i.suffix = SHORT_MNEM_SUFFIX;
3308 else
29b0f896
AM		 3309 case BYTE_MNEM_SUFFIX:
3310 case QWORD_MNEM_SUFFIX:
3311 i.suffix = mnem_p[-1];
3312 mnem_p[-1] = '\0';
d3ce72d0
NC		 3313 current_templates = (const templates *) hash_find (op_hash,
3314 mnemonic);
29b0f896
AM		 3315 break;
3316 case SHORT_MNEM_SUFFIX:
3317 case LONG_MNEM_SUFFIX:
3318 if (!intel_syntax)
3319 {
3320 i.suffix = mnem_p[-1];
3321 mnem_p[-1] = '\0';
d3ce72d0
NC		 3322 current_templates = (const templates *) hash_find (op_hash,
3323 mnemonic);
29b0f896
AM		 3324 }
3325 break;
252b5132 3326
29b0f896
AM		 3327 /* Intel Syntax. */
3328 case 'd':
3329 if (intel_syntax)
3330 {
9306ca4a 3331 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3332 i.suffix = SHORT_MNEM_SUFFIX;
3333 else
3334 i.suffix = LONG_MNEM_SUFFIX;
3335 mnem_p[-1] = '\0';
d3ce72d0
NC		 3336 current_templates = (const templates *) hash_find (op_hash,
3337 mnemonic);
29b0f896
AM		 3338 }
3339 break;
3340 }
3341 if (!current_templates)
3342 {
3343 as_bad (_("no such instruction: `%s'"), token_start);
3344 return NULL;
3345 }
3346 }
252b5132 3347
40fb9820
L		 3348 if (current_templates->start->opcode_modifier.jump
3349 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3350 {
3351 /* Check for a branch hint. We allow ",pt" and ",pn" for
3352 predict taken and predict not taken respectively.
3353 I'm not sure that branch hints actually do anything on loop
3354 and jcxz insns (JumpByte) for current Pentium4 chips. They
3355 may work in the future and it doesn't hurt to accept them
3356 now. */
3357 if (l[0] == ',' && l[1] == 'p')
3358 {
3359 if (l[2] == 't')
3360 {
3361 if (!add_prefix (DS_PREFIX_OPCODE))
3362 return NULL;
3363 l += 3;
3364 }
3365 else if (l[2] == 'n')
3366 {
3367 if (!add_prefix (CS_PREFIX_OPCODE))
3368 return NULL;
3369 l += 3;
3370 }
3371 }
3372 }
3373 /* Any other comma loses. */
3374 if (*l == ',')
3375 {
3376 as_bad (_("invalid character %s in mnemonic"),
3377 output_invalid (*l));
3378 return NULL;
3379 }
252b5132 3380
29b0f896 3381 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3382 supported = 0;
3383 for (t = current_templates->start; t < current_templates->end; ++t)
3384 {
c0f3af97
L		 3385 supported |= cpu_flags_match (t);
3386 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3387 goto skip;
5c6af06e 3388 }
3629bb00 3389
c0f3af97 3390 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3391 {
3392 as_bad (flag_code == CODE_64BIT
3393 ? _("`%s' is not supported in 64-bit mode")
3394 : _("`%s' is only supported in 64-bit mode"),
3395 current_templates->start->name);
3396 return NULL;
3397 }
c0f3af97 3398 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3399 {
3629bb00 3400 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3401 current_templates->start->name,
41aacd83 3402 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3403 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3404 return NULL;
29b0f896 3405 }
3629bb00
L		 3406
3407skip:
3408 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3409 && (flag_code != CODE_16BIT))
29b0f896
AM		 3410 {
3411 as_warn (_("use .code16 to ensure correct addressing mode"));
3412 }
252b5132 3413
29b0f896 3414 /* Check for rep/repne without a string instruction. */
f41bbced 3415 if (expecting_string_instruction)
29b0f896 3416 {
f41bbced
JB		 3417 static templates override;
3418
3419 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3420 if (t->opcode_modifier.isstring)
f41bbced
JB		 3421 break;
3422 if (t >= current_templates->end)
3423 {
3424 as_bad (_("expecting string instruction after `%s'"),
64e74474 3425 expecting_string_instruction);
f41bbced
JB		 3426 return NULL;
3427 }
3428 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3429 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3430 break;
3431 override.end = t;
3432 current_templates = &override;
29b0f896 3433 }
252b5132 3434
29b0f896
AM		 3435 return l;
3436}
252b5132 3437
29b0f896 3438static char *
e3bb37b5 3439parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3440{
3441 char *token_start;
3138f287 3442
29b0f896
AM		 3443 /* 1 if operand is pending after ','. */
3444 unsigned int expecting_operand = 0;
252b5132 3445
29b0f896
AM		 3446 /* Non-zero if operand parens not balanced. */
3447 unsigned int paren_not_balanced;
3448
3449 while (*l != END_OF_INSN)
3450 {
3451 /* Skip optional white space before operand. */
3452 if (is_space_char (*l))
3453 ++l;
3454 if (!is_operand_char (*l) && *l != END_OF_INSN)
3455 {
3456 as_bad (_("invalid character %s before operand %d"),
3457 output_invalid (*l),
3458 i.operands + 1);
3459 return NULL;
3460 }
3461 token_start = l; /* after white space */
3462 paren_not_balanced = 0;
3463 while (paren_not_balanced || *l != ',')
3464 {
3465 if (*l == END_OF_INSN)
3466 {
3467 if (paren_not_balanced)
3468 {
3469 if (!intel_syntax)
3470 as_bad (_("unbalanced parenthesis in operand %d."),
3471 i.operands + 1);
3472 else
3473 as_bad (_("unbalanced brackets in operand %d."),
3474 i.operands + 1);
3475 return NULL;
3476 }
3477 else
3478 break; /* we are done */
3479 }
3480 else if (!is_operand_char (*l) && !is_space_char (*l))
3481 {
3482 as_bad (_("invalid character %s in operand %d"),
3483 output_invalid (*l),
3484 i.operands + 1);
3485 return NULL;
3486 }
3487 if (!intel_syntax)
3488 {
3489 if (*l == '(')
3490 ++paren_not_balanced;
3491 if (*l == ')')
3492 --paren_not_balanced;
3493 }
3494 else
3495 {
3496 if (*l == '[')
3497 ++paren_not_balanced;
3498 if (*l == ']')
3499 --paren_not_balanced;
3500 }
3501 l++;
3502 }
3503 if (l != token_start)
3504 { /* Yes, we've read in another operand. */
3505 unsigned int operand_ok;
3506 this_operand = i.operands++;
7d5e4556 3507 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3508 if (i.operands > MAX_OPERANDS)
3509 {
3510 as_bad (_("spurious operands; (%d operands/instruction max)"),
3511 MAX_OPERANDS);
3512 return NULL;
3513 }
3514 /* Now parse operand adding info to 'i' as we go along. */
3515 END_STRING_AND_SAVE (l);
3516
3517 if (intel_syntax)
3518 operand_ok =
3519 i386_intel_operand (token_start,
3520 intel_float_operand (mnemonic));
3521 else
a7619375 3522 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3523
3524 RESTORE_END_STRING (l);
3525 if (!operand_ok)
3526 return NULL;
3527 }
3528 else
3529 {
3530 if (expecting_operand)
3531 {
3532 expecting_operand_after_comma:
3533 as_bad (_("expecting operand after ','; got nothing"));
3534 return NULL;
3535 }
3536 if (*l == ',')
3537 {
3538 as_bad (_("expecting operand before ','; got nothing"));
3539 return NULL;
3540 }
3541 }
7f3f1ea2 3542
29b0f896
AM		 3543 /* Now *l must be either ',' or END_OF_INSN. */
3544 if (*l == ',')
3545 {
3546 if (*++l == END_OF_INSN)
3547 {
3548 /* Just skip it, if it's \n complain. */
3549 goto expecting_operand_after_comma;
3550 }
3551 expecting_operand = 1;
3552 }
3553 }
3554 return l;
3555}
7f3f1ea2 3556
050dfa73 3557static void
4d456e3d 3558swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3559{
3560 union i386_op temp_op;
40fb9820 3561 i386_operand_type temp_type;
050dfa73 3562 enum bfd_reloc_code_real temp_reloc;
4eed87de 3563
050dfa73
MM		 3564 temp_type = i.types[xchg2];
3565 i.types[xchg2] = i.types[xchg1];
3566 i.types[xchg1] = temp_type;
3567 temp_op = i.op[xchg2];
3568 i.op[xchg2] = i.op[xchg1];
3569 i.op[xchg1] = temp_op;
3570 temp_reloc = i.reloc[xchg2];
3571 i.reloc[xchg2] = i.reloc[xchg1];
3572 i.reloc[xchg1] = temp_reloc;
3573}
3574
29b0f896 3575static void
e3bb37b5 3576swap_operands (void)
29b0f896 3577{
b7c61d9a 3578 switch (i.operands)
050dfa73 3579 {
c0f3af97 3580 case 5:
b7c61d9a 3581 case 4:
4d456e3d 3582 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3583 case 3:
3584 case 2:
4d456e3d 3585 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3586 break;
3587 default:
3588 abort ();
29b0f896 3589 }
29b0f896
AM		 3590
3591 if (i.mem_operands == 2)
3592 {
3593 const seg_entry *temp_seg;
3594 temp_seg = i.seg[0];
3595 i.seg[0] = i.seg[1];
3596 i.seg[1] = temp_seg;
3597 }
3598}
252b5132 3599
29b0f896
AM		 3600/* Try to ensure constant immediates are represented in the smallest
3601 opcode possible. */
3602static void
e3bb37b5 3603optimize_imm (void)
29b0f896
AM		 3604{
3605 char guess_suffix = 0;
3606 int op;
252b5132 3607
29b0f896
AM		 3608 if (i.suffix)
3609 guess_suffix = i.suffix;
3610 else if (i.reg_operands)
3611 {
3612 /* Figure out a suffix from the last register operand specified.
3613 We can't do this properly yet, ie. excluding InOutPortReg,
3614 but the following works for instructions with immediates.
3615 In any case, we can't set i.suffix yet. */
3616 for (op = i.operands; --op >= 0;)
40fb9820 3617 if (i.types[op].bitfield.reg8)
7ab9ffdd 3618 {
40fb9820
L		 3619 guess_suffix = BYTE_MNEM_SUFFIX;
3620 break;
3621 }
3622 else if (i.types[op].bitfield.reg16)
252b5132 3623 {
40fb9820
L		 3624 guess_suffix = WORD_MNEM_SUFFIX;
3625 break;
3626 }
3627 else if (i.types[op].bitfield.reg32)
3628 {
3629 guess_suffix = LONG_MNEM_SUFFIX;
3630 break;
3631 }
3632 else if (i.types[op].bitfield.reg64)
3633 {
3634 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3635 break;
252b5132 3636 }
29b0f896
AM		 3637 }
3638 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3639 guess_suffix = WORD_MNEM_SUFFIX;
3640
3641 for (op = i.operands; --op >= 0;)
40fb9820 3642 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3643 {
3644 switch (i.op[op].imms->X_op)
252b5132 3645 {
29b0f896
AM		 3646 case O_constant:
3647 /* If a suffix is given, this operand may be shortened. */
3648 switch (guess_suffix)
252b5132 3649 {
29b0f896 3650 case LONG_MNEM_SUFFIX:
40fb9820
L		 3651 i.types[op].bitfield.imm32 = 1;
3652 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3653 break;
3654 case WORD_MNEM_SUFFIX:
40fb9820
L		 3655 i.types[op].bitfield.imm16 = 1;
3656 i.types[op].bitfield.imm32 = 1;
3657 i.types[op].bitfield.imm32s = 1;
3658 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3659 break;
3660 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3661 i.types[op].bitfield.imm8 = 1;
3662 i.types[op].bitfield.imm8s = 1;
3663 i.types[op].bitfield.imm16 = 1;
3664 i.types[op].bitfield.imm32 = 1;
3665 i.types[op].bitfield.imm32s = 1;
3666 i.types[op].bitfield.imm64 = 1;
29b0f896 3667 break;
252b5132 3668 }
252b5132 3669
29b0f896
AM		 3670 /* If this operand is at most 16 bits, convert it
3671 to a signed 16 bit number before trying to see
3672 whether it will fit in an even smaller size.
3673 This allows a 16-bit operand such as $0xffe0 to
3674 be recognised as within Imm8S range. */
40fb9820 3675 if ((i.types[op].bitfield.imm16)
29b0f896 3676 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3677 {
29b0f896
AM		 3678 i.op[op].imms->X_add_number =
3679 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3680 }
40fb9820 3681 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3682 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3683 == 0))
3684 {
3685 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3686 ^ ((offsetT) 1 << 31))
3687 - ((offsetT) 1 << 31));
3688 }
40fb9820 3689 i.types[op]
c6fb90c8
L		 3690 = operand_type_or (i.types[op],
3691 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3692
29b0f896
AM		 3693 /* We must avoid matching of Imm32 templates when 64bit
3694 only immediate is available. */
3695 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3696 i.types[op].bitfield.imm32 = 0;
29b0f896 3697 break;
252b5132 3698
29b0f896
AM		 3699 case O_absent:
3700 case O_register:
3701 abort ();
3702
3703 /* Symbols and expressions. */
3704 default:
9cd96992
JB		 3705 /* Convert symbolic operand to proper sizes for matching, but don't
3706 prevent matching a set of insns that only supports sizes other
3707 than those matching the insn suffix. */
3708 {
40fb9820 3709 i386_operand_type mask, allowed;
d3ce72d0 3710 const insn_template *t;
9cd96992 3711
0dfbf9d7
L		 3712 operand_type_set (&mask, 0);
3713 operand_type_set (&allowed, 0);
40fb9820 3714
4eed87de
AM		 3715 for (t = current_templates->start;
3716 t < current_templates->end;
3717 ++t)
c6fb90c8
L		 3718 allowed = operand_type_or (allowed,
3719 t->operand_types[op]);
9cd96992
JB		 3720 switch (guess_suffix)
3721 {
3722 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3723 mask.bitfield.imm64 = 1;
3724 mask.bitfield.imm32s = 1;
9cd96992
JB		 3725 break;
3726 case LONG_MNEM_SUFFIX:
40fb9820 3727 mask.bitfield.imm32 = 1;
9cd96992
JB		 3728 break;
3729 case WORD_MNEM_SUFFIX:
40fb9820 3730 mask.bitfield.imm16 = 1;
9cd96992
JB		 3731 break;
3732 case BYTE_MNEM_SUFFIX:
40fb9820 3733 mask.bitfield.imm8 = 1;
9cd96992
JB		 3734 break;
3735 default:
9cd96992
JB		 3736 break;
3737 }
c6fb90c8 3738 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3739 if (!operand_type_all_zero (&allowed))
c6fb90c8 3740 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3741 }
29b0f896 3742 break;
252b5132 3743 }
29b0f896
AM		 3744 }
3745}
47926f60 3746
29b0f896
AM		 3747/* Try to use the smallest displacement type too. */
3748static void
e3bb37b5 3749optimize_disp (void)
29b0f896
AM		 3750{
3751 int op;
3e73aa7c 3752
29b0f896 3753 for (op = i.operands; --op >= 0;)
40fb9820 3754 if (operand_type_check (i.types[op], disp))
252b5132 3755 {
b300c311 3756 if (i.op[op].disps->X_op == O_constant)
252b5132 3757 {
91d6fa6a 3758 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3759
40fb9820 3760 if (i.types[op].bitfield.disp16
91d6fa6a 3761 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3762 {
3763 /* If this operand is at most 16 bits, convert
3764 to a signed 16 bit number and don't use 64bit
3765 displacement. */
91d6fa6a 3766 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3767 i.types[op].bitfield.disp64 = 0;
b300c311 3768 }
40fb9820 3769 if (i.types[op].bitfield.disp32
91d6fa6a 3770 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3771 {
3772 /* If this operand is at most 32 bits, convert
3773 to a signed 32 bit number and don't use 64bit
3774 displacement. */
91d6fa6a
NC		 3775 op_disp &= (((offsetT) 2 << 31) - 1);
3776 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3777 i.types[op].bitfield.disp64 = 0;
b300c311 3778 }
91d6fa6a 3779 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3780 {
40fb9820
L		 3781 i.types[op].bitfield.disp8 = 0;
3782 i.types[op].bitfield.disp16 = 0;
3783 i.types[op].bitfield.disp32 = 0;
3784 i.types[op].bitfield.disp32s = 0;
3785 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3786 i.op[op].disps = 0;
3787 i.disp_operands--;
3788 }
3789 else if (flag_code == CODE_64BIT)
3790 {
91d6fa6a 3791 if (fits_in_signed_long (op_disp))
28a9d8f5 3792 {
40fb9820
L		 3793 i.types[op].bitfield.disp64 = 0;
3794 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3795 }
0e1147d9 3796 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3797 && fits_in_unsigned_long (op_disp))
40fb9820 3798 i.types[op].bitfield.disp32 = 1;
b300c311 3799 }
40fb9820
L		 3800 if ((i.types[op].bitfield.disp32
3801 || i.types[op].bitfield.disp32s
3802 || i.types[op].bitfield.disp16)
91d6fa6a 3803 && fits_in_signed_byte (op_disp))
40fb9820 3804 i.types[op].bitfield.disp8 = 1;
252b5132 3805 }
67a4f2b7
AO		 3806 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3807 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3808 {
3809 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3810 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3811 i.types[op].bitfield.disp8 = 0;
3812 i.types[op].bitfield.disp16 = 0;
3813 i.types[op].bitfield.disp32 = 0;
3814 i.types[op].bitfield.disp32s = 0;
3815 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3816 }
3817 else
b300c311 3818 /* We only support 64bit displacement on constants. */
40fb9820 3819 i.types[op].bitfield.disp64 = 0;
252b5132 3820 }
29b0f896
AM		 3821}
3822
43f3e2ee 3823/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3824 operand types. */
3825
3826static int
3827VEX_check_operands (const insn_template *t)
3828{
3829 if (!t->opcode_modifier.vex)
3830 return 0;
3831
3832 /* Only check VEX_Imm4, which must be the first operand. */
3833 if (t->operand_types[0].bitfield.vec_imm4)
3834 {
3835 if (i.op[0].imms->X_op != O_constant
3836 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3837 {
a65babc9 3838 i.error = bad_imm4;
891edac4
L		 3839 return 1;
3840 }
a683cc34
SP		 3841
3842 /* Turn off Imm8 so that update_imm won't complain. */
3843 i.types[0] = vec_imm4;
3844 }
3845
3846 return 0;
3847}
3848
d3ce72d0 3849static const insn_template *
e3bb37b5 3850match_template (void)
29b0f896
AM		 3851{
3852 /* Points to template once we've found it. */
d3ce72d0 3853 const insn_template *t;
40fb9820 3854 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3855 i386_operand_type overlap4;
29b0f896 3856 unsigned int found_reverse_match;
40fb9820
L		 3857 i386_opcode_modifier suffix_check;
3858 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3859 int addr_prefix_disp;
a5c311ca 3860 unsigned int j;
3629bb00 3861 unsigned int found_cpu_match;
45664ddb 3862 unsigned int check_register;
29b0f896 3863
c0f3af97
L		 3864#if MAX_OPERANDS != 5
3865# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3866#endif
3867
29b0f896 3868 found_reverse_match = 0;
539e75ad 3869 addr_prefix_disp = -1;
40fb9820
L		 3870
3871 memset (&suffix_check, 0, sizeof (suffix_check));
3872 if (i.suffix == BYTE_MNEM_SUFFIX)
3873 suffix_check.no_bsuf = 1;
3874 else if (i.suffix == WORD_MNEM_SUFFIX)
3875 suffix_check.no_wsuf = 1;
3876 else if (i.suffix == SHORT_MNEM_SUFFIX)
3877 suffix_check.no_ssuf = 1;
3878 else if (i.suffix == LONG_MNEM_SUFFIX)
3879 suffix_check.no_lsuf = 1;
3880 else if (i.suffix == QWORD_MNEM_SUFFIX)
3881 suffix_check.no_qsuf = 1;
3882 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3883 suffix_check.no_ldsuf = 1;
29b0f896 3884
01559ecc
L		 3885 /* Must have right number of operands. */
3886 i.error = number_of_operands_mismatch;
3887
45aa61fe 3888 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3889 {
539e75ad
L		 3890 addr_prefix_disp = -1;
3891
29b0f896
AM		 3892 if (i.operands != t->operands)
3893 continue;
3894
50aecf8c 3895 /* Check processor support. */
a65babc9 3896 i.error = unsupported;
c0f3af97
L		 3897 found_cpu_match = (cpu_flags_match (t)
3898 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3899 if (!found_cpu_match)
3900 continue;
3901
e1d4d893 3902 /* Check old gcc support. */
a65babc9 3903 i.error = old_gcc_only;
e1d4d893
L		 3904 if (!old_gcc && t->opcode_modifier.oldgcc)
3905 continue;
3906
3907 /* Check AT&T mnemonic. */
a65babc9 3908 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3909 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3910 continue;
3911
891edac4 3912 /* Check AT&T/Intel syntax. */
a65babc9 3913 i.error = unsupported_syntax;
5c07affc
L		 3914 if ((intel_syntax && t->opcode_modifier.attsyntax)
3915 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3916 continue;
3917
20592a94 3918 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3919 i.error = invalid_instruction_suffix;
567e4e96
L		 3920 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3921 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3922 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3923 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3924 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3925 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3926 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3927 continue;
3928
5c07affc 3929 if (!operand_size_match (t))
7d5e4556 3930 continue;
539e75ad 3931
5c07affc
L		 3932 for (j = 0; j < MAX_OPERANDS; j++)
3933 operand_types[j] = t->operand_types[j];
3934
45aa61fe
AM		 3935 /* In general, don't allow 64-bit operands in 32-bit mode. */
3936 if (i.suffix == QWORD_MNEM_SUFFIX
3937 && flag_code != CODE_64BIT
3938 && (intel_syntax
40fb9820 3939 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3940 && !intel_float_operand (t->name))
3941 : intel_float_operand (t->name) != 2)
40fb9820 3942 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3943 && !operand_types[0].bitfield.regxmm
3944 && !operand_types[0].bitfield.regymm)
40fb9820 3945 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3946 && !!operand_types[t->operands > 1].bitfield.regxmm
3947 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3948 && (t->base_opcode != 0x0fc7
3949 || t->extension_opcode != 1 /* cmpxchg8b */))
3950 continue;
3951
192dc9c6
JB		 3952 /* In general, don't allow 32-bit operands on pre-386. */
3953 else if (i.suffix == LONG_MNEM_SUFFIX
3954 && !cpu_arch_flags.bitfield.cpui386
3955 && (intel_syntax
3956 ? (!t->opcode_modifier.ignoresize
3957 && !intel_float_operand (t->name))
3958 : intel_float_operand (t->name) != 2)
3959 && ((!operand_types[0].bitfield.regmmx
3960 && !operand_types[0].bitfield.regxmm)
3961 || (!operand_types[t->operands > 1].bitfield.regmmx
3962 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3963 continue;
3964
29b0f896 3965 /* Do not verify operands when there are none. */
50aecf8c 3966 else
29b0f896 3967 {
c6fb90c8 3968 if (!t->operands)
2dbab7d5
L		 3969 /* We've found a match; break out of loop. */
3970 break;
29b0f896 3971 }
252b5132 3972
539e75ad
L		 3973 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3974 into Disp32/Disp16/Disp32 operand. */
3975 if (i.prefix[ADDR_PREFIX] != 0)
3976 {
40fb9820 3977 /* There should be only one Disp operand. */
539e75ad
L		 3978 switch (flag_code)
3979 {
3980 case CODE_16BIT:
40fb9820
L		 3981 for (j = 0; j < MAX_OPERANDS; j++)
3982 {
3983 if (operand_types[j].bitfield.disp16)
3984 {
3985 addr_prefix_disp = j;
3986 operand_types[j].bitfield.disp32 = 1;
3987 operand_types[j].bitfield.disp16 = 0;
3988 break;
3989 }
3990 }
539e75ad
L		 3991 break;
3992 case CODE_32BIT:
40fb9820
L		 3993 for (j = 0; j < MAX_OPERANDS; j++)
3994 {
3995 if (operand_types[j].bitfield.disp32)
3996 {
3997 addr_prefix_disp = j;
3998 operand_types[j].bitfield.disp32 = 0;
3999 operand_types[j].bitfield.disp16 = 1;
4000 break;
4001 }
4002 }
539e75ad
L		 4003 break;
4004 case CODE_64BIT:
40fb9820
L		 4005 for (j = 0; j < MAX_OPERANDS; j++)
4006 {
4007 if (operand_types[j].bitfield.disp64)
4008 {
4009 addr_prefix_disp = j;
4010 operand_types[j].bitfield.disp64 = 0;
4011 operand_types[j].bitfield.disp32 = 1;
4012 break;
4013 }
4014 }
539e75ad
L		 4015 break;
4016 }
539e75ad
L		 4017 }
4018
56ffb741
L		 4019 /* We check register size if needed. */
4020 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4021 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4022 switch (t->operands)
4023 {
4024 case 1:
40fb9820 4025 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4026 continue;
4027 break;
4028 case 2:
8b38ad71
L		 4029 /* xchg %eax, %eax is a special case. It is an aliase for nop
4030 only in 32bit mode and we can use opcode 0x90. In 64bit
4031 mode, we can't use 0x90 for xchg %eax, %eax since it should
4032 zero-extend %eax to %rax. */
4033 if (flag_code == CODE_64BIT
4034 && t->base_opcode == 0x90
0dfbf9d7
L		 4035 && operand_type_equal (&i.types [0], &acc32)
4036 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4037 continue;
b6169b20
L		 4038 if (i.swap_operand)
4039 {
4040 /* If we swap operand in encoding, we either match
4041 the next one or reverse direction of operands. */
4042 if (t->opcode_modifier.s)
4043 continue;
4044 else if (t->opcode_modifier.d)
4045 goto check_reverse;
4046 }
4047
29b0f896 4048 case 3:
fa99fab2
L		 4049 /* If we swap operand in encoding, we match the next one. */
4050 if (i.swap_operand && t->opcode_modifier.s)
4051 continue;
f48ff2ae 4052 case 4:
c0f3af97 4053 case 5:
c6fb90c8 4054 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4055 if (!operand_type_match (overlap0, i.types[0])
4056 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4057 || (check_register
4058 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4059 operand_types[0],
4060 overlap1, i.types[1],
4061 operand_types[1])))
29b0f896
AM		 4062 {
4063 /* Check if other direction is valid ... */
40fb9820 4064 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4065 continue;
4066
b6169b20 4067check_reverse:
29b0f896 4068 /* Try reversing direction of operands. */
c6fb90c8
L		 4069 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4070 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4071 if (!operand_type_match (overlap0, i.types[0])
4072 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4073 || (check_register
4074 && !operand_type_register_match (overlap0,
4075 i.types[0],
4076 operand_types[1],
4077 overlap1,
4078 i.types[1],
4079 operand_types[0])))
29b0f896
AM		 4080 {
4081 /* Does not match either direction. */
4082 continue;
4083 }
4084 /* found_reverse_match holds which of D or FloatDR
4085 we've found. */
40fb9820 4086 if (t->opcode_modifier.d)
8a2ed489 4087 found_reverse_match = Opcode_D;
40fb9820 4088 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4089 found_reverse_match = Opcode_FloatD;
4090 else
4091 found_reverse_match = 0;
40fb9820 4092 if (t->opcode_modifier.floatr)
8a2ed489 4093 found_reverse_match |= Opcode_FloatR;
29b0f896 4094 }
f48ff2ae 4095 else
29b0f896 4096 {
f48ff2ae 4097 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4098 switch (t->operands)
4099 {
c0f3af97
L		 4100 case 5:
4101 overlap4 = operand_type_and (i.types[4],
4102 operand_types[4]);
d1cbb4db 4103 case 4:
c6fb90c8
L		 4104 overlap3 = operand_type_and (i.types[3],
4105 operand_types[3]);
d1cbb4db 4106 case 3:
c6fb90c8
L		 4107 overlap2 = operand_type_and (i.types[2],
4108 operand_types[2]);
d1cbb4db
L		 4109 break;
4110 }
29b0f896 4111
f48ff2ae
L		 4112 switch (t->operands)
4113 {
c0f3af97
L		 4114 case 5:
4115 if (!operand_type_match (overlap4, i.types[4])
4116 || !operand_type_register_match (overlap3,
4117 i.types[3],
4118 operand_types[3],
4119 overlap4,
4120 i.types[4],
4121 operand_types[4]))
4122 continue;
f48ff2ae 4123 case 4:
40fb9820 4124 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4125 || (check_register
4126 && !operand_type_register_match (overlap2,
4127 i.types[2],
4128 operand_types[2],
4129 overlap3,
4130 i.types[3],
4131 operand_types[3])))
f48ff2ae
L		 4132 continue;
4133 case 3:
4134 /* Here we make use of the fact that there are no
4135 reverse match 3 operand instructions, and all 3
4136 operand instructions only need to be checked for
4137 register consistency between operands 2 and 3. */
40fb9820 4138 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4139 || (check_register
4140 && !operand_type_register_match (overlap1,
4141 i.types[1],
4142 operand_types[1],
4143 overlap2,
4144 i.types[2],
4145 operand_types[2])))
f48ff2ae
L		 4146 continue;
4147 break;
4148 }
29b0f896 4149 }
f48ff2ae 4150 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4151 slip through to break. */
4152 }
3629bb00 4153 if (!found_cpu_match)
29b0f896
AM		 4154 {
4155 found_reverse_match = 0;
4156 continue;
4157 }
c0f3af97 4158
a683cc34
SP		 4159 /* Check if VEX operands are valid. */
4160 if (VEX_check_operands (t))
4161 continue;
4162
29b0f896
AM		 4163 /* We've found a match; break out of loop. */
4164 break;
4165 }
4166
4167 if (t == current_templates->end)
4168 {
4169 /* We found no match. */
a65babc9
L		 4170 const char *err_msg;
4171 switch (i.error)
4172 {
4173 default:
4174 abort ();
86e026a4 4175 case operand_size_mismatch:
a65babc9
L		 4176 err_msg = _("operand size mismatch");
4177 break;
4178 case operand_type_mismatch:
4179 err_msg = _("operand type mismatch");
4180 break;
4181 case register_type_mismatch:
4182 err_msg = _("register type mismatch");
4183 break;
4184 case number_of_operands_mismatch:
4185 err_msg = _("number of operands mismatch");
4186 break;
4187 case invalid_instruction_suffix:
4188 err_msg = _("invalid instruction suffix");
4189 break;
4190 case bad_imm4:
4191 err_msg = _("Imm4 isn't the first operand");
4192 break;
4193 case old_gcc_only:
4194 err_msg = _("only supported with old gcc");
4195 break;
4196 case unsupported_with_intel_mnemonic:
4197 err_msg = _("unsupported with Intel mnemonic");
4198 break;
4199 case unsupported_syntax:
4200 err_msg = _("unsupported syntax");
4201 break;
4202 case unsupported:
4203 err_msg = _("unsupported");
4204 break;
4205 }
4206 as_bad (_("%s for `%s'"), err_msg,
891edac4 4207 current_templates->start->name);
fa99fab2 4208 return NULL;
29b0f896 4209 }
252b5132 4210
29b0f896
AM		 4211 if (!quiet_warnings)
4212 {
4213 if (!intel_syntax
40fb9820
L		 4214 && (i.types[0].bitfield.jumpabsolute
4215 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4216 {
4217 as_warn (_("indirect %s without `*'"), t->name);
4218 }
4219
40fb9820
L		 4220 if (t->opcode_modifier.isprefix
4221 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4222 {
4223 /* Warn them that a data or address size prefix doesn't
4224 affect assembly of the next line of code. */
4225 as_warn (_("stand-alone `%s' prefix"), t->name);
4226 }
4227 }
4228
4229 /* Copy the template we found. */
4230 i.tm = *t;
539e75ad
L		 4231
4232 if (addr_prefix_disp != -1)
4233 i.tm.operand_types[addr_prefix_disp]
4234 = operand_types[addr_prefix_disp];
4235
29b0f896
AM		 4236 if (found_reverse_match)
4237 {
4238 /* If we found a reverse match we must alter the opcode
4239 direction bit. found_reverse_match holds bits to change
4240 (different for int & float insns). */
4241
4242 i.tm.base_opcode ^= found_reverse_match;
4243
539e75ad
L		 4244 i.tm.operand_types[0] = operand_types[1];
4245 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4246 }
4247
fa99fab2 4248 return t;
29b0f896
AM		 4249}
4250
4251static int
e3bb37b5 4252check_string (void)
29b0f896 4253{
40fb9820
L		 4254 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4255 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4256 {
4257 if (i.seg[0] != NULL && i.seg[0] != &es)
4258 {
a87af027 4259 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4260 i.tm.name,
a87af027
JB		 4261 mem_op + 1,
4262 register_prefix);
29b0f896
AM		 4263 return 0;
4264 }
4265 /* There's only ever one segment override allowed per instruction.
4266 This instruction possibly has a legal segment override on the
4267 second operand, so copy the segment to where non-string
4268 instructions store it, allowing common code. */
4269 i.seg[0] = i.seg[1];
4270 }
40fb9820 4271 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4272 {
4273 if (i.seg[1] != NULL && i.seg[1] != &es)
4274 {
a87af027 4275 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4276 i.tm.name,
a87af027
JB		 4277 mem_op + 2,
4278 register_prefix);
29b0f896
AM		 4279 return 0;
4280 }
4281 }
4282 return 1;
4283}
4284
4285static int
543613e9 4286process_suffix (void)
29b0f896
AM		 4287{
4288 /* If matched instruction specifies an explicit instruction mnemonic
4289 suffix, use it. */
40fb9820
L		 4290 if (i.tm.opcode_modifier.size16)
4291 i.suffix = WORD_MNEM_SUFFIX;
4292 else if (i.tm.opcode_modifier.size32)
4293 i.suffix = LONG_MNEM_SUFFIX;
4294 else if (i.tm.opcode_modifier.size64)
4295 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4296 else if (i.reg_operands)
4297 {
4298 /* If there's no instruction mnemonic suffix we try to invent one
4299 based on register operands. */
4300 if (!i.suffix)
4301 {
4302 /* We take i.suffix from the last register operand specified,
4303 Destination register type is more significant than source
381d071f
L		 4304 register type. crc32 in SSE4.2 prefers source register
4305 type. */
4306 if (i.tm.base_opcode == 0xf20f38f1)
4307 {
40fb9820
L		 4308 if (i.types[0].bitfield.reg16)
4309 i.suffix = WORD_MNEM_SUFFIX;
4310 else if (i.types[0].bitfield.reg32)
4311 i.suffix = LONG_MNEM_SUFFIX;
4312 else if (i.types[0].bitfield.reg64)
4313 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4314 }
9344ff29 4315 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4316 {
40fb9820 4317 if (i.types[0].bitfield.reg8)
20592a94
L		 4318 i.suffix = BYTE_MNEM_SUFFIX;
4319 }
381d071f
L		 4320
4321 if (!i.suffix)
4322 {
4323 int op;
4324
20592a94
L		 4325 if (i.tm.base_opcode == 0xf20f38f1
4326 || i.tm.base_opcode == 0xf20f38f0)
4327 {
4328 /* We have to know the operand size for crc32. */
4329 as_bad (_("ambiguous memory operand size for `%s`"),
4330 i.tm.name);
4331 return 0;
4332 }
4333
381d071f 4334 for (op = i.operands; --op >= 0;)
40fb9820 4335 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4336 {
40fb9820
L		 4337 if (i.types[op].bitfield.reg8)
4338 {
4339 i.suffix = BYTE_MNEM_SUFFIX;
4340 break;
4341 }
4342 else if (i.types[op].bitfield.reg16)
4343 {
4344 i.suffix = WORD_MNEM_SUFFIX;
4345 break;
4346 }
4347 else if (i.types[op].bitfield.reg32)
4348 {
4349 i.suffix = LONG_MNEM_SUFFIX;
4350 break;
4351 }
4352 else if (i.types[op].bitfield.reg64)
4353 {
4354 i.suffix = QWORD_MNEM_SUFFIX;
4355 break;
4356 }
381d071f
L		 4357 }
4358 }
29b0f896
AM		 4359 }
4360 else if (i.suffix == BYTE_MNEM_SUFFIX)
4361 {
2eb952a4
L		 4362 if (intel_syntax
4363 && i.tm.opcode_modifier.ignoresize
4364 && i.tm.opcode_modifier.no_bsuf)
4365 i.suffix = 0;
4366 else if (!check_byte_reg ())
29b0f896
AM		 4367 return 0;
4368 }
4369 else if (i.suffix == LONG_MNEM_SUFFIX)
4370 {
2eb952a4
L		 4371 if (intel_syntax
4372 && i.tm.opcode_modifier.ignoresize
4373 && i.tm.opcode_modifier.no_lsuf)
4374 i.suffix = 0;
4375 else if (!check_long_reg ())
29b0f896
AM		 4376 return 0;
4377 }
4378 else if (i.suffix == QWORD_MNEM_SUFFIX)
4379 {
955e1e6a
L		 4380 if (intel_syntax
4381 && i.tm.opcode_modifier.ignoresize
4382 && i.tm.opcode_modifier.no_qsuf)
4383 i.suffix = 0;
4384 else if (!check_qword_reg ())
29b0f896
AM		 4385 return 0;
4386 }
4387 else if (i.suffix == WORD_MNEM_SUFFIX)
4388 {
2eb952a4
L		 4389 if (intel_syntax
4390 && i.tm.opcode_modifier.ignoresize
4391 && i.tm.opcode_modifier.no_wsuf)
4392 i.suffix = 0;
4393 else if (!check_word_reg ())
29b0f896
AM		 4394 return 0;
4395 }
c0f3af97
L		 4396 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4397 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4398 {
c0f3af97 4399 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4400 should check if it is a valid suffix. */
4401 }
40fb9820 4402 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4403 /* Do nothing if the instruction is going to ignore the prefix. */
4404 ;
4405 else
4406 abort ();
4407 }
40fb9820 4408 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4409 && !i.suffix
4410 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4411 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4412 {
4413 i.suffix = stackop_size;
4414 }
9306ca4a
JB		 4415 else if (intel_syntax
4416 && !i.suffix
40fb9820
L		 4417 && (i.tm.operand_types[0].bitfield.jumpabsolute
4418 || i.tm.opcode_modifier.jumpbyte
4419 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4420 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4421 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4422 {
4423 switch (flag_code)
4424 {
4425 case CODE_64BIT:
40fb9820 4426 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4427 {
4428 i.suffix = QWORD_MNEM_SUFFIX;
4429 break;
4430 }
4431 case CODE_32BIT:
40fb9820 4432 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4433 i.suffix = LONG_MNEM_SUFFIX;
4434 break;
4435 case CODE_16BIT:
40fb9820 4436 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4437 i.suffix = WORD_MNEM_SUFFIX;
4438 break;
4439 }
4440 }
252b5132 4441
9306ca4a 4442 if (!i.suffix)
29b0f896 4443 {
9306ca4a
JB		 4444 if (!intel_syntax)
4445 {
40fb9820 4446 if (i.tm.opcode_modifier.w)
9306ca4a 4447 {
4eed87de
AM		 4448 as_bad (_("no instruction mnemonic suffix given and "
4449 "no register operands; can't size instruction"));
9306ca4a
JB		 4450 return 0;
4451 }
4452 }
4453 else
4454 {
40fb9820 4455 unsigned int suffixes;
7ab9ffdd 4456
40fb9820
L		 4457 suffixes = !i.tm.opcode_modifier.no_bsuf;
4458 if (!i.tm.opcode_modifier.no_wsuf)
4459 suffixes |= 1 << 1;
4460 if (!i.tm.opcode_modifier.no_lsuf)
4461 suffixes |= 1 << 2;
fc4adea1 4462 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4463 suffixes |= 1 << 3;
4464 if (!i.tm.opcode_modifier.no_ssuf)
4465 suffixes |= 1 << 4;
4466 if (!i.tm.opcode_modifier.no_qsuf)
4467 suffixes |= 1 << 5;
4468
4469 /* There are more than suffix matches. */
4470 if (i.tm.opcode_modifier.w
9306ca4a 4471 || ((suffixes & (suffixes - 1))
40fb9820
L		 4472 && !i.tm.opcode_modifier.defaultsize
4473 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4474 {
4475 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4476 return 0;
4477 }
4478 }
29b0f896 4479 }
252b5132 4480
9306ca4a
JB		 4481 /* Change the opcode based on the operand size given by i.suffix;
4482 We don't need to change things for byte insns. */
4483
582d5edd
L		 4484 if (i.suffix
4485 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4486 && i.suffix != XMMWORD_MNEM_SUFFIX
4487 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4488 {
4489 /* It's not a byte, select word/dword operation. */
40fb9820 4490 if (i.tm.opcode_modifier.w)
29b0f896 4491 {
40fb9820 4492 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4493 i.tm.base_opcode |= 8;
4494 else
4495 i.tm.base_opcode |= 1;
4496 }
0f3f3d8b 4497
29b0f896
AM		 4498 /* Now select between word & dword operations via the operand
4499 size prefix, except for instructions that will ignore this
4500 prefix anyway. */
ca61edf2 4501 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4502 {
ca61edf2
L		 4503 /* The address size override prefix changes the size of the
4504 first operand. */
40fb9820
L		 4505 if ((flag_code == CODE_32BIT
4506 && i.op->regs[0].reg_type.bitfield.reg16)
4507 || (flag_code != CODE_32BIT
4508 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4509 if (!add_prefix (ADDR_PREFIX_OPCODE))
4510 return 0;
4511 }
4512 else if (i.suffix != QWORD_MNEM_SUFFIX
4513 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4514 && !i.tm.opcode_modifier.ignoresize
4515 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4516 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4517 || (flag_code == CODE_64BIT
40fb9820 4518 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4519 {
4520 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4521
40fb9820 4522 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4523 prefix = ADDR_PREFIX_OPCODE;
252b5132 4524
29b0f896
AM		 4525 if (!add_prefix (prefix))
4526 return 0;
24eab124 4527 }
252b5132 4528
29b0f896
AM		 4529 /* Set mode64 for an operand. */
4530 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4531 && flag_code == CODE_64BIT
40fb9820 4532 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4533 {
4534 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4535 need rex64. cmpxchg8b is also a special case. */
4536 if (! (i.operands == 2
4537 && i.tm.base_opcode == 0x90
4538 && i.tm.extension_opcode == None
0dfbf9d7
L		 4539 && operand_type_equal (&i.types [0], &acc64)
4540 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4541 && ! (i.operands == 1
4542 && i.tm.base_opcode == 0xfc7
4543 && i.tm.extension_opcode == 1
40fb9820
L		 4544 && !operand_type_check (i.types [0], reg)
4545 && operand_type_check (i.types [0], anymem)))
f6bee062 4546 i.rex |= REX_W;
46e883c5 4547 }
3e73aa7c 4548
29b0f896
AM		 4549 /* Size floating point instruction. */
4550 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4551 if (i.tm.opcode_modifier.floatmf)
543613e9 4552 i.tm.base_opcode ^= 4;
29b0f896 4553 }
7ecd2f8b 4554
29b0f896
AM		 4555 return 1;
4556}
3e73aa7c 4557
29b0f896 4558static int
543613e9 4559check_byte_reg (void)
29b0f896
AM		 4560{
4561 int op;
543613e9 4562
29b0f896
AM		 4563 for (op = i.operands; --op >= 0;)
4564 {
4565 /* If this is an eight bit register, it's OK. If it's the 16 or
4566 32 bit version of an eight bit register, we will just use the
4567 low portion, and that's OK too. */
40fb9820 4568 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4569 continue;
4570
9344ff29
L		 4571 /* crc32 doesn't generate this warning. */
4572 if (i.tm.base_opcode == 0xf20f38f0)
4573 continue;
4574
40fb9820
L		 4575 if ((i.types[op].bitfield.reg16
4576 || i.types[op].bitfield.reg32
4577 || i.types[op].bitfield.reg64)
4578 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4579 {
4580 /* Prohibit these changes in the 64bit mode, since the
4581 lowering is more complicated. */
4582 if (flag_code == CODE_64BIT
40fb9820 4583 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4584 {
2ca3ace5
L		 4585 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4586 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4587 i.suffix);
4588 return 0;
4589 }
4590#if REGISTER_WARNINGS
4591 if (!quiet_warnings
40fb9820 4592 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4593 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4594 register_prefix,
40fb9820 4595 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4596 ? REGNAM_AL - REGNAM_AX
4597 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4598 register_prefix,
29b0f896
AM		 4599 i.op[op].regs->reg_name,
4600 i.suffix);
4601#endif
4602 continue;
4603 }
4604 /* Any other register is bad. */
40fb9820
L		 4605 if (i.types[op].bitfield.reg16
4606 || i.types[op].bitfield.reg32
4607 || i.types[op].bitfield.reg64
4608 || i.types[op].bitfield.regmmx
4609 || i.types[op].bitfield.regxmm
c0f3af97 4610 || i.types[op].bitfield.regymm
40fb9820
L		 4611 || i.types[op].bitfield.sreg2
4612 || i.types[op].bitfield.sreg3
4613 || i.types[op].bitfield.control
4614 || i.types[op].bitfield.debug
4615 || i.types[op].bitfield.test
4616 || i.types[op].bitfield.floatreg
4617 || i.types[op].bitfield.floatacc)
29b0f896 4618 {
a540244d
L		 4619 as_bad (_("`%s%s' not allowed with `%s%c'"),
4620 register_prefix,
29b0f896
AM		 4621 i.op[op].regs->reg_name,
4622 i.tm.name,
4623 i.suffix);
4624 return 0;
4625 }
4626 }
4627 return 1;
4628}
4629
4630static int
e3bb37b5 4631check_long_reg (void)
29b0f896
AM		 4632{
4633 int op;
4634
4635 for (op = i.operands; --op >= 0;)
4636 /* Reject eight bit registers, except where the template requires
4637 them. (eg. movzb) */
40fb9820
L		 4638 if (i.types[op].bitfield.reg8
4639 && (i.tm.operand_types[op].bitfield.reg16
4640 || i.tm.operand_types[op].bitfield.reg32
4641 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4642 {
a540244d
L		 4643 as_bad (_("`%s%s' not allowed with `%s%c'"),
4644 register_prefix,
29b0f896
AM		 4645 i.op[op].regs->reg_name,
4646 i.tm.name,
4647 i.suffix);
4648 return 0;
4649 }
4650 /* Warn if the e prefix on a general reg is missing. */
4651 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4652 && i.types[op].bitfield.reg16
4653 && (i.tm.operand_types[op].bitfield.reg32
4654 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4655 {
4656 /* Prohibit these changes in the 64bit mode, since the
4657 lowering is more complicated. */
4658 if (flag_code == CODE_64BIT)
252b5132 4659 {
2ca3ace5
L		 4660 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4661 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4662 i.suffix);
4663 return 0;
252b5132 4664 }
29b0f896
AM		 4665#if REGISTER_WARNINGS
4666 else
a540244d
L		 4667 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4668 register_prefix,
29b0f896 4669 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4670 register_prefix,
29b0f896
AM		 4671 i.op[op].regs->reg_name,
4672 i.suffix);
4673#endif
252b5132 4674 }
29b0f896 4675 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4676 else if (i.types[op].bitfield.reg64
4677 && (i.tm.operand_types[op].bitfield.reg32
4678 || i.tm.operand_types[op].bitfield.acc))
252b5132 4679 {
34828aad 4680 if (intel_syntax
ca61edf2 4681 && i.tm.opcode_modifier.toqword
40fb9820 4682 && !i.types[0].bitfield.regxmm)
34828aad 4683 {
ca61edf2 4684 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4685 i.suffix = QWORD_MNEM_SUFFIX;
4686 }
4687 else
4688 {
4689 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4690 register_prefix, i.op[op].regs->reg_name,
4691 i.suffix);
4692 return 0;
4693 }
29b0f896
AM		 4694 }
4695 return 1;
4696}
252b5132 4697
29b0f896 4698static int
e3bb37b5 4699check_qword_reg (void)
29b0f896
AM		 4700{
4701 int op;
252b5132 4702
29b0f896
AM		 4703 for (op = i.operands; --op >= 0; )
4704 /* Reject eight bit registers, except where the template requires
4705 them. (eg. movzb) */
40fb9820
L		 4706 if (i.types[op].bitfield.reg8
4707 && (i.tm.operand_types[op].bitfield.reg16
4708 || i.tm.operand_types[op].bitfield.reg32
4709 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4710 {
a540244d
L		 4711 as_bad (_("`%s%s' not allowed with `%s%c'"),
4712 register_prefix,
29b0f896
AM		 4713 i.op[op].regs->reg_name,
4714 i.tm.name,
4715 i.suffix);
4716 return 0;
4717 }
4718 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4719 else if ((i.types[op].bitfield.reg16
4720 || i.types[op].bitfield.reg32)
4721 && (i.tm.operand_types[op].bitfield.reg32
4722 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4723 {
4724 /* Prohibit these changes in the 64bit mode, since the
4725 lowering is more complicated. */
34828aad 4726 if (intel_syntax
ca61edf2 4727 && i.tm.opcode_modifier.todword
40fb9820 4728 && !i.types[0].bitfield.regxmm)
34828aad 4729 {
ca61edf2 4730 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4731 i.suffix = LONG_MNEM_SUFFIX;
4732 }
4733 else
4734 {
4735 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4736 register_prefix, i.op[op].regs->reg_name,
4737 i.suffix);
4738 return 0;
4739 }
252b5132 4740 }
29b0f896
AM		 4741 return 1;
4742}
252b5132 4743
29b0f896 4744static int
e3bb37b5 4745check_word_reg (void)
29b0f896
AM		 4746{
4747 int op;
4748 for (op = i.operands; --op >= 0;)
4749 /* Reject eight bit registers, except where the template requires
4750 them. (eg. movzb) */
40fb9820
L		 4751 if (i.types[op].bitfield.reg8
4752 && (i.tm.operand_types[op].bitfield.reg16
4753 || i.tm.operand_types[op].bitfield.reg32
4754 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4755 {
a540244d
L		 4756 as_bad (_("`%s%s' not allowed with `%s%c'"),
4757 register_prefix,
29b0f896
AM		 4758 i.op[op].regs->reg_name,
4759 i.tm.name,
4760 i.suffix);
4761 return 0;
4762 }
4763 /* Warn if the e prefix on a general reg is present. */
4764 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4765 && i.types[op].bitfield.reg32
4766 && (i.tm.operand_types[op].bitfield.reg16
4767 || i.tm.operand_types[op].bitfield.acc))
252b5132 4768 {
29b0f896
AM		 4769 /* Prohibit these changes in the 64bit mode, since the
4770 lowering is more complicated. */
4771 if (flag_code == CODE_64BIT)
252b5132 4772 {
2ca3ace5
L		 4773 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4774 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4775 i.suffix);
4776 return 0;
252b5132 4777 }
29b0f896
AM		 4778 else
4779#if REGISTER_WARNINGS
a540244d
L		 4780 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4781 register_prefix,
29b0f896 4782 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4783 register_prefix,
29b0f896
AM		 4784 i.op[op].regs->reg_name,
4785 i.suffix);
4786#endif
4787 }
4788 return 1;
4789}
252b5132 4790
29b0f896 4791static int
40fb9820 4792update_imm (unsigned int j)
29b0f896 4793{
bc0844ae 4794 i386_operand_type overlap = i.types[j];
40fb9820
L		 4795 if ((overlap.bitfield.imm8
4796 || overlap.bitfield.imm8s
4797 || overlap.bitfield.imm16
4798 || overlap.bitfield.imm32
4799 || overlap.bitfield.imm32s
4800 || overlap.bitfield.imm64)
0dfbf9d7
L		 4801 && !operand_type_equal (&overlap, &imm8)
4802 && !operand_type_equal (&overlap, &imm8s)
4803 && !operand_type_equal (&overlap, &imm16)
4804 && !operand_type_equal (&overlap, &imm32)
4805 && !operand_type_equal (&overlap, &imm32s)
4806 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4807 {
4808 if (i.suffix)
4809 {
40fb9820
L		 4810 i386_operand_type temp;
4811
0dfbf9d7 4812 operand_type_set (&temp, 0);
7ab9ffdd 4813 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4814 {
4815 temp.bitfield.imm8 = overlap.bitfield.imm8;
4816 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4817 }
4818 else if (i.suffix == WORD_MNEM_SUFFIX)
4819 temp.bitfield.imm16 = overlap.bitfield.imm16;
4820 else if (i.suffix == QWORD_MNEM_SUFFIX)
4821 {
4822 temp.bitfield.imm64 = overlap.bitfield.imm64;
4823 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4824 }
4825 else
4826 temp.bitfield.imm32 = overlap.bitfield.imm32;
4827 overlap = temp;
29b0f896 4828 }
0dfbf9d7
L		 4829 else if (operand_type_equal (&overlap, &imm16_32_32s)
4830 || operand_type_equal (&overlap, &imm16_32)
4831 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4832 {
40fb9820 4833 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4834 overlap = imm16;
40fb9820 4835 else
65da13b5 4836 overlap = imm32s;
29b0f896 4837 }
0dfbf9d7
L		 4838 if (!operand_type_equal (&overlap, &imm8)
4839 && !operand_type_equal (&overlap, &imm8s)
4840 && !operand_type_equal (&overlap, &imm16)
4841 && !operand_type_equal (&overlap, &imm32)
4842 && !operand_type_equal (&overlap, &imm32s)
4843 && !operand_type_equal (&overlap, &imm64))
29b0f896 4844 {
4eed87de
AM		 4845 as_bad (_("no instruction mnemonic suffix given; "
4846 "can't determine immediate size"));
29b0f896
AM		 4847 return 0;
4848 }
4849 }
40fb9820 4850 i.types[j] = overlap;
29b0f896 4851
40fb9820
L		 4852 return 1;
4853}
4854
4855static int
4856finalize_imm (void)
4857{
bc0844ae 4858 unsigned int j, n;
29b0f896 4859
bc0844ae
L		 4860 /* Update the first 2 immediate operands. */
4861 n = i.operands > 2 ? 2 : i.operands;
4862 if (n)
4863 {
4864 for (j = 0; j < n; j++)
4865 if (update_imm (j) == 0)
4866 return 0;
40fb9820 4867
bc0844ae
L		 4868 /* The 3rd operand can't be immediate operand. */
4869 gas_assert (operand_type_check (i.types[2], imm) == 0);
4870 }
29b0f896
AM		 4871
4872 return 1;
4873}
4874
c0f3af97
L		 4875static int
4876bad_implicit_operand (int xmm)
4877{
91d6fa6a
NC		 4878 const char *ireg = xmm ? "xmm0" : "ymm0";
4879
c0f3af97
L		 4880 if (intel_syntax)
4881 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4882 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4883 else
4884 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4885 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4886 return 0;
4887}
4888
29b0f896 4889static int
e3bb37b5 4890process_operands (void)
29b0f896
AM		 4891{
4892 /* Default segment register this instruction will use for memory
4893 accesses. 0 means unknown. This is only for optimizing out
4894 unnecessary segment overrides. */
4895 const seg_entry *default_seg = 0;
4896
2426c15f 4897 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4898 {
91d6fa6a
NC		 4899 unsigned int dupl = i.operands;
4900 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4901 unsigned int j;
4902
c0f3af97 4903 /* The destination must be an xmm register. */
9c2799c2 4904 gas_assert (i.reg_operands
91d6fa6a 4905 && MAX_OPERANDS > dupl
7ab9ffdd 4906 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4907
4908 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4909 {
c0f3af97 4910 /* The first operand is implicit and must be xmm0. */
9c2799c2 4911 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4912 if (i.op[0].regs->reg_num != 0)
4913 return bad_implicit_operand (1);
4914
8cd7925b 4915 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4916 {
4917 /* Keep xmm0 for instructions with VEX prefix and 3
4918 sources. */
4919 goto duplicate;
4920 }
e2ec9d29 4921 else
c0f3af97
L		 4922 {
4923 /* We remove the first xmm0 and keep the number of
4924 operands unchanged, which in fact duplicates the
4925 destination. */
4926 for (j = 1; j < i.operands; j++)
4927 {
4928 i.op[j - 1] = i.op[j];
4929 i.types[j - 1] = i.types[j];
4930 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4931 }
4932 }
4933 }
4934 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4935 {
91d6fa6a 4936 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4937 && (i.tm.opcode_modifier.vexsources
4938 == VEX3SOURCES));
c0f3af97
L		 4939
4940 /* Add the implicit xmm0 for instructions with VEX prefix
4941 and 3 sources. */
4942 for (j = i.operands; j > 0; j--)
4943 {
4944 i.op[j] = i.op[j - 1];
4945 i.types[j] = i.types[j - 1];
4946 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4947 }
4948 i.op[0].regs
4949 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4950 i.types[0] = regxmm;
c0f3af97
L		 4951 i.tm.operand_types[0] = regxmm;
4952
4953 i.operands += 2;
4954 i.reg_operands += 2;
4955 i.tm.operands += 2;
4956
91d6fa6a 4957 dupl++;
c0f3af97 4958 dest++;
91d6fa6a
NC		 4959 i.op[dupl] = i.op[dest];
4960 i.types[dupl] = i.types[dest];
4961 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4962 }
c0f3af97
L		 4963 else
4964 {
4965duplicate:
4966 i.operands++;
4967 i.reg_operands++;
4968 i.tm.operands++;
4969
91d6fa6a
NC		 4970 i.op[dupl] = i.op[dest];
4971 i.types[dupl] = i.types[dest];
4972 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4973 }
4974
4975 if (i.tm.opcode_modifier.immext)
4976 process_immext ();
4977 }
4978 else if (i.tm.opcode_modifier.firstxmm0)
4979 {
4980 unsigned int j;
4981
4982 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4983 gas_assert (i.reg_operands
7ab9ffdd
L		 4984 && (operand_type_equal (&i.types[0], &regxmm)
4985 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4986 if (i.op[0].regs->reg_num != 0)
4987 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4988
4989 for (j = 1; j < i.operands; j++)
4990 {
4991 i.op[j - 1] = i.op[j];
4992 i.types[j - 1] = i.types[j];
4993
4994 /* We need to adjust fields in i.tm since they are used by
4995 build_modrm_byte. */
4996 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4997 }
4998
e2ec9d29
L		 4999 i.operands--;
5000 i.reg_operands--;
e2ec9d29
L		 5001 i.tm.operands--;
5002 }
5003 else if (i.tm.opcode_modifier.regkludge)
5004 {
5005 /* The imul $imm, %reg instruction is converted into
5006 imul $imm, %reg, %reg, and the clr %reg instruction
5007 is converted into xor %reg, %reg. */
5008
5009 unsigned int first_reg_op;
5010
5011 if (operand_type_check (i.types[0], reg))
5012 first_reg_op = 0;
5013 else
5014 first_reg_op = 1;
5015 /* Pretend we saw the extra register operand. */
9c2799c2 5016 gas_assert (i.reg_operands == 1
7ab9ffdd 5017 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5018 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5019 i.types[first_reg_op + 1] = i.types[first_reg_op];
5020 i.operands++;
5021 i.reg_operands++;
29b0f896
AM		 5022 }
5023
40fb9820 5024 if (i.tm.opcode_modifier.shortform)
29b0f896 5025 {
40fb9820
L		 5026 if (i.types[0].bitfield.sreg2
5027 || i.types[0].bitfield.sreg3)
29b0f896 5028 {
4eed87de
AM		 5029 if (i.tm.base_opcode == POP_SEG_SHORT
5030 && i.op[0].regs->reg_num == 1)
29b0f896 5031 {
a87af027 5032 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5033 return 0;
29b0f896 5034 }
4eed87de
AM		 5035 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5036 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5037 i.rex |= REX_B;
4eed87de
AM		 5038 }
5039 else
5040 {
7ab9ffdd 5041 /* The register or float register operand is in operand
85f10a01 5042 0 or 1. */
40fb9820 5043 unsigned int op;
7ab9ffdd
L		 5044
5045 if (i.types[0].bitfield.floatreg
5046 || operand_type_check (i.types[0], reg))
5047 op = 0;
5048 else
5049 op = 1;
4eed87de
AM		 5050 /* Register goes in low 3 bits of opcode. */
5051 i.tm.base_opcode |= i.op[op].regs->reg_num;
5052 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5053 i.rex |= REX_B;
40fb9820 5054 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5055 {
4eed87de
AM		 5056 /* Warn about some common errors, but press on regardless.
5057 The first case can be generated by gcc (<= 2.8.1). */
5058 if (i.operands == 2)
5059 {
5060 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5061 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5062 register_prefix, i.op[!intel_syntax].regs->reg_name,
5063 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5064 }
5065 else
5066 {
5067 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5068 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5069 register_prefix, i.op[0].regs->reg_name);
4eed87de 5070 }
29b0f896
AM		 5071 }
5072 }
5073 }
40fb9820 5074 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5075 {
5076 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5077 must be put into the modrm byte). Now, we make the modrm and
5078 index base bytes based on all the info we've collected. */
29b0f896
AM		 5079
5080 default_seg = build_modrm_byte ();
5081 }
8a2ed489 5082 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5083 {
5084 default_seg = &ds;
5085 }
40fb9820 5086 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5087 {
5088 /* For the string instructions that allow a segment override
5089 on one of their operands, the default segment is ds. */
5090 default_seg = &ds;
5091 }
5092
75178d9d
L		 5093 if (i.tm.base_opcode == 0x8d /* lea */
5094 && i.seg[0]
5095 && !quiet_warnings)
30123838 5096 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5097
5098 /* If a segment was explicitly specified, and the specified segment
5099 is not the default, use an opcode prefix to select it. If we
5100 never figured out what the default segment is, then default_seg
5101 will be zero at this point, and the specified segment prefix will
5102 always be used. */
29b0f896
AM		 5103 if ((i.seg[0]) && (i.seg[0] != default_seg))
5104 {
5105 if (!add_prefix (i.seg[0]->seg_prefix))
5106 return 0;
5107 }
5108 return 1;
5109}
5110
5111static const seg_entry *
e3bb37b5 5112build_modrm_byte (void)
29b0f896
AM		 5113{
5114 const seg_entry *default_seg = 0;
c0f3af97 5115 unsigned int source, dest;
8cd7925b 5116 int vex_3_sources;
c0f3af97
L		 5117
5118 /* The first operand of instructions with VEX prefix and 3 sources
5119 must be VEX_Imm4. */
8cd7925b 5120 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5121 if (vex_3_sources)
5122 {
91d6fa6a 5123 unsigned int nds, reg_slot;
4c2c6516 5124 expressionS *exp;
c0f3af97 5125
922d8de8 5126 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5127 && i.tm.opcode_modifier.immext)
5128 {
5129 dest = i.operands - 2;
5130 gas_assert (dest == 3);
5131 }
922d8de8 5132 else
a683cc34 5133 dest = i.operands - 1;
c0f3af97 5134 nds = dest - 1;
922d8de8 5135
a683cc34
SP		 5136 /* There are 2 kinds of instructions:
5137 1. 5 operands: 4 register operands or 3 register operands
5138 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5139 VexW0 or VexW1. The destination must be either XMM or YMM
5140 register.
5141 2. 4 operands: 4 register operands or 3 register operands
5142 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5143 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5144 || (i.reg_operands == 3 && i.mem_operands == 1))
5145 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5146 && (i.tm.opcode_modifier.veximmext
5147 || (i.imm_operands == 1
5148 && i.types[0].bitfield.vec_imm4
5149 && (i.tm.opcode_modifier.vexw == VEXW0
5150 || i.tm.opcode_modifier.vexw == VEXW1)
5151 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5152 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5153
5154 if (i.imm_operands == 0)
5155 {
5156 /* When there is no immediate operand, generate an 8bit
5157 immediate operand to encode the first operand. */
5158 exp = &im_expressions[i.imm_operands++];
5159 i.op[i.operands].imms = exp;
5160 i.types[i.operands] = imm8;
5161 i.operands++;
5162 /* If VexW1 is set, the first operand is the source and
5163 the second operand is encoded in the immediate operand. */
5164 if (i.tm.opcode_modifier.vexw == VEXW1)
5165 {
5166 source = 0;
5167 reg_slot = 1;
5168 }
5169 else
5170 {
5171 source = 1;
5172 reg_slot = 0;
5173 }
5174
5175 /* FMA swaps REG and NDS. */
5176 if (i.tm.cpu_flags.bitfield.cpufma)
5177 {
5178 unsigned int tmp;
5179 tmp = reg_slot;
5180 reg_slot = nds;
5181 nds = tmp;
5182 }
5183
24981e7b
L		 5184 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5185 &regxmm)
a683cc34
SP		 5186 || operand_type_equal (&i.tm.operand_types[reg_slot],
5187 &regymm));
5188 exp->X_op = O_constant;
5189 exp->X_add_number
5190 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5191 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5192 << 4);
a683cc34 5193 }
922d8de8 5194 else
a683cc34
SP		 5195 {
5196 unsigned int imm_slot;
5197
5198 if (i.tm.opcode_modifier.vexw == VEXW0)
5199 {
5200 /* If VexW0 is set, the third operand is the source and
5201 the second operand is encoded in the immediate
5202 operand. */
5203 source = 2;
5204 reg_slot = 1;
5205 }
5206 else
5207 {
5208 /* VexW1 is set, the second operand is the source and
5209 the third operand is encoded in the immediate
5210 operand. */
5211 source = 1;
5212 reg_slot = 2;
5213 }
5214
5215 if (i.tm.opcode_modifier.immext)
5216 {
5217 /* When ImmExt is set, the immdiate byte is the last
5218 operand. */
5219 imm_slot = i.operands - 1;
5220 source--;
5221 reg_slot--;
5222 }
5223 else
5224 {
5225 imm_slot = 0;
5226
5227 /* Turn on Imm8 so that output_imm will generate it. */
5228 i.types[imm_slot].bitfield.imm8 = 1;
5229 }
5230
24981e7b
L		 5231 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5232 &regxmm)
5233 || operand_type_equal (&i.tm.operand_types[reg_slot],
5234 &regymm));
a683cc34
SP		 5235 i.op[imm_slot].imms->X_add_number
5236 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5237 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5238 << 4);
a683cc34
SP		 5239 }
5240
5241 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5242 || operand_type_equal (&i.tm.operand_types[nds],
5243 &regymm));
dae39acc 5244 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5245 }
5246 else
5247 source = dest = 0;
29b0f896
AM		 5248
5249 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5250 implicit registers do not count. If there are 3 register
5251 operands, it must be a instruction with VexNDS. For a
5252 instruction with VexNDD, the destination register is encoded
5253 in VEX prefix. If there are 4 register operands, it must be
5254 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5255 if (i.mem_operands == 0
5256 && ((i.reg_operands == 2
2426c15f 5257 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5258 || (i.reg_operands == 3
2426c15f 5259 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5260 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5261 {
cab737b9
L		 5262 switch (i.operands)
5263 {
5264 case 2:
5265 source = 0;
5266 break;
5267 case 3:
c81128dc
L		 5268 /* When there are 3 operands, one of them may be immediate,
5269 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5270 the first operand must be shift count register (cl) or it
5271 is an instruction with VexNDS. */
9c2799c2 5272 gas_assert (i.imm_operands == 1
7ab9ffdd 5273 || (i.imm_operands == 0
2426c15f 5274 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5275 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5276 if (operand_type_check (i.types[0], imm)
5277 || i.types[0].bitfield.shiftcount)
5278 source = 1;
5279 else
5280 source = 0;
cab737b9
L		 5281 break;
5282 case 4:
368d64cc
L		 5283 /* When there are 4 operands, the first two must be 8bit
5284 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5285 one.
5286
5287 For instructions with VexNDS, if the first operand
5288 an imm8, the source operand is the 2nd one. If the last
5289 operand is imm8, the source operand is the first one. */
9c2799c2 5290 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5291 && i.types[0].bitfield.imm8
5292 && i.types[1].bitfield.imm8)
2426c15f 5293 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5294 && i.imm_operands == 1
5295 && (i.types[0].bitfield.imm8
5296 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5297 if (i.imm_operands == 2)
5298 source = 2;
5299 else
c0f3af97
L		 5300 {
5301 if (i.types[0].bitfield.imm8)
5302 source = 1;
5303 else
5304 source = 0;
5305 }
c0f3af97
L		 5306 break;
5307 case 5:
cab737b9
L		 5308 break;
5309 default:
5310 abort ();
5311 }
5312
c0f3af97
L		 5313 if (!vex_3_sources)
5314 {
5315 dest = source + 1;
5316
2426c15f 5317 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5318 {
5319 /* For instructions with VexNDS, the register-only
f12dc422
L		 5320 source operand must be 32/64bit integer, XMM or
5321 YMM register. It is encoded in VEX prefix. We
5322 need to clear RegMem bit before calling
5323 operand_type_equal. */
5324
5325 i386_operand_type op;
5326 unsigned int vvvv;
5327
5328 /* Check register-only source operand when two source
5329 operands are swapped. */
5330 if (!i.tm.operand_types[source].bitfield.baseindex
5331 && i.tm.operand_types[dest].bitfield.baseindex)
5332 {
5333 vvvv = source;
5334 source = dest;
5335 }
5336 else
5337 vvvv = dest;
5338
5339 op = i.tm.operand_types[vvvv];
fa99fab2 5340 op.bitfield.regmem = 0;
c0f3af97 5341 if ((dest + 1) >= i.operands
f12dc422
L		 5342 || (op.bitfield.reg32 != 1
5343 && !op.bitfield.reg64 != 1
5344 && !operand_type_equal (&op, &regxmm)
fa99fab2 5345 && !operand_type_equal (&op, &regymm)))
c0f3af97 5346 abort ();
f12dc422 5347 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5348 dest++;
5349 }
5350 }
29b0f896
AM		 5351
5352 i.rm.mode = 3;
5353 /* One of the register operands will be encoded in the i.tm.reg
5354 field, the other in the combined i.tm.mode and i.tm.regmem
5355 fields. If no form of this instruction supports a memory
5356 destination operand, then we assume the source operand may
5357 sometimes be a memory operand and so we need to store the
5358 destination in the i.rm.reg field. */
40fb9820
L		 5359 if (!i.tm.operand_types[dest].bitfield.regmem
5360 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5361 {
5362 i.rm.reg = i.op[dest].regs->reg_num;
5363 i.rm.regmem = i.op[source].regs->reg_num;
5364 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5365 i.rex |= REX_R;
29b0f896 5366 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5367 i.rex |= REX_B;
29b0f896
AM		 5368 }
5369 else
5370 {
5371 i.rm.reg = i.op[source].regs->reg_num;
5372 i.rm.regmem = i.op[dest].regs->reg_num;
5373 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5374 i.rex |= REX_B;
29b0f896 5375 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5376 i.rex |= REX_R;
29b0f896 5377 }
161a04f6 5378 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5379 {
40fb9820
L		 5380 if (!i.types[0].bitfield.control
5381 && !i.types[1].bitfield.control)
c4a530c5 5382 abort ();
161a04f6 5383 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5384 add_prefix (LOCK_PREFIX_OPCODE);
5385 }
29b0f896
AM		 5386 }
5387 else
5388 { /* If it's not 2 reg operands... */
c0f3af97
L		 5389 unsigned int mem;
5390
29b0f896
AM		 5391 if (i.mem_operands)
5392 {
5393 unsigned int fake_zero_displacement = 0;
99018f42 5394 unsigned int op;
4eed87de 5395
7ab9ffdd
L		 5396 for (op = 0; op < i.operands; op++)
5397 if (operand_type_check (i.types[op], anymem))
5398 break;
7ab9ffdd 5399 gas_assert (op < i.operands);
29b0f896
AM		 5400
5401 default_seg = &ds;
5402
5403 if (i.base_reg == 0)
5404 {
5405 i.rm.mode = 0;
5406 if (!i.disp_operands)
5407 fake_zero_displacement = 1;
5408 if (i.index_reg == 0)
5409 {
5410 /* Operand is just <disp> */
20f0a1fc 5411 if (flag_code == CODE_64BIT)
29b0f896
AM		 5412 {
5413 /* 64bit mode overwrites the 32bit absolute
5414 addressing by RIP relative addressing and
5415 absolute addressing is encoded by one of the
5416 redundant SIB forms. */
5417 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5418 i.sib.base = NO_BASE_REGISTER;
5419 i.sib.index = NO_INDEX_REGISTER;
fc225355 5420 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5421 ? disp32s : disp32);
20f0a1fc 5422 }
fc225355
L		 5423 else if ((flag_code == CODE_16BIT)
5424 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5425 {
5426 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5427 i.types[op] = disp16;
20f0a1fc
NC		 5428 }
5429 else
5430 {
5431 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5432 i.types[op] = disp32;
29b0f896
AM		 5433 }
5434 }
5435 else /* !i.base_reg && i.index_reg */
5436 {
db51cc60
L		 5437 if (i.index_reg->reg_num == RegEiz
5438 || i.index_reg->reg_num == RegRiz)
5439 i.sib.index = NO_INDEX_REGISTER;
5440 else
5441 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5442 i.sib.base = NO_BASE_REGISTER;
5443 i.sib.scale = i.log2_scale_factor;
5444 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5445 i.types[op].bitfield.disp8 = 0;
5446 i.types[op].bitfield.disp16 = 0;
5447 i.types[op].bitfield.disp64 = 0;
29b0f896 5448 if (flag_code != CODE_64BIT)
40fb9820
L		 5449 {
5450 /* Must be 32 bit */
5451 i.types[op].bitfield.disp32 = 1;
5452 i.types[op].bitfield.disp32s = 0;
5453 }
29b0f896 5454 else
40fb9820
L		 5455 {
5456 i.types[op].bitfield.disp32 = 0;
5457 i.types[op].bitfield.disp32s = 1;
5458 }
29b0f896 5459 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5460 i.rex |= REX_X;
29b0f896
AM		 5461 }
5462 }
5463 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5464 else if (i.base_reg->reg_num == RegRip ||
5465 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5466 {
5467 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5468 i.types[op].bitfield.disp8 = 0;
5469 i.types[op].bitfield.disp16 = 0;
5470 i.types[op].bitfield.disp32 = 0;
5471 i.types[op].bitfield.disp32s = 1;
5472 i.types[op].bitfield.disp64 = 0;
71903a11 5473 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5474 if (! i.disp_operands)
5475 fake_zero_displacement = 1;
29b0f896 5476 }
40fb9820 5477 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5478 {
5479 switch (i.base_reg->reg_num)
5480 {
5481 case 3: /* (%bx) */
5482 if (i.index_reg == 0)
5483 i.rm.regmem = 7;
5484 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5485 i.rm.regmem = i.index_reg->reg_num - 6;
5486 break;
5487 case 5: /* (%bp) */
5488 default_seg = &ss;
5489 if (i.index_reg == 0)
5490 {
5491 i.rm.regmem = 6;
40fb9820 5492 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5493 {
5494 /* fake (%bp) into 0(%bp) */
40fb9820 5495 i.types[op].bitfield.disp8 = 1;
252b5132 5496 fake_zero_displacement = 1;
29b0f896
AM		 5497 }
5498 }
5499 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5500 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5501 break;
5502 default: /* (%si) -> 4 or (%di) -> 5 */
5503 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5504 }
5505 i.rm.mode = mode_from_disp_size (i.types[op]);
5506 }
5507 else /* i.base_reg and 32/64 bit mode */
5508 {
5509 if (flag_code == CODE_64BIT
40fb9820
L		 5510 && operand_type_check (i.types[op], disp))
5511 {
5512 i386_operand_type temp;
0dfbf9d7 5513 operand_type_set (&temp, 0);
40fb9820
L		 5514 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5515 i.types[op] = temp;
5516 if (i.prefix[ADDR_PREFIX] == 0)
5517 i.types[op].bitfield.disp32s = 1;
5518 else
5519 i.types[op].bitfield.disp32 = 1;
5520 }
20f0a1fc 5521
29b0f896
AM		 5522 i.rm.regmem = i.base_reg->reg_num;
5523 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5524 i.rex |= REX_B;
29b0f896
AM		 5525 i.sib.base = i.base_reg->reg_num;
5526 /* x86-64 ignores REX prefix bit here to avoid decoder
5527 complications. */
5528 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5529 {
5530 default_seg = &ss;
5531 if (i.disp_operands == 0)
5532 {
5533 fake_zero_displacement = 1;
40fb9820 5534 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5535 }
5536 }
5537 else if (i.base_reg->reg_num == ESP_REG_NUM)
5538 {
5539 default_seg = &ss;
5540 }
5541 i.sib.scale = i.log2_scale_factor;
5542 if (i.index_reg == 0)
5543 {
5544 /* <disp>(%esp) becomes two byte modrm with no index
5545 register. We've already stored the code for esp
5546 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5547 Any base register besides %esp will not use the
5548 extra modrm byte. */
5549 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5550 }
5551 else
5552 {
db51cc60
L		 5553 if (i.index_reg->reg_num == RegEiz
5554 || i.index_reg->reg_num == RegRiz)
5555 i.sib.index = NO_INDEX_REGISTER;
5556 else
5557 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5558 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5559 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5560 i.rex |= REX_X;
29b0f896 5561 }
67a4f2b7
AO		 5562
5563 if (i.disp_operands
5564 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5565 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5566 i.rm.mode = 0;
5567 else
5568 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5569 }
252b5132 5570
29b0f896
AM		 5571 if (fake_zero_displacement)
5572 {
5573 /* Fakes a zero displacement assuming that i.types[op]
5574 holds the correct displacement size. */
5575 expressionS *exp;
5576
9c2799c2 5577 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5578 exp = &disp_expressions[i.disp_operands++];
5579 i.op[op].disps = exp;
5580 exp->X_op = O_constant;
5581 exp->X_add_number = 0;
5582 exp->X_add_symbol = (symbolS *) 0;
5583 exp->X_op_symbol = (symbolS *) 0;
5584 }
c0f3af97
L		 5585
5586 mem = op;
29b0f896 5587 }
c0f3af97
L		 5588 else
5589 mem = ~0;
252b5132 5590
8c43a48b 5591 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5592 {
5593 if (operand_type_check (i.types[0], imm))
5594 i.vex.register_specifier = NULL;
5595 else
5596 {
5597 /* VEX.vvvv encodes one of the sources when the first
5598 operand is not an immediate. */
1ef99a7b 5599 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5600 i.vex.register_specifier = i.op[0].regs;
5601 else
5602 i.vex.register_specifier = i.op[1].regs;
5603 }
5604
5605 /* Destination is a XMM register encoded in the ModRM.reg
5606 and VEX.R bit. */
5607 i.rm.reg = i.op[2].regs->reg_num;
5608 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5609 i.rex |= REX_R;
5610
5611 /* ModRM.rm and VEX.B encodes the other source. */
5612 if (!i.mem_operands)
5613 {
5614 i.rm.mode = 3;
5615
1ef99a7b 5616 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5617 i.rm.regmem = i.op[1].regs->reg_num;
5618 else
5619 i.rm.regmem = i.op[0].regs->reg_num;
5620
5621 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5622 i.rex |= REX_B;
5623 }
5624 }
2426c15f 5625 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5626 {
5627 i.vex.register_specifier = i.op[2].regs;
5628 if (!i.mem_operands)
5629 {
5630 i.rm.mode = 3;
5631 i.rm.regmem = i.op[1].regs->reg_num;
5632 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5633 i.rex |= REX_B;
5634 }
5635 }
29b0f896
AM		 5636 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5637 (if any) based on i.tm.extension_opcode. Again, we must be
5638 careful to make sure that segment/control/debug/test/MMX
5639 registers are coded into the i.rm.reg field. */
f88c9eb0 5640 else if (i.reg_operands)
29b0f896 5641 {
99018f42 5642 unsigned int op;
7ab9ffdd
L		 5643 unsigned int vex_reg = ~0;
5644
5645 for (op = 0; op < i.operands; op++)
5646 if (i.types[op].bitfield.reg8
5647 || i.types[op].bitfield.reg16
5648 || i.types[op].bitfield.reg32
5649 || i.types[op].bitfield.reg64
5650 || i.types[op].bitfield.regmmx
5651 || i.types[op].bitfield.regxmm
5652 || i.types[op].bitfield.regymm
5653 || i.types[op].bitfield.sreg2
5654 || i.types[op].bitfield.sreg3
5655 || i.types[op].bitfield.control
5656 || i.types[op].bitfield.debug
5657 || i.types[op].bitfield.test)
5658 break;
c0209578 5659
7ab9ffdd
L		 5660 if (vex_3_sources)
5661 op = dest;
2426c15f 5662 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5663 {
5664 /* For instructions with VexNDS, the register-only
5665 source operand is encoded in VEX prefix. */
5666 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5667
7ab9ffdd 5668 if (op > mem)
c0f3af97 5669 {
7ab9ffdd
L		 5670 vex_reg = op++;
5671 gas_assert (op < i.operands);
c0f3af97
L		 5672 }
5673 else
c0f3af97 5674 {
f12dc422
L		 5675 /* Check register-only source operand when two source
5676 operands are swapped. */
5677 if (!i.tm.operand_types[op].bitfield.baseindex
5678 && i.tm.operand_types[op + 1].bitfield.baseindex)
5679 {
5680 vex_reg = op;
5681 op += 2;
5682 gas_assert (mem == (vex_reg + 1)
5683 && op < i.operands);
5684 }
5685 else
5686 {
5687 vex_reg = op + 1;
5688 gas_assert (vex_reg < i.operands);
5689 }
c0f3af97 5690 }
7ab9ffdd 5691 }
2426c15f 5692 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5693 {
f12dc422 5694 /* For instructions with VexNDD, the register destination
7ab9ffdd 5695 is encoded in VEX prefix. */
f12dc422
L		 5696 if (i.mem_operands == 0)
5697 {
5698 /* There is no memory operand. */
5699 gas_assert ((op + 2) == i.operands);
5700 vex_reg = op + 1;
5701 }
5702 else
5703 {
5704 /* There are only 2 operands. */
5705 gas_assert (op < 2 && i.operands == 2);
5706 vex_reg = 1;
5707 }
7ab9ffdd
L		 5708 }
5709 else
5710 gas_assert (op < i.operands);
99018f42 5711
7ab9ffdd
L		 5712 if (vex_reg != (unsigned int) ~0)
5713 {
f12dc422 5714 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5715
f12dc422
L		 5716 if (type->bitfield.reg32 != 1
5717 && type->bitfield.reg64 != 1
5718 && !operand_type_equal (type, &regxmm)
5719 && !operand_type_equal (type, &regymm))
7ab9ffdd 5720 abort ();
f88c9eb0 5721
7ab9ffdd
L		 5722 i.vex.register_specifier = i.op[vex_reg].regs;
5723 }
5724
1b9f0c97
L		 5725 /* Don't set OP operand twice. */
5726 if (vex_reg != op)
7ab9ffdd 5727 {
1b9f0c97
L		 5728 /* If there is an extension opcode to put here, the
5729 register number must be put into the regmem field. */
5730 if (i.tm.extension_opcode != None)
5731 {
5732 i.rm.regmem = i.op[op].regs->reg_num;
5733 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5734 i.rex |= REX_B;
5735 }
5736 else
5737 {
5738 i.rm.reg = i.op[op].regs->reg_num;
5739 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5740 i.rex |= REX_R;
5741 }
7ab9ffdd 5742 }
252b5132 5743
29b0f896
AM		 5744 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5745 must set it to 3 to indicate this is a register operand
5746 in the regmem field. */
5747 if (!i.mem_operands)
5748 i.rm.mode = 3;
5749 }
252b5132 5750
29b0f896 5751 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5752 if (i.tm.extension_opcode != None)
29b0f896
AM		 5753 i.rm.reg = i.tm.extension_opcode;
5754 }
5755 return default_seg;
5756}
252b5132 5757
29b0f896 5758static void
e3bb37b5 5759output_branch (void)
29b0f896
AM		 5760{
5761 char *p;
f8a5c266 5762 int size;
29b0f896
AM		 5763 int code16;
5764 int prefix;
5765 relax_substateT subtype;
5766 symbolS *sym;
5767 offsetT off;
5768
f8a5c266
L		 5769 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5770 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5771
5772 prefix = 0;
5773 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5774 {
29b0f896
AM		 5775 prefix = 1;
5776 i.prefixes -= 1;
5777 code16 ^= CODE16;
252b5132 5778 }
29b0f896
AM		 5779 /* Pentium4 branch hints. */
5780 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5781 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5782 {
29b0f896
AM		 5783 prefix++;
5784 i.prefixes--;
5785 }
5786 if (i.prefix[REX_PREFIX] != 0)
5787 {
5788 prefix++;
5789 i.prefixes--;
2f66722d
AM		 5790 }
5791
29b0f896
AM		 5792 if (i.prefixes != 0 && !intel_syntax)
5793 as_warn (_("skipping prefixes on this instruction"));
5794
5795 /* It's always a symbol; End frag & setup for relax.
5796 Make sure there is enough room in this frag for the largest
5797 instruction we may generate in md_convert_frag. This is 2
5798 bytes for the opcode and room for the prefix and largest
5799 displacement. */
5800 frag_grow (prefix + 2 + 4);
5801 /* Prefix and 1 opcode byte go in fr_fix. */
5802 p = frag_more (prefix + 1);
5803 if (i.prefix[DATA_PREFIX] != 0)
5804 *p++ = DATA_PREFIX_OPCODE;
5805 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5806 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5807 *p++ = i.prefix[SEG_PREFIX];
5808 if (i.prefix[REX_PREFIX] != 0)
5809 *p++ = i.prefix[REX_PREFIX];
5810 *p = i.tm.base_opcode;
5811
5812 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5813 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5814 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5815 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5816 else
f8a5c266 5817 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5818 subtype |= code16;
3e73aa7c 5819
29b0f896
AM		 5820 sym = i.op[0].disps->X_add_symbol;
5821 off = i.op[0].disps->X_add_number;
3e73aa7c 5822
29b0f896
AM		 5823 if (i.op[0].disps->X_op != O_constant
5824 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5825 {
29b0f896
AM		 5826 /* Handle complex expressions. */
5827 sym = make_expr_symbol (i.op[0].disps);
5828 off = 0;
5829 }
3e73aa7c 5830
29b0f896
AM		 5831 /* 1 possible extra opcode + 4 byte displacement go in var part.
5832 Pass reloc in fr_var. */
5833 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5834}
3e73aa7c 5835
29b0f896 5836static void
e3bb37b5 5837output_jump (void)
29b0f896
AM		 5838{
5839 char *p;
5840 int size;
3e02c1cc 5841 fixS *fixP;
29b0f896 5842
40fb9820 5843 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5844 {
5845 /* This is a loop or jecxz type instruction. */
5846 size = 1;
5847 if (i.prefix[ADDR_PREFIX] != 0)
5848 {
5849 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5850 i.prefixes -= 1;
5851 }
5852 /* Pentium4 branch hints. */
5853 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5854 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5855 {
5856 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5857 i.prefixes--;
3e73aa7c
JH		 5858 }
5859 }
29b0f896
AM		 5860 else
5861 {
5862 int code16;
3e73aa7c 5863
29b0f896
AM		 5864 code16 = 0;
5865 if (flag_code == CODE_16BIT)
5866 code16 = CODE16;
3e73aa7c 5867
29b0f896
AM		 5868 if (i.prefix[DATA_PREFIX] != 0)
5869 {
5870 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5871 i.prefixes -= 1;
5872 code16 ^= CODE16;
5873 }
252b5132 5874
29b0f896
AM		 5875 size = 4;
5876 if (code16)
5877 size = 2;
5878 }
9fcc94b6 5879
29b0f896
AM		 5880 if (i.prefix[REX_PREFIX] != 0)
5881 {
5882 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5883 i.prefixes -= 1;
5884 }
252b5132 5885
29b0f896
AM		 5886 if (i.prefixes != 0 && !intel_syntax)
5887 as_warn (_("skipping prefixes on this instruction"));
e0890092 5888
29b0f896
AM		 5889 p = frag_more (1 + size);
5890 *p++ = i.tm.base_opcode;
e0890092 5891
3e02c1cc
AM		 5892 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5893 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5894
5895 /* All jumps handled here are signed, but don't use a signed limit
5896 check for 32 and 16 bit jumps as we want to allow wrap around at
5897 4G and 64k respectively. */
5898 if (size == 1)
5899 fixP->fx_signed = 1;
29b0f896 5900}
e0890092 5901
29b0f896 5902static void
e3bb37b5 5903output_interseg_jump (void)
29b0f896
AM		 5904{
5905 char *p;
5906 int size;
5907 int prefix;
5908 int code16;
252b5132 5909
29b0f896
AM		 5910 code16 = 0;
5911 if (flag_code == CODE_16BIT)
5912 code16 = CODE16;
a217f122 5913
29b0f896
AM		 5914 prefix = 0;
5915 if (i.prefix[DATA_PREFIX] != 0)
5916 {
5917 prefix = 1;
5918 i.prefixes -= 1;
5919 code16 ^= CODE16;
5920 }
5921 if (i.prefix[REX_PREFIX] != 0)
5922 {
5923 prefix++;
5924 i.prefixes -= 1;
5925 }
252b5132 5926
29b0f896
AM		 5927 size = 4;
5928 if (code16)
5929 size = 2;
252b5132 5930
29b0f896
AM		 5931 if (i.prefixes != 0 && !intel_syntax)
5932 as_warn (_("skipping prefixes on this instruction"));
252b5132 5933
29b0f896
AM		 5934 /* 1 opcode; 2 segment; offset */
5935 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5936
29b0f896
AM		 5937 if (i.prefix[DATA_PREFIX] != 0)
5938 *p++ = DATA_PREFIX_OPCODE;
252b5132 5939
29b0f896
AM		 5940 if (i.prefix[REX_PREFIX] != 0)
5941 *p++ = i.prefix[REX_PREFIX];
252b5132 5942
29b0f896
AM		 5943 *p++ = i.tm.base_opcode;
5944 if (i.op[1].imms->X_op == O_constant)
5945 {
5946 offsetT n = i.op[1].imms->X_add_number;
252b5132 5947
29b0f896
AM		 5948 if (size == 2
5949 && !fits_in_unsigned_word (n)
5950 && !fits_in_signed_word (n))
5951 {
5952 as_bad (_("16-bit jump out of range"));
5953 return;
5954 }
5955 md_number_to_chars (p, n, size);
5956 }
5957 else
5958 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5959 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5960 if (i.op[0].imms->X_op != O_constant)
5961 as_bad (_("can't handle non absolute segment in `%s'"),
5962 i.tm.name);
5963 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5964}
a217f122 5965
29b0f896 5966static void
e3bb37b5 5967output_insn (void)
29b0f896 5968{
2bbd9c25
JJ		 5969 fragS *insn_start_frag;
5970 offsetT insn_start_off;
5971
29b0f896
AM		 5972 /* Tie dwarf2 debug info to the address at the start of the insn.
5973 We can't do this after the insn has been output as the current
5974 frag may have been closed off. eg. by frag_var. */
5975 dwarf2_emit_insn (0);
5976
2bbd9c25
JJ		 5977 insn_start_frag = frag_now;
5978 insn_start_off = frag_now_fix ();
5979
29b0f896 5980 /* Output jumps. */
40fb9820 5981 if (i.tm.opcode_modifier.jump)
29b0f896 5982 output_branch ();
40fb9820
L		 5983 else if (i.tm.opcode_modifier.jumpbyte
5984 || i.tm.opcode_modifier.jumpdword)
29b0f896 5985 output_jump ();
40fb9820 5986 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5987 output_interseg_jump ();
5988 else
5989 {
5990 /* Output normal instructions here. */
5991 char *p;
5992 unsigned char *q;
47465058 5993 unsigned int j;
331d2d0d 5994 unsigned int prefix;
4dffcebc 5995
c0f3af97
L		 5996 /* Since the VEX prefix contains the implicit prefix, we don't
5997 need the explicit prefix. */
5998 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5999 {
c0f3af97 6000 switch (i.tm.opcode_length)
bc4bd9ab 6001 {
c0f3af97
L		 6002 case 3:
6003 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6004 {
c0f3af97
L		 6005 prefix = (i.tm.base_opcode >> 24) & 0xff;
6006 goto check_prefix;
6007 }
6008 break;
6009 case 2:
6010 if ((i.tm.base_opcode & 0xff0000) != 0)
6011 {
6012 prefix = (i.tm.base_opcode >> 16) & 0xff;
6013 if (i.tm.cpu_flags.bitfield.cpupadlock)
6014 {
4dffcebc 6015check_prefix:
c0f3af97 6016 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6017 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6018 != REPE_PREFIX_OPCODE))
6019 add_prefix (prefix);
6020 }
6021 else
4dffcebc
L		 6022 add_prefix (prefix);
6023 }
c0f3af97
L		 6024 break;
6025 case 1:
6026 break;
6027 default:
6028 abort ();
bc4bd9ab 6029 }
c0f3af97
L		 6030
6031 /* The prefix bytes. */
6032 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6033 if (*q)
6034 FRAG_APPEND_1_CHAR (*q);
0f10071e 6035 }
252b5132 6036
c0f3af97
L		 6037 if (i.tm.opcode_modifier.vex)
6038 {
6039 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6040 if (*q)
6041 switch (j)
6042 {
6043 case REX_PREFIX:
6044 /* REX byte is encoded in VEX prefix. */
6045 break;
6046 case SEG_PREFIX:
6047 case ADDR_PREFIX:
6048 FRAG_APPEND_1_CHAR (*q);
6049 break;
6050 default:
6051 /* There should be no other prefixes for instructions
6052 with VEX prefix. */
6053 abort ();
6054 }
6055
6056 /* Now the VEX prefix. */
6057 p = frag_more (i.vex.length);
6058 for (j = 0; j < i.vex.length; j++)
6059 p[j] = i.vex.bytes[j];
6060 }
252b5132 6061
29b0f896 6062 /* Now the opcode; be careful about word order here! */
4dffcebc 6063 if (i.tm.opcode_length == 1)
29b0f896
AM		 6064 {
6065 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6066 }
6067 else
6068 {
4dffcebc 6069 switch (i.tm.opcode_length)
331d2d0d 6070 {
4dffcebc 6071 case 3:
331d2d0d
L		 6072 p = frag_more (3);
6073 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6074 break;
6075 case 2:
6076 p = frag_more (2);
6077 break;
6078 default:
6079 abort ();
6080 break;
331d2d0d 6081 }
0f10071e 6082
29b0f896
AM		 6083 /* Put out high byte first: can't use md_number_to_chars! */
6084 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6085 *p = i.tm.base_opcode & 0xff;
6086 }
3e73aa7c 6087
29b0f896 6088 /* Now the modrm byte and sib byte (if present). */
40fb9820 6089 if (i.tm.opcode_modifier.modrm)
29b0f896 6090 {
4a3523fa
L		 6091 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6092 | i.rm.reg << 3
6093 | i.rm.mode << 6));
29b0f896
AM		 6094 /* If i.rm.regmem == ESP (4)
6095 && i.rm.mode != (Register mode)
6096 && not 16 bit
6097 ==> need second modrm byte. */
6098 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6099 && i.rm.mode != 3
40fb9820 6100 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6101 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6102 | i.sib.index << 3
6103 | i.sib.scale << 6));
29b0f896 6104 }
3e73aa7c 6105
29b0f896 6106 if (i.disp_operands)
2bbd9c25 6107 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6108
29b0f896 6109 if (i.imm_operands)
2bbd9c25 6110 output_imm (insn_start_frag, insn_start_off);
29b0f896 6111 }
252b5132 6112
29b0f896
AM		 6113#ifdef DEBUG386
6114 if (flag_debug)
6115 {
7b81dfbb 6116 pi ("" /*line*/, &i);
29b0f896
AM		 6117 }
6118#endif /* DEBUG386 */
6119}
252b5132 6120
e205caa7
L		 6121/* Return the size of the displacement operand N. */
6122
6123static int
6124disp_size (unsigned int n)
6125{
6126 int size = 4;
40fb9820
L		 6127 if (i.types[n].bitfield.disp64)
6128 size = 8;
6129 else if (i.types[n].bitfield.disp8)
6130 size = 1;
6131 else if (i.types[n].bitfield.disp16)
6132 size = 2;
e205caa7
L		 6133 return size;
6134}
6135
6136/* Return the size of the immediate operand N. */
6137
6138static int
6139imm_size (unsigned int n)
6140{
6141 int size = 4;
40fb9820
L		 6142 if (i.types[n].bitfield.imm64)
6143 size = 8;
6144 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6145 size = 1;
6146 else if (i.types[n].bitfield.imm16)
6147 size = 2;
e205caa7
L		 6148 return size;
6149}
6150
29b0f896 6151static void
64e74474 6152output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6153{
6154 char *p;
6155 unsigned int n;
252b5132 6156
29b0f896
AM		 6157 for (n = 0; n < i.operands; n++)
6158 {
40fb9820 6159 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6160 {
6161 if (i.op[n].disps->X_op == O_constant)
6162 {
e205caa7 6163 int size = disp_size (n);
29b0f896 6164 offsetT val;
252b5132 6165
29b0f896
AM		 6166 val = offset_in_range (i.op[n].disps->X_add_number,
6167 size);
6168 p = frag_more (size);
6169 md_number_to_chars (p, val, size);
6170 }
6171 else
6172 {
f86103b7 6173 enum bfd_reloc_code_real reloc_type;
e205caa7 6174 int size = disp_size (n);
40fb9820 6175 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6176 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6177
e205caa7 6178 /* We can't have 8 bit displacement here. */
9c2799c2 6179 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6180
29b0f896
AM		 6181 /* The PC relative address is computed relative
6182 to the instruction boundary, so in case immediate
6183 fields follows, we need to adjust the value. */
6184 if (pcrel && i.imm_operands)
6185 {
29b0f896 6186 unsigned int n1;
e205caa7 6187 int sz = 0;
252b5132 6188
29b0f896 6189 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6190 if (operand_type_check (i.types[n1], imm))
252b5132 6191 {
e205caa7
L		 6192 /* Only one immediate is allowed for PC
6193 relative address. */
9c2799c2 6194 gas_assert (sz == 0);
e205caa7
L		 6195 sz = imm_size (n1);
6196 i.op[n].disps->X_add_number -= sz;
252b5132 6197 }
29b0f896 6198 /* We should find the immediate. */
9c2799c2 6199 gas_assert (sz != 0);
29b0f896 6200 }
520dc8e8 6201
29b0f896 6202 p = frag_more (size);
2bbd9c25 6203 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6204 if (GOT_symbol
2bbd9c25 6205 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6206 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6207 || reloc_type == BFD_RELOC_X86_64_32S
6208 || (reloc_type == BFD_RELOC_64
6209 && object_64bit))
d6ab8113
JB		 6210 && (i.op[n].disps->X_op == O_symbol
6211 || (i.op[n].disps->X_op == O_add
6212 && ((symbol_get_value_expression
6213 (i.op[n].disps->X_op_symbol)->X_op)
6214 == O_subtract))))
6215 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6216 {
6217 offsetT add;
6218
6219 if (insn_start_frag == frag_now)
6220 add = (p - frag_now->fr_literal) - insn_start_off;
6221 else
6222 {
6223 fragS *fr;
6224
6225 add = insn_start_frag->fr_fix - insn_start_off;
6226 for (fr = insn_start_frag->fr_next;
6227 fr && fr != frag_now; fr = fr->fr_next)
6228 add += fr->fr_fix;
6229 add += p - frag_now->fr_literal;
6230 }
6231
4fa24527 6232 if (!object_64bit)
7b81dfbb
AJ		 6233 {
6234 reloc_type = BFD_RELOC_386_GOTPC;
6235 i.op[n].imms->X_add_number += add;
6236 }
6237 else if (reloc_type == BFD_RELOC_64)
6238 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6239 else
7b81dfbb
AJ		 6240 /* Don't do the adjustment for x86-64, as there
6241 the pcrel addressing is relative to the _next_
6242 insn, and that is taken care of in other code. */
d6ab8113 6243 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6244 }
062cd5e7 6245 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6246 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6247 }
6248 }
6249 }
6250}
252b5132 6251
29b0f896 6252static void
64e74474 6253output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6254{
6255 char *p;
6256 unsigned int n;
252b5132 6257
29b0f896
AM		 6258 for (n = 0; n < i.operands; n++)
6259 {
40fb9820 6260 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6261 {
6262 if (i.op[n].imms->X_op == O_constant)
6263 {
e205caa7 6264 int size = imm_size (n);
29b0f896 6265 offsetT val;
b4cac588 6266
29b0f896
AM		 6267 val = offset_in_range (i.op[n].imms->X_add_number,
6268 size);
6269 p = frag_more (size);
6270 md_number_to_chars (p, val, size);
6271 }
6272 else
6273 {
6274 /* Not absolute_section.
6275 Need a 32-bit fixup (don't support 8bit
6276 non-absolute imms). Try to support other
6277 sizes ... */
f86103b7 6278 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6279 int size = imm_size (n);
6280 int sign;
29b0f896 6281
40fb9820 6282 if (i.types[n].bitfield.imm32s
a7d61044 6283 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6284 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6285 sign = 1;
e205caa7
L		 6286 else
6287 sign = 0;
520dc8e8 6288
29b0f896
AM		 6289 p = frag_more (size);
6290 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6291
2bbd9c25
JJ		 6292 /* This is tough to explain. We end up with this one if we
6293 * have operands that look like
6294 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6295 * obtain the absolute address of the GOT, and it is strongly
6296 * preferable from a performance point of view to avoid using
6297 * a runtime relocation for this. The actual sequence of
6298 * instructions often look something like:
6299 *
6300 * call .L66
6301 * .L66:
6302 * popl %ebx
6303 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6304 *
6305 * The call and pop essentially return the absolute address
6306 * of the label .L66 and store it in %ebx. The linker itself
6307 * will ultimately change the first operand of the addl so
6308 * that %ebx points to the GOT, but to keep things simple, the
6309 * .o file must have this operand set so that it generates not
6310 * the absolute address of .L66, but the absolute address of
6311 * itself. This allows the linker itself simply treat a GOTPC
6312 * relocation as asking for a pcrel offset to the GOT to be
6313 * added in, and the addend of the relocation is stored in the
6314 * operand field for the instruction itself.
6315 *
6316 * Our job here is to fix the operand so that it would add
6317 * the correct offset so that %ebx would point to itself. The
6318 * thing that is tricky is that .-.L66 will point to the
6319 * beginning of the instruction, so we need to further modify
6320 * the operand so that it will point to itself. There are
6321 * other cases where you have something like:
6322 *
6323 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6324 *
6325 * and here no correction would be required. Internally in
6326 * the assembler we treat operands of this form as not being
6327 * pcrel since the '.' is explicitly mentioned, and I wonder
6328 * whether it would simplify matters to do it this way. Who
6329 * knows. In earlier versions of the PIC patches, the
6330 * pcrel_adjust field was used to store the correction, but
6331 * since the expression is not pcrel, I felt it would be
6332 * confusing to do it this way. */
6333
d6ab8113 6334 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6335 || reloc_type == BFD_RELOC_X86_64_32S
6336 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6337 && GOT_symbol
6338 && GOT_symbol == i.op[n].imms->X_add_symbol
6339 && (i.op[n].imms->X_op == O_symbol
6340 || (i.op[n].imms->X_op == O_add
6341 && ((symbol_get_value_expression
6342 (i.op[n].imms->X_op_symbol)->X_op)
6343 == O_subtract))))
6344 {
2bbd9c25
JJ		 6345 offsetT add;
6346
6347 if (insn_start_frag == frag_now)
6348 add = (p - frag_now->fr_literal) - insn_start_off;
6349 else
6350 {
6351 fragS *fr;
6352
6353 add = insn_start_frag->fr_fix - insn_start_off;
6354 for (fr = insn_start_frag->fr_next;
6355 fr && fr != frag_now; fr = fr->fr_next)
6356 add += fr->fr_fix;
6357 add += p - frag_now->fr_literal;
6358 }
6359
4fa24527 6360 if (!object_64bit)
d6ab8113 6361 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6362 else if (size == 4)
d6ab8113 6363 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6364 else if (size == 8)
6365 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6366 i.op[n].imms->X_add_number += add;
29b0f896 6367 }
29b0f896
AM		 6368 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6369 i.op[n].imms, 0, reloc_type);
6370 }
6371 }
6372 }
252b5132
RH		 6373}
6374\f
d182319b
JB		 6375/* x86_cons_fix_new is called via the expression parsing code when a
6376 reloc is needed. We use this hook to get the correct .got reloc. */
6377static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6378static int cons_sign = -1;
6379
6380void
e3bb37b5 6381x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6382 expressionS *exp)
d182319b
JB		 6383{
6384 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6385
6386 got_reloc = NO_RELOC;
6387
6388#ifdef TE_PE
6389 if (exp->X_op == O_secrel)
6390 {
6391 exp->X_op = O_symbol;
6392 r = BFD_RELOC_32_SECREL;
6393 }
6394#endif
6395
6396 fix_new_exp (frag, off, len, exp, 0, r);
6397}
6398
718ddfc0
JB		 6399#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6400# define lex_got(reloc, adjust, types) NULL
6401#else
f3c180ae
AM		 6402/* Parse operands of the form
6403 <symbol>@GOTOFF+<nnn>
6404 and similar .plt or .got references.
6405
6406 If we find one, set up the correct relocation in RELOC and copy the
6407 input string, minus the `@GOTOFF' into a malloc'd buffer for
6408 parsing by the calling routine. Return this buffer, and if ADJUST
6409 is non-null set it to the length of the string we removed from the
6410 input line. Otherwise return NULL. */
6411static char *
91d6fa6a 6412lex_got (enum bfd_reloc_code_real *rel,
64e74474 6413 int *adjust,
40fb9820 6414 i386_operand_type *types)
f3c180ae 6415{
7b81dfbb
AJ		 6416 /* Some of the relocations depend on the size of what field is to
6417 be relocated. But in our callers i386_immediate and i386_displacement
6418 we don't yet know the operand size (this will be set by insn
6419 matching). Hence we record the word32 relocation here,
6420 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6421 static const struct {
6422 const char *str;
cff8d58a 6423 int len;
4fa24527 6424 const enum bfd_reloc_code_real rel[2];
40fb9820 6425 const i386_operand_type types64;
f3c180ae 6426 } gotrel[] = {
cff8d58a
L		 6427 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6428 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6429 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6430 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6431 BFD_RELOC_X86_64_PLT32 },
40fb9820 6432 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6433 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6434 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6435 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6436 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6437 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6438 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6439 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6440 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6441 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6442 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6443 BFD_RELOC_X86_64_TLSGD },
40fb9820 6444 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6445 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6446 _dummy_first_bfd_reloc_code_real },
40fb9820 6447 OPERAND_TYPE_NONE },
cff8d58a
L		 6448 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6449 BFD_RELOC_X86_64_TLSLD },
40fb9820 6450 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6451 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6452 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6453 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6454 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6455 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6456 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6457 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6458 _dummy_first_bfd_reloc_code_real },
40fb9820 6459 OPERAND_TYPE_NONE },
cff8d58a
L		 6460 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6461 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6462 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6463 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6464 _dummy_first_bfd_reloc_code_real },
40fb9820 6465 OPERAND_TYPE_NONE },
cff8d58a
L		 6466 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6467 _dummy_first_bfd_reloc_code_real },
40fb9820 6468 OPERAND_TYPE_NONE },
cff8d58a
L		 6469 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6470 BFD_RELOC_X86_64_GOT32 },
40fb9820 6471 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6472 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6473 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6474 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6475 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6476 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6477 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6478 };
6479 char *cp;
6480 unsigned int j;
6481
718ddfc0
JB		 6482 if (!IS_ELF)
6483 return NULL;
6484
f3c180ae 6485 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6486 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6487 return NULL;
6488
47465058 6489 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6490 {
cff8d58a 6491 int len = gotrel[j].len;
28f81592 6492 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6493 {
4fa24527 6494 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6495 {
28f81592
AM		 6496 int first, second;
6497 char *tmpbuf, *past_reloc;
f3c180ae 6498
91d6fa6a 6499 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6500 if (adjust)
6501 *adjust = len;
f3c180ae 6502
3956db08
JB		 6503 if (types)
6504 {
6505 if (flag_code != CODE_64BIT)
40fb9820
L		 6506 {
6507 types->bitfield.imm32 = 1;
6508 types->bitfield.disp32 = 1;
6509 }
3956db08
JB		 6510 else
6511 *types = gotrel[j].types64;
6512 }
6513
f3c180ae
AM		 6514 if (GOT_symbol == NULL)
6515 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6516
28f81592 6517 /* The length of the first part of our input line. */
f3c180ae 6518 first = cp - input_line_pointer;
28f81592
AM		 6519
6520 /* The second part goes from after the reloc token until
67c11a9b 6521 (and including) an end_of_line char or comma. */
28f81592 6522 past_reloc = cp + 1 + len;
67c11a9b
AM		 6523 cp = past_reloc;
6524 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6525 ++cp;
6526 second = cp + 1 - past_reloc;
28f81592
AM		 6527
6528 /* Allocate and copy string. The trailing NUL shouldn't
6529 be necessary, but be safe. */
1e9cc1c2 6530 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6531 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6532 if (second != 0 && *past_reloc != ' ')
6533 /* Replace the relocation token with ' ', so that
6534 errors like foo@GOTOFF1 will be detected. */
6535 tmpbuf[first++] = ' ';
6536 memcpy (tmpbuf + first, past_reloc, second);
6537 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6538 return tmpbuf;
6539 }
6540
4fa24527
JB		 6541 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6542 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6543 return NULL;
6544 }
6545 }
6546
6547 /* Might be a symbol version string. Don't as_bad here. */
6548 return NULL;
6549}
6550
f3c180ae 6551void
e3bb37b5 6552x86_cons (expressionS *exp, int size)
f3c180ae 6553{
ee86248c
JB		 6554 intel_syntax = -intel_syntax;
6555
3c7b9c2c 6556 exp->X_md = 0;
4fa24527 6557 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6558 {
6559 /* Handle @GOTOFF and the like in an expression. */
6560 char *save;
6561 char *gotfree_input_line;
6562 int adjust;
6563
6564 save = input_line_pointer;
3956db08 6565 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6566 if (gotfree_input_line)
6567 input_line_pointer = gotfree_input_line;
6568
6569 expression (exp);
6570
6571 if (gotfree_input_line)
6572 {
6573 /* expression () has merrily parsed up to the end of line,
6574 or a comma - in the wrong buffer. Transfer how far
6575 input_line_pointer has moved to the right buffer. */
6576 input_line_pointer = (save
6577 + (input_line_pointer - gotfree_input_line)
6578 + adjust);
6579 free (gotfree_input_line);
3992d3b7
AM		 6580 if (exp->X_op == O_constant
6581 || exp->X_op == O_absent
6582 || exp->X_op == O_illegal
0398aac5 6583 || exp->X_op == O_register
3992d3b7
AM		 6584 || exp->X_op == O_big)
6585 {
6586 char c = *input_line_pointer;
6587 *input_line_pointer = 0;
6588 as_bad (_("missing or invalid expression `%s'"), save);
6589 *input_line_pointer = c;
6590 }
f3c180ae
AM		 6591 }
6592 }
6593 else
6594 expression (exp);
ee86248c
JB		 6595
6596 intel_syntax = -intel_syntax;
6597
6598 if (intel_syntax)
6599 i386_intel_simplify (exp);
f3c180ae
AM		 6600}
6601#endif
6602
9f32dd5b
L		 6603static void
6604signed_cons (int size)
6482c264 6605{
d182319b
JB		 6606 if (flag_code == CODE_64BIT)
6607 cons_sign = 1;
6608 cons (size);
6609 cons_sign = -1;
6482c264
NC		 6610}
6611
d182319b 6612#ifdef TE_PE
6482c264
NC		 6613static void
6614pe_directive_secrel (dummy)
6615 int dummy ATTRIBUTE_UNUSED;
6616{
6617 expressionS exp;
6618
6619 do
6620 {
6621 expression (&exp);
6622 if (exp.X_op == O_symbol)
6623 exp.X_op = O_secrel;
6624
6625 emit_expr (&exp, 4);
6626 }
6627 while (*input_line_pointer++ == ',');
6628
6629 input_line_pointer--;
6630 demand_empty_rest_of_line ();
6631}
6482c264
NC		 6632#endif
6633
252b5132 6634static int
70e41ade 6635i386_immediate (char *imm_start)
252b5132
RH		 6636{
6637 char *save_input_line_pointer;
f3c180ae 6638 char *gotfree_input_line;
252b5132 6639 segT exp_seg = 0;
47926f60 6640 expressionS *exp;
40fb9820
L		 6641 i386_operand_type types;
6642
0dfbf9d7 6643 operand_type_set (&types, ~0);
252b5132
RH		 6644
6645 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6646 {
31b2323c
L		 6647 as_bad (_("at most %d immediate operands are allowed"),
6648 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6649 return 0;
6650 }
6651
6652 exp = &im_expressions[i.imm_operands++];
520dc8e8 6653 i.op[this_operand].imms = exp;
252b5132
RH		 6654
6655 if (is_space_char (*imm_start))
6656 ++imm_start;
6657
6658 save_input_line_pointer = input_line_pointer;
6659 input_line_pointer = imm_start;
6660
3956db08 6661 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6662 if (gotfree_input_line)
6663 input_line_pointer = gotfree_input_line;
252b5132
RH		 6664
6665 exp_seg = expression (exp);
6666
83183c0c 6667 SKIP_WHITESPACE ();
252b5132 6668 if (*input_line_pointer)
f3c180ae 6669 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6670
6671 input_line_pointer = save_input_line_pointer;
f3c180ae 6672 if (gotfree_input_line)
ee86248c
JB		 6673 {
6674 free (gotfree_input_line);
6675
6676 if (exp->X_op == O_constant || exp->X_op == O_register)
6677 exp->X_op = O_illegal;
6678 }
6679
6680 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6681}
252b5132 6682
ee86248c
JB		 6683static int
6684i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6685 i386_operand_type types, const char *imm_start)
6686{
6687 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6688 {
313c53d1
L		 6689 if (imm_start)
6690 as_bad (_("missing or invalid immediate expression `%s'"),
6691 imm_start);
3992d3b7 6692 return 0;
252b5132 6693 }
3e73aa7c 6694 else if (exp->X_op == O_constant)
252b5132 6695 {
47926f60 6696 /* Size it properly later. */
40fb9820 6697 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6698 /* If not 64bit, sign extend val. */
6699 if (flag_code != CODE_64BIT
4eed87de
AM		 6700 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6701 exp->X_add_number
6702 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6703 }
4c63da97 6704#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6705 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6706 && exp_seg != absolute_section
47926f60 6707 && exp_seg != text_section
24eab124
AM		 6708 && exp_seg != data_section
6709 && exp_seg != bss_section
6710 && exp_seg != undefined_section
f86103b7 6711 && !bfd_is_com_section (exp_seg))
252b5132 6712 {
d0b47220 6713 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6714 return 0;
6715 }
6716#endif
bb8f5920
L		 6717 else if (!intel_syntax && exp->X_op == O_register)
6718 {
313c53d1
L		 6719 if (imm_start)
6720 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6721 return 0;
6722 }
252b5132
RH		 6723 else
6724 {
6725 /* This is an address. The size of the address will be
24eab124 6726 determined later, depending on destination register,
3e73aa7c 6727 suffix, or the default for the section. */
40fb9820
L		 6728 i.types[this_operand].bitfield.imm8 = 1;
6729 i.types[this_operand].bitfield.imm16 = 1;
6730 i.types[this_operand].bitfield.imm32 = 1;
6731 i.types[this_operand].bitfield.imm32s = 1;
6732 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6733 i.types[this_operand] = operand_type_and (i.types[this_operand],
6734 types);
252b5132
RH		 6735 }
6736
6737 return 1;
6738}
6739
551c1ca1 6740static char *
e3bb37b5 6741i386_scale (char *scale)
252b5132 6742{
551c1ca1
AM		 6743 offsetT val;
6744 char *save = input_line_pointer;
252b5132 6745
551c1ca1
AM		 6746 input_line_pointer = scale;
6747 val = get_absolute_expression ();
6748
6749 switch (val)
252b5132 6750 {
551c1ca1 6751 case 1:
252b5132
RH		 6752 i.log2_scale_factor = 0;
6753 break;
551c1ca1 6754 case 2:
252b5132
RH		 6755 i.log2_scale_factor = 1;
6756 break;
551c1ca1 6757 case 4:
252b5132
RH		 6758 i.log2_scale_factor = 2;
6759 break;
551c1ca1 6760 case 8:
252b5132
RH		 6761 i.log2_scale_factor = 3;
6762 break;
6763 default:
a724f0f4
JB		 6764 {
6765 char sep = *input_line_pointer;
6766
6767 *input_line_pointer = '\0';
6768 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6769 scale);
6770 *input_line_pointer = sep;
6771 input_line_pointer = save;
6772 return NULL;
6773 }
252b5132 6774 }
29b0f896 6775 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6776 {
6777 as_warn (_("scale factor of %d without an index register"),
24eab124 6778 1 << i.log2_scale_factor);
252b5132 6779 i.log2_scale_factor = 0;
252b5132 6780 }
551c1ca1
AM		 6781 scale = input_line_pointer;
6782 input_line_pointer = save;
6783 return scale;
252b5132
RH		 6784}
6785
252b5132 6786static int
e3bb37b5 6787i386_displacement (char *disp_start, char *disp_end)
252b5132 6788{
29b0f896 6789 expressionS *exp;
252b5132
RH		 6790 segT exp_seg = 0;
6791 char *save_input_line_pointer;
f3c180ae 6792 char *gotfree_input_line;
40fb9820
L		 6793 int override;
6794 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6795 int ret;
252b5132 6796
31b2323c
L		 6797 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6798 {
6799 as_bad (_("at most %d displacement operands are allowed"),
6800 MAX_MEMORY_OPERANDS);
6801 return 0;
6802 }
6803
0dfbf9d7 6804 operand_type_set (&bigdisp, 0);
40fb9820
L		 6805 if ((i.types[this_operand].bitfield.jumpabsolute)
6806 || (!current_templates->start->opcode_modifier.jump
6807 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6808 {
40fb9820 6809 bigdisp.bitfield.disp32 = 1;
e05278af 6810 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6811 if (flag_code == CODE_64BIT)
6812 {
6813 if (!override)
6814 {
6815 bigdisp.bitfield.disp32s = 1;
6816 bigdisp.bitfield.disp64 = 1;
6817 }
6818 }
6819 else if ((flag_code == CODE_16BIT) ^ override)
6820 {
6821 bigdisp.bitfield.disp32 = 0;
6822 bigdisp.bitfield.disp16 = 1;
6823 }
e05278af
JB		 6824 }
6825 else
6826 {
6827 /* For PC-relative branches, the width of the displacement
6828 is dependent upon data size, not address size. */
e05278af 6829 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6830 if (flag_code == CODE_64BIT)
6831 {
6832 if (override || i.suffix == WORD_MNEM_SUFFIX)
6833 bigdisp.bitfield.disp16 = 1;
6834 else
6835 {
6836 bigdisp.bitfield.disp32 = 1;
6837 bigdisp.bitfield.disp32s = 1;
6838 }
6839 }
6840 else
e05278af
JB		 6841 {
6842 if (!override)
6843 override = (i.suffix == (flag_code != CODE_16BIT
6844 ? WORD_MNEM_SUFFIX
6845 : LONG_MNEM_SUFFIX));
40fb9820
L		 6846 bigdisp.bitfield.disp32 = 1;
6847 if ((flag_code == CODE_16BIT) ^ override)
6848 {
6849 bigdisp.bitfield.disp32 = 0;
6850 bigdisp.bitfield.disp16 = 1;
6851 }
e05278af 6852 }
e05278af 6853 }
c6fb90c8
L		 6854 i.types[this_operand] = operand_type_or (i.types[this_operand],
6855 bigdisp);
252b5132
RH		 6856
6857 exp = &disp_expressions[i.disp_operands];
520dc8e8 6858 i.op[this_operand].disps = exp;
252b5132
RH		 6859 i.disp_operands++;
6860 save_input_line_pointer = input_line_pointer;
6861 input_line_pointer = disp_start;
6862 END_STRING_AND_SAVE (disp_end);
6863
6864#ifndef GCC_ASM_O_HACK
6865#define GCC_ASM_O_HACK 0
6866#endif
6867#if GCC_ASM_O_HACK
6868 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6869 if (i.types[this_operand].bitfield.baseIndex
24eab124 6870 && displacement_string_end[-1] == '+')
252b5132
RH		 6871 {
6872 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6873 constraint within gcc asm statements.
6874 For instance:
6875
6876 #define _set_tssldt_desc(n,addr,limit,type) \
6877 __asm__ __volatile__ ( \
6878 "movw %w2,%0\n\t" \
6879 "movw %w1,2+%0\n\t" \
6880 "rorl $16,%1\n\t" \
6881 "movb %b1,4+%0\n\t" \
6882 "movb %4,5+%0\n\t" \
6883 "movb $0,6+%0\n\t" \
6884 "movb %h1,7+%0\n\t" \
6885 "rorl $16,%1" \
6886 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6887
6888 This works great except that the output assembler ends
6889 up looking a bit weird if it turns out that there is
6890 no offset. You end up producing code that looks like:
6891
6892 #APP
6893 movw $235,(%eax)
6894 movw %dx,2+(%eax)
6895 rorl $16,%edx
6896 movb %dl,4+(%eax)
6897 movb $137,5+(%eax)
6898 movb $0,6+(%eax)
6899 movb %dh,7+(%eax)
6900 rorl $16,%edx
6901 #NO_APP
6902
47926f60 6903 So here we provide the missing zero. */
24eab124
AM		 6904
6905 *displacement_string_end = '0';
252b5132
RH		 6906 }
6907#endif
3956db08 6908 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6909 if (gotfree_input_line)
6910 input_line_pointer = gotfree_input_line;
252b5132 6911
24eab124 6912 exp_seg = expression (exp);
252b5132 6913
636c26b0
AM		 6914 SKIP_WHITESPACE ();
6915 if (*input_line_pointer)
6916 as_bad (_("junk `%s' after expression"), input_line_pointer);
6917#if GCC_ASM_O_HACK
6918 RESTORE_END_STRING (disp_end + 1);
6919#endif
636c26b0 6920 input_line_pointer = save_input_line_pointer;
636c26b0 6921 if (gotfree_input_line)
ee86248c
JB		 6922 {
6923 free (gotfree_input_line);
6924
6925 if (exp->X_op == O_constant || exp->X_op == O_register)
6926 exp->X_op = O_illegal;
6927 }
6928
6929 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6930
6931 RESTORE_END_STRING (disp_end);
6932
6933 return ret;
6934}
6935
6936static int
6937i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6938 i386_operand_type types, const char *disp_start)
6939{
6940 i386_operand_type bigdisp;
6941 int ret = 1;
636c26b0 6942
24eab124
AM		 6943 /* We do this to make sure that the section symbol is in
6944 the symbol table. We will ultimately change the relocation
47926f60 6945 to be relative to the beginning of the section. */
1ae12ab7 6946 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6947 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6948 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6949 {
636c26b0 6950 if (exp->X_op != O_symbol)
3992d3b7 6951 goto inv_disp;
636c26b0 6952
e5cb08ac 6953 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6954 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6955 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6956 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6957 exp->X_op = O_subtract;
6958 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6959 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6960 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6961 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6962 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6963 else
29b0f896 6964 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6965 }
252b5132 6966
3992d3b7
AM		 6967 else if (exp->X_op == O_absent
6968 || exp->X_op == O_illegal
ee86248c 6969 || exp->X_op == O_big)
2daf4fd8 6970 {
3992d3b7
AM		 6971 inv_disp:
6972 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6973 disp_start);
3992d3b7 6974 ret = 0;
2daf4fd8
AM		 6975 }
6976
0e1147d9
L		 6977 else if (flag_code == CODE_64BIT
6978 && !i.prefix[ADDR_PREFIX]
6979 && exp->X_op == O_constant)
6980 {
6981 /* Since displacement is signed extended to 64bit, don't allow
6982 disp32 and turn off disp32s if they are out of range. */
6983 i.types[this_operand].bitfield.disp32 = 0;
6984 if (!fits_in_signed_long (exp->X_add_number))
6985 {
6986 i.types[this_operand].bitfield.disp32s = 0;
6987 if (i.types[this_operand].bitfield.baseindex)
6988 {
6989 as_bad (_("0x%lx out range of signed 32bit displacement"),
6990 (long) exp->X_add_number);
6991 ret = 0;
6992 }
6993 }
6994 }
6995
4c63da97 6996#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6997 else if (exp->X_op != O_constant
6998 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6999 && exp_seg != absolute_section
7000 && exp_seg != text_section
7001 && exp_seg != data_section
7002 && exp_seg != bss_section
7003 && exp_seg != undefined_section
7004 && !bfd_is_com_section (exp_seg))
24eab124 7005 {
d0b47220 7006 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7007 ret = 0;
24eab124 7008 }
252b5132 7009#endif
3956db08 7010
40fb9820
L		 7011 /* Check if this is a displacement only operand. */
7012 bigdisp = i.types[this_operand];
7013 bigdisp.bitfield.disp8 = 0;
7014 bigdisp.bitfield.disp16 = 0;
7015 bigdisp.bitfield.disp32 = 0;
7016 bigdisp.bitfield.disp32s = 0;
7017 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7018 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7019 i.types[this_operand] = operand_type_and (i.types[this_operand],
7020 types);
3956db08 7021
3992d3b7 7022 return ret;
252b5132
RH		 7023}
7024
eecb386c 7025/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7026 Return 1 on success, 0 on a failure. */
7027
252b5132 7028static int
e3bb37b5 7029i386_index_check (const char *operand_string)
252b5132 7030{
3e73aa7c 7031 int ok;
fc0763e6 7032 const char *kind = "base/index";
24eab124 7033#if INFER_ADDR_PREFIX
eecb386c
AM		 7034 int fudged = 0;
7035
24eab124
AM		 7036 tryprefix:
7037#endif
3e73aa7c 7038 ok = 1;
fc0763e6
JB		 7039 if (current_templates->start->opcode_modifier.isstring
7040 && !current_templates->start->opcode_modifier.immext
7041 && (current_templates->end[-1].opcode_modifier.isstring
7042 || i.mem_operands))
7043 {
7044 /* Memory operands of string insns are special in that they only allow
7045 a single register (rDI, rSI, or rBX) as their memory address. */
7046 unsigned int expected;
7047
7048 kind = "string address";
7049
7050 if (current_templates->start->opcode_modifier.w)
7051 {
7052 i386_operand_type type = current_templates->end[-1].operand_types[0];
7053
7054 if (!type.bitfield.baseindex
7055 || ((!i.mem_operands != !intel_syntax)
7056 && current_templates->end[-1].operand_types[1]
7057 .bitfield.baseindex))
7058 type = current_templates->end[-1].operand_types[1];
7059 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7060 }
7061 else
7062 expected = 3 /* rBX */;
7063
7064 if (!i.base_reg || i.index_reg
7065 || operand_type_check (i.types[this_operand], disp))
7066 ok = -1;
7067 else if (!(flag_code == CODE_64BIT
7068 ? i.prefix[ADDR_PREFIX]
7069 ? i.base_reg->reg_type.bitfield.reg32
7070 : i.base_reg->reg_type.bitfield.reg64
7071 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7072 ? i.base_reg->reg_type.bitfield.reg32
7073 : i.base_reg->reg_type.bitfield.reg16))
7074 ok = 0;
7075 else if (i.base_reg->reg_num != expected)
7076 ok = -1;
7077
7078 if (ok < 0)
7079 {
7080 unsigned int j;
7081
7082 for (j = 0; j < i386_regtab_size; ++j)
7083 if ((flag_code == CODE_64BIT
7084 ? i.prefix[ADDR_PREFIX]
7085 ? i386_regtab[j].reg_type.bitfield.reg32
7086 : i386_regtab[j].reg_type.bitfield.reg64
7087 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7088 ? i386_regtab[j].reg_type.bitfield.reg32
7089 : i386_regtab[j].reg_type.bitfield.reg16)
7090 && i386_regtab[j].reg_num == expected)
7091 break;
9c2799c2 7092 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7093 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7094 operand_string,
7095 intel_syntax ? '[' : '(',
7096 register_prefix,
7097 i386_regtab[j].reg_name,
7098 intel_syntax ? ']' : ')');
7099 ok = 1;
7100 }
7101 }
7102 else if (flag_code == CODE_64BIT)
64e74474 7103 {
64e74474 7104 if ((i.base_reg
40fb9820
L		 7105 && ((i.prefix[ADDR_PREFIX] == 0
7106 && !i.base_reg->reg_type.bitfield.reg64)
7107 || (i.prefix[ADDR_PREFIX]
7108 && !i.base_reg->reg_type.bitfield.reg32))
7109 && (i.index_reg
9a04903e
JB		 7110 || i.base_reg->reg_num !=
7111 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7112 || (i.index_reg
40fb9820
L		 7113 && (!i.index_reg->reg_type.bitfield.baseindex
7114 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7115 && i.index_reg->reg_num != RegRiz
7116 && !i.index_reg->reg_type.bitfield.reg64
7117 )
40fb9820 7118 || (i.prefix[ADDR_PREFIX]
db51cc60 7119 && i.index_reg->reg_num != RegEiz
40fb9820 7120 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7121 ok = 0;
3e73aa7c
JH		 7122 }
7123 else
7124 {
7125 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7126 {
7127 /* 16bit checks. */
7128 if ((i.base_reg
40fb9820
L		 7129 && (!i.base_reg->reg_type.bitfield.reg16
7130 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7131 || (i.index_reg
40fb9820
L		 7132 && (!i.index_reg->reg_type.bitfield.reg16
7133 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7134 || !(i.base_reg
7135 && i.base_reg->reg_num < 6
7136 && i.index_reg->reg_num >= 6
7137 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7138 ok = 0;
7139 }
7140 else
e5cb08ac 7141 {
3e73aa7c
JH		 7142 /* 32bit checks. */
7143 if ((i.base_reg
40fb9820 7144 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7145 || (i.index_reg
db51cc60
L		 7146 && ((!i.index_reg->reg_type.bitfield.reg32
7147 && i.index_reg->reg_num != RegEiz)
40fb9820 7148 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7149 ok = 0;
3e73aa7c
JH		 7150 }
7151 }
7152 if (!ok)
24eab124
AM		 7153 {
7154#if INFER_ADDR_PREFIX
fc0763e6 7155 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7156 {
7157 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7158 i.prefixes += 1;
b23bac36
AM		 7159 /* Change the size of any displacement too. At most one of
7160 Disp16 or Disp32 is set.
7161 FIXME. There doesn't seem to be any real need for separate
7162 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7163 Removing them would probably clean up the code quite a lot. */
4eed87de 7164 if (flag_code != CODE_64BIT
40fb9820
L		 7165 && (i.types[this_operand].bitfield.disp16
7166 || i.types[this_operand].bitfield.disp32))
7167 i.types[this_operand]
c6fb90c8 7168 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7169 fudged = 1;
24eab124
AM		 7170 goto tryprefix;
7171 }
eecb386c 7172 if (fudged)
fc0763e6
JB		 7173 as_bad (_("`%s' is not a valid %s expression"),
7174 operand_string,
7175 kind);
eecb386c 7176 else
c388dee8 7177#endif
fc0763e6 7178 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7179 operand_string,
fc0763e6
JB		 7180 flag_code_names[i.prefix[ADDR_PREFIX]
7181 ? flag_code == CODE_32BIT
7182 ? CODE_16BIT
7183 : CODE_32BIT
7184 : flag_code],
7185 kind);
24eab124 7186 }
20f0a1fc 7187 return ok;
24eab124 7188}
252b5132 7189
fc0763e6 7190/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7191 on error. */
252b5132 7192
252b5132 7193static int
a7619375 7194i386_att_operand (char *operand_string)
252b5132 7195{
af6bdddf
AM		 7196 const reg_entry *r;
7197 char *end_op;
24eab124 7198 char *op_string = operand_string;
252b5132 7199
24eab124 7200 if (is_space_char (*op_string))
252b5132
RH		 7201 ++op_string;
7202
24eab124 7203 /* We check for an absolute prefix (differentiating,
47926f60 7204 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7205 if (*op_string == ABSOLUTE_PREFIX)
7206 {
7207 ++op_string;
7208 if (is_space_char (*op_string))
7209 ++op_string;
40fb9820 7210 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7211 }
252b5132 7212
47926f60 7213 /* Check if operand is a register. */
4d1bb795 7214 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7215 {
40fb9820
L		 7216 i386_operand_type temp;
7217
24eab124
AM		 7218 /* Check for a segment override by searching for ':' after a
7219 segment register. */
7220 op_string = end_op;
7221 if (is_space_char (*op_string))
7222 ++op_string;
40fb9820
L		 7223 if (*op_string == ':'
7224 && (r->reg_type.bitfield.sreg2
7225 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7226 {
7227 switch (r->reg_num)
7228 {
7229 case 0:
7230 i.seg[i.mem_operands] = &es;
7231 break;
7232 case 1:
7233 i.seg[i.mem_operands] = &cs;
7234 break;
7235 case 2:
7236 i.seg[i.mem_operands] = &ss;
7237 break;
7238 case 3:
7239 i.seg[i.mem_operands] = &ds;
7240 break;
7241 case 4:
7242 i.seg[i.mem_operands] = &fs;
7243 break;
7244 case 5:
7245 i.seg[i.mem_operands] = &gs;
7246 break;
7247 }
252b5132 7248
24eab124 7249 /* Skip the ':' and whitespace. */
252b5132
RH		 7250 ++op_string;
7251 if (is_space_char (*op_string))
24eab124 7252 ++op_string;
252b5132 7253
24eab124
AM		 7254 if (!is_digit_char (*op_string)
7255 && !is_identifier_char (*op_string)
7256 && *op_string != '('
7257 && *op_string != ABSOLUTE_PREFIX)
7258 {
7259 as_bad (_("bad memory operand `%s'"), op_string);
7260 return 0;
7261 }
47926f60 7262 /* Handle case of %es:*foo. */
24eab124
AM		 7263 if (*op_string == ABSOLUTE_PREFIX)
7264 {
7265 ++op_string;
7266 if (is_space_char (*op_string))
7267 ++op_string;
40fb9820 7268 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7269 }
7270 goto do_memory_reference;
7271 }
7272 if (*op_string)
7273 {
d0b47220 7274 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7275 return 0;
7276 }
40fb9820
L		 7277 temp = r->reg_type;
7278 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7279 i.types[this_operand] = operand_type_or (i.types[this_operand],
7280 temp);
7d5e4556 7281 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7282 i.op[this_operand].regs = r;
24eab124
AM		 7283 i.reg_operands++;
7284 }
af6bdddf
AM		 7285 else if (*op_string == REGISTER_PREFIX)
7286 {
7287 as_bad (_("bad register name `%s'"), op_string);
7288 return 0;
7289 }
24eab124 7290 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7291 {
24eab124 7292 ++op_string;
40fb9820 7293 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7294 {
d0b47220 7295 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7296 return 0;
7297 }
7298 if (!i386_immediate (op_string))
7299 return 0;
7300 }
7301 else if (is_digit_char (*op_string)
7302 || is_identifier_char (*op_string)
e5cb08ac 7303 || *op_string == '(')
24eab124 7304 {
47926f60 7305 /* This is a memory reference of some sort. */
af6bdddf 7306 char *base_string;
252b5132 7307
47926f60 7308 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7309 char *displacement_string_start;
7310 char *displacement_string_end;
252b5132 7311
24eab124 7312 do_memory_reference:
24eab124 7313 if ((i.mem_operands == 1
40fb9820 7314 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7315 || i.mem_operands == 2)
7316 {
7317 as_bad (_("too many memory references for `%s'"),
7318 current_templates->start->name);
7319 return 0;
7320 }
252b5132 7321
24eab124
AM		 7322 /* Check for base index form. We detect the base index form by
7323 looking for an ')' at the end of the operand, searching
7324 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7325 after the '('. */
af6bdddf 7326 base_string = op_string + strlen (op_string);
c3332e24 7327
af6bdddf
AM		 7328 --base_string;
7329 if (is_space_char (*base_string))
7330 --base_string;
252b5132 7331
47926f60 7332 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7333 displacement_string_start = op_string;
7334 displacement_string_end = base_string + 1;
252b5132 7335
24eab124
AM		 7336 if (*base_string == ')')
7337 {
af6bdddf 7338 char *temp_string;
24eab124
AM		 7339 unsigned int parens_balanced = 1;
7340 /* We've already checked that the number of left & right ()'s are
47926f60 7341 equal, so this loop will not be infinite. */
24eab124
AM		 7342 do
7343 {
7344 base_string--;
7345 if (*base_string == ')')
7346 parens_balanced++;
7347 if (*base_string == '(')
7348 parens_balanced--;
7349 }
7350 while (parens_balanced);
c3332e24 7351
af6bdddf 7352 temp_string = base_string;
c3332e24 7353
24eab124 7354 /* Skip past '(' and whitespace. */
252b5132
RH		 7355 ++base_string;
7356 if (is_space_char (*base_string))
24eab124 7357 ++base_string;
252b5132 7358
af6bdddf 7359 if (*base_string == ','
4eed87de
AM		 7360 || ((i.base_reg = parse_register (base_string, &end_op))
7361 != NULL))
252b5132 7362 {
af6bdddf 7363 displacement_string_end = temp_string;
252b5132 7364
40fb9820 7365 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7366
af6bdddf 7367 if (i.base_reg)
24eab124 7368 {
24eab124
AM		 7369 base_string = end_op;
7370 if (is_space_char (*base_string))
7371 ++base_string;
af6bdddf
AM		 7372 }
7373
7374 /* There may be an index reg or scale factor here. */
7375 if (*base_string == ',')
7376 {
7377 ++base_string;
7378 if (is_space_char (*base_string))
7379 ++base_string;
7380
4eed87de
AM		 7381 if ((i.index_reg = parse_register (base_string, &end_op))
7382 != NULL)
24eab124 7383 {
af6bdddf 7384 base_string = end_op;
24eab124
AM		 7385 if (is_space_char (*base_string))
7386 ++base_string;
af6bdddf
AM		 7387 if (*base_string == ',')
7388 {
7389 ++base_string;
7390 if (is_space_char (*base_string))
7391 ++base_string;
7392 }
e5cb08ac 7393 else if (*base_string != ')')
af6bdddf 7394 {
4eed87de
AM		 7395 as_bad (_("expecting `,' or `)' "
7396 "after index register in `%s'"),
af6bdddf
AM		 7397 operand_string);
7398 return 0;
7399 }
24eab124 7400 }
af6bdddf 7401 else if (*base_string == REGISTER_PREFIX)
24eab124 7402 {
af6bdddf 7403 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7404 return 0;
7405 }
252b5132 7406
47926f60 7407 /* Check for scale factor. */
551c1ca1 7408 if (*base_string != ')')
af6bdddf 7409 {
551c1ca1
AM		 7410 char *end_scale = i386_scale (base_string);
7411
7412 if (!end_scale)
af6bdddf 7413 return 0;
24eab124 7414
551c1ca1 7415 base_string = end_scale;
af6bdddf
AM		 7416 if (is_space_char (*base_string))
7417 ++base_string;
7418 if (*base_string != ')')
7419 {
4eed87de
AM		 7420 as_bad (_("expecting `)' "
7421 "after scale factor in `%s'"),
af6bdddf
AM		 7422 operand_string);
7423 return 0;
7424 }
7425 }
7426 else if (!i.index_reg)
24eab124 7427 {
4eed87de
AM		 7428 as_bad (_("expecting index register or scale factor "
7429 "after `,'; got '%c'"),
af6bdddf 7430 *base_string);
24eab124
AM		 7431 return 0;
7432 }
7433 }
af6bdddf 7434 else if (*base_string != ')')
24eab124 7435 {
4eed87de
AM		 7436 as_bad (_("expecting `,' or `)' "
7437 "after base register in `%s'"),
af6bdddf 7438 operand_string);
24eab124
AM		 7439 return 0;
7440 }
c3332e24 7441 }
af6bdddf 7442 else if (*base_string == REGISTER_PREFIX)
c3332e24 7443 {
af6bdddf 7444 as_bad (_("bad register name `%s'"), base_string);
24eab124 7445 return 0;
c3332e24 7446 }
24eab124
AM		 7447 }
7448
7449 /* If there's an expression beginning the operand, parse it,
7450 assuming displacement_string_start and
7451 displacement_string_end are meaningful. */
7452 if (displacement_string_start != displacement_string_end)
7453 {
7454 if (!i386_displacement (displacement_string_start,
7455 displacement_string_end))
7456 return 0;
7457 }
7458
7459 /* Special case for (%dx) while doing input/output op. */
7460 if (i.base_reg
0dfbf9d7
L		 7461 && operand_type_equal (&i.base_reg->reg_type,
7462 &reg16_inoutportreg)
24eab124
AM		 7463 && i.index_reg == 0
7464 && i.log2_scale_factor == 0
7465 && i.seg[i.mem_operands] == 0
40fb9820 7466 && !operand_type_check (i.types[this_operand], disp))
24eab124 7467 {
65da13b5 7468 i.types[this_operand] = inoutportreg;
24eab124
AM		 7469 return 1;
7470 }
7471
eecb386c
AM		 7472 if (i386_index_check (operand_string) == 0)
7473 return 0;
5c07affc 7474 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7475 i.mem_operands++;
7476 }
7477 else
ce8a8b2f
AM		 7478 {
7479 /* It's not a memory operand; argh! */
24eab124
AM		 7480 as_bad (_("invalid char %s beginning operand %d `%s'"),
7481 output_invalid (*op_string),
7482 this_operand + 1,
7483 op_string);
7484 return 0;
7485 }
47926f60 7486 return 1; /* Normal return. */
252b5132
RH		 7487}
7488\f
ee7fcc42
AM		 7489/* md_estimate_size_before_relax()
7490
7491 Called just before relax() for rs_machine_dependent frags. The x86
7492 assembler uses these frags to handle variable size jump
7493 instructions.
7494
7495 Any symbol that is now undefined will not become defined.
7496 Return the correct fr_subtype in the frag.
7497 Return the initial "guess for variable size of frag" to caller.
7498 The guess is actually the growth beyond the fixed part. Whatever
7499 we do to grow the fixed or variable part contributes to our
7500 returned value. */
7501
252b5132
RH		 7502int
7503md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7504 fragS *fragP;
7505 segT segment;
252b5132 7506{
252b5132 7507 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7508 check for un-relaxable symbols. On an ELF system, we can't relax
7509 an externally visible symbol, because it may be overridden by a
7510 shared library. */
7511 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7512#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7513 || (IS_ELF
31312f95 7514 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7515 || S_IS_WEAK (fragP->fr_symbol)
7516 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7517 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7518#endif
7519#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7520 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7521 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7522#endif
7523 )
252b5132 7524 {
b98ef147
AM		 7525 /* Symbol is undefined in this segment, or we need to keep a
7526 reloc so that weak symbols can be overridden. */
7527 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7528 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7529 unsigned char *opcode;
7530 int old_fr_fix;
f6af82bd 7531
ee7fcc42 7532 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7533 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7534 else if (size == 2)
f6af82bd
AM		 7535 reloc_type = BFD_RELOC_16_PCREL;
7536 else
7537 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7538
ee7fcc42
AM		 7539 old_fr_fix = fragP->fr_fix;
7540 opcode = (unsigned char *) fragP->fr_opcode;
7541
fddf5b5b 7542 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7543 {
fddf5b5b
AM		 7544 case UNCOND_JUMP:
7545 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7546 opcode[0] = 0xe9;
252b5132 7547 fragP->fr_fix += size;
062cd5e7
AS		 7548 fix_new (fragP, old_fr_fix, size,
7549 fragP->fr_symbol,
7550 fragP->fr_offset, 1,
7551 reloc_type);
252b5132
RH		 7552 break;
7553
fddf5b5b 7554 case COND_JUMP86:
412167cb
AM		 7555 if (size == 2
7556 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7557 {
7558 /* Negate the condition, and branch past an
7559 unconditional jump. */
7560 opcode[0] ^= 1;
7561 opcode[1] = 3;
7562 /* Insert an unconditional jump. */
7563 opcode[2] = 0xe9;
7564 /* We added two extra opcode bytes, and have a two byte
7565 offset. */
7566 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7567 fix_new (fragP, old_fr_fix + 2, 2,
7568 fragP->fr_symbol,
7569 fragP->fr_offset, 1,
7570 reloc_type);
fddf5b5b
AM		 7571 break;
7572 }
7573 /* Fall through. */
7574
7575 case COND_JUMP:
412167cb
AM		 7576 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7577 {
3e02c1cc
AM		 7578 fixS *fixP;
7579
412167cb 7580 fragP->fr_fix += 1;
3e02c1cc
AM		 7581 fixP = fix_new (fragP, old_fr_fix, 1,
7582 fragP->fr_symbol,
7583 fragP->fr_offset, 1,
7584 BFD_RELOC_8_PCREL);
7585 fixP->fx_signed = 1;
412167cb
AM		 7586 break;
7587 }
93c2a809 7588
24eab124 7589 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7590 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7591 opcode[1] = opcode[0] + 0x10;
f6af82bd 7592 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7593 /* We've added an opcode byte. */
7594 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7595 fix_new (fragP, old_fr_fix + 1, size,
7596 fragP->fr_symbol,
7597 fragP->fr_offset, 1,
7598 reloc_type);
252b5132 7599 break;
fddf5b5b
AM		 7600
7601 default:
7602 BAD_CASE (fragP->fr_subtype);
7603 break;
252b5132
RH		 7604 }
7605 frag_wane (fragP);
ee7fcc42 7606 return fragP->fr_fix - old_fr_fix;
252b5132 7607 }
93c2a809 7608
93c2a809
AM		 7609 /* Guess size depending on current relax state. Initially the relax
7610 state will correspond to a short jump and we return 1, because
7611 the variable part of the frag (the branch offset) is one byte
7612 long. However, we can relax a section more than once and in that
7613 case we must either set fr_subtype back to the unrelaxed state,
7614 or return the value for the appropriate branch. */
7615 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7616}
7617
47926f60
KH		 7618/* Called after relax() is finished.
7619
7620 In: Address of frag.
7621 fr_type == rs_machine_dependent.
7622 fr_subtype is what the address relaxed to.
7623
7624 Out: Any fixSs and constants are set up.
7625 Caller will turn frag into a ".space 0". */
7626
252b5132
RH		 7627void
7628md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7629 bfd *abfd ATTRIBUTE_UNUSED;
7630 segT sec ATTRIBUTE_UNUSED;
29b0f896 7631 fragS *fragP;
252b5132 7632{
29b0f896 7633 unsigned char *opcode;
252b5132 7634 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7635 offsetT target_address;
7636 offsetT opcode_address;
252b5132 7637 unsigned int extension = 0;
847f7ad4 7638 offsetT displacement_from_opcode_start;
252b5132
RH		 7639
7640 opcode = (unsigned char *) fragP->fr_opcode;
7641
47926f60 7642 /* Address we want to reach in file space. */
252b5132 7643 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7644
47926f60 7645 /* Address opcode resides at in file space. */
252b5132
RH		 7646 opcode_address = fragP->fr_address + fragP->fr_fix;
7647
47926f60 7648 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7649 displacement_from_opcode_start = target_address - opcode_address;
7650
fddf5b5b 7651 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7652 {
47926f60
KH		 7653 /* Don't have to change opcode. */
7654 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7655 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7656 }
7657 else
7658 {
7659 if (no_cond_jump_promotion
7660 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7661 as_warn_where (fragP->fr_file, fragP->fr_line,
7662 _("long jump required"));
252b5132 7663
fddf5b5b
AM		 7664 switch (fragP->fr_subtype)
7665 {
7666 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7667 extension = 4; /* 1 opcode + 4 displacement */
7668 opcode[0] = 0xe9;
7669 where_to_put_displacement = &opcode[1];
7670 break;
252b5132 7671
fddf5b5b
AM		 7672 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7673 extension = 2; /* 1 opcode + 2 displacement */
7674 opcode[0] = 0xe9;
7675 where_to_put_displacement = &opcode[1];
7676 break;
252b5132 7677
fddf5b5b
AM		 7678 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7679 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7680 extension = 5; /* 2 opcode + 4 displacement */
7681 opcode[1] = opcode[0] + 0x10;
7682 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7683 where_to_put_displacement = &opcode[2];
7684 break;
252b5132 7685
fddf5b5b
AM		 7686 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7687 extension = 3; /* 2 opcode + 2 displacement */
7688 opcode[1] = opcode[0] + 0x10;
7689 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7690 where_to_put_displacement = &opcode[2];
7691 break;
252b5132 7692
fddf5b5b
AM		 7693 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7694 extension = 4;
7695 opcode[0] ^= 1;
7696 opcode[1] = 3;
7697 opcode[2] = 0xe9;
7698 where_to_put_displacement = &opcode[3];
7699 break;
7700
7701 default:
7702 BAD_CASE (fragP->fr_subtype);
7703 break;
7704 }
252b5132 7705 }
fddf5b5b 7706
7b81dfbb
AJ		 7707 /* If size if less then four we are sure that the operand fits,
7708 but if it's 4, then it could be that the displacement is larger
7709 then -/+ 2GB. */
7710 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7711 && object_64bit
7712 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7713 + ((addressT) 1 << 31))
7714 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7715 {
7716 as_bad_where (fragP->fr_file, fragP->fr_line,
7717 _("jump target out of range"));
7718 /* Make us emit 0. */
7719 displacement_from_opcode_start = extension;
7720 }
47926f60 7721 /* Now put displacement after opcode. */
252b5132
RH		 7722 md_number_to_chars ((char *) where_to_put_displacement,
7723 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7724 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7725 fragP->fr_fix += extension;
7726}
7727\f
252b5132
RH		 7728/* Apply a fixup (fixS) to segment data, once it has been determined
7729 by our caller that we have all the info we need to fix it up.
7730
7731 On the 386, immediates, displacements, and data pointers are all in
7732 the same (little-endian) format, so we don't need to care about which
7733 we are handling. */
7734
94f592af 7735void
55cf6793 7736md_apply_fix (fixP, valP, seg)
47926f60
KH		 7737 /* The fix we're to put in. */
7738 fixS *fixP;
47926f60 7739 /* Pointer to the value of the bits. */
c6682705 7740 valueT *valP;
47926f60
KH		 7741 /* Segment fix is from. */
7742 segT seg ATTRIBUTE_UNUSED;
252b5132 7743{
94f592af 7744 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7745 valueT value = *valP;
252b5132 7746
f86103b7 7747#if !defined (TE_Mach)
93382f6d
AM		 7748 if (fixP->fx_pcrel)
7749 {
7750 switch (fixP->fx_r_type)
7751 {
5865bb77
ILT		 7752 default:
7753 break;
7754
d6ab8113
JB		 7755 case BFD_RELOC_64:
7756 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7757 break;
93382f6d 7758 case BFD_RELOC_32:
ae8887b5 7759 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7760 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7761 break;
7762 case BFD_RELOC_16:
7763 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7764 break;
7765 case BFD_RELOC_8:
7766 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7767 break;
7768 }
7769 }
252b5132 7770
a161fe53 7771 if (fixP->fx_addsy != NULL
31312f95 7772 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7773 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7774 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7775 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7776 && !use_rela_relocations)
252b5132 7777 {
31312f95
AM		 7778 /* This is a hack. There should be a better way to handle this.
7779 This covers for the fact that bfd_install_relocation will
7780 subtract the current location (for partial_inplace, PC relative
7781 relocations); see more below. */
252b5132 7782#ifndef OBJ_AOUT
718ddfc0 7783 if (IS_ELF
252b5132
RH		 7784#ifdef TE_PE
7785 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7786#endif
7787 )
7788 value += fixP->fx_where + fixP->fx_frag->fr_address;
7789#endif
7790#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7791 if (IS_ELF)
252b5132 7792 {
6539b54b 7793 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7794
6539b54b 7795 if ((sym_seg == seg
2f66722d 7796 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7797 && sym_seg != absolute_section))
af65af87 7798 && !generic_force_reloc (fixP))
2f66722d
AM		 7799 {
7800 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7801 bfd_install_relocation subtracts them out again. I think
7802 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7803 it. FIXME. */
7804 value += fixP->fx_where + fixP->fx_frag->fr_address;
7805 }
252b5132
RH		 7806 }
7807#endif
7808#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7809 /* For some reason, the PE format does not store a
7810 section address offset for a PC relative symbol. */
7811 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7812 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7813 value += md_pcrel_from (fixP);
7814#endif
7815 }
fbeb56a4
DK		 7816#if defined (OBJ_COFF) && defined (TE_PE)
7817 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7818 {
7819 value -= S_GET_VALUE (fixP->fx_addsy);
7820 }
7821#endif
252b5132
RH		 7822
7823 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7824 and we must not disappoint it. */
252b5132 7825#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7826 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7827 switch (fixP->fx_r_type)
7828 {
7829 case BFD_RELOC_386_PLT32:
3e73aa7c 7830 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7831 /* Make the jump instruction point to the address of the operand. At
7832 runtime we merely add the offset to the actual PLT entry. */
7833 value = -4;
7834 break;
31312f95 7835
13ae64f3
JJ		 7836 case BFD_RELOC_386_TLS_GD:
7837 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7838 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7839 case BFD_RELOC_386_TLS_IE:
7840 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7841 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7842 case BFD_RELOC_X86_64_TLSGD:
7843 case BFD_RELOC_X86_64_TLSLD:
7844 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7845 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7846 value = 0; /* Fully resolved at runtime. No addend. */
7847 /* Fallthrough */
7848 case BFD_RELOC_386_TLS_LE:
7849 case BFD_RELOC_386_TLS_LDO_32:
7850 case BFD_RELOC_386_TLS_LE_32:
7851 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7852 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7853 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7854 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7855 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7856 break;
7857
67a4f2b7
AO		 7858 case BFD_RELOC_386_TLS_DESC_CALL:
7859 case BFD_RELOC_X86_64_TLSDESC_CALL:
7860 value = 0; /* Fully resolved at runtime. No addend. */
7861 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7862 fixP->fx_done = 0;
7863 return;
7864
00f7efb6
JJ		 7865 case BFD_RELOC_386_GOT32:
7866 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7867 value = 0; /* Fully resolved at runtime. No addend. */
7868 break;
47926f60
KH		 7869
7870 case BFD_RELOC_VTABLE_INHERIT:
7871 case BFD_RELOC_VTABLE_ENTRY:
7872 fixP->fx_done = 0;
94f592af 7873 return;
47926f60
KH		 7874
7875 default:
7876 break;
7877 }
7878#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7879 *valP = value;
f86103b7 7880#endif /* !defined (TE_Mach) */
3e73aa7c 7881
3e73aa7c 7882 /* Are we finished with this relocation now? */
c6682705 7883 if (fixP->fx_addsy == NULL)
3e73aa7c 7884 fixP->fx_done = 1;
fbeb56a4
DK		 7885#if defined (OBJ_COFF) && defined (TE_PE)
7886 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7887 {
7888 fixP->fx_done = 0;
7889 /* Remember value for tc_gen_reloc. */
7890 fixP->fx_addnumber = value;
7891 /* Clear out the frag for now. */
7892 value = 0;
7893 }
7894#endif
3e73aa7c
JH		 7895 else if (use_rela_relocations)
7896 {
7897 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7898 /* Remember value for tc_gen_reloc. */
7899 fixP->fx_addnumber = value;
3e73aa7c
JH		 7900 value = 0;
7901 }
f86103b7 7902
94f592af 7903 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7904}
252b5132 7905\f
252b5132 7906char *
499ac353 7907md_atof (int type, char *litP, int *sizeP)
252b5132 7908{
499ac353
NC		 7909 /* This outputs the LITTLENUMs in REVERSE order;
7910 in accord with the bigendian 386. */
7911 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7912}
7913\f
2d545b82 7914static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7915
252b5132 7916static char *
e3bb37b5 7917output_invalid (int c)
252b5132 7918{
3882b010 7919 if (ISPRINT (c))
f9f21a03
L		 7920 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7921 "'%c'", c);
252b5132 7922 else
f9f21a03 7923 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7924 "(0x%x)", (unsigned char) c);
252b5132
RH		 7925 return output_invalid_buf;
7926}
7927
af6bdddf 7928/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7929
7930static const reg_entry *
4d1bb795 7931parse_real_register (char *reg_string, char **end_op)
252b5132 7932{
af6bdddf
AM		 7933 char *s = reg_string;
7934 char *p;
252b5132
RH		 7935 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7936 const reg_entry *r;
7937
7938 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7939 if (*s == REGISTER_PREFIX)
7940 ++s;
7941
7942 if (is_space_char (*s))
7943 ++s;
7944
7945 p = reg_name_given;
af6bdddf 7946 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7947 {
7948 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7949 return (const reg_entry *) NULL;
7950 s++;
252b5132
RH		 7951 }
7952
6588847e
DN		 7953 /* For naked regs, make sure that we are not dealing with an identifier.
7954 This prevents confusing an identifier like `eax_var' with register
7955 `eax'. */
7956 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7957 return (const reg_entry *) NULL;
7958
af6bdddf 7959 *end_op = s;
252b5132
RH		 7960
7961 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7962
5f47d35b 7963 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7964 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7965 {
5f47d35b
AM		 7966 if (is_space_char (*s))
7967 ++s;
7968 if (*s == '(')
7969 {
af6bdddf 7970 ++s;
5f47d35b
AM		 7971 if (is_space_char (*s))
7972 ++s;
7973 if (*s >= '0' && *s <= '7')
7974 {
db557034 7975 int fpr = *s - '0';
af6bdddf 7976 ++s;
5f47d35b
AM		 7977 if (is_space_char (*s))
7978 ++s;
7979 if (*s == ')')
7980 {
7981 *end_op = s + 1;
1e9cc1c2 7982 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7983 know (r);
7984 return r + fpr;
5f47d35b 7985 }
5f47d35b 7986 }
47926f60 7987 /* We have "%st(" then garbage. */
5f47d35b
AM		 7988 return (const reg_entry *) NULL;
7989 }
7990 }
7991
a60de03c
JB		 7992 if (r == NULL || allow_pseudo_reg)
7993 return r;
7994
0dfbf9d7 7995 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7996 return (const reg_entry *) NULL;
7997
192dc9c6
JB		 7998 if ((r->reg_type.bitfield.reg32
7999 || r->reg_type.bitfield.sreg3
8000 || r->reg_type.bitfield.control
8001 || r->reg_type.bitfield.debug
8002 || r->reg_type.bitfield.test)
8003 && !cpu_arch_flags.bitfield.cpui386)
8004 return (const reg_entry *) NULL;
8005
309d3373
JB		 8006 if (r->reg_type.bitfield.floatreg
8007 && !cpu_arch_flags.bitfield.cpu8087
8008 && !cpu_arch_flags.bitfield.cpu287
8009 && !cpu_arch_flags.bitfield.cpu387)
8010 return (const reg_entry *) NULL;
8011
192dc9c6
JB		 8012 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8013 return (const reg_entry *) NULL;
8014
8015 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8016 return (const reg_entry *) NULL;
8017
40f12533
L		 8018 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8019 return (const reg_entry *) NULL;
8020
db51cc60 8021 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8022 if (!allow_index_reg
db51cc60
L		 8023 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8024 return (const reg_entry *) NULL;
8025
a60de03c
JB		 8026 if (((r->reg_flags & (RegRex64 | RegRex))
8027 || r->reg_type.bitfield.reg64)
40fb9820 8028 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8029 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8030 && flag_code != CODE_64BIT)
20f0a1fc 8031 return (const reg_entry *) NULL;
1ae00879 8032
b7240065
JB		 8033 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8034 return (const reg_entry *) NULL;
8035
252b5132
RH		 8036 return r;
8037}
4d1bb795
JB		 8038
8039/* REG_STRING starts *before* REGISTER_PREFIX. */
8040
8041static const reg_entry *
8042parse_register (char *reg_string, char **end_op)
8043{
8044 const reg_entry *r;
8045
8046 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8047 r = parse_real_register (reg_string, end_op);
8048 else
8049 r = NULL;
8050 if (!r)
8051 {
8052 char *save = input_line_pointer;
8053 char c;
8054 symbolS *symbolP;
8055
8056 input_line_pointer = reg_string;
8057 c = get_symbol_end ();
8058 symbolP = symbol_find (reg_string);
8059 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8060 {
8061 const expressionS *e = symbol_get_value_expression (symbolP);
8062
0398aac5 8063 know (e->X_op == O_register);
4eed87de 8064 know (e->X_add_number >= 0
c3fe08fa 8065 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8066 r = i386_regtab + e->X_add_number;
8067 *end_op = input_line_pointer;
8068 }
8069 *input_line_pointer = c;
8070 input_line_pointer = save;
8071 }
8072 return r;
8073}
8074
8075int
8076i386_parse_name (char *name, expressionS *e, char *nextcharP)
8077{
8078 const reg_entry *r;
8079 char *end = input_line_pointer;
8080
8081 *end = *nextcharP;
8082 r = parse_register (name, &input_line_pointer);
8083 if (r && end <= input_line_pointer)
8084 {
8085 *nextcharP = *input_line_pointer;
8086 *input_line_pointer = 0;
8087 e->X_op = O_register;
8088 e->X_add_number = r - i386_regtab;
8089 return 1;
8090 }
8091 input_line_pointer = end;
8092 *end = 0;
ee86248c 8093 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8094}
8095
8096void
8097md_operand (expressionS *e)
8098{
ee86248c
JB		 8099 char *end;
8100 const reg_entry *r;
4d1bb795 8101
ee86248c
JB		 8102 switch (*input_line_pointer)
8103 {
8104 case REGISTER_PREFIX:
8105 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8106 if (r)
8107 {
8108 e->X_op = O_register;
8109 e->X_add_number = r - i386_regtab;
8110 input_line_pointer = end;
8111 }
ee86248c
JB		 8112 break;
8113
8114 case '[':
9c2799c2 8115 gas_assert (intel_syntax);
ee86248c
JB		 8116 end = input_line_pointer++;
8117 expression (e);
8118 if (*input_line_pointer == ']')
8119 {
8120 ++input_line_pointer;
8121 e->X_op_symbol = make_expr_symbol (e);
8122 e->X_add_symbol = NULL;
8123 e->X_add_number = 0;
8124 e->X_op = O_index;
8125 }
8126 else
8127 {
8128 e->X_op = O_absent;
8129 input_line_pointer = end;
8130 }
8131 break;
4d1bb795
JB		 8132 }
8133}
8134
252b5132 8135\f
4cc782b5 8136#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8137const char *md_shortopts = "kVQ:sqn";
252b5132 8138#else
12b55ccc 8139const char *md_shortopts = "qn";
252b5132 8140#endif
6e0b89ee 8141
3e73aa7c 8142#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8143#define OPTION_64 (OPTION_MD_BASE + 1)
8144#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8145#define OPTION_MARCH (OPTION_MD_BASE + 3)
8146#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8147#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8148#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8149#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8150#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8151#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8152#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8153#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8154#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8155#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8156
99ad8390
NC		 8157struct option md_longopts[] =
8158{
3e73aa7c 8159 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8160#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8161 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8162 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8163#endif
8164#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8165 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8166#endif
b3b91714 8167 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8168 {"march", required_argument, NULL, OPTION_MARCH},
8169 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8170 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8171 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8172 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8173 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8174 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8175 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8176 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8177 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8178 {NULL, no_argument, NULL, 0}
8179};
8180size_t md_longopts_size = sizeof (md_longopts);
8181
8182int
9103f4f4 8183md_parse_option (int c, char *arg)
252b5132 8184{
91d6fa6a 8185 unsigned int j;
6305a203 8186 char *arch, *next;
9103f4f4 8187
252b5132
RH		 8188 switch (c)
8189 {
12b55ccc
L		 8190 case 'n':
8191 optimize_align_code = 0;
8192 break;
8193
a38cf1db
AM		 8194 case 'q':
8195 quiet_warnings = 1;
252b5132
RH		 8196 break;
8197
8198#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8199 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8200 should be emitted or not. FIXME: Not implemented. */
8201 case 'Q':
252b5132
RH		 8202 break;
8203
8204 /* -V: SVR4 argument to print version ID. */
8205 case 'V':
8206 print_version_id ();
8207 break;
8208
a38cf1db
AM		 8209 /* -k: Ignore for FreeBSD compatibility. */
8210 case 'k':
252b5132 8211 break;
4cc782b5
ILT		 8212
8213 case 's':
8214 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8215 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8216 break;
99ad8390 8217#endif
321098a5
L		 8218#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8219 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8220 case OPTION_64:
8221 {
8222 const char **list, **l;
8223
3e73aa7c
JH		 8224 list = bfd_target_list ();
8225 for (l = list; *l != NULL; l++)
8620418b 8226 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8227 || strcmp (*l, "coff-x86-64") == 0
8228 || strcmp (*l, "pe-x86-64") == 0
8229 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8230 {
8231 default_arch = "x86_64";
8232 break;
8233 }
3e73aa7c 8234 if (*l == NULL)
6e0b89ee 8235 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8236 free (list);
8237 }
8238 break;
8239#endif
252b5132 8240
351f65ca 8241#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8242 case OPTION_X32:
351f65ca
L		 8243 if (IS_ELF)
8244 {
8245 const char **list, **l;
8246
8247 list = bfd_target_list ();
8248 for (l = list; *l != NULL; l++)
8249 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8250 {
8251 default_arch = "x86_64:32";
8252 break;
8253 }
8254 if (*l == NULL)
8255 as_fatal (_("No compiled in support for 32bit x86_64"));
8256 free (list);
8257 }
8258 else
8259 as_fatal (_("32bit x86_64 is only supported for ELF"));
8260 break;
8261#endif
8262
6e0b89ee
AM		 8263 case OPTION_32:
8264 default_arch = "i386";
8265 break;
8266
b3b91714
AM		 8267 case OPTION_DIVIDE:
8268#ifdef SVR4_COMMENT_CHARS
8269 {
8270 char *n, *t;
8271 const char *s;
8272
8273 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8274 t = n;
8275 for (s = i386_comment_chars; *s != '\0'; s++)
8276 if (*s != '/')
8277 *t++ = *s;
8278 *t = '\0';
8279 i386_comment_chars = n;
8280 }
8281#endif
8282 break;
8283
9103f4f4 8284 case OPTION_MARCH:
6305a203
L		 8285 arch = xstrdup (arg);
8286 do
9103f4f4 8287 {
6305a203
L		 8288 if (*arch == '.')
8289 as_fatal (_("Invalid -march= option: `%s'"), arg);
8290 next = strchr (arch, '+');
8291 if (next)
8292 *next++ = '\0';
91d6fa6a 8293 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8294 {
91d6fa6a 8295 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8296 {
6305a203 8297 /* Processor. */
1ded5609
JB		 8298 if (! cpu_arch[j].flags.bitfield.cpui386)
8299 continue;
8300
91d6fa6a 8301 cpu_arch_name = cpu_arch[j].name;
6305a203 8302 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8303 cpu_arch_flags = cpu_arch[j].flags;
8304 cpu_arch_isa = cpu_arch[j].type;
8305 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8306 if (!cpu_arch_tune_set)
8307 {
8308 cpu_arch_tune = cpu_arch_isa;
8309 cpu_arch_tune_flags = cpu_arch_isa_flags;
8310 }
8311 break;
8312 }
91d6fa6a
NC		 8313 else if (*cpu_arch [j].name == '.'
8314 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8315 {
8316 /* ISA entension. */
8317 i386_cpu_flags flags;
309d3373 8318
49021df2 8319 if (!cpu_arch[j].negated)
309d3373 8320 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8321 cpu_arch[j].flags);
309d3373
JB		 8322 else
8323 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8324 cpu_arch[j].flags);
0dfbf9d7 8325 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8326 {
8327 if (cpu_sub_arch_name)
8328 {
8329 char *name = cpu_sub_arch_name;
8330 cpu_sub_arch_name = concat (name,
91d6fa6a 8331 cpu_arch[j].name,
1bf57e9f 8332 (const char *) NULL);
6305a203
L		 8333 free (name);
8334 }
8335 else
91d6fa6a 8336 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8337 cpu_arch_flags = flags;
8338 }
8339 break;
ccc9c027 8340 }
9103f4f4 8341 }
6305a203 8342
91d6fa6a 8343 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8344 as_fatal (_("Invalid -march= option: `%s'"), arg);
8345
8346 arch = next;
9103f4f4 8347 }
6305a203 8348 while (next != NULL );
9103f4f4
L		 8349 break;
8350
8351 case OPTION_MTUNE:
8352 if (*arg == '.')
8353 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8354 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8355 {
91d6fa6a 8356 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8357 {
ccc9c027 8358 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8359 cpu_arch_tune = cpu_arch [j].type;
8360 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8361 break;
8362 }
8363 }
91d6fa6a 8364 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8365 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8366 break;
8367
1efbbeb4
L		 8368 case OPTION_MMNEMONIC:
8369 if (strcasecmp (arg, "att") == 0)
8370 intel_mnemonic = 0;
8371 else if (strcasecmp (arg, "intel") == 0)
8372 intel_mnemonic = 1;
8373 else
8374 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8375 break;
8376
8377 case OPTION_MSYNTAX:
8378 if (strcasecmp (arg, "att") == 0)
8379 intel_syntax = 0;
8380 else if (strcasecmp (arg, "intel") == 0)
8381 intel_syntax = 1;
8382 else
8383 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8384 break;
8385
8386 case OPTION_MINDEX_REG:
8387 allow_index_reg = 1;
8388 break;
8389
8390 case OPTION_MNAKED_REG:
8391 allow_naked_reg = 1;
8392 break;
8393
8394 case OPTION_MOLD_GCC:
8395 old_gcc = 1;
1efbbeb4
L		 8396 break;
8397
c0f3af97
L		 8398 case OPTION_MSSE2AVX:
8399 sse2avx = 1;
8400 break;
8401
daf50ae7
L		 8402 case OPTION_MSSE_CHECK:
8403 if (strcasecmp (arg, "error") == 0)
8404 sse_check = sse_check_error;
8405 else if (strcasecmp (arg, "warning") == 0)
8406 sse_check = sse_check_warning;
8407 else if (strcasecmp (arg, "none") == 0)
8408 sse_check = sse_check_none;
8409 else
8410 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8411 break;
8412
539f890d
L		 8413 case OPTION_MAVXSCALAR:
8414 if (strcasecmp (arg, "128") == 0)
8415 avxscalar = vex128;
8416 else if (strcasecmp (arg, "256") == 0)
8417 avxscalar = vex256;
8418 else
8419 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8420 break;
8421
252b5132
RH		 8422 default:
8423 return 0;
8424 }
8425 return 1;
8426}
8427
8a2c8fef
L		 8428#define MESSAGE_TEMPLATE \
8429" "
8430
8431static void
1ded5609 8432show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8433{
8434 static char message[] = MESSAGE_TEMPLATE;
8435 char *start = message + 27;
8436 char *p;
8437 int size = sizeof (MESSAGE_TEMPLATE);
8438 int left;
8439 const char *name;
8440 int len;
8441 unsigned int j;
8442
8443 p = start;
8444 left = size - (start - message);
8445 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8446 {
8447 /* Should it be skipped? */
8448 if (cpu_arch [j].skip)
8449 continue;
8450
8451 name = cpu_arch [j].name;
8452 len = cpu_arch [j].len;
8453 if (*name == '.')
8454 {
8455 /* It is an extension. Skip if we aren't asked to show it. */
8456 if (ext)
8457 {
8458 name++;
8459 len--;
8460 }
8461 else
8462 continue;
8463 }
8464 else if (ext)
8465 {
8466 /* It is an processor. Skip if we show only extension. */
8467 continue;
8468 }
1ded5609
JB		 8469 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8470 {
8471 /* It is an impossible processor - skip. */
8472 continue;
8473 }
8a2c8fef
L		 8474
8475 /* Reserve 2 spaces for ", " or ",\0" */
8476 left -= len + 2;
8477
8478 /* Check if there is any room. */
8479 if (left >= 0)
8480 {
8481 if (p != start)
8482 {
8483 *p++ = ',';
8484 *p++ = ' ';
8485 }
8486 p = mempcpy (p, name, len);
8487 }
8488 else
8489 {
8490 /* Output the current message now and start a new one. */
8491 *p++ = ',';
8492 *p = '\0';
8493 fprintf (stream, "%s\n", message);
8494 p = start;
8495 left = size - (start - message) - len - 2;
8496
8497 gas_assert (left >= 0);
8498
8499 p = mempcpy (p, name, len);
8500 }
8501 }
8502
8503 *p = '\0';
8504 fprintf (stream, "%s\n", message);
8505}
8506
252b5132 8507void
8a2c8fef 8508md_show_usage (FILE *stream)
252b5132 8509{
4cc782b5
ILT		 8510#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8511 fprintf (stream, _("\
a38cf1db
AM		 8512 -Q ignored\n\
8513 -V print assembler version number\n\
b3b91714
AM		 8514 -k ignored\n"));
8515#endif
8516 fprintf (stream, _("\
12b55ccc 8517 -n Do not optimize code alignment\n\
b3b91714
AM		 8518 -q quieten some warnings\n"));
8519#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8520 fprintf (stream, _("\
a38cf1db 8521 -s ignored\n"));
b3b91714 8522#endif
321098a5
L		 8523#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8524 || defined (TE_PE) || defined (TE_PEP))
751d281c 8525 fprintf (stream, _("\
570561f7 8526 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8527#endif
b3b91714
AM		 8528#ifdef SVR4_COMMENT_CHARS
8529 fprintf (stream, _("\
8530 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8531#else
8532 fprintf (stream, _("\
b3b91714 8533 --divide ignored\n"));
4cc782b5 8534#endif
9103f4f4 8535 fprintf (stream, _("\
6305a203 8536 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8537 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8538 show_arch (stream, 0, 1);
8a2c8fef
L		 8539 fprintf (stream, _("\
8540 EXTENSION is combination of:\n"));
1ded5609 8541 show_arch (stream, 1, 0);
6305a203 8542 fprintf (stream, _("\
8a2c8fef 8543 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8544 show_arch (stream, 0, 0);
ba104c83 8545 fprintf (stream, _("\
c0f3af97
L		 8546 -msse2avx encode SSE instructions with VEX prefix\n"));
8547 fprintf (stream, _("\
daf50ae7
L		 8548 -msse-check=[none|error|warning]\n\
8549 check SSE instructions\n"));
8550 fprintf (stream, _("\
539f890d
L		 8551 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8552 length\n"));
8553 fprintf (stream, _("\
ba104c83
L		 8554 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8555 fprintf (stream, _("\
8556 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8557 fprintf (stream, _("\
8558 -mindex-reg support pseudo index registers\n"));
8559 fprintf (stream, _("\
8560 -mnaked-reg don't require `%%' prefix for registers\n"));
8561 fprintf (stream, _("\
8562 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8563}
8564
3e73aa7c 8565#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8566 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8567 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8568
8569/* Pick the target format to use. */
8570
47926f60 8571const char *
e3bb37b5 8572i386_target_format (void)
252b5132 8573{
351f65ca
L		 8574 if (!strncmp (default_arch, "x86_64", 6))
8575 {
8576 update_code_flag (CODE_64BIT, 1);
8577 if (default_arch[6] == '\0')
8578 x86_elf_abi = X86_64_LP64_ABI;
8579 else
8580 x86_elf_abi = X86_64_ILP32_ABI;
8581 }
3e73aa7c 8582 else if (!strcmp (default_arch, "i386"))
78f12dd3 8583 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8584 else
8585 as_fatal (_("Unknown architecture"));
89507696
JB		 8586
8587 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8588 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8589 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8590 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8591
252b5132
RH		 8592 switch (OUTPUT_FLAVOR)
8593 {
9384f2ff 8594#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8595 case bfd_target_aout_flavour:
47926f60 8596 return AOUT_TARGET_FORMAT;
4c63da97 8597#endif
9384f2ff
AM		 8598#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8599# if defined (TE_PE) || defined (TE_PEP)
8600 case bfd_target_coff_flavour:
8601 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8602# elif defined (TE_GO32)
0561d57c
JK		 8603 case bfd_target_coff_flavour:
8604 return "coff-go32";
9384f2ff 8605# else
252b5132
RH		 8606 case bfd_target_coff_flavour:
8607 return "coff-i386";
9384f2ff 8608# endif
4c63da97 8609#endif
3e73aa7c 8610#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8611 case bfd_target_elf_flavour:
3e73aa7c 8612 {
351f65ca
L		 8613 const char *format;
8614
8615 switch (x86_elf_abi)
4fa24527 8616 {
351f65ca
L		 8617 default:
8618 format = ELF_TARGET_FORMAT;
8619 break;
8620 case X86_64_LP64_ABI:
8621 use_rela_relocations = 1;
4fa24527 8622 object_64bit = 1;
351f65ca
L		 8623 format = ELF_TARGET_FORMAT64;
8624 break;
8625 case X86_64_ILP32_ABI:
4fa24527 8626 use_rela_relocations = 1;
351f65ca
L		 8627 object_64bit = 1;
8628 format = ELF_TARGET_FORMAT32;
8629 break;
4fa24527 8630 }
3632d14b 8631 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8632 {
351f65ca 8633 if (x86_elf_abi != X86_64_LP64_ABI)
8a9036a4
L		 8634 as_fatal (_("Intel L1OM is 64bit only"));
8635 return ELF_TARGET_L1OM_FORMAT;
8636 }
8637 else
351f65ca 8638 return format;
3e73aa7c 8639 }
e57f8c65
TG		 8640#endif
8641#if defined (OBJ_MACH_O)
8642 case bfd_target_mach_o_flavour:
8643 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8644#endif
252b5132
RH		 8645 default:
8646 abort ();
8647 return NULL;
8648 }
8649}
8650
47926f60 8651#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8652
8653#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8654void
8655i386_elf_emit_arch_note (void)
a847613f 8656{
718ddfc0 8657 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8658 {
8659 char *p;
8660 asection *seg = now_seg;
8661 subsegT subseg = now_subseg;
8662 Elf_Internal_Note i_note;
8663 Elf_External_Note e_note;
8664 asection *note_secp;
8665 int len;
8666
8667 /* Create the .note section. */
8668 note_secp = subseg_new (".note", 0);
8669 bfd_set_section_flags (stdoutput,
8670 note_secp,
8671 SEC_HAS_CONTENTS | SEC_READONLY);
8672
8673 /* Process the arch string. */
8674 len = strlen (cpu_arch_name);
8675
8676 i_note.namesz = len + 1;
8677 i_note.descsz = 0;
8678 i_note.type = NT_ARCH;
8679 p = frag_more (sizeof (e_note.namesz));
8680 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8681 p = frag_more (sizeof (e_note.descsz));
8682 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8683 p = frag_more (sizeof (e_note.type));
8684 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8685 p = frag_more (len + 1);
8686 strcpy (p, cpu_arch_name);
8687
8688 frag_align (2, 0, 0);
8689
8690 subseg_set (seg, subseg);
8691 }
8692}
8693#endif
252b5132 8694\f
252b5132
RH		 8695symbolS *
8696md_undefined_symbol (name)
8697 char *name;
8698{
18dc2407
ILT		 8699 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8700 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8701 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8702 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8703 {
8704 if (!GOT_symbol)
8705 {
8706 if (symbol_find (name))
8707 as_bad (_("GOT already in symbol table"));
8708 GOT_symbol = symbol_new (name, undefined_section,
8709 (valueT) 0, &zero_address_frag);
8710 };
8711 return GOT_symbol;
8712 }
252b5132
RH		 8713 return 0;
8714}
8715
8716/* Round up a section size to the appropriate boundary. */
47926f60 8717
252b5132
RH		 8718valueT
8719md_section_align (segment, size)
ab9da554 8720 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8721 valueT size;
8722{
4c63da97
AM		 8723#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8724 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8725 {
8726 /* For a.out, force the section size to be aligned. If we don't do
8727 this, BFD will align it for us, but it will not write out the
8728 final bytes of the section. This may be a bug in BFD, but it is
8729 easier to fix it here since that is how the other a.out targets
8730 work. */
8731 int align;
8732
8733 align = bfd_get_section_alignment (stdoutput, segment);
8734 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8735 }
252b5132
RH		 8736#endif
8737
8738 return size;
8739}
8740
8741/* On the i386, PC-relative offsets are relative to the start of the
8742 next instruction. That is, the address of the offset, plus its
8743 size, since the offset is always the last part of the insn. */
8744
8745long
e3bb37b5 8746md_pcrel_from (fixS *fixP)
252b5132
RH		 8747{
8748 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8749}
8750
8751#ifndef I386COFF
8752
8753static void
e3bb37b5 8754s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8755{
29b0f896 8756 int temp;
252b5132 8757
8a75718c
JB		 8758#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8759 if (IS_ELF)
8760 obj_elf_section_change_hook ();
8761#endif
252b5132
RH		 8762 temp = get_absolute_expression ();
8763 subseg_set (bss_section, (subsegT) temp);
8764 demand_empty_rest_of_line ();
8765}
8766
8767#endif
8768
252b5132 8769void
e3bb37b5 8770i386_validate_fix (fixS *fixp)
252b5132
RH		 8771{
8772 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8773 {
23df1078
JH		 8774 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8775 {
4fa24527 8776 if (!object_64bit)
23df1078
JH		 8777 abort ();
8778 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8779 }
8780 else
8781 {
4fa24527 8782 if (!object_64bit)
d6ab8113
JB		 8783 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8784 else
8785 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8786 }
252b5132
RH		 8787 fixp->fx_subsy = 0;
8788 }
8789}
8790
252b5132
RH		 8791arelent *
8792tc_gen_reloc (section, fixp)
ab9da554 8793 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8794 fixS *fixp;
8795{
8796 arelent *rel;
8797 bfd_reloc_code_real_type code;
8798
8799 switch (fixp->fx_r_type)
8800 {
3e73aa7c
JH		 8801 case BFD_RELOC_X86_64_PLT32:
8802 case BFD_RELOC_X86_64_GOT32:
8803 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8804 case BFD_RELOC_386_PLT32:
8805 case BFD_RELOC_386_GOT32:
8806 case BFD_RELOC_386_GOTOFF:
8807 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8808 case BFD_RELOC_386_TLS_GD:
8809 case BFD_RELOC_386_TLS_LDM:
8810 case BFD_RELOC_386_TLS_LDO_32:
8811 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8812 case BFD_RELOC_386_TLS_IE:
8813 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8814 case BFD_RELOC_386_TLS_LE_32:
8815 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8816 case BFD_RELOC_386_TLS_GOTDESC:
8817 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8818 case BFD_RELOC_X86_64_TLSGD:
8819 case BFD_RELOC_X86_64_TLSLD:
8820 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8821 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8822 case BFD_RELOC_X86_64_GOTTPOFF:
8823 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8824 case BFD_RELOC_X86_64_TPOFF64:
8825 case BFD_RELOC_X86_64_GOTOFF64:
8826 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8827 case BFD_RELOC_X86_64_GOT64:
8828 case BFD_RELOC_X86_64_GOTPCREL64:
8829 case BFD_RELOC_X86_64_GOTPC64:
8830 case BFD_RELOC_X86_64_GOTPLT64:
8831 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8832 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8833 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8834 case BFD_RELOC_RVA:
8835 case BFD_RELOC_VTABLE_ENTRY:
8836 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8837#ifdef TE_PE
8838 case BFD_RELOC_32_SECREL:
8839#endif
252b5132
RH		 8840 code = fixp->fx_r_type;
8841 break;
dbbaec26
L		 8842 case BFD_RELOC_X86_64_32S:
8843 if (!fixp->fx_pcrel)
8844 {
8845 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8846 code = fixp->fx_r_type;
8847 break;
8848 }
252b5132 8849 default:
93382f6d 8850 if (fixp->fx_pcrel)
252b5132 8851 {
93382f6d
AM		 8852 switch (fixp->fx_size)
8853 {
8854 default:
b091f402
AM		 8855 as_bad_where (fixp->fx_file, fixp->fx_line,
8856 _("can not do %d byte pc-relative relocation"),
8857 fixp->fx_size);
93382f6d
AM		 8858 code = BFD_RELOC_32_PCREL;
8859 break;
8860 case 1: code = BFD_RELOC_8_PCREL; break;
8861 case 2: code = BFD_RELOC_16_PCREL; break;
8862 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8863#ifdef BFD64
8864 case 8: code = BFD_RELOC_64_PCREL; break;
8865#endif
93382f6d
AM		 8866 }
8867 }
8868 else
8869 {
8870 switch (fixp->fx_size)
8871 {
8872 default:
b091f402
AM		 8873 as_bad_where (fixp->fx_file, fixp->fx_line,
8874 _("can not do %d byte relocation"),
8875 fixp->fx_size);
93382f6d
AM		 8876 code = BFD_RELOC_32;
8877 break;
8878 case 1: code = BFD_RELOC_8; break;
8879 case 2: code = BFD_RELOC_16; break;
8880 case 4: code = BFD_RELOC_32; break;
937149dd 8881#ifdef BFD64
3e73aa7c 8882 case 8: code = BFD_RELOC_64; break;
937149dd 8883#endif
93382f6d 8884 }
252b5132
RH		 8885 }
8886 break;
8887 }
252b5132 8888
d182319b
JB		 8889 if ((code == BFD_RELOC_32
8890 || code == BFD_RELOC_32_PCREL
8891 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8892 && GOT_symbol
8893 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8894 {
4fa24527 8895 if (!object_64bit)
d6ab8113
JB		 8896 code = BFD_RELOC_386_GOTPC;
8897 else
8898 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8899 }
7b81dfbb
AJ		 8900 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8901 && GOT_symbol
8902 && fixp->fx_addsy == GOT_symbol)
8903 {
8904 code = BFD_RELOC_X86_64_GOTPC64;
8905 }
252b5132
RH		 8906
8907 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8908 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8909 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8910
8911 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8912
3e73aa7c
JH		 8913 if (!use_rela_relocations)
8914 {
8915 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8916 vtable entry to be used in the relocation's section offset. */
8917 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8918 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8919#if defined (OBJ_COFF) && defined (TE_PE)
8920 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8921 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8922 else
8923#endif
c6682705 8924 rel->addend = 0;
3e73aa7c
JH		 8925 }
8926 /* Use the rela in 64bit mode. */
252b5132 8927 else
3e73aa7c 8928 {
062cd5e7
AS		 8929 if (!fixp->fx_pcrel)
8930 rel->addend = fixp->fx_offset;
8931 else
8932 switch (code)
8933 {
8934 case BFD_RELOC_X86_64_PLT32:
8935 case BFD_RELOC_X86_64_GOT32:
8936 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8937 case BFD_RELOC_X86_64_TLSGD:
8938 case BFD_RELOC_X86_64_TLSLD:
8939 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8940 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8941 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8942 rel->addend = fixp->fx_offset - fixp->fx_size;
8943 break;
8944 default:
8945 rel->addend = (section->vma
8946 - fixp->fx_size
8947 + fixp->fx_addnumber
8948 + md_pcrel_from (fixp));
8949 break;
8950 }
3e73aa7c
JH		 8951 }
8952
252b5132
RH		 8953 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8954 if (rel->howto == NULL)
8955 {
8956 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8957 _("cannot represent relocation type %s"),
252b5132
RH		 8958 bfd_get_reloc_code_name (code));
8959 /* Set howto to a garbage value so that we can keep going. */
8960 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8961 gas_assert (rel->howto != NULL);
252b5132
RH		 8962 }
8963
8964 return rel;
8965}
8966
ee86248c 8967#include "tc-i386-intel.c"
54cfded0 8968
a60de03c
JB		 8969void
8970tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8971{
a60de03c
JB		 8972 int saved_naked_reg;
8973 char saved_register_dot;
54cfded0 8974
a60de03c
JB		 8975 saved_naked_reg = allow_naked_reg;
8976 allow_naked_reg = 1;
8977 saved_register_dot = register_chars['.'];
8978 register_chars['.'] = '.';
8979 allow_pseudo_reg = 1;
8980 expression_and_evaluate (exp);
8981 allow_pseudo_reg = 0;
8982 register_chars['.'] = saved_register_dot;
8983 allow_naked_reg = saved_naked_reg;
8984
e96d56a1 8985 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8986 {
a60de03c
JB		 8987 if ((addressT) exp->X_add_number < i386_regtab_size)
8988 {
8989 exp->X_op = O_constant;
8990 exp->X_add_number = i386_regtab[exp->X_add_number]
8991 .dw2_regnum[flag_code >> 1];
8992 }
8993 else
8994 exp->X_op = O_illegal;
54cfded0 8995 }
54cfded0
AM		 8996}
8997
8998void
8999tc_x86_frame_initial_instructions (void)
9000{
a60de03c
JB		 9001 static unsigned int sp_regno[2];
9002
9003 if (!sp_regno[flag_code >> 1])
9004 {
9005 char *saved_input = input_line_pointer;
9006 char sp[][4] = {"esp", "rsp"};
9007 expressionS exp;
a4447b93 9008
a60de03c
JB		 9009 input_line_pointer = sp[flag_code >> 1];
9010 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9011 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9012 sp_regno[flag_code >> 1] = exp.X_add_number;
9013 input_line_pointer = saved_input;
9014 }
a4447b93 9015
a60de03c 9016 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9017 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9018}
d2b2c203
DJ		 9019
9020int
9021i386_elf_section_type (const char *str, size_t len)
9022{
9023 if (flag_code == CODE_64BIT
9024 && len == sizeof ("unwind") - 1
9025 && strncmp (str, "unwind", 6) == 0)
9026 return SHT_X86_64_UNWIND;
9027
9028 return -1;
9029}
bb41ade5 9030
ad5fec3b
EB		 9031#ifdef TE_SOLARIS
9032void
9033i386_solaris_fix_up_eh_frame (segT sec)
9034{
9035 if (flag_code == CODE_64BIT)
9036 elf_section_type (sec) = SHT_X86_64_UNWIND;
9037}
9038#endif
9039
bb41ade5
AM		 9040#ifdef TE_PE
9041void
9042tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9043{
91d6fa6a 9044 expressionS exp;
bb41ade5 9045
91d6fa6a
NC		 9046 exp.X_op = O_secrel;
9047 exp.X_add_symbol = symbol;
9048 exp.X_add_number = 0;
9049 emit_expr (&exp, size);
bb41ade5
AM		 9050}
9051#endif
3b22753a
L		 9052
9053#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9054/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9055
01e1a5bc 9056bfd_vma
3b22753a
L		 9057x86_64_section_letter (int letter, char **ptr_msg)
9058{
9059 if (flag_code == CODE_64BIT)
9060 {
9061 if (letter == 'l')
9062 return SHF_X86_64_LARGE;
9063
8f3bae45 9064 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9065 }
3b22753a 9066 else
8f3bae45 9067 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9068 return -1;
9069}
9070
01e1a5bc 9071bfd_vma
3b22753a
L		 9072x86_64_section_word (char *str, size_t len)
9073{
8620418b 9074 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9075 return SHF_X86_64_LARGE;
9076
9077 return -1;
9078}
9079
9080static void
9081handle_large_common (int small ATTRIBUTE_UNUSED)
9082{
9083 if (flag_code != CODE_64BIT)
9084 {
9085 s_comm_internal (0, elf_common_parse);
9086 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9087 }
9088 else
9089 {
9090 static segT lbss_section;
9091 asection *saved_com_section_ptr = elf_com_section_ptr;
9092 asection *saved_bss_section = bss_section;
9093
9094 if (lbss_section == NULL)
9095 {
9096 flagword applicable;
9097 segT seg = now_seg;
9098 subsegT subseg = now_subseg;
9099
9100 /* The .lbss section is for local .largecomm symbols. */
9101 lbss_section = subseg_new (".lbss", 0);
9102 applicable = bfd_applicable_section_flags (stdoutput);
9103 bfd_set_section_flags (stdoutput, lbss_section,
9104 applicable & SEC_ALLOC);
9105 seg_info (lbss_section)->bss = 1;
9106
9107 subseg_set (seg, subseg);
9108 }
9109
9110 elf_com_section_ptr = &_bfd_elf_large_com_section;
9111 bss_section = lbss_section;
9112
9113 s_comm_internal (0, elf_common_parse);
9114
9115 elf_com_section_ptr = saved_com_section_ptr;
9116 bss_section = saved_bss_section;
9117 }
9118}
9119#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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