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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
b3adc24a | 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
c3332e24 | 47 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 48 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
49 | #endif |
50 | ||
29b0f896 AM |
51 | #ifndef DEFAULT_ARCH |
52 | #define DEFAULT_ARCH "i386" | |
246fcdee | 53 | #endif |
252b5132 | 54 | |
edde18a5 AM |
55 | #ifndef INLINE |
56 | #if __GNUC__ >= 2 | |
57 | #define INLINE __inline__ | |
58 | #else | |
59 | #define INLINE | |
60 | #endif | |
61 | #endif | |
62 | ||
6305a203 L |
63 | /* Prefixes will be emitted in the order defined below. |
64 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
65 | instruction, and so must come before any prefixes. | |
66 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 67 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
68 | #define WAIT_PREFIX 0 |
69 | #define SEG_PREFIX 1 | |
70 | #define ADDR_PREFIX 2 | |
71 | #define DATA_PREFIX 3 | |
c32fa91d | 72 | #define REP_PREFIX 4 |
42164a71 | 73 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 74 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 75 | #define LOCK_PREFIX 5 |
4e9ac44a L |
76 | #define REX_PREFIX 6 /* must come last. */ |
77 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
78 | |
79 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
80 | #define REGISTER_PREFIX '%' | |
81 | #define IMMEDIATE_PREFIX '$' | |
82 | #define ABSOLUTE_PREFIX '*' | |
83 | ||
84 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
85 | memory operand size in Intel syntax. */ | |
86 | #define WORD_MNEM_SUFFIX 'w' | |
87 | #define BYTE_MNEM_SUFFIX 'b' | |
88 | #define SHORT_MNEM_SUFFIX 's' | |
89 | #define LONG_MNEM_SUFFIX 'l' | |
90 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
91 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
92 | in instructions. */ | |
93 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
94 | ||
95 | #define END_OF_INSN '\0' | |
96 | ||
79dec6b7 JB |
97 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
98 | #define commutative staticrounding | |
99 | ||
6305a203 L |
100 | /* |
101 | 'templates' is for grouping together 'template' structures for opcodes | |
102 | of the same name. This is only used for storing the insns in the grand | |
103 | ole hash table of insns. | |
104 | The templates themselves start at START and range up to (but not including) | |
105 | END. | |
106 | */ | |
107 | typedef struct | |
108 | { | |
d3ce72d0 NC |
109 | const insn_template *start; |
110 | const insn_template *end; | |
6305a203 L |
111 | } |
112 | templates; | |
113 | ||
114 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
115 | typedef struct | |
116 | { | |
117 | unsigned int regmem; /* codes register or memory operand */ | |
118 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
119 | unsigned int mode; /* how to interpret regmem & reg */ | |
120 | } | |
121 | modrm_byte; | |
122 | ||
123 | /* x86-64 extension prefix. */ | |
124 | typedef int rex_byte; | |
125 | ||
6305a203 L |
126 | /* 386 opcode byte to code indirect addressing. */ |
127 | typedef struct | |
128 | { | |
129 | unsigned base; | |
130 | unsigned index; | |
131 | unsigned scale; | |
132 | } | |
133 | sib_byte; | |
134 | ||
6305a203 L |
135 | /* x86 arch names, types and features */ |
136 | typedef struct | |
137 | { | |
138 | const char *name; /* arch name */ | |
8a2c8fef | 139 | unsigned int len; /* arch string length */ |
6305a203 L |
140 | enum processor_type type; /* arch type */ |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 142 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
143 | } |
144 | arch_entry; | |
145 | ||
293f5f65 L |
146 | /* Used to turn off indicated flags. */ |
147 | typedef struct | |
148 | { | |
149 | const char *name; /* arch name */ | |
150 | unsigned int len; /* arch string length */ | |
151 | i386_cpu_flags flags; /* cpu feature flags */ | |
152 | } | |
153 | noarch_entry; | |
154 | ||
78f12dd3 | 155 | static void update_code_flag (int, int); |
e3bb37b5 L |
156 | static void set_code_flag (int); |
157 | static void set_16bit_gcc_code_flag (int); | |
158 | static void set_intel_syntax (int); | |
1efbbeb4 | 159 | static void set_intel_mnemonic (int); |
db51cc60 | 160 | static void set_allow_index_reg (int); |
7bab8ab5 | 161 | static void set_check (int); |
e3bb37b5 | 162 | static void set_cpu_arch (int); |
6482c264 | 163 | #ifdef TE_PE |
e3bb37b5 | 164 | static void pe_directive_secrel (int); |
6482c264 | 165 | #endif |
e3bb37b5 L |
166 | static void signed_cons (int); |
167 | static char *output_invalid (int c); | |
ee86248c JB |
168 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
169 | const char *); | |
170 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
171 | const char *); | |
a7619375 | 172 | static int i386_att_operand (char *); |
e3bb37b5 | 173 | static int i386_intel_operand (char *, int); |
ee86248c JB |
174 | static int i386_intel_simplify (expressionS *); |
175 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
176 | static const reg_entry *parse_register (char *, char **); |
177 | static char *parse_insn (char *, char *); | |
178 | static char *parse_operands (char *, const char *); | |
179 | static void swap_operands (void); | |
4d456e3d | 180 | static void swap_2_operands (int, int); |
48bcea9f | 181 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
50128d0c JB |
353 | /* Register is in low 3 bits of opcode. */ |
354 | bfd_boolean short_form; | |
355 | ||
6f2f06be JB |
356 | /* The operand to a branch insn indicates an absolute branch. */ |
357 | bfd_boolean jumpabsolute; | |
358 | ||
b4a3a7b4 L |
359 | /* Has MMX register operands. */ |
360 | bfd_boolean has_regmmx; | |
361 | ||
362 | /* Has XMM register operands. */ | |
363 | bfd_boolean has_regxmm; | |
364 | ||
365 | /* Has YMM register operands. */ | |
366 | bfd_boolean has_regymm; | |
367 | ||
368 | /* Has ZMM register operands. */ | |
369 | bfd_boolean has_regzmm; | |
370 | ||
e379e5f3 L |
371 | /* Has GOTPC or TLS relocation. */ |
372 | bfd_boolean has_gotpc_tls_reloc; | |
373 | ||
252b5132 | 374 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 375 | addressing modes of this insn are encoded. */ |
252b5132 | 376 | modrm_byte rm; |
3e73aa7c | 377 | rex_byte rex; |
43234a1e | 378 | rex_byte vrex; |
252b5132 | 379 | sib_byte sib; |
c0f3af97 | 380 | vex_prefix vex; |
b6169b20 | 381 | |
43234a1e L |
382 | /* Masking attributes. */ |
383 | struct Mask_Operation *mask; | |
384 | ||
385 | /* Rounding control and SAE attributes. */ | |
386 | struct RC_Operation *rounding; | |
387 | ||
388 | /* Broadcasting attributes. */ | |
389 | struct Broadcast_Operation *broadcast; | |
390 | ||
391 | /* Compressed disp8*N attribute. */ | |
392 | unsigned int memshift; | |
393 | ||
86fa6981 L |
394 | /* Prefer load or store in encoding. */ |
395 | enum | |
396 | { | |
397 | dir_encoding_default = 0, | |
398 | dir_encoding_load, | |
64c49ab3 JB |
399 | dir_encoding_store, |
400 | dir_encoding_swap | |
86fa6981 | 401 | } dir_encoding; |
891edac4 | 402 | |
a501d77e L |
403 | /* Prefer 8bit or 32bit displacement in encoding. */ |
404 | enum | |
405 | { | |
406 | disp_encoding_default = 0, | |
407 | disp_encoding_8bit, | |
408 | disp_encoding_32bit | |
409 | } disp_encoding; | |
f8a5c266 | 410 | |
6b6b6807 L |
411 | /* Prefer the REX byte in encoding. */ |
412 | bfd_boolean rex_encoding; | |
413 | ||
b6f8c7c4 L |
414 | /* Disable instruction size optimization. */ |
415 | bfd_boolean no_optimize; | |
416 | ||
86fa6981 L |
417 | /* How to encode vector instructions. */ |
418 | enum | |
419 | { | |
420 | vex_encoding_default = 0, | |
42e04b36 | 421 | vex_encoding_vex, |
86fa6981 L |
422 | vex_encoding_vex3, |
423 | vex_encoding_evex | |
424 | } vec_encoding; | |
425 | ||
d5de92cf L |
426 | /* REP prefix. */ |
427 | const char *rep_prefix; | |
428 | ||
165de32a L |
429 | /* HLE prefix. */ |
430 | const char *hle_prefix; | |
42164a71 | 431 | |
7e8b059b L |
432 | /* Have BND prefix. */ |
433 | const char *bnd_prefix; | |
434 | ||
04ef582a L |
435 | /* Have NOTRACK prefix. */ |
436 | const char *notrack_prefix; | |
437 | ||
891edac4 | 438 | /* Error message. */ |
a65babc9 | 439 | enum i386_error error; |
252b5132 RH |
440 | }; |
441 | ||
442 | typedef struct _i386_insn i386_insn; | |
443 | ||
43234a1e L |
444 | /* Link RC type with corresponding string, that'll be looked for in |
445 | asm. */ | |
446 | struct RC_name | |
447 | { | |
448 | enum rc_type type; | |
449 | const char *name; | |
450 | unsigned int len; | |
451 | }; | |
452 | ||
453 | static const struct RC_name RC_NamesTable[] = | |
454 | { | |
455 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
456 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
457 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
458 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
459 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
460 | }; | |
461 | ||
252b5132 RH |
462 | /* List of chars besides those in app.c:symbol_chars that can start an |
463 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 464 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 465 | #ifdef LEX_AT |
32137342 NC |
466 | "@" |
467 | #endif | |
468 | #ifdef LEX_QM | |
469 | "?" | |
252b5132 | 470 | #endif |
32137342 | 471 | ; |
252b5132 | 472 | |
29b0f896 AM |
473 | #if (defined (TE_I386AIX) \ |
474 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 475 | && !defined (TE_GNU) \ |
29b0f896 | 476 | && !defined (TE_LINUX) \ |
8d63c93e | 477 | && !defined (TE_NACL) \ |
29b0f896 | 478 | && !defined (TE_FreeBSD) \ |
5b806d27 | 479 | && !defined (TE_DragonFly) \ |
29b0f896 | 480 | && !defined (TE_NetBSD))) |
252b5132 | 481 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
482 | pre-processor is disabled, these aren't very useful. The option |
483 | --divide will remove '/' from this list. */ | |
484 | const char *i386_comment_chars = "#/"; | |
485 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 486 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 487 | |
b3b91714 AM |
488 | #else |
489 | const char *i386_comment_chars = "#"; | |
490 | #define PREFIX_SEPARATOR '/' | |
491 | #endif | |
492 | ||
252b5132 RH |
493 | /* This array holds the chars that only start a comment at the beginning of |
494 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
495 | .line and .file directives will appear in the pre-processed output. |
496 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 497 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
498 | #NO_APP at the beginning of its output. |
499 | Also note that comments started like this one will always work if | |
252b5132 | 500 | '/' isn't otherwise defined. */ |
b3b91714 | 501 | const char line_comment_chars[] = "#/"; |
252b5132 | 502 | |
63a0b638 | 503 | const char line_separator_chars[] = ";"; |
252b5132 | 504 | |
ce8a8b2f AM |
505 | /* Chars that can be used to separate mant from exp in floating point |
506 | nums. */ | |
252b5132 RH |
507 | const char EXP_CHARS[] = "eE"; |
508 | ||
ce8a8b2f AM |
509 | /* Chars that mean this number is a floating point constant |
510 | As in 0f12.456 | |
511 | or 0d1.2345e12. */ | |
252b5132 RH |
512 | const char FLT_CHARS[] = "fFdDxX"; |
513 | ||
ce8a8b2f | 514 | /* Tables for lexical analysis. */ |
252b5132 RH |
515 | static char mnemonic_chars[256]; |
516 | static char register_chars[256]; | |
517 | static char operand_chars[256]; | |
518 | static char identifier_chars[256]; | |
519 | static char digit_chars[256]; | |
520 | ||
ce8a8b2f | 521 | /* Lexical macros. */ |
252b5132 RH |
522 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
523 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
524 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
525 | #define is_space_char(x) ((x) == ' ') | |
526 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
527 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
528 | ||
0234cb7c | 529 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
530 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
531 | ||
532 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
533 | effect this we maintain a stack of saved characters that we've smashed | |
534 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 535 | assembler instruction). */ |
252b5132 | 536 | static char save_stack[32]; |
ce8a8b2f | 537 | static char *save_stack_p; |
252b5132 RH |
538 | #define END_STRING_AND_SAVE(s) \ |
539 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
540 | #define RESTORE_END_STRING(s) \ | |
541 | do { *(s) = *--save_stack_p; } while (0) | |
542 | ||
47926f60 | 543 | /* The instruction we're assembling. */ |
252b5132 RH |
544 | static i386_insn i; |
545 | ||
546 | /* Possible templates for current insn. */ | |
547 | static const templates *current_templates; | |
548 | ||
31b2323c L |
549 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
550 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
551 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 552 | |
47926f60 | 553 | /* Current operand we are working on. */ |
ee86248c | 554 | static int this_operand = -1; |
252b5132 | 555 | |
3e73aa7c JH |
556 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
557 | these. */ | |
558 | ||
559 | enum flag_code { | |
560 | CODE_32BIT, | |
561 | CODE_16BIT, | |
562 | CODE_64BIT }; | |
563 | ||
564 | static enum flag_code flag_code; | |
4fa24527 | 565 | static unsigned int object_64bit; |
862be3fb | 566 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 567 | static int use_rela_relocations = 0; |
e379e5f3 L |
568 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
569 | static const char *tls_get_addr; | |
3e73aa7c | 570 | |
7af8ed2d NC |
571 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
572 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
573 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
574 | ||
351f65ca L |
575 | /* The ELF ABI to use. */ |
576 | enum x86_elf_abi | |
577 | { | |
578 | I386_ABI, | |
7f56bc95 L |
579 | X86_64_ABI, |
580 | X86_64_X32_ABI | |
351f65ca L |
581 | }; |
582 | ||
583 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 584 | #endif |
351f65ca | 585 | |
167ad85b TG |
586 | #if defined (TE_PE) || defined (TE_PEP) |
587 | /* Use big object file format. */ | |
588 | static int use_big_obj = 0; | |
589 | #endif | |
590 | ||
8dcea932 L |
591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
592 | /* 1 if generating code for a shared library. */ | |
593 | static int shared = 0; | |
594 | #endif | |
595 | ||
47926f60 KH |
596 | /* 1 for intel syntax, |
597 | 0 if att syntax. */ | |
598 | static int intel_syntax = 0; | |
252b5132 | 599 | |
4b5aaf5f L |
600 | static enum x86_64_isa |
601 | { | |
602 | amd64 = 1, /* AMD64 ISA. */ | |
603 | intel64 /* Intel64 ISA. */ | |
604 | } isa64; | |
e89c5eaa | 605 | |
1efbbeb4 L |
606 | /* 1 for intel mnemonic, |
607 | 0 if att mnemonic. */ | |
608 | static int intel_mnemonic = !SYSV386_COMPAT; | |
609 | ||
a60de03c JB |
610 | /* 1 if pseudo registers are permitted. */ |
611 | static int allow_pseudo_reg = 0; | |
612 | ||
47926f60 KH |
613 | /* 1 if register prefix % not required. */ |
614 | static int allow_naked_reg = 0; | |
252b5132 | 615 | |
33eaf5de | 616 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
617 | instructions supporting it, even if this prefix wasn't specified |
618 | explicitly. */ | |
619 | static int add_bnd_prefix = 0; | |
620 | ||
ba104c83 | 621 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
622 | static int allow_index_reg = 0; |
623 | ||
d022bddd IT |
624 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
625 | specified explicitly. */ | |
626 | static int omit_lock_prefix = 0; | |
627 | ||
e4e00185 AS |
628 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
629 | "lock addl $0, (%{re}sp)". */ | |
630 | static int avoid_fence = 0; | |
631 | ||
e379e5f3 L |
632 | /* Type of the previous instruction. */ |
633 | static struct | |
634 | { | |
635 | segT seg; | |
636 | const char *file; | |
637 | const char *name; | |
638 | unsigned int line; | |
639 | enum last_insn_kind | |
640 | { | |
641 | last_insn_other = 0, | |
642 | last_insn_directive, | |
643 | last_insn_prefix | |
644 | } kind; | |
645 | } last_insn; | |
646 | ||
0cb4071e L |
647 | /* 1 if the assembler should generate relax relocations. */ |
648 | ||
649 | static int generate_relax_relocations | |
650 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
651 | ||
7bab8ab5 | 652 | static enum check_kind |
daf50ae7 | 653 | { |
7bab8ab5 JB |
654 | check_none = 0, |
655 | check_warning, | |
656 | check_error | |
daf50ae7 | 657 | } |
7bab8ab5 | 658 | sse_check, operand_check = check_warning; |
daf50ae7 | 659 | |
e379e5f3 L |
660 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
661 | static int align_branch_power = 0; | |
662 | ||
663 | /* Types of branches to align. */ | |
664 | enum align_branch_kind | |
665 | { | |
666 | align_branch_none = 0, | |
667 | align_branch_jcc = 1, | |
668 | align_branch_fused = 2, | |
669 | align_branch_jmp = 3, | |
670 | align_branch_call = 4, | |
671 | align_branch_indirect = 5, | |
672 | align_branch_ret = 6 | |
673 | }; | |
674 | ||
675 | /* Type bits of branches to align. */ | |
676 | enum align_branch_bit | |
677 | { | |
678 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
679 | align_branch_fused_bit = 1 << align_branch_fused, | |
680 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
681 | align_branch_call_bit = 1 << align_branch_call, | |
682 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
683 | align_branch_ret_bit = 1 << align_branch_ret | |
684 | }; | |
685 | ||
686 | static unsigned int align_branch = (align_branch_jcc_bit | |
687 | | align_branch_fused_bit | |
688 | | align_branch_jmp_bit); | |
689 | ||
79d72f45 HL |
690 | /* Types of condition jump used by macro-fusion. */ |
691 | enum mf_jcc_kind | |
692 | { | |
693 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
694 | mf_jcc_jc, /* base opcode 0x72 */ | |
695 | mf_jcc_je, /* base opcode 0x74 */ | |
696 | mf_jcc_jna, /* base opcode 0x76 */ | |
697 | mf_jcc_js, /* base opcode 0x78 */ | |
698 | mf_jcc_jp, /* base opcode 0x7a */ | |
699 | mf_jcc_jl, /* base opcode 0x7c */ | |
700 | mf_jcc_jle, /* base opcode 0x7e */ | |
701 | }; | |
702 | ||
703 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
704 | enum mf_cmp_kind | |
705 | { | |
706 | mf_cmp_test_and, /* test/cmp */ | |
707 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
708 | mf_cmp_incdec /* inc/dec */ | |
709 | }; | |
710 | ||
e379e5f3 L |
711 | /* The maximum padding size for fused jcc. CMP like instruction can |
712 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
713 | prefixes. */ | |
714 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
715 | ||
716 | /* The maximum number of prefixes added for an instruction. */ | |
717 | static unsigned int align_branch_prefix_size = 5; | |
718 | ||
b6f8c7c4 L |
719 | /* Optimization: |
720 | 1. Clear the REX_W bit with register operand if possible. | |
721 | 2. Above plus use 128bit vector instruction to clear the full vector | |
722 | register. | |
723 | */ | |
724 | static int optimize = 0; | |
725 | ||
726 | /* Optimization: | |
727 | 1. Clear the REX_W bit with register operand if possible. | |
728 | 2. Above plus use 128bit vector instruction to clear the full vector | |
729 | register. | |
730 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
731 | "testb $imm7,%r8". | |
732 | */ | |
733 | static int optimize_for_space = 0; | |
734 | ||
2ca3ace5 L |
735 | /* Register prefix used for error message. */ |
736 | static const char *register_prefix = "%"; | |
737 | ||
47926f60 KH |
738 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
739 | leave, push, and pop instructions so that gcc has the same stack | |
740 | frame as in 32 bit mode. */ | |
741 | static char stackop_size = '\0'; | |
eecb386c | 742 | |
12b55ccc L |
743 | /* Non-zero to optimize code alignment. */ |
744 | int optimize_align_code = 1; | |
745 | ||
47926f60 KH |
746 | /* Non-zero to quieten some warnings. */ |
747 | static int quiet_warnings = 0; | |
a38cf1db | 748 | |
47926f60 KH |
749 | /* CPU name. */ |
750 | static const char *cpu_arch_name = NULL; | |
6305a203 | 751 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 752 | |
47926f60 | 753 | /* CPU feature flags. */ |
40fb9820 L |
754 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
755 | ||
ccc9c027 L |
756 | /* If we have selected a cpu we are generating instructions for. */ |
757 | static int cpu_arch_tune_set = 0; | |
758 | ||
9103f4f4 | 759 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 760 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
761 | |
762 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 763 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 764 | |
ccc9c027 | 765 | /* CPU instruction set architecture used. */ |
fbf3f584 | 766 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 767 | |
9103f4f4 | 768 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 769 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 770 | |
fddf5b5b AM |
771 | /* If set, conditional jumps are not automatically promoted to handle |
772 | larger than a byte offset. */ | |
773 | static unsigned int no_cond_jump_promotion = 0; | |
774 | ||
c0f3af97 L |
775 | /* Encode SSE instructions with VEX prefix. */ |
776 | static unsigned int sse2avx; | |
777 | ||
539f890d L |
778 | /* Encode scalar AVX instructions with specific vector length. */ |
779 | static enum | |
780 | { | |
781 | vex128 = 0, | |
782 | vex256 | |
783 | } avxscalar; | |
784 | ||
03751133 L |
785 | /* Encode VEX WIG instructions with specific vex.w. */ |
786 | static enum | |
787 | { | |
788 | vexw0 = 0, | |
789 | vexw1 | |
790 | } vexwig; | |
791 | ||
43234a1e L |
792 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
793 | static enum | |
794 | { | |
795 | evexl128 = 0, | |
796 | evexl256, | |
797 | evexl512 | |
798 | } evexlig; | |
799 | ||
800 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
801 | static enum | |
802 | { | |
803 | evexw0 = 0, | |
804 | evexw1 | |
805 | } evexwig; | |
806 | ||
d3d3c6db IT |
807 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
808 | static enum rc_type evexrcig = rne; | |
809 | ||
29b0f896 | 810 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 811 | static symbolS *GOT_symbol; |
29b0f896 | 812 | |
a4447b93 RH |
813 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
814 | unsigned int x86_dwarf2_return_column; | |
815 | ||
816 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
817 | int x86_cie_data_alignment; | |
818 | ||
252b5132 | 819 | /* Interface to relax_segment. |
fddf5b5b AM |
820 | There are 3 major relax states for 386 jump insns because the |
821 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
822 | figuring out what sort of jump to choose to reach a given label. |
823 | ||
824 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
825 | branches which are handled by md_estimate_size_before_relax() and | |
826 | i386_generic_table_relax_frag(). */ | |
252b5132 | 827 | |
47926f60 | 828 | /* Types. */ |
93c2a809 AM |
829 | #define UNCOND_JUMP 0 |
830 | #define COND_JUMP 1 | |
831 | #define COND_JUMP86 2 | |
e379e5f3 L |
832 | #define BRANCH_PADDING 3 |
833 | #define BRANCH_PREFIX 4 | |
834 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 835 | |
47926f60 | 836 | /* Sizes. */ |
252b5132 RH |
837 | #define CODE16 1 |
838 | #define SMALL 0 | |
29b0f896 | 839 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 840 | #define BIG 2 |
29b0f896 | 841 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
842 | |
843 | #ifndef INLINE | |
844 | #ifdef __GNUC__ | |
845 | #define INLINE __inline__ | |
846 | #else | |
847 | #define INLINE | |
848 | #endif | |
849 | #endif | |
850 | ||
fddf5b5b AM |
851 | #define ENCODE_RELAX_STATE(type, size) \ |
852 | ((relax_substateT) (((type) << 2) | (size))) | |
853 | #define TYPE_FROM_RELAX_STATE(s) \ | |
854 | ((s) >> 2) | |
855 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
856 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
857 | |
858 | /* This table is used by relax_frag to promote short jumps to long | |
859 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
860 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
861 | don't allow a short jump in a 32 bit code segment to be promoted to | |
862 | a 16 bit offset jump because it's slower (requires data size | |
863 | prefix), and doesn't work, unless the destination is in the bottom | |
864 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
865 | ||
866 | const relax_typeS md_relax_table[] = | |
867 | { | |
24eab124 AM |
868 | /* The fields are: |
869 | 1) most positive reach of this state, | |
870 | 2) most negative reach of this state, | |
93c2a809 | 871 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 872 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 873 | |
fddf5b5b | 874 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
875 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
876 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
877 | /* dword jmp adds 4 bytes to frag: | |
878 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 879 | {0, 0, 4, 0}, |
93c2a809 AM |
880 | /* word jmp adds 2 byte2 to frag: |
881 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
882 | {0, 0, 2, 0}, |
883 | ||
93c2a809 AM |
884 | /* COND_JUMP states. */ |
885 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
886 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
887 | /* dword conditionals adds 5 bytes to frag: | |
888 | 1 extra opcode byte, 4 displacement bytes. */ | |
889 | {0, 0, 5, 0}, | |
fddf5b5b | 890 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
891 | 1 extra opcode byte, 2 displacement bytes. */ |
892 | {0, 0, 3, 0}, | |
893 | ||
894 | /* COND_JUMP86 states. */ | |
895 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
896 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
897 | /* dword conditionals adds 5 bytes to frag: | |
898 | 1 extra opcode byte, 4 displacement bytes. */ | |
899 | {0, 0, 5, 0}, | |
900 | /* word conditionals add 4 bytes to frag: | |
901 | 1 displacement byte and a 3 byte long branch insn. */ | |
902 | {0, 0, 4, 0} | |
252b5132 RH |
903 | }; |
904 | ||
9103f4f4 L |
905 | static const arch_entry cpu_arch[] = |
906 | { | |
89507696 JB |
907 | /* Do not replace the first two entries - i386_target_format() |
908 | relies on them being there in this order. */ | |
8a2c8fef | 909 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 910 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 912 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 920 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 922 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 923 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 924 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 926 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 928 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 929 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 930 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 931 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 932 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 933 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 934 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 936 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 937 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 938 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 940 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 941 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 942 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 944 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 946 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 947 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 948 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 949 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 950 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 951 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 952 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 953 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 954 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 955 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 956 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 958 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 959 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 960 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 961 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 962 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 963 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 964 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 965 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 966 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 968 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 970 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 971 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 972 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 973 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 974 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 975 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 976 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 977 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 978 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 979 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 980 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
981 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
982 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 983 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 984 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 985 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 986 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 987 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 991 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_387_FLAGS, 0 }, |
1848e567 L |
993 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
994 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
995 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
996 | CPU_CMOV_FLAGS, 0 }, | |
997 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
998 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 999 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 1001 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 1003 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 1005 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_SSE3_FLAGS, 0 }, |
af5c13b0 L |
1007 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
1008 | CPU_SSE4A_FLAGS, 0 }, | |
8a2c8fef | 1009 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 1011 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 1013 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1015 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1017 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 1019 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 1021 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1023 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1025 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1026 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1027 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1028 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1029 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1030 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1031 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1033 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1035 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1037 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1039 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1040 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1041 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1042 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1043 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1044 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1045 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1046 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1047 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1048 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1049 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1050 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1051 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1053 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1055 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1057 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1059 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1060 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1061 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1062 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1063 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1064 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1065 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1066 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1067 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1068 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1069 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1070 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1071 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1072 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1073 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1074 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1075 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1076 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1077 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1078 | CPU_LZCNT_FLAGS, 0 }, |
272a84b1 L |
1079 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
1080 | CPU_POPCNT_FLAGS, 0 }, | |
42164a71 | 1081 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1082 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1083 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1084 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1085 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1086 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1087 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1088 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1089 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1090 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1091 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1092 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1093 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1094 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1095 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1096 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1097 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1098 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1099 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1100 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1101 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1102 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1103 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1104 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1105 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1106 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1107 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1108 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1109 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1110 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1111 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1112 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1113 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1114 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1115 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1116 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1117 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1118 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1119 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1120 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1121 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1122 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1123 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1124 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1125 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1126 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1127 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1128 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1129 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1130 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1131 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1132 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1133 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1134 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1135 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1136 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1137 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1138 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1139 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1140 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1141 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1142 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1143 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1144 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1145 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1146 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1147 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1148 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1149 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1150 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1151 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1152 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1153 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1154 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1155 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1156 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1157 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1158 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1159 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1160 | CPU_IBT_FLAGS, 0 }, | |
1161 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1162 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1163 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1164 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1165 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1166 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1167 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1168 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1169 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1170 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1171 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1172 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1173 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1174 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1175 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1176 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1177 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1178 | CPU_MOVDIRI_FLAGS, 0 }, | |
1179 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1180 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1181 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1182 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1183 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1184 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1185 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1186 | CPU_ENQCMD_FLAGS, 0 }, | |
142861df JB |
1187 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1188 | CPU_RDPRU_FLAGS, 0 }, | |
1189 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1190 | CPU_MCOMMIT_FLAGS, 0 }, | |
a847e322 JB |
1191 | { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN, |
1192 | CPU_SEV_ES_FLAGS, 0 }, | |
293f5f65 L |
1193 | }; |
1194 | ||
1195 | static const noarch_entry cpu_noarch[] = | |
1196 | { | |
1197 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1198 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1199 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1200 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1201 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1202 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1203 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1204 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1205 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1206 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
af5c13b0 | 1207 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
1848e567 L |
1208 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
1209 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1210 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
af5c13b0 | 1211 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
293f5f65 | 1212 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1213 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1214 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1215 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1216 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1217 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1218 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1219 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1220 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1221 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1222 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1223 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1224 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1225 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1226 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1227 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1228 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1229 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1230 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1231 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1232 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1233 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1234 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1235 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1236 | }; |
1237 | ||
704209c0 | 1238 | #ifdef I386COFF |
a6c24e68 NC |
1239 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1240 | is allowed to be optional. */ | |
1241 | ||
1242 | static symbolS * | |
1243 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1244 | { | |
1245 | addressT align = 0; | |
1246 | ||
1247 | SKIP_WHITESPACE (); | |
1248 | ||
7ab9ffdd | 1249 | if (needs_align |
a6c24e68 NC |
1250 | && *input_line_pointer == ',') |
1251 | { | |
1252 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1253 | |
a6c24e68 NC |
1254 | if (align == (addressT) -1) |
1255 | return NULL; | |
1256 | } | |
1257 | else | |
1258 | { | |
1259 | if (size >= 8) | |
1260 | align = 3; | |
1261 | else if (size >= 4) | |
1262 | align = 2; | |
1263 | else if (size >= 2) | |
1264 | align = 1; | |
1265 | else | |
1266 | align = 0; | |
1267 | } | |
1268 | ||
1269 | bss_alloc (symbolP, size, align); | |
1270 | return symbolP; | |
1271 | } | |
1272 | ||
704209c0 | 1273 | static void |
a6c24e68 NC |
1274 | pe_lcomm (int needs_align) |
1275 | { | |
1276 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1277 | } | |
704209c0 | 1278 | #endif |
a6c24e68 | 1279 | |
29b0f896 AM |
1280 | const pseudo_typeS md_pseudo_table[] = |
1281 | { | |
1282 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1283 | {"align", s_align_bytes, 0}, | |
1284 | #else | |
1285 | {"align", s_align_ptwo, 0}, | |
1286 | #endif | |
1287 | {"arch", set_cpu_arch, 0}, | |
1288 | #ifndef I386COFF | |
1289 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1290 | #else |
1291 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1292 | #endif |
1293 | {"ffloat", float_cons, 'f'}, | |
1294 | {"dfloat", float_cons, 'd'}, | |
1295 | {"tfloat", float_cons, 'x'}, | |
1296 | {"value", cons, 2}, | |
d182319b | 1297 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1298 | {"noopt", s_ignore, 0}, |
1299 | {"optim", s_ignore, 0}, | |
1300 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1301 | {"code16", set_code_flag, CODE_16BIT}, | |
1302 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1303 | #ifdef BFD64 |
29b0f896 | 1304 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1305 | #endif |
29b0f896 AM |
1306 | {"intel_syntax", set_intel_syntax, 1}, |
1307 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1308 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1309 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1310 | {"allow_index_reg", set_allow_index_reg, 1}, |
1311 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1312 | {"sse_check", set_check, 0}, |
1313 | {"operand_check", set_check, 1}, | |
3b22753a L |
1314 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1315 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1316 | #else |
68d20676 | 1317 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1318 | {"loc", dwarf2_directive_loc, 0}, |
1319 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1320 | #endif |
6482c264 NC |
1321 | #ifdef TE_PE |
1322 | {"secrel32", pe_directive_secrel, 0}, | |
1323 | #endif | |
29b0f896 AM |
1324 | {0, 0, 0} |
1325 | }; | |
1326 | ||
1327 | /* For interface with expression (). */ | |
1328 | extern char *input_line_pointer; | |
1329 | ||
1330 | /* Hash table for instruction mnemonic lookup. */ | |
1331 | static struct hash_control *op_hash; | |
1332 | ||
1333 | /* Hash table for register lookup. */ | |
1334 | static struct hash_control *reg_hash; | |
1335 | \f | |
ce8a8b2f AM |
1336 | /* Various efficient no-op patterns for aligning code labels. |
1337 | Note: Don't try to assemble the instructions in the comments. | |
1338 | 0L and 0w are not legal. */ | |
62a02d25 L |
1339 | static const unsigned char f32_1[] = |
1340 | {0x90}; /* nop */ | |
1341 | static const unsigned char f32_2[] = | |
1342 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1343 | static const unsigned char f32_3[] = | |
1344 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1345 | static const unsigned char f32_4[] = | |
1346 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1347 | static const unsigned char f32_6[] = |
1348 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1349 | static const unsigned char f32_7[] = | |
1350 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1351 | static const unsigned char f16_3[] = |
3ae729d5 | 1352 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1353 | static const unsigned char f16_4[] = |
3ae729d5 L |
1354 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1355 | static const unsigned char jump_disp8[] = | |
1356 | {0xeb}; /* jmp disp8 */ | |
1357 | static const unsigned char jump32_disp32[] = | |
1358 | {0xe9}; /* jmp disp32 */ | |
1359 | static const unsigned char jump16_disp32[] = | |
1360 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1361 | /* 32-bit NOPs patterns. */ |
1362 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1363 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1364 | }; |
1365 | /* 16-bit NOPs patterns. */ | |
1366 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1367 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1368 | }; |
1369 | /* nopl (%[re]ax) */ | |
1370 | static const unsigned char alt_3[] = | |
1371 | {0x0f,0x1f,0x00}; | |
1372 | /* nopl 0(%[re]ax) */ | |
1373 | static const unsigned char alt_4[] = | |
1374 | {0x0f,0x1f,0x40,0x00}; | |
1375 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1376 | static const unsigned char alt_5[] = | |
1377 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1378 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1379 | static const unsigned char alt_6[] = | |
1380 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1381 | /* nopl 0L(%[re]ax) */ | |
1382 | static const unsigned char alt_7[] = | |
1383 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1384 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1385 | static const unsigned char alt_8[] = | |
1386 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1387 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1388 | static const unsigned char alt_9[] = | |
1389 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1390 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1391 | static const unsigned char alt_10[] = | |
1392 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1393 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1394 | static const unsigned char alt_11[] = | |
1395 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1396 | /* 32-bit and 64-bit NOPs patterns. */ |
1397 | static const unsigned char *const alt_patt[] = { | |
1398 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1399 | alt_9, alt_10, alt_11 |
62a02d25 L |
1400 | }; |
1401 | ||
1402 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1403 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1404 | ||
1405 | static void | |
1406 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1407 | int count, int max_single_nop_size) | |
1408 | ||
1409 | { | |
3ae729d5 L |
1410 | /* Place the longer NOP first. */ |
1411 | int last; | |
1412 | int offset; | |
3076e594 NC |
1413 | const unsigned char *nops; |
1414 | ||
1415 | if (max_single_nop_size < 1) | |
1416 | { | |
1417 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1418 | max_single_nop_size); | |
1419 | return; | |
1420 | } | |
1421 | ||
1422 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1423 | |
1424 | /* Use the smaller one if the requsted one isn't available. */ | |
1425 | if (nops == NULL) | |
62a02d25 | 1426 | { |
3ae729d5 L |
1427 | max_single_nop_size--; |
1428 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1429 | } |
1430 | ||
3ae729d5 L |
1431 | last = count % max_single_nop_size; |
1432 | ||
1433 | count -= last; | |
1434 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1435 | memcpy (where + offset, nops, max_single_nop_size); | |
1436 | ||
1437 | if (last) | |
1438 | { | |
1439 | nops = patt[last - 1]; | |
1440 | if (nops == NULL) | |
1441 | { | |
1442 | /* Use the smaller one plus one-byte NOP if the needed one | |
1443 | isn't available. */ | |
1444 | last--; | |
1445 | nops = patt[last - 1]; | |
1446 | memcpy (where + offset, nops, last); | |
1447 | where[offset + last] = *patt[0]; | |
1448 | } | |
1449 | else | |
1450 | memcpy (where + offset, nops, last); | |
1451 | } | |
62a02d25 L |
1452 | } |
1453 | ||
3ae729d5 L |
1454 | static INLINE int |
1455 | fits_in_imm7 (offsetT num) | |
1456 | { | |
1457 | return (num & 0x7f) == num; | |
1458 | } | |
1459 | ||
1460 | static INLINE int | |
1461 | fits_in_imm31 (offsetT num) | |
1462 | { | |
1463 | return (num & 0x7fffffff) == num; | |
1464 | } | |
62a02d25 L |
1465 | |
1466 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1467 | single NOP instruction LIMIT. */ | |
1468 | ||
1469 | void | |
3ae729d5 | 1470 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1471 | { |
3ae729d5 | 1472 | const unsigned char *const *patt = NULL; |
62a02d25 | 1473 | int max_single_nop_size; |
3ae729d5 L |
1474 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1475 | int max_number_of_nops; | |
62a02d25 | 1476 | |
3ae729d5 | 1477 | switch (fragP->fr_type) |
62a02d25 | 1478 | { |
3ae729d5 L |
1479 | case rs_fill_nop: |
1480 | case rs_align_code: | |
1481 | break; | |
e379e5f3 L |
1482 | case rs_machine_dependent: |
1483 | /* Allow NOP padding for jumps and calls. */ | |
1484 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1485 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1486 | break; | |
1487 | /* Fall through. */ | |
3ae729d5 | 1488 | default: |
62a02d25 L |
1489 | return; |
1490 | } | |
1491 | ||
ccc9c027 L |
1492 | /* We need to decide which NOP sequence to use for 32bit and |
1493 | 64bit. When -mtune= is used: | |
4eed87de | 1494 | |
76bc74dc L |
1495 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1496 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1497 | 2. For the rest, alt_patt will be used. |
1498 | ||
1499 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1500 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1501 | be used. |
ccc9c027 L |
1502 | |
1503 | When -march= or .arch is used, we can't use anything beyond | |
1504 | cpu_arch_isa_flags. */ | |
1505 | ||
1506 | if (flag_code == CODE_16BIT) | |
1507 | { | |
3ae729d5 L |
1508 | patt = f16_patt; |
1509 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1510 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1511 | max_number_of_nops = 2; | |
252b5132 | 1512 | } |
33fef721 | 1513 | else |
ccc9c027 | 1514 | { |
fbf3f584 | 1515 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1516 | { |
1517 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1518 | switch (cpu_arch_tune) | |
1519 | { | |
1520 | case PROCESSOR_UNKNOWN: | |
1521 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1522 | optimize with nops. */ |
1523 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1524 | patt = alt_patt; |
ccc9c027 L |
1525 | else |
1526 | patt = f32_patt; | |
1527 | break; | |
ccc9c027 L |
1528 | case PROCESSOR_PENTIUM4: |
1529 | case PROCESSOR_NOCONA: | |
ef05d495 | 1530 | case PROCESSOR_CORE: |
76bc74dc | 1531 | case PROCESSOR_CORE2: |
bd5295b2 | 1532 | case PROCESSOR_COREI7: |
3632d14b | 1533 | case PROCESSOR_L1OM: |
7a9068fe | 1534 | case PROCESSOR_K1OM: |
76bc74dc | 1535 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1536 | case PROCESSOR_K6: |
1537 | case PROCESSOR_ATHLON: | |
1538 | case PROCESSOR_K8: | |
4eed87de | 1539 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1540 | case PROCESSOR_BD: |
029f3522 | 1541 | case PROCESSOR_ZNVER: |
7b458c12 | 1542 | case PROCESSOR_BT: |
80b8656c | 1543 | patt = alt_patt; |
ccc9c027 | 1544 | break; |
76bc74dc | 1545 | case PROCESSOR_I386: |
ccc9c027 L |
1546 | case PROCESSOR_I486: |
1547 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1548 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1549 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1550 | case PROCESSOR_GENERIC32: |
1551 | patt = f32_patt; | |
1552 | break; | |
4eed87de | 1553 | } |
ccc9c027 L |
1554 | } |
1555 | else | |
1556 | { | |
fbf3f584 | 1557 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1558 | { |
1559 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1560 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1561 | PROCESSOR_UNKNOWN. */ |
1562 | abort (); | |
1563 | break; | |
1564 | ||
76bc74dc | 1565 | case PROCESSOR_I386: |
ccc9c027 L |
1566 | case PROCESSOR_I486: |
1567 | case PROCESSOR_PENTIUM: | |
81486035 | 1568 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1569 | case PROCESSOR_K6: |
1570 | case PROCESSOR_ATHLON: | |
1571 | case PROCESSOR_K8: | |
4eed87de | 1572 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1573 | case PROCESSOR_BD: |
029f3522 | 1574 | case PROCESSOR_ZNVER: |
7b458c12 | 1575 | case PROCESSOR_BT: |
ccc9c027 L |
1576 | case PROCESSOR_GENERIC32: |
1577 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1578 | with nops. */ |
1579 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1580 | patt = alt_patt; |
ccc9c027 L |
1581 | else |
1582 | patt = f32_patt; | |
1583 | break; | |
76bc74dc L |
1584 | case PROCESSOR_PENTIUMPRO: |
1585 | case PROCESSOR_PENTIUM4: | |
1586 | case PROCESSOR_NOCONA: | |
1587 | case PROCESSOR_CORE: | |
ef05d495 | 1588 | case PROCESSOR_CORE2: |
bd5295b2 | 1589 | case PROCESSOR_COREI7: |
3632d14b | 1590 | case PROCESSOR_L1OM: |
7a9068fe | 1591 | case PROCESSOR_K1OM: |
22109423 | 1592 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1593 | patt = alt_patt; |
ccc9c027 L |
1594 | else |
1595 | patt = f32_patt; | |
1596 | break; | |
1597 | case PROCESSOR_GENERIC64: | |
80b8656c | 1598 | patt = alt_patt; |
ccc9c027 | 1599 | break; |
4eed87de | 1600 | } |
ccc9c027 L |
1601 | } |
1602 | ||
76bc74dc L |
1603 | if (patt == f32_patt) |
1604 | { | |
3ae729d5 L |
1605 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1606 | /* Limit number of NOPs to 2 for older processors. */ | |
1607 | max_number_of_nops = 2; | |
76bc74dc L |
1608 | } |
1609 | else | |
1610 | { | |
3ae729d5 L |
1611 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1612 | /* Limit number of NOPs to 7 for newer processors. */ | |
1613 | max_number_of_nops = 7; | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | if (limit == 0) | |
1618 | limit = max_single_nop_size; | |
1619 | ||
1620 | if (fragP->fr_type == rs_fill_nop) | |
1621 | { | |
1622 | /* Output NOPs for .nop directive. */ | |
1623 | if (limit > max_single_nop_size) | |
1624 | { | |
1625 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1626 | _("invalid single nop size: %d " | |
1627 | "(expect within [0, %d])"), | |
1628 | limit, max_single_nop_size); | |
1629 | return; | |
1630 | } | |
1631 | } | |
e379e5f3 | 1632 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1633 | fragP->fr_var = count; |
1634 | ||
1635 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1636 | { | |
1637 | /* Generate jump over NOPs. */ | |
1638 | offsetT disp = count - 2; | |
1639 | if (fits_in_imm7 (disp)) | |
1640 | { | |
1641 | /* Use "jmp disp8" if possible. */ | |
1642 | count = disp; | |
1643 | where[0] = jump_disp8[0]; | |
1644 | where[1] = count; | |
1645 | where += 2; | |
1646 | } | |
1647 | else | |
1648 | { | |
1649 | unsigned int size_of_jump; | |
1650 | ||
1651 | if (flag_code == CODE_16BIT) | |
1652 | { | |
1653 | where[0] = jump16_disp32[0]; | |
1654 | where[1] = jump16_disp32[1]; | |
1655 | size_of_jump = 2; | |
1656 | } | |
1657 | else | |
1658 | { | |
1659 | where[0] = jump32_disp32[0]; | |
1660 | size_of_jump = 1; | |
1661 | } | |
1662 | ||
1663 | count -= size_of_jump + 4; | |
1664 | if (!fits_in_imm31 (count)) | |
1665 | { | |
1666 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1667 | _("jump over nop padding out of range")); | |
1668 | return; | |
1669 | } | |
1670 | ||
1671 | md_number_to_chars (where + size_of_jump, count, 4); | |
1672 | where += size_of_jump + 4; | |
76bc74dc | 1673 | } |
ccc9c027 | 1674 | } |
3ae729d5 L |
1675 | |
1676 | /* Generate multiple NOPs. */ | |
1677 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1678 | } |
1679 | ||
c6fb90c8 | 1680 | static INLINE int |
0dfbf9d7 | 1681 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1682 | { |
0dfbf9d7 | 1683 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1684 | { |
1685 | case 3: | |
0dfbf9d7 | 1686 | if (x->array[2]) |
c6fb90c8 | 1687 | return 0; |
1a0670f3 | 1688 | /* Fall through. */ |
c6fb90c8 | 1689 | case 2: |
0dfbf9d7 | 1690 | if (x->array[1]) |
c6fb90c8 | 1691 | return 0; |
1a0670f3 | 1692 | /* Fall through. */ |
c6fb90c8 | 1693 | case 1: |
0dfbf9d7 | 1694 | return !x->array[0]; |
c6fb90c8 L |
1695 | default: |
1696 | abort (); | |
1697 | } | |
40fb9820 L |
1698 | } |
1699 | ||
c6fb90c8 | 1700 | static INLINE void |
0dfbf9d7 | 1701 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1702 | { |
0dfbf9d7 | 1703 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1704 | { |
1705 | case 3: | |
0dfbf9d7 | 1706 | x->array[2] = v; |
1a0670f3 | 1707 | /* Fall through. */ |
c6fb90c8 | 1708 | case 2: |
0dfbf9d7 | 1709 | x->array[1] = v; |
1a0670f3 | 1710 | /* Fall through. */ |
c6fb90c8 | 1711 | case 1: |
0dfbf9d7 | 1712 | x->array[0] = v; |
1a0670f3 | 1713 | /* Fall through. */ |
c6fb90c8 L |
1714 | break; |
1715 | default: | |
1716 | abort (); | |
1717 | } | |
bab6aec1 JB |
1718 | |
1719 | x->bitfield.class = ClassNone; | |
75e5731b | 1720 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1721 | } |
40fb9820 | 1722 | |
c6fb90c8 | 1723 | static INLINE int |
0dfbf9d7 L |
1724 | operand_type_equal (const union i386_operand_type *x, |
1725 | const union i386_operand_type *y) | |
c6fb90c8 | 1726 | { |
0dfbf9d7 | 1727 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1728 | { |
1729 | case 3: | |
0dfbf9d7 | 1730 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1731 | return 0; |
1a0670f3 | 1732 | /* Fall through. */ |
c6fb90c8 | 1733 | case 2: |
0dfbf9d7 | 1734 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1735 | return 0; |
1a0670f3 | 1736 | /* Fall through. */ |
c6fb90c8 | 1737 | case 1: |
0dfbf9d7 | 1738 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1739 | break; |
1740 | default: | |
1741 | abort (); | |
1742 | } | |
1743 | } | |
40fb9820 | 1744 | |
0dfbf9d7 L |
1745 | static INLINE int |
1746 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1747 | { | |
1748 | switch (ARRAY_SIZE(x->array)) | |
1749 | { | |
53467f57 IT |
1750 | case 4: |
1751 | if (x->array[3]) | |
1752 | return 0; | |
1753 | /* Fall through. */ | |
0dfbf9d7 L |
1754 | case 3: |
1755 | if (x->array[2]) | |
1756 | return 0; | |
1a0670f3 | 1757 | /* Fall through. */ |
0dfbf9d7 L |
1758 | case 2: |
1759 | if (x->array[1]) | |
1760 | return 0; | |
1a0670f3 | 1761 | /* Fall through. */ |
0dfbf9d7 L |
1762 | case 1: |
1763 | return !x->array[0]; | |
1764 | default: | |
1765 | abort (); | |
1766 | } | |
1767 | } | |
1768 | ||
0dfbf9d7 L |
1769 | static INLINE int |
1770 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1771 | const union i386_cpu_flags *y) | |
1772 | { | |
1773 | switch (ARRAY_SIZE(x->array)) | |
1774 | { | |
53467f57 IT |
1775 | case 4: |
1776 | if (x->array[3] != y->array[3]) | |
1777 | return 0; | |
1778 | /* Fall through. */ | |
0dfbf9d7 L |
1779 | case 3: |
1780 | if (x->array[2] != y->array[2]) | |
1781 | return 0; | |
1a0670f3 | 1782 | /* Fall through. */ |
0dfbf9d7 L |
1783 | case 2: |
1784 | if (x->array[1] != y->array[1]) | |
1785 | return 0; | |
1a0670f3 | 1786 | /* Fall through. */ |
0dfbf9d7 L |
1787 | case 1: |
1788 | return x->array[0] == y->array[0]; | |
1789 | break; | |
1790 | default: | |
1791 | abort (); | |
1792 | } | |
1793 | } | |
c6fb90c8 L |
1794 | |
1795 | static INLINE int | |
1796 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1797 | { | |
1798 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1799 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1800 | } |
1801 | ||
c6fb90c8 L |
1802 | static INLINE i386_cpu_flags |
1803 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1804 | { |
c6fb90c8 L |
1805 | switch (ARRAY_SIZE (x.array)) |
1806 | { | |
53467f57 IT |
1807 | case 4: |
1808 | x.array [3] &= y.array [3]; | |
1809 | /* Fall through. */ | |
c6fb90c8 L |
1810 | case 3: |
1811 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1812 | /* Fall through. */ |
c6fb90c8 L |
1813 | case 2: |
1814 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1815 | /* Fall through. */ |
c6fb90c8 L |
1816 | case 1: |
1817 | x.array [0] &= y.array [0]; | |
1818 | break; | |
1819 | default: | |
1820 | abort (); | |
1821 | } | |
1822 | return x; | |
1823 | } | |
40fb9820 | 1824 | |
c6fb90c8 L |
1825 | static INLINE i386_cpu_flags |
1826 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1827 | { |
c6fb90c8 | 1828 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1829 | { |
53467f57 IT |
1830 | case 4: |
1831 | x.array [3] |= y.array [3]; | |
1832 | /* Fall through. */ | |
c6fb90c8 L |
1833 | case 3: |
1834 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1835 | /* Fall through. */ |
c6fb90c8 L |
1836 | case 2: |
1837 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1838 | /* Fall through. */ |
c6fb90c8 L |
1839 | case 1: |
1840 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1841 | break; |
1842 | default: | |
1843 | abort (); | |
1844 | } | |
40fb9820 L |
1845 | return x; |
1846 | } | |
1847 | ||
309d3373 JB |
1848 | static INLINE i386_cpu_flags |
1849 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1850 | { | |
1851 | switch (ARRAY_SIZE (x.array)) | |
1852 | { | |
53467f57 IT |
1853 | case 4: |
1854 | x.array [3] &= ~y.array [3]; | |
1855 | /* Fall through. */ | |
309d3373 JB |
1856 | case 3: |
1857 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1858 | /* Fall through. */ |
309d3373 JB |
1859 | case 2: |
1860 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1861 | /* Fall through. */ |
309d3373 JB |
1862 | case 1: |
1863 | x.array [0] &= ~y.array [0]; | |
1864 | break; | |
1865 | default: | |
1866 | abort (); | |
1867 | } | |
1868 | return x; | |
1869 | } | |
1870 | ||
6c0946d0 JB |
1871 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1872 | ||
c0f3af97 L |
1873 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1874 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1875 | ||
c0f3af97 | 1876 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1877 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1878 | |
1879 | /* Return CPU flags match bits. */ | |
3629bb00 | 1880 | |
40fb9820 | 1881 | static int |
d3ce72d0 | 1882 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1883 | { |
c0f3af97 L |
1884 | i386_cpu_flags x = t->cpu_flags; |
1885 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1886 | |
1887 | x.bitfield.cpu64 = 0; | |
1888 | x.bitfield.cpuno64 = 0; | |
1889 | ||
0dfbf9d7 | 1890 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1891 | { |
1892 | /* This instruction is available on all archs. */ | |
db12e14e | 1893 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1894 | } |
3629bb00 L |
1895 | else |
1896 | { | |
c0f3af97 | 1897 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1898 | i386_cpu_flags cpu = cpu_arch_flags; |
1899 | ||
ab592e75 JB |
1900 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1901 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1902 | return match; | |
1903 | x.bitfield.cpuavx512vl = 0; | |
1904 | ||
3629bb00 | 1905 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1906 | if (!cpu_flags_all_zero (&cpu)) |
1907 | { | |
a5ff0eb2 L |
1908 | if (x.bitfield.cpuavx) |
1909 | { | |
929f69fa | 1910 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1911 | if (cpu.bitfield.cpuavx |
1912 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1913 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1914 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1915 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1916 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1917 | } |
929f69fa JB |
1918 | else if (x.bitfield.cpuavx512f) |
1919 | { | |
1920 | /* We need to check a few extra flags with AVX512F. */ | |
1921 | if (cpu.bitfield.cpuavx512f | |
1922 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1923 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1924 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1925 | match |= CPU_FLAGS_ARCH_MATCH; | |
1926 | } | |
a5ff0eb2 | 1927 | else |
db12e14e | 1928 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1929 | } |
3629bb00 | 1930 | } |
c0f3af97 | 1931 | return match; |
40fb9820 L |
1932 | } |
1933 | ||
c6fb90c8 L |
1934 | static INLINE i386_operand_type |
1935 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1936 | { |
bab6aec1 JB |
1937 | if (x.bitfield.class != y.bitfield.class) |
1938 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1939 | if (x.bitfield.instance != y.bitfield.instance) |
1940 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1941 | |
c6fb90c8 L |
1942 | switch (ARRAY_SIZE (x.array)) |
1943 | { | |
1944 | case 3: | |
1945 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1946 | /* Fall through. */ |
c6fb90c8 L |
1947 | case 2: |
1948 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1949 | /* Fall through. */ |
c6fb90c8 L |
1950 | case 1: |
1951 | x.array [0] &= y.array [0]; | |
1952 | break; | |
1953 | default: | |
1954 | abort (); | |
1955 | } | |
1956 | return x; | |
40fb9820 L |
1957 | } |
1958 | ||
73053c1f JB |
1959 | static INLINE i386_operand_type |
1960 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1961 | { | |
bab6aec1 | 1962 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1963 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1964 | |
73053c1f JB |
1965 | switch (ARRAY_SIZE (x.array)) |
1966 | { | |
1967 | case 3: | |
1968 | x.array [2] &= ~y.array [2]; | |
1969 | /* Fall through. */ | |
1970 | case 2: | |
1971 | x.array [1] &= ~y.array [1]; | |
1972 | /* Fall through. */ | |
1973 | case 1: | |
1974 | x.array [0] &= ~y.array [0]; | |
1975 | break; | |
1976 | default: | |
1977 | abort (); | |
1978 | } | |
1979 | return x; | |
1980 | } | |
1981 | ||
c6fb90c8 L |
1982 | static INLINE i386_operand_type |
1983 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1984 | { |
bab6aec1 JB |
1985 | gas_assert (x.bitfield.class == ClassNone || |
1986 | y.bitfield.class == ClassNone || | |
1987 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1988 | gas_assert (x.bitfield.instance == InstanceNone || |
1989 | y.bitfield.instance == InstanceNone || | |
1990 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1991 | |
c6fb90c8 | 1992 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1993 | { |
c6fb90c8 L |
1994 | case 3: |
1995 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1996 | /* Fall through. */ |
c6fb90c8 L |
1997 | case 2: |
1998 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1999 | /* Fall through. */ |
c6fb90c8 L |
2000 | case 1: |
2001 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2002 | break; |
2003 | default: | |
2004 | abort (); | |
2005 | } | |
c6fb90c8 L |
2006 | return x; |
2007 | } | |
40fb9820 | 2008 | |
c6fb90c8 L |
2009 | static INLINE i386_operand_type |
2010 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2011 | { | |
bab6aec1 | 2012 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2013 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2014 | |
c6fb90c8 L |
2015 | switch (ARRAY_SIZE (x.array)) |
2016 | { | |
2017 | case 3: | |
2018 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2019 | /* Fall through. */ |
c6fb90c8 L |
2020 | case 2: |
2021 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2022 | /* Fall through. */ |
c6fb90c8 L |
2023 | case 1: |
2024 | x.array [0] ^= y.array [0]; | |
2025 | break; | |
2026 | default: | |
2027 | abort (); | |
2028 | } | |
40fb9820 L |
2029 | return x; |
2030 | } | |
2031 | ||
40fb9820 L |
2032 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2033 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2034 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2035 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2036 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2037 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2038 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2039 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2040 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2041 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2042 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2043 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2044 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2045 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2046 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2047 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2048 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2049 | ||
2050 | enum operand_type | |
2051 | { | |
2052 | reg, | |
40fb9820 L |
2053 | imm, |
2054 | disp, | |
2055 | anymem | |
2056 | }; | |
2057 | ||
c6fb90c8 | 2058 | static INLINE int |
40fb9820 L |
2059 | operand_type_check (i386_operand_type t, enum operand_type c) |
2060 | { | |
2061 | switch (c) | |
2062 | { | |
2063 | case reg: | |
bab6aec1 | 2064 | return t.bitfield.class == Reg; |
40fb9820 | 2065 | |
40fb9820 L |
2066 | case imm: |
2067 | return (t.bitfield.imm8 | |
2068 | || t.bitfield.imm8s | |
2069 | || t.bitfield.imm16 | |
2070 | || t.bitfield.imm32 | |
2071 | || t.bitfield.imm32s | |
2072 | || t.bitfield.imm64); | |
2073 | ||
2074 | case disp: | |
2075 | return (t.bitfield.disp8 | |
2076 | || t.bitfield.disp16 | |
2077 | || t.bitfield.disp32 | |
2078 | || t.bitfield.disp32s | |
2079 | || t.bitfield.disp64); | |
2080 | ||
2081 | case anymem: | |
2082 | return (t.bitfield.disp8 | |
2083 | || t.bitfield.disp16 | |
2084 | || t.bitfield.disp32 | |
2085 | || t.bitfield.disp32s | |
2086 | || t.bitfield.disp64 | |
2087 | || t.bitfield.baseindex); | |
2088 | ||
2089 | default: | |
2090 | abort (); | |
2091 | } | |
2cfe26b6 AM |
2092 | |
2093 | return 0; | |
40fb9820 L |
2094 | } |
2095 | ||
7a54636a L |
2096 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2097 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2098 | |
2099 | static INLINE int | |
7a54636a L |
2100 | match_operand_size (const insn_template *t, unsigned int wanted, |
2101 | unsigned int given) | |
5c07affc | 2102 | { |
3ac21baa JB |
2103 | return !((i.types[given].bitfield.byte |
2104 | && !t->operand_types[wanted].bitfield.byte) | |
2105 | || (i.types[given].bitfield.word | |
2106 | && !t->operand_types[wanted].bitfield.word) | |
2107 | || (i.types[given].bitfield.dword | |
2108 | && !t->operand_types[wanted].bitfield.dword) | |
2109 | || (i.types[given].bitfield.qword | |
2110 | && !t->operand_types[wanted].bitfield.qword) | |
2111 | || (i.types[given].bitfield.tbyte | |
2112 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2113 | } |
2114 | ||
dd40ce22 L |
2115 | /* Return 1 if there is no conflict in SIMD register between operand |
2116 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2117 | |
2118 | static INLINE int | |
dd40ce22 L |
2119 | match_simd_size (const insn_template *t, unsigned int wanted, |
2120 | unsigned int given) | |
1b54b8d7 | 2121 | { |
3ac21baa JB |
2122 | return !((i.types[given].bitfield.xmmword |
2123 | && !t->operand_types[wanted].bitfield.xmmword) | |
2124 | || (i.types[given].bitfield.ymmword | |
2125 | && !t->operand_types[wanted].bitfield.ymmword) | |
2126 | || (i.types[given].bitfield.zmmword | |
2127 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2128 | } |
2129 | ||
7a54636a L |
2130 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2131 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2132 | |
2133 | static INLINE int | |
dd40ce22 L |
2134 | match_mem_size (const insn_template *t, unsigned int wanted, |
2135 | unsigned int given) | |
5c07affc | 2136 | { |
7a54636a | 2137 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2138 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2139 | && !i.broadcast |
3ac21baa JB |
2140 | && !t->operand_types[wanted].bitfield.unspecified) |
2141 | || (i.types[given].bitfield.fword | |
2142 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2143 | /* For scalar opcode templates to allow register and memory |
2144 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2145 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2146 | down-conversion vpmov*. */ | |
3528c362 | 2147 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
1b54b8d7 | 2148 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2149 | && (t->operand_types[wanted].bitfield.byte |
2150 | || t->operand_types[wanted].bitfield.word | |
2151 | || t->operand_types[wanted].bitfield.dword | |
2152 | || t->operand_types[wanted].bitfield.qword)) | |
2153 | ? (i.types[given].bitfield.xmmword | |
2154 | || i.types[given].bitfield.ymmword | |
2155 | || i.types[given].bitfield.zmmword) | |
2156 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2157 | } |
2158 | ||
3ac21baa JB |
2159 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2160 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2161 | is no size conflict on any operands for the template with operands reversed | |
2162 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2163 | |
3ac21baa JB |
2164 | #define MATCH_STRAIGHT 1 |
2165 | #define MATCH_REVERSE 2 | |
2166 | ||
2167 | static INLINE unsigned int | |
d3ce72d0 | 2168 | operand_size_match (const insn_template *t) |
5c07affc | 2169 | { |
3ac21baa | 2170 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2171 | |
0cfa3eb3 | 2172 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2173 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2174 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2175 | return match; |
2176 | ||
2177 | /* Check memory and accumulator operand size. */ | |
2178 | for (j = 0; j < i.operands; j++) | |
2179 | { | |
3528c362 JB |
2180 | if (i.types[j].bitfield.class != Reg |
2181 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2182 | && t->opcode_modifier.anysize) |
5c07affc L |
2183 | continue; |
2184 | ||
bab6aec1 | 2185 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2186 | && !match_operand_size (t, j, j)) |
5c07affc L |
2187 | { |
2188 | match = 0; | |
2189 | break; | |
2190 | } | |
2191 | ||
3528c362 | 2192 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2193 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2194 | { |
2195 | match = 0; | |
2196 | break; | |
2197 | } | |
2198 | ||
75e5731b | 2199 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2200 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2201 | { |
2202 | match = 0; | |
2203 | break; | |
2204 | } | |
2205 | ||
c48dadc9 | 2206 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2207 | { |
2208 | match = 0; | |
2209 | break; | |
2210 | } | |
2211 | } | |
2212 | ||
3ac21baa | 2213 | if (!t->opcode_modifier.d) |
891edac4 | 2214 | { |
dc1e8a47 | 2215 | mismatch: |
3ac21baa JB |
2216 | if (!match) |
2217 | i.error = operand_size_mismatch; | |
2218 | return match; | |
891edac4 | 2219 | } |
5c07affc L |
2220 | |
2221 | /* Check reverse. */ | |
f5eb1d70 | 2222 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2223 | |
f5eb1d70 | 2224 | for (j = 0; j < i.operands; j++) |
5c07affc | 2225 | { |
f5eb1d70 JB |
2226 | unsigned int given = i.operands - j - 1; |
2227 | ||
bab6aec1 | 2228 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2229 | && !match_operand_size (t, j, given)) |
891edac4 | 2230 | goto mismatch; |
5c07affc | 2231 | |
3528c362 | 2232 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2233 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2234 | goto mismatch; |
2235 | ||
75e5731b | 2236 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2237 | && (!match_operand_size (t, j, given) |
2238 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2239 | goto mismatch; |
2240 | ||
f5eb1d70 | 2241 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2242 | goto mismatch; |
5c07affc L |
2243 | } |
2244 | ||
3ac21baa | 2245 | return match | MATCH_REVERSE; |
5c07affc L |
2246 | } |
2247 | ||
c6fb90c8 | 2248 | static INLINE int |
40fb9820 L |
2249 | operand_type_match (i386_operand_type overlap, |
2250 | i386_operand_type given) | |
2251 | { | |
2252 | i386_operand_type temp = overlap; | |
2253 | ||
7d5e4556 | 2254 | temp.bitfield.unspecified = 0; |
5c07affc L |
2255 | temp.bitfield.byte = 0; |
2256 | temp.bitfield.word = 0; | |
2257 | temp.bitfield.dword = 0; | |
2258 | temp.bitfield.fword = 0; | |
2259 | temp.bitfield.qword = 0; | |
2260 | temp.bitfield.tbyte = 0; | |
2261 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2262 | temp.bitfield.ymmword = 0; |
43234a1e | 2263 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2264 | if (operand_type_all_zero (&temp)) |
891edac4 | 2265 | goto mismatch; |
40fb9820 | 2266 | |
6f2f06be | 2267 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2268 | return 1; |
2269 | ||
dc1e8a47 | 2270 | mismatch: |
a65babc9 | 2271 | i.error = operand_type_mismatch; |
891edac4 | 2272 | return 0; |
40fb9820 L |
2273 | } |
2274 | ||
7d5e4556 | 2275 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2276 | unless the expected operand type register overlap is null. |
5de4d9ef | 2277 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2278 | |
c6fb90c8 | 2279 | static INLINE int |
dc821c5f | 2280 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2281 | i386_operand_type t0, |
40fb9820 L |
2282 | i386_operand_type g1, |
2283 | i386_operand_type t1) | |
2284 | { | |
bab6aec1 | 2285 | if (g0.bitfield.class != Reg |
3528c362 | 2286 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2287 | && (!operand_type_check (g0, anymem) |
2288 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2289 | || (t0.bitfield.class != Reg |
2290 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2291 | return 1; |
2292 | ||
bab6aec1 | 2293 | if (g1.bitfield.class != Reg |
3528c362 | 2294 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2295 | && (!operand_type_check (g1, anymem) |
2296 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2297 | || (t1.bitfield.class != Reg |
2298 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2299 | return 1; |
2300 | ||
dc821c5f JB |
2301 | if (g0.bitfield.byte == g1.bitfield.byte |
2302 | && g0.bitfield.word == g1.bitfield.word | |
2303 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2304 | && g0.bitfield.qword == g1.bitfield.qword |
2305 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2306 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2307 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2308 | return 1; |
2309 | ||
dc821c5f JB |
2310 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2311 | && !(t0.bitfield.word & t1.bitfield.word) | |
2312 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2313 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2314 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2315 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2316 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2317 | return 1; |
2318 | ||
a65babc9 | 2319 | i.error = register_type_mismatch; |
891edac4 L |
2320 | |
2321 | return 0; | |
40fb9820 L |
2322 | } |
2323 | ||
4c692bc7 JB |
2324 | static INLINE unsigned int |
2325 | register_number (const reg_entry *r) | |
2326 | { | |
2327 | unsigned int nr = r->reg_num; | |
2328 | ||
2329 | if (r->reg_flags & RegRex) | |
2330 | nr += 8; | |
2331 | ||
200cbe0f L |
2332 | if (r->reg_flags & RegVRex) |
2333 | nr += 16; | |
2334 | ||
4c692bc7 JB |
2335 | return nr; |
2336 | } | |
2337 | ||
252b5132 | 2338 | static INLINE unsigned int |
40fb9820 | 2339 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2340 | { |
b5014f7a | 2341 | if (t.bitfield.disp8) |
40fb9820 L |
2342 | return 1; |
2343 | else if (t.bitfield.disp16 | |
2344 | || t.bitfield.disp32 | |
2345 | || t.bitfield.disp32s) | |
2346 | return 2; | |
2347 | else | |
2348 | return 0; | |
252b5132 RH |
2349 | } |
2350 | ||
2351 | static INLINE int | |
65879393 | 2352 | fits_in_signed_byte (addressT num) |
252b5132 | 2353 | { |
65879393 | 2354 | return num + 0x80 <= 0xff; |
47926f60 | 2355 | } |
252b5132 RH |
2356 | |
2357 | static INLINE int | |
65879393 | 2358 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2359 | { |
65879393 | 2360 | return num <= 0xff; |
47926f60 | 2361 | } |
252b5132 RH |
2362 | |
2363 | static INLINE int | |
65879393 | 2364 | fits_in_unsigned_word (addressT num) |
252b5132 | 2365 | { |
65879393 | 2366 | return num <= 0xffff; |
47926f60 | 2367 | } |
252b5132 RH |
2368 | |
2369 | static INLINE int | |
65879393 | 2370 | fits_in_signed_word (addressT num) |
252b5132 | 2371 | { |
65879393 | 2372 | return num + 0x8000 <= 0xffff; |
47926f60 | 2373 | } |
2a962e6d | 2374 | |
3e73aa7c | 2375 | static INLINE int |
65879393 | 2376 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2377 | { |
2378 | #ifndef BFD64 | |
2379 | return 1; | |
2380 | #else | |
65879393 | 2381 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2382 | #endif |
2383 | } /* fits_in_signed_long() */ | |
2a962e6d | 2384 | |
3e73aa7c | 2385 | static INLINE int |
65879393 | 2386 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2387 | { |
2388 | #ifndef BFD64 | |
2389 | return 1; | |
2390 | #else | |
65879393 | 2391 | return num <= 0xffffffff; |
3e73aa7c JH |
2392 | #endif |
2393 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2394 | |
43234a1e | 2395 | static INLINE int |
b5014f7a | 2396 | fits_in_disp8 (offsetT num) |
43234a1e L |
2397 | { |
2398 | int shift = i.memshift; | |
2399 | unsigned int mask; | |
2400 | ||
2401 | if (shift == -1) | |
2402 | abort (); | |
2403 | ||
2404 | mask = (1 << shift) - 1; | |
2405 | ||
2406 | /* Return 0 if NUM isn't properly aligned. */ | |
2407 | if ((num & mask)) | |
2408 | return 0; | |
2409 | ||
2410 | /* Check if NUM will fit in 8bit after shift. */ | |
2411 | return fits_in_signed_byte (num >> shift); | |
2412 | } | |
2413 | ||
a683cc34 SP |
2414 | static INLINE int |
2415 | fits_in_imm4 (offsetT num) | |
2416 | { | |
2417 | return (num & 0xf) == num; | |
2418 | } | |
2419 | ||
40fb9820 | 2420 | static i386_operand_type |
e3bb37b5 | 2421 | smallest_imm_type (offsetT num) |
252b5132 | 2422 | { |
40fb9820 | 2423 | i386_operand_type t; |
7ab9ffdd | 2424 | |
0dfbf9d7 | 2425 | operand_type_set (&t, 0); |
40fb9820 L |
2426 | t.bitfield.imm64 = 1; |
2427 | ||
2428 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2429 | { |
2430 | /* This code is disabled on the 486 because all the Imm1 forms | |
2431 | in the opcode table are slower on the i486. They're the | |
2432 | versions with the implicitly specified single-position | |
2433 | displacement, which has another syntax if you really want to | |
2434 | use that form. */ | |
40fb9820 L |
2435 | t.bitfield.imm1 = 1; |
2436 | t.bitfield.imm8 = 1; | |
2437 | t.bitfield.imm8s = 1; | |
2438 | t.bitfield.imm16 = 1; | |
2439 | t.bitfield.imm32 = 1; | |
2440 | t.bitfield.imm32s = 1; | |
2441 | } | |
2442 | else if (fits_in_signed_byte (num)) | |
2443 | { | |
2444 | t.bitfield.imm8 = 1; | |
2445 | t.bitfield.imm8s = 1; | |
2446 | t.bitfield.imm16 = 1; | |
2447 | t.bitfield.imm32 = 1; | |
2448 | t.bitfield.imm32s = 1; | |
2449 | } | |
2450 | else if (fits_in_unsigned_byte (num)) | |
2451 | { | |
2452 | t.bitfield.imm8 = 1; | |
2453 | t.bitfield.imm16 = 1; | |
2454 | t.bitfield.imm32 = 1; | |
2455 | t.bitfield.imm32s = 1; | |
2456 | } | |
2457 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2458 | { | |
2459 | t.bitfield.imm16 = 1; | |
2460 | t.bitfield.imm32 = 1; | |
2461 | t.bitfield.imm32s = 1; | |
2462 | } | |
2463 | else if (fits_in_signed_long (num)) | |
2464 | { | |
2465 | t.bitfield.imm32 = 1; | |
2466 | t.bitfield.imm32s = 1; | |
2467 | } | |
2468 | else if (fits_in_unsigned_long (num)) | |
2469 | t.bitfield.imm32 = 1; | |
2470 | ||
2471 | return t; | |
47926f60 | 2472 | } |
252b5132 | 2473 | |
847f7ad4 | 2474 | static offsetT |
e3bb37b5 | 2475 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2476 | { |
508866be | 2477 | addressT mask; |
ba2adb93 | 2478 | |
847f7ad4 AM |
2479 | switch (size) |
2480 | { | |
508866be L |
2481 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2482 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2483 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2484 | #ifdef BFD64 |
2485 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2486 | #endif | |
47926f60 | 2487 | default: abort (); |
847f7ad4 AM |
2488 | } |
2489 | ||
9de868bf L |
2490 | #ifdef BFD64 |
2491 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2492 | if (flag_code != CODE_64BIT | |
2493 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2494 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2495 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2496 | #endif |
ba2adb93 | 2497 | |
47926f60 | 2498 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2499 | { |
2500 | char buf1[40], buf2[40]; | |
2501 | ||
2502 | sprint_value (buf1, val); | |
2503 | sprint_value (buf2, val & mask); | |
2504 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2505 | } | |
2506 | return val & mask; | |
2507 | } | |
2508 | ||
c32fa91d L |
2509 | enum PREFIX_GROUP |
2510 | { | |
2511 | PREFIX_EXIST = 0, | |
2512 | PREFIX_LOCK, | |
2513 | PREFIX_REP, | |
04ef582a | 2514 | PREFIX_DS, |
c32fa91d L |
2515 | PREFIX_OTHER |
2516 | }; | |
2517 | ||
2518 | /* Returns | |
2519 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2520 | same class already exists. | |
2521 | b. PREFIX_LOCK if lock prefix is added. | |
2522 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2523 | d. PREFIX_DS if ds prefix is added. |
2524 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2525 | */ |
2526 | ||
2527 | static enum PREFIX_GROUP | |
e3bb37b5 | 2528 | add_prefix (unsigned int prefix) |
252b5132 | 2529 | { |
c32fa91d | 2530 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2531 | unsigned int q; |
252b5132 | 2532 | |
29b0f896 AM |
2533 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2534 | && flag_code == CODE_64BIT) | |
b1905489 | 2535 | { |
161a04f6 | 2536 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2537 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2538 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2539 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2540 | ret = PREFIX_EXIST; |
b1905489 JB |
2541 | q = REX_PREFIX; |
2542 | } | |
3e73aa7c | 2543 | else |
b1905489 JB |
2544 | { |
2545 | switch (prefix) | |
2546 | { | |
2547 | default: | |
2548 | abort (); | |
2549 | ||
b1905489 | 2550 | case DS_PREFIX_OPCODE: |
04ef582a L |
2551 | ret = PREFIX_DS; |
2552 | /* Fall through. */ | |
2553 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2554 | case ES_PREFIX_OPCODE: |
2555 | case FS_PREFIX_OPCODE: | |
2556 | case GS_PREFIX_OPCODE: | |
2557 | case SS_PREFIX_OPCODE: | |
2558 | q = SEG_PREFIX; | |
2559 | break; | |
2560 | ||
2561 | case REPNE_PREFIX_OPCODE: | |
2562 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2563 | q = REP_PREFIX; |
2564 | ret = PREFIX_REP; | |
2565 | break; | |
2566 | ||
b1905489 | 2567 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2568 | q = LOCK_PREFIX; |
2569 | ret = PREFIX_LOCK; | |
b1905489 JB |
2570 | break; |
2571 | ||
2572 | case FWAIT_OPCODE: | |
2573 | q = WAIT_PREFIX; | |
2574 | break; | |
2575 | ||
2576 | case ADDR_PREFIX_OPCODE: | |
2577 | q = ADDR_PREFIX; | |
2578 | break; | |
2579 | ||
2580 | case DATA_PREFIX_OPCODE: | |
2581 | q = DATA_PREFIX; | |
2582 | break; | |
2583 | } | |
2584 | if (i.prefix[q] != 0) | |
c32fa91d | 2585 | ret = PREFIX_EXIST; |
b1905489 | 2586 | } |
252b5132 | 2587 | |
b1905489 | 2588 | if (ret) |
252b5132 | 2589 | { |
b1905489 JB |
2590 | if (!i.prefix[q]) |
2591 | ++i.prefixes; | |
2592 | i.prefix[q] |= prefix; | |
252b5132 | 2593 | } |
b1905489 JB |
2594 | else |
2595 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2596 | |
252b5132 RH |
2597 | return ret; |
2598 | } | |
2599 | ||
2600 | static void | |
78f12dd3 | 2601 | update_code_flag (int value, int check) |
eecb386c | 2602 | { |
78f12dd3 L |
2603 | PRINTF_LIKE ((*as_error)); |
2604 | ||
1e9cc1c2 | 2605 | flag_code = (enum flag_code) value; |
40fb9820 L |
2606 | if (flag_code == CODE_64BIT) |
2607 | { | |
2608 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2609 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2610 | } |
2611 | else | |
2612 | { | |
2613 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2614 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2615 | } |
2616 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2617 | { |
78f12dd3 L |
2618 | if (check) |
2619 | as_error = as_fatal; | |
2620 | else | |
2621 | as_error = as_bad; | |
2622 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2623 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2624 | } |
40fb9820 | 2625 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2626 | { |
78f12dd3 L |
2627 | if (check) |
2628 | as_error = as_fatal; | |
2629 | else | |
2630 | as_error = as_bad; | |
2631 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2632 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2633 | } |
eecb386c AM |
2634 | stackop_size = '\0'; |
2635 | } | |
2636 | ||
78f12dd3 L |
2637 | static void |
2638 | set_code_flag (int value) | |
2639 | { | |
2640 | update_code_flag (value, 0); | |
2641 | } | |
2642 | ||
eecb386c | 2643 | static void |
e3bb37b5 | 2644 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2645 | { |
1e9cc1c2 | 2646 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2647 | if (flag_code != CODE_16BIT) |
2648 | abort (); | |
2649 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2650 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2651 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2652 | } |
2653 | ||
2654 | static void | |
e3bb37b5 | 2655 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2656 | { |
2657 | /* Find out if register prefixing is specified. */ | |
2658 | int ask_naked_reg = 0; | |
2659 | ||
2660 | SKIP_WHITESPACE (); | |
29b0f896 | 2661 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2662 | { |
d02603dc NC |
2663 | char *string; |
2664 | int e = get_symbol_name (&string); | |
252b5132 | 2665 | |
47926f60 | 2666 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2667 | ask_naked_reg = 1; |
47926f60 | 2668 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2669 | ask_naked_reg = -1; |
2670 | else | |
d0b47220 | 2671 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2672 | (void) restore_line_pointer (e); |
252b5132 RH |
2673 | } |
2674 | demand_empty_rest_of_line (); | |
c3332e24 | 2675 | |
252b5132 RH |
2676 | intel_syntax = syntax_flag; |
2677 | ||
2678 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2679 | allow_naked_reg = (intel_syntax |
2680 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2681 | else |
2682 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2683 | |
ee86248c | 2684 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2685 | |
e4a3b5a4 | 2686 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2687 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2688 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2689 | } |
2690 | ||
1efbbeb4 L |
2691 | static void |
2692 | set_intel_mnemonic (int mnemonic_flag) | |
2693 | { | |
e1d4d893 | 2694 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2695 | } |
2696 | ||
db51cc60 L |
2697 | static void |
2698 | set_allow_index_reg (int flag) | |
2699 | { | |
2700 | allow_index_reg = flag; | |
2701 | } | |
2702 | ||
cb19c032 | 2703 | static void |
7bab8ab5 | 2704 | set_check (int what) |
cb19c032 | 2705 | { |
7bab8ab5 JB |
2706 | enum check_kind *kind; |
2707 | const char *str; | |
2708 | ||
2709 | if (what) | |
2710 | { | |
2711 | kind = &operand_check; | |
2712 | str = "operand"; | |
2713 | } | |
2714 | else | |
2715 | { | |
2716 | kind = &sse_check; | |
2717 | str = "sse"; | |
2718 | } | |
2719 | ||
cb19c032 L |
2720 | SKIP_WHITESPACE (); |
2721 | ||
2722 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2723 | { | |
d02603dc NC |
2724 | char *string; |
2725 | int e = get_symbol_name (&string); | |
cb19c032 L |
2726 | |
2727 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2728 | *kind = check_none; |
cb19c032 | 2729 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2730 | *kind = check_warning; |
cb19c032 | 2731 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2732 | *kind = check_error; |
cb19c032 | 2733 | else |
7bab8ab5 | 2734 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2735 | (void) restore_line_pointer (e); |
cb19c032 L |
2736 | } |
2737 | else | |
7bab8ab5 | 2738 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2739 | |
2740 | demand_empty_rest_of_line (); | |
2741 | } | |
2742 | ||
8a9036a4 L |
2743 | static void |
2744 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2745 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2746 | { |
2747 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2748 | static const char *arch; | |
2749 | ||
2750 | /* Intel LIOM is only supported on ELF. */ | |
2751 | if (!IS_ELF) | |
2752 | return; | |
2753 | ||
2754 | if (!arch) | |
2755 | { | |
2756 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2757 | use default_arch. */ | |
2758 | arch = cpu_arch_name; | |
2759 | if (!arch) | |
2760 | arch = default_arch; | |
2761 | } | |
2762 | ||
81486035 L |
2763 | /* If we are targeting Intel MCU, we must enable it. */ |
2764 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2765 | || new_flag.bitfield.cpuiamcu) | |
2766 | return; | |
2767 | ||
3632d14b | 2768 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2769 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2770 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2771 | return; |
76ba9986 | 2772 | |
7a9068fe L |
2773 | /* If we are targeting Intel K1OM, we must enable it. */ |
2774 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2775 | || new_flag.bitfield.cpuk1om) | |
2776 | return; | |
2777 | ||
8a9036a4 L |
2778 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2779 | #endif | |
2780 | } | |
2781 | ||
e413e4e9 | 2782 | static void |
e3bb37b5 | 2783 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2784 | { |
47926f60 | 2785 | SKIP_WHITESPACE (); |
e413e4e9 | 2786 | |
29b0f896 | 2787 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2788 | { |
d02603dc NC |
2789 | char *string; |
2790 | int e = get_symbol_name (&string); | |
91d6fa6a | 2791 | unsigned int j; |
40fb9820 | 2792 | i386_cpu_flags flags; |
e413e4e9 | 2793 | |
91d6fa6a | 2794 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2795 | { |
91d6fa6a | 2796 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2797 | { |
91d6fa6a | 2798 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2799 | |
5c6af06e JB |
2800 | if (*string != '.') |
2801 | { | |
91d6fa6a | 2802 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2803 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2804 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2805 | if (flag_code == CODE_64BIT) |
2806 | { | |
2807 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2808 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2809 | } | |
2810 | else | |
2811 | { | |
2812 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2813 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2814 | } | |
91d6fa6a NC |
2815 | cpu_arch_isa = cpu_arch[j].type; |
2816 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2817 | if (!cpu_arch_tune_set) |
2818 | { | |
2819 | cpu_arch_tune = cpu_arch_isa; | |
2820 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2821 | } | |
5c6af06e JB |
2822 | break; |
2823 | } | |
40fb9820 | 2824 | |
293f5f65 L |
2825 | flags = cpu_flags_or (cpu_arch_flags, |
2826 | cpu_arch[j].flags); | |
81486035 | 2827 | |
5b64d091 | 2828 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2829 | { |
6305a203 L |
2830 | if (cpu_sub_arch_name) |
2831 | { | |
2832 | char *name = cpu_sub_arch_name; | |
2833 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2834 | cpu_arch[j].name, |
1bf57e9f | 2835 | (const char *) NULL); |
6305a203 L |
2836 | free (name); |
2837 | } | |
2838 | else | |
91d6fa6a | 2839 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2840 | cpu_arch_flags = flags; |
a586129e | 2841 | cpu_arch_isa_flags = flags; |
5c6af06e | 2842 | } |
0089dace L |
2843 | else |
2844 | cpu_arch_isa_flags | |
2845 | = cpu_flags_or (cpu_arch_isa_flags, | |
2846 | cpu_arch[j].flags); | |
d02603dc | 2847 | (void) restore_line_pointer (e); |
5c6af06e JB |
2848 | demand_empty_rest_of_line (); |
2849 | return; | |
e413e4e9 AM |
2850 | } |
2851 | } | |
293f5f65 L |
2852 | |
2853 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2854 | { | |
33eaf5de | 2855 | /* Disable an ISA extension. */ |
293f5f65 L |
2856 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2857 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2858 | { | |
2859 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2860 | cpu_noarch[j].flags); | |
2861 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2862 | { | |
2863 | if (cpu_sub_arch_name) | |
2864 | { | |
2865 | char *name = cpu_sub_arch_name; | |
2866 | cpu_sub_arch_name = concat (name, string, | |
2867 | (const char *) NULL); | |
2868 | free (name); | |
2869 | } | |
2870 | else | |
2871 | cpu_sub_arch_name = xstrdup (string); | |
2872 | cpu_arch_flags = flags; | |
2873 | cpu_arch_isa_flags = flags; | |
2874 | } | |
2875 | (void) restore_line_pointer (e); | |
2876 | demand_empty_rest_of_line (); | |
2877 | return; | |
2878 | } | |
2879 | ||
2880 | j = ARRAY_SIZE (cpu_arch); | |
2881 | } | |
2882 | ||
91d6fa6a | 2883 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2884 | as_bad (_("no such architecture: `%s'"), string); |
2885 | ||
2886 | *input_line_pointer = e; | |
2887 | } | |
2888 | else | |
2889 | as_bad (_("missing cpu architecture")); | |
2890 | ||
fddf5b5b AM |
2891 | no_cond_jump_promotion = 0; |
2892 | if (*input_line_pointer == ',' | |
29b0f896 | 2893 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2894 | { |
d02603dc NC |
2895 | char *string; |
2896 | char e; | |
2897 | ||
2898 | ++input_line_pointer; | |
2899 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2900 | |
2901 | if (strcmp (string, "nojumps") == 0) | |
2902 | no_cond_jump_promotion = 1; | |
2903 | else if (strcmp (string, "jumps") == 0) | |
2904 | ; | |
2905 | else | |
2906 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2907 | ||
d02603dc | 2908 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2909 | } |
2910 | ||
e413e4e9 AM |
2911 | demand_empty_rest_of_line (); |
2912 | } | |
2913 | ||
8a9036a4 L |
2914 | enum bfd_architecture |
2915 | i386_arch (void) | |
2916 | { | |
3632d14b | 2917 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2918 | { |
2919 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2920 | || flag_code != CODE_64BIT) | |
2921 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2922 | return bfd_arch_l1om; | |
2923 | } | |
7a9068fe L |
2924 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2925 | { | |
2926 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2927 | || flag_code != CODE_64BIT) | |
2928 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2929 | return bfd_arch_k1om; | |
2930 | } | |
81486035 L |
2931 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2932 | { | |
2933 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2934 | || flag_code == CODE_64BIT) | |
2935 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2936 | return bfd_arch_iamcu; | |
2937 | } | |
8a9036a4 L |
2938 | else |
2939 | return bfd_arch_i386; | |
2940 | } | |
2941 | ||
b9d79e03 | 2942 | unsigned long |
7016a5d5 | 2943 | i386_mach (void) |
b9d79e03 | 2944 | { |
351f65ca | 2945 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2946 | { |
3632d14b | 2947 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2948 | { |
351f65ca L |
2949 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2950 | || default_arch[6] != '\0') | |
8a9036a4 L |
2951 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2952 | return bfd_mach_l1om; | |
2953 | } | |
7a9068fe L |
2954 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2955 | { | |
2956 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2957 | || default_arch[6] != '\0') | |
2958 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2959 | return bfd_mach_k1om; | |
2960 | } | |
351f65ca | 2961 | else if (default_arch[6] == '\0') |
8a9036a4 | 2962 | return bfd_mach_x86_64; |
351f65ca L |
2963 | else |
2964 | return bfd_mach_x64_32; | |
8a9036a4 | 2965 | } |
5197d474 L |
2966 | else if (!strcmp (default_arch, "i386") |
2967 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2968 | { |
2969 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2970 | { | |
2971 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2972 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2973 | return bfd_mach_i386_iamcu; | |
2974 | } | |
2975 | else | |
2976 | return bfd_mach_i386_i386; | |
2977 | } | |
b9d79e03 | 2978 | else |
2b5d6a91 | 2979 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2980 | } |
b9d79e03 | 2981 | \f |
252b5132 | 2982 | void |
7016a5d5 | 2983 | md_begin (void) |
252b5132 RH |
2984 | { |
2985 | const char *hash_err; | |
2986 | ||
86fa6981 L |
2987 | /* Support pseudo prefixes like {disp32}. */ |
2988 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2989 | ||
47926f60 | 2990 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2991 | op_hash = hash_new (); |
2992 | ||
2993 | { | |
d3ce72d0 | 2994 | const insn_template *optab; |
29b0f896 | 2995 | templates *core_optab; |
252b5132 | 2996 | |
47926f60 KH |
2997 | /* Setup for loop. */ |
2998 | optab = i386_optab; | |
add39d23 | 2999 | core_optab = XNEW (templates); |
252b5132 RH |
3000 | core_optab->start = optab; |
3001 | ||
3002 | while (1) | |
3003 | { | |
3004 | ++optab; | |
3005 | if (optab->name == NULL | |
3006 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
3007 | { | |
3008 | /* different name --> ship out current template list; | |
47926f60 | 3009 | add to hash table; & begin anew. */ |
252b5132 RH |
3010 | core_optab->end = optab; |
3011 | hash_err = hash_insert (op_hash, | |
3012 | (optab - 1)->name, | |
5a49b8ac | 3013 | (void *) core_optab); |
252b5132 RH |
3014 | if (hash_err) |
3015 | { | |
b37df7c4 | 3016 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
3017 | (optab - 1)->name, |
3018 | hash_err); | |
3019 | } | |
3020 | if (optab->name == NULL) | |
3021 | break; | |
add39d23 | 3022 | core_optab = XNEW (templates); |
252b5132 RH |
3023 | core_optab->start = optab; |
3024 | } | |
3025 | } | |
3026 | } | |
3027 | ||
47926f60 | 3028 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
3029 | reg_hash = hash_new (); |
3030 | { | |
29b0f896 | 3031 | const reg_entry *regtab; |
c3fe08fa | 3032 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3033 | |
c3fe08fa | 3034 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 3035 | { |
5a49b8ac | 3036 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 3037 | if (hash_err) |
b37df7c4 | 3038 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
3039 | regtab->reg_name, |
3040 | hash_err); | |
252b5132 RH |
3041 | } |
3042 | } | |
3043 | ||
47926f60 | 3044 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3045 | { |
29b0f896 AM |
3046 | int c; |
3047 | char *p; | |
252b5132 RH |
3048 | |
3049 | for (c = 0; c < 256; c++) | |
3050 | { | |
3882b010 | 3051 | if (ISDIGIT (c)) |
252b5132 RH |
3052 | { |
3053 | digit_chars[c] = c; | |
3054 | mnemonic_chars[c] = c; | |
3055 | register_chars[c] = c; | |
3056 | operand_chars[c] = c; | |
3057 | } | |
3882b010 | 3058 | else if (ISLOWER (c)) |
252b5132 RH |
3059 | { |
3060 | mnemonic_chars[c] = c; | |
3061 | register_chars[c] = c; | |
3062 | operand_chars[c] = c; | |
3063 | } | |
3882b010 | 3064 | else if (ISUPPER (c)) |
252b5132 | 3065 | { |
3882b010 | 3066 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3067 | register_chars[c] = mnemonic_chars[c]; |
3068 | operand_chars[c] = c; | |
3069 | } | |
43234a1e | 3070 | else if (c == '{' || c == '}') |
86fa6981 L |
3071 | { |
3072 | mnemonic_chars[c] = c; | |
3073 | operand_chars[c] = c; | |
3074 | } | |
252b5132 | 3075 | |
3882b010 | 3076 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3077 | identifier_chars[c] = c; |
3078 | else if (c >= 128) | |
3079 | { | |
3080 | identifier_chars[c] = c; | |
3081 | operand_chars[c] = c; | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | #ifdef LEX_AT | |
3086 | identifier_chars['@'] = '@'; | |
32137342 NC |
3087 | #endif |
3088 | #ifdef LEX_QM | |
3089 | identifier_chars['?'] = '?'; | |
3090 | operand_chars['?'] = '?'; | |
252b5132 | 3091 | #endif |
252b5132 | 3092 | digit_chars['-'] = '-'; |
c0f3af97 | 3093 | mnemonic_chars['_'] = '_'; |
791fe849 | 3094 | mnemonic_chars['-'] = '-'; |
0003779b | 3095 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3096 | identifier_chars['_'] = '_'; |
3097 | identifier_chars['.'] = '.'; | |
3098 | ||
3099 | for (p = operand_special_chars; *p != '\0'; p++) | |
3100 | operand_chars[(unsigned char) *p] = *p; | |
3101 | } | |
3102 | ||
a4447b93 RH |
3103 | if (flag_code == CODE_64BIT) |
3104 | { | |
ca19b261 KT |
3105 | #if defined (OBJ_COFF) && defined (TE_PE) |
3106 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3107 | ? 32 : 16); | |
3108 | #else | |
a4447b93 | 3109 | x86_dwarf2_return_column = 16; |
ca19b261 | 3110 | #endif |
61ff971f | 3111 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3112 | } |
3113 | else | |
3114 | { | |
3115 | x86_dwarf2_return_column = 8; | |
3116 | x86_cie_data_alignment = -4; | |
3117 | } | |
e379e5f3 L |
3118 | |
3119 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3120 | can be turned into BRANCH_PREFIX frag. */ | |
3121 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3122 | abort (); | |
252b5132 RH |
3123 | } |
3124 | ||
3125 | void | |
e3bb37b5 | 3126 | i386_print_statistics (FILE *file) |
252b5132 RH |
3127 | { |
3128 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3129 | hash_print_statistics (file, "i386 register", reg_hash); | |
3130 | } | |
3131 | \f | |
252b5132 RH |
3132 | #ifdef DEBUG386 |
3133 | ||
ce8a8b2f | 3134 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3135 | static void pte (insn_template *); |
40fb9820 | 3136 | static void pt (i386_operand_type); |
e3bb37b5 L |
3137 | static void pe (expressionS *); |
3138 | static void ps (symbolS *); | |
252b5132 RH |
3139 | |
3140 | static void | |
2c703856 | 3141 | pi (const char *line, i386_insn *x) |
252b5132 | 3142 | { |
09137c09 | 3143 | unsigned int j; |
252b5132 RH |
3144 | |
3145 | fprintf (stdout, "%s: template ", line); | |
3146 | pte (&x->tm); | |
09f131f2 JH |
3147 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3148 | x->base_reg ? x->base_reg->reg_name : "none", | |
3149 | x->index_reg ? x->index_reg->reg_name : "none", | |
3150 | x->log2_scale_factor); | |
3151 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3152 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3153 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3154 | x->sib.base, x->sib.index, x->sib.scale); | |
3155 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3156 | (x->rex & REX_W) != 0, |
3157 | (x->rex & REX_R) != 0, | |
3158 | (x->rex & REX_X) != 0, | |
3159 | (x->rex & REX_B) != 0); | |
09137c09 | 3160 | for (j = 0; j < x->operands; j++) |
252b5132 | 3161 | { |
09137c09 SP |
3162 | fprintf (stdout, " #%d: ", j + 1); |
3163 | pt (x->types[j]); | |
252b5132 | 3164 | fprintf (stdout, "\n"); |
bab6aec1 | 3165 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3166 | || x->types[j].bitfield.class == RegMMX |
3167 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3168 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3169 | || x->types[j].bitfield.class == RegCR |
3170 | || x->types[j].bitfield.class == RegDR | |
3171 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3172 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3173 | if (operand_type_check (x->types[j], imm)) | |
3174 | pe (x->op[j].imms); | |
3175 | if (operand_type_check (x->types[j], disp)) | |
3176 | pe (x->op[j].disps); | |
252b5132 RH |
3177 | } |
3178 | } | |
3179 | ||
3180 | static void | |
d3ce72d0 | 3181 | pte (insn_template *t) |
252b5132 | 3182 | { |
09137c09 | 3183 | unsigned int j; |
252b5132 | 3184 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3185 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3186 | if (t->extension_opcode != None) |
3187 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3188 | if (t->opcode_modifier.d) |
252b5132 | 3189 | fprintf (stdout, "D"); |
40fb9820 | 3190 | if (t->opcode_modifier.w) |
252b5132 RH |
3191 | fprintf (stdout, "W"); |
3192 | fprintf (stdout, "\n"); | |
09137c09 | 3193 | for (j = 0; j < t->operands; j++) |
252b5132 | 3194 | { |
09137c09 SP |
3195 | fprintf (stdout, " #%d type ", j + 1); |
3196 | pt (t->operand_types[j]); | |
252b5132 RH |
3197 | fprintf (stdout, "\n"); |
3198 | } | |
3199 | } | |
3200 | ||
3201 | static void | |
e3bb37b5 | 3202 | pe (expressionS *e) |
252b5132 | 3203 | { |
24eab124 | 3204 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3205 | fprintf (stdout, " add_number %ld (%lx)\n", |
3206 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3207 | if (e->X_add_symbol) |
3208 | { | |
3209 | fprintf (stdout, " add_symbol "); | |
3210 | ps (e->X_add_symbol); | |
3211 | fprintf (stdout, "\n"); | |
3212 | } | |
3213 | if (e->X_op_symbol) | |
3214 | { | |
3215 | fprintf (stdout, " op_symbol "); | |
3216 | ps (e->X_op_symbol); | |
3217 | fprintf (stdout, "\n"); | |
3218 | } | |
3219 | } | |
3220 | ||
3221 | static void | |
e3bb37b5 | 3222 | ps (symbolS *s) |
252b5132 RH |
3223 | { |
3224 | fprintf (stdout, "%s type %s%s", | |
3225 | S_GET_NAME (s), | |
3226 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3227 | segment_name (S_GET_SEGMENT (s))); | |
3228 | } | |
3229 | ||
7b81dfbb | 3230 | static struct type_name |
252b5132 | 3231 | { |
40fb9820 L |
3232 | i386_operand_type mask; |
3233 | const char *name; | |
252b5132 | 3234 | } |
7b81dfbb | 3235 | const type_names[] = |
252b5132 | 3236 | { |
40fb9820 L |
3237 | { OPERAND_TYPE_REG8, "r8" }, |
3238 | { OPERAND_TYPE_REG16, "r16" }, | |
3239 | { OPERAND_TYPE_REG32, "r32" }, | |
3240 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3241 | { OPERAND_TYPE_ACC8, "acc8" }, |
3242 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3243 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3244 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3245 | { OPERAND_TYPE_IMM8, "i8" }, |
3246 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3247 | { OPERAND_TYPE_IMM16, "i16" }, | |
3248 | { OPERAND_TYPE_IMM32, "i32" }, | |
3249 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3250 | { OPERAND_TYPE_IMM64, "i64" }, | |
3251 | { OPERAND_TYPE_IMM1, "i1" }, | |
3252 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3253 | { OPERAND_TYPE_DISP8, "d8" }, | |
3254 | { OPERAND_TYPE_DISP16, "d16" }, | |
3255 | { OPERAND_TYPE_DISP32, "d32" }, | |
3256 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3257 | { OPERAND_TYPE_DISP64, "d64" }, | |
3258 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3259 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3260 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3261 | { OPERAND_TYPE_TEST, "test reg" }, | |
3262 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3263 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3264 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3265 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3266 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3267 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3268 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3269 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3270 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
252b5132 RH |
3271 | }; |
3272 | ||
3273 | static void | |
40fb9820 | 3274 | pt (i386_operand_type t) |
252b5132 | 3275 | { |
40fb9820 | 3276 | unsigned int j; |
c6fb90c8 | 3277 | i386_operand_type a; |
252b5132 | 3278 | |
40fb9820 | 3279 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3280 | { |
3281 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3282 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3283 | fprintf (stdout, "%s, ", type_names[j].name); |
3284 | } | |
252b5132 RH |
3285 | fflush (stdout); |
3286 | } | |
3287 | ||
3288 | #endif /* DEBUG386 */ | |
3289 | \f | |
252b5132 | 3290 | static bfd_reloc_code_real_type |
3956db08 | 3291 | reloc (unsigned int size, |
64e74474 AM |
3292 | int pcrel, |
3293 | int sign, | |
3294 | bfd_reloc_code_real_type other) | |
252b5132 | 3295 | { |
47926f60 | 3296 | if (other != NO_RELOC) |
3956db08 | 3297 | { |
91d6fa6a | 3298 | reloc_howto_type *rel; |
3956db08 JB |
3299 | |
3300 | if (size == 8) | |
3301 | switch (other) | |
3302 | { | |
64e74474 AM |
3303 | case BFD_RELOC_X86_64_GOT32: |
3304 | return BFD_RELOC_X86_64_GOT64; | |
3305 | break; | |
553d1284 L |
3306 | case BFD_RELOC_X86_64_GOTPLT64: |
3307 | return BFD_RELOC_X86_64_GOTPLT64; | |
3308 | break; | |
64e74474 AM |
3309 | case BFD_RELOC_X86_64_PLTOFF64: |
3310 | return BFD_RELOC_X86_64_PLTOFF64; | |
3311 | break; | |
3312 | case BFD_RELOC_X86_64_GOTPC32: | |
3313 | other = BFD_RELOC_X86_64_GOTPC64; | |
3314 | break; | |
3315 | case BFD_RELOC_X86_64_GOTPCREL: | |
3316 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3317 | break; | |
3318 | case BFD_RELOC_X86_64_TPOFF32: | |
3319 | other = BFD_RELOC_X86_64_TPOFF64; | |
3320 | break; | |
3321 | case BFD_RELOC_X86_64_DTPOFF32: | |
3322 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3323 | break; | |
3324 | default: | |
3325 | break; | |
3956db08 | 3326 | } |
e05278af | 3327 | |
8ce3d284 | 3328 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3329 | if (other == BFD_RELOC_SIZE32) |
3330 | { | |
3331 | if (size == 8) | |
1ab668bf | 3332 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3333 | if (pcrel) |
1ab668bf AM |
3334 | { |
3335 | as_bad (_("there are no pc-relative size relocations")); | |
3336 | return NO_RELOC; | |
3337 | } | |
8fd4256d | 3338 | } |
8ce3d284 | 3339 | #endif |
8fd4256d | 3340 | |
e05278af | 3341 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3342 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3343 | sign = -1; |
3344 | ||
91d6fa6a NC |
3345 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3346 | if (!rel) | |
3956db08 | 3347 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3348 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3349 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3350 | bfd_get_reloc_size (rel), |
3956db08 | 3351 | size); |
91d6fa6a | 3352 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3353 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3354 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3355 | && !sign) |
91d6fa6a | 3356 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3357 | && sign > 0)) |
3956db08 JB |
3358 | as_bad (_("relocated field and relocation type differ in signedness")); |
3359 | else | |
3360 | return other; | |
3361 | return NO_RELOC; | |
3362 | } | |
252b5132 RH |
3363 | |
3364 | if (pcrel) | |
3365 | { | |
3e73aa7c | 3366 | if (!sign) |
3956db08 | 3367 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3368 | switch (size) |
3369 | { | |
3370 | case 1: return BFD_RELOC_8_PCREL; | |
3371 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3372 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3373 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3374 | } |
3956db08 | 3375 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3376 | } |
3377 | else | |
3378 | { | |
3956db08 | 3379 | if (sign > 0) |
e5cb08ac | 3380 | switch (size) |
3e73aa7c JH |
3381 | { |
3382 | case 4: return BFD_RELOC_X86_64_32S; | |
3383 | } | |
3384 | else | |
3385 | switch (size) | |
3386 | { | |
3387 | case 1: return BFD_RELOC_8; | |
3388 | case 2: return BFD_RELOC_16; | |
3389 | case 4: return BFD_RELOC_32; | |
3390 | case 8: return BFD_RELOC_64; | |
3391 | } | |
3956db08 JB |
3392 | as_bad (_("cannot do %s %u byte relocation"), |
3393 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3394 | } |
3395 | ||
0cc9e1d3 | 3396 | return NO_RELOC; |
252b5132 RH |
3397 | } |
3398 | ||
47926f60 KH |
3399 | /* Here we decide which fixups can be adjusted to make them relative to |
3400 | the beginning of the section instead of the symbol. Basically we need | |
3401 | to make sure that the dynamic relocations are done correctly, so in | |
3402 | some cases we force the original symbol to be used. */ | |
3403 | ||
252b5132 | 3404 | int |
e3bb37b5 | 3405 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3406 | { |
6d249963 | 3407 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3408 | if (!IS_ELF) |
31312f95 AM |
3409 | return 1; |
3410 | ||
a161fe53 AM |
3411 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3412 | mode. */ | |
3413 | if (use_rela_relocations | |
3414 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3415 | && fixP->fx_pcrel) | |
252b5132 | 3416 | return 0; |
31312f95 | 3417 | |
8d01d9a9 AJ |
3418 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3419 | and changed later by validate_fix. */ | |
3420 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3421 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3422 | return 0; | |
3423 | ||
8fd4256d L |
3424 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3425 | for size relocations. */ | |
3426 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3427 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3428 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3429 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3430 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3431 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3432 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3433 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3434 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3435 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3436 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3437 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3438 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3439 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3440 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3441 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3442 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3443 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3444 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3445 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3446 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3447 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3448 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3449 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3450 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3451 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3452 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3453 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3454 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3455 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3456 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3457 | return 0; | |
31312f95 | 3458 | #endif |
252b5132 RH |
3459 | return 1; |
3460 | } | |
252b5132 | 3461 | |
b4cac588 | 3462 | static int |
e3bb37b5 | 3463 | intel_float_operand (const char *mnemonic) |
252b5132 | 3464 | { |
9306ca4a JB |
3465 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3466 | operands, hence the code here is free to improperly handle opcodes that | |
3467 | have no operands (for better performance and smaller code). */ | |
3468 | ||
3469 | if (mnemonic[0] != 'f') | |
3470 | return 0; /* non-math */ | |
3471 | ||
3472 | switch (mnemonic[1]) | |
3473 | { | |
3474 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3475 | the fs segment override prefix not currently handled because no | |
3476 | call path can make opcodes without operands get here */ | |
3477 | case 'i': | |
3478 | return 2 /* integer op */; | |
3479 | case 'l': | |
3480 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3481 | return 3; /* fldcw/fldenv */ | |
3482 | break; | |
3483 | case 'n': | |
3484 | if (mnemonic[2] != 'o' /* fnop */) | |
3485 | return 3; /* non-waiting control op */ | |
3486 | break; | |
3487 | case 'r': | |
3488 | if (mnemonic[2] == 's') | |
3489 | return 3; /* frstor/frstpm */ | |
3490 | break; | |
3491 | case 's': | |
3492 | if (mnemonic[2] == 'a') | |
3493 | return 3; /* fsave */ | |
3494 | if (mnemonic[2] == 't') | |
3495 | { | |
3496 | switch (mnemonic[3]) | |
3497 | { | |
3498 | case 'c': /* fstcw */ | |
3499 | case 'd': /* fstdw */ | |
3500 | case 'e': /* fstenv */ | |
3501 | case 's': /* fsts[gw] */ | |
3502 | return 3; | |
3503 | } | |
3504 | } | |
3505 | break; | |
3506 | case 'x': | |
3507 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3508 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3509 | break; | |
3510 | } | |
252b5132 | 3511 | |
9306ca4a | 3512 | return 1; |
252b5132 RH |
3513 | } |
3514 | ||
c0f3af97 L |
3515 | /* Build the VEX prefix. */ |
3516 | ||
3517 | static void | |
d3ce72d0 | 3518 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3519 | { |
3520 | unsigned int register_specifier; | |
3521 | unsigned int implied_prefix; | |
3522 | unsigned int vector_length; | |
03751133 | 3523 | unsigned int w; |
c0f3af97 L |
3524 | |
3525 | /* Check register specifier. */ | |
3526 | if (i.vex.register_specifier) | |
43234a1e L |
3527 | { |
3528 | register_specifier = | |
3529 | ~register_number (i.vex.register_specifier) & 0xf; | |
3530 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3531 | } | |
c0f3af97 L |
3532 | else |
3533 | register_specifier = 0xf; | |
3534 | ||
79f0fa25 L |
3535 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3536 | if there are more than 1 register operand. */ | |
3537 | if (i.reg_operands > 1 | |
3538 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3539 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3540 | && i.operands == i.reg_operands |
dbbc8b7e | 3541 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3542 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3543 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3544 | && i.rex == REX_B) |
3545 | { | |
3546 | unsigned int xchg = i.operands - 1; | |
3547 | union i386_op temp_op; | |
3548 | i386_operand_type temp_type; | |
3549 | ||
3550 | temp_type = i.types[xchg]; | |
3551 | i.types[xchg] = i.types[0]; | |
3552 | i.types[0] = temp_type; | |
3553 | temp_op = i.op[xchg]; | |
3554 | i.op[xchg] = i.op[0]; | |
3555 | i.op[0] = temp_op; | |
3556 | ||
9c2799c2 | 3557 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3558 | |
3559 | i.rex = REX_R; | |
3560 | xchg = i.rm.regmem; | |
3561 | i.rm.regmem = i.rm.reg; | |
3562 | i.rm.reg = xchg; | |
3563 | ||
dbbc8b7e JB |
3564 | if (i.tm.opcode_modifier.d) |
3565 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3566 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3567 | else /* Use the next insn. */ | |
3568 | i.tm = t[1]; | |
fa99fab2 L |
3569 | } |
3570 | ||
79dec6b7 JB |
3571 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3572 | are no memory operands and at least 3 register ones. */ | |
3573 | if (i.reg_operands >= 3 | |
3574 | && i.vec_encoding != vex_encoding_vex3 | |
3575 | && i.reg_operands == i.operands - i.imm_operands | |
3576 | && i.tm.opcode_modifier.vex | |
3577 | && i.tm.opcode_modifier.commutative | |
3578 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3579 | && i.rex == REX_B | |
3580 | && i.vex.register_specifier | |
3581 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3582 | { | |
3583 | unsigned int xchg = i.operands - i.reg_operands; | |
3584 | union i386_op temp_op; | |
3585 | i386_operand_type temp_type; | |
3586 | ||
3587 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3588 | gas_assert (!i.tm.opcode_modifier.sae); | |
3589 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3590 | &i.types[i.operands - 3])); | |
3591 | gas_assert (i.rm.mode == 3); | |
3592 | ||
3593 | temp_type = i.types[xchg]; | |
3594 | i.types[xchg] = i.types[xchg + 1]; | |
3595 | i.types[xchg + 1] = temp_type; | |
3596 | temp_op = i.op[xchg]; | |
3597 | i.op[xchg] = i.op[xchg + 1]; | |
3598 | i.op[xchg + 1] = temp_op; | |
3599 | ||
3600 | i.rex = 0; | |
3601 | xchg = i.rm.regmem | 8; | |
3602 | i.rm.regmem = ~register_specifier & 0xf; | |
3603 | gas_assert (!(i.rm.regmem & 8)); | |
3604 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3605 | register_specifier = ~xchg & 0xf; | |
3606 | } | |
3607 | ||
539f890d L |
3608 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3609 | vector_length = avxscalar; | |
10c17abd JB |
3610 | else if (i.tm.opcode_modifier.vex == VEX256) |
3611 | vector_length = 1; | |
539f890d | 3612 | else |
10c17abd | 3613 | { |
56522fc5 | 3614 | unsigned int op; |
10c17abd | 3615 | |
c7213af9 L |
3616 | /* Determine vector length from the last multi-length vector |
3617 | operand. */ | |
10c17abd | 3618 | vector_length = 0; |
56522fc5 | 3619 | for (op = t->operands; op--;) |
10c17abd JB |
3620 | if (t->operand_types[op].bitfield.xmmword |
3621 | && t->operand_types[op].bitfield.ymmword | |
3622 | && i.types[op].bitfield.ymmword) | |
3623 | { | |
3624 | vector_length = 1; | |
3625 | break; | |
3626 | } | |
3627 | } | |
c0f3af97 L |
3628 | |
3629 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3630 | { | |
3631 | case 0: | |
3632 | implied_prefix = 0; | |
3633 | break; | |
3634 | case DATA_PREFIX_OPCODE: | |
3635 | implied_prefix = 1; | |
3636 | break; | |
3637 | case REPE_PREFIX_OPCODE: | |
3638 | implied_prefix = 2; | |
3639 | break; | |
3640 | case REPNE_PREFIX_OPCODE: | |
3641 | implied_prefix = 3; | |
3642 | break; | |
3643 | default: | |
3644 | abort (); | |
3645 | } | |
3646 | ||
03751133 L |
3647 | /* Check the REX.W bit and VEXW. */ |
3648 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3649 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3650 | else if (i.tm.opcode_modifier.vexw) | |
3651 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3652 | else | |
931d03b7 | 3653 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3654 | |
c0f3af97 | 3655 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3656 | if (w == 0 |
3657 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3658 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3659 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3660 | { | |
3661 | /* 2-byte VEX prefix. */ | |
3662 | unsigned int r; | |
3663 | ||
3664 | i.vex.length = 2; | |
3665 | i.vex.bytes[0] = 0xc5; | |
3666 | ||
3667 | /* Check the REX.R bit. */ | |
3668 | r = (i.rex & REX_R) ? 0 : 1; | |
3669 | i.vex.bytes[1] = (r << 7 | |
3670 | | register_specifier << 3 | |
3671 | | vector_length << 2 | |
3672 | | implied_prefix); | |
3673 | } | |
3674 | else | |
3675 | { | |
3676 | /* 3-byte VEX prefix. */ | |
03751133 | 3677 | unsigned int m; |
c0f3af97 | 3678 | |
f88c9eb0 | 3679 | i.vex.length = 3; |
f88c9eb0 | 3680 | |
7f399153 | 3681 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3682 | { |
7f399153 L |
3683 | case VEX0F: |
3684 | m = 0x1; | |
80de6e00 | 3685 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3686 | break; |
3687 | case VEX0F38: | |
3688 | m = 0x2; | |
80de6e00 | 3689 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3690 | break; |
3691 | case VEX0F3A: | |
3692 | m = 0x3; | |
80de6e00 | 3693 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3694 | break; |
3695 | case XOP08: | |
5dd85c99 SP |
3696 | m = 0x8; |
3697 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3698 | break; |
3699 | case XOP09: | |
f88c9eb0 SP |
3700 | m = 0x9; |
3701 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3702 | break; |
3703 | case XOP0A: | |
f88c9eb0 SP |
3704 | m = 0xa; |
3705 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3706 | break; |
3707 | default: | |
3708 | abort (); | |
f88c9eb0 | 3709 | } |
c0f3af97 | 3710 | |
c0f3af97 L |
3711 | /* The high 3 bits of the second VEX byte are 1's compliment |
3712 | of RXB bits from REX. */ | |
3713 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3714 | ||
c0f3af97 L |
3715 | i.vex.bytes[2] = (w << 7 |
3716 | | register_specifier << 3 | |
3717 | | vector_length << 2 | |
3718 | | implied_prefix); | |
3719 | } | |
3720 | } | |
3721 | ||
e771e7c9 JB |
3722 | static INLINE bfd_boolean |
3723 | is_evex_encoding (const insn_template *t) | |
3724 | { | |
7091c612 | 3725 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3726 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3727 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3728 | } |
3729 | ||
7a8655d2 JB |
3730 | static INLINE bfd_boolean |
3731 | is_any_vex_encoding (const insn_template *t) | |
3732 | { | |
3733 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3734 | || is_evex_encoding (t); | |
3735 | } | |
3736 | ||
43234a1e L |
3737 | /* Build the EVEX prefix. */ |
3738 | ||
3739 | static void | |
3740 | build_evex_prefix (void) | |
3741 | { | |
3742 | unsigned int register_specifier; | |
3743 | unsigned int implied_prefix; | |
3744 | unsigned int m, w; | |
3745 | rex_byte vrex_used = 0; | |
3746 | ||
3747 | /* Check register specifier. */ | |
3748 | if (i.vex.register_specifier) | |
3749 | { | |
3750 | gas_assert ((i.vrex & REX_X) == 0); | |
3751 | ||
3752 | register_specifier = i.vex.register_specifier->reg_num; | |
3753 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3754 | register_specifier += 8; | |
3755 | /* The upper 16 registers are encoded in the fourth byte of the | |
3756 | EVEX prefix. */ | |
3757 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3758 | i.vex.bytes[3] = 0x8; | |
3759 | register_specifier = ~register_specifier & 0xf; | |
3760 | } | |
3761 | else | |
3762 | { | |
3763 | register_specifier = 0xf; | |
3764 | ||
3765 | /* Encode upper 16 vector index register in the fourth byte of | |
3766 | the EVEX prefix. */ | |
3767 | if (!(i.vrex & REX_X)) | |
3768 | i.vex.bytes[3] = 0x8; | |
3769 | else | |
3770 | vrex_used |= REX_X; | |
3771 | } | |
3772 | ||
3773 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3774 | { | |
3775 | case 0: | |
3776 | implied_prefix = 0; | |
3777 | break; | |
3778 | case DATA_PREFIX_OPCODE: | |
3779 | implied_prefix = 1; | |
3780 | break; | |
3781 | case REPE_PREFIX_OPCODE: | |
3782 | implied_prefix = 2; | |
3783 | break; | |
3784 | case REPNE_PREFIX_OPCODE: | |
3785 | implied_prefix = 3; | |
3786 | break; | |
3787 | default: | |
3788 | abort (); | |
3789 | } | |
3790 | ||
3791 | /* 4 byte EVEX prefix. */ | |
3792 | i.vex.length = 4; | |
3793 | i.vex.bytes[0] = 0x62; | |
3794 | ||
3795 | /* mmmm bits. */ | |
3796 | switch (i.tm.opcode_modifier.vexopcode) | |
3797 | { | |
3798 | case VEX0F: | |
3799 | m = 1; | |
3800 | break; | |
3801 | case VEX0F38: | |
3802 | m = 2; | |
3803 | break; | |
3804 | case VEX0F3A: | |
3805 | m = 3; | |
3806 | break; | |
3807 | default: | |
3808 | abort (); | |
3809 | break; | |
3810 | } | |
3811 | ||
3812 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3813 | bits from REX. */ | |
3814 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3815 | ||
3816 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3817 | REX_R bit in VREX. */ | |
3818 | if (!(i.vrex & REX_R)) | |
3819 | i.vex.bytes[1] |= 0x10; | |
3820 | else | |
3821 | vrex_used |= REX_R; | |
3822 | ||
3823 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3824 | { | |
3825 | /* When all operands are registers, the REX_X bit in REX is not | |
3826 | used. We reuse it to encode the upper 16 registers, which is | |
3827 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3828 | as 1's compliment. */ | |
3829 | if ((i.vrex & REX_B)) | |
3830 | { | |
3831 | vrex_used |= REX_B; | |
3832 | i.vex.bytes[1] &= ~0x40; | |
3833 | } | |
3834 | } | |
3835 | ||
3836 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3837 | i.vrex &= ~vrex_used; | |
3838 | gas_assert (i.vrex == 0); | |
3839 | ||
6865c043 L |
3840 | /* Check the REX.W bit and VEXW. */ |
3841 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3842 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3843 | else if (i.tm.opcode_modifier.vexw) | |
3844 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3845 | else | |
931d03b7 | 3846 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3847 | |
3848 | /* Encode the U bit. */ | |
3849 | implied_prefix |= 0x4; | |
3850 | ||
3851 | /* The third byte of the EVEX prefix. */ | |
3852 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3853 | ||
3854 | /* The fourth byte of the EVEX prefix. */ | |
3855 | /* The zeroing-masking bit. */ | |
3856 | if (i.mask && i.mask->zeroing) | |
3857 | i.vex.bytes[3] |= 0x80; | |
3858 | ||
3859 | /* Don't always set the broadcast bit if there is no RC. */ | |
3860 | if (!i.rounding) | |
3861 | { | |
3862 | /* Encode the vector length. */ | |
3863 | unsigned int vec_length; | |
3864 | ||
e771e7c9 JB |
3865 | if (!i.tm.opcode_modifier.evex |
3866 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3867 | { | |
56522fc5 | 3868 | unsigned int op; |
e771e7c9 | 3869 | |
c7213af9 L |
3870 | /* Determine vector length from the last multi-length vector |
3871 | operand. */ | |
e771e7c9 | 3872 | vec_length = 0; |
56522fc5 | 3873 | for (op = i.operands; op--;) |
e771e7c9 JB |
3874 | if (i.tm.operand_types[op].bitfield.xmmword |
3875 | + i.tm.operand_types[op].bitfield.ymmword | |
3876 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3877 | { | |
3878 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3879 | { |
3880 | i.tm.opcode_modifier.evex = EVEX512; | |
3881 | break; | |
3882 | } | |
e771e7c9 | 3883 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3884 | { |
3885 | i.tm.opcode_modifier.evex = EVEX256; | |
3886 | break; | |
3887 | } | |
e771e7c9 | 3888 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3889 | { |
3890 | i.tm.opcode_modifier.evex = EVEX128; | |
3891 | break; | |
3892 | } | |
625cbd7a JB |
3893 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3894 | { | |
4a1b91ea | 3895 | switch (i.broadcast->bytes) |
625cbd7a JB |
3896 | { |
3897 | case 64: | |
3898 | i.tm.opcode_modifier.evex = EVEX512; | |
3899 | break; | |
3900 | case 32: | |
3901 | i.tm.opcode_modifier.evex = EVEX256; | |
3902 | break; | |
3903 | case 16: | |
3904 | i.tm.opcode_modifier.evex = EVEX128; | |
3905 | break; | |
3906 | default: | |
c7213af9 | 3907 | abort (); |
625cbd7a | 3908 | } |
c7213af9 | 3909 | break; |
625cbd7a | 3910 | } |
e771e7c9 | 3911 | } |
c7213af9 | 3912 | |
56522fc5 | 3913 | if (op >= MAX_OPERANDS) |
c7213af9 | 3914 | abort (); |
e771e7c9 JB |
3915 | } |
3916 | ||
43234a1e L |
3917 | switch (i.tm.opcode_modifier.evex) |
3918 | { | |
3919 | case EVEXLIG: /* LL' is ignored */ | |
3920 | vec_length = evexlig << 5; | |
3921 | break; | |
3922 | case EVEX128: | |
3923 | vec_length = 0 << 5; | |
3924 | break; | |
3925 | case EVEX256: | |
3926 | vec_length = 1 << 5; | |
3927 | break; | |
3928 | case EVEX512: | |
3929 | vec_length = 2 << 5; | |
3930 | break; | |
3931 | default: | |
3932 | abort (); | |
3933 | break; | |
3934 | } | |
3935 | i.vex.bytes[3] |= vec_length; | |
3936 | /* Encode the broadcast bit. */ | |
3937 | if (i.broadcast) | |
3938 | i.vex.bytes[3] |= 0x10; | |
3939 | } | |
3940 | else | |
3941 | { | |
3942 | if (i.rounding->type != saeonly) | |
3943 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3944 | else | |
d3d3c6db | 3945 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3946 | } |
3947 | ||
3948 | if (i.mask && i.mask->mask) | |
3949 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3950 | } | |
3951 | ||
65da13b5 L |
3952 | static void |
3953 | process_immext (void) | |
3954 | { | |
3955 | expressionS *exp; | |
3956 | ||
c0f3af97 | 3957 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3958 | which is coded in the same place as an 8-bit immediate field |
3959 | would be. Here we fake an 8-bit immediate operand from the | |
3960 | opcode suffix stored in tm.extension_opcode. | |
3961 | ||
c1e679ec | 3962 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3963 | 3 argument instructions. */ |
65da13b5 | 3964 | |
43234a1e | 3965 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3966 | && (i.operands <= 2 |
7a8655d2 | 3967 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3968 | && i.operands <= 4))); |
65da13b5 L |
3969 | |
3970 | exp = &im_expressions[i.imm_operands++]; | |
3971 | i.op[i.operands].imms = exp; | |
3972 | i.types[i.operands] = imm8; | |
3973 | i.operands++; | |
3974 | exp->X_op = O_constant; | |
3975 | exp->X_add_number = i.tm.extension_opcode; | |
3976 | i.tm.extension_opcode = None; | |
3977 | } | |
3978 | ||
42164a71 L |
3979 | |
3980 | static int | |
3981 | check_hle (void) | |
3982 | { | |
3983 | switch (i.tm.opcode_modifier.hleprefixok) | |
3984 | { | |
3985 | default: | |
3986 | abort (); | |
82c2def5 | 3987 | case HLEPrefixNone: |
165de32a L |
3988 | as_bad (_("invalid instruction `%s' after `%s'"), |
3989 | i.tm.name, i.hle_prefix); | |
42164a71 | 3990 | return 0; |
82c2def5 | 3991 | case HLEPrefixLock: |
42164a71 L |
3992 | if (i.prefix[LOCK_PREFIX]) |
3993 | return 1; | |
165de32a | 3994 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3995 | return 0; |
82c2def5 | 3996 | case HLEPrefixAny: |
42164a71 | 3997 | return 1; |
82c2def5 | 3998 | case HLEPrefixRelease: |
42164a71 L |
3999 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4000 | { | |
4001 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4002 | i.tm.name); | |
4003 | return 0; | |
4004 | } | |
8dc0818e | 4005 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4006 | { |
4007 | as_bad (_("memory destination needed for instruction `%s'" | |
4008 | " after `xrelease'"), i.tm.name); | |
4009 | return 0; | |
4010 | } | |
4011 | return 1; | |
4012 | } | |
4013 | } | |
4014 | ||
b6f8c7c4 L |
4015 | /* Try the shortest encoding by shortening operand size. */ |
4016 | ||
4017 | static void | |
4018 | optimize_encoding (void) | |
4019 | { | |
a0a1771e | 4020 | unsigned int j; |
b6f8c7c4 L |
4021 | |
4022 | if (optimize_for_space | |
72aea328 | 4023 | && !is_any_vex_encoding (&i.tm) |
b6f8c7c4 L |
4024 | && i.reg_operands == 1 |
4025 | && i.imm_operands == 1 | |
4026 | && !i.types[1].bitfield.byte | |
4027 | && i.op[0].imms->X_op == O_constant | |
4028 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4029 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4030 | || (i.tm.base_opcode == 0xf6 |
4031 | && i.tm.extension_opcode == 0x0))) | |
4032 | { | |
4033 | /* Optimize: -Os: | |
4034 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4035 | */ | |
4036 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4037 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4038 | { | |
4039 | i.types[1].bitfield.byte = 1; | |
4040 | /* Ignore the suffix. */ | |
4041 | i.suffix = 0; | |
7697afb6 JB |
4042 | /* Convert to byte registers. */ |
4043 | if (i.types[1].bitfield.word) | |
4044 | j = 16; | |
4045 | else if (i.types[1].bitfield.dword) | |
4046 | j = 32; | |
4047 | else | |
4048 | j = 48; | |
4049 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4050 | j += 8; | |
4051 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4052 | } |
4053 | } | |
4054 | else if (flag_code == CODE_64BIT | |
72aea328 | 4055 | && !is_any_vex_encoding (&i.tm) |
d3d50934 L |
4056 | && ((i.types[1].bitfield.qword |
4057 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4058 | && i.imm_operands == 1 |
4059 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4060 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4061 | && i.tm.extension_opcode == None |
4062 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4063 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4064 | && ((i.tm.base_opcode == 0x24 |
4065 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4066 | || (i.tm.base_opcode == 0x80 |
4067 | && i.tm.extension_opcode == 0x4) | |
4068 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4069 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4070 | && i.tm.extension_opcode == 0x0))) |
4071 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4072 | && i.tm.base_opcode == 0x83 | |
4073 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4074 | || (i.types[0].bitfield.qword |
4075 | && ((i.reg_operands == 2 | |
4076 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4077 | && (i.tm.base_opcode == 0x30 |
4078 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4079 | || (i.reg_operands == 1 |
4080 | && i.operands == 1 | |
72aea328 | 4081 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4082 | { |
4083 | /* Optimize: -O: | |
4084 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4085 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4086 | testq $imm31, %r64 -> testl $imm31, %r32 |
4087 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4088 | subq %r64, %r64 -> subl %r32, %r32 | |
4089 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4090 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4091 | */ | |
4092 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4093 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4094 | { |
4095 | /* Handle | |
4096 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4097 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4098 | */ | |
4099 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4100 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4101 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4102 | i.types[0].bitfield.imm32 = 1; | |
4103 | i.types[0].bitfield.imm32s = 0; | |
4104 | i.types[0].bitfield.imm64 = 0; | |
4105 | i.types[1].bitfield.dword = 1; | |
4106 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4107 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4108 | { |
4109 | /* Handle | |
4110 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4111 | */ | |
507916b8 | 4112 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4113 | i.tm.extension_opcode = None; |
507916b8 | 4114 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4115 | i.tm.opcode_modifier.modrm = 0; |
4116 | } | |
4117 | } | |
4118 | } | |
5641ec01 JB |
4119 | else if (optimize > 1 |
4120 | && !optimize_for_space | |
72aea328 | 4121 | && !is_any_vex_encoding (&i.tm) |
5641ec01 JB |
4122 | && i.reg_operands == 2 |
4123 | && i.op[0].regs == i.op[1].regs | |
4124 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4125 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4126 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4127 | { | |
4128 | /* Optimize: -O2: | |
4129 | andb %rN, %rN -> testb %rN, %rN | |
4130 | andw %rN, %rN -> testw %rN, %rN | |
4131 | andq %rN, %rN -> testq %rN, %rN | |
4132 | orb %rN, %rN -> testb %rN, %rN | |
4133 | orw %rN, %rN -> testw %rN, %rN | |
4134 | orq %rN, %rN -> testq %rN, %rN | |
4135 | ||
4136 | and outside of 64-bit mode | |
4137 | ||
4138 | andl %rN, %rN -> testl %rN, %rN | |
4139 | orl %rN, %rN -> testl %rN, %rN | |
4140 | */ | |
4141 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4142 | } | |
99112332 | 4143 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4144 | && i.op[0].regs == i.op[1].regs |
4145 | && !i.types[2].bitfield.xmmword | |
4146 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4147 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4148 | && !i.rounding |
e771e7c9 | 4149 | && is_evex_encoding (&i.tm) |
80c34c38 | 4150 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4151 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4152 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4153 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4154 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4155 | && ((i.tm.base_opcode == 0x55 |
4156 | || i.tm.base_opcode == 0x6655 | |
4157 | || i.tm.base_opcode == 0x66df | |
4158 | || i.tm.base_opcode == 0x57 | |
4159 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4160 | || i.tm.base_opcode == 0x66ef |
4161 | || i.tm.base_opcode == 0x66f8 | |
4162 | || i.tm.base_opcode == 0x66f9 | |
4163 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4164 | || i.tm.base_opcode == 0x66fb |
4165 | || i.tm.base_opcode == 0x42 | |
4166 | || i.tm.base_opcode == 0x6642 | |
4167 | || i.tm.base_opcode == 0x47 | |
4168 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4169 | && i.tm.extension_opcode == None)) |
4170 | { | |
99112332 | 4171 | /* Optimize: -O1: |
8305403a L |
4172 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4173 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4174 | EVEX VOP %zmmM, %zmmM, %zmmN |
4175 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4176 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4177 | EVEX VOP %ymmM, %ymmM, %ymmN |
4178 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4179 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4180 | VEX VOP %ymmM, %ymmM, %ymmN |
4181 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4182 | VOP, one of vpandn and vpxor: | |
4183 | VEX VOP %ymmM, %ymmM, %ymmN | |
4184 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4185 | VOP, one of vpandnd and vpandnq: | |
4186 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4187 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4188 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4189 | EVEX VOP %ymmM, %ymmM, %ymmN |
4190 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4191 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4192 | VOP, one of vpxord and vpxorq: |
4193 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4194 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4195 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4196 | EVEX VOP %ymmM, %ymmM, %ymmN |
4197 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4198 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4199 | VOP, one of kxord and kxorq: |
4200 | VEX VOP %kM, %kM, %kN | |
4201 | -> VEX kxorw %kM, %kM, %kN | |
4202 | VOP, one of kandnd and kandnq: | |
4203 | VEX VOP %kM, %kM, %kN | |
4204 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4205 | */ |
e771e7c9 | 4206 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4207 | { |
7b1d7ca1 | 4208 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4209 | { |
4210 | i.tm.opcode_modifier.vex = VEX128; | |
4211 | i.tm.opcode_modifier.vexw = VEXW0; | |
4212 | i.tm.opcode_modifier.evex = 0; | |
4213 | } | |
7b1d7ca1 | 4214 | else if (optimize > 1) |
dd22218c L |
4215 | i.tm.opcode_modifier.evex = EVEX128; |
4216 | else | |
4217 | return; | |
b6f8c7c4 | 4218 | } |
f74a6307 | 4219 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4220 | { |
4221 | i.tm.base_opcode &= 0xff; | |
4222 | i.tm.opcode_modifier.vexw = VEXW0; | |
4223 | } | |
b6f8c7c4 L |
4224 | else |
4225 | i.tm.opcode_modifier.vex = VEX128; | |
4226 | ||
4227 | if (i.tm.opcode_modifier.vex) | |
4228 | for (j = 0; j < 3; j++) | |
4229 | { | |
4230 | i.types[j].bitfield.xmmword = 1; | |
4231 | i.types[j].bitfield.ymmword = 0; | |
4232 | } | |
4233 | } | |
392a5972 | 4234 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4235 | && !i.types[0].bitfield.zmmword |
392a5972 | 4236 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4237 | && !i.mask |
a0a1771e | 4238 | && !i.broadcast |
97ed31ae | 4239 | && is_evex_encoding (&i.tm) |
392a5972 L |
4240 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4241 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4242 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4243 | || (i.tm.base_opcode & ~4) == 0x66db | |
4244 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4245 | && i.tm.extension_opcode == None) |
4246 | { | |
4247 | /* Optimize: -O1: | |
4248 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4249 | vmovdqu32 and vmovdqu64: | |
4250 | EVEX VOP %xmmM, %xmmN | |
4251 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4252 | EVEX VOP %ymmM, %ymmN | |
4253 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4254 | EVEX VOP %xmmM, mem | |
4255 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4256 | EVEX VOP %ymmM, mem | |
4257 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4258 | EVEX VOP mem, %xmmN | |
4259 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4260 | EVEX VOP mem, %ymmN | |
4261 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4262 | VOP, one of vpand, vpandn, vpor, vpxor: |
4263 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4264 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4265 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4266 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4267 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4268 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4269 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4270 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4271 | */ |
a0a1771e | 4272 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4273 | if (operand_type_check (i.types[j], disp) |
4274 | && i.op[j].disps->X_op == O_constant) | |
4275 | { | |
4276 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4277 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4278 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4279 | int evex_disp8, vex_disp8; | |
4280 | unsigned int memshift = i.memshift; | |
4281 | offsetT n = i.op[j].disps->X_add_number; | |
4282 | ||
4283 | evex_disp8 = fits_in_disp8 (n); | |
4284 | i.memshift = 0; | |
4285 | vex_disp8 = fits_in_disp8 (n); | |
4286 | if (evex_disp8 != vex_disp8) | |
4287 | { | |
4288 | i.memshift = memshift; | |
4289 | return; | |
4290 | } | |
4291 | ||
4292 | i.types[j].bitfield.disp8 = vex_disp8; | |
4293 | break; | |
4294 | } | |
4295 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4296 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4297 | i.tm.opcode_modifier.vex |
4298 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4299 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4300 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4301 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4302 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4303 | i.tm.opcode_modifier.evex = 0; |
4304 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4305 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4306 | i.tm.opcode_modifier.disp8memshift = 0; |
4307 | i.memshift = 0; | |
a0a1771e JB |
4308 | if (j < i.operands) |
4309 | i.types[j].bitfield.disp8 | |
4310 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4311 | } |
b6f8c7c4 L |
4312 | } |
4313 | ||
252b5132 RH |
4314 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4315 | machine dependent instruction. This function is supposed to emit | |
4316 | the frags/bytes it assembles to. */ | |
4317 | ||
4318 | void | |
65da13b5 | 4319 | md_assemble (char *line) |
252b5132 | 4320 | { |
40fb9820 | 4321 | unsigned int j; |
83b16ac6 | 4322 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4323 | const insn_template *t; |
252b5132 | 4324 | |
47926f60 | 4325 | /* Initialize globals. */ |
252b5132 RH |
4326 | memset (&i, '\0', sizeof (i)); |
4327 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4328 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4329 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4330 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4331 | save_stack_p = save_stack; |
252b5132 RH |
4332 | |
4333 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4334 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4335 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4336 | |
29b0f896 AM |
4337 | line = parse_insn (line, mnemonic); |
4338 | if (line == NULL) | |
4339 | return; | |
83b16ac6 | 4340 | mnem_suffix = i.suffix; |
252b5132 | 4341 | |
29b0f896 | 4342 | line = parse_operands (line, mnemonic); |
ee86248c | 4343 | this_operand = -1; |
8325cc63 JB |
4344 | xfree (i.memop1_string); |
4345 | i.memop1_string = NULL; | |
29b0f896 AM |
4346 | if (line == NULL) |
4347 | return; | |
252b5132 | 4348 | |
29b0f896 AM |
4349 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4350 | operands at hand. */ | |
4351 | ||
b630c145 JB |
4352 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
4353 | "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse | |
4354 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
4355 | that the immediate segment precedes the offset, as it does when in AT&T | |
4356 | mode. */ | |
4d456e3d L |
4357 | if (intel_syntax |
4358 | && i.operands > 1 | |
29b0f896 | 4359 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4360 | && (strcmp (mnemonic, "invlpga") != 0) |
eedb0f2c JB |
4361 | && (strncmp (mnemonic, "monitor", 7) != 0) |
4362 | && (strncmp (mnemonic, "mwait", 5) != 0) | |
b630c145 JB |
4363 | && (strcmp (mnemonic, "tpause") != 0) |
4364 | && (strcmp (mnemonic, "umwait") != 0) | |
40fb9820 L |
4365 | && !(operand_type_check (i.types[0], imm) |
4366 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4367 | swap_operands (); |
4368 | ||
ec56d5c0 JB |
4369 | /* The order of the immediates should be reversed |
4370 | for 2 immediates extrq and insertq instructions */ | |
4371 | if (i.imm_operands == 2 | |
4372 | && (strcmp (mnemonic, "extrq") == 0 | |
4373 | || strcmp (mnemonic, "insertq") == 0)) | |
4374 | swap_2_operands (0, 1); | |
4375 | ||
29b0f896 AM |
4376 | if (i.imm_operands) |
4377 | optimize_imm (); | |
4378 | ||
b300c311 L |
4379 | /* Don't optimize displacement for movabs since it only takes 64bit |
4380 | displacement. */ | |
4381 | if (i.disp_operands | |
a501d77e | 4382 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4383 | && (flag_code != CODE_64BIT |
4384 | || strcmp (mnemonic, "movabs") != 0)) | |
4385 | optimize_disp (); | |
29b0f896 AM |
4386 | |
4387 | /* Next, we find a template that matches the given insn, | |
4388 | making sure the overlap of the given operands types is consistent | |
4389 | with the template operand types. */ | |
252b5132 | 4390 | |
83b16ac6 | 4391 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4392 | return; |
252b5132 | 4393 | |
7bab8ab5 | 4394 | if (sse_check != check_none |
81f8a913 | 4395 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4396 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4397 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4398 | && (i.tm.cpu_flags.bitfield.cpusse |
4399 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4400 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4401 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4402 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e | 4403 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
569d50f1 | 4404 | || i.tm.cpu_flags.bitfield.cpusse4a |
6e3e5c9e JB |
4405 | || i.tm.cpu_flags.bitfield.cpupclmul |
4406 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4407 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4408 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4409 | { |
7bab8ab5 | 4410 | (sse_check == check_warning |
daf50ae7 L |
4411 | ? as_warn |
4412 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4413 | } | |
4414 | ||
40fb9820 | 4415 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4416 | if (!add_prefix (FWAIT_OPCODE)) |
4417 | return; | |
252b5132 | 4418 | |
d5de92cf L |
4419 | /* Check if REP prefix is OK. */ |
4420 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4421 | { | |
4422 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4423 | i.tm.name, i.rep_prefix); | |
4424 | return; | |
4425 | } | |
4426 | ||
c1ba0266 L |
4427 | /* Check for lock without a lockable instruction. Destination operand |
4428 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4429 | if (i.prefix[LOCK_PREFIX] |
4430 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4431 | || i.mem_operands == 0 |
4432 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4433 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4434 | { |
4435 | as_bad (_("expecting lockable instruction after `lock'")); | |
4436 | return; | |
4437 | } | |
4438 | ||
7a8655d2 JB |
4439 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4440 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4441 | { | |
4442 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4443 | return; | |
4444 | } | |
4445 | ||
42164a71 | 4446 | /* Check if HLE prefix is OK. */ |
165de32a | 4447 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4448 | return; |
4449 | ||
7e8b059b L |
4450 | /* Check BND prefix. */ |
4451 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4452 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4453 | ||
04ef582a | 4454 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4455 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4456 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4457 | |
327e8c42 JB |
4458 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4459 | { | |
4460 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4461 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4462 | else if (flag_code != CODE_16BIT | |
4463 | ? i.prefix[ADDR_PREFIX] | |
4464 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4465 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4466 | } | |
7e8b059b L |
4467 | |
4468 | /* Insert BND prefix. */ | |
76d3a78a JB |
4469 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4470 | { | |
4471 | if (!i.prefix[BND_PREFIX]) | |
4472 | add_prefix (BND_PREFIX_OPCODE); | |
4473 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4474 | { | |
4475 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4476 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4477 | } | |
4478 | } | |
7e8b059b | 4479 | |
29b0f896 | 4480 | /* Check string instruction segment overrides. */ |
51c8edf6 | 4481 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 4482 | { |
51c8edf6 | 4483 | gas_assert (i.mem_operands); |
29b0f896 | 4484 | if (!check_string ()) |
5dd0794d | 4485 | return; |
fc0763e6 | 4486 | i.disp_operands = 0; |
29b0f896 | 4487 | } |
5dd0794d | 4488 | |
b6f8c7c4 L |
4489 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4490 | optimize_encoding (); | |
4491 | ||
29b0f896 AM |
4492 | if (!process_suffix ()) |
4493 | return; | |
e413e4e9 | 4494 | |
bc0844ae L |
4495 | /* Update operand types. */ |
4496 | for (j = 0; j < i.operands; j++) | |
4497 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4498 | ||
29b0f896 AM |
4499 | /* Make still unresolved immediate matches conform to size of immediate |
4500 | given in i.suffix. */ | |
4501 | if (!finalize_imm ()) | |
4502 | return; | |
252b5132 | 4503 | |
40fb9820 | 4504 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4505 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4506 | |
9afe6eb8 L |
4507 | /* We only need to check those implicit registers for instructions |
4508 | with 3 operands or less. */ | |
4509 | if (i.operands <= 3) | |
4510 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4511 | if (i.types[j].bitfield.instance != InstanceNone |
4512 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4513 | i.reg_operands--; |
40fb9820 | 4514 | |
c0f3af97 L |
4515 | /* ImmExt should be processed after SSE2AVX. */ |
4516 | if (!i.tm.opcode_modifier.sse2avx | |
4517 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4518 | process_immext (); |
252b5132 | 4519 | |
29b0f896 AM |
4520 | /* For insns with operands there are more diddles to do to the opcode. */ |
4521 | if (i.operands) | |
4522 | { | |
4523 | if (!process_operands ()) | |
4524 | return; | |
4525 | } | |
40fb9820 | 4526 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4527 | { |
4528 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4529 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4530 | } | |
252b5132 | 4531 | |
7a8655d2 | 4532 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4533 | { |
c1dc7af5 | 4534 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4535 | { |
c1dc7af5 | 4536 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4537 | i.tm.name); |
4538 | return; | |
4539 | } | |
c0f3af97 | 4540 | |
9e5e5283 L |
4541 | if (i.tm.opcode_modifier.vex) |
4542 | build_vex_prefix (t); | |
4543 | else | |
4544 | build_evex_prefix (); | |
4545 | } | |
43234a1e | 4546 | |
5dd85c99 SP |
4547 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4548 | instructions may define INT_OPCODE as well, so avoid this corner | |
4549 | case for those instructions that use MODRM. */ | |
4550 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4551 | && !i.tm.opcode_modifier.modrm |
4552 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4553 | { |
4554 | i.tm.base_opcode = INT3_OPCODE; | |
4555 | i.imm_operands = 0; | |
4556 | } | |
252b5132 | 4557 | |
0cfa3eb3 JB |
4558 | if ((i.tm.opcode_modifier.jump == JUMP |
4559 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
4560 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
4561 | && i.op[0].disps->X_op == O_constant) |
4562 | { | |
4563 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4564 | the absolute address given by the constant. Since ix86 jumps and | |
4565 | calls are pc relative, we need to generate a reloc. */ | |
4566 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4567 | i.op[0].disps->X_op = O_symbol; | |
4568 | } | |
252b5132 | 4569 | |
40fb9820 | 4570 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4571 | i.rex |= REX_W; |
252b5132 | 4572 | |
29b0f896 AM |
4573 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4574 | instruction already has a prefix, we need to convert old | |
4575 | registers to new ones. */ | |
773f551c | 4576 | |
bab6aec1 | 4577 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4578 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4579 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4580 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4581 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4582 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4583 | && i.rex != 0)) |
4584 | { | |
4585 | int x; | |
726c5dcd | 4586 | |
29b0f896 AM |
4587 | i.rex |= REX_OPCODE; |
4588 | for (x = 0; x < 2; x++) | |
4589 | { | |
4590 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4591 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4592 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4593 | { |
3f93af61 | 4594 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
4595 | /* In case it is "hi" register, give up. */ |
4596 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4597 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4598 | "instruction requiring REX prefix."), |
a540244d | 4599 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4600 | |
29b0f896 AM |
4601 | /* Otherwise it is equivalent to the extended register. |
4602 | Since the encoding doesn't change this is merely | |
4603 | cosmetic cleanup for debug output. */ | |
4604 | ||
4605 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4606 | } |
29b0f896 AM |
4607 | } |
4608 | } | |
773f551c | 4609 | |
6b6b6807 L |
4610 | if (i.rex == 0 && i.rex_encoding) |
4611 | { | |
4612 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 4613 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
4614 | the REX_OPCODE byte. */ |
4615 | int x; | |
4616 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4617 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4618 | && i.types[x].bitfield.byte |
4619 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4620 | && i.op[x].regs->reg_num > 3) | |
4621 | { | |
3f93af61 | 4622 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
6b6b6807 L |
4623 | i.rex_encoding = FALSE; |
4624 | break; | |
4625 | } | |
4626 | ||
4627 | if (i.rex_encoding) | |
4628 | i.rex = REX_OPCODE; | |
4629 | } | |
4630 | ||
7ab9ffdd | 4631 | if (i.rex != 0) |
29b0f896 AM |
4632 | add_prefix (REX_OPCODE | i.rex); |
4633 | ||
4634 | /* We are ready to output the insn. */ | |
4635 | output_insn (); | |
e379e5f3 L |
4636 | |
4637 | last_insn.seg = now_seg; | |
4638 | ||
4639 | if (i.tm.opcode_modifier.isprefix) | |
4640 | { | |
4641 | last_insn.kind = last_insn_prefix; | |
4642 | last_insn.name = i.tm.name; | |
4643 | last_insn.file = as_where (&last_insn.line); | |
4644 | } | |
4645 | else | |
4646 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
4647 | } |
4648 | ||
4649 | static char * | |
e3bb37b5 | 4650 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4651 | { |
4652 | char *l = line; | |
4653 | char *token_start = l; | |
4654 | char *mnem_p; | |
5c6af06e | 4655 | int supported; |
d3ce72d0 | 4656 | const insn_template *t; |
b6169b20 | 4657 | char *dot_p = NULL; |
29b0f896 | 4658 | |
29b0f896 AM |
4659 | while (1) |
4660 | { | |
4661 | mnem_p = mnemonic; | |
4662 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4663 | { | |
b6169b20 L |
4664 | if (*mnem_p == '.') |
4665 | dot_p = mnem_p; | |
29b0f896 AM |
4666 | mnem_p++; |
4667 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4668 | { |
29b0f896 AM |
4669 | as_bad (_("no such instruction: `%s'"), token_start); |
4670 | return NULL; | |
4671 | } | |
4672 | l++; | |
4673 | } | |
4674 | if (!is_space_char (*l) | |
4675 | && *l != END_OF_INSN | |
e44823cf JB |
4676 | && (intel_syntax |
4677 | || (*l != PREFIX_SEPARATOR | |
4678 | && *l != ','))) | |
29b0f896 AM |
4679 | { |
4680 | as_bad (_("invalid character %s in mnemonic"), | |
4681 | output_invalid (*l)); | |
4682 | return NULL; | |
4683 | } | |
4684 | if (token_start == l) | |
4685 | { | |
e44823cf | 4686 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4687 | as_bad (_("expecting prefix; got nothing")); |
4688 | else | |
4689 | as_bad (_("expecting mnemonic; got nothing")); | |
4690 | return NULL; | |
4691 | } | |
45288df1 | 4692 | |
29b0f896 | 4693 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4694 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4695 | |
29b0f896 AM |
4696 | if (*l != END_OF_INSN |
4697 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4698 | && current_templates | |
40fb9820 | 4699 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4700 | { |
c6fb90c8 | 4701 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4702 | { |
4703 | as_bad ((flag_code != CODE_64BIT | |
4704 | ? _("`%s' is only supported in 64-bit mode") | |
4705 | : _("`%s' is not supported in 64-bit mode")), | |
4706 | current_templates->start->name); | |
4707 | return NULL; | |
4708 | } | |
29b0f896 AM |
4709 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4710 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4711 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4712 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4713 | && flag_code != CODE_64BIT |
673fe0f0 | 4714 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4715 | ^ (flag_code == CODE_16BIT))) |
4716 | { | |
4717 | as_bad (_("redundant %s prefix"), | |
4718 | current_templates->start->name); | |
4719 | return NULL; | |
45288df1 | 4720 | } |
86fa6981 | 4721 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4722 | { |
86fa6981 L |
4723 | /* Handle pseudo prefixes. */ |
4724 | switch (current_templates->start->base_opcode) | |
4725 | { | |
4726 | case 0x0: | |
4727 | /* {disp8} */ | |
4728 | i.disp_encoding = disp_encoding_8bit; | |
4729 | break; | |
4730 | case 0x1: | |
4731 | /* {disp32} */ | |
4732 | i.disp_encoding = disp_encoding_32bit; | |
4733 | break; | |
4734 | case 0x2: | |
4735 | /* {load} */ | |
4736 | i.dir_encoding = dir_encoding_load; | |
4737 | break; | |
4738 | case 0x3: | |
4739 | /* {store} */ | |
4740 | i.dir_encoding = dir_encoding_store; | |
4741 | break; | |
4742 | case 0x4: | |
42e04b36 L |
4743 | /* {vex} */ |
4744 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 L |
4745 | break; |
4746 | case 0x5: | |
4747 | /* {vex3} */ | |
4748 | i.vec_encoding = vex_encoding_vex3; | |
4749 | break; | |
4750 | case 0x6: | |
4751 | /* {evex} */ | |
4752 | i.vec_encoding = vex_encoding_evex; | |
4753 | break; | |
6b6b6807 L |
4754 | case 0x7: |
4755 | /* {rex} */ | |
4756 | i.rex_encoding = TRUE; | |
4757 | break; | |
b6f8c7c4 L |
4758 | case 0x8: |
4759 | /* {nooptimize} */ | |
4760 | i.no_optimize = TRUE; | |
4761 | break; | |
86fa6981 L |
4762 | default: |
4763 | abort (); | |
4764 | } | |
4765 | } | |
4766 | else | |
4767 | { | |
4768 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4769 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4770 | { |
4e9ac44a L |
4771 | case PREFIX_EXIST: |
4772 | return NULL; | |
4773 | case PREFIX_DS: | |
d777820b | 4774 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4775 | i.notrack_prefix = current_templates->start->name; |
4776 | break; | |
4777 | case PREFIX_REP: | |
4778 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4779 | i.hle_prefix = current_templates->start->name; | |
4780 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4781 | i.bnd_prefix = current_templates->start->name; | |
4782 | else | |
4783 | i.rep_prefix = current_templates->start->name; | |
4784 | break; | |
4785 | default: | |
4786 | break; | |
86fa6981 | 4787 | } |
29b0f896 AM |
4788 | } |
4789 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4790 | token_start = ++l; | |
4791 | } | |
4792 | else | |
4793 | break; | |
4794 | } | |
45288df1 | 4795 | |
30a55f88 | 4796 | if (!current_templates) |
b6169b20 | 4797 | { |
07d5e953 JB |
4798 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4799 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4800 | encoding. */ |
30a55f88 | 4801 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4802 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4803 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4804 | && dot_p[1] == 'd' |
4805 | && dot_p[2] == '8') | |
4806 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4807 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4808 | && dot_p[1] == 'd' |
4809 | && dot_p[2] == '3' | |
4810 | && dot_p[3] == '2') | |
a501d77e | 4811 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4812 | else |
4813 | goto check_suffix; | |
4814 | mnem_p = dot_p; | |
4815 | *dot_p = '\0'; | |
d3ce72d0 | 4816 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4817 | } |
4818 | ||
29b0f896 AM |
4819 | if (!current_templates) |
4820 | { | |
dc1e8a47 | 4821 | check_suffix: |
1c529385 | 4822 | if (mnem_p > mnemonic) |
29b0f896 | 4823 | { |
1c529385 LH |
4824 | /* See if we can get a match by trimming off a suffix. */ |
4825 | switch (mnem_p[-1]) | |
29b0f896 | 4826 | { |
1c529385 LH |
4827 | case WORD_MNEM_SUFFIX: |
4828 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4829 | i.suffix = SHORT_MNEM_SUFFIX; |
4830 | else | |
1c529385 LH |
4831 | /* Fall through. */ |
4832 | case BYTE_MNEM_SUFFIX: | |
4833 | case QWORD_MNEM_SUFFIX: | |
4834 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4835 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4836 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4837 | mnemonic); |
4838 | break; | |
4839 | case SHORT_MNEM_SUFFIX: | |
4840 | case LONG_MNEM_SUFFIX: | |
4841 | if (!intel_syntax) | |
4842 | { | |
4843 | i.suffix = mnem_p[-1]; | |
4844 | mnem_p[-1] = '\0'; | |
4845 | current_templates = (const templates *) hash_find (op_hash, | |
4846 | mnemonic); | |
4847 | } | |
4848 | break; | |
4849 | ||
4850 | /* Intel Syntax. */ | |
4851 | case 'd': | |
4852 | if (intel_syntax) | |
4853 | { | |
4854 | if (intel_float_operand (mnemonic) == 1) | |
4855 | i.suffix = SHORT_MNEM_SUFFIX; | |
4856 | else | |
4857 | i.suffix = LONG_MNEM_SUFFIX; | |
4858 | mnem_p[-1] = '\0'; | |
4859 | current_templates = (const templates *) hash_find (op_hash, | |
4860 | mnemonic); | |
4861 | } | |
4862 | break; | |
29b0f896 | 4863 | } |
29b0f896 | 4864 | } |
1c529385 | 4865 | |
29b0f896 AM |
4866 | if (!current_templates) |
4867 | { | |
4868 | as_bad (_("no such instruction: `%s'"), token_start); | |
4869 | return NULL; | |
4870 | } | |
4871 | } | |
252b5132 | 4872 | |
0cfa3eb3 JB |
4873 | if (current_templates->start->opcode_modifier.jump == JUMP |
4874 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
4875 | { |
4876 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4877 | predict taken and predict not taken respectively. | |
4878 | I'm not sure that branch hints actually do anything on loop | |
4879 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4880 | may work in the future and it doesn't hurt to accept them | |
4881 | now. */ | |
4882 | if (l[0] == ',' && l[1] == 'p') | |
4883 | { | |
4884 | if (l[2] == 't') | |
4885 | { | |
4886 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4887 | return NULL; | |
4888 | l += 3; | |
4889 | } | |
4890 | else if (l[2] == 'n') | |
4891 | { | |
4892 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4893 | return NULL; | |
4894 | l += 3; | |
4895 | } | |
4896 | } | |
4897 | } | |
4898 | /* Any other comma loses. */ | |
4899 | if (*l == ',') | |
4900 | { | |
4901 | as_bad (_("invalid character %s in mnemonic"), | |
4902 | output_invalid (*l)); | |
4903 | return NULL; | |
4904 | } | |
252b5132 | 4905 | |
29b0f896 | 4906 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4907 | supported = 0; |
4908 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4909 | { | |
c0f3af97 L |
4910 | supported |= cpu_flags_match (t); |
4911 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4912 | { |
4913 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4914 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4915 | |
548d0ee6 JB |
4916 | return l; |
4917 | } | |
29b0f896 | 4918 | } |
3629bb00 | 4919 | |
548d0ee6 JB |
4920 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4921 | as_bad (flag_code == CODE_64BIT | |
4922 | ? _("`%s' is not supported in 64-bit mode") | |
4923 | : _("`%s' is only supported in 64-bit mode"), | |
4924 | current_templates->start->name); | |
4925 | else | |
4926 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4927 | current_templates->start->name, | |
4928 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4929 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4930 | |
548d0ee6 | 4931 | return NULL; |
29b0f896 | 4932 | } |
252b5132 | 4933 | |
29b0f896 | 4934 | static char * |
e3bb37b5 | 4935 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4936 | { |
4937 | char *token_start; | |
3138f287 | 4938 | |
29b0f896 AM |
4939 | /* 1 if operand is pending after ','. */ |
4940 | unsigned int expecting_operand = 0; | |
252b5132 | 4941 | |
29b0f896 AM |
4942 | /* Non-zero if operand parens not balanced. */ |
4943 | unsigned int paren_not_balanced; | |
4944 | ||
4945 | while (*l != END_OF_INSN) | |
4946 | { | |
4947 | /* Skip optional white space before operand. */ | |
4948 | if (is_space_char (*l)) | |
4949 | ++l; | |
d02603dc | 4950 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4951 | { |
4952 | as_bad (_("invalid character %s before operand %d"), | |
4953 | output_invalid (*l), | |
4954 | i.operands + 1); | |
4955 | return NULL; | |
4956 | } | |
d02603dc | 4957 | token_start = l; /* After white space. */ |
29b0f896 AM |
4958 | paren_not_balanced = 0; |
4959 | while (paren_not_balanced || *l != ',') | |
4960 | { | |
4961 | if (*l == END_OF_INSN) | |
4962 | { | |
4963 | if (paren_not_balanced) | |
4964 | { | |
4965 | if (!intel_syntax) | |
4966 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4967 | i.operands + 1); | |
4968 | else | |
4969 | as_bad (_("unbalanced brackets in operand %d."), | |
4970 | i.operands + 1); | |
4971 | return NULL; | |
4972 | } | |
4973 | else | |
4974 | break; /* we are done */ | |
4975 | } | |
d02603dc | 4976 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4977 | { |
4978 | as_bad (_("invalid character %s in operand %d"), | |
4979 | output_invalid (*l), | |
4980 | i.operands + 1); | |
4981 | return NULL; | |
4982 | } | |
4983 | if (!intel_syntax) | |
4984 | { | |
4985 | if (*l == '(') | |
4986 | ++paren_not_balanced; | |
4987 | if (*l == ')') | |
4988 | --paren_not_balanced; | |
4989 | } | |
4990 | else | |
4991 | { | |
4992 | if (*l == '[') | |
4993 | ++paren_not_balanced; | |
4994 | if (*l == ']') | |
4995 | --paren_not_balanced; | |
4996 | } | |
4997 | l++; | |
4998 | } | |
4999 | if (l != token_start) | |
5000 | { /* Yes, we've read in another operand. */ | |
5001 | unsigned int operand_ok; | |
5002 | this_operand = i.operands++; | |
5003 | if (i.operands > MAX_OPERANDS) | |
5004 | { | |
5005 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5006 | MAX_OPERANDS); | |
5007 | return NULL; | |
5008 | } | |
9d46ce34 | 5009 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5010 | /* Now parse operand adding info to 'i' as we go along. */ |
5011 | END_STRING_AND_SAVE (l); | |
5012 | ||
1286ab78 L |
5013 | if (i.mem_operands > 1) |
5014 | { | |
5015 | as_bad (_("too many memory references for `%s'"), | |
5016 | mnemonic); | |
5017 | return 0; | |
5018 | } | |
5019 | ||
29b0f896 AM |
5020 | if (intel_syntax) |
5021 | operand_ok = | |
5022 | i386_intel_operand (token_start, | |
5023 | intel_float_operand (mnemonic)); | |
5024 | else | |
a7619375 | 5025 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5026 | |
5027 | RESTORE_END_STRING (l); | |
5028 | if (!operand_ok) | |
5029 | return NULL; | |
5030 | } | |
5031 | else | |
5032 | { | |
5033 | if (expecting_operand) | |
5034 | { | |
5035 | expecting_operand_after_comma: | |
5036 | as_bad (_("expecting operand after ','; got nothing")); | |
5037 | return NULL; | |
5038 | } | |
5039 | if (*l == ',') | |
5040 | { | |
5041 | as_bad (_("expecting operand before ','; got nothing")); | |
5042 | return NULL; | |
5043 | } | |
5044 | } | |
7f3f1ea2 | 5045 | |
29b0f896 AM |
5046 | /* Now *l must be either ',' or END_OF_INSN. */ |
5047 | if (*l == ',') | |
5048 | { | |
5049 | if (*++l == END_OF_INSN) | |
5050 | { | |
5051 | /* Just skip it, if it's \n complain. */ | |
5052 | goto expecting_operand_after_comma; | |
5053 | } | |
5054 | expecting_operand = 1; | |
5055 | } | |
5056 | } | |
5057 | return l; | |
5058 | } | |
7f3f1ea2 | 5059 | |
050dfa73 | 5060 | static void |
4d456e3d | 5061 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
5062 | { |
5063 | union i386_op temp_op; | |
40fb9820 | 5064 | i386_operand_type temp_type; |
c48dadc9 | 5065 | unsigned int temp_flags; |
050dfa73 | 5066 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5067 | |
050dfa73 MM |
5068 | temp_type = i.types[xchg2]; |
5069 | i.types[xchg2] = i.types[xchg1]; | |
5070 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5071 | |
5072 | temp_flags = i.flags[xchg2]; | |
5073 | i.flags[xchg2] = i.flags[xchg1]; | |
5074 | i.flags[xchg1] = temp_flags; | |
5075 | ||
050dfa73 MM |
5076 | temp_op = i.op[xchg2]; |
5077 | i.op[xchg2] = i.op[xchg1]; | |
5078 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5079 | |
050dfa73 MM |
5080 | temp_reloc = i.reloc[xchg2]; |
5081 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5082 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5083 | |
5084 | if (i.mask) | |
5085 | { | |
5086 | if (i.mask->operand == xchg1) | |
5087 | i.mask->operand = xchg2; | |
5088 | else if (i.mask->operand == xchg2) | |
5089 | i.mask->operand = xchg1; | |
5090 | } | |
5091 | if (i.broadcast) | |
5092 | { | |
5093 | if (i.broadcast->operand == xchg1) | |
5094 | i.broadcast->operand = xchg2; | |
5095 | else if (i.broadcast->operand == xchg2) | |
5096 | i.broadcast->operand = xchg1; | |
5097 | } | |
5098 | if (i.rounding) | |
5099 | { | |
5100 | if (i.rounding->operand == xchg1) | |
5101 | i.rounding->operand = xchg2; | |
5102 | else if (i.rounding->operand == xchg2) | |
5103 | i.rounding->operand = xchg1; | |
5104 | } | |
050dfa73 MM |
5105 | } |
5106 | ||
29b0f896 | 5107 | static void |
e3bb37b5 | 5108 | swap_operands (void) |
29b0f896 | 5109 | { |
b7c61d9a | 5110 | switch (i.operands) |
050dfa73 | 5111 | { |
c0f3af97 | 5112 | case 5: |
b7c61d9a | 5113 | case 4: |
4d456e3d | 5114 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5115 | /* Fall through. */ |
b7c61d9a L |
5116 | case 3: |
5117 | case 2: | |
4d456e3d | 5118 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5119 | break; |
5120 | default: | |
5121 | abort (); | |
29b0f896 | 5122 | } |
29b0f896 AM |
5123 | |
5124 | if (i.mem_operands == 2) | |
5125 | { | |
5126 | const seg_entry *temp_seg; | |
5127 | temp_seg = i.seg[0]; | |
5128 | i.seg[0] = i.seg[1]; | |
5129 | i.seg[1] = temp_seg; | |
5130 | } | |
5131 | } | |
252b5132 | 5132 | |
29b0f896 AM |
5133 | /* Try to ensure constant immediates are represented in the smallest |
5134 | opcode possible. */ | |
5135 | static void | |
e3bb37b5 | 5136 | optimize_imm (void) |
29b0f896 AM |
5137 | { |
5138 | char guess_suffix = 0; | |
5139 | int op; | |
252b5132 | 5140 | |
29b0f896 AM |
5141 | if (i.suffix) |
5142 | guess_suffix = i.suffix; | |
5143 | else if (i.reg_operands) | |
5144 | { | |
5145 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5146 | We can't do this properly yet, i.e. excluding special register |
5147 | instances, but the following works for instructions with | |
5148 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5149 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5150 | if (i.types[op].bitfield.class != Reg) |
5151 | continue; | |
5152 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5153 | { |
40fb9820 L |
5154 | guess_suffix = BYTE_MNEM_SUFFIX; |
5155 | break; | |
5156 | } | |
bab6aec1 | 5157 | else if (i.types[op].bitfield.word) |
252b5132 | 5158 | { |
40fb9820 L |
5159 | guess_suffix = WORD_MNEM_SUFFIX; |
5160 | break; | |
5161 | } | |
bab6aec1 | 5162 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5163 | { |
5164 | guess_suffix = LONG_MNEM_SUFFIX; | |
5165 | break; | |
5166 | } | |
bab6aec1 | 5167 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5168 | { |
5169 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5170 | break; |
252b5132 | 5171 | } |
29b0f896 AM |
5172 | } |
5173 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5174 | guess_suffix = WORD_MNEM_SUFFIX; | |
5175 | ||
5176 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5177 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5178 | { |
5179 | switch (i.op[op].imms->X_op) | |
252b5132 | 5180 | { |
29b0f896 AM |
5181 | case O_constant: |
5182 | /* If a suffix is given, this operand may be shortened. */ | |
5183 | switch (guess_suffix) | |
252b5132 | 5184 | { |
29b0f896 | 5185 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5186 | i.types[op].bitfield.imm32 = 1; |
5187 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5188 | break; |
5189 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5190 | i.types[op].bitfield.imm16 = 1; |
5191 | i.types[op].bitfield.imm32 = 1; | |
5192 | i.types[op].bitfield.imm32s = 1; | |
5193 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5194 | break; |
5195 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5196 | i.types[op].bitfield.imm8 = 1; |
5197 | i.types[op].bitfield.imm8s = 1; | |
5198 | i.types[op].bitfield.imm16 = 1; | |
5199 | i.types[op].bitfield.imm32 = 1; | |
5200 | i.types[op].bitfield.imm32s = 1; | |
5201 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5202 | break; |
252b5132 | 5203 | } |
252b5132 | 5204 | |
29b0f896 AM |
5205 | /* If this operand is at most 16 bits, convert it |
5206 | to a signed 16 bit number before trying to see | |
5207 | whether it will fit in an even smaller size. | |
5208 | This allows a 16-bit operand such as $0xffe0 to | |
5209 | be recognised as within Imm8S range. */ | |
40fb9820 | 5210 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5211 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5212 | { |
29b0f896 AM |
5213 | i.op[op].imms->X_add_number = |
5214 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5215 | } | |
a28def75 L |
5216 | #ifdef BFD64 |
5217 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5218 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5219 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5220 | == 0)) | |
5221 | { | |
5222 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5223 | ^ ((offsetT) 1 << 31)) | |
5224 | - ((offsetT) 1 << 31)); | |
5225 | } | |
a28def75 | 5226 | #endif |
40fb9820 | 5227 | i.types[op] |
c6fb90c8 L |
5228 | = operand_type_or (i.types[op], |
5229 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5230 | |
29b0f896 AM |
5231 | /* We must avoid matching of Imm32 templates when 64bit |
5232 | only immediate is available. */ | |
5233 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5234 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5235 | break; |
252b5132 | 5236 | |
29b0f896 AM |
5237 | case O_absent: |
5238 | case O_register: | |
5239 | abort (); | |
5240 | ||
5241 | /* Symbols and expressions. */ | |
5242 | default: | |
9cd96992 JB |
5243 | /* Convert symbolic operand to proper sizes for matching, but don't |
5244 | prevent matching a set of insns that only supports sizes other | |
5245 | than those matching the insn suffix. */ | |
5246 | { | |
40fb9820 | 5247 | i386_operand_type mask, allowed; |
d3ce72d0 | 5248 | const insn_template *t; |
9cd96992 | 5249 | |
0dfbf9d7 L |
5250 | operand_type_set (&mask, 0); |
5251 | operand_type_set (&allowed, 0); | |
40fb9820 | 5252 | |
4eed87de AM |
5253 | for (t = current_templates->start; |
5254 | t < current_templates->end; | |
5255 | ++t) | |
bab6aec1 JB |
5256 | { |
5257 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5258 | allowed = operand_type_and (allowed, anyimm); | |
5259 | } | |
9cd96992 JB |
5260 | switch (guess_suffix) |
5261 | { | |
5262 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5263 | mask.bitfield.imm64 = 1; |
5264 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5265 | break; |
5266 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5267 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5268 | break; |
5269 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5270 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5271 | break; |
5272 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5273 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5274 | break; |
5275 | default: | |
9cd96992 JB |
5276 | break; |
5277 | } | |
c6fb90c8 | 5278 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5279 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5280 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5281 | } |
29b0f896 | 5282 | break; |
252b5132 | 5283 | } |
29b0f896 AM |
5284 | } |
5285 | } | |
47926f60 | 5286 | |
29b0f896 AM |
5287 | /* Try to use the smallest displacement type too. */ |
5288 | static void | |
e3bb37b5 | 5289 | optimize_disp (void) |
29b0f896 AM |
5290 | { |
5291 | int op; | |
3e73aa7c | 5292 | |
29b0f896 | 5293 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5294 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5295 | { |
b300c311 | 5296 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5297 | { |
91d6fa6a | 5298 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5299 | |
40fb9820 | 5300 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5301 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5302 | { |
5303 | /* If this operand is at most 16 bits, convert | |
5304 | to a signed 16 bit number and don't use 64bit | |
5305 | displacement. */ | |
91d6fa6a | 5306 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5307 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5308 | } |
a28def75 L |
5309 | #ifdef BFD64 |
5310 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5311 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5312 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5313 | { |
5314 | /* If this operand is at most 32 bits, convert | |
5315 | to a signed 32 bit number and don't use 64bit | |
5316 | displacement. */ | |
91d6fa6a NC |
5317 | op_disp &= (((offsetT) 2 << 31) - 1); |
5318 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5319 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5320 | } |
a28def75 | 5321 | #endif |
91d6fa6a | 5322 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5323 | { |
40fb9820 L |
5324 | i.types[op].bitfield.disp8 = 0; |
5325 | i.types[op].bitfield.disp16 = 0; | |
5326 | i.types[op].bitfield.disp32 = 0; | |
5327 | i.types[op].bitfield.disp32s = 0; | |
5328 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5329 | i.op[op].disps = 0; |
5330 | i.disp_operands--; | |
5331 | } | |
5332 | else if (flag_code == CODE_64BIT) | |
5333 | { | |
91d6fa6a | 5334 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5335 | { |
40fb9820 L |
5336 | i.types[op].bitfield.disp64 = 0; |
5337 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5338 | } |
0e1147d9 | 5339 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5340 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5341 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5342 | } |
40fb9820 L |
5343 | if ((i.types[op].bitfield.disp32 |
5344 | || i.types[op].bitfield.disp32s | |
5345 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5346 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5347 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5348 | } |
67a4f2b7 AO |
5349 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5350 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5351 | { | |
5352 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5353 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5354 | i.types[op].bitfield.disp8 = 0; |
5355 | i.types[op].bitfield.disp16 = 0; | |
5356 | i.types[op].bitfield.disp32 = 0; | |
5357 | i.types[op].bitfield.disp32s = 0; | |
5358 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5359 | } |
5360 | else | |
b300c311 | 5361 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5362 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5363 | } |
29b0f896 AM |
5364 | } |
5365 | ||
4a1b91ea L |
5366 | /* Return 1 if there is a match in broadcast bytes between operand |
5367 | GIVEN and instruction template T. */ | |
5368 | ||
5369 | static INLINE int | |
5370 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5371 | { | |
5372 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5373 | && i.types[given].bitfield.byte) | |
5374 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5375 | && i.types[given].bitfield.word) | |
5376 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5377 | && i.types[given].bitfield.dword) | |
5378 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5379 | && i.types[given].bitfield.qword)); | |
5380 | } | |
5381 | ||
6c30d220 L |
5382 | /* Check if operands are valid for the instruction. */ |
5383 | ||
5384 | static int | |
5385 | check_VecOperands (const insn_template *t) | |
5386 | { | |
43234a1e | 5387 | unsigned int op; |
e2195274 | 5388 | i386_cpu_flags cpu; |
e2195274 JB |
5389 | |
5390 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5391 | any one operand are implicity requiring AVX512VL support if the actual | |
5392 | operand size is YMMword or XMMword. Since this function runs after | |
5393 | template matching, there's no need to check for YMMword/XMMword in | |
5394 | the template. */ | |
5395 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5396 | if (!cpu_flags_all_zero (&cpu) | |
5397 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5398 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5399 | { | |
5400 | for (op = 0; op < t->operands; ++op) | |
5401 | { | |
5402 | if (t->operand_types[op].bitfield.zmmword | |
5403 | && (i.types[op].bitfield.ymmword | |
5404 | || i.types[op].bitfield.xmmword)) | |
5405 | { | |
5406 | i.error = unsupported; | |
5407 | return 1; | |
5408 | } | |
5409 | } | |
5410 | } | |
43234a1e | 5411 | |
6c30d220 L |
5412 | /* Without VSIB byte, we can't have a vector register for index. */ |
5413 | if (!t->opcode_modifier.vecsib | |
5414 | && i.index_reg | |
1b54b8d7 JB |
5415 | && (i.index_reg->reg_type.bitfield.xmmword |
5416 | || i.index_reg->reg_type.bitfield.ymmword | |
5417 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5418 | { |
5419 | i.error = unsupported_vector_index_register; | |
5420 | return 1; | |
5421 | } | |
5422 | ||
ad8ecc81 MZ |
5423 | /* Check if default mask is allowed. */ |
5424 | if (t->opcode_modifier.nodefmask | |
5425 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5426 | { | |
5427 | i.error = no_default_mask; | |
5428 | return 1; | |
5429 | } | |
5430 | ||
7bab8ab5 JB |
5431 | /* For VSIB byte, we need a vector register for index, and all vector |
5432 | registers must be distinct. */ | |
5433 | if (t->opcode_modifier.vecsib) | |
5434 | { | |
5435 | if (!i.index_reg | |
6c30d220 | 5436 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5437 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5438 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5439 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5440 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5441 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5442 | { |
5443 | i.error = invalid_vsib_address; | |
5444 | return 1; | |
5445 | } | |
5446 | ||
43234a1e L |
5447 | gas_assert (i.reg_operands == 2 || i.mask); |
5448 | if (i.reg_operands == 2 && !i.mask) | |
5449 | { | |
3528c362 | 5450 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5451 | gas_assert (i.types[0].bitfield.xmmword |
5452 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5453 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5454 | gas_assert (i.types[2].bitfield.xmmword |
5455 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5456 | if (operand_check == check_none) |
5457 | return 0; | |
5458 | if (register_number (i.op[0].regs) | |
5459 | != register_number (i.index_reg) | |
5460 | && register_number (i.op[2].regs) | |
5461 | != register_number (i.index_reg) | |
5462 | && register_number (i.op[0].regs) | |
5463 | != register_number (i.op[2].regs)) | |
5464 | return 0; | |
5465 | if (operand_check == check_error) | |
5466 | { | |
5467 | i.error = invalid_vector_register_set; | |
5468 | return 1; | |
5469 | } | |
5470 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5471 | } | |
8444f82a MZ |
5472 | else if (i.reg_operands == 1 && i.mask) |
5473 | { | |
3528c362 | 5474 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5475 | && (i.types[1].bitfield.xmmword |
5476 | || i.types[1].bitfield.ymmword | |
5477 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5478 | && (register_number (i.op[1].regs) |
5479 | == register_number (i.index_reg))) | |
5480 | { | |
5481 | if (operand_check == check_error) | |
5482 | { | |
5483 | i.error = invalid_vector_register_set; | |
5484 | return 1; | |
5485 | } | |
5486 | if (operand_check != check_none) | |
5487 | as_warn (_("index and destination registers should be distinct")); | |
5488 | } | |
5489 | } | |
43234a1e | 5490 | } |
7bab8ab5 | 5491 | |
43234a1e L |
5492 | /* Check if broadcast is supported by the instruction and is applied |
5493 | to the memory operand. */ | |
5494 | if (i.broadcast) | |
5495 | { | |
8e6e0792 | 5496 | i386_operand_type type, overlap; |
43234a1e L |
5497 | |
5498 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5499 | and its broadcast bytes match the memory operand. */ |
32546502 | 5500 | op = i.broadcast->operand; |
8e6e0792 | 5501 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5502 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5503 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5504 | && !match_broadcast_size (t, op))) |
43234a1e L |
5505 | { |
5506 | bad_broadcast: | |
5507 | i.error = unsupported_broadcast; | |
5508 | return 1; | |
5509 | } | |
8e6e0792 | 5510 | |
4a1b91ea L |
5511 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5512 | * i.broadcast->type); | |
8e6e0792 | 5513 | operand_type_set (&type, 0); |
4a1b91ea | 5514 | switch (i.broadcast->bytes) |
8e6e0792 | 5515 | { |
4a1b91ea L |
5516 | case 2: |
5517 | type.bitfield.word = 1; | |
5518 | break; | |
5519 | case 4: | |
5520 | type.bitfield.dword = 1; | |
5521 | break; | |
8e6e0792 JB |
5522 | case 8: |
5523 | type.bitfield.qword = 1; | |
5524 | break; | |
5525 | case 16: | |
5526 | type.bitfield.xmmword = 1; | |
5527 | break; | |
5528 | case 32: | |
5529 | type.bitfield.ymmword = 1; | |
5530 | break; | |
5531 | case 64: | |
5532 | type.bitfield.zmmword = 1; | |
5533 | break; | |
5534 | default: | |
5535 | goto bad_broadcast; | |
5536 | } | |
5537 | ||
5538 | overlap = operand_type_and (type, t->operand_types[op]); | |
5539 | if (operand_type_all_zero (&overlap)) | |
5540 | goto bad_broadcast; | |
5541 | ||
5542 | if (t->opcode_modifier.checkregsize) | |
5543 | { | |
5544 | unsigned int j; | |
5545 | ||
e2195274 | 5546 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5547 | for (j = 0; j < i.operands; ++j) |
5548 | { | |
5549 | if (j != op | |
5550 | && !operand_type_register_match(i.types[j], | |
5551 | t->operand_types[j], | |
5552 | type, | |
5553 | t->operand_types[op])) | |
5554 | goto bad_broadcast; | |
5555 | } | |
5556 | } | |
43234a1e L |
5557 | } |
5558 | /* If broadcast is supported in this instruction, we need to check if | |
5559 | operand of one-element size isn't specified without broadcast. */ | |
5560 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5561 | { | |
5562 | /* Find memory operand. */ | |
5563 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5564 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5565 | break; |
5566 | gas_assert (op < i.operands); | |
5567 | /* Check size of the memory operand. */ | |
4a1b91ea | 5568 | if (match_broadcast_size (t, op)) |
43234a1e L |
5569 | { |
5570 | i.error = broadcast_needed; | |
5571 | return 1; | |
5572 | } | |
5573 | } | |
c39e5b26 JB |
5574 | else |
5575 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5576 | |
5577 | /* Check if requested masking is supported. */ | |
ae2387fe | 5578 | if (i.mask) |
43234a1e | 5579 | { |
ae2387fe JB |
5580 | switch (t->opcode_modifier.masking) |
5581 | { | |
5582 | case BOTH_MASKING: | |
5583 | break; | |
5584 | case MERGING_MASKING: | |
5585 | if (i.mask->zeroing) | |
5586 | { | |
5587 | case 0: | |
5588 | i.error = unsupported_masking; | |
5589 | return 1; | |
5590 | } | |
5591 | break; | |
5592 | case DYNAMIC_MASKING: | |
5593 | /* Memory destinations allow only merging masking. */ | |
5594 | if (i.mask->zeroing && i.mem_operands) | |
5595 | { | |
5596 | /* Find memory operand. */ | |
5597 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5598 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5599 | break; |
5600 | gas_assert (op < i.operands); | |
5601 | if (op == i.operands - 1) | |
5602 | { | |
5603 | i.error = unsupported_masking; | |
5604 | return 1; | |
5605 | } | |
5606 | } | |
5607 | break; | |
5608 | default: | |
5609 | abort (); | |
5610 | } | |
43234a1e L |
5611 | } |
5612 | ||
5613 | /* Check if masking is applied to dest operand. */ | |
5614 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5615 | { | |
5616 | i.error = mask_not_on_destination; | |
5617 | return 1; | |
5618 | } | |
5619 | ||
43234a1e L |
5620 | /* Check RC/SAE. */ |
5621 | if (i.rounding) | |
5622 | { | |
a80195f1 JB |
5623 | if (!t->opcode_modifier.sae |
5624 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5625 | { |
5626 | i.error = unsupported_rc_sae; | |
5627 | return 1; | |
5628 | } | |
5629 | /* If the instruction has several immediate operands and one of | |
5630 | them is rounding, the rounding operand should be the last | |
5631 | immediate operand. */ | |
5632 | if (i.imm_operands > 1 | |
5633 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5634 | { |
43234a1e | 5635 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5636 | return 1; |
5637 | } | |
6c30d220 L |
5638 | } |
5639 | ||
43234a1e | 5640 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5641 | if (t->opcode_modifier.disp8memshift |
5642 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5643 | { |
5644 | if (i.broadcast) | |
4a1b91ea | 5645 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5646 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5647 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5648 | else |
5649 | { | |
5650 | const i386_operand_type *type = NULL; | |
5651 | ||
5652 | i.memshift = 0; | |
5653 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5654 | if (i.flags[op] & Operand_Mem) |
7091c612 | 5655 | { |
4174bfff JB |
5656 | if (t->opcode_modifier.evex == EVEXLIG) |
5657 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5658 | else if (t->operand_types[op].bitfield.xmmword | |
5659 | + t->operand_types[op].bitfield.ymmword | |
5660 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5661 | type = &t->operand_types[op]; |
5662 | else if (!i.types[op].bitfield.unspecified) | |
5663 | type = &i.types[op]; | |
5664 | } | |
3528c362 | 5665 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 5666 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
5667 | { |
5668 | if (i.types[op].bitfield.zmmword) | |
5669 | i.memshift = 6; | |
5670 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5671 | i.memshift = 5; | |
5672 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5673 | i.memshift = 4; | |
5674 | } | |
5675 | ||
5676 | if (type) | |
5677 | { | |
5678 | if (type->bitfield.zmmword) | |
5679 | i.memshift = 6; | |
5680 | else if (type->bitfield.ymmword) | |
5681 | i.memshift = 5; | |
5682 | else if (type->bitfield.xmmword) | |
5683 | i.memshift = 4; | |
5684 | } | |
5685 | ||
5686 | /* For the check in fits_in_disp8(). */ | |
5687 | if (i.memshift == 0) | |
5688 | i.memshift = -1; | |
5689 | } | |
43234a1e L |
5690 | |
5691 | for (op = 0; op < i.operands; op++) | |
5692 | if (operand_type_check (i.types[op], disp) | |
5693 | && i.op[op].disps->X_op == O_constant) | |
5694 | { | |
b5014f7a | 5695 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5696 | { |
b5014f7a JB |
5697 | i.types[op].bitfield.disp8 = 1; |
5698 | return 0; | |
43234a1e | 5699 | } |
b5014f7a | 5700 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5701 | } |
5702 | } | |
b5014f7a JB |
5703 | |
5704 | i.memshift = 0; | |
43234a1e | 5705 | |
6c30d220 L |
5706 | return 0; |
5707 | } | |
5708 | ||
43f3e2ee | 5709 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5710 | operand types. */ |
5711 | ||
5712 | static int | |
5713 | VEX_check_operands (const insn_template *t) | |
5714 | { | |
86fa6981 | 5715 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5716 | { |
86fa6981 | 5717 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5718 | if (!is_evex_encoding (t)) |
86fa6981 L |
5719 | { |
5720 | i.error = unsupported; | |
5721 | return 1; | |
5722 | } | |
5723 | return 0; | |
43234a1e L |
5724 | } |
5725 | ||
a683cc34 | 5726 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5727 | { |
5728 | /* This instruction template doesn't have VEX prefix. */ | |
5729 | if (i.vec_encoding != vex_encoding_default) | |
5730 | { | |
5731 | i.error = unsupported; | |
5732 | return 1; | |
5733 | } | |
5734 | return 0; | |
5735 | } | |
a683cc34 | 5736 | |
9d3bf266 JB |
5737 | /* Check the special Imm4 cases; must be the first operand. */ |
5738 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
5739 | { |
5740 | if (i.op[0].imms->X_op != O_constant | |
5741 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5742 | { |
a65babc9 | 5743 | i.error = bad_imm4; |
891edac4 L |
5744 | return 1; |
5745 | } | |
a683cc34 | 5746 | |
9d3bf266 JB |
5747 | /* Turn off Imm<N> so that update_imm won't complain. */ |
5748 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
5749 | } |
5750 | ||
5751 | return 0; | |
5752 | } | |
5753 | ||
d3ce72d0 | 5754 | static const insn_template * |
83b16ac6 | 5755 | match_template (char mnem_suffix) |
29b0f896 AM |
5756 | { |
5757 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5758 | const insn_template *t; |
40fb9820 | 5759 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5760 | i386_operand_type overlap4; |
29b0f896 | 5761 | unsigned int found_reverse_match; |
dc2be329 | 5762 | i386_opcode_modifier suffix_check; |
40fb9820 | 5763 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5764 | int addr_prefix_disp; |
45a4bb20 | 5765 | unsigned int j, size_match, check_register; |
5614d22c | 5766 | enum i386_error specific_error = 0; |
29b0f896 | 5767 | |
c0f3af97 L |
5768 | #if MAX_OPERANDS != 5 |
5769 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5770 | #endif |
5771 | ||
29b0f896 | 5772 | found_reverse_match = 0; |
539e75ad | 5773 | addr_prefix_disp = -1; |
40fb9820 | 5774 | |
dc2be329 | 5775 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 5776 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
5777 | switch (mnem_suffix) |
5778 | { | |
5779 | case BYTE_MNEM_SUFFIX: | |
5780 | suffix_check.no_bsuf = 1; | |
5781 | break; | |
5782 | case WORD_MNEM_SUFFIX: | |
5783 | suffix_check.no_wsuf = 1; | |
5784 | break; | |
5785 | case SHORT_MNEM_SUFFIX: | |
5786 | suffix_check.no_ssuf = 1; | |
5787 | break; | |
5788 | case LONG_MNEM_SUFFIX: | |
5789 | suffix_check.no_lsuf = 1; | |
5790 | break; | |
5791 | case QWORD_MNEM_SUFFIX: | |
5792 | suffix_check.no_qsuf = 1; | |
5793 | break; | |
5794 | default: | |
5795 | /* NB: In Intel syntax, normally we can check for memory operand | |
5796 | size when there is no mnemonic suffix. But jmp and call have | |
5797 | 2 different encodings with Dword memory operand size, one with | |
5798 | No_ldSuf and the other without. i.suffix is set to | |
5799 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
5800 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
5801 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
5802 | } |
5803 | ||
01559ecc L |
5804 | /* Must have right number of operands. */ |
5805 | i.error = number_of_operands_mismatch; | |
5806 | ||
45aa61fe | 5807 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5808 | { |
539e75ad | 5809 | addr_prefix_disp = -1; |
dbbc8b7e | 5810 | found_reverse_match = 0; |
539e75ad | 5811 | |
29b0f896 AM |
5812 | if (i.operands != t->operands) |
5813 | continue; | |
5814 | ||
50aecf8c | 5815 | /* Check processor support. */ |
a65babc9 | 5816 | i.error = unsupported; |
45a4bb20 | 5817 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
5818 | continue; |
5819 | ||
e1d4d893 | 5820 | /* Check AT&T mnemonic. */ |
a65babc9 | 5821 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5822 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5823 | continue; |
5824 | ||
4b5aaf5f | 5825 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 5826 | i.error = unsupported_syntax; |
5c07affc | 5827 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 5828 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
5829 | continue; |
5830 | ||
4b5aaf5f L |
5831 | /* Check Intel64/AMD64 ISA. */ |
5832 | switch (isa64) | |
5833 | { | |
5834 | default: | |
5835 | /* Default: Don't accept Intel64. */ | |
5836 | if (t->opcode_modifier.isa64 == INTEL64) | |
5837 | continue; | |
5838 | break; | |
5839 | case amd64: | |
5840 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
5841 | if (t->opcode_modifier.isa64 >= INTEL64) | |
5842 | continue; | |
5843 | break; | |
5844 | case intel64: | |
5845 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 5846 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
5847 | continue; |
5848 | break; | |
5849 | } | |
5850 | ||
dc2be329 | 5851 | /* Check the suffix. */ |
a65babc9 | 5852 | i.error = invalid_instruction_suffix; |
dc2be329 L |
5853 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
5854 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5855 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5856 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5857 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5858 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 5859 | continue; |
29b0f896 | 5860 | |
3ac21baa JB |
5861 | size_match = operand_size_match (t); |
5862 | if (!size_match) | |
7d5e4556 | 5863 | continue; |
539e75ad | 5864 | |
6f2f06be JB |
5865 | /* This is intentionally not |
5866 | ||
0cfa3eb3 | 5867 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
5868 | |
5869 | as the case of a missing * on the operand is accepted (perhaps with | |
5870 | a warning, issued further down). */ | |
0cfa3eb3 | 5871 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
5872 | { |
5873 | i.error = operand_type_mismatch; | |
5874 | continue; | |
5875 | } | |
5876 | ||
5c07affc L |
5877 | for (j = 0; j < MAX_OPERANDS; j++) |
5878 | operand_types[j] = t->operand_types[j]; | |
5879 | ||
45aa61fe AM |
5880 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5881 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5882 | && flag_code != CODE_64BIT | |
5883 | && (intel_syntax | |
3cd7f3e3 | 5884 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
625cbd7a | 5885 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5886 | && !intel_float_operand (t->name)) |
5887 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5888 | && ((operand_types[0].bitfield.class != RegMMX |
5889 | && operand_types[0].bitfield.class != RegSIMD) | |
5890 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5891 | && operand_types[t->operands > 1].bitfield.class != RegSIMD)) | |
45aa61fe AM |
5892 | && (t->base_opcode != 0x0fc7 |
5893 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5894 | continue; | |
5895 | ||
192dc9c6 JB |
5896 | /* In general, don't allow 32-bit operands on pre-386. */ |
5897 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5898 | && !cpu_arch_flags.bitfield.cpui386 | |
5899 | && (intel_syntax | |
3cd7f3e3 | 5900 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
192dc9c6 JB |
5901 | && !intel_float_operand (t->name)) |
5902 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5903 | && ((operand_types[0].bitfield.class != RegMMX |
5904 | && operand_types[0].bitfield.class != RegSIMD) | |
5905 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5906 | && operand_types[t->operands > 1].bitfield.class | |
5907 | != RegSIMD))) | |
192dc9c6 JB |
5908 | continue; |
5909 | ||
29b0f896 | 5910 | /* Do not verify operands when there are none. */ |
50aecf8c | 5911 | else |
29b0f896 | 5912 | { |
c6fb90c8 | 5913 | if (!t->operands) |
2dbab7d5 L |
5914 | /* We've found a match; break out of loop. */ |
5915 | break; | |
29b0f896 | 5916 | } |
252b5132 | 5917 | |
48bcea9f JB |
5918 | if (!t->opcode_modifier.jump |
5919 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
5920 | { | |
5921 | /* There should be only one Disp operand. */ | |
5922 | for (j = 0; j < MAX_OPERANDS; j++) | |
5923 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 5924 | break; |
48bcea9f JB |
5925 | if (j < MAX_OPERANDS) |
5926 | { | |
5927 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); | |
5928 | ||
5929 | addr_prefix_disp = j; | |
5930 | ||
5931 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
5932 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
5933 | switch (flag_code) | |
40fb9820 | 5934 | { |
48bcea9f JB |
5935 | case CODE_16BIT: |
5936 | override = !override; | |
5937 | /* Fall through. */ | |
5938 | case CODE_32BIT: | |
5939 | if (operand_types[j].bitfield.disp32 | |
5940 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 5941 | { |
48bcea9f JB |
5942 | operand_types[j].bitfield.disp16 = override; |
5943 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 5944 | } |
48bcea9f JB |
5945 | operand_types[j].bitfield.disp32s = 0; |
5946 | operand_types[j].bitfield.disp64 = 0; | |
5947 | break; | |
5948 | ||
5949 | case CODE_64BIT: | |
5950 | if (operand_types[j].bitfield.disp32s | |
5951 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 5952 | { |
48bcea9f JB |
5953 | operand_types[j].bitfield.disp64 &= !override; |
5954 | operand_types[j].bitfield.disp32s &= !override; | |
5955 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 5956 | } |
48bcea9f JB |
5957 | operand_types[j].bitfield.disp16 = 0; |
5958 | break; | |
40fb9820 | 5959 | } |
539e75ad | 5960 | } |
48bcea9f | 5961 | } |
539e75ad | 5962 | |
02a86693 L |
5963 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5964 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5965 | continue; | |
5966 | ||
56ffb741 | 5967 | /* We check register size if needed. */ |
e2195274 JB |
5968 | if (t->opcode_modifier.checkregsize) |
5969 | { | |
5970 | check_register = (1 << t->operands) - 1; | |
5971 | if (i.broadcast) | |
5972 | check_register &= ~(1 << i.broadcast->operand); | |
5973 | } | |
5974 | else | |
5975 | check_register = 0; | |
5976 | ||
c6fb90c8 | 5977 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5978 | switch (t->operands) |
5979 | { | |
5980 | case 1: | |
40fb9820 | 5981 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5982 | continue; |
5983 | break; | |
5984 | case 2: | |
33eaf5de | 5985 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5986 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5987 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5988 | zero-extend %eax to %rax. */ | |
5989 | if (flag_code == CODE_64BIT | |
5990 | && t->base_opcode == 0x90 | |
75e5731b JB |
5991 | && i.types[0].bitfield.instance == Accum |
5992 | && i.types[0].bitfield.dword | |
5993 | && i.types[1].bitfield.instance == Accum | |
5994 | && i.types[1].bitfield.dword) | |
8b38ad71 | 5995 | continue; |
1212781b JB |
5996 | /* xrelease mov %eax, <disp> is another special case. It must not |
5997 | match the accumulator-only encoding of mov. */ | |
5998 | if (flag_code != CODE_64BIT | |
5999 | && i.hle_prefix | |
6000 | && t->base_opcode == 0xa0 | |
75e5731b | 6001 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 6002 | && (i.flags[1] & Operand_Mem)) |
1212781b | 6003 | continue; |
f5eb1d70 JB |
6004 | /* Fall through. */ |
6005 | ||
6006 | case 3: | |
3ac21baa JB |
6007 | if (!(size_match & MATCH_STRAIGHT)) |
6008 | goto check_reverse; | |
64c49ab3 JB |
6009 | /* Reverse direction of operands if swapping is possible in the first |
6010 | place (operands need to be symmetric) and | |
6011 | - the load form is requested, and the template is a store form, | |
6012 | - the store form is requested, and the template is a load form, | |
6013 | - the non-default (swapped) form is requested. */ | |
6014 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6015 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6016 | && !operand_type_all_zero (&overlap1)) |
6017 | switch (i.dir_encoding) | |
6018 | { | |
6019 | case dir_encoding_load: | |
6020 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6021 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6022 | goto check_reverse; |
6023 | break; | |
6024 | ||
6025 | case dir_encoding_store: | |
6026 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6027 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6028 | goto check_reverse; |
6029 | break; | |
6030 | ||
6031 | case dir_encoding_swap: | |
6032 | goto check_reverse; | |
6033 | ||
6034 | case dir_encoding_default: | |
6035 | break; | |
6036 | } | |
86fa6981 | 6037 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6038 | if ((i.dir_encoding == dir_encoding_store |
6039 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6040 | && i.mem_operands == 0 |
6041 | && t->opcode_modifier.load) | |
fa99fab2 | 6042 | continue; |
1a0670f3 | 6043 | /* Fall through. */ |
f48ff2ae | 6044 | case 4: |
c0f3af97 | 6045 | case 5: |
c6fb90c8 | 6046 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6047 | if (!operand_type_match (overlap0, i.types[0]) |
6048 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6049 | || ((check_register & 3) == 3 |
dc821c5f | 6050 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6051 | operand_types[0], |
dc821c5f | 6052 | i.types[1], |
40fb9820 | 6053 | operand_types[1]))) |
29b0f896 AM |
6054 | { |
6055 | /* Check if other direction is valid ... */ | |
38e314eb | 6056 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6057 | continue; |
6058 | ||
dc1e8a47 | 6059 | check_reverse: |
3ac21baa JB |
6060 | if (!(size_match & MATCH_REVERSE)) |
6061 | continue; | |
29b0f896 | 6062 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6063 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6064 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6065 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6066 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6067 | || (check_register |
dc821c5f | 6068 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6069 | operand_types[i.operands - 1], |
6070 | i.types[i.operands - 1], | |
45664ddb | 6071 | operand_types[0]))) |
29b0f896 AM |
6072 | { |
6073 | /* Does not match either direction. */ | |
6074 | continue; | |
6075 | } | |
38e314eb | 6076 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6077 | we've found. */ |
38e314eb JB |
6078 | if (!t->opcode_modifier.d) |
6079 | found_reverse_match = 0; | |
6080 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6081 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6082 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6083 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6084 | || operand_types[0].bitfield.class == RegMMX |
6085 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6086 | || is_any_vex_encoding(t)) |
6087 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6088 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6089 | else |
38e314eb | 6090 | found_reverse_match = Opcode_D; |
40fb9820 | 6091 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6092 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6093 | } |
f48ff2ae | 6094 | else |
29b0f896 | 6095 | { |
f48ff2ae | 6096 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6097 | switch (t->operands) |
6098 | { | |
c0f3af97 L |
6099 | case 5: |
6100 | overlap4 = operand_type_and (i.types[4], | |
6101 | operand_types[4]); | |
1a0670f3 | 6102 | /* Fall through. */ |
d1cbb4db | 6103 | case 4: |
c6fb90c8 L |
6104 | overlap3 = operand_type_and (i.types[3], |
6105 | operand_types[3]); | |
1a0670f3 | 6106 | /* Fall through. */ |
d1cbb4db | 6107 | case 3: |
c6fb90c8 L |
6108 | overlap2 = operand_type_and (i.types[2], |
6109 | operand_types[2]); | |
d1cbb4db L |
6110 | break; |
6111 | } | |
29b0f896 | 6112 | |
f48ff2ae L |
6113 | switch (t->operands) |
6114 | { | |
c0f3af97 L |
6115 | case 5: |
6116 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6117 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6118 | operand_types[3], |
c0f3af97 L |
6119 | i.types[4], |
6120 | operand_types[4])) | |
6121 | continue; | |
1a0670f3 | 6122 | /* Fall through. */ |
f48ff2ae | 6123 | case 4: |
40fb9820 | 6124 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6125 | || ((check_register & 0xa) == 0xa |
6126 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6127 | operand_types[1], |
6128 | i.types[3], | |
e2195274 JB |
6129 | operand_types[3])) |
6130 | || ((check_register & 0xc) == 0xc | |
6131 | && !operand_type_register_match (i.types[2], | |
6132 | operand_types[2], | |
6133 | i.types[3], | |
6134 | operand_types[3]))) | |
f48ff2ae | 6135 | continue; |
1a0670f3 | 6136 | /* Fall through. */ |
f48ff2ae L |
6137 | case 3: |
6138 | /* Here we make use of the fact that there are no | |
23e42951 | 6139 | reverse match 3 operand instructions. */ |
40fb9820 | 6140 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6141 | || ((check_register & 5) == 5 |
6142 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6143 | operand_types[0], |
6144 | i.types[2], | |
e2195274 JB |
6145 | operand_types[2])) |
6146 | || ((check_register & 6) == 6 | |
6147 | && !operand_type_register_match (i.types[1], | |
6148 | operand_types[1], | |
6149 | i.types[2], | |
6150 | operand_types[2]))) | |
f48ff2ae L |
6151 | continue; |
6152 | break; | |
6153 | } | |
29b0f896 | 6154 | } |
f48ff2ae | 6155 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6156 | slip through to break. */ |
6157 | } | |
c0f3af97 | 6158 | |
5614d22c JB |
6159 | /* Check if vector and VEX operands are valid. */ |
6160 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6161 | { | |
6162 | specific_error = i.error; | |
6163 | continue; | |
6164 | } | |
a683cc34 | 6165 | |
29b0f896 AM |
6166 | /* We've found a match; break out of loop. */ |
6167 | break; | |
6168 | } | |
6169 | ||
6170 | if (t == current_templates->end) | |
6171 | { | |
6172 | /* We found no match. */ | |
a65babc9 | 6173 | const char *err_msg; |
5614d22c | 6174 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6175 | { |
6176 | default: | |
6177 | abort (); | |
86e026a4 | 6178 | case operand_size_mismatch: |
a65babc9 L |
6179 | err_msg = _("operand size mismatch"); |
6180 | break; | |
6181 | case operand_type_mismatch: | |
6182 | err_msg = _("operand type mismatch"); | |
6183 | break; | |
6184 | case register_type_mismatch: | |
6185 | err_msg = _("register type mismatch"); | |
6186 | break; | |
6187 | case number_of_operands_mismatch: | |
6188 | err_msg = _("number of operands mismatch"); | |
6189 | break; | |
6190 | case invalid_instruction_suffix: | |
6191 | err_msg = _("invalid instruction suffix"); | |
6192 | break; | |
6193 | case bad_imm4: | |
4a2608e3 | 6194 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6195 | break; |
a65babc9 L |
6196 | case unsupported_with_intel_mnemonic: |
6197 | err_msg = _("unsupported with Intel mnemonic"); | |
6198 | break; | |
6199 | case unsupported_syntax: | |
6200 | err_msg = _("unsupported syntax"); | |
6201 | break; | |
6202 | case unsupported: | |
35262a23 | 6203 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6204 | current_templates->start->name); |
6205 | return NULL; | |
6c30d220 L |
6206 | case invalid_vsib_address: |
6207 | err_msg = _("invalid VSIB address"); | |
6208 | break; | |
7bab8ab5 JB |
6209 | case invalid_vector_register_set: |
6210 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6211 | break; | |
6c30d220 L |
6212 | case unsupported_vector_index_register: |
6213 | err_msg = _("unsupported vector index register"); | |
6214 | break; | |
43234a1e L |
6215 | case unsupported_broadcast: |
6216 | err_msg = _("unsupported broadcast"); | |
6217 | break; | |
43234a1e L |
6218 | case broadcast_needed: |
6219 | err_msg = _("broadcast is needed for operand of such type"); | |
6220 | break; | |
6221 | case unsupported_masking: | |
6222 | err_msg = _("unsupported masking"); | |
6223 | break; | |
6224 | case mask_not_on_destination: | |
6225 | err_msg = _("mask not on destination operand"); | |
6226 | break; | |
6227 | case no_default_mask: | |
6228 | err_msg = _("default mask isn't allowed"); | |
6229 | break; | |
6230 | case unsupported_rc_sae: | |
6231 | err_msg = _("unsupported static rounding/sae"); | |
6232 | break; | |
6233 | case rc_sae_operand_not_last_imm: | |
6234 | if (intel_syntax) | |
6235 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6236 | else | |
6237 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6238 | break; | |
6239 | case invalid_register_operand: | |
6240 | err_msg = _("invalid register operand"); | |
6241 | break; | |
a65babc9 L |
6242 | } |
6243 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6244 | current_templates->start->name); |
fa99fab2 | 6245 | return NULL; |
29b0f896 | 6246 | } |
252b5132 | 6247 | |
29b0f896 AM |
6248 | if (!quiet_warnings) |
6249 | { | |
6250 | if (!intel_syntax | |
0cfa3eb3 | 6251 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6252 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6253 | |
40fb9820 | 6254 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 6255 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
6256 | { |
6257 | /* Warn them that a data or address size prefix doesn't | |
6258 | affect assembly of the next line of code. */ | |
6259 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6260 | } | |
6261 | } | |
6262 | ||
6263 | /* Copy the template we found. */ | |
6264 | i.tm = *t; | |
539e75ad L |
6265 | |
6266 | if (addr_prefix_disp != -1) | |
6267 | i.tm.operand_types[addr_prefix_disp] | |
6268 | = operand_types[addr_prefix_disp]; | |
6269 | ||
29b0f896 AM |
6270 | if (found_reverse_match) |
6271 | { | |
dfd69174 JB |
6272 | /* If we found a reverse match we must alter the opcode direction |
6273 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6274 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6275 | |
6276 | i.tm.base_opcode ^= found_reverse_match; | |
6277 | ||
f5eb1d70 JB |
6278 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6279 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6280 | |
6281 | /* Certain SIMD insns have their load forms specified in the opcode | |
6282 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6283 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6284 | i.tm.opcode_modifier.regmem | |
6285 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6286 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6287 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6288 | } |
6289 | ||
fa99fab2 | 6290 | return t; |
29b0f896 AM |
6291 | } |
6292 | ||
6293 | static int | |
e3bb37b5 | 6294 | check_string (void) |
29b0f896 | 6295 | { |
51c8edf6 JB |
6296 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6297 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6298 | |
51c8edf6 | 6299 | if (i.seg[op] != NULL && i.seg[op] != &es) |
29b0f896 | 6300 | { |
51c8edf6 JB |
6301 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6302 | i.tm.name, | |
6303 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6304 | register_prefix); | |
6305 | return 0; | |
29b0f896 | 6306 | } |
51c8edf6 JB |
6307 | |
6308 | /* There's only ever one segment override allowed per instruction. | |
6309 | This instruction possibly has a legal segment override on the | |
6310 | second operand, so copy the segment to where non-string | |
6311 | instructions store it, allowing common code. */ | |
6312 | i.seg[op] = i.seg[1]; | |
6313 | ||
29b0f896 AM |
6314 | return 1; |
6315 | } | |
6316 | ||
6317 | static int | |
543613e9 | 6318 | process_suffix (void) |
29b0f896 AM |
6319 | { |
6320 | /* If matched instruction specifies an explicit instruction mnemonic | |
6321 | suffix, use it. */ | |
673fe0f0 | 6322 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6323 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6324 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6325 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6326 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6327 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 6328 | else if (i.reg_operands |
c8f8eebc JB |
6329 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
6330 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 6331 | { |
65fca059 JB |
6332 | unsigned int numop = i.operands; |
6333 | ||
6334 | /* movsx/movzx want only their source operand considered here, for the | |
6335 | ambiguity checking below. The suffix will be replaced afterwards | |
6336 | to represent the destination (register). */ | |
6337 | if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w) | |
6338 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6339 | --i.operands; | |
6340 | ||
29b0f896 | 6341 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 6342 | based on GPR operands. */ |
29b0f896 AM |
6343 | if (!i.suffix) |
6344 | { | |
6345 | /* We take i.suffix from the last register operand specified, | |
6346 | Destination register type is more significant than source | |
381d071f L |
6347 | register type. crc32 in SSE4.2 prefers source register |
6348 | type. */ | |
1a035124 | 6349 | unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1; |
20592a94 | 6350 | |
1a035124 JB |
6351 | while (op--) |
6352 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
6353 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
6354 | { | |
6355 | if (i.types[op].bitfield.class != Reg) | |
6356 | continue; | |
6357 | if (i.types[op].bitfield.byte) | |
6358 | i.suffix = BYTE_MNEM_SUFFIX; | |
6359 | else if (i.types[op].bitfield.word) | |
6360 | i.suffix = WORD_MNEM_SUFFIX; | |
6361 | else if (i.types[op].bitfield.dword) | |
6362 | i.suffix = LONG_MNEM_SUFFIX; | |
6363 | else if (i.types[op].bitfield.qword) | |
6364 | i.suffix = QWORD_MNEM_SUFFIX; | |
6365 | else | |
6366 | continue; | |
6367 | break; | |
6368 | } | |
65fca059 JB |
6369 | |
6370 | /* As an exception, movsx/movzx silently default to a byte source | |
6371 | in AT&T mode. */ | |
6372 | if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w | |
6373 | && !i.suffix && !intel_syntax) | |
6374 | i.suffix = BYTE_MNEM_SUFFIX; | |
29b0f896 AM |
6375 | } |
6376 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6377 | { | |
2eb952a4 | 6378 | if (intel_syntax |
3cd7f3e3 | 6379 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6380 | && i.tm.opcode_modifier.no_bsuf) |
6381 | i.suffix = 0; | |
6382 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6383 | return 0; |
6384 | } | |
6385 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6386 | { | |
2eb952a4 | 6387 | if (intel_syntax |
3cd7f3e3 | 6388 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6389 | && i.tm.opcode_modifier.no_lsuf |
6390 | && !i.tm.opcode_modifier.todword | |
6391 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6392 | i.suffix = 0; |
6393 | else if (!check_long_reg ()) | |
29b0f896 AM |
6394 | return 0; |
6395 | } | |
6396 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6397 | { | |
955e1e6a | 6398 | if (intel_syntax |
3cd7f3e3 | 6399 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6400 | && i.tm.opcode_modifier.no_qsuf |
6401 | && !i.tm.opcode_modifier.todword | |
6402 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6403 | i.suffix = 0; |
6404 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6405 | return 0; |
6406 | } | |
6407 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6408 | { | |
2eb952a4 | 6409 | if (intel_syntax |
3cd7f3e3 | 6410 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6411 | && i.tm.opcode_modifier.no_wsuf) |
6412 | i.suffix = 0; | |
6413 | else if (!check_word_reg ()) | |
29b0f896 AM |
6414 | return 0; |
6415 | } | |
3cd7f3e3 L |
6416 | else if (intel_syntax |
6417 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
6418 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6419 | ; | |
6420 | else | |
6421 | abort (); | |
65fca059 JB |
6422 | |
6423 | /* Undo the movsx/movzx change done above. */ | |
6424 | i.operands = numop; | |
29b0f896 | 6425 | } |
3cd7f3e3 L |
6426 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
6427 | && !i.suffix) | |
29b0f896 | 6428 | { |
13e600d0 JB |
6429 | i.suffix = stackop_size; |
6430 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
6431 | { |
6432 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6433 | .code16gcc directive to support 16-bit mode with | |
6434 | 32-bit address. For IRET without a suffix, generate | |
6435 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6436 | handler. */ | |
13e600d0 JB |
6437 | if (i.tm.base_opcode == 0xcf) |
6438 | { | |
6439 | i.suffix = WORD_MNEM_SUFFIX; | |
6440 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6441 | } | |
6442 | /* Warn about changed behavior for segment register push/pop. */ | |
6443 | else if ((i.tm.base_opcode | 1) == 0x07) | |
6444 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
6445 | i.tm.name); | |
06f74c5c | 6446 | } |
29b0f896 | 6447 | } |
c006a730 | 6448 | else if (!i.suffix |
0cfa3eb3 JB |
6449 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
6450 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
6451 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
64e74474 AM |
6452 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6453 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6454 | { |
6455 | switch (flag_code) | |
6456 | { | |
6457 | case CODE_64BIT: | |
40fb9820 | 6458 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6459 | { |
6460 | i.suffix = QWORD_MNEM_SUFFIX; | |
6461 | break; | |
6462 | } | |
1a0670f3 | 6463 | /* Fall through. */ |
9306ca4a | 6464 | case CODE_32BIT: |
40fb9820 | 6465 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6466 | i.suffix = LONG_MNEM_SUFFIX; |
6467 | break; | |
6468 | case CODE_16BIT: | |
40fb9820 | 6469 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6470 | i.suffix = WORD_MNEM_SUFFIX; |
6471 | break; | |
6472 | } | |
6473 | } | |
252b5132 | 6474 | |
c006a730 | 6475 | if (!i.suffix |
3cd7f3e3 | 6476 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
6477 | /* Also cover lret/retf/iret in 64-bit mode. */ |
6478 | || (flag_code == CODE_64BIT | |
6479 | && !i.tm.opcode_modifier.no_lsuf | |
6480 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 6481 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
62b3f548 JB |
6482 | /* Accept FLDENV et al without suffix. */ |
6483 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 6484 | { |
6c0946d0 | 6485 | unsigned int suffixes, evex = 0; |
c006a730 JB |
6486 | |
6487 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
6488 | if (!i.tm.opcode_modifier.no_wsuf) | |
6489 | suffixes |= 1 << 1; | |
6490 | if (!i.tm.opcode_modifier.no_lsuf) | |
6491 | suffixes |= 1 << 2; | |
6492 | if (!i.tm.opcode_modifier.no_ldsuf) | |
6493 | suffixes |= 1 << 3; | |
6494 | if (!i.tm.opcode_modifier.no_ssuf) | |
6495 | suffixes |= 1 << 4; | |
6496 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
6497 | suffixes |= 1 << 5; | |
6498 | ||
6c0946d0 JB |
6499 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
6500 | also suitable for AT&T syntax mode, it was requested that this be | |
6501 | restricted to just Intel syntax. */ | |
b9915cbc | 6502 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast) |
6c0946d0 | 6503 | { |
b9915cbc | 6504 | unsigned int op; |
6c0946d0 | 6505 | |
b9915cbc | 6506 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 6507 | { |
b9915cbc JB |
6508 | if (is_evex_encoding (&i.tm) |
6509 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 6510 | { |
b9915cbc JB |
6511 | if (i.tm.operand_types[op].bitfield.ymmword) |
6512 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
6513 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6514 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
6515 | if (!i.tm.opcode_modifier.evex | |
6516 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
6517 | i.tm.opcode_modifier.evex = EVEX512; | |
6518 | } | |
6c0946d0 | 6519 | |
b9915cbc JB |
6520 | if (i.tm.operand_types[op].bitfield.xmmword |
6521 | + i.tm.operand_types[op].bitfield.ymmword | |
6522 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
6523 | continue; | |
6c0946d0 | 6524 | |
b9915cbc JB |
6525 | /* Any properly sized operand disambiguates the insn. */ |
6526 | if (i.types[op].bitfield.xmmword | |
6527 | || i.types[op].bitfield.ymmword | |
6528 | || i.types[op].bitfield.zmmword) | |
6529 | { | |
6530 | suffixes &= ~(7 << 6); | |
6531 | evex = 0; | |
6532 | break; | |
6533 | } | |
6c0946d0 | 6534 | |
b9915cbc JB |
6535 | if ((i.flags[op] & Operand_Mem) |
6536 | && i.tm.operand_types[op].bitfield.unspecified) | |
6537 | { | |
6538 | if (i.tm.operand_types[op].bitfield.xmmword) | |
6539 | suffixes |= 1 << 6; | |
6540 | if (i.tm.operand_types[op].bitfield.ymmword) | |
6541 | suffixes |= 1 << 7; | |
6542 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6543 | suffixes |= 1 << 8; | |
6544 | if (is_evex_encoding (&i.tm)) | |
6545 | evex = EVEX512; | |
6c0946d0 JB |
6546 | } |
6547 | } | |
6548 | } | |
6549 | ||
6550 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 6551 | if (suffixes & (suffixes - 1)) |
9306ca4a | 6552 | { |
873494c8 | 6553 | if (intel_syntax |
3cd7f3e3 | 6554 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 6555 | || operand_check == check_error)) |
9306ca4a | 6556 | { |
c006a730 | 6557 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
6558 | return 0; |
6559 | } | |
c006a730 | 6560 | if (operand_check == check_error) |
9306ca4a | 6561 | { |
c006a730 JB |
6562 | as_bad (_("no instruction mnemonic suffix given and " |
6563 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
6564 | return 0; |
6565 | } | |
c006a730 | 6566 | if (operand_check == check_warning) |
873494c8 JB |
6567 | as_warn (_("%s; using default for `%s'"), |
6568 | intel_syntax | |
6569 | ? _("ambiguous operand size") | |
6570 | : _("no instruction mnemonic suffix given and " | |
6571 | "no register operands"), | |
6572 | i.tm.name); | |
c006a730 JB |
6573 | |
6574 | if (i.tm.opcode_modifier.floatmf) | |
6575 | i.suffix = SHORT_MNEM_SUFFIX; | |
65fca059 JB |
6576 | else if ((i.tm.base_opcode | 8) == 0xfbe |
6577 | || (i.tm.base_opcode == 0x63 | |
6578 | && i.tm.cpu_flags.bitfield.cpu64)) | |
6579 | /* handled below */; | |
6c0946d0 JB |
6580 | else if (evex) |
6581 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
6582 | else if (flag_code == CODE_16BIT) |
6583 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 6584 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 6585 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
6586 | else |
6587 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 6588 | } |
29b0f896 | 6589 | } |
252b5132 | 6590 | |
65fca059 JB |
6591 | if ((i.tm.base_opcode | 8) == 0xfbe |
6592 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6593 | { | |
6594 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
6595 | In AT&T syntax, if there is no suffix (warned about above), the default | |
6596 | will be byte extension. */ | |
6597 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
6598 | i.tm.base_opcode |= 1; | |
6599 | ||
6600 | /* For further processing, the suffix should represent the destination | |
6601 | (register). This is already the case when one was used with | |
6602 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
6603 | no suffix to begin with. */ | |
6604 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
6605 | { | |
6606 | if (i.types[1].bitfield.word) | |
6607 | i.suffix = WORD_MNEM_SUFFIX; | |
6608 | else if (i.types[1].bitfield.qword) | |
6609 | i.suffix = QWORD_MNEM_SUFFIX; | |
6610 | else | |
6611 | i.suffix = LONG_MNEM_SUFFIX; | |
6612 | ||
6613 | i.tm.opcode_modifier.w = 0; | |
6614 | } | |
6615 | } | |
6616 | ||
50128d0c JB |
6617 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
6618 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
6619 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
6620 | ||
d2224064 JB |
6621 | /* Change the opcode based on the operand size given by i.suffix. */ |
6622 | switch (i.suffix) | |
29b0f896 | 6623 | { |
d2224064 JB |
6624 | /* Size floating point instruction. */ |
6625 | case LONG_MNEM_SUFFIX: | |
6626 | if (i.tm.opcode_modifier.floatmf) | |
6627 | { | |
6628 | i.tm.base_opcode ^= 4; | |
6629 | break; | |
6630 | } | |
6631 | /* fall through */ | |
6632 | case WORD_MNEM_SUFFIX: | |
6633 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6634 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6635 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6636 | { |
50128d0c | 6637 | if (i.short_form) |
29b0f896 AM |
6638 | i.tm.base_opcode |= 8; |
6639 | else | |
6640 | i.tm.base_opcode |= 1; | |
6641 | } | |
d2224064 JB |
6642 | /* fall through */ |
6643 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6644 | /* Now select between word & dword operations via the operand |
6645 | size prefix, except for instructions that will ignore this | |
6646 | prefix anyway. */ | |
c8f8eebc | 6647 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 6648 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
6649 | && !i.tm.opcode_modifier.floatmf |
6650 | && !is_any_vex_encoding (&i.tm) | |
6651 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
6652 | || (flag_code == CODE_64BIT | |
6653 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
6654 | { |
6655 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6656 | |
0cfa3eb3 | 6657 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 6658 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6659 | |
29b0f896 AM |
6660 | if (!add_prefix (prefix)) |
6661 | return 0; | |
24eab124 | 6662 | } |
252b5132 | 6663 | |
29b0f896 AM |
6664 | /* Set mode64 for an operand. */ |
6665 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6666 | && flag_code == CODE_64BIT |
d2224064 | 6667 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6668 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6669 | need rex64. */ |
6670 | && ! (i.operands == 2 | |
6671 | && i.tm.base_opcode == 0x90 | |
6672 | && i.tm.extension_opcode == None | |
75e5731b JB |
6673 | && i.types[0].bitfield.instance == Accum |
6674 | && i.types[0].bitfield.qword | |
6675 | && i.types[1].bitfield.instance == Accum | |
6676 | && i.types[1].bitfield.qword)) | |
d2224064 | 6677 | i.rex |= REX_W; |
3e73aa7c | 6678 | |
d2224064 | 6679 | break; |
29b0f896 | 6680 | } |
7ecd2f8b | 6681 | |
c8f8eebc | 6682 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 6683 | { |
c8f8eebc JB |
6684 | gas_assert (!i.suffix); |
6685 | gas_assert (i.reg_operands); | |
c0a30a9f | 6686 | |
c8f8eebc JB |
6687 | if (i.tm.operand_types[0].bitfield.instance == Accum |
6688 | || i.operands == 1) | |
6689 | { | |
6690 | /* The address size override prefix changes the size of the | |
6691 | first operand. */ | |
6692 | if (flag_code == CODE_64BIT | |
6693 | && i.op[0].regs->reg_type.bitfield.word) | |
6694 | { | |
6695 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
6696 | i.tm.name); | |
6697 | return 0; | |
6698 | } | |
6699 | ||
6700 | if ((flag_code == CODE_32BIT | |
6701 | ? i.op[0].regs->reg_type.bitfield.word | |
6702 | : i.op[0].regs->reg_type.bitfield.dword) | |
6703 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
6704 | return 0; | |
6705 | } | |
c0a30a9f L |
6706 | else |
6707 | { | |
c8f8eebc JB |
6708 | /* Check invalid register operand when the address size override |
6709 | prefix changes the size of register operands. */ | |
6710 | unsigned int op; | |
6711 | enum { need_word, need_dword, need_qword } need; | |
6712 | ||
6713 | if (flag_code == CODE_32BIT) | |
6714 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6715 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
6716 | need = need_dword; |
6717 | else | |
6718 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 6719 | |
c8f8eebc JB |
6720 | for (op = 0; op < i.operands; op++) |
6721 | { | |
6722 | if (i.types[op].bitfield.class != Reg) | |
6723 | continue; | |
6724 | ||
6725 | switch (need) | |
6726 | { | |
6727 | case need_word: | |
6728 | if (i.op[op].regs->reg_type.bitfield.word) | |
6729 | continue; | |
6730 | break; | |
6731 | case need_dword: | |
6732 | if (i.op[op].regs->reg_type.bitfield.dword) | |
6733 | continue; | |
6734 | break; | |
6735 | case need_qword: | |
6736 | if (i.op[op].regs->reg_type.bitfield.qword) | |
6737 | continue; | |
6738 | break; | |
6739 | } | |
6740 | ||
6741 | as_bad (_("invalid register operand size for `%s'"), | |
6742 | i.tm.name); | |
6743 | return 0; | |
6744 | } | |
6745 | } | |
c0a30a9f L |
6746 | } |
6747 | ||
29b0f896 AM |
6748 | return 1; |
6749 | } | |
3e73aa7c | 6750 | |
29b0f896 | 6751 | static int |
543613e9 | 6752 | check_byte_reg (void) |
29b0f896 AM |
6753 | { |
6754 | int op; | |
543613e9 | 6755 | |
29b0f896 AM |
6756 | for (op = i.operands; --op >= 0;) |
6757 | { | |
dc821c5f | 6758 | /* Skip non-register operands. */ |
bab6aec1 | 6759 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
6760 | continue; |
6761 | ||
29b0f896 AM |
6762 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6763 | 32 bit version of an eight bit register, we will just use the | |
6764 | low portion, and that's OK too. */ | |
dc821c5f | 6765 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6766 | continue; |
6767 | ||
5a819eb9 | 6768 | /* I/O port address operands are OK too. */ |
75e5731b JB |
6769 | if (i.tm.operand_types[op].bitfield.instance == RegD |
6770 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
6771 | continue; |
6772 | ||
9706160a JB |
6773 | /* crc32 only wants its source operand checked here. */ |
6774 | if (i.tm.base_opcode == 0xf20f38f0 && op) | |
9344ff29 L |
6775 | continue; |
6776 | ||
29b0f896 | 6777 | /* Any other register is bad. */ |
bab6aec1 | 6778 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
6779 | || i.types[op].bitfield.class == RegMMX |
6780 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 6781 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
6782 | || i.types[op].bitfield.class == RegCR |
6783 | || i.types[op].bitfield.class == RegDR | |
6784 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 6785 | { |
a540244d L |
6786 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6787 | register_prefix, | |
29b0f896 AM |
6788 | i.op[op].regs->reg_name, |
6789 | i.tm.name, | |
6790 | i.suffix); | |
6791 | return 0; | |
6792 | } | |
6793 | } | |
6794 | return 1; | |
6795 | } | |
6796 | ||
6797 | static int | |
e3bb37b5 | 6798 | check_long_reg (void) |
29b0f896 AM |
6799 | { |
6800 | int op; | |
6801 | ||
6802 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6803 | /* Skip non-register operands. */ |
bab6aec1 | 6804 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6805 | continue; |
29b0f896 AM |
6806 | /* Reject eight bit registers, except where the template requires |
6807 | them. (eg. movzb) */ | |
dc821c5f | 6808 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6809 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6810 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6811 | && (i.tm.operand_types[op].bitfield.word |
6812 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6813 | { |
a540244d L |
6814 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6815 | register_prefix, | |
29b0f896 AM |
6816 | i.op[op].regs->reg_name, |
6817 | i.tm.name, | |
6818 | i.suffix); | |
6819 | return 0; | |
6820 | } | |
be4c5e58 L |
6821 | /* Error if the e prefix on a general reg is missing. */ |
6822 | else if (i.types[op].bitfield.word | |
bab6aec1 | 6823 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6824 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6825 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 6826 | { |
be4c5e58 L |
6827 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6828 | register_prefix, i.op[op].regs->reg_name, | |
6829 | i.suffix); | |
6830 | return 0; | |
252b5132 | 6831 | } |
e4630f71 | 6832 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 6833 | else if (i.types[op].bitfield.qword |
bab6aec1 | 6834 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6835 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6836 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 6837 | { |
34828aad | 6838 | if (intel_syntax |
65fca059 | 6839 | && i.tm.opcode_modifier.toqword |
3528c362 | 6840 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6841 | { |
ca61edf2 | 6842 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6843 | i.suffix = QWORD_MNEM_SUFFIX; |
6844 | } | |
6845 | else | |
6846 | { | |
2b5d6a91 | 6847 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6848 | register_prefix, i.op[op].regs->reg_name, |
6849 | i.suffix); | |
6850 | return 0; | |
6851 | } | |
29b0f896 AM |
6852 | } |
6853 | return 1; | |
6854 | } | |
252b5132 | 6855 | |
29b0f896 | 6856 | static int |
e3bb37b5 | 6857 | check_qword_reg (void) |
29b0f896 AM |
6858 | { |
6859 | int op; | |
252b5132 | 6860 | |
29b0f896 | 6861 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 6862 | /* Skip non-register operands. */ |
bab6aec1 | 6863 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6864 | continue; |
29b0f896 AM |
6865 | /* Reject eight bit registers, except where the template requires |
6866 | them. (eg. movzb) */ | |
dc821c5f | 6867 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6868 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6869 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6870 | && (i.tm.operand_types[op].bitfield.word |
6871 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6872 | { |
a540244d L |
6873 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6874 | register_prefix, | |
29b0f896 AM |
6875 | i.op[op].regs->reg_name, |
6876 | i.tm.name, | |
6877 | i.suffix); | |
6878 | return 0; | |
6879 | } | |
e4630f71 | 6880 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6881 | else if ((i.types[op].bitfield.word |
6882 | || i.types[op].bitfield.dword) | |
bab6aec1 | 6883 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6884 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6885 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
6886 | { |
6887 | /* Prohibit these changes in the 64bit mode, since the | |
6888 | lowering is more complicated. */ | |
34828aad | 6889 | if (intel_syntax |
ca61edf2 | 6890 | && i.tm.opcode_modifier.todword |
3528c362 | 6891 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6892 | { |
ca61edf2 | 6893 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6894 | i.suffix = LONG_MNEM_SUFFIX; |
6895 | } | |
6896 | else | |
6897 | { | |
2b5d6a91 | 6898 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6899 | register_prefix, i.op[op].regs->reg_name, |
6900 | i.suffix); | |
6901 | return 0; | |
6902 | } | |
252b5132 | 6903 | } |
29b0f896 AM |
6904 | return 1; |
6905 | } | |
252b5132 | 6906 | |
29b0f896 | 6907 | static int |
e3bb37b5 | 6908 | check_word_reg (void) |
29b0f896 AM |
6909 | { |
6910 | int op; | |
6911 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6912 | /* Skip non-register operands. */ |
bab6aec1 | 6913 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6914 | continue; |
29b0f896 AM |
6915 | /* Reject eight bit registers, except where the template requires |
6916 | them. (eg. movzb) */ | |
dc821c5f | 6917 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6918 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6919 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6920 | && (i.tm.operand_types[op].bitfield.word |
6921 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6922 | { |
a540244d L |
6923 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6924 | register_prefix, | |
29b0f896 AM |
6925 | i.op[op].regs->reg_name, |
6926 | i.tm.name, | |
6927 | i.suffix); | |
6928 | return 0; | |
6929 | } | |
9706160a JB |
6930 | /* Error if the e or r prefix on a general reg is present. */ |
6931 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 6932 | || i.types[op].bitfield.qword) |
bab6aec1 | 6933 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6934 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6935 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 6936 | { |
9706160a JB |
6937 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6938 | register_prefix, i.op[op].regs->reg_name, | |
6939 | i.suffix); | |
6940 | return 0; | |
29b0f896 AM |
6941 | } |
6942 | return 1; | |
6943 | } | |
252b5132 | 6944 | |
29b0f896 | 6945 | static int |
40fb9820 | 6946 | update_imm (unsigned int j) |
29b0f896 | 6947 | { |
bc0844ae | 6948 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6949 | if ((overlap.bitfield.imm8 |
6950 | || overlap.bitfield.imm8s | |
6951 | || overlap.bitfield.imm16 | |
6952 | || overlap.bitfield.imm32 | |
6953 | || overlap.bitfield.imm32s | |
6954 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6955 | && !operand_type_equal (&overlap, &imm8) |
6956 | && !operand_type_equal (&overlap, &imm8s) | |
6957 | && !operand_type_equal (&overlap, &imm16) | |
6958 | && !operand_type_equal (&overlap, &imm32) | |
6959 | && !operand_type_equal (&overlap, &imm32s) | |
6960 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6961 | { |
6962 | if (i.suffix) | |
6963 | { | |
40fb9820 L |
6964 | i386_operand_type temp; |
6965 | ||
0dfbf9d7 | 6966 | operand_type_set (&temp, 0); |
7ab9ffdd | 6967 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6968 | { |
6969 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6970 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6971 | } | |
6972 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6973 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6974 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6975 | { | |
6976 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6977 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6978 | } | |
6979 | else | |
6980 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6981 | overlap = temp; | |
29b0f896 | 6982 | } |
0dfbf9d7 L |
6983 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6984 | || operand_type_equal (&overlap, &imm16_32) | |
6985 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6986 | { |
40fb9820 | 6987 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6988 | overlap = imm16; |
40fb9820 | 6989 | else |
65da13b5 | 6990 | overlap = imm32s; |
29b0f896 | 6991 | } |
0dfbf9d7 L |
6992 | if (!operand_type_equal (&overlap, &imm8) |
6993 | && !operand_type_equal (&overlap, &imm8s) | |
6994 | && !operand_type_equal (&overlap, &imm16) | |
6995 | && !operand_type_equal (&overlap, &imm32) | |
6996 | && !operand_type_equal (&overlap, &imm32s) | |
6997 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6998 | { |
4eed87de AM |
6999 | as_bad (_("no instruction mnemonic suffix given; " |
7000 | "can't determine immediate size")); | |
29b0f896 AM |
7001 | return 0; |
7002 | } | |
7003 | } | |
40fb9820 | 7004 | i.types[j] = overlap; |
29b0f896 | 7005 | |
40fb9820 L |
7006 | return 1; |
7007 | } | |
7008 | ||
7009 | static int | |
7010 | finalize_imm (void) | |
7011 | { | |
bc0844ae | 7012 | unsigned int j, n; |
29b0f896 | 7013 | |
bc0844ae L |
7014 | /* Update the first 2 immediate operands. */ |
7015 | n = i.operands > 2 ? 2 : i.operands; | |
7016 | if (n) | |
7017 | { | |
7018 | for (j = 0; j < n; j++) | |
7019 | if (update_imm (j) == 0) | |
7020 | return 0; | |
40fb9820 | 7021 | |
bc0844ae L |
7022 | /* The 3rd operand can't be immediate operand. */ |
7023 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7024 | } | |
29b0f896 AM |
7025 | |
7026 | return 1; | |
7027 | } | |
7028 | ||
7029 | static int | |
e3bb37b5 | 7030 | process_operands (void) |
29b0f896 AM |
7031 | { |
7032 | /* Default segment register this instruction will use for memory | |
7033 | accesses. 0 means unknown. This is only for optimizing out | |
7034 | unnecessary segment overrides. */ | |
7035 | const seg_entry *default_seg = 0; | |
7036 | ||
2426c15f | 7037 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7038 | { |
91d6fa6a NC |
7039 | unsigned int dupl = i.operands; |
7040 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7041 | unsigned int j; |
7042 | ||
c0f3af97 | 7043 | /* The destination must be an xmm register. */ |
9c2799c2 | 7044 | gas_assert (i.reg_operands |
91d6fa6a | 7045 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7046 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7047 | |
75e5731b | 7048 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7049 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7050 | { |
8cd7925b | 7051 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7052 | { |
7053 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7054 | sources. */ | |
75e5731b | 7055 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7056 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7057 | goto duplicate; |
7058 | } | |
e2ec9d29 | 7059 | else |
c0f3af97 L |
7060 | { |
7061 | /* We remove the first xmm0 and keep the number of | |
7062 | operands unchanged, which in fact duplicates the | |
7063 | destination. */ | |
7064 | for (j = 1; j < i.operands; j++) | |
7065 | { | |
7066 | i.op[j - 1] = i.op[j]; | |
7067 | i.types[j - 1] = i.types[j]; | |
7068 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7069 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7070 | } |
7071 | } | |
7072 | } | |
7073 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7074 | { |
91d6fa6a | 7075 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7076 | && (i.tm.opcode_modifier.vexsources |
7077 | == VEX3SOURCES)); | |
c0f3af97 L |
7078 | |
7079 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7080 | and 3 sources. */ | |
7081 | for (j = i.operands; j > 0; j--) | |
7082 | { | |
7083 | i.op[j] = i.op[j - 1]; | |
7084 | i.types[j] = i.types[j - 1]; | |
7085 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7086 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7087 | } |
7088 | i.op[0].regs | |
7089 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 7090 | i.types[0] = regxmm; |
c0f3af97 L |
7091 | i.tm.operand_types[0] = regxmm; |
7092 | ||
7093 | i.operands += 2; | |
7094 | i.reg_operands += 2; | |
7095 | i.tm.operands += 2; | |
7096 | ||
91d6fa6a | 7097 | dupl++; |
c0f3af97 | 7098 | dest++; |
91d6fa6a NC |
7099 | i.op[dupl] = i.op[dest]; |
7100 | i.types[dupl] = i.types[dest]; | |
7101 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7102 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7103 | } |
c0f3af97 L |
7104 | else |
7105 | { | |
dc1e8a47 | 7106 | duplicate: |
c0f3af97 L |
7107 | i.operands++; |
7108 | i.reg_operands++; | |
7109 | i.tm.operands++; | |
7110 | ||
91d6fa6a NC |
7111 | i.op[dupl] = i.op[dest]; |
7112 | i.types[dupl] = i.types[dest]; | |
7113 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7114 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7115 | } |
7116 | ||
7117 | if (i.tm.opcode_modifier.immext) | |
7118 | process_immext (); | |
7119 | } | |
75e5731b | 7120 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7121 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7122 | { |
7123 | unsigned int j; | |
7124 | ||
9fcfb3d7 L |
7125 | for (j = 1; j < i.operands; j++) |
7126 | { | |
7127 | i.op[j - 1] = i.op[j]; | |
7128 | i.types[j - 1] = i.types[j]; | |
7129 | ||
7130 | /* We need to adjust fields in i.tm since they are used by | |
7131 | build_modrm_byte. */ | |
7132 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7133 | |
7134 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7135 | } |
7136 | ||
e2ec9d29 L |
7137 | i.operands--; |
7138 | i.reg_operands--; | |
e2ec9d29 L |
7139 | i.tm.operands--; |
7140 | } | |
920d2ddc IT |
7141 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7142 | { | |
a477a8c4 JB |
7143 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7144 | ||
920d2ddc | 7145 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7146 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7147 | regnum = register_number (i.op[1].regs); |
7148 | first_reg_in_group = regnum & ~3; | |
7149 | last_reg_in_group = first_reg_in_group + 3; | |
7150 | if (regnum != first_reg_in_group) | |
7151 | as_warn (_("source register `%s%s' implicitly denotes" | |
7152 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7153 | register_prefix, i.op[1].regs->reg_name, | |
7154 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7155 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7156 | i.tm.name); | |
7157 | } | |
e2ec9d29 L |
7158 | else if (i.tm.opcode_modifier.regkludge) |
7159 | { | |
7160 | /* The imul $imm, %reg instruction is converted into | |
7161 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7162 | is converted into xor %reg, %reg. */ | |
7163 | ||
7164 | unsigned int first_reg_op; | |
7165 | ||
7166 | if (operand_type_check (i.types[0], reg)) | |
7167 | first_reg_op = 0; | |
7168 | else | |
7169 | first_reg_op = 1; | |
7170 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7171 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7172 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7173 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7174 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7175 | i.operands++; | |
7176 | i.reg_operands++; | |
29b0f896 AM |
7177 | } |
7178 | ||
85b80b0f | 7179 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7180 | { |
7181 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7182 | must be put into the modrm byte). Now, we make the modrm and |
7183 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7184 | |
7185 | default_seg = build_modrm_byte (); | |
7186 | } | |
00cee14f | 7187 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7188 | { |
7189 | if (flag_code != CODE_64BIT | |
7190 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7191 | && i.op[0].regs->reg_num == 1 | |
7192 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7193 | && i.op[0].regs->reg_num < 4) | |
7194 | { | |
7195 | as_bad (_("you can't `%s %s%s'"), | |
7196 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7197 | return 0; | |
7198 | } | |
7199 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7200 | { | |
7201 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7202 | i.tm.opcode_length = 2; | |
7203 | } | |
7204 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7205 | } | |
8a2ed489 | 7206 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7207 | { |
7208 | default_seg = &ds; | |
7209 | } | |
40fb9820 | 7210 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7211 | { |
7212 | /* For the string instructions that allow a segment override | |
7213 | on one of their operands, the default segment is ds. */ | |
7214 | default_seg = &ds; | |
7215 | } | |
50128d0c | 7216 | else if (i.short_form) |
85b80b0f JB |
7217 | { |
7218 | /* The register or float register operand is in operand | |
7219 | 0 or 1. */ | |
bab6aec1 | 7220 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7221 | |
7222 | /* Register goes in low 3 bits of opcode. */ | |
7223 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7224 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7225 | i.rex |= REX_B; | |
7226 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7227 | { | |
7228 | /* Warn about some common errors, but press on regardless. | |
7229 | The first case can be generated by gcc (<= 2.8.1). */ | |
7230 | if (i.operands == 2) | |
7231 | { | |
7232 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7233 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7234 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7235 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7236 | } | |
7237 | else | |
7238 | { | |
7239 | /* Extraneous `l' suffix on fp insn. */ | |
7240 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7241 | register_prefix, i.op[0].regs->reg_name); | |
7242 | } | |
7243 | } | |
7244 | } | |
29b0f896 | 7245 | |
514a8bb0 | 7246 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 JB |
7247 | && i.tm.base_opcode == 0x8d /* lea */ |
7248 | && !is_any_vex_encoding(&i.tm)) | |
92334ad2 JB |
7249 | { |
7250 | if (!quiet_warnings) | |
7251 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7252 | if (optimize) | |
7253 | { | |
7254 | i.seg[0] = NULL; | |
7255 | i.prefix[SEG_PREFIX] = 0; | |
7256 | } | |
7257 | } | |
52271982 AM |
7258 | |
7259 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
7260 | is neither the default nor the one already recorded from a prefix, |
7261 | use an opcode prefix to select it. If we never figured out what | |
7262 | the default segment is, then default_seg will be zero at this | |
7263 | point, and the specified segment prefix will always be used. */ | |
7264 | if (i.seg[0] | |
7265 | && i.seg[0] != default_seg | |
7266 | && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX]) | |
29b0f896 AM |
7267 | { |
7268 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7269 | return 0; | |
7270 | } | |
7271 | return 1; | |
7272 | } | |
7273 | ||
7274 | static const seg_entry * | |
e3bb37b5 | 7275 | build_modrm_byte (void) |
29b0f896 AM |
7276 | { |
7277 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7278 | unsigned int source, dest; |
8cd7925b | 7279 | int vex_3_sources; |
c0f3af97 | 7280 | |
8cd7925b | 7281 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7282 | if (vex_3_sources) |
7283 | { | |
91d6fa6a | 7284 | unsigned int nds, reg_slot; |
4c2c6516 | 7285 | expressionS *exp; |
c0f3af97 | 7286 | |
6b8d3588 | 7287 | dest = i.operands - 1; |
c0f3af97 | 7288 | nds = dest - 1; |
922d8de8 | 7289 | |
a683cc34 | 7290 | /* There are 2 kinds of instructions: |
bed3d976 | 7291 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7292 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7293 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7294 | ZMM register. |
bed3d976 | 7295 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7296 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7297 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7298 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7299 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7300 | && i.tm.opcode_modifier.vexw |
3528c362 | 7301 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7302 | |
48db9223 JB |
7303 | /* If VexW1 is set, the first non-immediate operand is the source and |
7304 | the second non-immediate one is encoded in the immediate operand. */ | |
7305 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7306 | { | |
7307 | source = i.imm_operands; | |
7308 | reg_slot = i.imm_operands + 1; | |
7309 | } | |
7310 | else | |
7311 | { | |
7312 | source = i.imm_operands + 1; | |
7313 | reg_slot = i.imm_operands; | |
7314 | } | |
7315 | ||
a683cc34 | 7316 | if (i.imm_operands == 0) |
bed3d976 JB |
7317 | { |
7318 | /* When there is no immediate operand, generate an 8bit | |
7319 | immediate operand to encode the first operand. */ | |
7320 | exp = &im_expressions[i.imm_operands++]; | |
7321 | i.op[i.operands].imms = exp; | |
7322 | i.types[i.operands] = imm8; | |
7323 | i.operands++; | |
7324 | ||
3528c362 | 7325 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7326 | exp->X_op = O_constant; |
7327 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7328 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7329 | } | |
922d8de8 | 7330 | else |
bed3d976 | 7331 | { |
9d3bf266 JB |
7332 | gas_assert (i.imm_operands == 1); |
7333 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7334 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7335 | |
9d3bf266 JB |
7336 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7337 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7338 | |
3528c362 | 7339 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7340 | i.op[0].imms->X_add_number |
bed3d976 | 7341 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7342 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7343 | } |
a683cc34 | 7344 | |
3528c362 | 7345 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7346 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7347 | } |
7348 | else | |
7349 | source = dest = 0; | |
29b0f896 AM |
7350 | |
7351 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7352 | implicit registers do not count. If there are 3 register |
7353 | operands, it must be a instruction with VexNDS. For a | |
7354 | instruction with VexNDD, the destination register is encoded | |
7355 | in VEX prefix. If there are 4 register operands, it must be | |
7356 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7357 | if (i.mem_operands == 0 |
7358 | && ((i.reg_operands == 2 | |
2426c15f | 7359 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7360 | || (i.reg_operands == 3 |
2426c15f | 7361 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7362 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7363 | { |
cab737b9 L |
7364 | switch (i.operands) |
7365 | { | |
7366 | case 2: | |
7367 | source = 0; | |
7368 | break; | |
7369 | case 3: | |
c81128dc L |
7370 | /* When there are 3 operands, one of them may be immediate, |
7371 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7372 | the first operand must be shift count register (cl) or it |
7373 | is an instruction with VexNDS. */ | |
9c2799c2 | 7374 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7375 | || (i.imm_operands == 0 |
2426c15f | 7376 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7377 | || (i.types[0].bitfield.instance == RegC |
7378 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7379 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7380 | || (i.types[0].bitfield.instance == RegC |
7381 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7382 | source = 1; |
7383 | else | |
7384 | source = 0; | |
cab737b9 L |
7385 | break; |
7386 | case 4: | |
368d64cc L |
7387 | /* When there are 4 operands, the first two must be 8bit |
7388 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7389 | one. |
7390 | ||
7391 | For instructions with VexNDS, if the first operand | |
7392 | an imm8, the source operand is the 2nd one. If the last | |
7393 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7394 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7395 | && i.types[0].bitfield.imm8 |
7396 | && i.types[1].bitfield.imm8) | |
2426c15f | 7397 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7398 | && i.imm_operands == 1 |
7399 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7400 | || i.types[i.operands - 1].bitfield.imm8 |
7401 | || i.rounding))); | |
9f2670f2 L |
7402 | if (i.imm_operands == 2) |
7403 | source = 2; | |
7404 | else | |
c0f3af97 L |
7405 | { |
7406 | if (i.types[0].bitfield.imm8) | |
7407 | source = 1; | |
7408 | else | |
7409 | source = 0; | |
7410 | } | |
c0f3af97 L |
7411 | break; |
7412 | case 5: | |
e771e7c9 | 7413 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7414 | { |
7415 | /* For EVEX instructions, when there are 5 operands, the | |
7416 | first one must be immediate operand. If the second one | |
7417 | is immediate operand, the source operand is the 3th | |
7418 | one. If the last one is immediate operand, the source | |
7419 | operand is the 2nd one. */ | |
7420 | gas_assert (i.imm_operands == 2 | |
7421 | && i.tm.opcode_modifier.sae | |
7422 | && operand_type_check (i.types[0], imm)); | |
7423 | if (operand_type_check (i.types[1], imm)) | |
7424 | source = 2; | |
7425 | else if (operand_type_check (i.types[4], imm)) | |
7426 | source = 1; | |
7427 | else | |
7428 | abort (); | |
7429 | } | |
cab737b9 L |
7430 | break; |
7431 | default: | |
7432 | abort (); | |
7433 | } | |
7434 | ||
c0f3af97 L |
7435 | if (!vex_3_sources) |
7436 | { | |
7437 | dest = source + 1; | |
7438 | ||
43234a1e L |
7439 | /* RC/SAE operand could be between DEST and SRC. That happens |
7440 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7441 | register. */ | |
7442 | if (i.rounding && i.rounding->operand == (int) dest) | |
7443 | dest++; | |
7444 | ||
2426c15f | 7445 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7446 | { |
43234a1e | 7447 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7448 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7449 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7450 | |
7451 | i386_operand_type op; | |
7452 | unsigned int vvvv; | |
7453 | ||
7454 | /* Check register-only source operand when two source | |
7455 | operands are swapped. */ | |
7456 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7457 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7458 | { | |
7459 | vvvv = source; | |
7460 | source = dest; | |
7461 | } | |
7462 | else | |
7463 | vvvv = dest; | |
7464 | ||
7465 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7466 | if ((dest + 1) >= i.operands |
bab6aec1 | 7467 | || ((op.bitfield.class != Reg |
dc821c5f | 7468 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7469 | && op.bitfield.class != RegSIMD |
43234a1e | 7470 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7471 | abort (); |
f12dc422 | 7472 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7473 | dest++; |
7474 | } | |
7475 | } | |
29b0f896 AM |
7476 | |
7477 | i.rm.mode = 3; | |
dfd69174 JB |
7478 | /* One of the register operands will be encoded in the i.rm.reg |
7479 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7480 | fields. If no form of this instruction supports a memory |
7481 | destination operand, then we assume the source operand may | |
7482 | sometimes be a memory operand and so we need to store the | |
7483 | destination in the i.rm.reg field. */ | |
dfd69174 | 7484 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7485 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7486 | { |
7487 | i.rm.reg = i.op[dest].regs->reg_num; | |
7488 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7489 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7490 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7491 | i.has_regmmx = TRUE; |
3528c362 JB |
7492 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7493 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7494 | { |
7495 | if (i.types[dest].bitfield.zmmword | |
7496 | || i.types[source].bitfield.zmmword) | |
7497 | i.has_regzmm = TRUE; | |
7498 | else if (i.types[dest].bitfield.ymmword | |
7499 | || i.types[source].bitfield.ymmword) | |
7500 | i.has_regymm = TRUE; | |
7501 | else | |
7502 | i.has_regxmm = TRUE; | |
7503 | } | |
29b0f896 | 7504 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7505 | i.rex |= REX_R; |
43234a1e L |
7506 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7507 | i.vrex |= REX_R; | |
29b0f896 | 7508 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7509 | i.rex |= REX_B; |
43234a1e L |
7510 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7511 | i.vrex |= REX_B; | |
29b0f896 AM |
7512 | } |
7513 | else | |
7514 | { | |
7515 | i.rm.reg = i.op[source].regs->reg_num; | |
7516 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7517 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7518 | i.rex |= REX_B; |
43234a1e L |
7519 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7520 | i.vrex |= REX_B; | |
29b0f896 | 7521 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7522 | i.rex |= REX_R; |
43234a1e L |
7523 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7524 | i.vrex |= REX_R; | |
29b0f896 | 7525 | } |
e0c7f900 | 7526 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7527 | { |
4a5c67ed | 7528 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7529 | abort (); |
e0c7f900 | 7530 | i.rex &= ~REX_R; |
c4a530c5 JB |
7531 | add_prefix (LOCK_PREFIX_OPCODE); |
7532 | } | |
29b0f896 AM |
7533 | } |
7534 | else | |
7535 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7536 | unsigned int mem; |
7537 | ||
29b0f896 AM |
7538 | if (i.mem_operands) |
7539 | { | |
7540 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7541 | unsigned int op; |
4eed87de | 7542 | |
7ab9ffdd | 7543 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7544 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7545 | break; |
7ab9ffdd | 7546 | gas_assert (op < i.operands); |
29b0f896 | 7547 | |
6c30d220 L |
7548 | if (i.tm.opcode_modifier.vecsib) |
7549 | { | |
e968fc9b | 7550 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7551 | abort (); |
7552 | ||
7553 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7554 | if (!i.base_reg) | |
7555 | { | |
7556 | i.sib.base = NO_BASE_REGISTER; | |
7557 | i.sib.scale = i.log2_scale_factor; | |
7558 | i.types[op].bitfield.disp8 = 0; | |
7559 | i.types[op].bitfield.disp16 = 0; | |
7560 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7561 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7562 | { |
7563 | /* Must be 32 bit */ | |
7564 | i.types[op].bitfield.disp32 = 1; | |
7565 | i.types[op].bitfield.disp32s = 0; | |
7566 | } | |
7567 | else | |
7568 | { | |
7569 | i.types[op].bitfield.disp32 = 0; | |
7570 | i.types[op].bitfield.disp32s = 1; | |
7571 | } | |
7572 | } | |
7573 | i.sib.index = i.index_reg->reg_num; | |
7574 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7575 | i.rex |= REX_X; | |
43234a1e L |
7576 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7577 | i.vrex |= REX_X; | |
6c30d220 L |
7578 | } |
7579 | ||
29b0f896 AM |
7580 | default_seg = &ds; |
7581 | ||
7582 | if (i.base_reg == 0) | |
7583 | { | |
7584 | i.rm.mode = 0; | |
7585 | if (!i.disp_operands) | |
9bb129e8 | 7586 | fake_zero_displacement = 1; |
29b0f896 AM |
7587 | if (i.index_reg == 0) |
7588 | { | |
73053c1f JB |
7589 | i386_operand_type newdisp; |
7590 | ||
6c30d220 | 7591 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7592 | /* Operand is just <disp> */ |
20f0a1fc | 7593 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7594 | { |
7595 | /* 64bit mode overwrites the 32bit absolute | |
7596 | addressing by RIP relative addressing and | |
7597 | absolute addressing is encoded by one of the | |
7598 | redundant SIB forms. */ | |
7599 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7600 | i.sib.base = NO_BASE_REGISTER; | |
7601 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7602 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7603 | } |
fc225355 L |
7604 | else if ((flag_code == CODE_16BIT) |
7605 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7606 | { |
7607 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7608 | newdisp = disp16; |
20f0a1fc NC |
7609 | } |
7610 | else | |
7611 | { | |
7612 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7613 | newdisp = disp32; |
29b0f896 | 7614 | } |
73053c1f JB |
7615 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7616 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7617 | } |
6c30d220 | 7618 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7619 | { |
6c30d220 | 7620 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7621 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7622 | i.sib.index = NO_INDEX_REGISTER; |
7623 | else | |
7624 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7625 | i.sib.base = NO_BASE_REGISTER; |
7626 | i.sib.scale = i.log2_scale_factor; | |
7627 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7628 | i.types[op].bitfield.disp8 = 0; |
7629 | i.types[op].bitfield.disp16 = 0; | |
7630 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7631 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7632 | { |
7633 | /* Must be 32 bit */ | |
7634 | i.types[op].bitfield.disp32 = 1; | |
7635 | i.types[op].bitfield.disp32s = 0; | |
7636 | } | |
29b0f896 | 7637 | else |
40fb9820 L |
7638 | { |
7639 | i.types[op].bitfield.disp32 = 0; | |
7640 | i.types[op].bitfield.disp32s = 1; | |
7641 | } | |
29b0f896 | 7642 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7643 | i.rex |= REX_X; |
29b0f896 AM |
7644 | } |
7645 | } | |
7646 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7647 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7648 | { |
6c30d220 | 7649 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7650 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7651 | i.types[op].bitfield.disp8 = 0; |
7652 | i.types[op].bitfield.disp16 = 0; | |
7653 | i.types[op].bitfield.disp32 = 0; | |
7654 | i.types[op].bitfield.disp32s = 1; | |
7655 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7656 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7657 | if (! i.disp_operands) |
7658 | fake_zero_displacement = 1; | |
29b0f896 | 7659 | } |
dc821c5f | 7660 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7661 | { |
6c30d220 | 7662 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7663 | switch (i.base_reg->reg_num) |
7664 | { | |
7665 | case 3: /* (%bx) */ | |
7666 | if (i.index_reg == 0) | |
7667 | i.rm.regmem = 7; | |
7668 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7669 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7670 | break; | |
7671 | case 5: /* (%bp) */ | |
7672 | default_seg = &ss; | |
7673 | if (i.index_reg == 0) | |
7674 | { | |
7675 | i.rm.regmem = 6; | |
40fb9820 | 7676 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7677 | { |
7678 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7679 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7680 | fake_zero_displacement = 1; |
29b0f896 AM |
7681 | } |
7682 | } | |
7683 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7684 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7685 | break; | |
7686 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7687 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7688 | } | |
7689 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7690 | } | |
7691 | else /* i.base_reg and 32/64 bit mode */ | |
7692 | { | |
7693 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7694 | && operand_type_check (i.types[op], disp)) |
7695 | { | |
73053c1f JB |
7696 | i.types[op].bitfield.disp16 = 0; |
7697 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7698 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7699 | { |
7700 | i.types[op].bitfield.disp32 = 0; | |
7701 | i.types[op].bitfield.disp32s = 1; | |
7702 | } | |
40fb9820 | 7703 | else |
73053c1f JB |
7704 | { |
7705 | i.types[op].bitfield.disp32 = 1; | |
7706 | i.types[op].bitfield.disp32s = 0; | |
7707 | } | |
40fb9820 | 7708 | } |
20f0a1fc | 7709 | |
6c30d220 L |
7710 | if (!i.tm.opcode_modifier.vecsib) |
7711 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7712 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7713 | i.rex |= REX_B; |
29b0f896 AM |
7714 | i.sib.base = i.base_reg->reg_num; |
7715 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7716 | complications. */ | |
848930b2 JB |
7717 | if (!(i.base_reg->reg_flags & RegRex) |
7718 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7719 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7720 | default_seg = &ss; |
848930b2 | 7721 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7722 | { |
848930b2 | 7723 | fake_zero_displacement = 1; |
b5014f7a | 7724 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7725 | } |
7726 | i.sib.scale = i.log2_scale_factor; | |
7727 | if (i.index_reg == 0) | |
7728 | { | |
6c30d220 | 7729 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7730 | /* <disp>(%esp) becomes two byte modrm with no index |
7731 | register. We've already stored the code for esp | |
7732 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7733 | Any base register besides %esp will not use the | |
7734 | extra modrm byte. */ | |
7735 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7736 | } |
6c30d220 | 7737 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7738 | { |
e968fc9b | 7739 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7740 | i.sib.index = NO_INDEX_REGISTER; |
7741 | else | |
7742 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7743 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7744 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7745 | i.rex |= REX_X; |
29b0f896 | 7746 | } |
67a4f2b7 AO |
7747 | |
7748 | if (i.disp_operands | |
7749 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7750 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7751 | i.rm.mode = 0; | |
7752 | else | |
a501d77e L |
7753 | { |
7754 | if (!fake_zero_displacement | |
7755 | && !i.disp_operands | |
7756 | && i.disp_encoding) | |
7757 | { | |
7758 | fake_zero_displacement = 1; | |
7759 | if (i.disp_encoding == disp_encoding_8bit) | |
7760 | i.types[op].bitfield.disp8 = 1; | |
7761 | else | |
7762 | i.types[op].bitfield.disp32 = 1; | |
7763 | } | |
7764 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7765 | } | |
29b0f896 | 7766 | } |
252b5132 | 7767 | |
29b0f896 AM |
7768 | if (fake_zero_displacement) |
7769 | { | |
7770 | /* Fakes a zero displacement assuming that i.types[op] | |
7771 | holds the correct displacement size. */ | |
7772 | expressionS *exp; | |
7773 | ||
9c2799c2 | 7774 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7775 | exp = &disp_expressions[i.disp_operands++]; |
7776 | i.op[op].disps = exp; | |
7777 | exp->X_op = O_constant; | |
7778 | exp->X_add_number = 0; | |
7779 | exp->X_add_symbol = (symbolS *) 0; | |
7780 | exp->X_op_symbol = (symbolS *) 0; | |
7781 | } | |
c0f3af97 L |
7782 | |
7783 | mem = op; | |
29b0f896 | 7784 | } |
c0f3af97 L |
7785 | else |
7786 | mem = ~0; | |
252b5132 | 7787 | |
8c43a48b | 7788 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7789 | { |
7790 | if (operand_type_check (i.types[0], imm)) | |
7791 | i.vex.register_specifier = NULL; | |
7792 | else | |
7793 | { | |
7794 | /* VEX.vvvv encodes one of the sources when the first | |
7795 | operand is not an immediate. */ | |
1ef99a7b | 7796 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7797 | i.vex.register_specifier = i.op[0].regs; |
7798 | else | |
7799 | i.vex.register_specifier = i.op[1].regs; | |
7800 | } | |
7801 | ||
7802 | /* Destination is a XMM register encoded in the ModRM.reg | |
7803 | and VEX.R bit. */ | |
7804 | i.rm.reg = i.op[2].regs->reg_num; | |
7805 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7806 | i.rex |= REX_R; | |
7807 | ||
7808 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7809 | if (!i.mem_operands) | |
7810 | { | |
7811 | i.rm.mode = 3; | |
7812 | ||
1ef99a7b | 7813 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7814 | i.rm.regmem = i.op[1].regs->reg_num; |
7815 | else | |
7816 | i.rm.regmem = i.op[0].regs->reg_num; | |
7817 | ||
7818 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7819 | i.rex |= REX_B; | |
7820 | } | |
7821 | } | |
2426c15f | 7822 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7823 | { |
7824 | i.vex.register_specifier = i.op[2].regs; | |
7825 | if (!i.mem_operands) | |
7826 | { | |
7827 | i.rm.mode = 3; | |
7828 | i.rm.regmem = i.op[1].regs->reg_num; | |
7829 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7830 | i.rex |= REX_B; | |
7831 | } | |
7832 | } | |
29b0f896 AM |
7833 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7834 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7835 | careful to make sure that segment/control/debug/test/MMX | |
7836 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7837 | else if (i.reg_operands) |
29b0f896 | 7838 | { |
99018f42 | 7839 | unsigned int op; |
7ab9ffdd L |
7840 | unsigned int vex_reg = ~0; |
7841 | ||
7842 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 7843 | { |
bab6aec1 | 7844 | if (i.types[op].bitfield.class == Reg |
f74a6307 JB |
7845 | || i.types[op].bitfield.class == RegBND |
7846 | || i.types[op].bitfield.class == RegMask | |
00cee14f | 7847 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7848 | || i.types[op].bitfield.class == RegCR |
7849 | || i.types[op].bitfield.class == RegDR | |
7850 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 7851 | break; |
3528c362 | 7852 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
7853 | { |
7854 | if (i.types[op].bitfield.zmmword) | |
7855 | i.has_regzmm = TRUE; | |
7856 | else if (i.types[op].bitfield.ymmword) | |
7857 | i.has_regymm = TRUE; | |
7858 | else | |
7859 | i.has_regxmm = TRUE; | |
7860 | break; | |
7861 | } | |
3528c362 | 7862 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
7863 | { |
7864 | i.has_regmmx = TRUE; | |
7865 | break; | |
7866 | } | |
7867 | } | |
c0209578 | 7868 | |
7ab9ffdd L |
7869 | if (vex_3_sources) |
7870 | op = dest; | |
2426c15f | 7871 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7872 | { |
7873 | /* For instructions with VexNDS, the register-only | |
7874 | source operand is encoded in VEX prefix. */ | |
7875 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7876 | |
7ab9ffdd | 7877 | if (op > mem) |
c0f3af97 | 7878 | { |
7ab9ffdd L |
7879 | vex_reg = op++; |
7880 | gas_assert (op < i.operands); | |
c0f3af97 L |
7881 | } |
7882 | else | |
c0f3af97 | 7883 | { |
f12dc422 L |
7884 | /* Check register-only source operand when two source |
7885 | operands are swapped. */ | |
7886 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7887 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7888 | { | |
7889 | vex_reg = op; | |
7890 | op += 2; | |
7891 | gas_assert (mem == (vex_reg + 1) | |
7892 | && op < i.operands); | |
7893 | } | |
7894 | else | |
7895 | { | |
7896 | vex_reg = op + 1; | |
7897 | gas_assert (vex_reg < i.operands); | |
7898 | } | |
c0f3af97 | 7899 | } |
7ab9ffdd | 7900 | } |
2426c15f | 7901 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7902 | { |
f12dc422 | 7903 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7904 | is encoded in VEX prefix. */ |
f12dc422 L |
7905 | if (i.mem_operands == 0) |
7906 | { | |
7907 | /* There is no memory operand. */ | |
7908 | gas_assert ((op + 2) == i.operands); | |
7909 | vex_reg = op + 1; | |
7910 | } | |
7911 | else | |
8d63c93e | 7912 | { |
ed438a93 JB |
7913 | /* There are only 2 non-immediate operands. */ |
7914 | gas_assert (op < i.imm_operands + 2 | |
7915 | && i.operands == i.imm_operands + 2); | |
7916 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7917 | } |
7ab9ffdd L |
7918 | } |
7919 | else | |
7920 | gas_assert (op < i.operands); | |
99018f42 | 7921 | |
7ab9ffdd L |
7922 | if (vex_reg != (unsigned int) ~0) |
7923 | { | |
f12dc422 | 7924 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7925 | |
bab6aec1 | 7926 | if ((type->bitfield.class != Reg |
dc821c5f | 7927 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 7928 | && type->bitfield.class != RegSIMD |
43234a1e | 7929 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7930 | abort (); |
f88c9eb0 | 7931 | |
7ab9ffdd L |
7932 | i.vex.register_specifier = i.op[vex_reg].regs; |
7933 | } | |
7934 | ||
1b9f0c97 L |
7935 | /* Don't set OP operand twice. */ |
7936 | if (vex_reg != op) | |
7ab9ffdd | 7937 | { |
1b9f0c97 L |
7938 | /* If there is an extension opcode to put here, the |
7939 | register number must be put into the regmem field. */ | |
7940 | if (i.tm.extension_opcode != None) | |
7941 | { | |
7942 | i.rm.regmem = i.op[op].regs->reg_num; | |
7943 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7944 | i.rex |= REX_B; | |
43234a1e L |
7945 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7946 | i.vrex |= REX_B; | |
1b9f0c97 L |
7947 | } |
7948 | else | |
7949 | { | |
7950 | i.rm.reg = i.op[op].regs->reg_num; | |
7951 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7952 | i.rex |= REX_R; | |
43234a1e L |
7953 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7954 | i.vrex |= REX_R; | |
1b9f0c97 | 7955 | } |
7ab9ffdd | 7956 | } |
252b5132 | 7957 | |
29b0f896 AM |
7958 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7959 | must set it to 3 to indicate this is a register operand | |
7960 | in the regmem field. */ | |
7961 | if (!i.mem_operands) | |
7962 | i.rm.mode = 3; | |
7963 | } | |
252b5132 | 7964 | |
29b0f896 | 7965 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7966 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7967 | i.rm.reg = i.tm.extension_opcode; |
7968 | } | |
7969 | return default_seg; | |
7970 | } | |
252b5132 | 7971 | |
376cd056 JB |
7972 | static unsigned int |
7973 | flip_code16 (unsigned int code16) | |
7974 | { | |
7975 | gas_assert (i.tm.operands == 1); | |
7976 | ||
7977 | return !(i.prefix[REX_PREFIX] & REX_W) | |
7978 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
7979 | || i.tm.operand_types[0].bitfield.disp32s | |
7980 | : i.tm.operand_types[0].bitfield.disp16) | |
7981 | ? CODE16 : 0; | |
7982 | } | |
7983 | ||
29b0f896 | 7984 | static void |
e3bb37b5 | 7985 | output_branch (void) |
29b0f896 AM |
7986 | { |
7987 | char *p; | |
f8a5c266 | 7988 | int size; |
29b0f896 AM |
7989 | int code16; |
7990 | int prefix; | |
7991 | relax_substateT subtype; | |
7992 | symbolS *sym; | |
7993 | offsetT off; | |
7994 | ||
f8a5c266 | 7995 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7996 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7997 | |
7998 | prefix = 0; | |
7999 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8000 | { |
29b0f896 AM |
8001 | prefix = 1; |
8002 | i.prefixes -= 1; | |
376cd056 | 8003 | code16 ^= flip_code16(code16); |
252b5132 | 8004 | } |
29b0f896 AM |
8005 | /* Pentium4 branch hints. */ |
8006 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8007 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8008 | { |
29b0f896 AM |
8009 | prefix++; |
8010 | i.prefixes--; | |
8011 | } | |
8012 | if (i.prefix[REX_PREFIX] != 0) | |
8013 | { | |
8014 | prefix++; | |
8015 | i.prefixes--; | |
2f66722d AM |
8016 | } |
8017 | ||
7e8b059b L |
8018 | /* BND prefixed jump. */ |
8019 | if (i.prefix[BND_PREFIX] != 0) | |
8020 | { | |
6cb0a70e JB |
8021 | prefix++; |
8022 | i.prefixes--; | |
7e8b059b L |
8023 | } |
8024 | ||
f2810fe0 JB |
8025 | if (i.prefixes != 0) |
8026 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8027 | |
8028 | /* It's always a symbol; End frag & setup for relax. | |
8029 | Make sure there is enough room in this frag for the largest | |
8030 | instruction we may generate in md_convert_frag. This is 2 | |
8031 | bytes for the opcode and room for the prefix and largest | |
8032 | displacement. */ | |
8033 | frag_grow (prefix + 2 + 4); | |
8034 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8035 | p = frag_more (prefix + 1); | |
8036 | if (i.prefix[DATA_PREFIX] != 0) | |
8037 | *p++ = DATA_PREFIX_OPCODE; | |
8038 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8039 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8040 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8041 | if (i.prefix[BND_PREFIX] != 0) |
8042 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8043 | if (i.prefix[REX_PREFIX] != 0) |
8044 | *p++ = i.prefix[REX_PREFIX]; | |
8045 | *p = i.tm.base_opcode; | |
8046 | ||
8047 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8048 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8049 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8050 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8051 | else |
f8a5c266 | 8052 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8053 | subtype |= code16; |
3e73aa7c | 8054 | |
29b0f896 AM |
8055 | sym = i.op[0].disps->X_add_symbol; |
8056 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8057 | |
29b0f896 AM |
8058 | if (i.op[0].disps->X_op != O_constant |
8059 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8060 | { |
29b0f896 AM |
8061 | /* Handle complex expressions. */ |
8062 | sym = make_expr_symbol (i.op[0].disps); | |
8063 | off = 0; | |
8064 | } | |
3e73aa7c | 8065 | |
29b0f896 AM |
8066 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8067 | Pass reloc in fr_var. */ | |
d258b828 | 8068 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8069 | } |
3e73aa7c | 8070 | |
bd7ab16b L |
8071 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8072 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8073 | symbol S. */ | |
8074 | ||
8075 | static bfd_boolean | |
8076 | need_plt32_p (symbolS *s) | |
8077 | { | |
8078 | /* PLT32 relocation is ELF only. */ | |
8079 | if (!IS_ELF) | |
8080 | return FALSE; | |
8081 | ||
a5def729 RO |
8082 | #ifdef TE_SOLARIS |
8083 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8084 | krtld support it. */ | |
8085 | return FALSE; | |
8086 | #endif | |
8087 | ||
bd7ab16b L |
8088 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8089 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8090 | be used as a marker for 32-bit PC-relative branches. */ | |
8091 | if (!object_64bit) | |
8092 | return FALSE; | |
8093 | ||
8094 | /* Weak or undefined symbol need PLT32 relocation. */ | |
8095 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
8096 | return TRUE; | |
8097 | ||
8098 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8099 | if (! S_IS_EXTERNAL (s)) | |
8100 | return FALSE; | |
8101 | ||
8102 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8103 | non-default visibilities are treated as normal global symbol | |
8104 | so that PLT32 relocation can be used as a marker for 32-bit | |
8105 | PC-relative branches. It is useful for linker relaxation. */ | |
8106 | return TRUE; | |
8107 | } | |
8108 | #endif | |
8109 | ||
29b0f896 | 8110 | static void |
e3bb37b5 | 8111 | output_jump (void) |
29b0f896 AM |
8112 | { |
8113 | char *p; | |
8114 | int size; | |
3e02c1cc | 8115 | fixS *fixP; |
bd7ab16b | 8116 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8117 | |
0cfa3eb3 | 8118 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8119 | { |
8120 | /* This is a loop or jecxz type instruction. */ | |
8121 | size = 1; | |
8122 | if (i.prefix[ADDR_PREFIX] != 0) | |
8123 | { | |
8124 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
8125 | i.prefixes -= 1; | |
8126 | } | |
8127 | /* Pentium4 branch hints. */ | |
8128 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8129 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8130 | { | |
8131 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
8132 | i.prefixes--; | |
3e73aa7c JH |
8133 | } |
8134 | } | |
29b0f896 AM |
8135 | else |
8136 | { | |
8137 | int code16; | |
3e73aa7c | 8138 | |
29b0f896 AM |
8139 | code16 = 0; |
8140 | if (flag_code == CODE_16BIT) | |
8141 | code16 = CODE16; | |
3e73aa7c | 8142 | |
29b0f896 AM |
8143 | if (i.prefix[DATA_PREFIX] != 0) |
8144 | { | |
8145 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
8146 | i.prefixes -= 1; | |
376cd056 | 8147 | code16 ^= flip_code16(code16); |
29b0f896 | 8148 | } |
252b5132 | 8149 | |
29b0f896 AM |
8150 | size = 4; |
8151 | if (code16) | |
8152 | size = 2; | |
8153 | } | |
9fcc94b6 | 8154 | |
6cb0a70e JB |
8155 | /* BND prefixed jump. */ |
8156 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8157 | { |
6cb0a70e | 8158 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8159 | i.prefixes -= 1; |
8160 | } | |
252b5132 | 8161 | |
6cb0a70e | 8162 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8163 | { |
6cb0a70e | 8164 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
7e8b059b L |
8165 | i.prefixes -= 1; |
8166 | } | |
8167 | ||
f2810fe0 JB |
8168 | if (i.prefixes != 0) |
8169 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8170 | |
42164a71 L |
8171 | p = frag_more (i.tm.opcode_length + size); |
8172 | switch (i.tm.opcode_length) | |
8173 | { | |
8174 | case 2: | |
8175 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8176 | /* Fall through. */ |
42164a71 L |
8177 | case 1: |
8178 | *p++ = i.tm.base_opcode; | |
8179 | break; | |
8180 | default: | |
8181 | abort (); | |
8182 | } | |
e0890092 | 8183 | |
bd7ab16b L |
8184 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8185 | if (size == 4 | |
8186 | && jump_reloc == NO_RELOC | |
8187 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8188 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8189 | #endif | |
8190 | ||
8191 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8192 | ||
3e02c1cc | 8193 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8194 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8195 | |
8196 | /* All jumps handled here are signed, but don't use a signed limit | |
8197 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8198 | 4G and 64k respectively. */ | |
8199 | if (size == 1) | |
8200 | fixP->fx_signed = 1; | |
29b0f896 | 8201 | } |
e0890092 | 8202 | |
29b0f896 | 8203 | static void |
e3bb37b5 | 8204 | output_interseg_jump (void) |
29b0f896 AM |
8205 | { |
8206 | char *p; | |
8207 | int size; | |
8208 | int prefix; | |
8209 | int code16; | |
252b5132 | 8210 | |
29b0f896 AM |
8211 | code16 = 0; |
8212 | if (flag_code == CODE_16BIT) | |
8213 | code16 = CODE16; | |
a217f122 | 8214 | |
29b0f896 AM |
8215 | prefix = 0; |
8216 | if (i.prefix[DATA_PREFIX] != 0) | |
8217 | { | |
8218 | prefix = 1; | |
8219 | i.prefixes -= 1; | |
8220 | code16 ^= CODE16; | |
8221 | } | |
6cb0a70e JB |
8222 | |
8223 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8224 | |
29b0f896 AM |
8225 | size = 4; |
8226 | if (code16) | |
8227 | size = 2; | |
252b5132 | 8228 | |
f2810fe0 JB |
8229 | if (i.prefixes != 0) |
8230 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8231 | |
29b0f896 AM |
8232 | /* 1 opcode; 2 segment; offset */ |
8233 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8234 | |
29b0f896 AM |
8235 | if (i.prefix[DATA_PREFIX] != 0) |
8236 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8237 | |
29b0f896 AM |
8238 | if (i.prefix[REX_PREFIX] != 0) |
8239 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8240 | |
29b0f896 AM |
8241 | *p++ = i.tm.base_opcode; |
8242 | if (i.op[1].imms->X_op == O_constant) | |
8243 | { | |
8244 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8245 | |
29b0f896 AM |
8246 | if (size == 2 |
8247 | && !fits_in_unsigned_word (n) | |
8248 | && !fits_in_signed_word (n)) | |
8249 | { | |
8250 | as_bad (_("16-bit jump out of range")); | |
8251 | return; | |
8252 | } | |
8253 | md_number_to_chars (p, n, size); | |
8254 | } | |
8255 | else | |
8256 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8257 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8258 | if (i.op[0].imms->X_op != O_constant) |
8259 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8260 | i.tm.name); | |
8261 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8262 | } | |
a217f122 | 8263 | |
b4a3a7b4 L |
8264 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8265 | void | |
8266 | x86_cleanup (void) | |
8267 | { | |
8268 | char *p; | |
8269 | asection *seg = now_seg; | |
8270 | subsegT subseg = now_subseg; | |
8271 | asection *sec; | |
8272 | unsigned int alignment, align_size_1; | |
8273 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8274 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8275 | unsigned int padding; | |
8276 | ||
8277 | if (!IS_ELF || !x86_used_note) | |
8278 | return; | |
8279 | ||
b4a3a7b4 L |
8280 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8281 | ||
8282 | /* The .note.gnu.property section layout: | |
8283 | ||
8284 | Field Length Contents | |
8285 | ---- ---- ---- | |
8286 | n_namsz 4 4 | |
8287 | n_descsz 4 The note descriptor size | |
8288 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8289 | n_name 4 "GNU" | |
8290 | n_desc n_descsz The program property array | |
8291 | .... .... .... | |
8292 | */ | |
8293 | ||
8294 | /* Create the .note.gnu.property section. */ | |
8295 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8296 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8297 | (SEC_ALLOC |
8298 | | SEC_LOAD | |
8299 | | SEC_DATA | |
8300 | | SEC_HAS_CONTENTS | |
8301 | | SEC_READONLY)); | |
8302 | ||
8303 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8304 | { | |
8305 | align_size_1 = 7; | |
8306 | alignment = 3; | |
8307 | } | |
8308 | else | |
8309 | { | |
8310 | align_size_1 = 3; | |
8311 | alignment = 2; | |
8312 | } | |
8313 | ||
fd361982 | 8314 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8315 | elf_section_type (sec) = SHT_NOTE; |
8316 | ||
8317 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8318 | + 4-byte data */ | |
8319 | isa_1_descsz_raw = 4 + 4 + 4; | |
8320 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8321 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8322 | ||
8323 | feature_2_descsz_raw = isa_1_descsz; | |
8324 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8325 | + 4-byte data */ | |
8326 | feature_2_descsz_raw += 4 + 4 + 4; | |
8327 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8328 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8329 | & ~align_size_1); | |
8330 | ||
8331 | descsz = feature_2_descsz; | |
8332 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8333 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8334 | ||
8335 | /* Write n_namsz. */ | |
8336 | md_number_to_chars (p, (valueT) 4, 4); | |
8337 | ||
8338 | /* Write n_descsz. */ | |
8339 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8340 | ||
8341 | /* Write n_type. */ | |
8342 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8343 | ||
8344 | /* Write n_name. */ | |
8345 | memcpy (p + 4 * 3, "GNU", 4); | |
8346 | ||
8347 | /* Write 4-byte type. */ | |
8348 | md_number_to_chars (p + 4 * 4, | |
8349 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8350 | ||
8351 | /* Write 4-byte data size. */ | |
8352 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8353 | ||
8354 | /* Write 4-byte data. */ | |
8355 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8356 | ||
8357 | /* Zero out paddings. */ | |
8358 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8359 | if (padding) | |
8360 | memset (p + 4 * 7, 0, padding); | |
8361 | ||
8362 | /* Write 4-byte type. */ | |
8363 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8364 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8365 | ||
8366 | /* Write 4-byte data size. */ | |
8367 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8368 | ||
8369 | /* Write 4-byte data. */ | |
8370 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8371 | (valueT) x86_feature_2_used, 4); | |
8372 | ||
8373 | /* Zero out paddings. */ | |
8374 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8375 | if (padding) | |
8376 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8377 | ||
8378 | /* We probably can't restore the current segment, for there likely | |
8379 | isn't one yet... */ | |
8380 | if (seg && subseg) | |
8381 | subseg_set (seg, subseg); | |
8382 | } | |
8383 | #endif | |
8384 | ||
9c33702b JB |
8385 | static unsigned int |
8386 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8387 | const char *frag_now_ptr) | |
8388 | { | |
8389 | unsigned int len = 0; | |
8390 | ||
8391 | if (start_frag != frag_now) | |
8392 | { | |
8393 | const fragS *fr = start_frag; | |
8394 | ||
8395 | do { | |
8396 | len += fr->fr_fix; | |
8397 | fr = fr->fr_next; | |
8398 | } while (fr && fr != frag_now); | |
8399 | } | |
8400 | ||
8401 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8402 | } | |
8403 | ||
e379e5f3 | 8404 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
8405 | be macro-fused with conditional jumps. |
8406 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
8407 | or is one of the following format: | |
8408 | ||
8409 | cmp m, imm | |
8410 | add m, imm | |
8411 | sub m, imm | |
8412 | test m, imm | |
8413 | and m, imm | |
8414 | inc m | |
8415 | dec m | |
8416 | ||
8417 | it is unfusible. */ | |
e379e5f3 L |
8418 | |
8419 | static int | |
79d72f45 | 8420 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8421 | { |
8422 | /* No RIP address. */ | |
8423 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
8424 | return 0; | |
8425 | ||
8426 | /* No VEX/EVEX encoding. */ | |
8427 | if (is_any_vex_encoding (&i.tm)) | |
8428 | return 0; | |
8429 | ||
79d72f45 HL |
8430 | /* add, sub without add/sub m, imm. */ |
8431 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
8432 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
8433 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 8434 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 8435 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
8436 | { |
8437 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8438 | return !(i.mem_operands && i.imm_operands); | |
8439 | } | |
e379e5f3 | 8440 | |
79d72f45 HL |
8441 | /* and without and m, imm. */ |
8442 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
8443 | || ((i.tm.base_opcode | 3) == 0x83 | |
8444 | && i.tm.extension_opcode == 0x4)) | |
8445 | { | |
8446 | *mf_cmp_p = mf_cmp_test_and; | |
8447 | return !(i.mem_operands && i.imm_operands); | |
8448 | } | |
8449 | ||
8450 | /* test without test m imm. */ | |
e379e5f3 L |
8451 | if ((i.tm.base_opcode | 1) == 0x85 |
8452 | || (i.tm.base_opcode | 1) == 0xa9 | |
8453 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
8454 | && i.tm.extension_opcode == 0)) |
8455 | { | |
8456 | *mf_cmp_p = mf_cmp_test_and; | |
8457 | return !(i.mem_operands && i.imm_operands); | |
8458 | } | |
8459 | ||
8460 | /* cmp without cmp m, imm. */ | |
8461 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
8462 | || ((i.tm.base_opcode | 3) == 0x83 |
8463 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
8464 | { |
8465 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8466 | return !(i.mem_operands && i.imm_operands); | |
8467 | } | |
e379e5f3 | 8468 | |
79d72f45 | 8469 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
8470 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
8471 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
8472 | || ((i.tm.base_opcode | 1) == 0xff | |
8473 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
8474 | { |
8475 | *mf_cmp_p = mf_cmp_incdec; | |
8476 | return !i.mem_operands; | |
8477 | } | |
e379e5f3 L |
8478 | |
8479 | return 0; | |
8480 | } | |
8481 | ||
8482 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
8483 | ||
8484 | static int | |
79d72f45 | 8485 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8486 | { |
8487 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8488 | if (!align_branch_power | |
8489 | || now_seg == absolute_section | |
8490 | || !cpu_arch_flags.bitfield.cpui386 | |
8491 | || !(align_branch & align_branch_fused_bit)) | |
8492 | return 0; | |
8493 | ||
79d72f45 | 8494 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
8495 | { |
8496 | if (last_insn.kind == last_insn_other | |
8497 | || last_insn.seg != now_seg) | |
8498 | return 1; | |
8499 | if (flag_debug) | |
8500 | as_warn_where (last_insn.file, last_insn.line, | |
8501 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8502 | last_insn.name, i.tm.name); | |
8503 | } | |
8504 | ||
8505 | return 0; | |
8506 | } | |
8507 | ||
8508 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
8509 | ||
8510 | static int | |
8511 | add_branch_prefix_frag_p (void) | |
8512 | { | |
8513 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
8514 | to PadLock instructions since they include prefixes in opcode. */ | |
8515 | if (!align_branch_power | |
8516 | || !align_branch_prefix_size | |
8517 | || now_seg == absolute_section | |
8518 | || i.tm.cpu_flags.bitfield.cpupadlock | |
8519 | || !cpu_arch_flags.bitfield.cpui386) | |
8520 | return 0; | |
8521 | ||
8522 | /* Don't add prefix if it is a prefix or there is no operand in case | |
8523 | that segment prefix is special. */ | |
8524 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
8525 | return 0; | |
8526 | ||
8527 | if (last_insn.kind == last_insn_other | |
8528 | || last_insn.seg != now_seg) | |
8529 | return 1; | |
8530 | ||
8531 | if (flag_debug) | |
8532 | as_warn_where (last_insn.file, last_insn.line, | |
8533 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8534 | last_insn.name, i.tm.name); | |
8535 | ||
8536 | return 0; | |
8537 | } | |
8538 | ||
8539 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
8540 | ||
8541 | static int | |
79d72f45 HL |
8542 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
8543 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
8544 | { |
8545 | int add_padding; | |
8546 | ||
8547 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8548 | if (!align_branch_power | |
8549 | || now_seg == absolute_section | |
8550 | || !cpu_arch_flags.bitfield.cpui386) | |
8551 | return 0; | |
8552 | ||
8553 | add_padding = 0; | |
8554 | ||
8555 | /* Check for jcc and direct jmp. */ | |
8556 | if (i.tm.opcode_modifier.jump == JUMP) | |
8557 | { | |
8558 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
8559 | { | |
8560 | *branch_p = align_branch_jmp; | |
8561 | add_padding = align_branch & align_branch_jmp_bit; | |
8562 | } | |
8563 | else | |
8564 | { | |
79d72f45 HL |
8565 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
8566 | igore the lowest bit. */ | |
8567 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
8568 | *branch_p = align_branch_jcc; |
8569 | if ((align_branch & align_branch_jcc_bit)) | |
8570 | add_padding = 1; | |
8571 | } | |
8572 | } | |
8573 | else if (is_any_vex_encoding (&i.tm)) | |
8574 | return 0; | |
8575 | else if ((i.tm.base_opcode | 1) == 0xc3) | |
8576 | { | |
8577 | /* Near ret. */ | |
8578 | *branch_p = align_branch_ret; | |
8579 | if ((align_branch & align_branch_ret_bit)) | |
8580 | add_padding = 1; | |
8581 | } | |
8582 | else | |
8583 | { | |
8584 | /* Check for indirect jmp, direct and indirect calls. */ | |
8585 | if (i.tm.base_opcode == 0xe8) | |
8586 | { | |
8587 | /* Direct call. */ | |
8588 | *branch_p = align_branch_call; | |
8589 | if ((align_branch & align_branch_call_bit)) | |
8590 | add_padding = 1; | |
8591 | } | |
8592 | else if (i.tm.base_opcode == 0xff | |
8593 | && (i.tm.extension_opcode == 2 | |
8594 | || i.tm.extension_opcode == 4)) | |
8595 | { | |
8596 | /* Indirect call and jmp. */ | |
8597 | *branch_p = align_branch_indirect; | |
8598 | if ((align_branch & align_branch_indirect_bit)) | |
8599 | add_padding = 1; | |
8600 | } | |
8601 | ||
8602 | if (add_padding | |
8603 | && i.disp_operands | |
8604 | && tls_get_addr | |
8605 | && (i.op[0].disps->X_op == O_symbol | |
8606 | || (i.op[0].disps->X_op == O_subtract | |
8607 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
8608 | { | |
8609 | symbolS *s = i.op[0].disps->X_add_symbol; | |
8610 | /* No padding to call to global or undefined tls_get_addr. */ | |
8611 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
8612 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
8613 | return 0; | |
8614 | } | |
8615 | } | |
8616 | ||
8617 | if (add_padding | |
8618 | && last_insn.kind != last_insn_other | |
8619 | && last_insn.seg == now_seg) | |
8620 | { | |
8621 | if (flag_debug) | |
8622 | as_warn_where (last_insn.file, last_insn.line, | |
8623 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8624 | last_insn.name, i.tm.name); | |
8625 | return 0; | |
8626 | } | |
8627 | ||
8628 | return add_padding; | |
8629 | } | |
8630 | ||
29b0f896 | 8631 | static void |
e3bb37b5 | 8632 | output_insn (void) |
29b0f896 | 8633 | { |
2bbd9c25 JJ |
8634 | fragS *insn_start_frag; |
8635 | offsetT insn_start_off; | |
e379e5f3 L |
8636 | fragS *fragP = NULL; |
8637 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
8638 | /* The initializer is arbitrary just to avoid uninitialized error. |
8639 | it's actually either assigned in add_branch_padding_frag_p | |
8640 | or never be used. */ | |
8641 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 8642 | |
b4a3a7b4 L |
8643 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8644 | if (IS_ELF && x86_used_note) | |
8645 | { | |
8646 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8647 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8648 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8649 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8650 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8651 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8652 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8653 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8654 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8655 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8656 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8657 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8658 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8659 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8660 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8661 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8662 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8663 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8664 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8665 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8666 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8667 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8668 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8669 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8670 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8671 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8672 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8673 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8674 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8675 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8676 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8677 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8678 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8679 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8680 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8681 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8682 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8683 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8684 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8685 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8686 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8687 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8688 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8689 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8690 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8691 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8692 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8693 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8694 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8695 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8696 | |
8697 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8698 | || i.tm.cpu_flags.bitfield.cpu287 | |
8699 | || i.tm.cpu_flags.bitfield.cpu387 | |
8700 | || i.tm.cpu_flags.bitfield.cpu687 | |
8701 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8702 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
319ff62c JB |
8703 | if (i.has_regmmx |
8704 | || i.tm.base_opcode == 0xf77 /* emms */ | |
a7e12755 L |
8705 | || i.tm.base_opcode == 0xf0e /* femms */ |
8706 | || i.tm.base_opcode == 0xf2a /* cvtpi2ps */ | |
8707 | || i.tm.base_opcode == 0x660f2a /* cvtpi2pd */) | |
b4a3a7b4 L |
8708 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
8709 | if (i.has_regxmm) | |
8710 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8711 | if (i.has_regymm) | |
8712 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8713 | if (i.has_regzmm) | |
8714 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8715 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8716 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8717 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8718 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8719 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8720 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8721 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8722 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8723 | } | |
8724 | #endif | |
8725 | ||
29b0f896 AM |
8726 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8727 | We can't do this after the insn has been output as the current | |
8728 | frag may have been closed off. eg. by frag_var. */ | |
8729 | dwarf2_emit_insn (0); | |
8730 | ||
2bbd9c25 JJ |
8731 | insn_start_frag = frag_now; |
8732 | insn_start_off = frag_now_fix (); | |
8733 | ||
79d72f45 | 8734 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
8735 | { |
8736 | char *p; | |
8737 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
8738 | unsigned int max_branch_padding_size = 14; | |
8739 | ||
8740 | /* Align section to boundary. */ | |
8741 | record_alignment (now_seg, align_branch_power); | |
8742 | ||
8743 | /* Make room for padding. */ | |
8744 | frag_grow (max_branch_padding_size); | |
8745 | ||
8746 | /* Start of the padding. */ | |
8747 | p = frag_more (0); | |
8748 | ||
8749 | fragP = frag_now; | |
8750 | ||
8751 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
8752 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
8753 | NULL, 0, p); | |
8754 | ||
79d72f45 | 8755 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
8756 | fragP->tc_frag_data.branch_type = branch; |
8757 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
8758 | } | |
8759 | ||
29b0f896 | 8760 | /* Output jumps. */ |
0cfa3eb3 | 8761 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 8762 | output_branch (); |
0cfa3eb3 JB |
8763 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
8764 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 8765 | output_jump (); |
0cfa3eb3 | 8766 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
8767 | output_interseg_jump (); |
8768 | else | |
8769 | { | |
8770 | /* Output normal instructions here. */ | |
8771 | char *p; | |
8772 | unsigned char *q; | |
47465058 | 8773 | unsigned int j; |
331d2d0d | 8774 | unsigned int prefix; |
79d72f45 | 8775 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 8776 | |
e4e00185 | 8777 | if (avoid_fence |
c3949f43 JB |
8778 | && (i.tm.base_opcode == 0xfaee8 |
8779 | || i.tm.base_opcode == 0xfaef0 | |
8780 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
8781 | { |
8782 | /* Encode lfence, mfence, and sfence as | |
8783 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8784 | offsetT val = 0x240483f0ULL; | |
8785 | p = frag_more (5); | |
8786 | md_number_to_chars (p, val, 5); | |
8787 | return; | |
8788 | } | |
8789 | ||
d022bddd IT |
8790 | /* Some processors fail on LOCK prefix. This options makes |
8791 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8792 | if (omit_lock_prefix) | |
8793 | { | |
8794 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8795 | return; | |
8796 | i.prefix[LOCK_PREFIX] = 0; | |
8797 | } | |
8798 | ||
e379e5f3 L |
8799 | if (branch) |
8800 | /* Skip if this is a branch. */ | |
8801 | ; | |
79d72f45 | 8802 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
8803 | { |
8804 | /* Make room for padding. */ | |
8805 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
8806 | p = frag_more (0); | |
8807 | ||
8808 | fragP = frag_now; | |
8809 | ||
8810 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
8811 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
8812 | NULL, 0, p); | |
8813 | ||
79d72f45 | 8814 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
8815 | fragP->tc_frag_data.branch_type = align_branch_fused; |
8816 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
8817 | } | |
8818 | else if (add_branch_prefix_frag_p ()) | |
8819 | { | |
8820 | unsigned int max_prefix_size = align_branch_prefix_size; | |
8821 | ||
8822 | /* Make room for padding. */ | |
8823 | frag_grow (max_prefix_size); | |
8824 | p = frag_more (0); | |
8825 | ||
8826 | fragP = frag_now; | |
8827 | ||
8828 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
8829 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
8830 | NULL, 0, p); | |
8831 | ||
8832 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
8833 | } | |
8834 | ||
43234a1e L |
8835 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8836 | don't need the explicit prefix. */ | |
8837 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8838 | { |
c0f3af97 | 8839 | switch (i.tm.opcode_length) |
bc4bd9ab | 8840 | { |
c0f3af97 L |
8841 | case 3: |
8842 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8843 | { |
c0f3af97 | 8844 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
8845 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8846 | || prefix != REPE_PREFIX_OPCODE | |
8847 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
8848 | add_prefix (prefix); | |
c0f3af97 L |
8849 | } |
8850 | break; | |
8851 | case 2: | |
8852 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8853 | { | |
8854 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 8855 | add_prefix (prefix); |
4dffcebc | 8856 | } |
c0f3af97 L |
8857 | break; |
8858 | case 1: | |
8859 | break; | |
390c91cf L |
8860 | case 0: |
8861 | /* Check for pseudo prefixes. */ | |
8862 | as_bad_where (insn_start_frag->fr_file, | |
8863 | insn_start_frag->fr_line, | |
8864 | _("pseudo prefix without instruction")); | |
8865 | return; | |
c0f3af97 L |
8866 | default: |
8867 | abort (); | |
bc4bd9ab | 8868 | } |
c0f3af97 | 8869 | |
6d19a37a | 8870 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8871 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8872 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
8873 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
8874 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
8875 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
8876 | if (x86_elf_abi == X86_64_X32_ABI |
8877 | && i.operands == 2 | |
14470f07 L |
8878 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
8879 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
8880 | && i.prefix[REX_PREFIX] == 0) |
8881 | add_prefix (REX_OPCODE); | |
6d19a37a | 8882 | #endif |
cf61b747 | 8883 | |
c0f3af97 L |
8884 | /* The prefix bytes. */ |
8885 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8886 | if (*q) | |
8887 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8888 | } |
ae5c1c7b | 8889 | else |
c0f3af97 L |
8890 | { |
8891 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8892 | if (*q) | |
8893 | switch (j) | |
8894 | { | |
8895 | case REX_PREFIX: | |
8896 | /* REX byte is encoded in VEX prefix. */ | |
8897 | break; | |
8898 | case SEG_PREFIX: | |
8899 | case ADDR_PREFIX: | |
8900 | FRAG_APPEND_1_CHAR (*q); | |
8901 | break; | |
8902 | default: | |
8903 | /* There should be no other prefixes for instructions | |
8904 | with VEX prefix. */ | |
8905 | abort (); | |
8906 | } | |
8907 | ||
43234a1e L |
8908 | /* For EVEX instructions i.vrex should become 0 after |
8909 | build_evex_prefix. For VEX instructions upper 16 registers | |
8910 | aren't available, so VREX should be 0. */ | |
8911 | if (i.vrex) | |
8912 | abort (); | |
c0f3af97 L |
8913 | /* Now the VEX prefix. */ |
8914 | p = frag_more (i.vex.length); | |
8915 | for (j = 0; j < i.vex.length; j++) | |
8916 | p[j] = i.vex.bytes[j]; | |
8917 | } | |
252b5132 | 8918 | |
29b0f896 | 8919 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8920 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8921 | { |
8922 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8923 | } | |
8924 | else | |
8925 | { | |
4dffcebc | 8926 | switch (i.tm.opcode_length) |
331d2d0d | 8927 | { |
43234a1e L |
8928 | case 4: |
8929 | p = frag_more (4); | |
8930 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8931 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8932 | break; | |
4dffcebc | 8933 | case 3: |
331d2d0d L |
8934 | p = frag_more (3); |
8935 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8936 | break; |
8937 | case 2: | |
8938 | p = frag_more (2); | |
8939 | break; | |
8940 | default: | |
8941 | abort (); | |
8942 | break; | |
331d2d0d | 8943 | } |
0f10071e | 8944 | |
29b0f896 AM |
8945 | /* Put out high byte first: can't use md_number_to_chars! */ |
8946 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8947 | *p = i.tm.base_opcode & 0xff; | |
8948 | } | |
3e73aa7c | 8949 | |
29b0f896 | 8950 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8951 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8952 | { |
4a3523fa L |
8953 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8954 | | i.rm.reg << 3 | |
8955 | | i.rm.mode << 6)); | |
29b0f896 AM |
8956 | /* If i.rm.regmem == ESP (4) |
8957 | && i.rm.mode != (Register mode) | |
8958 | && not 16 bit | |
8959 | ==> need second modrm byte. */ | |
8960 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8961 | && i.rm.mode != 3 | |
dc821c5f | 8962 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8963 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8964 | | i.sib.index << 3 | |
8965 | | i.sib.scale << 6)); | |
29b0f896 | 8966 | } |
3e73aa7c | 8967 | |
29b0f896 | 8968 | if (i.disp_operands) |
2bbd9c25 | 8969 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8970 | |
29b0f896 | 8971 | if (i.imm_operands) |
2bbd9c25 | 8972 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
8973 | |
8974 | /* | |
8975 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
8976 | * absolute section, and abs_section_offset not getting updated as data | |
8977 | * gets added to the frag breaks the logic below. | |
8978 | */ | |
8979 | if (now_seg != absolute_section) | |
8980 | { | |
8981 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
8982 | if (j > 15) | |
8983 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
8984 | j); | |
e379e5f3 L |
8985 | else if (fragP) |
8986 | { | |
8987 | /* NB: Don't add prefix with GOTPC relocation since | |
8988 | output_disp() above depends on the fixed encoding | |
8989 | length. Can't add prefix with TLS relocation since | |
8990 | it breaks TLS linker optimization. */ | |
8991 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
8992 | /* Prefix count on the current instruction. */ | |
8993 | unsigned int count = i.vex.length; | |
8994 | unsigned int k; | |
8995 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
8996 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
8997 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
8998 | count++; | |
8999 | ||
9000 | /* Count prefixes for extended opcode maps. */ | |
9001 | if (!i.vex.length) | |
9002 | switch (i.tm.opcode_length) | |
9003 | { | |
9004 | case 3: | |
9005 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) | |
9006 | { | |
9007 | count++; | |
9008 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
9009 | { | |
9010 | case 0x38: | |
9011 | case 0x3a: | |
9012 | count++; | |
9013 | break; | |
9014 | default: | |
9015 | break; | |
9016 | } | |
9017 | } | |
9018 | break; | |
9019 | case 2: | |
9020 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) | |
9021 | count++; | |
9022 | break; | |
9023 | case 1: | |
9024 | break; | |
9025 | default: | |
9026 | abort (); | |
9027 | } | |
9028 | ||
9029 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9030 | == BRANCH_PREFIX) | |
9031 | { | |
9032 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9033 | frag. */ | |
9034 | if (fragP->tc_frag_data.max_bytes > max) | |
9035 | fragP->tc_frag_data.max_bytes = max; | |
9036 | if (fragP->tc_frag_data.max_bytes > count) | |
9037 | fragP->tc_frag_data.max_bytes -= count; | |
9038 | else | |
9039 | fragP->tc_frag_data.max_bytes = 0; | |
9040 | } | |
9041 | else | |
9042 | { | |
9043 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9044 | frag. */ | |
9045 | unsigned int max_prefix_size; | |
9046 | if (align_branch_prefix_size > max) | |
9047 | max_prefix_size = max; | |
9048 | else | |
9049 | max_prefix_size = align_branch_prefix_size; | |
9050 | if (max_prefix_size > count) | |
9051 | fragP->tc_frag_data.max_prefix_length | |
9052 | = max_prefix_size - count; | |
9053 | } | |
9054 | ||
9055 | /* Use existing segment prefix if possible. Use CS | |
9056 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9057 | segment prefix with ESP/EBP base register and use DS | |
9058 | segment prefix without ESP/EBP base register. */ | |
9059 | if (i.prefix[SEG_PREFIX]) | |
9060 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9061 | else if (flag_code == CODE_64BIT) | |
9062 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9063 | else if (i.base_reg | |
9064 | && (i.base_reg->reg_num == 4 | |
9065 | || i.base_reg->reg_num == 5)) | |
9066 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9067 | else | |
9068 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9069 | } | |
9c33702b | 9070 | } |
29b0f896 | 9071 | } |
252b5132 | 9072 | |
e379e5f3 L |
9073 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9074 | if (align_branch_power | |
9075 | && now_seg != absolute_section | |
9076 | && cpu_arch_flags.bitfield.cpui386) | |
9077 | { | |
9078 | /* Terminate each frag so that we can add prefix and check for | |
9079 | fused jcc. */ | |
9080 | frag_wane (frag_now); | |
9081 | frag_new (0); | |
9082 | } | |
9083 | ||
29b0f896 AM |
9084 | #ifdef DEBUG386 |
9085 | if (flag_debug) | |
9086 | { | |
7b81dfbb | 9087 | pi ("" /*line*/, &i); |
29b0f896 AM |
9088 | } |
9089 | #endif /* DEBUG386 */ | |
9090 | } | |
252b5132 | 9091 | |
e205caa7 L |
9092 | /* Return the size of the displacement operand N. */ |
9093 | ||
9094 | static int | |
9095 | disp_size (unsigned int n) | |
9096 | { | |
9097 | int size = 4; | |
43234a1e | 9098 | |
b5014f7a | 9099 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9100 | size = 8; |
9101 | else if (i.types[n].bitfield.disp8) | |
9102 | size = 1; | |
9103 | else if (i.types[n].bitfield.disp16) | |
9104 | size = 2; | |
e205caa7 L |
9105 | return size; |
9106 | } | |
9107 | ||
9108 | /* Return the size of the immediate operand N. */ | |
9109 | ||
9110 | static int | |
9111 | imm_size (unsigned int n) | |
9112 | { | |
9113 | int size = 4; | |
40fb9820 L |
9114 | if (i.types[n].bitfield.imm64) |
9115 | size = 8; | |
9116 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9117 | size = 1; | |
9118 | else if (i.types[n].bitfield.imm16) | |
9119 | size = 2; | |
e205caa7 L |
9120 | return size; |
9121 | } | |
9122 | ||
29b0f896 | 9123 | static void |
64e74474 | 9124 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9125 | { |
9126 | char *p; | |
9127 | unsigned int n; | |
252b5132 | 9128 | |
29b0f896 AM |
9129 | for (n = 0; n < i.operands; n++) |
9130 | { | |
b5014f7a | 9131 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
9132 | { |
9133 | if (i.op[n].disps->X_op == O_constant) | |
9134 | { | |
e205caa7 | 9135 | int size = disp_size (n); |
43234a1e | 9136 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9137 | |
629cfaf1 JB |
9138 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9139 | size); | |
29b0f896 AM |
9140 | p = frag_more (size); |
9141 | md_number_to_chars (p, val, size); | |
9142 | } | |
9143 | else | |
9144 | { | |
f86103b7 | 9145 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 9146 | int size = disp_size (n); |
40fb9820 | 9147 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9148 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9149 | fixS *fixP; |
29b0f896 | 9150 | |
e205caa7 | 9151 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9152 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9153 | |
29b0f896 AM |
9154 | /* The PC relative address is computed relative |
9155 | to the instruction boundary, so in case immediate | |
9156 | fields follows, we need to adjust the value. */ | |
9157 | if (pcrel && i.imm_operands) | |
9158 | { | |
29b0f896 | 9159 | unsigned int n1; |
e205caa7 | 9160 | int sz = 0; |
252b5132 | 9161 | |
29b0f896 | 9162 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9163 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9164 | { |
e205caa7 L |
9165 | /* Only one immediate is allowed for PC |
9166 | relative address. */ | |
9c2799c2 | 9167 | gas_assert (sz == 0); |
e205caa7 L |
9168 | sz = imm_size (n1); |
9169 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9170 | } |
29b0f896 | 9171 | /* We should find the immediate. */ |
9c2799c2 | 9172 | gas_assert (sz != 0); |
29b0f896 | 9173 | } |
520dc8e8 | 9174 | |
29b0f896 | 9175 | p = frag_more (size); |
d258b828 | 9176 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9177 | if (GOT_symbol |
2bbd9c25 | 9178 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9179 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9180 | || reloc_type == BFD_RELOC_X86_64_32S |
9181 | || (reloc_type == BFD_RELOC_64 | |
9182 | && object_64bit)) | |
d6ab8113 JB |
9183 | && (i.op[n].disps->X_op == O_symbol |
9184 | || (i.op[n].disps->X_op == O_add | |
9185 | && ((symbol_get_value_expression | |
9186 | (i.op[n].disps->X_op_symbol)->X_op) | |
9187 | == O_subtract)))) | |
9188 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9189 | { |
4fa24527 | 9190 | if (!object_64bit) |
7b81dfbb AJ |
9191 | { |
9192 | reloc_type = BFD_RELOC_386_GOTPC; | |
e379e5f3 | 9193 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9194 | i.op[n].imms->X_add_number += |
9195 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
9196 | } |
9197 | else if (reloc_type == BFD_RELOC_64) | |
9198 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 9199 | else |
7b81dfbb AJ |
9200 | /* Don't do the adjustment for x86-64, as there |
9201 | the pcrel addressing is relative to the _next_ | |
9202 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 9203 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 9204 | } |
e379e5f3 L |
9205 | else if (align_branch_power) |
9206 | { | |
9207 | switch (reloc_type) | |
9208 | { | |
9209 | case BFD_RELOC_386_TLS_GD: | |
9210 | case BFD_RELOC_386_TLS_LDM: | |
9211 | case BFD_RELOC_386_TLS_IE: | |
9212 | case BFD_RELOC_386_TLS_IE_32: | |
9213 | case BFD_RELOC_386_TLS_GOTIE: | |
9214 | case BFD_RELOC_386_TLS_GOTDESC: | |
9215 | case BFD_RELOC_386_TLS_DESC_CALL: | |
9216 | case BFD_RELOC_X86_64_TLSGD: | |
9217 | case BFD_RELOC_X86_64_TLSLD: | |
9218 | case BFD_RELOC_X86_64_GOTTPOFF: | |
9219 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
9220 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9221 | i.has_gotpc_tls_reloc = TRUE; | |
9222 | default: | |
9223 | break; | |
9224 | } | |
9225 | } | |
02a86693 L |
9226 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
9227 | size, i.op[n].disps, pcrel, | |
9228 | reloc_type); | |
9229 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
9230 | "test %reg, mem" and "binop mem, %reg" where binop | |
9231 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
9232 | instructions without data prefix. Always generate |
9233 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
9234 | if (i.prefix[DATA_PREFIX] == 0 | |
9235 | && (generate_relax_relocations | |
9236 | || (!object_64bit | |
9237 | && i.rm.mode == 0 | |
9238 | && i.rm.regmem == 5)) | |
0cb4071e L |
9239 | && (i.rm.mode == 2 |
9240 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
2ae4c703 | 9241 | && !is_any_vex_encoding(&i.tm) |
02a86693 L |
9242 | && ((i.operands == 1 |
9243 | && i.tm.base_opcode == 0xff | |
9244 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
9245 | || (i.operands == 2 | |
9246 | && (i.tm.base_opcode == 0x8b | |
9247 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 9248 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
9249 | { |
9250 | if (object_64bit) | |
9251 | { | |
9252 | fixP->fx_tcbit = i.rex != 0; | |
9253 | if (i.base_reg | |
e968fc9b | 9254 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
9255 | fixP->fx_tcbit2 = 1; |
9256 | } | |
9257 | else | |
9258 | fixP->fx_tcbit2 = 1; | |
9259 | } | |
29b0f896 AM |
9260 | } |
9261 | } | |
9262 | } | |
9263 | } | |
252b5132 | 9264 | |
29b0f896 | 9265 | static void |
64e74474 | 9266 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9267 | { |
9268 | char *p; | |
9269 | unsigned int n; | |
252b5132 | 9270 | |
29b0f896 AM |
9271 | for (n = 0; n < i.operands; n++) |
9272 | { | |
43234a1e L |
9273 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
9274 | if (i.rounding && (int) n == i.rounding->operand) | |
9275 | continue; | |
9276 | ||
40fb9820 | 9277 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
9278 | { |
9279 | if (i.op[n].imms->X_op == O_constant) | |
9280 | { | |
e205caa7 | 9281 | int size = imm_size (n); |
29b0f896 | 9282 | offsetT val; |
b4cac588 | 9283 | |
29b0f896 AM |
9284 | val = offset_in_range (i.op[n].imms->X_add_number, |
9285 | size); | |
9286 | p = frag_more (size); | |
9287 | md_number_to_chars (p, val, size); | |
9288 | } | |
9289 | else | |
9290 | { | |
9291 | /* Not absolute_section. | |
9292 | Need a 32-bit fixup (don't support 8bit | |
9293 | non-absolute imms). Try to support other | |
9294 | sizes ... */ | |
f86103b7 | 9295 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
9296 | int size = imm_size (n); |
9297 | int sign; | |
29b0f896 | 9298 | |
40fb9820 | 9299 | if (i.types[n].bitfield.imm32s |
a7d61044 | 9300 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 9301 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 9302 | sign = 1; |
e205caa7 L |
9303 | else |
9304 | sign = 0; | |
520dc8e8 | 9305 | |
29b0f896 | 9306 | p = frag_more (size); |
d258b828 | 9307 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 9308 | |
2bbd9c25 JJ |
9309 | /* This is tough to explain. We end up with this one if we |
9310 | * have operands that look like | |
9311 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
9312 | * obtain the absolute address of the GOT, and it is strongly | |
9313 | * preferable from a performance point of view to avoid using | |
9314 | * a runtime relocation for this. The actual sequence of | |
9315 | * instructions often look something like: | |
9316 | * | |
9317 | * call .L66 | |
9318 | * .L66: | |
9319 | * popl %ebx | |
9320 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
9321 | * | |
9322 | * The call and pop essentially return the absolute address | |
9323 | * of the label .L66 and store it in %ebx. The linker itself | |
9324 | * will ultimately change the first operand of the addl so | |
9325 | * that %ebx points to the GOT, but to keep things simple, the | |
9326 | * .o file must have this operand set so that it generates not | |
9327 | * the absolute address of .L66, but the absolute address of | |
9328 | * itself. This allows the linker itself simply treat a GOTPC | |
9329 | * relocation as asking for a pcrel offset to the GOT to be | |
9330 | * added in, and the addend of the relocation is stored in the | |
9331 | * operand field for the instruction itself. | |
9332 | * | |
9333 | * Our job here is to fix the operand so that it would add | |
9334 | * the correct offset so that %ebx would point to itself. The | |
9335 | * thing that is tricky is that .-.L66 will point to the | |
9336 | * beginning of the instruction, so we need to further modify | |
9337 | * the operand so that it will point to itself. There are | |
9338 | * other cases where you have something like: | |
9339 | * | |
9340 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
9341 | * | |
9342 | * and here no correction would be required. Internally in | |
9343 | * the assembler we treat operands of this form as not being | |
9344 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
9345 | * whether it would simplify matters to do it this way. Who | |
9346 | * knows. In earlier versions of the PIC patches, the | |
9347 | * pcrel_adjust field was used to store the correction, but | |
9348 | * since the expression is not pcrel, I felt it would be | |
9349 | * confusing to do it this way. */ | |
9350 | ||
d6ab8113 | 9351 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9352 | || reloc_type == BFD_RELOC_X86_64_32S |
9353 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
9354 | && GOT_symbol |
9355 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
9356 | && (i.op[n].imms->X_op == O_symbol | |
9357 | || (i.op[n].imms->X_op == O_add | |
9358 | && ((symbol_get_value_expression | |
9359 | (i.op[n].imms->X_op_symbol)->X_op) | |
9360 | == O_subtract)))) | |
9361 | { | |
4fa24527 | 9362 | if (!object_64bit) |
d6ab8113 | 9363 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 9364 | else if (size == 4) |
d6ab8113 | 9365 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
9366 | else if (size == 8) |
9367 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
e379e5f3 | 9368 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9369 | i.op[n].imms->X_add_number += |
9370 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 9371 | } |
29b0f896 AM |
9372 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
9373 | i.op[n].imms, 0, reloc_type); | |
9374 | } | |
9375 | } | |
9376 | } | |
252b5132 RH |
9377 | } |
9378 | \f | |
d182319b JB |
9379 | /* x86_cons_fix_new is called via the expression parsing code when a |
9380 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
9381 | static int cons_sign = -1; |
9382 | ||
9383 | void | |
e3bb37b5 | 9384 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 9385 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 9386 | { |
d258b828 | 9387 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
9388 | |
9389 | #ifdef TE_PE | |
9390 | if (exp->X_op == O_secrel) | |
9391 | { | |
9392 | exp->X_op = O_symbol; | |
9393 | r = BFD_RELOC_32_SECREL; | |
9394 | } | |
9395 | #endif | |
9396 | ||
9397 | fix_new_exp (frag, off, len, exp, 0, r); | |
9398 | } | |
9399 | ||
357d1bd8 L |
9400 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
9401 | purpose of the `.dc.a' internal pseudo-op. */ | |
9402 | ||
9403 | int | |
9404 | x86_address_bytes (void) | |
9405 | { | |
9406 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
9407 | return 4; | |
9408 | return stdoutput->arch_info->bits_per_address / 8; | |
9409 | } | |
9410 | ||
d382c579 TG |
9411 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
9412 | || defined (LEX_AT) | |
d258b828 | 9413 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 9414 | #else |
f3c180ae AM |
9415 | /* Parse operands of the form |
9416 | <symbol>@GOTOFF+<nnn> | |
9417 | and similar .plt or .got references. | |
9418 | ||
9419 | If we find one, set up the correct relocation in RELOC and copy the | |
9420 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
9421 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9422 | is non-null set it to the length of the string we removed from the | |
9423 | input line. Otherwise return NULL. */ | |
9424 | static char * | |
91d6fa6a | 9425 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 9426 | int *adjust, |
d258b828 | 9427 | i386_operand_type *types) |
f3c180ae | 9428 | { |
7b81dfbb AJ |
9429 | /* Some of the relocations depend on the size of what field is to |
9430 | be relocated. But in our callers i386_immediate and i386_displacement | |
9431 | we don't yet know the operand size (this will be set by insn | |
9432 | matching). Hence we record the word32 relocation here, | |
9433 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
9434 | static const struct { |
9435 | const char *str; | |
cff8d58a | 9436 | int len; |
4fa24527 | 9437 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 9438 | const i386_operand_type types64; |
f3c180ae | 9439 | } gotrel[] = { |
8ce3d284 | 9440 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
9441 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
9442 | BFD_RELOC_SIZE32 }, | |
9443 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 9444 | #endif |
cff8d58a L |
9445 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
9446 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 9447 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
9448 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
9449 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 9450 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9451 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
9452 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 9453 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9454 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
9455 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 9456 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9457 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
9458 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 9459 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9460 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
9461 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 9462 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9463 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
9464 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9465 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9466 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
9467 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 9468 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9469 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
9470 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 9471 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9472 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
9473 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 9474 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9475 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
9476 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9477 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9478 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
9479 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 9480 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9481 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
9482 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9483 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9484 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
9485 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9486 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9487 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
9488 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 9489 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
9490 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
9491 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 9492 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9493 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
9494 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 9495 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
9496 | }; |
9497 | char *cp; | |
9498 | unsigned int j; | |
9499 | ||
d382c579 | 9500 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
9501 | if (!IS_ELF) |
9502 | return NULL; | |
d382c579 | 9503 | #endif |
718ddfc0 | 9504 | |
f3c180ae | 9505 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 9506 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
9507 | return NULL; |
9508 | ||
47465058 | 9509 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 9510 | { |
cff8d58a | 9511 | int len = gotrel[j].len; |
28f81592 | 9512 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 9513 | { |
4fa24527 | 9514 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 9515 | { |
28f81592 AM |
9516 | int first, second; |
9517 | char *tmpbuf, *past_reloc; | |
f3c180ae | 9518 | |
91d6fa6a | 9519 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 9520 | |
3956db08 JB |
9521 | if (types) |
9522 | { | |
9523 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
9524 | { |
9525 | types->bitfield.imm32 = 1; | |
9526 | types->bitfield.disp32 = 1; | |
9527 | } | |
3956db08 JB |
9528 | else |
9529 | *types = gotrel[j].types64; | |
9530 | } | |
9531 | ||
8fd4256d | 9532 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
9533 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
9534 | ||
28f81592 | 9535 | /* The length of the first part of our input line. */ |
f3c180ae | 9536 | first = cp - input_line_pointer; |
28f81592 AM |
9537 | |
9538 | /* The second part goes from after the reloc token until | |
67c11a9b | 9539 | (and including) an end_of_line char or comma. */ |
28f81592 | 9540 | past_reloc = cp + 1 + len; |
67c11a9b AM |
9541 | cp = past_reloc; |
9542 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9543 | ++cp; | |
9544 | second = cp + 1 - past_reloc; | |
28f81592 AM |
9545 | |
9546 | /* Allocate and copy string. The trailing NUL shouldn't | |
9547 | be necessary, but be safe. */ | |
add39d23 | 9548 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 9549 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
9550 | if (second != 0 && *past_reloc != ' ') |
9551 | /* Replace the relocation token with ' ', so that | |
9552 | errors like foo@GOTOFF1 will be detected. */ | |
9553 | tmpbuf[first++] = ' '; | |
af89796a L |
9554 | else |
9555 | /* Increment length by 1 if the relocation token is | |
9556 | removed. */ | |
9557 | len++; | |
9558 | if (adjust) | |
9559 | *adjust = len; | |
0787a12d AM |
9560 | memcpy (tmpbuf + first, past_reloc, second); |
9561 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
9562 | return tmpbuf; |
9563 | } | |
9564 | ||
4fa24527 JB |
9565 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
9566 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
9567 | return NULL; |
9568 | } | |
9569 | } | |
9570 | ||
9571 | /* Might be a symbol version string. Don't as_bad here. */ | |
9572 | return NULL; | |
9573 | } | |
4e4f7c87 | 9574 | #endif |
f3c180ae | 9575 | |
a988325c NC |
9576 | #ifdef TE_PE |
9577 | #ifdef lex_got | |
9578 | #undef lex_got | |
9579 | #endif | |
9580 | /* Parse operands of the form | |
9581 | <symbol>@SECREL32+<nnn> | |
9582 | ||
9583 | If we find one, set up the correct relocation in RELOC and copy the | |
9584 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
9585 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9586 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
9587 | input line. Otherwise return NULL. |
9588 | ||
a988325c NC |
9589 | This function is copied from the ELF version above adjusted for PE targets. */ |
9590 | ||
9591 | static char * | |
9592 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
9593 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 9594 | i386_operand_type *types) |
a988325c NC |
9595 | { |
9596 | static const struct | |
9597 | { | |
9598 | const char *str; | |
9599 | int len; | |
9600 | const enum bfd_reloc_code_real rel[2]; | |
9601 | const i386_operand_type types64; | |
9602 | } | |
9603 | gotrel[] = | |
9604 | { | |
9605 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
9606 | BFD_RELOC_32_SECREL }, | |
9607 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
9608 | }; | |
9609 | ||
9610 | char *cp; | |
9611 | unsigned j; | |
9612 | ||
9613 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
9614 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
9615 | return NULL; | |
9616 | ||
9617 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
9618 | { | |
9619 | int len = gotrel[j].len; | |
9620 | ||
9621 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
9622 | { | |
9623 | if (gotrel[j].rel[object_64bit] != 0) | |
9624 | { | |
9625 | int first, second; | |
9626 | char *tmpbuf, *past_reloc; | |
9627 | ||
9628 | *rel = gotrel[j].rel[object_64bit]; | |
9629 | if (adjust) | |
9630 | *adjust = len; | |
9631 | ||
9632 | if (types) | |
9633 | { | |
9634 | if (flag_code != CODE_64BIT) | |
9635 | { | |
9636 | types->bitfield.imm32 = 1; | |
9637 | types->bitfield.disp32 = 1; | |
9638 | } | |
9639 | else | |
9640 | *types = gotrel[j].types64; | |
9641 | } | |
9642 | ||
9643 | /* The length of the first part of our input line. */ | |
9644 | first = cp - input_line_pointer; | |
9645 | ||
9646 | /* The second part goes from after the reloc token until | |
9647 | (and including) an end_of_line char or comma. */ | |
9648 | past_reloc = cp + 1 + len; | |
9649 | cp = past_reloc; | |
9650 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9651 | ++cp; | |
9652 | second = cp + 1 - past_reloc; | |
9653 | ||
9654 | /* Allocate and copy string. The trailing NUL shouldn't | |
9655 | be necessary, but be safe. */ | |
add39d23 | 9656 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
9657 | memcpy (tmpbuf, input_line_pointer, first); |
9658 | if (second != 0 && *past_reloc != ' ') | |
9659 | /* Replace the relocation token with ' ', so that | |
9660 | errors like foo@SECLREL321 will be detected. */ | |
9661 | tmpbuf[first++] = ' '; | |
9662 | memcpy (tmpbuf + first, past_reloc, second); | |
9663 | tmpbuf[first + second] = '\0'; | |
9664 | return tmpbuf; | |
9665 | } | |
9666 | ||
9667 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
9668 | gotrel[j].str, 1 << (5 + object_64bit)); | |
9669 | return NULL; | |
9670 | } | |
9671 | } | |
9672 | ||
9673 | /* Might be a symbol version string. Don't as_bad here. */ | |
9674 | return NULL; | |
9675 | } | |
9676 | ||
9677 | #endif /* TE_PE */ | |
9678 | ||
62ebcb5c | 9679 | bfd_reloc_code_real_type |
e3bb37b5 | 9680 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9681 | { |
62ebcb5c AM |
9682 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9683 | ||
ee86248c JB |
9684 | intel_syntax = -intel_syntax; |
9685 | ||
3c7b9c2c | 9686 | exp->X_md = 0; |
4fa24527 | 9687 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9688 | { |
9689 | /* Handle @GOTOFF and the like in an expression. */ | |
9690 | char *save; | |
9691 | char *gotfree_input_line; | |
4a57f2cf | 9692 | int adjust = 0; |
f3c180ae AM |
9693 | |
9694 | save = input_line_pointer; | |
d258b828 | 9695 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9696 | if (gotfree_input_line) |
9697 | input_line_pointer = gotfree_input_line; | |
9698 | ||
9699 | expression (exp); | |
9700 | ||
9701 | if (gotfree_input_line) | |
9702 | { | |
9703 | /* expression () has merrily parsed up to the end of line, | |
9704 | or a comma - in the wrong buffer. Transfer how far | |
9705 | input_line_pointer has moved to the right buffer. */ | |
9706 | input_line_pointer = (save | |
9707 | + (input_line_pointer - gotfree_input_line) | |
9708 | + adjust); | |
9709 | free (gotfree_input_line); | |
3992d3b7 AM |
9710 | if (exp->X_op == O_constant |
9711 | || exp->X_op == O_absent | |
9712 | || exp->X_op == O_illegal | |
0398aac5 | 9713 | || exp->X_op == O_register |
3992d3b7 AM |
9714 | || exp->X_op == O_big) |
9715 | { | |
9716 | char c = *input_line_pointer; | |
9717 | *input_line_pointer = 0; | |
9718 | as_bad (_("missing or invalid expression `%s'"), save); | |
9719 | *input_line_pointer = c; | |
9720 | } | |
b9519cfe L |
9721 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9722 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9723 | && exp->X_op != O_symbol) | |
9724 | { | |
9725 | char c = *input_line_pointer; | |
9726 | *input_line_pointer = 0; | |
9727 | as_bad (_("invalid PLT expression `%s'"), save); | |
9728 | *input_line_pointer = c; | |
9729 | } | |
f3c180ae AM |
9730 | } |
9731 | } | |
9732 | else | |
9733 | expression (exp); | |
ee86248c JB |
9734 | |
9735 | intel_syntax = -intel_syntax; | |
9736 | ||
9737 | if (intel_syntax) | |
9738 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9739 | |
9740 | return got_reloc; | |
f3c180ae | 9741 | } |
f3c180ae | 9742 | |
9f32dd5b L |
9743 | static void |
9744 | signed_cons (int size) | |
6482c264 | 9745 | { |
d182319b JB |
9746 | if (flag_code == CODE_64BIT) |
9747 | cons_sign = 1; | |
9748 | cons (size); | |
9749 | cons_sign = -1; | |
6482c264 NC |
9750 | } |
9751 | ||
d182319b | 9752 | #ifdef TE_PE |
6482c264 | 9753 | static void |
7016a5d5 | 9754 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9755 | { |
9756 | expressionS exp; | |
9757 | ||
9758 | do | |
9759 | { | |
9760 | expression (&exp); | |
9761 | if (exp.X_op == O_symbol) | |
9762 | exp.X_op = O_secrel; | |
9763 | ||
9764 | emit_expr (&exp, 4); | |
9765 | } | |
9766 | while (*input_line_pointer++ == ','); | |
9767 | ||
9768 | input_line_pointer--; | |
9769 | demand_empty_rest_of_line (); | |
9770 | } | |
6482c264 NC |
9771 | #endif |
9772 | ||
43234a1e L |
9773 | /* Handle Vector operations. */ |
9774 | ||
9775 | static char * | |
9776 | check_VecOperations (char *op_string, char *op_end) | |
9777 | { | |
9778 | const reg_entry *mask; | |
9779 | const char *saved; | |
9780 | char *end_op; | |
9781 | ||
9782 | while (*op_string | |
9783 | && (op_end == NULL || op_string < op_end)) | |
9784 | { | |
9785 | saved = op_string; | |
9786 | if (*op_string == '{') | |
9787 | { | |
9788 | op_string++; | |
9789 | ||
9790 | /* Check broadcasts. */ | |
9791 | if (strncmp (op_string, "1to", 3) == 0) | |
9792 | { | |
9793 | int bcst_type; | |
9794 | ||
9795 | if (i.broadcast) | |
9796 | goto duplicated_vec_op; | |
9797 | ||
9798 | op_string += 3; | |
9799 | if (*op_string == '8') | |
8e6e0792 | 9800 | bcst_type = 8; |
b28d1bda | 9801 | else if (*op_string == '4') |
8e6e0792 | 9802 | bcst_type = 4; |
b28d1bda | 9803 | else if (*op_string == '2') |
8e6e0792 | 9804 | bcst_type = 2; |
43234a1e L |
9805 | else if (*op_string == '1' |
9806 | && *(op_string+1) == '6') | |
9807 | { | |
8e6e0792 | 9808 | bcst_type = 16; |
43234a1e L |
9809 | op_string++; |
9810 | } | |
9811 | else | |
9812 | { | |
9813 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9814 | return NULL; | |
9815 | } | |
9816 | op_string++; | |
9817 | ||
9818 | broadcast_op.type = bcst_type; | |
9819 | broadcast_op.operand = this_operand; | |
1f75763a | 9820 | broadcast_op.bytes = 0; |
43234a1e L |
9821 | i.broadcast = &broadcast_op; |
9822 | } | |
9823 | /* Check masking operation. */ | |
9824 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9825 | { | |
9826 | /* k0 can't be used for write mask. */ | |
f74a6307 | 9827 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 9828 | { |
6d2cd6b2 JB |
9829 | as_bad (_("`%s%s' can't be used for write mask"), |
9830 | register_prefix, mask->reg_name); | |
43234a1e L |
9831 | return NULL; |
9832 | } | |
9833 | ||
9834 | if (!i.mask) | |
9835 | { | |
9836 | mask_op.mask = mask; | |
9837 | mask_op.zeroing = 0; | |
9838 | mask_op.operand = this_operand; | |
9839 | i.mask = &mask_op; | |
9840 | } | |
9841 | else | |
9842 | { | |
9843 | if (i.mask->mask) | |
9844 | goto duplicated_vec_op; | |
9845 | ||
9846 | i.mask->mask = mask; | |
9847 | ||
9848 | /* Only "{z}" is allowed here. No need to check | |
9849 | zeroing mask explicitly. */ | |
9850 | if (i.mask->operand != this_operand) | |
9851 | { | |
9852 | as_bad (_("invalid write mask `%s'"), saved); | |
9853 | return NULL; | |
9854 | } | |
9855 | } | |
9856 | ||
9857 | op_string = end_op; | |
9858 | } | |
9859 | /* Check zeroing-flag for masking operation. */ | |
9860 | else if (*op_string == 'z') | |
9861 | { | |
9862 | if (!i.mask) | |
9863 | { | |
9864 | mask_op.mask = NULL; | |
9865 | mask_op.zeroing = 1; | |
9866 | mask_op.operand = this_operand; | |
9867 | i.mask = &mask_op; | |
9868 | } | |
9869 | else | |
9870 | { | |
9871 | if (i.mask->zeroing) | |
9872 | { | |
9873 | duplicated_vec_op: | |
9874 | as_bad (_("duplicated `%s'"), saved); | |
9875 | return NULL; | |
9876 | } | |
9877 | ||
9878 | i.mask->zeroing = 1; | |
9879 | ||
9880 | /* Only "{%k}" is allowed here. No need to check mask | |
9881 | register explicitly. */ | |
9882 | if (i.mask->operand != this_operand) | |
9883 | { | |
9884 | as_bad (_("invalid zeroing-masking `%s'"), | |
9885 | saved); | |
9886 | return NULL; | |
9887 | } | |
9888 | } | |
9889 | ||
9890 | op_string++; | |
9891 | } | |
9892 | else | |
9893 | goto unknown_vec_op; | |
9894 | ||
9895 | if (*op_string != '}') | |
9896 | { | |
9897 | as_bad (_("missing `}' in `%s'"), saved); | |
9898 | return NULL; | |
9899 | } | |
9900 | op_string++; | |
0ba3a731 L |
9901 | |
9902 | /* Strip whitespace since the addition of pseudo prefixes | |
9903 | changed how the scrubber treats '{'. */ | |
9904 | if (is_space_char (*op_string)) | |
9905 | ++op_string; | |
9906 | ||
43234a1e L |
9907 | continue; |
9908 | } | |
9909 | unknown_vec_op: | |
9910 | /* We don't know this one. */ | |
9911 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9912 | return NULL; | |
9913 | } | |
9914 | ||
6d2cd6b2 JB |
9915 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9916 | { | |
9917 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9918 | return NULL; | |
9919 | } | |
9920 | ||
43234a1e L |
9921 | return op_string; |
9922 | } | |
9923 | ||
252b5132 | 9924 | static int |
70e41ade | 9925 | i386_immediate (char *imm_start) |
252b5132 RH |
9926 | { |
9927 | char *save_input_line_pointer; | |
f3c180ae | 9928 | char *gotfree_input_line; |
252b5132 | 9929 | segT exp_seg = 0; |
47926f60 | 9930 | expressionS *exp; |
40fb9820 L |
9931 | i386_operand_type types; |
9932 | ||
0dfbf9d7 | 9933 | operand_type_set (&types, ~0); |
252b5132 RH |
9934 | |
9935 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9936 | { | |
31b2323c L |
9937 | as_bad (_("at most %d immediate operands are allowed"), |
9938 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9939 | return 0; |
9940 | } | |
9941 | ||
9942 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9943 | i.op[this_operand].imms = exp; |
252b5132 RH |
9944 | |
9945 | if (is_space_char (*imm_start)) | |
9946 | ++imm_start; | |
9947 | ||
9948 | save_input_line_pointer = input_line_pointer; | |
9949 | input_line_pointer = imm_start; | |
9950 | ||
d258b828 | 9951 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9952 | if (gotfree_input_line) |
9953 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9954 | |
9955 | exp_seg = expression (exp); | |
9956 | ||
83183c0c | 9957 | SKIP_WHITESPACE (); |
43234a1e L |
9958 | |
9959 | /* Handle vector operations. */ | |
9960 | if (*input_line_pointer == '{') | |
9961 | { | |
9962 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9963 | NULL); | |
9964 | if (input_line_pointer == NULL) | |
9965 | return 0; | |
9966 | } | |
9967 | ||
252b5132 | 9968 | if (*input_line_pointer) |
f3c180ae | 9969 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9970 | |
9971 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9972 | if (gotfree_input_line) |
ee86248c JB |
9973 | { |
9974 | free (gotfree_input_line); | |
9975 | ||
9976 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9977 | exp->X_op = O_illegal; | |
9978 | } | |
9979 | ||
9980 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9981 | } | |
252b5132 | 9982 | |
ee86248c JB |
9983 | static int |
9984 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9985 | i386_operand_type types, const char *imm_start) | |
9986 | { | |
9987 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9988 | { |
313c53d1 L |
9989 | if (imm_start) |
9990 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9991 | imm_start); | |
3992d3b7 | 9992 | return 0; |
252b5132 | 9993 | } |
3e73aa7c | 9994 | else if (exp->X_op == O_constant) |
252b5132 | 9995 | { |
47926f60 | 9996 | /* Size it properly later. */ |
40fb9820 | 9997 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9998 | /* If not 64bit, sign extend val. */ |
9999 | if (flag_code != CODE_64BIT | |
4eed87de AM |
10000 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
10001 | exp->X_add_number | |
10002 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 10003 | } |
4c63da97 | 10004 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 10005 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 10006 | && exp_seg != absolute_section |
47926f60 | 10007 | && exp_seg != text_section |
24eab124 AM |
10008 | && exp_seg != data_section |
10009 | && exp_seg != bss_section | |
10010 | && exp_seg != undefined_section | |
f86103b7 | 10011 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10012 | { |
d0b47220 | 10013 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10014 | return 0; |
10015 | } | |
10016 | #endif | |
a841bdf5 | 10017 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 10018 | { |
313c53d1 L |
10019 | if (imm_start) |
10020 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
10021 | return 0; |
10022 | } | |
252b5132 RH |
10023 | else |
10024 | { | |
10025 | /* This is an address. The size of the address will be | |
24eab124 | 10026 | determined later, depending on destination register, |
3e73aa7c | 10027 | suffix, or the default for the section. */ |
40fb9820 L |
10028 | i.types[this_operand].bitfield.imm8 = 1; |
10029 | i.types[this_operand].bitfield.imm16 = 1; | |
10030 | i.types[this_operand].bitfield.imm32 = 1; | |
10031 | i.types[this_operand].bitfield.imm32s = 1; | |
10032 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10033 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10034 | types); | |
252b5132 RH |
10035 | } |
10036 | ||
10037 | return 1; | |
10038 | } | |
10039 | ||
551c1ca1 | 10040 | static char * |
e3bb37b5 | 10041 | i386_scale (char *scale) |
252b5132 | 10042 | { |
551c1ca1 AM |
10043 | offsetT val; |
10044 | char *save = input_line_pointer; | |
252b5132 | 10045 | |
551c1ca1 AM |
10046 | input_line_pointer = scale; |
10047 | val = get_absolute_expression (); | |
10048 | ||
10049 | switch (val) | |
252b5132 | 10050 | { |
551c1ca1 | 10051 | case 1: |
252b5132 RH |
10052 | i.log2_scale_factor = 0; |
10053 | break; | |
551c1ca1 | 10054 | case 2: |
252b5132 RH |
10055 | i.log2_scale_factor = 1; |
10056 | break; | |
551c1ca1 | 10057 | case 4: |
252b5132 RH |
10058 | i.log2_scale_factor = 2; |
10059 | break; | |
551c1ca1 | 10060 | case 8: |
252b5132 RH |
10061 | i.log2_scale_factor = 3; |
10062 | break; | |
10063 | default: | |
a724f0f4 JB |
10064 | { |
10065 | char sep = *input_line_pointer; | |
10066 | ||
10067 | *input_line_pointer = '\0'; | |
10068 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10069 | scale); | |
10070 | *input_line_pointer = sep; | |
10071 | input_line_pointer = save; | |
10072 | return NULL; | |
10073 | } | |
252b5132 | 10074 | } |
29b0f896 | 10075 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10076 | { |
10077 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10078 | 1 << i.log2_scale_factor); |
252b5132 | 10079 | i.log2_scale_factor = 0; |
252b5132 | 10080 | } |
551c1ca1 AM |
10081 | scale = input_line_pointer; |
10082 | input_line_pointer = save; | |
10083 | return scale; | |
252b5132 RH |
10084 | } |
10085 | ||
252b5132 | 10086 | static int |
e3bb37b5 | 10087 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10088 | { |
29b0f896 | 10089 | expressionS *exp; |
252b5132 RH |
10090 | segT exp_seg = 0; |
10091 | char *save_input_line_pointer; | |
f3c180ae | 10092 | char *gotfree_input_line; |
40fb9820 L |
10093 | int override; |
10094 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10095 | int ret; |
252b5132 | 10096 | |
31b2323c L |
10097 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10098 | { | |
10099 | as_bad (_("at most %d displacement operands are allowed"), | |
10100 | MAX_MEMORY_OPERANDS); | |
10101 | return 0; | |
10102 | } | |
10103 | ||
0dfbf9d7 | 10104 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10105 | if (i.jumpabsolute |
48bcea9f | 10106 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10107 | || (current_templates->start->opcode_modifier.jump != JUMP |
10108 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10109 | { |
48bcea9f | 10110 | i386_addressing_mode (); |
e05278af | 10111 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10112 | if (flag_code == CODE_64BIT) |
10113 | { | |
10114 | if (!override) | |
10115 | { | |
10116 | bigdisp.bitfield.disp32s = 1; | |
10117 | bigdisp.bitfield.disp64 = 1; | |
10118 | } | |
48bcea9f JB |
10119 | else |
10120 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
10121 | } |
10122 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10123 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10124 | else |
10125 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10126 | } |
10127 | else | |
10128 | { | |
376cd056 JB |
10129 | /* For PC-relative branches, the width of the displacement may be |
10130 | dependent upon data size, but is never dependent upon address size. | |
10131 | Also make sure to not unintentionally match against a non-PC-relative | |
10132 | branch template. */ | |
10133 | static templates aux_templates; | |
10134 | const insn_template *t = current_templates->start; | |
10135 | bfd_boolean has_intel64 = FALSE; | |
10136 | ||
10137 | aux_templates.start = t; | |
10138 | while (++t < current_templates->end) | |
10139 | { | |
10140 | if (t->opcode_modifier.jump | |
10141 | != current_templates->start->opcode_modifier.jump) | |
10142 | break; | |
4b5aaf5f | 10143 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
376cd056 JB |
10144 | has_intel64 = TRUE; |
10145 | } | |
10146 | if (t < current_templates->end) | |
10147 | { | |
10148 | aux_templates.end = t; | |
10149 | current_templates = &aux_templates; | |
10150 | } | |
10151 | ||
e05278af | 10152 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10153 | if (flag_code == CODE_64BIT) |
10154 | { | |
376cd056 JB |
10155 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10156 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10157 | bigdisp.bitfield.disp16 = 1; |
10158 | else | |
48bcea9f | 10159 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10160 | } |
10161 | else | |
e05278af JB |
10162 | { |
10163 | if (!override) | |
10164 | override = (i.suffix == (flag_code != CODE_16BIT | |
10165 | ? WORD_MNEM_SUFFIX | |
10166 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10167 | bigdisp.bitfield.disp32 = 1; |
10168 | if ((flag_code == CODE_16BIT) ^ override) | |
10169 | { | |
10170 | bigdisp.bitfield.disp32 = 0; | |
10171 | bigdisp.bitfield.disp16 = 1; | |
10172 | } | |
e05278af | 10173 | } |
e05278af | 10174 | } |
c6fb90c8 L |
10175 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10176 | bigdisp); | |
252b5132 RH |
10177 | |
10178 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10179 | i.op[this_operand].disps = exp; |
252b5132 RH |
10180 | i.disp_operands++; |
10181 | save_input_line_pointer = input_line_pointer; | |
10182 | input_line_pointer = disp_start; | |
10183 | END_STRING_AND_SAVE (disp_end); | |
10184 | ||
10185 | #ifndef GCC_ASM_O_HACK | |
10186 | #define GCC_ASM_O_HACK 0 | |
10187 | #endif | |
10188 | #if GCC_ASM_O_HACK | |
10189 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10190 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10191 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10192 | { |
10193 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10194 | constraint within gcc asm statements. |
10195 | For instance: | |
10196 | ||
10197 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10198 | __asm__ __volatile__ ( \ | |
10199 | "movw %w2,%0\n\t" \ | |
10200 | "movw %w1,2+%0\n\t" \ | |
10201 | "rorl $16,%1\n\t" \ | |
10202 | "movb %b1,4+%0\n\t" \ | |
10203 | "movb %4,5+%0\n\t" \ | |
10204 | "movb $0,6+%0\n\t" \ | |
10205 | "movb %h1,7+%0\n\t" \ | |
10206 | "rorl $16,%1" \ | |
10207 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10208 | ||
10209 | This works great except that the output assembler ends | |
10210 | up looking a bit weird if it turns out that there is | |
10211 | no offset. You end up producing code that looks like: | |
10212 | ||
10213 | #APP | |
10214 | movw $235,(%eax) | |
10215 | movw %dx,2+(%eax) | |
10216 | rorl $16,%edx | |
10217 | movb %dl,4+(%eax) | |
10218 | movb $137,5+(%eax) | |
10219 | movb $0,6+(%eax) | |
10220 | movb %dh,7+(%eax) | |
10221 | rorl $16,%edx | |
10222 | #NO_APP | |
10223 | ||
47926f60 | 10224 | So here we provide the missing zero. */ |
24eab124 AM |
10225 | |
10226 | *displacement_string_end = '0'; | |
252b5132 RH |
10227 | } |
10228 | #endif | |
d258b828 | 10229 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10230 | if (gotfree_input_line) |
10231 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10232 | |
24eab124 | 10233 | exp_seg = expression (exp); |
252b5132 | 10234 | |
636c26b0 AM |
10235 | SKIP_WHITESPACE (); |
10236 | if (*input_line_pointer) | |
10237 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10238 | #if GCC_ASM_O_HACK | |
10239 | RESTORE_END_STRING (disp_end + 1); | |
10240 | #endif | |
636c26b0 | 10241 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10242 | if (gotfree_input_line) |
ee86248c JB |
10243 | { |
10244 | free (gotfree_input_line); | |
10245 | ||
10246 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10247 | exp->X_op = O_illegal; | |
10248 | } | |
10249 | ||
10250 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10251 | ||
10252 | RESTORE_END_STRING (disp_end); | |
10253 | ||
10254 | return ret; | |
10255 | } | |
10256 | ||
10257 | static int | |
10258 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10259 | i386_operand_type types, const char *disp_start) | |
10260 | { | |
10261 | i386_operand_type bigdisp; | |
10262 | int ret = 1; | |
636c26b0 | 10263 | |
24eab124 AM |
10264 | /* We do this to make sure that the section symbol is in |
10265 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10266 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10267 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10268 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10269 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10270 | { |
636c26b0 | 10271 | if (exp->X_op != O_symbol) |
3992d3b7 | 10272 | goto inv_disp; |
636c26b0 | 10273 | |
e5cb08ac | 10274 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10275 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
10276 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 10277 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
10278 | exp->X_op = O_subtract; |
10279 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 10280 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 10281 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
10282 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
10283 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 10284 | else |
29b0f896 | 10285 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 10286 | } |
252b5132 | 10287 | |
3992d3b7 AM |
10288 | else if (exp->X_op == O_absent |
10289 | || exp->X_op == O_illegal | |
ee86248c | 10290 | || exp->X_op == O_big) |
2daf4fd8 | 10291 | { |
3992d3b7 AM |
10292 | inv_disp: |
10293 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 10294 | disp_start); |
3992d3b7 | 10295 | ret = 0; |
2daf4fd8 AM |
10296 | } |
10297 | ||
0e1147d9 L |
10298 | else if (flag_code == CODE_64BIT |
10299 | && !i.prefix[ADDR_PREFIX] | |
10300 | && exp->X_op == O_constant) | |
10301 | { | |
10302 | /* Since displacement is signed extended to 64bit, don't allow | |
10303 | disp32 and turn off disp32s if they are out of range. */ | |
10304 | i.types[this_operand].bitfield.disp32 = 0; | |
10305 | if (!fits_in_signed_long (exp->X_add_number)) | |
10306 | { | |
10307 | i.types[this_operand].bitfield.disp32s = 0; | |
10308 | if (i.types[this_operand].bitfield.baseindex) | |
10309 | { | |
10310 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
10311 | (long) exp->X_add_number); | |
10312 | ret = 0; | |
10313 | } | |
10314 | } | |
10315 | } | |
10316 | ||
4c63da97 | 10317 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
10318 | else if (exp->X_op != O_constant |
10319 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
10320 | && exp_seg != absolute_section | |
10321 | && exp_seg != text_section | |
10322 | && exp_seg != data_section | |
10323 | && exp_seg != bss_section | |
10324 | && exp_seg != undefined_section | |
10325 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 10326 | { |
d0b47220 | 10327 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 10328 | ret = 0; |
24eab124 | 10329 | } |
252b5132 | 10330 | #endif |
3956db08 | 10331 | |
48bcea9f JB |
10332 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
10333 | /* Constants get taken care of by optimize_disp(). */ | |
10334 | && exp->X_op != O_constant) | |
10335 | i.types[this_operand].bitfield.disp8 = 1; | |
10336 | ||
40fb9820 L |
10337 | /* Check if this is a displacement only operand. */ |
10338 | bigdisp = i.types[this_operand]; | |
10339 | bigdisp.bitfield.disp8 = 0; | |
10340 | bigdisp.bitfield.disp16 = 0; | |
10341 | bigdisp.bitfield.disp32 = 0; | |
10342 | bigdisp.bitfield.disp32s = 0; | |
10343 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 10344 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
10345 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10346 | types); | |
3956db08 | 10347 | |
3992d3b7 | 10348 | return ret; |
252b5132 RH |
10349 | } |
10350 | ||
2abc2bec JB |
10351 | /* Return the active addressing mode, taking address override and |
10352 | registers forming the address into consideration. Update the | |
10353 | address override prefix if necessary. */ | |
47926f60 | 10354 | |
2abc2bec JB |
10355 | static enum flag_code |
10356 | i386_addressing_mode (void) | |
252b5132 | 10357 | { |
be05d201 L |
10358 | enum flag_code addr_mode; |
10359 | ||
10360 | if (i.prefix[ADDR_PREFIX]) | |
10361 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 JB |
10362 | else if (flag_code == CODE_16BIT |
10363 | && current_templates->start->cpu_flags.bitfield.cpumpx | |
10364 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic | |
10365 | from md_assemble() by "is not a valid base/index expression" | |
10366 | when there is a base and/or index. */ | |
10367 | && !i.types[this_operand].bitfield.baseindex) | |
10368 | { | |
10369 | /* MPX insn memory operands with neither base nor index must be forced | |
10370 | to use 32-bit addressing in 16-bit mode. */ | |
10371 | addr_mode = CODE_32BIT; | |
10372 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10373 | ++i.prefixes; | |
10374 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
10375 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
10376 | } | |
be05d201 L |
10377 | else |
10378 | { | |
10379 | addr_mode = flag_code; | |
10380 | ||
24eab124 | 10381 | #if INFER_ADDR_PREFIX |
be05d201 L |
10382 | if (i.mem_operands == 0) |
10383 | { | |
10384 | /* Infer address prefix from the first memory operand. */ | |
10385 | const reg_entry *addr_reg = i.base_reg; | |
10386 | ||
10387 | if (addr_reg == NULL) | |
10388 | addr_reg = i.index_reg; | |
eecb386c | 10389 | |
be05d201 L |
10390 | if (addr_reg) |
10391 | { | |
e968fc9b | 10392 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
10393 | addr_mode = CODE_32BIT; |
10394 | else if (flag_code != CODE_64BIT | |
dc821c5f | 10395 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
10396 | addr_mode = CODE_16BIT; |
10397 | ||
10398 | if (addr_mode != flag_code) | |
10399 | { | |
10400 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10401 | i.prefixes += 1; | |
10402 | /* Change the size of any displacement too. At most one | |
10403 | of Disp16 or Disp32 is set. | |
10404 | FIXME. There doesn't seem to be any real need for | |
10405 | separate Disp16 and Disp32 flags. The same goes for | |
10406 | Imm16 and Imm32. Removing them would probably clean | |
10407 | up the code quite a lot. */ | |
10408 | if (flag_code != CODE_64BIT | |
10409 | && (i.types[this_operand].bitfield.disp16 | |
10410 | || i.types[this_operand].bitfield.disp32)) | |
10411 | i.types[this_operand] | |
10412 | = operand_type_xor (i.types[this_operand], disp16_32); | |
10413 | } | |
10414 | } | |
10415 | } | |
24eab124 | 10416 | #endif |
be05d201 L |
10417 | } |
10418 | ||
2abc2bec JB |
10419 | return addr_mode; |
10420 | } | |
10421 | ||
10422 | /* Make sure the memory operand we've been dealt is valid. | |
10423 | Return 1 on success, 0 on a failure. */ | |
10424 | ||
10425 | static int | |
10426 | i386_index_check (const char *operand_string) | |
10427 | { | |
10428 | const char *kind = "base/index"; | |
10429 | enum flag_code addr_mode = i386_addressing_mode (); | |
10430 | ||
fc0763e6 | 10431 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 10432 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
10433 | && (current_templates->end[-1].opcode_modifier.isstring |
10434 | || i.mem_operands)) | |
10435 | { | |
10436 | /* Memory operands of string insns are special in that they only allow | |
10437 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
10438 | const reg_entry *expected_reg; |
10439 | static const char *di_si[][2] = | |
10440 | { | |
10441 | { "esi", "edi" }, | |
10442 | { "si", "di" }, | |
10443 | { "rsi", "rdi" } | |
10444 | }; | |
10445 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
10446 | |
10447 | kind = "string address"; | |
10448 | ||
8325cc63 | 10449 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 | 10450 | { |
51c8edf6 JB |
10451 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
10452 | - IS_STRING_ES_OP0; | |
10453 | int op = 0; | |
fc0763e6 | 10454 | |
51c8edf6 | 10455 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
10456 | || ((!i.mem_operands != !intel_syntax) |
10457 | && current_templates->end[-1].operand_types[1] | |
10458 | .bitfield.baseindex)) | |
51c8edf6 JB |
10459 | op = 1; |
10460 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
10461 | } |
10462 | else | |
be05d201 | 10463 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 10464 | |
be05d201 L |
10465 | if (i.base_reg != expected_reg |
10466 | || i.index_reg | |
fc0763e6 | 10467 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 10468 | { |
be05d201 L |
10469 | /* The second memory operand must have the same size as |
10470 | the first one. */ | |
10471 | if (i.mem_operands | |
10472 | && i.base_reg | |
10473 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 10474 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 10475 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
10476 | ? i.base_reg->reg_type.bitfield.dword |
10477 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
10478 | goto bad_address; |
10479 | ||
fc0763e6 JB |
10480 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
10481 | operand_string, | |
10482 | intel_syntax ? '[' : '(', | |
10483 | register_prefix, | |
be05d201 | 10484 | expected_reg->reg_name, |
fc0763e6 | 10485 | intel_syntax ? ']' : ')'); |
be05d201 | 10486 | return 1; |
fc0763e6 | 10487 | } |
be05d201 L |
10488 | else |
10489 | return 1; | |
10490 | ||
dc1e8a47 | 10491 | bad_address: |
be05d201 L |
10492 | as_bad (_("`%s' is not a valid %s expression"), |
10493 | operand_string, kind); | |
10494 | return 0; | |
3e73aa7c JH |
10495 | } |
10496 | else | |
10497 | { | |
be05d201 L |
10498 | if (addr_mode != CODE_16BIT) |
10499 | { | |
10500 | /* 32-bit/64-bit checks. */ | |
10501 | if ((i.base_reg | |
e968fc9b JB |
10502 | && ((addr_mode == CODE_64BIT |
10503 | ? !i.base_reg->reg_type.bitfield.qword | |
10504 | : !i.base_reg->reg_type.bitfield.dword) | |
10505 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
10506 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 10507 | || (i.index_reg |
1b54b8d7 JB |
10508 | && !i.index_reg->reg_type.bitfield.xmmword |
10509 | && !i.index_reg->reg_type.bitfield.ymmword | |
10510 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 10511 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
10512 | ? !i.index_reg->reg_type.bitfield.qword |
10513 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
10514 | || !i.index_reg->reg_type.bitfield.baseindex))) |
10515 | goto bad_address; | |
8178be5b JB |
10516 | |
10517 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
10518 | if (current_templates->start->base_opcode == 0xf30f1b | |
10519 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
10520 | { | |
10521 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 10522 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
10523 | { |
10524 | as_bad (_("`%s' cannot be used here"), operand_string); | |
10525 | return 0; | |
10526 | } | |
10527 | ||
10528 | /* bndldx and bndstx ignore their scale factor. */ | |
10529 | if (current_templates->start->base_opcode != 0xf30f1b | |
10530 | && i.log2_scale_factor) | |
10531 | as_warn (_("register scaling is being ignored here")); | |
10532 | } | |
be05d201 L |
10533 | } |
10534 | else | |
3e73aa7c | 10535 | { |
be05d201 | 10536 | /* 16-bit checks. */ |
3e73aa7c | 10537 | if ((i.base_reg |
dc821c5f | 10538 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 10539 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 10540 | || (i.index_reg |
dc821c5f | 10541 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 10542 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
10543 | || !(i.base_reg |
10544 | && i.base_reg->reg_num < 6 | |
10545 | && i.index_reg->reg_num >= 6 | |
10546 | && i.log2_scale_factor == 0)))) | |
be05d201 | 10547 | goto bad_address; |
3e73aa7c JH |
10548 | } |
10549 | } | |
be05d201 | 10550 | return 1; |
24eab124 | 10551 | } |
252b5132 | 10552 | |
43234a1e L |
10553 | /* Handle vector immediates. */ |
10554 | ||
10555 | static int | |
10556 | RC_SAE_immediate (const char *imm_start) | |
10557 | { | |
10558 | unsigned int match_found, j; | |
10559 | const char *pstr = imm_start; | |
10560 | expressionS *exp; | |
10561 | ||
10562 | if (*pstr != '{') | |
10563 | return 0; | |
10564 | ||
10565 | pstr++; | |
10566 | match_found = 0; | |
10567 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10568 | { | |
10569 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10570 | { | |
10571 | if (!i.rounding) | |
10572 | { | |
10573 | rc_op.type = RC_NamesTable[j].type; | |
10574 | rc_op.operand = this_operand; | |
10575 | i.rounding = &rc_op; | |
10576 | } | |
10577 | else | |
10578 | { | |
10579 | as_bad (_("duplicated `%s'"), imm_start); | |
10580 | return 0; | |
10581 | } | |
10582 | pstr += RC_NamesTable[j].len; | |
10583 | match_found = 1; | |
10584 | break; | |
10585 | } | |
10586 | } | |
10587 | if (!match_found) | |
10588 | return 0; | |
10589 | ||
10590 | if (*pstr++ != '}') | |
10591 | { | |
10592 | as_bad (_("Missing '}': '%s'"), imm_start); | |
10593 | return 0; | |
10594 | } | |
10595 | /* RC/SAE immediate string should contain nothing more. */; | |
10596 | if (*pstr != 0) | |
10597 | { | |
10598 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
10599 | return 0; | |
10600 | } | |
10601 | ||
10602 | exp = &im_expressions[i.imm_operands++]; | |
10603 | i.op[this_operand].imms = exp; | |
10604 | ||
10605 | exp->X_op = O_constant; | |
10606 | exp->X_add_number = 0; | |
10607 | exp->X_add_symbol = (symbolS *) 0; | |
10608 | exp->X_op_symbol = (symbolS *) 0; | |
10609 | ||
10610 | i.types[this_operand].bitfield.imm8 = 1; | |
10611 | return 1; | |
10612 | } | |
10613 | ||
8325cc63 JB |
10614 | /* Only string instructions can have a second memory operand, so |
10615 | reduce current_templates to just those if it contains any. */ | |
10616 | static int | |
10617 | maybe_adjust_templates (void) | |
10618 | { | |
10619 | const insn_template *t; | |
10620 | ||
10621 | gas_assert (i.mem_operands == 1); | |
10622 | ||
10623 | for (t = current_templates->start; t < current_templates->end; ++t) | |
10624 | if (t->opcode_modifier.isstring) | |
10625 | break; | |
10626 | ||
10627 | if (t < current_templates->end) | |
10628 | { | |
10629 | static templates aux_templates; | |
10630 | bfd_boolean recheck; | |
10631 | ||
10632 | aux_templates.start = t; | |
10633 | for (; t < current_templates->end; ++t) | |
10634 | if (!t->opcode_modifier.isstring) | |
10635 | break; | |
10636 | aux_templates.end = t; | |
10637 | ||
10638 | /* Determine whether to re-check the first memory operand. */ | |
10639 | recheck = (aux_templates.start != current_templates->start | |
10640 | || t != current_templates->end); | |
10641 | ||
10642 | current_templates = &aux_templates; | |
10643 | ||
10644 | if (recheck) | |
10645 | { | |
10646 | i.mem_operands = 0; | |
10647 | if (i.memop1_string != NULL | |
10648 | && i386_index_check (i.memop1_string) == 0) | |
10649 | return 0; | |
10650 | i.mem_operands = 1; | |
10651 | } | |
10652 | } | |
10653 | ||
10654 | return 1; | |
10655 | } | |
10656 | ||
fc0763e6 | 10657 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 10658 | on error. */ |
252b5132 | 10659 | |
252b5132 | 10660 | static int |
a7619375 | 10661 | i386_att_operand (char *operand_string) |
252b5132 | 10662 | { |
af6bdddf AM |
10663 | const reg_entry *r; |
10664 | char *end_op; | |
24eab124 | 10665 | char *op_string = operand_string; |
252b5132 | 10666 | |
24eab124 | 10667 | if (is_space_char (*op_string)) |
252b5132 RH |
10668 | ++op_string; |
10669 | ||
24eab124 | 10670 | /* We check for an absolute prefix (differentiating, |
47926f60 | 10671 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
10672 | if (*op_string == ABSOLUTE_PREFIX) |
10673 | { | |
10674 | ++op_string; | |
10675 | if (is_space_char (*op_string)) | |
10676 | ++op_string; | |
6f2f06be | 10677 | i.jumpabsolute = TRUE; |
24eab124 | 10678 | } |
252b5132 | 10679 | |
47926f60 | 10680 | /* Check if operand is a register. */ |
4d1bb795 | 10681 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 10682 | { |
40fb9820 L |
10683 | i386_operand_type temp; |
10684 | ||
24eab124 AM |
10685 | /* Check for a segment override by searching for ':' after a |
10686 | segment register. */ | |
10687 | op_string = end_op; | |
10688 | if (is_space_char (*op_string)) | |
10689 | ++op_string; | |
00cee14f | 10690 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
10691 | { |
10692 | switch (r->reg_num) | |
10693 | { | |
10694 | case 0: | |
10695 | i.seg[i.mem_operands] = &es; | |
10696 | break; | |
10697 | case 1: | |
10698 | i.seg[i.mem_operands] = &cs; | |
10699 | break; | |
10700 | case 2: | |
10701 | i.seg[i.mem_operands] = &ss; | |
10702 | break; | |
10703 | case 3: | |
10704 | i.seg[i.mem_operands] = &ds; | |
10705 | break; | |
10706 | case 4: | |
10707 | i.seg[i.mem_operands] = &fs; | |
10708 | break; | |
10709 | case 5: | |
10710 | i.seg[i.mem_operands] = &gs; | |
10711 | break; | |
10712 | } | |
252b5132 | 10713 | |
24eab124 | 10714 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10715 | ++op_string; |
10716 | if (is_space_char (*op_string)) | |
24eab124 | 10717 | ++op_string; |
252b5132 | 10718 | |
24eab124 AM |
10719 | if (!is_digit_char (*op_string) |
10720 | && !is_identifier_char (*op_string) | |
10721 | && *op_string != '(' | |
10722 | && *op_string != ABSOLUTE_PREFIX) | |
10723 | { | |
10724 | as_bad (_("bad memory operand `%s'"), op_string); | |
10725 | return 0; | |
10726 | } | |
47926f60 | 10727 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10728 | if (*op_string == ABSOLUTE_PREFIX) |
10729 | { | |
10730 | ++op_string; | |
10731 | if (is_space_char (*op_string)) | |
10732 | ++op_string; | |
6f2f06be | 10733 | i.jumpabsolute = TRUE; |
24eab124 AM |
10734 | } |
10735 | goto do_memory_reference; | |
10736 | } | |
43234a1e L |
10737 | |
10738 | /* Handle vector operations. */ | |
10739 | if (*op_string == '{') | |
10740 | { | |
10741 | op_string = check_VecOperations (op_string, NULL); | |
10742 | if (op_string == NULL) | |
10743 | return 0; | |
10744 | } | |
10745 | ||
24eab124 AM |
10746 | if (*op_string) |
10747 | { | |
d0b47220 | 10748 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10749 | return 0; |
10750 | } | |
40fb9820 L |
10751 | temp = r->reg_type; |
10752 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10753 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10754 | temp); | |
7d5e4556 | 10755 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10756 | i.op[this_operand].regs = r; |
24eab124 AM |
10757 | i.reg_operands++; |
10758 | } | |
af6bdddf AM |
10759 | else if (*op_string == REGISTER_PREFIX) |
10760 | { | |
10761 | as_bad (_("bad register name `%s'"), op_string); | |
10762 | return 0; | |
10763 | } | |
24eab124 | 10764 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10765 | { |
24eab124 | 10766 | ++op_string; |
6f2f06be | 10767 | if (i.jumpabsolute) |
24eab124 | 10768 | { |
d0b47220 | 10769 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10770 | return 0; |
10771 | } | |
10772 | if (!i386_immediate (op_string)) | |
10773 | return 0; | |
10774 | } | |
43234a1e L |
10775 | else if (RC_SAE_immediate (operand_string)) |
10776 | { | |
10777 | /* If it is a RC or SAE immediate, do nothing. */ | |
10778 | ; | |
10779 | } | |
24eab124 AM |
10780 | else if (is_digit_char (*op_string) |
10781 | || is_identifier_char (*op_string) | |
d02603dc | 10782 | || *op_string == '"' |
e5cb08ac | 10783 | || *op_string == '(') |
24eab124 | 10784 | { |
47926f60 | 10785 | /* This is a memory reference of some sort. */ |
af6bdddf | 10786 | char *base_string; |
252b5132 | 10787 | |
47926f60 | 10788 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10789 | char *displacement_string_start; |
10790 | char *displacement_string_end; | |
43234a1e | 10791 | char *vop_start; |
252b5132 | 10792 | |
24eab124 | 10793 | do_memory_reference: |
8325cc63 JB |
10794 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10795 | return 0; | |
24eab124 | 10796 | if ((i.mem_operands == 1 |
40fb9820 | 10797 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10798 | || i.mem_operands == 2) |
10799 | { | |
10800 | as_bad (_("too many memory references for `%s'"), | |
10801 | current_templates->start->name); | |
10802 | return 0; | |
10803 | } | |
252b5132 | 10804 | |
24eab124 AM |
10805 | /* Check for base index form. We detect the base index form by |
10806 | looking for an ')' at the end of the operand, searching | |
10807 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10808 | after the '('. */ | |
af6bdddf | 10809 | base_string = op_string + strlen (op_string); |
c3332e24 | 10810 | |
43234a1e L |
10811 | /* Handle vector operations. */ |
10812 | vop_start = strchr (op_string, '{'); | |
10813 | if (vop_start && vop_start < base_string) | |
10814 | { | |
10815 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10816 | return 0; | |
10817 | base_string = vop_start; | |
10818 | } | |
10819 | ||
af6bdddf AM |
10820 | --base_string; |
10821 | if (is_space_char (*base_string)) | |
10822 | --base_string; | |
252b5132 | 10823 | |
47926f60 | 10824 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10825 | displacement_string_start = op_string; |
10826 | displacement_string_end = base_string + 1; | |
252b5132 | 10827 | |
24eab124 AM |
10828 | if (*base_string == ')') |
10829 | { | |
af6bdddf | 10830 | char *temp_string; |
24eab124 AM |
10831 | unsigned int parens_balanced = 1; |
10832 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10833 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10834 | do |
10835 | { | |
10836 | base_string--; | |
10837 | if (*base_string == ')') | |
10838 | parens_balanced++; | |
10839 | if (*base_string == '(') | |
10840 | parens_balanced--; | |
10841 | } | |
10842 | while (parens_balanced); | |
c3332e24 | 10843 | |
af6bdddf | 10844 | temp_string = base_string; |
c3332e24 | 10845 | |
24eab124 | 10846 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10847 | ++base_string; |
10848 | if (is_space_char (*base_string)) | |
24eab124 | 10849 | ++base_string; |
252b5132 | 10850 | |
af6bdddf | 10851 | if (*base_string == ',' |
4eed87de AM |
10852 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10853 | != NULL)) | |
252b5132 | 10854 | { |
af6bdddf | 10855 | displacement_string_end = temp_string; |
252b5132 | 10856 | |
40fb9820 | 10857 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10858 | |
af6bdddf | 10859 | if (i.base_reg) |
24eab124 | 10860 | { |
24eab124 AM |
10861 | base_string = end_op; |
10862 | if (is_space_char (*base_string)) | |
10863 | ++base_string; | |
af6bdddf AM |
10864 | } |
10865 | ||
10866 | /* There may be an index reg or scale factor here. */ | |
10867 | if (*base_string == ',') | |
10868 | { | |
10869 | ++base_string; | |
10870 | if (is_space_char (*base_string)) | |
10871 | ++base_string; | |
10872 | ||
4eed87de AM |
10873 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10874 | != NULL) | |
24eab124 | 10875 | { |
af6bdddf | 10876 | base_string = end_op; |
24eab124 AM |
10877 | if (is_space_char (*base_string)) |
10878 | ++base_string; | |
af6bdddf AM |
10879 | if (*base_string == ',') |
10880 | { | |
10881 | ++base_string; | |
10882 | if (is_space_char (*base_string)) | |
10883 | ++base_string; | |
10884 | } | |
e5cb08ac | 10885 | else if (*base_string != ')') |
af6bdddf | 10886 | { |
4eed87de AM |
10887 | as_bad (_("expecting `,' or `)' " |
10888 | "after index register in `%s'"), | |
af6bdddf AM |
10889 | operand_string); |
10890 | return 0; | |
10891 | } | |
24eab124 | 10892 | } |
af6bdddf | 10893 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10894 | { |
f76bf5e0 L |
10895 | end_op = strchr (base_string, ','); |
10896 | if (end_op) | |
10897 | *end_op = '\0'; | |
af6bdddf | 10898 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10899 | return 0; |
10900 | } | |
252b5132 | 10901 | |
47926f60 | 10902 | /* Check for scale factor. */ |
551c1ca1 | 10903 | if (*base_string != ')') |
af6bdddf | 10904 | { |
551c1ca1 AM |
10905 | char *end_scale = i386_scale (base_string); |
10906 | ||
10907 | if (!end_scale) | |
af6bdddf | 10908 | return 0; |
24eab124 | 10909 | |
551c1ca1 | 10910 | base_string = end_scale; |
af6bdddf AM |
10911 | if (is_space_char (*base_string)) |
10912 | ++base_string; | |
10913 | if (*base_string != ')') | |
10914 | { | |
4eed87de AM |
10915 | as_bad (_("expecting `)' " |
10916 | "after scale factor in `%s'"), | |
af6bdddf AM |
10917 | operand_string); |
10918 | return 0; | |
10919 | } | |
10920 | } | |
10921 | else if (!i.index_reg) | |
24eab124 | 10922 | { |
4eed87de AM |
10923 | as_bad (_("expecting index register or scale factor " |
10924 | "after `,'; got '%c'"), | |
af6bdddf | 10925 | *base_string); |
24eab124 AM |
10926 | return 0; |
10927 | } | |
10928 | } | |
af6bdddf | 10929 | else if (*base_string != ')') |
24eab124 | 10930 | { |
4eed87de AM |
10931 | as_bad (_("expecting `,' or `)' " |
10932 | "after base register in `%s'"), | |
af6bdddf | 10933 | operand_string); |
24eab124 AM |
10934 | return 0; |
10935 | } | |
c3332e24 | 10936 | } |
af6bdddf | 10937 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10938 | { |
f76bf5e0 L |
10939 | end_op = strchr (base_string, ','); |
10940 | if (end_op) | |
10941 | *end_op = '\0'; | |
af6bdddf | 10942 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10943 | return 0; |
c3332e24 | 10944 | } |
24eab124 AM |
10945 | } |
10946 | ||
10947 | /* If there's an expression beginning the operand, parse it, | |
10948 | assuming displacement_string_start and | |
10949 | displacement_string_end are meaningful. */ | |
10950 | if (displacement_string_start != displacement_string_end) | |
10951 | { | |
10952 | if (!i386_displacement (displacement_string_start, | |
10953 | displacement_string_end)) | |
10954 | return 0; | |
10955 | } | |
10956 | ||
10957 | /* Special case for (%dx) while doing input/output op. */ | |
10958 | if (i.base_reg | |
75e5731b JB |
10959 | && i.base_reg->reg_type.bitfield.instance == RegD |
10960 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
10961 | && i.index_reg == 0 |
10962 | && i.log2_scale_factor == 0 | |
10963 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10964 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10965 | { |
2fb5be8d | 10966 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10967 | return 1; |
10968 | } | |
10969 | ||
eecb386c AM |
10970 | if (i386_index_check (operand_string) == 0) |
10971 | return 0; | |
c48dadc9 | 10972 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10973 | if (i.mem_operands == 0) |
10974 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10975 | i.mem_operands++; |
10976 | } | |
10977 | else | |
ce8a8b2f AM |
10978 | { |
10979 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10980 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10981 | output_invalid (*op_string), | |
10982 | this_operand + 1, | |
10983 | op_string); | |
10984 | return 0; | |
10985 | } | |
47926f60 | 10986 | return 1; /* Normal return. */ |
252b5132 RH |
10987 | } |
10988 | \f | |
fa94de6b RM |
10989 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10990 | that an rs_machine_dependent frag may reach. */ | |
10991 | ||
10992 | unsigned int | |
10993 | i386_frag_max_var (fragS *frag) | |
10994 | { | |
10995 | /* The only relaxable frags are for jumps. | |
10996 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10997 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10998 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10999 | } | |
11000 | ||
b084df0b L |
11001 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11002 | static int | |
8dcea932 | 11003 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
11004 | { |
11005 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
11006 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
11007 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
11008 | return 0; | |
11009 | ||
11010 | if (!S_IS_EXTERNAL (fr_symbol)) | |
11011 | /* Symbol may be weak or local. */ | |
11012 | return !S_IS_WEAK (fr_symbol); | |
11013 | ||
8dcea932 L |
11014 | /* Global symbols with non-default visibility can't be preempted. */ |
11015 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
11016 | return 1; | |
11017 | ||
11018 | if (fr_var != NO_RELOC) | |
11019 | switch ((enum bfd_reloc_code_real) fr_var) | |
11020 | { | |
11021 | case BFD_RELOC_386_PLT32: | |
11022 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11023 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11024 | return 0; |
11025 | default: | |
11026 | abort (); | |
11027 | } | |
11028 | ||
b084df0b L |
11029 | /* Global symbols with default visibility in a shared library may be |
11030 | preempted by another definition. */ | |
8dcea932 | 11031 | return !shared; |
b084df0b L |
11032 | } |
11033 | #endif | |
11034 | ||
79d72f45 HL |
11035 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11036 | Note also work for Skylake and Cascadelake. | |
11037 | --------------------------------------------------------------------- | |
11038 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11039 | | ------ | ----------- | ------- | -------- | | |
11040 | | Jo | N | N | Y | | |
11041 | | Jno | N | N | Y | | |
11042 | | Jc/Jb | Y | N | Y | | |
11043 | | Jae/Jnb | Y | N | Y | | |
11044 | | Je/Jz | Y | Y | Y | | |
11045 | | Jne/Jnz | Y | Y | Y | | |
11046 | | Jna/Jbe | Y | N | Y | | |
11047 | | Ja/Jnbe | Y | N | Y | | |
11048 | | Js | N | N | Y | | |
11049 | | Jns | N | N | Y | | |
11050 | | Jp/Jpe | N | N | Y | | |
11051 | | Jnp/Jpo | N | N | Y | | |
11052 | | Jl/Jnge | Y | Y | Y | | |
11053 | | Jge/Jnl | Y | Y | Y | | |
11054 | | Jle/Jng | Y | Y | Y | | |
11055 | | Jg/Jnle | Y | Y | Y | | |
11056 | --------------------------------------------------------------------- */ | |
11057 | static int | |
11058 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11059 | { | |
11060 | if (mf_cmp == mf_cmp_alu_cmp) | |
11061 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11062 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11063 | if (mf_cmp == mf_cmp_incdec) | |
11064 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11065 | || mf_jcc == mf_jcc_jle); | |
11066 | if (mf_cmp == mf_cmp_test_and) | |
11067 | return 1; | |
11068 | return 0; | |
11069 | } | |
11070 | ||
e379e5f3 L |
11071 | /* Return the next non-empty frag. */ |
11072 | ||
11073 | static fragS * | |
11074 | i386_next_non_empty_frag (fragS *fragP) | |
11075 | { | |
11076 | /* There may be a frag with a ".fill 0" when there is no room in | |
11077 | the current frag for frag_grow in output_insn. */ | |
11078 | for (fragP = fragP->fr_next; | |
11079 | (fragP != NULL | |
11080 | && fragP->fr_type == rs_fill | |
11081 | && fragP->fr_fix == 0); | |
11082 | fragP = fragP->fr_next) | |
11083 | ; | |
11084 | return fragP; | |
11085 | } | |
11086 | ||
11087 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11088 | ||
11089 | static fragS * | |
79d72f45 | 11090 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11091 | { |
79d72f45 HL |
11092 | fragS *branch_fragP; |
11093 | if (!pad_fragP) | |
e379e5f3 L |
11094 | return NULL; |
11095 | ||
79d72f45 HL |
11096 | if (pad_fragP->fr_type == rs_machine_dependent |
11097 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11098 | == BRANCH_PADDING)) |
11099 | { | |
79d72f45 HL |
11100 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11101 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11102 | return NULL; |
79d72f45 HL |
11103 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11104 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11105 | pad_fragP->tc_frag_data.mf_type)) | |
11106 | return branch_fragP; | |
e379e5f3 L |
11107 | } |
11108 | ||
11109 | return NULL; | |
11110 | } | |
11111 | ||
11112 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11113 | ||
11114 | static void | |
11115 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11116 | { | |
11117 | fragS *cmp_fragP; | |
11118 | fragS *pad_fragP; | |
11119 | fragS *branch_fragP; | |
11120 | fragS *next_fragP; | |
11121 | unsigned int max_prefix_length; | |
11122 | ||
11123 | if (fragP->tc_frag_data.classified) | |
11124 | return; | |
11125 | ||
11126 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11127 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11128 | for (next_fragP = fragP; | |
11129 | next_fragP != NULL; | |
11130 | next_fragP = next_fragP->fr_next) | |
11131 | { | |
11132 | next_fragP->tc_frag_data.classified = 1; | |
11133 | if (next_fragP->fr_type == rs_machine_dependent) | |
11134 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11135 | { | |
11136 | case BRANCH_PADDING: | |
11137 | /* The BRANCH_PADDING frag must be followed by a branch | |
11138 | frag. */ | |
11139 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11140 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11141 | break; | |
11142 | case FUSED_JCC_PADDING: | |
11143 | /* Check if this is a fused jcc: | |
11144 | FUSED_JCC_PADDING | |
11145 | CMP like instruction | |
11146 | BRANCH_PADDING | |
11147 | COND_JUMP | |
11148 | */ | |
11149 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11150 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11151 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11152 | if (branch_fragP) |
11153 | { | |
11154 | /* The BRANCH_PADDING frag is merged with the | |
11155 | FUSED_JCC_PADDING frag. */ | |
11156 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11157 | /* CMP like instruction size. */ | |
11158 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11159 | frag_wane (pad_fragP); | |
11160 | /* Skip to branch_fragP. */ | |
11161 | next_fragP = branch_fragP; | |
11162 | } | |
11163 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11164 | { | |
11165 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11166 | a fused jcc. */ | |
11167 | next_fragP->fr_subtype | |
11168 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11169 | next_fragP->tc_frag_data.max_bytes | |
11170 | = next_fragP->tc_frag_data.max_prefix_length; | |
11171 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11172 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11173 | } | |
11174 | else | |
11175 | frag_wane (next_fragP); | |
11176 | break; | |
11177 | } | |
11178 | } | |
11179 | ||
11180 | /* Stop if there is no BRANCH_PREFIX. */ | |
11181 | if (!align_branch_prefix_size) | |
11182 | return; | |
11183 | ||
11184 | /* Scan for BRANCH_PREFIX. */ | |
11185 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11186 | { | |
11187 | if (fragP->fr_type != rs_machine_dependent | |
11188 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11189 | != BRANCH_PREFIX)) | |
11190 | continue; | |
11191 | ||
11192 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11193 | COND_JUMP_PREFIX. */ | |
11194 | max_prefix_length = 0; | |
11195 | for (next_fragP = fragP; | |
11196 | next_fragP != NULL; | |
11197 | next_fragP = next_fragP->fr_next) | |
11198 | { | |
11199 | if (next_fragP->fr_type == rs_fill) | |
11200 | /* Skip rs_fill frags. */ | |
11201 | continue; | |
11202 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11203 | /* Stop for all other frags. */ | |
11204 | break; | |
11205 | ||
11206 | /* rs_machine_dependent frags. */ | |
11207 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11208 | == BRANCH_PREFIX) | |
11209 | { | |
11210 | /* Count BRANCH_PREFIX frags. */ | |
11211 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11212 | { | |
11213 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11214 | frag_wane (next_fragP); | |
11215 | } | |
11216 | else | |
11217 | max_prefix_length | |
11218 | += next_fragP->tc_frag_data.max_bytes; | |
11219 | } | |
11220 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11221 | == BRANCH_PADDING) | |
11222 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11223 | == FUSED_JCC_PADDING)) | |
11224 | { | |
11225 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11226 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11227 | break; | |
11228 | } | |
11229 | else | |
11230 | /* Stop for other rs_machine_dependent frags. */ | |
11231 | break; | |
11232 | } | |
11233 | ||
11234 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11235 | ||
11236 | /* Skip to the next frag. */ | |
11237 | fragP = next_fragP; | |
11238 | } | |
11239 | } | |
11240 | ||
11241 | /* Compute padding size for | |
11242 | ||
11243 | FUSED_JCC_PADDING | |
11244 | CMP like instruction | |
11245 | BRANCH_PADDING | |
11246 | COND_JUMP/UNCOND_JUMP | |
11247 | ||
11248 | or | |
11249 | ||
11250 | BRANCH_PADDING | |
11251 | COND_JUMP/UNCOND_JUMP | |
11252 | */ | |
11253 | ||
11254 | static int | |
11255 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11256 | { | |
11257 | unsigned int offset, size, padding_size; | |
11258 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11259 | ||
11260 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11261 | if (!address) | |
11262 | address = fragP->fr_address; | |
11263 | address += fragP->fr_fix; | |
11264 | ||
11265 | /* CMP like instrunction size. */ | |
11266 | size = fragP->tc_frag_data.cmp_size; | |
11267 | ||
11268 | /* The base size of the branch frag. */ | |
11269 | size += branch_fragP->fr_fix; | |
11270 | ||
11271 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11272 | branch frag. */ | |
11273 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11274 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11275 | ||
11276 | /* Check if branch is within boundary and doesn't end at the last | |
11277 | byte. */ | |
11278 | offset = address & ((1U << align_branch_power) - 1); | |
11279 | if ((offset + size) >= (1U << align_branch_power)) | |
11280 | /* Padding needed to avoid crossing boundary. */ | |
11281 | padding_size = (1U << align_branch_power) - offset; | |
11282 | else | |
11283 | /* No padding needed. */ | |
11284 | padding_size = 0; | |
11285 | ||
11286 | /* The return value may be saved in tc_frag_data.length which is | |
11287 | unsigned byte. */ | |
11288 | if (!fits_in_unsigned_byte (padding_size)) | |
11289 | abort (); | |
11290 | ||
11291 | return padding_size; | |
11292 | } | |
11293 | ||
11294 | /* i386_generic_table_relax_frag() | |
11295 | ||
11296 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
11297 | grow/shrink padding to align branch frags. Hand others to | |
11298 | relax_frag(). */ | |
11299 | ||
11300 | long | |
11301 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
11302 | { | |
11303 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
11304 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11305 | { | |
11306 | long padding_size = i386_branch_padding_size (fragP, 0); | |
11307 | long grow = padding_size - fragP->tc_frag_data.length; | |
11308 | ||
11309 | /* When the BRANCH_PREFIX frag is used, the computed address | |
11310 | must match the actual address and there should be no padding. */ | |
11311 | if (fragP->tc_frag_data.padding_address | |
11312 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
11313 | || padding_size)) | |
11314 | abort (); | |
11315 | ||
11316 | /* Update the padding size. */ | |
11317 | if (grow) | |
11318 | fragP->tc_frag_data.length = padding_size; | |
11319 | ||
11320 | return grow; | |
11321 | } | |
11322 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11323 | { | |
11324 | fragS *padding_fragP, *next_fragP; | |
11325 | long padding_size, left_size, last_size; | |
11326 | ||
11327 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11328 | if (!padding_fragP) | |
11329 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
11330 | return (fragP->tc_frag_data.length | |
11331 | - fragP->tc_frag_data.last_length); | |
11332 | ||
11333 | /* Compute the relative address of the padding frag in the very | |
11334 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
11335 | if (!fragP->tc_frag_data.padding_address) | |
11336 | fragP->tc_frag_data.padding_address | |
11337 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
11338 | ||
11339 | /* First update the last length from the previous interation. */ | |
11340 | left_size = fragP->tc_frag_data.prefix_length; | |
11341 | for (next_fragP = fragP; | |
11342 | next_fragP != padding_fragP; | |
11343 | next_fragP = next_fragP->fr_next) | |
11344 | if (next_fragP->fr_type == rs_machine_dependent | |
11345 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11346 | == BRANCH_PREFIX)) | |
11347 | { | |
11348 | if (left_size) | |
11349 | { | |
11350 | int max = next_fragP->tc_frag_data.max_bytes; | |
11351 | if (max) | |
11352 | { | |
11353 | int size; | |
11354 | if (max > left_size) | |
11355 | size = left_size; | |
11356 | else | |
11357 | size = max; | |
11358 | left_size -= size; | |
11359 | next_fragP->tc_frag_data.last_length = size; | |
11360 | } | |
11361 | } | |
11362 | else | |
11363 | next_fragP->tc_frag_data.last_length = 0; | |
11364 | } | |
11365 | ||
11366 | /* Check the padding size for the padding frag. */ | |
11367 | padding_size = i386_branch_padding_size | |
11368 | (padding_fragP, (fragP->fr_address | |
11369 | + fragP->tc_frag_data.padding_address)); | |
11370 | ||
11371 | last_size = fragP->tc_frag_data.prefix_length; | |
11372 | /* Check if there is change from the last interation. */ | |
11373 | if (padding_size == last_size) | |
11374 | { | |
11375 | /* Update the expected address of the padding frag. */ | |
11376 | padding_fragP->tc_frag_data.padding_address | |
11377 | = (fragP->fr_address + padding_size | |
11378 | + fragP->tc_frag_data.padding_address); | |
11379 | return 0; | |
11380 | } | |
11381 | ||
11382 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
11383 | { | |
11384 | /* No padding if there is no sufficient room. Clear the | |
11385 | expected address of the padding frag. */ | |
11386 | padding_fragP->tc_frag_data.padding_address = 0; | |
11387 | padding_size = 0; | |
11388 | } | |
11389 | else | |
11390 | /* Store the expected address of the padding frag. */ | |
11391 | padding_fragP->tc_frag_data.padding_address | |
11392 | = (fragP->fr_address + padding_size | |
11393 | + fragP->tc_frag_data.padding_address); | |
11394 | ||
11395 | fragP->tc_frag_data.prefix_length = padding_size; | |
11396 | ||
11397 | /* Update the length for the current interation. */ | |
11398 | left_size = padding_size; | |
11399 | for (next_fragP = fragP; | |
11400 | next_fragP != padding_fragP; | |
11401 | next_fragP = next_fragP->fr_next) | |
11402 | if (next_fragP->fr_type == rs_machine_dependent | |
11403 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11404 | == BRANCH_PREFIX)) | |
11405 | { | |
11406 | if (left_size) | |
11407 | { | |
11408 | int max = next_fragP->tc_frag_data.max_bytes; | |
11409 | if (max) | |
11410 | { | |
11411 | int size; | |
11412 | if (max > left_size) | |
11413 | size = left_size; | |
11414 | else | |
11415 | size = max; | |
11416 | left_size -= size; | |
11417 | next_fragP->tc_frag_data.length = size; | |
11418 | } | |
11419 | } | |
11420 | else | |
11421 | next_fragP->tc_frag_data.length = 0; | |
11422 | } | |
11423 | ||
11424 | return (fragP->tc_frag_data.length | |
11425 | - fragP->tc_frag_data.last_length); | |
11426 | } | |
11427 | return relax_frag (segment, fragP, stretch); | |
11428 | } | |
11429 | ||
ee7fcc42 AM |
11430 | /* md_estimate_size_before_relax() |
11431 | ||
11432 | Called just before relax() for rs_machine_dependent frags. The x86 | |
11433 | assembler uses these frags to handle variable size jump | |
11434 | instructions. | |
11435 | ||
11436 | Any symbol that is now undefined will not become defined. | |
11437 | Return the correct fr_subtype in the frag. | |
11438 | Return the initial "guess for variable size of frag" to caller. | |
11439 | The guess is actually the growth beyond the fixed part. Whatever | |
11440 | we do to grow the fixed or variable part contributes to our | |
11441 | returned value. */ | |
11442 | ||
252b5132 | 11443 | int |
7016a5d5 | 11444 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 11445 | { |
e379e5f3 L |
11446 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11447 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
11448 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11449 | { | |
11450 | i386_classify_machine_dependent_frag (fragP); | |
11451 | return fragP->tc_frag_data.length; | |
11452 | } | |
11453 | ||
252b5132 | 11454 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
11455 | check for un-relaxable symbols. On an ELF system, we can't relax |
11456 | an externally visible symbol, because it may be overridden by a | |
11457 | shared library. */ | |
11458 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 11459 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11460 | || (IS_ELF |
8dcea932 L |
11461 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
11462 | fragP->fr_var)) | |
fbeb56a4 DK |
11463 | #endif |
11464 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 11465 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 11466 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
11467 | #endif |
11468 | ) | |
252b5132 | 11469 | { |
b98ef147 AM |
11470 | /* Symbol is undefined in this segment, or we need to keep a |
11471 | reloc so that weak symbols can be overridden. */ | |
11472 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 11473 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
11474 | unsigned char *opcode; |
11475 | int old_fr_fix; | |
f6af82bd | 11476 | |
ee7fcc42 | 11477 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 11478 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 11479 | else if (size == 2) |
f6af82bd | 11480 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
11481 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11482 | else if (need_plt32_p (fragP->fr_symbol)) | |
11483 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
11484 | #endif | |
f6af82bd AM |
11485 | else |
11486 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 11487 | |
ee7fcc42 AM |
11488 | old_fr_fix = fragP->fr_fix; |
11489 | opcode = (unsigned char *) fragP->fr_opcode; | |
11490 | ||
fddf5b5b | 11491 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 11492 | { |
fddf5b5b AM |
11493 | case UNCOND_JUMP: |
11494 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 11495 | opcode[0] = 0xe9; |
252b5132 | 11496 | fragP->fr_fix += size; |
062cd5e7 AS |
11497 | fix_new (fragP, old_fr_fix, size, |
11498 | fragP->fr_symbol, | |
11499 | fragP->fr_offset, 1, | |
11500 | reloc_type); | |
252b5132 RH |
11501 | break; |
11502 | ||
fddf5b5b | 11503 | case COND_JUMP86: |
412167cb AM |
11504 | if (size == 2 |
11505 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
11506 | { |
11507 | /* Negate the condition, and branch past an | |
11508 | unconditional jump. */ | |
11509 | opcode[0] ^= 1; | |
11510 | opcode[1] = 3; | |
11511 | /* Insert an unconditional jump. */ | |
11512 | opcode[2] = 0xe9; | |
11513 | /* We added two extra opcode bytes, and have a two byte | |
11514 | offset. */ | |
11515 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
11516 | fix_new (fragP, old_fr_fix + 2, 2, |
11517 | fragP->fr_symbol, | |
11518 | fragP->fr_offset, 1, | |
11519 | reloc_type); | |
fddf5b5b AM |
11520 | break; |
11521 | } | |
11522 | /* Fall through. */ | |
11523 | ||
11524 | case COND_JUMP: | |
412167cb AM |
11525 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
11526 | { | |
3e02c1cc AM |
11527 | fixS *fixP; |
11528 | ||
412167cb | 11529 | fragP->fr_fix += 1; |
3e02c1cc AM |
11530 | fixP = fix_new (fragP, old_fr_fix, 1, |
11531 | fragP->fr_symbol, | |
11532 | fragP->fr_offset, 1, | |
11533 | BFD_RELOC_8_PCREL); | |
11534 | fixP->fx_signed = 1; | |
412167cb AM |
11535 | break; |
11536 | } | |
93c2a809 | 11537 | |
24eab124 | 11538 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 11539 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 11540 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 11541 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
11542 | /* We've added an opcode byte. */ |
11543 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
11544 | fix_new (fragP, old_fr_fix + 1, size, |
11545 | fragP->fr_symbol, | |
11546 | fragP->fr_offset, 1, | |
11547 | reloc_type); | |
252b5132 | 11548 | break; |
fddf5b5b AM |
11549 | |
11550 | default: | |
11551 | BAD_CASE (fragP->fr_subtype); | |
11552 | break; | |
252b5132 RH |
11553 | } |
11554 | frag_wane (fragP); | |
ee7fcc42 | 11555 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 11556 | } |
93c2a809 | 11557 | |
93c2a809 AM |
11558 | /* Guess size depending on current relax state. Initially the relax |
11559 | state will correspond to a short jump and we return 1, because | |
11560 | the variable part of the frag (the branch offset) is one byte | |
11561 | long. However, we can relax a section more than once and in that | |
11562 | case we must either set fr_subtype back to the unrelaxed state, | |
11563 | or return the value for the appropriate branch. */ | |
11564 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
11565 | } |
11566 | ||
47926f60 KH |
11567 | /* Called after relax() is finished. |
11568 | ||
11569 | In: Address of frag. | |
11570 | fr_type == rs_machine_dependent. | |
11571 | fr_subtype is what the address relaxed to. | |
11572 | ||
11573 | Out: Any fixSs and constants are set up. | |
11574 | Caller will turn frag into a ".space 0". */ | |
11575 | ||
252b5132 | 11576 | void |
7016a5d5 TG |
11577 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
11578 | fragS *fragP) | |
252b5132 | 11579 | { |
29b0f896 | 11580 | unsigned char *opcode; |
252b5132 | 11581 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
11582 | offsetT target_address; |
11583 | offsetT opcode_address; | |
252b5132 | 11584 | unsigned int extension = 0; |
847f7ad4 | 11585 | offsetT displacement_from_opcode_start; |
252b5132 | 11586 | |
e379e5f3 L |
11587 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11588 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
11589 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11590 | { | |
11591 | /* Generate nop padding. */ | |
11592 | unsigned int size = fragP->tc_frag_data.length; | |
11593 | if (size) | |
11594 | { | |
11595 | if (size > fragP->tc_frag_data.max_bytes) | |
11596 | abort (); | |
11597 | ||
11598 | if (flag_debug) | |
11599 | { | |
11600 | const char *msg; | |
11601 | const char *branch = "branch"; | |
11602 | const char *prefix = ""; | |
11603 | fragS *padding_fragP; | |
11604 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11605 | == BRANCH_PREFIX) | |
11606 | { | |
11607 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11608 | switch (fragP->tc_frag_data.default_prefix) | |
11609 | { | |
11610 | default: | |
11611 | abort (); | |
11612 | break; | |
11613 | case CS_PREFIX_OPCODE: | |
11614 | prefix = " cs"; | |
11615 | break; | |
11616 | case DS_PREFIX_OPCODE: | |
11617 | prefix = " ds"; | |
11618 | break; | |
11619 | case ES_PREFIX_OPCODE: | |
11620 | prefix = " es"; | |
11621 | break; | |
11622 | case FS_PREFIX_OPCODE: | |
11623 | prefix = " fs"; | |
11624 | break; | |
11625 | case GS_PREFIX_OPCODE: | |
11626 | prefix = " gs"; | |
11627 | break; | |
11628 | case SS_PREFIX_OPCODE: | |
11629 | prefix = " ss"; | |
11630 | break; | |
11631 | } | |
11632 | if (padding_fragP) | |
11633 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
11634 | "%s within %d-byte boundary\n"); | |
11635 | else | |
11636 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
11637 | "align %s within %d-byte boundary\n"); | |
11638 | } | |
11639 | else | |
11640 | { | |
11641 | padding_fragP = fragP; | |
11642 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
11643 | "%s within %d-byte boundary\n"); | |
11644 | } | |
11645 | ||
11646 | if (padding_fragP) | |
11647 | switch (padding_fragP->tc_frag_data.branch_type) | |
11648 | { | |
11649 | case align_branch_jcc: | |
11650 | branch = "jcc"; | |
11651 | break; | |
11652 | case align_branch_fused: | |
11653 | branch = "fused jcc"; | |
11654 | break; | |
11655 | case align_branch_jmp: | |
11656 | branch = "jmp"; | |
11657 | break; | |
11658 | case align_branch_call: | |
11659 | branch = "call"; | |
11660 | break; | |
11661 | case align_branch_indirect: | |
11662 | branch = "indiret branch"; | |
11663 | break; | |
11664 | case align_branch_ret: | |
11665 | branch = "ret"; | |
11666 | break; | |
11667 | default: | |
11668 | break; | |
11669 | } | |
11670 | ||
11671 | fprintf (stdout, msg, | |
11672 | fragP->fr_file, fragP->fr_line, size, prefix, | |
11673 | (long long) fragP->fr_address, branch, | |
11674 | 1 << align_branch_power); | |
11675 | } | |
11676 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11677 | memset (fragP->fr_opcode, | |
11678 | fragP->tc_frag_data.default_prefix, size); | |
11679 | else | |
11680 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
11681 | size, 0); | |
11682 | fragP->fr_fix += size; | |
11683 | } | |
11684 | return; | |
11685 | } | |
11686 | ||
252b5132 RH |
11687 | opcode = (unsigned char *) fragP->fr_opcode; |
11688 | ||
47926f60 | 11689 | /* Address we want to reach in file space. */ |
252b5132 | 11690 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 11691 | |
47926f60 | 11692 | /* Address opcode resides at in file space. */ |
252b5132 RH |
11693 | opcode_address = fragP->fr_address + fragP->fr_fix; |
11694 | ||
47926f60 | 11695 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
11696 | displacement_from_opcode_start = target_address - opcode_address; |
11697 | ||
fddf5b5b | 11698 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 11699 | { |
47926f60 KH |
11700 | /* Don't have to change opcode. */ |
11701 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 11702 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
11703 | } |
11704 | else | |
11705 | { | |
11706 | if (no_cond_jump_promotion | |
11707 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
11708 | as_warn_where (fragP->fr_file, fragP->fr_line, |
11709 | _("long jump required")); | |
252b5132 | 11710 | |
fddf5b5b AM |
11711 | switch (fragP->fr_subtype) |
11712 | { | |
11713 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
11714 | extension = 4; /* 1 opcode + 4 displacement */ | |
11715 | opcode[0] = 0xe9; | |
11716 | where_to_put_displacement = &opcode[1]; | |
11717 | break; | |
252b5132 | 11718 | |
fddf5b5b AM |
11719 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
11720 | extension = 2; /* 1 opcode + 2 displacement */ | |
11721 | opcode[0] = 0xe9; | |
11722 | where_to_put_displacement = &opcode[1]; | |
11723 | break; | |
252b5132 | 11724 | |
fddf5b5b AM |
11725 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
11726 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
11727 | extension = 5; /* 2 opcode + 4 displacement */ | |
11728 | opcode[1] = opcode[0] + 0x10; | |
11729 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11730 | where_to_put_displacement = &opcode[2]; | |
11731 | break; | |
252b5132 | 11732 | |
fddf5b5b AM |
11733 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
11734 | extension = 3; /* 2 opcode + 2 displacement */ | |
11735 | opcode[1] = opcode[0] + 0x10; | |
11736 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11737 | where_to_put_displacement = &opcode[2]; | |
11738 | break; | |
252b5132 | 11739 | |
fddf5b5b AM |
11740 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
11741 | extension = 4; | |
11742 | opcode[0] ^= 1; | |
11743 | opcode[1] = 3; | |
11744 | opcode[2] = 0xe9; | |
11745 | where_to_put_displacement = &opcode[3]; | |
11746 | break; | |
11747 | ||
11748 | default: | |
11749 | BAD_CASE (fragP->fr_subtype); | |
11750 | break; | |
11751 | } | |
252b5132 | 11752 | } |
fddf5b5b | 11753 | |
7b81dfbb AJ |
11754 | /* If size if less then four we are sure that the operand fits, |
11755 | but if it's 4, then it could be that the displacement is larger | |
11756 | then -/+ 2GB. */ | |
11757 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
11758 | && object_64bit | |
11759 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
11760 | + ((addressT) 1 << 31)) |
11761 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
11762 | { |
11763 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
11764 | _("jump target out of range")); | |
11765 | /* Make us emit 0. */ | |
11766 | displacement_from_opcode_start = extension; | |
11767 | } | |
47926f60 | 11768 | /* Now put displacement after opcode. */ |
252b5132 RH |
11769 | md_number_to_chars ((char *) where_to_put_displacement, |
11770 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 11771 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
11772 | fragP->fr_fix += extension; |
11773 | } | |
11774 | \f | |
7016a5d5 | 11775 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
11776 | by our caller that we have all the info we need to fix it up. |
11777 | ||
7016a5d5 TG |
11778 | Parameter valP is the pointer to the value of the bits. |
11779 | ||
252b5132 RH |
11780 | On the 386, immediates, displacements, and data pointers are all in |
11781 | the same (little-endian) format, so we don't need to care about which | |
11782 | we are handling. */ | |
11783 | ||
94f592af | 11784 | void |
7016a5d5 | 11785 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11786 | { |
94f592af | 11787 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 11788 | valueT value = *valP; |
252b5132 | 11789 | |
f86103b7 | 11790 | #if !defined (TE_Mach) |
93382f6d AM |
11791 | if (fixP->fx_pcrel) |
11792 | { | |
11793 | switch (fixP->fx_r_type) | |
11794 | { | |
5865bb77 ILT |
11795 | default: |
11796 | break; | |
11797 | ||
d6ab8113 JB |
11798 | case BFD_RELOC_64: |
11799 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
11800 | break; | |
93382f6d | 11801 | case BFD_RELOC_32: |
ae8887b5 | 11802 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
11803 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
11804 | break; | |
11805 | case BFD_RELOC_16: | |
11806 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
11807 | break; | |
11808 | case BFD_RELOC_8: | |
11809 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
11810 | break; | |
11811 | } | |
11812 | } | |
252b5132 | 11813 | |
a161fe53 | 11814 | if (fixP->fx_addsy != NULL |
31312f95 | 11815 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 11816 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 11817 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 11818 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 11819 | && !use_rela_relocations) |
252b5132 | 11820 | { |
31312f95 AM |
11821 | /* This is a hack. There should be a better way to handle this. |
11822 | This covers for the fact that bfd_install_relocation will | |
11823 | subtract the current location (for partial_inplace, PC relative | |
11824 | relocations); see more below. */ | |
252b5132 | 11825 | #ifndef OBJ_AOUT |
718ddfc0 | 11826 | if (IS_ELF |
252b5132 RH |
11827 | #ifdef TE_PE |
11828 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
11829 | #endif | |
11830 | ) | |
11831 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11832 | #endif | |
11833 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 11834 | if (IS_ELF) |
252b5132 | 11835 | { |
6539b54b | 11836 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 11837 | |
6539b54b | 11838 | if ((sym_seg == seg |
2f66722d | 11839 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 11840 | && sym_seg != absolute_section)) |
af65af87 | 11841 | && !generic_force_reloc (fixP)) |
2f66722d AM |
11842 | { |
11843 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
11844 | bfd_install_relocation subtracts them out again. I think |
11845 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
11846 | it. FIXME. */ |
11847 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11848 | } | |
252b5132 RH |
11849 | } |
11850 | #endif | |
11851 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
11852 | /* For some reason, the PE format does not store a |
11853 | section address offset for a PC relative symbol. */ | |
11854 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 11855 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
11856 | value += md_pcrel_from (fixP); |
11857 | #endif | |
11858 | } | |
fbeb56a4 | 11859 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
11860 | if (fixP->fx_addsy != NULL |
11861 | && S_IS_WEAK (fixP->fx_addsy) | |
11862 | /* PR 16858: Do not modify weak function references. */ | |
11863 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 11864 | { |
296a8689 NC |
11865 | #if !defined (TE_PEP) |
11866 | /* For x86 PE weak function symbols are neither PC-relative | |
11867 | nor do they set S_IS_FUNCTION. So the only reliable way | |
11868 | to detect them is to check the flags of their containing | |
11869 | section. */ | |
11870 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
11871 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
11872 | ; | |
11873 | else | |
11874 | #endif | |
fbeb56a4 DK |
11875 | value -= S_GET_VALUE (fixP->fx_addsy); |
11876 | } | |
11877 | #endif | |
252b5132 RH |
11878 | |
11879 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 11880 | and we must not disappoint it. */ |
252b5132 | 11881 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11882 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
11883 | switch (fixP->fx_r_type) |
11884 | { | |
11885 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 11886 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
11887 | /* Make the jump instruction point to the address of the operand. |
11888 | At runtime we merely add the offset to the actual PLT entry. | |
11889 | NB: Subtract the offset size only for jump instructions. */ | |
11890 | if (fixP->fx_pcrel) | |
11891 | value = -4; | |
47926f60 | 11892 | break; |
31312f95 | 11893 | |
13ae64f3 JJ |
11894 | case BFD_RELOC_386_TLS_GD: |
11895 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 11896 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
11897 | case BFD_RELOC_386_TLS_IE: |
11898 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 11899 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
11900 | case BFD_RELOC_X86_64_TLSGD: |
11901 | case BFD_RELOC_X86_64_TLSLD: | |
11902 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 11903 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
11904 | value = 0; /* Fully resolved at runtime. No addend. */ |
11905 | /* Fallthrough */ | |
11906 | case BFD_RELOC_386_TLS_LE: | |
11907 | case BFD_RELOC_386_TLS_LDO_32: | |
11908 | case BFD_RELOC_386_TLS_LE_32: | |
11909 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11910 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 11911 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 11912 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
11913 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
11914 | break; | |
11915 | ||
67a4f2b7 AO |
11916 | case BFD_RELOC_386_TLS_DESC_CALL: |
11917 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
11918 | value = 0; /* Fully resolved at runtime. No addend. */ | |
11919 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11920 | fixP->fx_done = 0; | |
11921 | return; | |
11922 | ||
47926f60 KH |
11923 | case BFD_RELOC_VTABLE_INHERIT: |
11924 | case BFD_RELOC_VTABLE_ENTRY: | |
11925 | fixP->fx_done = 0; | |
94f592af | 11926 | return; |
47926f60 KH |
11927 | |
11928 | default: | |
11929 | break; | |
11930 | } | |
11931 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 11932 | *valP = value; |
f86103b7 | 11933 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 11934 | |
3e73aa7c | 11935 | /* Are we finished with this relocation now? */ |
c6682705 | 11936 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 11937 | fixP->fx_done = 1; |
fbeb56a4 DK |
11938 | #if defined (OBJ_COFF) && defined (TE_PE) |
11939 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
11940 | { | |
11941 | fixP->fx_done = 0; | |
11942 | /* Remember value for tc_gen_reloc. */ | |
11943 | fixP->fx_addnumber = value; | |
11944 | /* Clear out the frag for now. */ | |
11945 | value = 0; | |
11946 | } | |
11947 | #endif | |
3e73aa7c JH |
11948 | else if (use_rela_relocations) |
11949 | { | |
11950 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
11951 | /* Remember value for tc_gen_reloc. */ |
11952 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
11953 | value = 0; |
11954 | } | |
f86103b7 | 11955 | |
94f592af | 11956 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 11957 | } |
252b5132 | 11958 | \f |
6d4af3c2 | 11959 | const char * |
499ac353 | 11960 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11961 | { |
499ac353 NC |
11962 | /* This outputs the LITTLENUMs in REVERSE order; |
11963 | in accord with the bigendian 386. */ | |
11964 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
11965 | } |
11966 | \f | |
2d545b82 | 11967 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 11968 | |
252b5132 | 11969 | static char * |
e3bb37b5 | 11970 | output_invalid (int c) |
252b5132 | 11971 | { |
3882b010 | 11972 | if (ISPRINT (c)) |
f9f21a03 L |
11973 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
11974 | "'%c'", c); | |
252b5132 | 11975 | else |
f9f21a03 | 11976 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 11977 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
11978 | return output_invalid_buf; |
11979 | } | |
11980 | ||
af6bdddf | 11981 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
11982 | |
11983 | static const reg_entry * | |
4d1bb795 | 11984 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 11985 | { |
af6bdddf AM |
11986 | char *s = reg_string; |
11987 | char *p; | |
252b5132 RH |
11988 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
11989 | const reg_entry *r; | |
11990 | ||
11991 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
11992 | if (*s == REGISTER_PREFIX) | |
11993 | ++s; | |
11994 | ||
11995 | if (is_space_char (*s)) | |
11996 | ++s; | |
11997 | ||
11998 | p = reg_name_given; | |
af6bdddf | 11999 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
12000 | { |
12001 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
12002 | return (const reg_entry *) NULL; |
12003 | s++; | |
252b5132 RH |
12004 | } |
12005 | ||
6588847e DN |
12006 | /* For naked regs, make sure that we are not dealing with an identifier. |
12007 | This prevents confusing an identifier like `eax_var' with register | |
12008 | `eax'. */ | |
12009 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
12010 | return (const reg_entry *) NULL; | |
12011 | ||
af6bdddf | 12012 | *end_op = s; |
252b5132 RH |
12013 | |
12014 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
12015 | ||
5f47d35b | 12016 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 12017 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 12018 | { |
0e0eea78 JB |
12019 | if (!cpu_arch_flags.bitfield.cpu8087 |
12020 | && !cpu_arch_flags.bitfield.cpu287 | |
12021 | && !cpu_arch_flags.bitfield.cpu387) | |
12022 | return (const reg_entry *) NULL; | |
12023 | ||
5f47d35b AM |
12024 | if (is_space_char (*s)) |
12025 | ++s; | |
12026 | if (*s == '(') | |
12027 | { | |
af6bdddf | 12028 | ++s; |
5f47d35b AM |
12029 | if (is_space_char (*s)) |
12030 | ++s; | |
12031 | if (*s >= '0' && *s <= '7') | |
12032 | { | |
db557034 | 12033 | int fpr = *s - '0'; |
af6bdddf | 12034 | ++s; |
5f47d35b AM |
12035 | if (is_space_char (*s)) |
12036 | ++s; | |
12037 | if (*s == ')') | |
12038 | { | |
12039 | *end_op = s + 1; | |
1e9cc1c2 | 12040 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
12041 | know (r); |
12042 | return r + fpr; | |
5f47d35b | 12043 | } |
5f47d35b | 12044 | } |
47926f60 | 12045 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12046 | return (const reg_entry *) NULL; |
12047 | } | |
12048 | } | |
12049 | ||
a60de03c JB |
12050 | if (r == NULL || allow_pseudo_reg) |
12051 | return r; | |
12052 | ||
0dfbf9d7 | 12053 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
12054 | return (const reg_entry *) NULL; |
12055 | ||
dc821c5f | 12056 | if ((r->reg_type.bitfield.dword |
00cee14f | 12057 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
12058 | || r->reg_type.bitfield.class == RegCR |
12059 | || r->reg_type.bitfield.class == RegDR | |
12060 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
12061 | && !cpu_arch_flags.bitfield.cpui386) |
12062 | return (const reg_entry *) NULL; | |
12063 | ||
3528c362 | 12064 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
12065 | return (const reg_entry *) NULL; |
12066 | ||
6e041cf4 JB |
12067 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
12068 | { | |
f74a6307 JB |
12069 | if (r->reg_type.bitfield.zmmword |
12070 | || r->reg_type.bitfield.class == RegMask) | |
6e041cf4 | 12071 | return (const reg_entry *) NULL; |
40f12533 | 12072 | |
6e041cf4 JB |
12073 | if (!cpu_arch_flags.bitfield.cpuavx) |
12074 | { | |
12075 | if (r->reg_type.bitfield.ymmword) | |
12076 | return (const reg_entry *) NULL; | |
1848e567 | 12077 | |
6e041cf4 JB |
12078 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
12079 | return (const reg_entry *) NULL; | |
12080 | } | |
12081 | } | |
43234a1e | 12082 | |
f74a6307 | 12083 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
1adf7f56 JB |
12084 | return (const reg_entry *) NULL; |
12085 | ||
db51cc60 | 12086 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 12087 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
12088 | return (const reg_entry *) NULL; |
12089 | ||
1d3f8286 JB |
12090 | /* Upper 16 vector registers are only available with VREX in 64bit |
12091 | mode, and require EVEX encoding. */ | |
12092 | if (r->reg_flags & RegVRex) | |
43234a1e | 12093 | { |
e951d5ca | 12094 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
12095 | || flag_code != CODE_64BIT) |
12096 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
12097 | |
12098 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
12099 | } |
12100 | ||
4787f4a5 | 12101 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 12102 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 12103 | && flag_code != CODE_64BIT) |
20f0a1fc | 12104 | return (const reg_entry *) NULL; |
1ae00879 | 12105 | |
00cee14f JB |
12106 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
12107 | && !intel_syntax) | |
b7240065 JB |
12108 | return (const reg_entry *) NULL; |
12109 | ||
252b5132 RH |
12110 | return r; |
12111 | } | |
4d1bb795 JB |
12112 | |
12113 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12114 | ||
12115 | static const reg_entry * | |
12116 | parse_register (char *reg_string, char **end_op) | |
12117 | { | |
12118 | const reg_entry *r; | |
12119 | ||
12120 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12121 | r = parse_real_register (reg_string, end_op); | |
12122 | else | |
12123 | r = NULL; | |
12124 | if (!r) | |
12125 | { | |
12126 | char *save = input_line_pointer; | |
12127 | char c; | |
12128 | symbolS *symbolP; | |
12129 | ||
12130 | input_line_pointer = reg_string; | |
d02603dc | 12131 | c = get_symbol_name (®_string); |
4d1bb795 JB |
12132 | symbolP = symbol_find (reg_string); |
12133 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
12134 | { | |
12135 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12136 | ||
0398aac5 | 12137 | know (e->X_op == O_register); |
4eed87de | 12138 | know (e->X_add_number >= 0 |
c3fe08fa | 12139 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 12140 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 12141 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 12142 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
12143 | *end_op = input_line_pointer; |
12144 | } | |
12145 | *input_line_pointer = c; | |
12146 | input_line_pointer = save; | |
12147 | } | |
12148 | return r; | |
12149 | } | |
12150 | ||
12151 | int | |
12152 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12153 | { | |
12154 | const reg_entry *r; | |
12155 | char *end = input_line_pointer; | |
12156 | ||
12157 | *end = *nextcharP; | |
12158 | r = parse_register (name, &input_line_pointer); | |
12159 | if (r && end <= input_line_pointer) | |
12160 | { | |
12161 | *nextcharP = *input_line_pointer; | |
12162 | *input_line_pointer = 0; | |
12163 | e->X_op = O_register; | |
12164 | e->X_add_number = r - i386_regtab; | |
12165 | return 1; | |
12166 | } | |
12167 | input_line_pointer = end; | |
12168 | *end = 0; | |
ee86248c | 12169 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
12170 | } |
12171 | ||
12172 | void | |
12173 | md_operand (expressionS *e) | |
12174 | { | |
ee86248c JB |
12175 | char *end; |
12176 | const reg_entry *r; | |
4d1bb795 | 12177 | |
ee86248c JB |
12178 | switch (*input_line_pointer) |
12179 | { | |
12180 | case REGISTER_PREFIX: | |
12181 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
12182 | if (r) |
12183 | { | |
12184 | e->X_op = O_register; | |
12185 | e->X_add_number = r - i386_regtab; | |
12186 | input_line_pointer = end; | |
12187 | } | |
ee86248c JB |
12188 | break; |
12189 | ||
12190 | case '[': | |
9c2799c2 | 12191 | gas_assert (intel_syntax); |
ee86248c JB |
12192 | end = input_line_pointer++; |
12193 | expression (e); | |
12194 | if (*input_line_pointer == ']') | |
12195 | { | |
12196 | ++input_line_pointer; | |
12197 | e->X_op_symbol = make_expr_symbol (e); | |
12198 | e->X_add_symbol = NULL; | |
12199 | e->X_add_number = 0; | |
12200 | e->X_op = O_index; | |
12201 | } | |
12202 | else | |
12203 | { | |
12204 | e->X_op = O_absent; | |
12205 | input_line_pointer = end; | |
12206 | } | |
12207 | break; | |
4d1bb795 JB |
12208 | } |
12209 | } | |
12210 | ||
252b5132 | 12211 | \f |
4cc782b5 | 12212 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12213 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12214 | #else |
b6f8c7c4 | 12215 | const char *md_shortopts = "qnO::"; |
252b5132 | 12216 | #endif |
6e0b89ee | 12217 | |
3e73aa7c | 12218 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12219 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12220 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12221 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12222 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12223 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12224 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12225 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12226 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12227 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12228 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12229 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12230 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12231 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12232 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12233 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12234 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12235 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 12236 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 12237 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 12238 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 12239 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
12240 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
12241 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 12242 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 12243 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 12244 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
12245 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
12246 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
12247 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 12248 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
b3b91714 | 12249 | |
99ad8390 NC |
12250 | struct option md_longopts[] = |
12251 | { | |
3e73aa7c | 12252 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 12253 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12254 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 12255 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
12256 | #endif |
12257 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 12258 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 12259 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 12260 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 12261 | #endif |
b3b91714 | 12262 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
12263 | {"march", required_argument, NULL, OPTION_MARCH}, |
12264 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
12265 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
12266 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
12267 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
12268 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 12269 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 12270 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 12271 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 12272 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 12273 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 12274 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
12275 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
12276 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
12277 | # if defined (TE_PE) || defined (TE_PEP) |
12278 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
12279 | #endif | |
d1982f93 | 12280 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 12281 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 12282 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 12283 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
12284 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
12285 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
12286 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 12287 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
5db04b09 L |
12288 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
12289 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
12290 | {NULL, no_argument, NULL, 0} |
12291 | }; | |
12292 | size_t md_longopts_size = sizeof (md_longopts); | |
12293 | ||
12294 | int | |
17b9d67d | 12295 | md_parse_option (int c, const char *arg) |
252b5132 | 12296 | { |
91d6fa6a | 12297 | unsigned int j; |
e379e5f3 | 12298 | char *arch, *next, *saved, *type; |
9103f4f4 | 12299 | |
252b5132 RH |
12300 | switch (c) |
12301 | { | |
12b55ccc L |
12302 | case 'n': |
12303 | optimize_align_code = 0; | |
12304 | break; | |
12305 | ||
a38cf1db AM |
12306 | case 'q': |
12307 | quiet_warnings = 1; | |
252b5132 RH |
12308 | break; |
12309 | ||
12310 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
12311 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
12312 | should be emitted or not. FIXME: Not implemented. */ | |
12313 | case 'Q': | |
d4693039 JB |
12314 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
12315 | return 0; | |
252b5132 RH |
12316 | break; |
12317 | ||
12318 | /* -V: SVR4 argument to print version ID. */ | |
12319 | case 'V': | |
12320 | print_version_id (); | |
12321 | break; | |
12322 | ||
a38cf1db AM |
12323 | /* -k: Ignore for FreeBSD compatibility. */ |
12324 | case 'k': | |
252b5132 | 12325 | break; |
4cc782b5 ILT |
12326 | |
12327 | case 's': | |
12328 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 12329 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 12330 | break; |
8dcea932 L |
12331 | |
12332 | case OPTION_MSHARED: | |
12333 | shared = 1; | |
12334 | break; | |
b4a3a7b4 L |
12335 | |
12336 | case OPTION_X86_USED_NOTE: | |
12337 | if (strcasecmp (arg, "yes") == 0) | |
12338 | x86_used_note = 1; | |
12339 | else if (strcasecmp (arg, "no") == 0) | |
12340 | x86_used_note = 0; | |
12341 | else | |
12342 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
12343 | break; | |
12344 | ||
12345 | ||
99ad8390 | 12346 | #endif |
321098a5 | 12347 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12348 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
12349 | case OPTION_64: |
12350 | { | |
12351 | const char **list, **l; | |
12352 | ||
3e73aa7c JH |
12353 | list = bfd_target_list (); |
12354 | for (l = list; *l != NULL; l++) | |
8620418b | 12355 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
12356 | || strcmp (*l, "coff-x86-64") == 0 |
12357 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
12358 | || strcmp (*l, "pei-x86-64") == 0 |
12359 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
12360 | { |
12361 | default_arch = "x86_64"; | |
12362 | break; | |
12363 | } | |
3e73aa7c | 12364 | if (*l == NULL) |
2b5d6a91 | 12365 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
12366 | free (list); |
12367 | } | |
12368 | break; | |
12369 | #endif | |
252b5132 | 12370 | |
351f65ca | 12371 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 12372 | case OPTION_X32: |
351f65ca L |
12373 | if (IS_ELF) |
12374 | { | |
12375 | const char **list, **l; | |
12376 | ||
12377 | list = bfd_target_list (); | |
12378 | for (l = list; *l != NULL; l++) | |
12379 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
12380 | { | |
12381 | default_arch = "x86_64:32"; | |
12382 | break; | |
12383 | } | |
12384 | if (*l == NULL) | |
2b5d6a91 | 12385 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
12386 | free (list); |
12387 | } | |
12388 | else | |
12389 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
12390 | break; | |
12391 | #endif | |
12392 | ||
6e0b89ee AM |
12393 | case OPTION_32: |
12394 | default_arch = "i386"; | |
12395 | break; | |
12396 | ||
b3b91714 AM |
12397 | case OPTION_DIVIDE: |
12398 | #ifdef SVR4_COMMENT_CHARS | |
12399 | { | |
12400 | char *n, *t; | |
12401 | const char *s; | |
12402 | ||
add39d23 | 12403 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
12404 | t = n; |
12405 | for (s = i386_comment_chars; *s != '\0'; s++) | |
12406 | if (*s != '/') | |
12407 | *t++ = *s; | |
12408 | *t = '\0'; | |
12409 | i386_comment_chars = n; | |
12410 | } | |
12411 | #endif | |
12412 | break; | |
12413 | ||
9103f4f4 | 12414 | case OPTION_MARCH: |
293f5f65 L |
12415 | saved = xstrdup (arg); |
12416 | arch = saved; | |
12417 | /* Allow -march=+nosse. */ | |
12418 | if (*arch == '+') | |
12419 | arch++; | |
6305a203 | 12420 | do |
9103f4f4 | 12421 | { |
6305a203 | 12422 | if (*arch == '.') |
2b5d6a91 | 12423 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12424 | next = strchr (arch, '+'); |
12425 | if (next) | |
12426 | *next++ = '\0'; | |
91d6fa6a | 12427 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12428 | { |
91d6fa6a | 12429 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 12430 | { |
6305a203 | 12431 | /* Processor. */ |
1ded5609 JB |
12432 | if (! cpu_arch[j].flags.bitfield.cpui386) |
12433 | continue; | |
12434 | ||
91d6fa6a | 12435 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 12436 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
12437 | cpu_arch_flags = cpu_arch[j].flags; |
12438 | cpu_arch_isa = cpu_arch[j].type; | |
12439 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
12440 | if (!cpu_arch_tune_set) |
12441 | { | |
12442 | cpu_arch_tune = cpu_arch_isa; | |
12443 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12444 | } | |
12445 | break; | |
12446 | } | |
91d6fa6a NC |
12447 | else if (*cpu_arch [j].name == '.' |
12448 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 12449 | { |
33eaf5de | 12450 | /* ISA extension. */ |
6305a203 | 12451 | i386_cpu_flags flags; |
309d3373 | 12452 | |
293f5f65 L |
12453 | flags = cpu_flags_or (cpu_arch_flags, |
12454 | cpu_arch[j].flags); | |
81486035 | 12455 | |
5b64d091 | 12456 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
12457 | { |
12458 | if (cpu_sub_arch_name) | |
12459 | { | |
12460 | char *name = cpu_sub_arch_name; | |
12461 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 12462 | cpu_arch[j].name, |
1bf57e9f | 12463 | (const char *) NULL); |
6305a203 L |
12464 | free (name); |
12465 | } | |
12466 | else | |
91d6fa6a | 12467 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 12468 | cpu_arch_flags = flags; |
a586129e | 12469 | cpu_arch_isa_flags = flags; |
6305a203 | 12470 | } |
0089dace L |
12471 | else |
12472 | cpu_arch_isa_flags | |
12473 | = cpu_flags_or (cpu_arch_isa_flags, | |
12474 | cpu_arch[j].flags); | |
6305a203 | 12475 | break; |
ccc9c027 | 12476 | } |
9103f4f4 | 12477 | } |
6305a203 | 12478 | |
293f5f65 L |
12479 | if (j >= ARRAY_SIZE (cpu_arch)) |
12480 | { | |
33eaf5de | 12481 | /* Disable an ISA extension. */ |
293f5f65 L |
12482 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
12483 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
12484 | { | |
12485 | i386_cpu_flags flags; | |
12486 | ||
12487 | flags = cpu_flags_and_not (cpu_arch_flags, | |
12488 | cpu_noarch[j].flags); | |
12489 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
12490 | { | |
12491 | if (cpu_sub_arch_name) | |
12492 | { | |
12493 | char *name = cpu_sub_arch_name; | |
12494 | cpu_sub_arch_name = concat (arch, | |
12495 | (const char *) NULL); | |
12496 | free (name); | |
12497 | } | |
12498 | else | |
12499 | cpu_sub_arch_name = xstrdup (arch); | |
12500 | cpu_arch_flags = flags; | |
12501 | cpu_arch_isa_flags = flags; | |
12502 | } | |
12503 | break; | |
12504 | } | |
12505 | ||
12506 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
12507 | j = ARRAY_SIZE (cpu_arch); | |
12508 | } | |
12509 | ||
91d6fa6a | 12510 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12511 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12512 | |
12513 | arch = next; | |
9103f4f4 | 12514 | } |
293f5f65 L |
12515 | while (next != NULL); |
12516 | free (saved); | |
9103f4f4 L |
12517 | break; |
12518 | ||
12519 | case OPTION_MTUNE: | |
12520 | if (*arg == '.') | |
2b5d6a91 | 12521 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 12522 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12523 | { |
91d6fa6a | 12524 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 12525 | { |
ccc9c027 | 12526 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
12527 | cpu_arch_tune = cpu_arch [j].type; |
12528 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
12529 | break; |
12530 | } | |
12531 | } | |
91d6fa6a | 12532 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12533 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
12534 | break; |
12535 | ||
1efbbeb4 L |
12536 | case OPTION_MMNEMONIC: |
12537 | if (strcasecmp (arg, "att") == 0) | |
12538 | intel_mnemonic = 0; | |
12539 | else if (strcasecmp (arg, "intel") == 0) | |
12540 | intel_mnemonic = 1; | |
12541 | else | |
2b5d6a91 | 12542 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
12543 | break; |
12544 | ||
12545 | case OPTION_MSYNTAX: | |
12546 | if (strcasecmp (arg, "att") == 0) | |
12547 | intel_syntax = 0; | |
12548 | else if (strcasecmp (arg, "intel") == 0) | |
12549 | intel_syntax = 1; | |
12550 | else | |
2b5d6a91 | 12551 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
12552 | break; |
12553 | ||
12554 | case OPTION_MINDEX_REG: | |
12555 | allow_index_reg = 1; | |
12556 | break; | |
12557 | ||
12558 | case OPTION_MNAKED_REG: | |
12559 | allow_naked_reg = 1; | |
12560 | break; | |
12561 | ||
c0f3af97 L |
12562 | case OPTION_MSSE2AVX: |
12563 | sse2avx = 1; | |
12564 | break; | |
12565 | ||
daf50ae7 L |
12566 | case OPTION_MSSE_CHECK: |
12567 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 12568 | sse_check = check_error; |
daf50ae7 | 12569 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 12570 | sse_check = check_warning; |
daf50ae7 | 12571 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 12572 | sse_check = check_none; |
daf50ae7 | 12573 | else |
2b5d6a91 | 12574 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
12575 | break; |
12576 | ||
7bab8ab5 JB |
12577 | case OPTION_MOPERAND_CHECK: |
12578 | if (strcasecmp (arg, "error") == 0) | |
12579 | operand_check = check_error; | |
12580 | else if (strcasecmp (arg, "warning") == 0) | |
12581 | operand_check = check_warning; | |
12582 | else if (strcasecmp (arg, "none") == 0) | |
12583 | operand_check = check_none; | |
12584 | else | |
12585 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
12586 | break; | |
12587 | ||
539f890d L |
12588 | case OPTION_MAVXSCALAR: |
12589 | if (strcasecmp (arg, "128") == 0) | |
12590 | avxscalar = vex128; | |
12591 | else if (strcasecmp (arg, "256") == 0) | |
12592 | avxscalar = vex256; | |
12593 | else | |
2b5d6a91 | 12594 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
12595 | break; |
12596 | ||
03751133 L |
12597 | case OPTION_MVEXWIG: |
12598 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 12599 | vexwig = vexw0; |
03751133 | 12600 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 12601 | vexwig = vexw1; |
03751133 L |
12602 | else |
12603 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
12604 | break; | |
12605 | ||
7e8b059b L |
12606 | case OPTION_MADD_BND_PREFIX: |
12607 | add_bnd_prefix = 1; | |
12608 | break; | |
12609 | ||
43234a1e L |
12610 | case OPTION_MEVEXLIG: |
12611 | if (strcmp (arg, "128") == 0) | |
12612 | evexlig = evexl128; | |
12613 | else if (strcmp (arg, "256") == 0) | |
12614 | evexlig = evexl256; | |
12615 | else if (strcmp (arg, "512") == 0) | |
12616 | evexlig = evexl512; | |
12617 | else | |
12618 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
12619 | break; | |
12620 | ||
d3d3c6db IT |
12621 | case OPTION_MEVEXRCIG: |
12622 | if (strcmp (arg, "rne") == 0) | |
12623 | evexrcig = rne; | |
12624 | else if (strcmp (arg, "rd") == 0) | |
12625 | evexrcig = rd; | |
12626 | else if (strcmp (arg, "ru") == 0) | |
12627 | evexrcig = ru; | |
12628 | else if (strcmp (arg, "rz") == 0) | |
12629 | evexrcig = rz; | |
12630 | else | |
12631 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
12632 | break; | |
12633 | ||
43234a1e L |
12634 | case OPTION_MEVEXWIG: |
12635 | if (strcmp (arg, "0") == 0) | |
12636 | evexwig = evexw0; | |
12637 | else if (strcmp (arg, "1") == 0) | |
12638 | evexwig = evexw1; | |
12639 | else | |
12640 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
12641 | break; | |
12642 | ||
167ad85b TG |
12643 | # if defined (TE_PE) || defined (TE_PEP) |
12644 | case OPTION_MBIG_OBJ: | |
12645 | use_big_obj = 1; | |
12646 | break; | |
12647 | #endif | |
12648 | ||
d1982f93 | 12649 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
12650 | if (strcasecmp (arg, "yes") == 0) |
12651 | omit_lock_prefix = 1; | |
12652 | else if (strcasecmp (arg, "no") == 0) | |
12653 | omit_lock_prefix = 0; | |
12654 | else | |
12655 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
12656 | break; | |
12657 | ||
e4e00185 AS |
12658 | case OPTION_MFENCE_AS_LOCK_ADD: |
12659 | if (strcasecmp (arg, "yes") == 0) | |
12660 | avoid_fence = 1; | |
12661 | else if (strcasecmp (arg, "no") == 0) | |
12662 | avoid_fence = 0; | |
12663 | else | |
12664 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
12665 | break; | |
12666 | ||
0cb4071e L |
12667 | case OPTION_MRELAX_RELOCATIONS: |
12668 | if (strcasecmp (arg, "yes") == 0) | |
12669 | generate_relax_relocations = 1; | |
12670 | else if (strcasecmp (arg, "no") == 0) | |
12671 | generate_relax_relocations = 0; | |
12672 | else | |
12673 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
12674 | break; | |
12675 | ||
e379e5f3 L |
12676 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
12677 | { | |
12678 | char *end; | |
12679 | long int align = strtoul (arg, &end, 0); | |
12680 | if (*end == '\0') | |
12681 | { | |
12682 | if (align == 0) | |
12683 | { | |
12684 | align_branch_power = 0; | |
12685 | break; | |
12686 | } | |
12687 | else if (align >= 16) | |
12688 | { | |
12689 | int align_power; | |
12690 | for (align_power = 0; | |
12691 | (align & 1) == 0; | |
12692 | align >>= 1, align_power++) | |
12693 | continue; | |
12694 | /* Limit alignment power to 31. */ | |
12695 | if (align == 1 && align_power < 32) | |
12696 | { | |
12697 | align_branch_power = align_power; | |
12698 | break; | |
12699 | } | |
12700 | } | |
12701 | } | |
12702 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
12703 | } | |
12704 | break; | |
12705 | ||
12706 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
12707 | { | |
12708 | char *end; | |
12709 | int align = strtoul (arg, &end, 0); | |
12710 | /* Some processors only support 5 prefixes. */ | |
12711 | if (*end == '\0' && align >= 0 && align < 6) | |
12712 | { | |
12713 | align_branch_prefix_size = align; | |
12714 | break; | |
12715 | } | |
12716 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
12717 | arg); | |
12718 | } | |
12719 | break; | |
12720 | ||
12721 | case OPTION_MALIGN_BRANCH: | |
12722 | align_branch = 0; | |
12723 | saved = xstrdup (arg); | |
12724 | type = saved; | |
12725 | do | |
12726 | { | |
12727 | next = strchr (type, '+'); | |
12728 | if (next) | |
12729 | *next++ = '\0'; | |
12730 | if (strcasecmp (type, "jcc") == 0) | |
12731 | align_branch |= align_branch_jcc_bit; | |
12732 | else if (strcasecmp (type, "fused") == 0) | |
12733 | align_branch |= align_branch_fused_bit; | |
12734 | else if (strcasecmp (type, "jmp") == 0) | |
12735 | align_branch |= align_branch_jmp_bit; | |
12736 | else if (strcasecmp (type, "call") == 0) | |
12737 | align_branch |= align_branch_call_bit; | |
12738 | else if (strcasecmp (type, "ret") == 0) | |
12739 | align_branch |= align_branch_ret_bit; | |
12740 | else if (strcasecmp (type, "indirect") == 0) | |
12741 | align_branch |= align_branch_indirect_bit; | |
12742 | else | |
12743 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
12744 | type = next; | |
12745 | } | |
12746 | while (next != NULL); | |
12747 | free (saved); | |
12748 | break; | |
12749 | ||
76cf450b L |
12750 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
12751 | align_branch_power = 5; | |
12752 | align_branch_prefix_size = 5; | |
12753 | align_branch = (align_branch_jcc_bit | |
12754 | | align_branch_fused_bit | |
12755 | | align_branch_jmp_bit); | |
12756 | break; | |
12757 | ||
5db04b09 | 12758 | case OPTION_MAMD64: |
4b5aaf5f | 12759 | isa64 = amd64; |
5db04b09 L |
12760 | break; |
12761 | ||
12762 | case OPTION_MINTEL64: | |
4b5aaf5f | 12763 | isa64 = intel64; |
5db04b09 L |
12764 | break; |
12765 | ||
b6f8c7c4 L |
12766 | case 'O': |
12767 | if (arg == NULL) | |
12768 | { | |
12769 | optimize = 1; | |
12770 | /* Turn off -Os. */ | |
12771 | optimize_for_space = 0; | |
12772 | } | |
12773 | else if (*arg == 's') | |
12774 | { | |
12775 | optimize_for_space = 1; | |
12776 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 12777 | optimize = INT_MAX; |
b6f8c7c4 L |
12778 | } |
12779 | else | |
12780 | { | |
12781 | optimize = atoi (arg); | |
12782 | /* Turn off -Os. */ | |
12783 | optimize_for_space = 0; | |
12784 | } | |
12785 | break; | |
12786 | ||
252b5132 RH |
12787 | default: |
12788 | return 0; | |
12789 | } | |
12790 | return 1; | |
12791 | } | |
12792 | ||
8a2c8fef L |
12793 | #define MESSAGE_TEMPLATE \ |
12794 | " " | |
12795 | ||
293f5f65 L |
12796 | static char * |
12797 | output_message (FILE *stream, char *p, char *message, char *start, | |
12798 | int *left_p, const char *name, int len) | |
12799 | { | |
12800 | int size = sizeof (MESSAGE_TEMPLATE); | |
12801 | int left = *left_p; | |
12802 | ||
12803 | /* Reserve 2 spaces for ", " or ",\0" */ | |
12804 | left -= len + 2; | |
12805 | ||
12806 | /* Check if there is any room. */ | |
12807 | if (left >= 0) | |
12808 | { | |
12809 | if (p != start) | |
12810 | { | |
12811 | *p++ = ','; | |
12812 | *p++ = ' '; | |
12813 | } | |
12814 | p = mempcpy (p, name, len); | |
12815 | } | |
12816 | else | |
12817 | { | |
12818 | /* Output the current message now and start a new one. */ | |
12819 | *p++ = ','; | |
12820 | *p = '\0'; | |
12821 | fprintf (stream, "%s\n", message); | |
12822 | p = start; | |
12823 | left = size - (start - message) - len - 2; | |
12824 | ||
12825 | gas_assert (left >= 0); | |
12826 | ||
12827 | p = mempcpy (p, name, len); | |
12828 | } | |
12829 | ||
12830 | *left_p = left; | |
12831 | return p; | |
12832 | } | |
12833 | ||
8a2c8fef | 12834 | static void |
1ded5609 | 12835 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
12836 | { |
12837 | static char message[] = MESSAGE_TEMPLATE; | |
12838 | char *start = message + 27; | |
12839 | char *p; | |
12840 | int size = sizeof (MESSAGE_TEMPLATE); | |
12841 | int left; | |
12842 | const char *name; | |
12843 | int len; | |
12844 | unsigned int j; | |
12845 | ||
12846 | p = start; | |
12847 | left = size - (start - message); | |
12848 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
12849 | { | |
12850 | /* Should it be skipped? */ | |
12851 | if (cpu_arch [j].skip) | |
12852 | continue; | |
12853 | ||
12854 | name = cpu_arch [j].name; | |
12855 | len = cpu_arch [j].len; | |
12856 | if (*name == '.') | |
12857 | { | |
12858 | /* It is an extension. Skip if we aren't asked to show it. */ | |
12859 | if (ext) | |
12860 | { | |
12861 | name++; | |
12862 | len--; | |
12863 | } | |
12864 | else | |
12865 | continue; | |
12866 | } | |
12867 | else if (ext) | |
12868 | { | |
12869 | /* It is an processor. Skip if we show only extension. */ | |
12870 | continue; | |
12871 | } | |
1ded5609 JB |
12872 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
12873 | { | |
12874 | /* It is an impossible processor - skip. */ | |
12875 | continue; | |
12876 | } | |
8a2c8fef | 12877 | |
293f5f65 | 12878 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
12879 | } |
12880 | ||
293f5f65 L |
12881 | /* Display disabled extensions. */ |
12882 | if (ext) | |
12883 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
12884 | { | |
12885 | name = cpu_noarch [j].name; | |
12886 | len = cpu_noarch [j].len; | |
12887 | p = output_message (stream, p, message, start, &left, name, | |
12888 | len); | |
12889 | } | |
12890 | ||
8a2c8fef L |
12891 | *p = '\0'; |
12892 | fprintf (stream, "%s\n", message); | |
12893 | } | |
12894 | ||
252b5132 | 12895 | void |
8a2c8fef | 12896 | md_show_usage (FILE *stream) |
252b5132 | 12897 | { |
4cc782b5 ILT |
12898 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12899 | fprintf (stream, _("\ | |
d4693039 | 12900 | -Qy, -Qn ignored\n\ |
a38cf1db | 12901 | -V print assembler version number\n\ |
b3b91714 AM |
12902 | -k ignored\n")); |
12903 | #endif | |
12904 | fprintf (stream, _("\ | |
12b55ccc | 12905 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
12906 | -q quieten some warnings\n")); |
12907 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12908 | fprintf (stream, _("\ | |
a38cf1db | 12909 | -s ignored\n")); |
b3b91714 | 12910 | #endif |
d7f449c0 L |
12911 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
12912 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 12913 | fprintf (stream, _("\ |
570561f7 | 12914 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 12915 | #endif |
b3b91714 AM |
12916 | #ifdef SVR4_COMMENT_CHARS |
12917 | fprintf (stream, _("\ | |
12918 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
12919 | #else |
12920 | fprintf (stream, _("\ | |
b3b91714 | 12921 | --divide ignored\n")); |
4cc782b5 | 12922 | #endif |
9103f4f4 | 12923 | fprintf (stream, _("\ |
6305a203 | 12924 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 12925 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 12926 | show_arch (stream, 0, 1); |
8a2c8fef L |
12927 | fprintf (stream, _("\ |
12928 | EXTENSION is combination of:\n")); | |
1ded5609 | 12929 | show_arch (stream, 1, 0); |
6305a203 | 12930 | fprintf (stream, _("\ |
8a2c8fef | 12931 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 12932 | show_arch (stream, 0, 0); |
ba104c83 | 12933 | fprintf (stream, _("\ |
c0f3af97 L |
12934 | -msse2avx encode SSE instructions with VEX prefix\n")); |
12935 | fprintf (stream, _("\ | |
7c5c05ef | 12936 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
12937 | check SSE instructions\n")); |
12938 | fprintf (stream, _("\ | |
7c5c05ef | 12939 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
12940 | check operand combinations for validity\n")); |
12941 | fprintf (stream, _("\ | |
7c5c05ef L |
12942 | -mavxscalar=[128|256] (default: 128)\n\ |
12943 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
12944 | length\n")); |
12945 | fprintf (stream, _("\ | |
03751133 L |
12946 | -mvexwig=[0|1] (default: 0)\n\ |
12947 | encode VEX instructions with specific VEX.W value\n\ | |
12948 | for VEX.W bit ignored instructions\n")); | |
12949 | fprintf (stream, _("\ | |
7c5c05ef L |
12950 | -mevexlig=[128|256|512] (default: 128)\n\ |
12951 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
12952 | length\n")); |
12953 | fprintf (stream, _("\ | |
7c5c05ef L |
12954 | -mevexwig=[0|1] (default: 0)\n\ |
12955 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
12956 | for EVEX.W bit ignored instructions\n")); |
12957 | fprintf (stream, _("\ | |
7c5c05ef | 12958 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
12959 | encode EVEX instructions with specific EVEX.RC value\n\ |
12960 | for SAE-only ignored instructions\n")); | |
12961 | fprintf (stream, _("\ | |
7c5c05ef L |
12962 | -mmnemonic=[att|intel] ")); |
12963 | if (SYSV386_COMPAT) | |
12964 | fprintf (stream, _("(default: att)\n")); | |
12965 | else | |
12966 | fprintf (stream, _("(default: intel)\n")); | |
12967 | fprintf (stream, _("\ | |
12968 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 12969 | fprintf (stream, _("\ |
7c5c05ef L |
12970 | -msyntax=[att|intel] (default: att)\n\ |
12971 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
12972 | fprintf (stream, _("\ |
12973 | -mindex-reg support pseudo index registers\n")); | |
12974 | fprintf (stream, _("\ | |
12975 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
12976 | fprintf (stream, _("\ | |
7e8b059b | 12977 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 12978 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
12979 | fprintf (stream, _("\ |
12980 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
12981 | fprintf (stream, _("\ |
12982 | -mx86-used-note=[no|yes] ")); | |
12983 | if (DEFAULT_X86_USED_NOTE) | |
12984 | fprintf (stream, _("(default: yes)\n")); | |
12985 | else | |
12986 | fprintf (stream, _("(default: no)\n")); | |
12987 | fprintf (stream, _("\ | |
12988 | generate x86 used ISA and feature properties\n")); | |
12989 | #endif | |
12990 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
12991 | fprintf (stream, _("\ |
12992 | -mbig-obj generate big object files\n")); | |
12993 | #endif | |
d022bddd | 12994 | fprintf (stream, _("\ |
7c5c05ef | 12995 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 12996 | strip all lock prefixes\n")); |
5db04b09 | 12997 | fprintf (stream, _("\ |
7c5c05ef | 12998 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
12999 | encode lfence, mfence and sfence as\n\ |
13000 | lock addl $0x0, (%%{re}sp)\n")); | |
13001 | fprintf (stream, _("\ | |
7c5c05ef L |
13002 | -mrelax-relocations=[no|yes] ")); |
13003 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
13004 | fprintf (stream, _("(default: yes)\n")); | |
13005 | else | |
13006 | fprintf (stream, _("(default: no)\n")); | |
13007 | fprintf (stream, _("\ | |
0cb4071e L |
13008 | generate relax relocations\n")); |
13009 | fprintf (stream, _("\ | |
e379e5f3 L |
13010 | -malign-branch-boundary=NUM (default: 0)\n\ |
13011 | align branches within NUM byte boundary\n")); | |
13012 | fprintf (stream, _("\ | |
13013 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
13014 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
13015 | indirect\n\ | |
13016 | specify types of branches to align\n")); | |
13017 | fprintf (stream, _("\ | |
13018 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
13019 | align branches with NUM prefixes per instruction\n")); | |
13020 | fprintf (stream, _("\ | |
76cf450b L |
13021 | -mbranches-within-32B-boundaries\n\ |
13022 | align branches within 32 byte boundary\n")); | |
13023 | fprintf (stream, _("\ | |
7c5c05ef | 13024 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13025 | fprintf (stream, _("\ |
13026 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13027 | } |
13028 | ||
3e73aa7c | 13029 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13030 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13031 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13032 | |
13033 | /* Pick the target format to use. */ | |
13034 | ||
47926f60 | 13035 | const char * |
e3bb37b5 | 13036 | i386_target_format (void) |
252b5132 | 13037 | { |
351f65ca L |
13038 | if (!strncmp (default_arch, "x86_64", 6)) |
13039 | { | |
13040 | update_code_flag (CODE_64BIT, 1); | |
13041 | if (default_arch[6] == '\0') | |
7f56bc95 | 13042 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13043 | else |
7f56bc95 | 13044 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13045 | } |
3e73aa7c | 13046 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13047 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13048 | else if (!strcmp (default_arch, "iamcu")) |
13049 | { | |
13050 | update_code_flag (CODE_32BIT, 1); | |
13051 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13052 | { | |
13053 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13054 | cpu_arch_name = "iamcu"; | |
13055 | cpu_sub_arch_name = NULL; | |
13056 | cpu_arch_flags = iamcu_flags; | |
13057 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13058 | cpu_arch_isa_flags = iamcu_flags; | |
13059 | if (!cpu_arch_tune_set) | |
13060 | { | |
13061 | cpu_arch_tune = cpu_arch_isa; | |
13062 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13063 | } | |
13064 | } | |
8d471ec1 | 13065 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13066 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13067 | cpu_arch_name); | |
13068 | } | |
3e73aa7c | 13069 | else |
2b5d6a91 | 13070 | as_fatal (_("unknown architecture")); |
89507696 JB |
13071 | |
13072 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
13073 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13074 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
13075 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13076 | ||
252b5132 RH |
13077 | switch (OUTPUT_FLAVOR) |
13078 | { | |
9384f2ff | 13079 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13080 | case bfd_target_aout_flavour: |
47926f60 | 13081 | return AOUT_TARGET_FORMAT; |
4c63da97 | 13082 | #endif |
9384f2ff AM |
13083 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
13084 | # if defined (TE_PE) || defined (TE_PEP) | |
13085 | case bfd_target_coff_flavour: | |
167ad85b TG |
13086 | if (flag_code == CODE_64BIT) |
13087 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
13088 | else | |
13089 | return "pe-i386"; | |
9384f2ff | 13090 | # elif defined (TE_GO32) |
0561d57c JK |
13091 | case bfd_target_coff_flavour: |
13092 | return "coff-go32"; | |
9384f2ff | 13093 | # else |
252b5132 RH |
13094 | case bfd_target_coff_flavour: |
13095 | return "coff-i386"; | |
9384f2ff | 13096 | # endif |
4c63da97 | 13097 | #endif |
3e73aa7c | 13098 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 13099 | case bfd_target_elf_flavour: |
3e73aa7c | 13100 | { |
351f65ca L |
13101 | const char *format; |
13102 | ||
13103 | switch (x86_elf_abi) | |
4fa24527 | 13104 | { |
351f65ca L |
13105 | default: |
13106 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
13107 | #ifndef TE_SOLARIS |
13108 | tls_get_addr = "___tls_get_addr"; | |
13109 | #endif | |
351f65ca | 13110 | break; |
7f56bc95 | 13111 | case X86_64_ABI: |
351f65ca | 13112 | use_rela_relocations = 1; |
4fa24527 | 13113 | object_64bit = 1; |
e379e5f3 L |
13114 | #ifndef TE_SOLARIS |
13115 | tls_get_addr = "__tls_get_addr"; | |
13116 | #endif | |
351f65ca L |
13117 | format = ELF_TARGET_FORMAT64; |
13118 | break; | |
7f56bc95 | 13119 | case X86_64_X32_ABI: |
4fa24527 | 13120 | use_rela_relocations = 1; |
351f65ca | 13121 | object_64bit = 1; |
e379e5f3 L |
13122 | #ifndef TE_SOLARIS |
13123 | tls_get_addr = "__tls_get_addr"; | |
13124 | #endif | |
862be3fb | 13125 | disallow_64bit_reloc = 1; |
351f65ca L |
13126 | format = ELF_TARGET_FORMAT32; |
13127 | break; | |
4fa24527 | 13128 | } |
3632d14b | 13129 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 13130 | { |
7f56bc95 | 13131 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
13132 | as_fatal (_("Intel L1OM is 64bit only")); |
13133 | return ELF_TARGET_L1OM_FORMAT; | |
13134 | } | |
b49f93f6 | 13135 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
13136 | { |
13137 | if (x86_elf_abi != X86_64_ABI) | |
13138 | as_fatal (_("Intel K1OM is 64bit only")); | |
13139 | return ELF_TARGET_K1OM_FORMAT; | |
13140 | } | |
81486035 L |
13141 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
13142 | { | |
13143 | if (x86_elf_abi != I386_ABI) | |
13144 | as_fatal (_("Intel MCU is 32bit only")); | |
13145 | return ELF_TARGET_IAMCU_FORMAT; | |
13146 | } | |
8a9036a4 | 13147 | else |
351f65ca | 13148 | return format; |
3e73aa7c | 13149 | } |
e57f8c65 TG |
13150 | #endif |
13151 | #if defined (OBJ_MACH_O) | |
13152 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
13153 | if (flag_code == CODE_64BIT) |
13154 | { | |
13155 | use_rela_relocations = 1; | |
13156 | object_64bit = 1; | |
13157 | return "mach-o-x86-64"; | |
13158 | } | |
13159 | else | |
13160 | return "mach-o-i386"; | |
4c63da97 | 13161 | #endif |
252b5132 RH |
13162 | default: |
13163 | abort (); | |
13164 | return NULL; | |
13165 | } | |
13166 | } | |
13167 | ||
47926f60 | 13168 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 13169 | \f |
252b5132 | 13170 | symbolS * |
7016a5d5 | 13171 | md_undefined_symbol (char *name) |
252b5132 | 13172 | { |
18dc2407 ILT |
13173 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
13174 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
13175 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
13176 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
13177 | { |
13178 | if (!GOT_symbol) | |
13179 | { | |
13180 | if (symbol_find (name)) | |
13181 | as_bad (_("GOT already in symbol table")); | |
13182 | GOT_symbol = symbol_new (name, undefined_section, | |
13183 | (valueT) 0, &zero_address_frag); | |
13184 | }; | |
13185 | return GOT_symbol; | |
13186 | } | |
252b5132 RH |
13187 | return 0; |
13188 | } | |
13189 | ||
13190 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 13191 | |
252b5132 | 13192 | valueT |
7016a5d5 | 13193 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 13194 | { |
4c63da97 AM |
13195 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
13196 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
13197 | { | |
13198 | /* For a.out, force the section size to be aligned. If we don't do | |
13199 | this, BFD will align it for us, but it will not write out the | |
13200 | final bytes of the section. This may be a bug in BFD, but it is | |
13201 | easier to fix it here since that is how the other a.out targets | |
13202 | work. */ | |
13203 | int align; | |
13204 | ||
fd361982 | 13205 | align = bfd_section_alignment (segment); |
8d3842cd | 13206 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 13207 | } |
252b5132 RH |
13208 | #endif |
13209 | ||
13210 | return size; | |
13211 | } | |
13212 | ||
13213 | /* On the i386, PC-relative offsets are relative to the start of the | |
13214 | next instruction. That is, the address of the offset, plus its | |
13215 | size, since the offset is always the last part of the insn. */ | |
13216 | ||
13217 | long | |
e3bb37b5 | 13218 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
13219 | { |
13220 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
13221 | } | |
13222 | ||
13223 | #ifndef I386COFF | |
13224 | ||
13225 | static void | |
e3bb37b5 | 13226 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13227 | { |
29b0f896 | 13228 | int temp; |
252b5132 | 13229 | |
8a75718c JB |
13230 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13231 | if (IS_ELF) | |
13232 | obj_elf_section_change_hook (); | |
13233 | #endif | |
252b5132 RH |
13234 | temp = get_absolute_expression (); |
13235 | subseg_set (bss_section, (subsegT) temp); | |
13236 | demand_empty_rest_of_line (); | |
13237 | } | |
13238 | ||
13239 | #endif | |
13240 | ||
e379e5f3 L |
13241 | /* Remember constant directive. */ |
13242 | ||
13243 | void | |
13244 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
13245 | { | |
13246 | if (last_insn.kind != last_insn_directive | |
13247 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
13248 | { | |
13249 | last_insn.seg = now_seg; | |
13250 | last_insn.kind = last_insn_directive; | |
13251 | last_insn.name = "constant directive"; | |
13252 | last_insn.file = as_where (&last_insn.line); | |
13253 | } | |
13254 | } | |
13255 | ||
252b5132 | 13256 | void |
e3bb37b5 | 13257 | i386_validate_fix (fixS *fixp) |
252b5132 | 13258 | { |
02a86693 | 13259 | if (fixp->fx_subsy) |
252b5132 | 13260 | { |
02a86693 | 13261 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 13262 | { |
02a86693 L |
13263 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
13264 | { | |
13265 | if (!object_64bit) | |
13266 | abort (); | |
13267 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13268 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
13269 | fixp->fx_r_type = (fixp->fx_tcbit |
13270 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
13271 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
13272 | else |
13273 | #endif | |
13274 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
13275 | } | |
d6ab8113 | 13276 | else |
02a86693 L |
13277 | { |
13278 | if (!object_64bit) | |
13279 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
13280 | else | |
13281 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
13282 | } | |
13283 | fixp->fx_subsy = 0; | |
23df1078 | 13284 | } |
252b5132 | 13285 | } |
02a86693 L |
13286 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13287 | else if (!object_64bit) | |
13288 | { | |
13289 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
13290 | && fixp->fx_tcbit2) | |
13291 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
13292 | } | |
13293 | #endif | |
252b5132 RH |
13294 | } |
13295 | ||
252b5132 | 13296 | arelent * |
7016a5d5 | 13297 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13298 | { |
13299 | arelent *rel; | |
13300 | bfd_reloc_code_real_type code; | |
13301 | ||
13302 | switch (fixp->fx_r_type) | |
13303 | { | |
8ce3d284 | 13304 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
13305 | case BFD_RELOC_SIZE32: |
13306 | case BFD_RELOC_SIZE64: | |
13307 | if (S_IS_DEFINED (fixp->fx_addsy) | |
13308 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
13309 | { | |
13310 | /* Resolve size relocation against local symbol to size of | |
13311 | the symbol plus addend. */ | |
13312 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
13313 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
13314 | && !fits_in_unsigned_long (value)) | |
13315 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13316 | _("symbol size computation overflow")); | |
13317 | fixp->fx_addsy = NULL; | |
13318 | fixp->fx_subsy = NULL; | |
13319 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
13320 | return NULL; | |
13321 | } | |
8ce3d284 | 13322 | #endif |
1a0670f3 | 13323 | /* Fall through. */ |
8fd4256d | 13324 | |
3e73aa7c JH |
13325 | case BFD_RELOC_X86_64_PLT32: |
13326 | case BFD_RELOC_X86_64_GOT32: | |
13327 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13328 | case BFD_RELOC_X86_64_GOTPCRELX: |
13329 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
13330 | case BFD_RELOC_386_PLT32: |
13331 | case BFD_RELOC_386_GOT32: | |
02a86693 | 13332 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
13333 | case BFD_RELOC_386_GOTOFF: |
13334 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
13335 | case BFD_RELOC_386_TLS_GD: |
13336 | case BFD_RELOC_386_TLS_LDM: | |
13337 | case BFD_RELOC_386_TLS_LDO_32: | |
13338 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
13339 | case BFD_RELOC_386_TLS_IE: |
13340 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
13341 | case BFD_RELOC_386_TLS_LE_32: |
13342 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
13343 | case BFD_RELOC_386_TLS_GOTDESC: |
13344 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
13345 | case BFD_RELOC_X86_64_TLSGD: |
13346 | case BFD_RELOC_X86_64_TLSLD: | |
13347 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 13348 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
13349 | case BFD_RELOC_X86_64_GOTTPOFF: |
13350 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
13351 | case BFD_RELOC_X86_64_TPOFF64: |
13352 | case BFD_RELOC_X86_64_GOTOFF64: | |
13353 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
13354 | case BFD_RELOC_X86_64_GOT64: |
13355 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13356 | case BFD_RELOC_X86_64_GOTPC64: | |
13357 | case BFD_RELOC_X86_64_GOTPLT64: | |
13358 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
13359 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13360 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
13361 | case BFD_RELOC_RVA: |
13362 | case BFD_RELOC_VTABLE_ENTRY: | |
13363 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
13364 | #ifdef TE_PE |
13365 | case BFD_RELOC_32_SECREL: | |
13366 | #endif | |
252b5132 RH |
13367 | code = fixp->fx_r_type; |
13368 | break; | |
dbbaec26 L |
13369 | case BFD_RELOC_X86_64_32S: |
13370 | if (!fixp->fx_pcrel) | |
13371 | { | |
13372 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
13373 | code = fixp->fx_r_type; | |
13374 | break; | |
13375 | } | |
1a0670f3 | 13376 | /* Fall through. */ |
252b5132 | 13377 | default: |
93382f6d | 13378 | if (fixp->fx_pcrel) |
252b5132 | 13379 | { |
93382f6d AM |
13380 | switch (fixp->fx_size) |
13381 | { | |
13382 | default: | |
b091f402 AM |
13383 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13384 | _("can not do %d byte pc-relative relocation"), | |
13385 | fixp->fx_size); | |
93382f6d AM |
13386 | code = BFD_RELOC_32_PCREL; |
13387 | break; | |
13388 | case 1: code = BFD_RELOC_8_PCREL; break; | |
13389 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 13390 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
13391 | #ifdef BFD64 |
13392 | case 8: code = BFD_RELOC_64_PCREL; break; | |
13393 | #endif | |
93382f6d AM |
13394 | } |
13395 | } | |
13396 | else | |
13397 | { | |
13398 | switch (fixp->fx_size) | |
13399 | { | |
13400 | default: | |
b091f402 AM |
13401 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13402 | _("can not do %d byte relocation"), | |
13403 | fixp->fx_size); | |
93382f6d AM |
13404 | code = BFD_RELOC_32; |
13405 | break; | |
13406 | case 1: code = BFD_RELOC_8; break; | |
13407 | case 2: code = BFD_RELOC_16; break; | |
13408 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 13409 | #ifdef BFD64 |
3e73aa7c | 13410 | case 8: code = BFD_RELOC_64; break; |
937149dd | 13411 | #endif |
93382f6d | 13412 | } |
252b5132 RH |
13413 | } |
13414 | break; | |
13415 | } | |
252b5132 | 13416 | |
d182319b JB |
13417 | if ((code == BFD_RELOC_32 |
13418 | || code == BFD_RELOC_32_PCREL | |
13419 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
13420 | && GOT_symbol |
13421 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 13422 | { |
4fa24527 | 13423 | if (!object_64bit) |
d6ab8113 JB |
13424 | code = BFD_RELOC_386_GOTPC; |
13425 | else | |
13426 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 13427 | } |
7b81dfbb AJ |
13428 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
13429 | && GOT_symbol | |
13430 | && fixp->fx_addsy == GOT_symbol) | |
13431 | { | |
13432 | code = BFD_RELOC_X86_64_GOTPC64; | |
13433 | } | |
252b5132 | 13434 | |
add39d23 TS |
13435 | rel = XNEW (arelent); |
13436 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 13437 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
13438 | |
13439 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 13440 | |
3e73aa7c JH |
13441 | if (!use_rela_relocations) |
13442 | { | |
13443 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
13444 | vtable entry to be used in the relocation's section offset. */ | |
13445 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13446 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
13447 | #if defined (OBJ_COFF) && defined (TE_PE) |
13448 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
13449 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
13450 | else | |
13451 | #endif | |
c6682705 | 13452 | rel->addend = 0; |
3e73aa7c JH |
13453 | } |
13454 | /* Use the rela in 64bit mode. */ | |
252b5132 | 13455 | else |
3e73aa7c | 13456 | { |
862be3fb L |
13457 | if (disallow_64bit_reloc) |
13458 | switch (code) | |
13459 | { | |
862be3fb L |
13460 | case BFD_RELOC_X86_64_DTPOFF64: |
13461 | case BFD_RELOC_X86_64_TPOFF64: | |
13462 | case BFD_RELOC_64_PCREL: | |
13463 | case BFD_RELOC_X86_64_GOTOFF64: | |
13464 | case BFD_RELOC_X86_64_GOT64: | |
13465 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13466 | case BFD_RELOC_X86_64_GOTPC64: | |
13467 | case BFD_RELOC_X86_64_GOTPLT64: | |
13468 | case BFD_RELOC_X86_64_PLTOFF64: | |
13469 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13470 | _("cannot represent relocation type %s in x32 mode"), | |
13471 | bfd_get_reloc_code_name (code)); | |
13472 | break; | |
13473 | default: | |
13474 | break; | |
13475 | } | |
13476 | ||
062cd5e7 AS |
13477 | if (!fixp->fx_pcrel) |
13478 | rel->addend = fixp->fx_offset; | |
13479 | else | |
13480 | switch (code) | |
13481 | { | |
13482 | case BFD_RELOC_X86_64_PLT32: | |
13483 | case BFD_RELOC_X86_64_GOT32: | |
13484 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13485 | case BFD_RELOC_X86_64_GOTPCRELX: |
13486 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
13487 | case BFD_RELOC_X86_64_TLSGD: |
13488 | case BFD_RELOC_X86_64_TLSLD: | |
13489 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
13490 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13491 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
13492 | rel->addend = fixp->fx_offset - fixp->fx_size; |
13493 | break; | |
13494 | default: | |
13495 | rel->addend = (section->vma | |
13496 | - fixp->fx_size | |
13497 | + fixp->fx_addnumber | |
13498 | + md_pcrel_from (fixp)); | |
13499 | break; | |
13500 | } | |
3e73aa7c JH |
13501 | } |
13502 | ||
252b5132 RH |
13503 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
13504 | if (rel->howto == NULL) | |
13505 | { | |
13506 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 13507 | _("cannot represent relocation type %s"), |
252b5132 RH |
13508 | bfd_get_reloc_code_name (code)); |
13509 | /* Set howto to a garbage value so that we can keep going. */ | |
13510 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 13511 | gas_assert (rel->howto != NULL); |
252b5132 RH |
13512 | } |
13513 | ||
13514 | return rel; | |
13515 | } | |
13516 | ||
ee86248c | 13517 | #include "tc-i386-intel.c" |
54cfded0 | 13518 | |
a60de03c JB |
13519 | void |
13520 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 13521 | { |
a60de03c JB |
13522 | int saved_naked_reg; |
13523 | char saved_register_dot; | |
54cfded0 | 13524 | |
a60de03c JB |
13525 | saved_naked_reg = allow_naked_reg; |
13526 | allow_naked_reg = 1; | |
13527 | saved_register_dot = register_chars['.']; | |
13528 | register_chars['.'] = '.'; | |
13529 | allow_pseudo_reg = 1; | |
13530 | expression_and_evaluate (exp); | |
13531 | allow_pseudo_reg = 0; | |
13532 | register_chars['.'] = saved_register_dot; | |
13533 | allow_naked_reg = saved_naked_reg; | |
13534 | ||
e96d56a1 | 13535 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 13536 | { |
a60de03c JB |
13537 | if ((addressT) exp->X_add_number < i386_regtab_size) |
13538 | { | |
13539 | exp->X_op = O_constant; | |
13540 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
13541 | .dw2_regnum[flag_code >> 1]; | |
13542 | } | |
13543 | else | |
13544 | exp->X_op = O_illegal; | |
54cfded0 | 13545 | } |
54cfded0 AM |
13546 | } |
13547 | ||
13548 | void | |
13549 | tc_x86_frame_initial_instructions (void) | |
13550 | { | |
a60de03c JB |
13551 | static unsigned int sp_regno[2]; |
13552 | ||
13553 | if (!sp_regno[flag_code >> 1]) | |
13554 | { | |
13555 | char *saved_input = input_line_pointer; | |
13556 | char sp[][4] = {"esp", "rsp"}; | |
13557 | expressionS exp; | |
a4447b93 | 13558 | |
a60de03c JB |
13559 | input_line_pointer = sp[flag_code >> 1]; |
13560 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 13561 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
13562 | sp_regno[flag_code >> 1] = exp.X_add_number; |
13563 | input_line_pointer = saved_input; | |
13564 | } | |
a4447b93 | 13565 | |
61ff971f L |
13566 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
13567 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 13568 | } |
d2b2c203 | 13569 | |
d7921315 L |
13570 | int |
13571 | x86_dwarf2_addr_size (void) | |
13572 | { | |
13573 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
13574 | if (x86_elf_abi == X86_64_X32_ABI) | |
13575 | return 4; | |
13576 | #endif | |
13577 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
13578 | } | |
13579 | ||
d2b2c203 DJ |
13580 | int |
13581 | i386_elf_section_type (const char *str, size_t len) | |
13582 | { | |
13583 | if (flag_code == CODE_64BIT | |
13584 | && len == sizeof ("unwind") - 1 | |
13585 | && strncmp (str, "unwind", 6) == 0) | |
13586 | return SHT_X86_64_UNWIND; | |
13587 | ||
13588 | return -1; | |
13589 | } | |
bb41ade5 | 13590 | |
ad5fec3b EB |
13591 | #ifdef TE_SOLARIS |
13592 | void | |
13593 | i386_solaris_fix_up_eh_frame (segT sec) | |
13594 | { | |
13595 | if (flag_code == CODE_64BIT) | |
13596 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
13597 | } | |
13598 | #endif | |
13599 | ||
bb41ade5 AM |
13600 | #ifdef TE_PE |
13601 | void | |
13602 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
13603 | { | |
91d6fa6a | 13604 | expressionS exp; |
bb41ade5 | 13605 | |
91d6fa6a NC |
13606 | exp.X_op = O_secrel; |
13607 | exp.X_add_symbol = symbol; | |
13608 | exp.X_add_number = 0; | |
13609 | emit_expr (&exp, size); | |
bb41ade5 AM |
13610 | } |
13611 | #endif | |
3b22753a L |
13612 | |
13613 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13614 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
13615 | ||
01e1a5bc | 13616 | bfd_vma |
6d4af3c2 | 13617 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
13618 | { |
13619 | if (flag_code == CODE_64BIT) | |
13620 | { | |
13621 | if (letter == 'l') | |
13622 | return SHF_X86_64_LARGE; | |
13623 | ||
8f3bae45 | 13624 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 13625 | } |
3b22753a | 13626 | else |
8f3bae45 | 13627 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
13628 | return -1; |
13629 | } | |
13630 | ||
01e1a5bc | 13631 | bfd_vma |
3b22753a L |
13632 | x86_64_section_word (char *str, size_t len) |
13633 | { | |
8620418b | 13634 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
13635 | return SHF_X86_64_LARGE; |
13636 | ||
13637 | return -1; | |
13638 | } | |
13639 | ||
13640 | static void | |
13641 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
13642 | { | |
13643 | if (flag_code != CODE_64BIT) | |
13644 | { | |
13645 | s_comm_internal (0, elf_common_parse); | |
13646 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
13647 | } | |
13648 | else | |
13649 | { | |
13650 | static segT lbss_section; | |
13651 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
13652 | asection *saved_bss_section = bss_section; | |
13653 | ||
13654 | if (lbss_section == NULL) | |
13655 | { | |
13656 | flagword applicable; | |
13657 | segT seg = now_seg; | |
13658 | subsegT subseg = now_subseg; | |
13659 | ||
13660 | /* The .lbss section is for local .largecomm symbols. */ | |
13661 | lbss_section = subseg_new (".lbss", 0); | |
13662 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 13663 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
13664 | seg_info (lbss_section)->bss = 1; |
13665 | ||
13666 | subseg_set (seg, subseg); | |
13667 | } | |
13668 | ||
13669 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
13670 | bss_section = lbss_section; | |
13671 | ||
13672 | s_comm_internal (0, elf_common_parse); | |
13673 | ||
13674 | elf_com_section_ptr = saved_com_section_ptr; | |
13675 | bss_section = saved_bss_section; | |
13676 | } | |
13677 | } | |
13678 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |