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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
c32fa91d
L		 70#define LOCK_PREFIX 5
71#define REX_PREFIX 6 /* must come last. */
72#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 73
74/* we define the syntax here (modulo base,index,scale syntax) */
75#define REGISTER_PREFIX '%'
76#define IMMEDIATE_PREFIX '$'
77#define ABSOLUTE_PREFIX '*'
78
79/* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81#define WORD_MNEM_SUFFIX 'w'
82#define BYTE_MNEM_SUFFIX 'b'
83#define SHORT_MNEM_SUFFIX 's'
84#define LONG_MNEM_SUFFIX 'l'
85#define QWORD_MNEM_SUFFIX 'q'
86#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 87#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 88/* Intel Syntax. Use a non-ascii letter since since it never appears
89 in instructions. */
90#define LONG_DOUBLE_MNEM_SUFFIX '\1'
91
92#define END_OF_INSN '\0'
93
94/*
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
99 END.
100 */
101typedef struct
102{
d3ce72d0
NC		 103 const insn_template *start;
104 const insn_template *end;
6305a203
L		 105}
106templates;
107
108/* 386 operand encoding bytes: see 386 book for details of this. */
109typedef struct
110{
111 unsigned int regmem; /* codes register or memory operand */
112 unsigned int reg; /* codes register operand (or extended opcode) */
113 unsigned int mode; /* how to interpret regmem & reg */
114}
115modrm_byte;
116
117/* x86-64 extension prefix. */
118typedef int rex_byte;
119
6305a203
L		 120/* 386 opcode byte to code indirect addressing. */
121typedef struct
122{
123 unsigned base;
124 unsigned index;
125 unsigned scale;
126}
127sib_byte;
128
6305a203
L		 129/* x86 arch names, types and features */
130typedef struct
131{
132 const char *name; /* arch name */
8a2c8fef 133 unsigned int len; /* arch string length */
6305a203
L		 134 enum processor_type type; /* arch type */
135 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 136 unsigned int skip; /* show_arch should skip this. */
22109423 137 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 138}
139arch_entry;
140
78f12dd3 141static void update_code_flag (int, int);
e3bb37b5
L		 142static void set_code_flag (int);
143static void set_16bit_gcc_code_flag (int);
144static void set_intel_syntax (int);
1efbbeb4 145static void set_intel_mnemonic (int);
db51cc60 146static void set_allow_index_reg (int);
7bab8ab5 147static void set_check (int);
e3bb37b5 148static void set_cpu_arch (int);
6482c264 149#ifdef TE_PE
e3bb37b5 150static void pe_directive_secrel (int);
6482c264 151#endif
e3bb37b5
L		 152static void signed_cons (int);
153static char *output_invalid (int c);
ee86248c
JB		 154static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 const char *);
156static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 const char *);
a7619375 158static int i386_att_operand (char *);
e3bb37b5 159static int i386_intel_operand (char *, int);
ee86248c
JB		 160static int i386_intel_simplify (expressionS *);
161static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 162static const reg_entry *parse_register (char *, char **);
163static char *parse_insn (char *, char *);
164static char *parse_operands (char *, const char *);
165static void swap_operands (void);
4d456e3d 166static void swap_2_operands (int, int);
e3bb37b5
L		 167static void optimize_imm (void);
168static void optimize_disp (void);
d3ce72d0 169static const insn_template *match_template (void);
e3bb37b5
L		 170static int check_string (void);
171static int process_suffix (void);
172static int check_byte_reg (void);
173static int check_long_reg (void);
174static int check_qword_reg (void);
175static int check_word_reg (void);
176static int finalize_imm (void);
177static int process_operands (void);
178static const seg_entry *build_modrm_byte (void);
179static void output_insn (void);
180static void output_imm (fragS *, offsetT);
181static void output_disp (fragS *, offsetT);
29b0f896 182#ifndef I386COFF
e3bb37b5 183static void s_bss (int);
252b5132 184#endif
17d4e2a2
L		 185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186static void handle_large_common (int small ATTRIBUTE_UNUSED);
187#endif
252b5132 188
a847613f 189static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 190
c0f3af97
L		 191/* VEX prefix. */
192typedef struct
193{
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes[3];
196 unsigned int length;
197 /* Destination or source register specifier. */
198 const reg_entry *register_specifier;
199} vex_prefix;
200
252b5132 201/* 'md_assemble ()' gathers together information and puts it into a
47926f60 202 i386_insn. */
252b5132 203
520dc8e8
AM		 204union i386_op
205 {
206 expressionS *disps;
207 expressionS *imms;
208 const reg_entry *regs;
209 };
210
a65babc9
L		 211enum i386_error
212 {
86e026a4 213 operand_size_mismatch,
a65babc9
L		 214 operand_type_mismatch,
215 register_type_mismatch,
216 number_of_operands_mismatch,
217 invalid_instruction_suffix,
218 bad_imm4,
219 old_gcc_only,
220 unsupported_with_intel_mnemonic,
221 unsupported_syntax,
6c30d220
L		 222 unsupported,
223 invalid_vsib_address,
7bab8ab5 224 invalid_vector_register_set,
6c30d220 225 unsupported_vector_index_register
a65babc9
L		 226 };
227
252b5132
RH		 228struct _i386_insn
229 {
47926f60 230 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 231 insn_template tm;
252b5132 232
7d5e4556
L		 233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
252b5132
RH		 235 char suffix;
236
47926f60 237 /* OPERANDS gives the number of given operands. */
252b5132
RH		 238 unsigned int operands;
239
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
47926f60 242 operands. */
252b5132
RH		 243 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
244
245 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 246 use OP[i] for the corresponding operand. */
40fb9820 247 i386_operand_type types[MAX_OPERANDS];
252b5132 248
520dc8e8
AM		 249 /* Displacement expression, immediate expression, or register for each
250 operand. */
251 union i386_op op[MAX_OPERANDS];
252b5132 252
3e73aa7c
JH		 253 /* Flags for operands. */
254 unsigned int flags[MAX_OPERANDS];
255#define Operand_PCrel 1
256
252b5132 257 /* Relocation type for operand */
f86103b7 258 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 259
252b5132
RH		 260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry *base_reg;
263 const reg_entry *index_reg;
264 unsigned int log2_scale_factor;
265
266 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 267 explicit segment overrides are given. */
ce8a8b2f 268 const seg_entry *seg[2];
252b5132
RH		 269
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes;
273 unsigned char prefix[MAX_PREFIXES];
274
275 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 276 addressing modes of this insn are encoded. */
252b5132 277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
c0f3af97 280 vex_prefix vex;
b6169b20
L		 281
282 /* Swap operand in encoding. */
4473e004 283 unsigned int swap_operand;
891edac4 284
a501d77e
L		 285 /* Prefer 8bit or 32bit displacement in encoding. */
286 enum
287 {
288 disp_encoding_default = 0,
289 disp_encoding_8bit,
290 disp_encoding_32bit
291 } disp_encoding;
f8a5c266 292
42164a71
L		 293 /* Have HLE prefix. */
294 unsigned int have_hle;
295
891edac4 296 /* Error message. */
a65babc9 297 enum i386_error error;
252b5132
RH		 298 };
299
300typedef struct _i386_insn i386_insn;
301
302/* List of chars besides those in app.c:symbol_chars that can start an
303 operand. Used to prevent the scrubber eating vital white-space. */
32137342 304const char extra_symbol_chars[] = "*%-(["
252b5132 305#ifdef LEX_AT
32137342
NC		 306 "@"
307#endif
308#ifdef LEX_QM
309 "?"
252b5132 310#endif
32137342 311 ;
252b5132 312
29b0f896
AM		 313#if (defined (TE_I386AIX) \
314 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 315 && !defined (TE_GNU) \
29b0f896 316 && !defined (TE_LINUX) \
8d63c93e
RM		 317 && !defined (TE_NACL) \
318 && !defined (TE_NETWARE) \
29b0f896 319 && !defined (TE_FreeBSD) \
5b806d27 320 && !defined (TE_DragonFly) \
29b0f896 321 && !defined (TE_NetBSD)))
252b5132 322/* This array holds the chars that always start a comment. If the
b3b91714
AM		 323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325const char *i386_comment_chars = "#/";
326#define SVR4_COMMENT_CHARS 1
252b5132 327#define PREFIX_SEPARATOR '\\'
252b5132 328
b3b91714
AM		 329#else
330const char *i386_comment_chars = "#";
331#define PREFIX_SEPARATOR '/'
332#endif
333
252b5132
RH		 334/* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 338 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
252b5132 341 '/' isn't otherwise defined. */
b3b91714 342const char line_comment_chars[] = "#/";
252b5132 343
63a0b638 344const char line_separator_chars[] = ";";
252b5132 345
ce8a8b2f
AM		 346/* Chars that can be used to separate mant from exp in floating point
347 nums. */
252b5132
RH		 348const char EXP_CHARS[] = "eE";
349
ce8a8b2f
AM		 350/* Chars that mean this number is a floating point constant
351 As in 0f12.456
352 or 0d1.2345e12. */
252b5132
RH		 353const char FLT_CHARS[] = "fFdDxX";
354
ce8a8b2f 355/* Tables for lexical analysis. */
252b5132
RH		 356static char mnemonic_chars[256];
357static char register_chars[256];
358static char operand_chars[256];
359static char identifier_chars[256];
360static char digit_chars[256];
361
ce8a8b2f 362/* Lexical macros. */
252b5132
RH		 363#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364#define is_operand_char(x) (operand_chars[(unsigned char) x])
365#define is_register_char(x) (register_chars[(unsigned char) x])
366#define is_space_char(x) ((x) == ' ')
367#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368#define is_digit_char(x) (digit_chars[(unsigned char) x])
369
0234cb7c 370/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 371static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
372
373/* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
47926f60 376 assembler instruction). */
252b5132 377static char save_stack[32];
ce8a8b2f 378static char *save_stack_p;
252b5132
RH		 379#define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381#define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
383
47926f60 384/* The instruction we're assembling. */
252b5132
RH		 385static i386_insn i;
386
387/* Possible templates for current insn. */
388static const templates *current_templates;
389
31b2323c
L		 390/* Per instruction expressionS buffers: max displacements & immediates. */
391static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
392static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 393
47926f60 394/* Current operand we are working on. */
ee86248c 395static int this_operand = -1;
252b5132 396
3e73aa7c
JH		 397/* We support four different modes. FLAG_CODE variable is used to distinguish
398 these. */
399
400enum flag_code {
401 CODE_32BIT,
402 CODE_16BIT,
403 CODE_64BIT };
404
405static enum flag_code flag_code;
4fa24527 406static unsigned int object_64bit;
862be3fb 407static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 408static int use_rela_relocations = 0;
409
7af8ed2d
NC		 410#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
411 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
412 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
413
351f65ca
L		 414/* The ELF ABI to use. */
415enum x86_elf_abi
416{
417 I386_ABI,
7f56bc95
L		 418 X86_64_ABI,
419 X86_64_X32_ABI
351f65ca
L		 420};
421
422static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 423#endif
351f65ca 424
3e73aa7c 425/* The names used to print error messages. */
b77a7acd 426static const char *flag_code_names[] =
3e73aa7c
JH		 427 {
428 "32",
429 "16",
430 "64"
431 };
252b5132 432
47926f60
KH		 433/* 1 for intel syntax,
434 0 if att syntax. */
435static int intel_syntax = 0;
252b5132 436
1efbbeb4
L		 437/* 1 for intel mnemonic,
438 0 if att mnemonic. */
439static int intel_mnemonic = !SYSV386_COMPAT;
440
5209009a 441/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 442static int old_gcc = OLDGCC_COMPAT;
443
a60de03c
JB		 444/* 1 if pseudo registers are permitted. */
445static int allow_pseudo_reg = 0;
446
47926f60
KH		 447/* 1 if register prefix % not required. */
448static int allow_naked_reg = 0;
252b5132 449
ba104c83 450/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 451static int allow_index_reg = 0;
452
7bab8ab5 453static enum check_kind
daf50ae7 454 {
7bab8ab5
JB		 455 check_none = 0,
456 check_warning,
457 check_error
daf50ae7 458 }
7bab8ab5 459sse_check, operand_check = check_warning;
daf50ae7 460
2ca3ace5
L		 461/* Register prefix used for error message. */
462static const char *register_prefix = "%";
463
47926f60
KH		 464/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
465 leave, push, and pop instructions so that gcc has the same stack
466 frame as in 32 bit mode. */
467static char stackop_size = '\0';
eecb386c 468
12b55ccc
L		 469/* Non-zero to optimize code alignment. */
470int optimize_align_code = 1;
471
47926f60
KH		 472/* Non-zero to quieten some warnings. */
473static int quiet_warnings = 0;
a38cf1db 474
47926f60
KH		 475/* CPU name. */
476static const char *cpu_arch_name = NULL;
6305a203 477static char *cpu_sub_arch_name = NULL;
a38cf1db 478
47926f60 479/* CPU feature flags. */
40fb9820
L		 480static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
481
ccc9c027
L		 482/* If we have selected a cpu we are generating instructions for. */
483static int cpu_arch_tune_set = 0;
484
9103f4f4 485/* Cpu we are generating instructions for. */
fbf3f584 486enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 487
488/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 489static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 490
ccc9c027 491/* CPU instruction set architecture used. */
fbf3f584 492enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 493
9103f4f4 494/* CPU feature flags of instruction set architecture used. */
fbf3f584 495i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 496
fddf5b5b
AM		 497/* If set, conditional jumps are not automatically promoted to handle
498 larger than a byte offset. */
499static unsigned int no_cond_jump_promotion = 0;
500
c0f3af97
L		 501/* Encode SSE instructions with VEX prefix. */
502static unsigned int sse2avx;
503
539f890d
L		 504/* Encode scalar AVX instructions with specific vector length. */
505static enum
506 {
507 vex128 = 0,
508 vex256
509 } avxscalar;
510
29b0f896 511/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 512static symbolS *GOT_symbol;
29b0f896 513
a4447b93
RH		 514/* The dwarf2 return column, adjusted for 32 or 64 bit. */
515unsigned int x86_dwarf2_return_column;
516
517/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
518int x86_cie_data_alignment;
519
252b5132 520/* Interface to relax_segment.
fddf5b5b
AM		 521 There are 3 major relax states for 386 jump insns because the
522 different types of jumps add different sizes to frags when we're
523 figuring out what sort of jump to choose to reach a given label. */
252b5132 524
47926f60 525/* Types. */
93c2a809
AM		 526#define UNCOND_JUMP 0
527#define COND_JUMP 1
528#define COND_JUMP86 2
fddf5b5b 529
47926f60 530/* Sizes. */
252b5132
RH		 531#define CODE16 1
532#define SMALL 0
29b0f896 533#define SMALL16 (SMALL | CODE16)
252b5132 534#define BIG 2
29b0f896 535#define BIG16 (BIG | CODE16)
252b5132
RH		 536
537#ifndef INLINE
538#ifdef __GNUC__
539#define INLINE __inline__
540#else
541#define INLINE
542#endif
543#endif
544
fddf5b5b
AM		 545#define ENCODE_RELAX_STATE(type, size) \
546 ((relax_substateT) (((type) << 2) | (size)))
547#define TYPE_FROM_RELAX_STATE(s) \
548 ((s) >> 2)
549#define DISP_SIZE_FROM_RELAX_STATE(s) \
550 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 551
552/* This table is used by relax_frag to promote short jumps to long
553 ones where necessary. SMALL (short) jumps may be promoted to BIG
554 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
555 don't allow a short jump in a 32 bit code segment to be promoted to
556 a 16 bit offset jump because it's slower (requires data size
557 prefix), and doesn't work, unless the destination is in the bottom
558 64k of the code segment (The top 16 bits of eip are zeroed). */
559
560const relax_typeS md_relax_table[] =
561{
24eab124
AM		 562 /* The fields are:
563 1) most positive reach of this state,
564 2) most negative reach of this state,
93c2a809 565 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 566 4) which index into the table to try if we can't fit into this one. */
252b5132 567
fddf5b5b 568 /* UNCOND_JUMP states. */
93c2a809
AM		 569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
570 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
571 /* dword jmp adds 4 bytes to frag:
572 0 extra opcode bytes, 4 displacement bytes. */
252b5132 573 {0, 0, 4, 0},
93c2a809
AM		 574 /* word jmp adds 2 byte2 to frag:
575 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 576 {0, 0, 2, 0},
577
93c2a809
AM		 578 /* COND_JUMP states. */
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
580 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
581 /* dword conditionals adds 5 bytes to frag:
582 1 extra opcode byte, 4 displacement bytes. */
583 {0, 0, 5, 0},
fddf5b5b 584 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 585 1 extra opcode byte, 2 displacement bytes. */
586 {0, 0, 3, 0},
587
588 /* COND_JUMP86 states. */
589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
590 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
591 /* dword conditionals adds 5 bytes to frag:
592 1 extra opcode byte, 4 displacement bytes. */
593 {0, 0, 5, 0},
594 /* word conditionals add 4 bytes to frag:
595 1 displacement byte and a 3 byte long branch insn. */
596 {0, 0, 4, 0}
252b5132
RH		 597};
598
9103f4f4
L		 599static const arch_entry cpu_arch[] =
600{
89507696
JB		 601 /* Do not replace the first two entries - i386_target_format()
602 relies on them being there in this order. */
8a2c8fef 603 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 604 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 605 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 606 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 607 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 608 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 609 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 610 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 611 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 612 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 613 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 614 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 615 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 616 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 617 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 618 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 619 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 620 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 621 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 622 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 623 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 624 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 625 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 626 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 627 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 628 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 629 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 630 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 631 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 632 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 633 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 634 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 635 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 636 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 637 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 638 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 639 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 640 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 641 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 642 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 643 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 644 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 645 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 646 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 647 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
648 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 649 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 650 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 651 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 652 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 653 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 654 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 655 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 656 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 657 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 658 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 659 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 660 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 661 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 662 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 663 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 664 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 665 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 666 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 667 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
668 CPU_BDVER3_FLAGS, 0, 0 },
7b458c12
L		 669 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
670 CPU_BTVER1_FLAGS, 0, 0 },
671 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
672 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 673 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 674 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 675 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 676 CPU_287_FLAGS, 0, 0 },
8a2c8fef 677 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 678 CPU_387_FLAGS, 0, 0 },
8a2c8fef 679 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 680 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 681 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 682 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 683 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 684 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 685 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 686 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 687 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 688 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 689 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 690 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 691 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 692 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 693 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 694 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 695 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 696 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 697 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 698 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 699 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 700 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 701 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 702 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 703 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
704 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 705 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 706 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 707 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 708 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 709 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
710 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 712 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 714 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 715 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 716 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 718 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 720 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 722 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 723 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 724 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 725 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 726 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 727 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 728 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 729 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
730 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 732 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 734 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 736 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 738 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 740 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 741 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
742 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 744 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 745 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
746 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 747 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
748 CPU_HLE_FLAGS, 0, 0 },
749 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
750 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 751 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
752 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 754 CPU_CLFLUSH_FLAGS, 0, 0 },
755 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
756 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 758 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 760 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 762 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 764 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 766 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 768 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 769 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 770 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 772 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 774 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 775 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
776 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 777 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
778 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 779 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
780 CPU_ADX_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
782 CPU_RDSEED_FLAGS, 0, 0 },
783 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
784 CPU_PRFCHW_FLAGS, 0, 0 },
e413e4e9
AM		 785};
786
704209c0 787#ifdef I386COFF
a6c24e68
NC		 788/* Like s_lcomm_internal in gas/read.c but the alignment string
789 is allowed to be optional. */
790
791static symbolS *
792pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
793{
794 addressT align = 0;
795
796 SKIP_WHITESPACE ();
797
7ab9ffdd 798 if (needs_align
a6c24e68
NC		 799 && *input_line_pointer == ',')
800 {
801 align = parse_align (needs_align - 1);
7ab9ffdd 802
a6c24e68
NC		 803 if (align == (addressT) -1)
804 return NULL;
805 }
806 else
807 {
808 if (size >= 8)
809 align = 3;
810 else if (size >= 4)
811 align = 2;
812 else if (size >= 2)
813 align = 1;
814 else
815 align = 0;
816 }
817
818 bss_alloc (symbolP, size, align);
819 return symbolP;
820}
821
704209c0 822static void
a6c24e68
NC		 823pe_lcomm (int needs_align)
824{
825 s_comm_internal (needs_align * 2, pe_lcomm_internal);
826}
704209c0 827#endif
a6c24e68 828
29b0f896
AM		 829const pseudo_typeS md_pseudo_table[] =
830{
831#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
832 {"align", s_align_bytes, 0},
833#else
834 {"align", s_align_ptwo, 0},
835#endif
836 {"arch", set_cpu_arch, 0},
837#ifndef I386COFF
838 {"bss", s_bss, 0},
a6c24e68
NC		 839#else
840 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 841#endif
842 {"ffloat", float_cons, 'f'},
843 {"dfloat", float_cons, 'd'},
844 {"tfloat", float_cons, 'x'},
845 {"value", cons, 2},
d182319b 846 {"slong", signed_cons, 4},
29b0f896
AM		 847 {"noopt", s_ignore, 0},
848 {"optim", s_ignore, 0},
849 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
850 {"code16", set_code_flag, CODE_16BIT},
851 {"code32", set_code_flag, CODE_32BIT},
852 {"code64", set_code_flag, CODE_64BIT},
853 {"intel_syntax", set_intel_syntax, 1},
854 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 855 {"intel_mnemonic", set_intel_mnemonic, 1},
856 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 857 {"allow_index_reg", set_allow_index_reg, 1},
858 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 859 {"sse_check", set_check, 0},
860 {"operand_check", set_check, 1},
3b22753a
L		 861#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
862 {"largecomm", handle_large_common, 0},
07a53e5c 863#else
e3bb37b5 864 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 865 {"loc", dwarf2_directive_loc, 0},
866 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 867#endif
6482c264
NC		 868#ifdef TE_PE
869 {"secrel32", pe_directive_secrel, 0},
870#endif
29b0f896
AM		 871 {0, 0, 0}
872};
873
874/* For interface with expression (). */
875extern char *input_line_pointer;
876
877/* Hash table for instruction mnemonic lookup. */
878static struct hash_control *op_hash;
879
880/* Hash table for register lookup. */
881static struct hash_control *reg_hash;
882\f
252b5132 883void
e3bb37b5 884i386_align_code (fragS *fragP, int count)
252b5132 885{
ce8a8b2f
AM		 886 /* Various efficient no-op patterns for aligning code labels.
887 Note: Don't try to assemble the instructions in the comments.
888 0L and 0w are not legal. */
252b5132
RH		 889 static const char f32_1[] =
890 {0x90}; /* nop */
891 static const char f32_2[] =
ccc9c027 892 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 893 static const char f32_3[] =
894 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
895 static const char f32_4[] =
896 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
897 static const char f32_5[] =
898 {0x90, /* nop */
899 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
900 static const char f32_6[] =
901 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
902 static const char f32_7[] =
903 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
904 static const char f32_8[] =
905 {0x90, /* nop */
906 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
907 static const char f32_9[] =
908 {0x89,0xf6, /* movl %esi,%esi */
909 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
910 static const char f32_10[] =
911 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
912 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
913 static const char f32_11[] =
914 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
915 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
916 static const char f32_12[] =
917 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
918 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
919 static const char f32_13[] =
920 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
921 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
922 static const char f32_14[] =
923 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
924 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 925 static const char f16_3[] =
926 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 927 static const char f16_4[] =
928 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
929 static const char f16_5[] =
930 {0x90, /* nop */
931 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
932 static const char f16_6[] =
933 {0x89,0xf6, /* mov %si,%si */
934 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
935 static const char f16_7[] =
936 {0x8d,0x74,0x00, /* lea 0(%si),%si */
937 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
938 static const char f16_8[] =
939 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
940 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 941 static const char jump_31[] =
942 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
943 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
944 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
945 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 946 static const char *const f32_patt[] = {
947 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 948 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 949 };
950 static const char *const f16_patt[] = {
76bc74dc 951 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 952 };
ccc9c027
L		 953 /* nopl (%[re]ax) */
954 static const char alt_3[] =
955 {0x0f,0x1f,0x00};
956 /* nopl 0(%[re]ax) */
957 static const char alt_4[] =
958 {0x0f,0x1f,0x40,0x00};
959 /* nopl 0(%[re]ax,%[re]ax,1) */
960 static const char alt_5[] =
961 {0x0f,0x1f,0x44,0x00,0x00};
962 /* nopw 0(%[re]ax,%[re]ax,1) */
963 static const char alt_6[] =
964 {0x66,0x0f,0x1f,0x44,0x00,0x00};
965 /* nopl 0L(%[re]ax) */
966 static const char alt_7[] =
967 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
968 /* nopl 0L(%[re]ax,%[re]ax,1) */
969 static const char alt_8[] =
970 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 /* nopw 0L(%[re]ax,%[re]ax,1) */
972 static const char alt_9[] =
973 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
974 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
975 static const char alt_10[] =
976 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
977 /* data16
978 nopw %cs:0L(%[re]ax,%[re]ax,1) */
979 static const char alt_long_11[] =
980 {0x66,
981 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
982 /* data16
983 data16
984 nopw %cs:0L(%[re]ax,%[re]ax,1) */
985 static const char alt_long_12[] =
986 {0x66,
987 0x66,
988 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
989 /* data16
990 data16
991 data16
992 nopw %cs:0L(%[re]ax,%[re]ax,1) */
993 static const char alt_long_13[] =
994 {0x66,
995 0x66,
996 0x66,
997 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
998 /* data16
999 data16
1000 data16
1001 data16
1002 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1003 static const char alt_long_14[] =
1004 {0x66,
1005 0x66,
1006 0x66,
1007 0x66,
1008 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1009 /* data16
1010 data16
1011 data16
1012 data16
1013 data16
1014 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1015 static const char alt_long_15[] =
1016 {0x66,
1017 0x66,
1018 0x66,
1019 0x66,
1020 0x66,
1021 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1022 /* nopl 0(%[re]ax,%[re]ax,1)
1023 nopw 0(%[re]ax,%[re]ax,1) */
1024 static const char alt_short_11[] =
1025 {0x0f,0x1f,0x44,0x00,0x00,
1026 0x66,0x0f,0x1f,0x44,0x00,0x00};
1027 /* nopw 0(%[re]ax,%[re]ax,1)
1028 nopw 0(%[re]ax,%[re]ax,1) */
1029 static const char alt_short_12[] =
1030 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1031 0x66,0x0f,0x1f,0x44,0x00,0x00};
1032 /* nopw 0(%[re]ax,%[re]ax,1)
1033 nopl 0L(%[re]ax) */
1034 static const char alt_short_13[] =
1035 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1036 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1037 /* nopl 0L(%[re]ax)
1038 nopl 0L(%[re]ax) */
1039 static const char alt_short_14[] =
1040 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1041 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1042 /* nopl 0L(%[re]ax)
1043 nopl 0L(%[re]ax,%[re]ax,1) */
1044 static const char alt_short_15[] =
1045 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1046 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1047 static const char *const alt_short_patt[] = {
1048 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1049 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1050 alt_short_14, alt_short_15
1051 };
1052 static const char *const alt_long_patt[] = {
1053 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1054 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1055 alt_long_14, alt_long_15
1056 };
252b5132 1057
76bc74dc
L		 1058 /* Only align for at least a positive non-zero boundary. */
1059 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1060 return;
3e73aa7c 1061
ccc9c027
L		 1062 /* We need to decide which NOP sequence to use for 32bit and
1063 64bit. When -mtune= is used:
4eed87de 1064
76bc74dc
L		 1065 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1066 PROCESSOR_GENERIC32, f32_patt will be used.
1067 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1068 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1069 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1070 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1071 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1072 will be used.
ccc9c027 1073
76bc74dc 1074 When -mtune= isn't used, alt_long_patt will be used if
22109423 1075 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1076 be used.
ccc9c027
L		 1077
1078 When -march= or .arch is used, we can't use anything beyond
1079 cpu_arch_isa_flags. */
1080
1081 if (flag_code == CODE_16BIT)
1082 {
ccc9c027 1083 if (count > 8)
33fef721 1084 {
76bc74dc
L		 1085 memcpy (fragP->fr_literal + fragP->fr_fix,
1086 jump_31, count);
1087 /* Adjust jump offset. */
1088 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1089 }
76bc74dc
L		 1090 else
1091 memcpy (fragP->fr_literal + fragP->fr_fix,
1092 f16_patt[count - 1], count);
252b5132 1093 }
33fef721 1094 else
ccc9c027
L		 1095 {
1096 const char *const *patt = NULL;
1097
fbf3f584 1098 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1099 {
1100 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1101 switch (cpu_arch_tune)
1102 {
1103 case PROCESSOR_UNKNOWN:
1104 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1105 optimize with nops. */
1106 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1107 patt = alt_long_patt;
ccc9c027
L		 1108 else
1109 patt = f32_patt;
1110 break;
ccc9c027
L		 1111 case PROCESSOR_PENTIUM4:
1112 case PROCESSOR_NOCONA:
ef05d495 1113 case PROCESSOR_CORE:
76bc74dc 1114 case PROCESSOR_CORE2:
bd5295b2 1115 case PROCESSOR_COREI7:
3632d14b 1116 case PROCESSOR_L1OM:
7a9068fe 1117 case PROCESSOR_K1OM:
76bc74dc
L		 1118 case PROCESSOR_GENERIC64:
1119 patt = alt_long_patt;
1120 break;
ccc9c027
L		 1121 case PROCESSOR_K6:
1122 case PROCESSOR_ATHLON:
1123 case PROCESSOR_K8:
4eed87de 1124 case PROCESSOR_AMDFAM10:
8aedb9fe 1125 case PROCESSOR_BD:
7b458c12 1126 case PROCESSOR_BT:
ccc9c027
L		 1127 patt = alt_short_patt;
1128 break;
76bc74dc 1129 case PROCESSOR_I386:
ccc9c027
L		 1130 case PROCESSOR_I486:
1131 case PROCESSOR_PENTIUM:
2dde1948 1132 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1133 case PROCESSOR_GENERIC32:
1134 patt = f32_patt;
1135 break;
4eed87de 1136 }
ccc9c027
L		 1137 }
1138 else
1139 {
fbf3f584 1140 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1141 {
1142 case PROCESSOR_UNKNOWN:
e6a14101 1143 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1144 PROCESSOR_UNKNOWN. */
1145 abort ();
1146 break;
1147
76bc74dc 1148 case PROCESSOR_I386:
ccc9c027
L		 1149 case PROCESSOR_I486:
1150 case PROCESSOR_PENTIUM:
ccc9c027
L		 1151 case PROCESSOR_K6:
1152 case PROCESSOR_ATHLON:
1153 case PROCESSOR_K8:
4eed87de 1154 case PROCESSOR_AMDFAM10:
8aedb9fe 1155 case PROCESSOR_BD:
7b458c12 1156 case PROCESSOR_BT:
ccc9c027
L		 1157 case PROCESSOR_GENERIC32:
1158 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1159 with nops. */
1160 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1161 patt = alt_short_patt;
1162 else
1163 patt = f32_patt;
1164 break;
76bc74dc
L		 1165 case PROCESSOR_PENTIUMPRO:
1166 case PROCESSOR_PENTIUM4:
1167 case PROCESSOR_NOCONA:
1168 case PROCESSOR_CORE:
ef05d495 1169 case PROCESSOR_CORE2:
bd5295b2 1170 case PROCESSOR_COREI7:
3632d14b 1171 case PROCESSOR_L1OM:
7a9068fe 1172 case PROCESSOR_K1OM:
22109423 1173 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1174 patt = alt_long_patt;
1175 else
1176 patt = f32_patt;
1177 break;
1178 case PROCESSOR_GENERIC64:
76bc74dc 1179 patt = alt_long_patt;
ccc9c027 1180 break;
4eed87de 1181 }
ccc9c027
L		 1182 }
1183
76bc74dc
L		 1184 if (patt == f32_patt)
1185 {
1186 /* If the padding is less than 15 bytes, we use the normal
1187 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1188 its offset. */
1189 int limit;
76ba9986 1190
711eedef
L		 1191 /* For 64bit, the limit is 3 bytes. */
1192 if (flag_code == CODE_64BIT
1193 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1194 limit = 3;
1195 else
1196 limit = 15;
1197 if (count < limit)
76bc74dc
L		 1198 memcpy (fragP->fr_literal + fragP->fr_fix,
1199 patt[count - 1], count);
1200 else
1201 {
1202 memcpy (fragP->fr_literal + fragP->fr_fix,
1203 jump_31, count);
1204 /* Adjust jump offset. */
1205 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1206 }
1207 }
1208 else
1209 {
1210 /* Maximum length of an instruction is 15 byte. If the
1211 padding is greater than 15 bytes and we don't use jump,
1212 we have to break it into smaller pieces. */
1213 int padding = count;
1214 while (padding > 15)
1215 {
1216 padding -= 15;
1217 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1218 patt [14], 15);
1219 }
1220
1221 if (padding)
1222 memcpy (fragP->fr_literal + fragP->fr_fix,
1223 patt [padding - 1], padding);
1224 }
ccc9c027 1225 }
33fef721 1226 fragP->fr_var = count;
252b5132
RH		 1227}
1228
c6fb90c8 1229static INLINE int
0dfbf9d7 1230operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1231{
0dfbf9d7 1232 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1233 {
1234 case 3:
0dfbf9d7 1235 if (x->array[2])
c6fb90c8
L		 1236 return 0;
1237 case 2:
0dfbf9d7 1238 if (x->array[1])
c6fb90c8
L		 1239 return 0;
1240 case 1:
0dfbf9d7 1241 return !x->array[0];
c6fb90c8
L		 1242 default:
1243 abort ();
1244 }
40fb9820
L		 1245}
1246
c6fb90c8 1247static INLINE void
0dfbf9d7 1248operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1249{
0dfbf9d7 1250 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1251 {
1252 case 3:
0dfbf9d7 1253 x->array[2] = v;
c6fb90c8 1254 case 2:
0dfbf9d7 1255 x->array[1] = v;
c6fb90c8 1256 case 1:
0dfbf9d7 1257 x->array[0] = v;
c6fb90c8
L		 1258 break;
1259 default:
1260 abort ();
1261 }
1262}
40fb9820 1263
c6fb90c8 1264static INLINE int
0dfbf9d7
L		 1265operand_type_equal (const union i386_operand_type *x,
1266 const union i386_operand_type *y)
c6fb90c8 1267{
0dfbf9d7 1268 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1269 {
1270 case 3:
0dfbf9d7 1271 if (x->array[2] != y->array[2])
c6fb90c8
L		 1272 return 0;
1273 case 2:
0dfbf9d7 1274 if (x->array[1] != y->array[1])
c6fb90c8
L		 1275 return 0;
1276 case 1:
0dfbf9d7 1277 return x->array[0] == y->array[0];
c6fb90c8
L		 1278 break;
1279 default:
1280 abort ();
1281 }
1282}
40fb9820 1283
0dfbf9d7
L		 1284static INLINE int
1285cpu_flags_all_zero (const union i386_cpu_flags *x)
1286{
1287 switch (ARRAY_SIZE(x->array))
1288 {
1289 case 3:
1290 if (x->array[2])
1291 return 0;
1292 case 2:
1293 if (x->array[1])
1294 return 0;
1295 case 1:
1296 return !x->array[0];
1297 default:
1298 abort ();
1299 }
1300}
1301
1302static INLINE void
1303cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1304{
1305 switch (ARRAY_SIZE(x->array))
1306 {
1307 case 3:
1308 x->array[2] = v;
1309 case 2:
1310 x->array[1] = v;
1311 case 1:
1312 x->array[0] = v;
1313 break;
1314 default:
1315 abort ();
1316 }
1317}
1318
1319static INLINE int
1320cpu_flags_equal (const union i386_cpu_flags *x,
1321 const union i386_cpu_flags *y)
1322{
1323 switch (ARRAY_SIZE(x->array))
1324 {
1325 case 3:
1326 if (x->array[2] != y->array[2])
1327 return 0;
1328 case 2:
1329 if (x->array[1] != y->array[1])
1330 return 0;
1331 case 1:
1332 return x->array[0] == y->array[0];
1333 break;
1334 default:
1335 abort ();
1336 }
1337}
c6fb90c8
L		 1338
1339static INLINE int
1340cpu_flags_check_cpu64 (i386_cpu_flags f)
1341{
1342 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1343 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1344}
1345
c6fb90c8
L		 1346static INLINE i386_cpu_flags
1347cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1348{
c6fb90c8
L		 1349 switch (ARRAY_SIZE (x.array))
1350 {
1351 case 3:
1352 x.array [2] &= y.array [2];
1353 case 2:
1354 x.array [1] &= y.array [1];
1355 case 1:
1356 x.array [0] &= y.array [0];
1357 break;
1358 default:
1359 abort ();
1360 }
1361 return x;
1362}
40fb9820 1363
c6fb90c8
L		 1364static INLINE i386_cpu_flags
1365cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1366{
c6fb90c8 1367 switch (ARRAY_SIZE (x.array))
40fb9820 1368 {
c6fb90c8
L		 1369 case 3:
1370 x.array [2] |= y.array [2];
1371 case 2:
1372 x.array [1] |= y.array [1];
1373 case 1:
1374 x.array [0] |= y.array [0];
40fb9820
L		 1375 break;
1376 default:
1377 abort ();
1378 }
40fb9820
L		 1379 return x;
1380}
1381
309d3373
JB		 1382static INLINE i386_cpu_flags
1383cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1384{
1385 switch (ARRAY_SIZE (x.array))
1386 {
1387 case 3:
1388 x.array [2] &= ~y.array [2];
1389 case 2:
1390 x.array [1] &= ~y.array [1];
1391 case 1:
1392 x.array [0] &= ~y.array [0];
1393 break;
1394 default:
1395 abort ();
1396 }
1397 return x;
1398}
1399
c0f3af97
L		 1400#define CPU_FLAGS_ARCH_MATCH 0x1
1401#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1402#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1403#define CPU_FLAGS_PCLMUL_MATCH 0x8
1404#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1405
a5ff0eb2 1406#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1407 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1408 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1409#define CPU_FLAGS_PERFECT_MATCH \
1410 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1411
1412/* Return CPU flags match bits. */
3629bb00 1413
40fb9820 1414static int
d3ce72d0 1415cpu_flags_match (const insn_template *t)
40fb9820 1416{
c0f3af97
L		 1417 i386_cpu_flags x = t->cpu_flags;
1418 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1419
1420 x.bitfield.cpu64 = 0;
1421 x.bitfield.cpuno64 = 0;
1422
0dfbf9d7 1423 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1424 {
1425 /* This instruction is available on all archs. */
1426 match |= CPU_FLAGS_32BIT_MATCH;
1427 }
3629bb00
L		 1428 else
1429 {
c0f3af97 1430 /* This instruction is available only on some archs. */
3629bb00
L		 1431 i386_cpu_flags cpu = cpu_arch_flags;
1432
1433 cpu.bitfield.cpu64 = 0;
1434 cpu.bitfield.cpuno64 = 0;
1435 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1436 if (!cpu_flags_all_zero (&cpu))
1437 {
a5ff0eb2
L		 1438 if (x.bitfield.cpuavx)
1439 {
ce2f5b3c 1440 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1441 if (cpu.bitfield.cpuavx)
1442 {
1443 /* Check SSE2AVX. */
1444 if (!t->opcode_modifier.sse2avx|| sse2avx)
1445 {
1446 match |= (CPU_FLAGS_ARCH_MATCH
1447 | CPU_FLAGS_AVX_MATCH);
1448 /* Check AES. */
1449 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1450 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1451 /* Check PCLMUL. */
1452 if (!x.bitfield.cpupclmul
1453 || cpu.bitfield.cpupclmul)
1454 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1455 }
1456 }
1457 else
1458 match |= CPU_FLAGS_ARCH_MATCH;
1459 }
1460 else
c0f3af97
L		 1461 match |= CPU_FLAGS_32BIT_MATCH;
1462 }
3629bb00 1463 }
c0f3af97 1464 return match;
40fb9820
L		 1465}
1466
c6fb90c8
L		 1467static INLINE i386_operand_type
1468operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1469{
c6fb90c8
L		 1470 switch (ARRAY_SIZE (x.array))
1471 {
1472 case 3:
1473 x.array [2] &= y.array [2];
1474 case 2:
1475 x.array [1] &= y.array [1];
1476 case 1:
1477 x.array [0] &= y.array [0];
1478 break;
1479 default:
1480 abort ();
1481 }
1482 return x;
40fb9820
L		 1483}
1484
c6fb90c8
L		 1485static INLINE i386_operand_type
1486operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1487{
c6fb90c8 1488 switch (ARRAY_SIZE (x.array))
40fb9820 1489 {
c6fb90c8
L		 1490 case 3:
1491 x.array [2] |= y.array [2];
1492 case 2:
1493 x.array [1] |= y.array [1];
1494 case 1:
1495 x.array [0] |= y.array [0];
40fb9820
L		 1496 break;
1497 default:
1498 abort ();
1499 }
c6fb90c8
L		 1500 return x;
1501}
40fb9820 1502
c6fb90c8
L		 1503static INLINE i386_operand_type
1504operand_type_xor (i386_operand_type x, i386_operand_type y)
1505{
1506 switch (ARRAY_SIZE (x.array))
1507 {
1508 case 3:
1509 x.array [2] ^= y.array [2];
1510 case 2:
1511 x.array [1] ^= y.array [1];
1512 case 1:
1513 x.array [0] ^= y.array [0];
1514 break;
1515 default:
1516 abort ();
1517 }
40fb9820
L		 1518 return x;
1519}
1520
1521static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1522static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1523static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1524static const i386_operand_type inoutportreg
1525 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1526static const i386_operand_type reg16_inoutportreg
1527 = OPERAND_TYPE_REG16_INOUTPORTREG;
1528static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1529static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1530static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1531static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1532static const i386_operand_type anydisp
1533 = OPERAND_TYPE_ANYDISP;
40fb9820 1534static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1535static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1536static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1537static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1538static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1539static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1540static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1541static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1542static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1543static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1544static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1545static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1546
1547enum operand_type
1548{
1549 reg,
40fb9820
L		 1550 imm,
1551 disp,
1552 anymem
1553};
1554
c6fb90c8 1555static INLINE int
40fb9820
L		 1556operand_type_check (i386_operand_type t, enum operand_type c)
1557{
1558 switch (c)
1559 {
1560 case reg:
1561 return (t.bitfield.reg8
1562 || t.bitfield.reg16
1563 || t.bitfield.reg32
1564 || t.bitfield.reg64);
1565
40fb9820
L		 1566 case imm:
1567 return (t.bitfield.imm8
1568 || t.bitfield.imm8s
1569 || t.bitfield.imm16
1570 || t.bitfield.imm32
1571 || t.bitfield.imm32s
1572 || t.bitfield.imm64);
1573
1574 case disp:
1575 return (t.bitfield.disp8
1576 || t.bitfield.disp16
1577 || t.bitfield.disp32
1578 || t.bitfield.disp32s
1579 || t.bitfield.disp64);
1580
1581 case anymem:
1582 return (t.bitfield.disp8
1583 || t.bitfield.disp16
1584 || t.bitfield.disp32
1585 || t.bitfield.disp32s
1586 || t.bitfield.disp64
1587 || t.bitfield.baseindex);
1588
1589 default:
1590 abort ();
1591 }
2cfe26b6
AM		 1592
1593 return 0;
40fb9820
L		 1594}
1595
5c07affc
L		 1596/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1597 operand J for instruction template T. */
1598
1599static INLINE int
d3ce72d0 1600match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1601{
1602 return !((i.types[j].bitfield.byte
1603 && !t->operand_types[j].bitfield.byte)
1604 || (i.types[j].bitfield.word
1605 && !t->operand_types[j].bitfield.word)
1606 || (i.types[j].bitfield.dword
1607 && !t->operand_types[j].bitfield.dword)
1608 || (i.types[j].bitfield.qword
1609 && !t->operand_types[j].bitfield.qword));
1610}
1611
1612/* Return 1 if there is no conflict in any size on operand J for
1613 instruction template T. */
1614
1615static INLINE int
d3ce72d0 1616match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1617{
1618 return (match_reg_size (t, j)
1619 && !((i.types[j].bitfield.unspecified
1620 && !t->operand_types[j].bitfield.unspecified)
1621 || (i.types[j].bitfield.fword
1622 && !t->operand_types[j].bitfield.fword)
1623 || (i.types[j].bitfield.tbyte
1624 && !t->operand_types[j].bitfield.tbyte)
1625 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1626 && !t->operand_types[j].bitfield.xmmword)
1627 || (i.types[j].bitfield.ymmword
1628 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1629}
1630
1631/* Return 1 if there is no size conflict on any operands for
1632 instruction template T. */
1633
1634static INLINE int
d3ce72d0 1635operand_size_match (const insn_template *t)
5c07affc
L		 1636{
1637 unsigned int j;
1638 int match = 1;
1639
1640 /* Don't check jump instructions. */
1641 if (t->opcode_modifier.jump
1642 || t->opcode_modifier.jumpbyte
1643 || t->opcode_modifier.jumpdword
1644 || t->opcode_modifier.jumpintersegment)
1645 return match;
1646
1647 /* Check memory and accumulator operand size. */
1648 for (j = 0; j < i.operands; j++)
1649 {
1650 if (t->operand_types[j].bitfield.anysize)
1651 continue;
1652
1653 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1654 {
1655 match = 0;
1656 break;
1657 }
1658
1659 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1660 {
1661 match = 0;
1662 break;
1663 }
1664 }
1665
891edac4 1666 if (match)
5c07affc 1667 return match;
891edac4
L		 1668 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1669 {
1670mismatch:
86e026a4 1671 i.error = operand_size_mismatch;
891edac4
L		 1672 return 0;
1673 }
5c07affc
L		 1674
1675 /* Check reverse. */
9c2799c2 1676 gas_assert (i.operands == 2);
5c07affc
L		 1677
1678 match = 1;
1679 for (j = 0; j < 2; j++)
1680 {
1681 if (t->operand_types[j].bitfield.acc
1682 && !match_reg_size (t, j ? 0 : 1))
891edac4 1683 goto mismatch;
5c07affc
L		 1684
1685 if (i.types[j].bitfield.mem
1686 && !match_mem_size (t, j ? 0 : 1))
891edac4 1687 goto mismatch;
5c07affc
L		 1688 }
1689
1690 return match;
1691}
1692
c6fb90c8 1693static INLINE int
40fb9820
L		 1694operand_type_match (i386_operand_type overlap,
1695 i386_operand_type given)
1696{
1697 i386_operand_type temp = overlap;
1698
1699 temp.bitfield.jumpabsolute = 0;
7d5e4556 1700 temp.bitfield.unspecified = 0;
5c07affc
L		 1701 temp.bitfield.byte = 0;
1702 temp.bitfield.word = 0;
1703 temp.bitfield.dword = 0;
1704 temp.bitfield.fword = 0;
1705 temp.bitfield.qword = 0;
1706 temp.bitfield.tbyte = 0;
1707 temp.bitfield.xmmword = 0;
c0f3af97 1708 temp.bitfield.ymmword = 0;
0dfbf9d7 1709 if (operand_type_all_zero (&temp))
891edac4 1710 goto mismatch;
40fb9820 1711
891edac4
L		 1712 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1713 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1714 return 1;
1715
1716mismatch:
a65babc9 1717 i.error = operand_type_mismatch;
891edac4 1718 return 0;
40fb9820
L		 1719}
1720
7d5e4556 1721/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1722 unless the expected operand type register overlap is null.
1723 Note that Acc in a template matches every size of reg. */
1724
c6fb90c8 1725static INLINE int
40fb9820
L		 1726operand_type_register_match (i386_operand_type m0,
1727 i386_operand_type g0,
1728 i386_operand_type t0,
1729 i386_operand_type m1,
1730 i386_operand_type g1,
1731 i386_operand_type t1)
1732{
1733 if (!operand_type_check (g0, reg))
1734 return 1;
1735
1736 if (!operand_type_check (g1, reg))
1737 return 1;
1738
1739 if (g0.bitfield.reg8 == g1.bitfield.reg8
1740 && g0.bitfield.reg16 == g1.bitfield.reg16
1741 && g0.bitfield.reg32 == g1.bitfield.reg32
1742 && g0.bitfield.reg64 == g1.bitfield.reg64)
1743 return 1;
1744
1745 if (m0.bitfield.acc)
1746 {
1747 t0.bitfield.reg8 = 1;
1748 t0.bitfield.reg16 = 1;
1749 t0.bitfield.reg32 = 1;
1750 t0.bitfield.reg64 = 1;
1751 }
1752
1753 if (m1.bitfield.acc)
1754 {
1755 t1.bitfield.reg8 = 1;
1756 t1.bitfield.reg16 = 1;
1757 t1.bitfield.reg32 = 1;
1758 t1.bitfield.reg64 = 1;
1759 }
1760
891edac4
L		 1761 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1762 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1763 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1764 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1765 return 1;
1766
a65babc9 1767 i.error = register_type_mismatch;
891edac4
L		 1768
1769 return 0;
40fb9820
L		 1770}
1771
4c692bc7
JB		 1772static INLINE unsigned int
1773register_number (const reg_entry *r)
1774{
1775 unsigned int nr = r->reg_num;
1776
1777 if (r->reg_flags & RegRex)
1778 nr += 8;
1779
1780 return nr;
1781}
1782
252b5132 1783static INLINE unsigned int
40fb9820 1784mode_from_disp_size (i386_operand_type t)
252b5132 1785{
40fb9820
L		 1786 if (t.bitfield.disp8)
1787 return 1;
1788 else if (t.bitfield.disp16
1789 || t.bitfield.disp32
1790 || t.bitfield.disp32s)
1791 return 2;
1792 else
1793 return 0;
252b5132
RH		 1794}
1795
1796static INLINE int
e3bb37b5 1797fits_in_signed_byte (offsetT num)
252b5132
RH		 1798{
1799 return (num >= -128) && (num <= 127);
47926f60 1800}
252b5132
RH		 1801
1802static INLINE int
e3bb37b5 1803fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1804{
1805 return (num & 0xff) == num;
47926f60 1806}
252b5132
RH		 1807
1808static INLINE int
e3bb37b5 1809fits_in_unsigned_word (offsetT num)
252b5132
RH		 1810{
1811 return (num & 0xffff) == num;
47926f60 1812}
252b5132
RH		 1813
1814static INLINE int
e3bb37b5 1815fits_in_signed_word (offsetT num)
252b5132
RH		 1816{
1817 return (-32768 <= num) && (num <= 32767);
47926f60 1818}
2a962e6d 1819
3e73aa7c 1820static INLINE int
e3bb37b5 1821fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1822{
1823#ifndef BFD64
1824 return 1;
1825#else
1826 return (!(((offsetT) -1 << 31) & num)
1827 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1828#endif
1829} /* fits_in_signed_long() */
2a962e6d 1830
3e73aa7c 1831static INLINE int
e3bb37b5 1832fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1833{
1834#ifndef BFD64
1835 return 1;
1836#else
1837 return (num & (((offsetT) 2 << 31) - 1)) == num;
1838#endif
1839} /* fits_in_unsigned_long() */
252b5132 1840
a683cc34
SP		 1841static INLINE int
1842fits_in_imm4 (offsetT num)
1843{
1844 return (num & 0xf) == num;
1845}
1846
40fb9820 1847static i386_operand_type
e3bb37b5 1848smallest_imm_type (offsetT num)
252b5132 1849{
40fb9820 1850 i386_operand_type t;
7ab9ffdd 1851
0dfbf9d7 1852 operand_type_set (&t, 0);
40fb9820
L		 1853 t.bitfield.imm64 = 1;
1854
1855 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1856 {
1857 /* This code is disabled on the 486 because all the Imm1 forms
1858 in the opcode table are slower on the i486. They're the
1859 versions with the implicitly specified single-position
1860 displacement, which has another syntax if you really want to
1861 use that form. */
40fb9820
L		 1862 t.bitfield.imm1 = 1;
1863 t.bitfield.imm8 = 1;
1864 t.bitfield.imm8s = 1;
1865 t.bitfield.imm16 = 1;
1866 t.bitfield.imm32 = 1;
1867 t.bitfield.imm32s = 1;
1868 }
1869 else if (fits_in_signed_byte (num))
1870 {
1871 t.bitfield.imm8 = 1;
1872 t.bitfield.imm8s = 1;
1873 t.bitfield.imm16 = 1;
1874 t.bitfield.imm32 = 1;
1875 t.bitfield.imm32s = 1;
1876 }
1877 else if (fits_in_unsigned_byte (num))
1878 {
1879 t.bitfield.imm8 = 1;
1880 t.bitfield.imm16 = 1;
1881 t.bitfield.imm32 = 1;
1882 t.bitfield.imm32s = 1;
1883 }
1884 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1885 {
1886 t.bitfield.imm16 = 1;
1887 t.bitfield.imm32 = 1;
1888 t.bitfield.imm32s = 1;
1889 }
1890 else if (fits_in_signed_long (num))
1891 {
1892 t.bitfield.imm32 = 1;
1893 t.bitfield.imm32s = 1;
1894 }
1895 else if (fits_in_unsigned_long (num))
1896 t.bitfield.imm32 = 1;
1897
1898 return t;
47926f60 1899}
252b5132 1900
847f7ad4 1901static offsetT
e3bb37b5 1902offset_in_range (offsetT val, int size)
847f7ad4 1903{
508866be 1904 addressT mask;
ba2adb93 1905
847f7ad4
AM		 1906 switch (size)
1907 {
508866be
L		 1908 case 1: mask = ((addressT) 1 << 8) - 1; break;
1909 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1910 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1911#ifdef BFD64
1912 case 8: mask = ((addressT) 2 << 63) - 1; break;
1913#endif
47926f60 1914 default: abort ();
847f7ad4
AM		 1915 }
1916
9de868bf
L		 1917#ifdef BFD64
1918 /* If BFD64, sign extend val for 32bit address mode. */
1919 if (flag_code != CODE_64BIT
1920 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1921 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1922 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1923#endif
ba2adb93 1924
47926f60 1925 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1926 {
1927 char buf1[40], buf2[40];
1928
1929 sprint_value (buf1, val);
1930 sprint_value (buf2, val & mask);
1931 as_warn (_("%s shortened to %s"), buf1, buf2);
1932 }
1933 return val & mask;
1934}
1935
c32fa91d
L		 1936enum PREFIX_GROUP
1937{
1938 PREFIX_EXIST = 0,
1939 PREFIX_LOCK,
1940 PREFIX_REP,
1941 PREFIX_OTHER
1942};
1943
1944/* Returns
1945 a. PREFIX_EXIST if attempting to add a prefix where one from the
1946 same class already exists.
1947 b. PREFIX_LOCK if lock prefix is added.
1948 c. PREFIX_REP if rep/repne prefix is added.
1949 d. PREFIX_OTHER if other prefix is added.
1950 */
1951
1952static enum PREFIX_GROUP
e3bb37b5 1953add_prefix (unsigned int prefix)
252b5132 1954{
c32fa91d 1955 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1956 unsigned int q;
252b5132 1957
29b0f896
AM		 1958 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1959 && flag_code == CODE_64BIT)
b1905489 1960 {
161a04f6
L		 1961 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1962 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1963 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1964 ret = PREFIX_EXIST;
b1905489
JB		 1965 q = REX_PREFIX;
1966 }
3e73aa7c 1967 else
b1905489
JB		 1968 {
1969 switch (prefix)
1970 {
1971 default:
1972 abort ();
1973
1974 case CS_PREFIX_OPCODE:
1975 case DS_PREFIX_OPCODE:
1976 case ES_PREFIX_OPCODE:
1977 case FS_PREFIX_OPCODE:
1978 case GS_PREFIX_OPCODE:
1979 case SS_PREFIX_OPCODE:
1980 q = SEG_PREFIX;
1981 break;
1982
1983 case REPNE_PREFIX_OPCODE:
1984 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1985 q = REP_PREFIX;
1986 ret = PREFIX_REP;
1987 break;
1988
b1905489 1989 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1990 q = LOCK_PREFIX;
1991 ret = PREFIX_LOCK;
b1905489
JB		 1992 break;
1993
1994 case FWAIT_OPCODE:
1995 q = WAIT_PREFIX;
1996 break;
1997
1998 case ADDR_PREFIX_OPCODE:
1999 q = ADDR_PREFIX;
2000 break;
2001
2002 case DATA_PREFIX_OPCODE:
2003 q = DATA_PREFIX;
2004 break;
2005 }
2006 if (i.prefix[q] != 0)
c32fa91d 2007 ret = PREFIX_EXIST;
b1905489 2008 }
252b5132 2009
b1905489 2010 if (ret)
252b5132 2011 {
b1905489
JB		 2012 if (!i.prefix[q])
2013 ++i.prefixes;
2014 i.prefix[q] |= prefix;
252b5132 2015 }
b1905489
JB		 2016 else
2017 as_bad (_("same type of prefix used twice"));
252b5132 2018
252b5132
RH		 2019 return ret;
2020}
2021
2022static void
78f12dd3 2023update_code_flag (int value, int check)
eecb386c 2024{
78f12dd3
L		 2025 PRINTF_LIKE ((*as_error));
2026
1e9cc1c2 2027 flag_code = (enum flag_code) value;
40fb9820
L		 2028 if (flag_code == CODE_64BIT)
2029 {
2030 cpu_arch_flags.bitfield.cpu64 = 1;
2031 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2032 }
2033 else
2034 {
2035 cpu_arch_flags.bitfield.cpu64 = 0;
2036 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2037 }
2038 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2039 {
78f12dd3
L		 2040 if (check)
2041 as_error = as_fatal;
2042 else
2043 as_error = as_bad;
2044 (*as_error) (_("64bit mode not supported on `%s'."),
2045 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2046 }
40fb9820 2047 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2048 {
78f12dd3
L		 2049 if (check)
2050 as_error = as_fatal;
2051 else
2052 as_error = as_bad;
2053 (*as_error) (_("32bit mode not supported on `%s'."),
2054 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2055 }
eecb386c
AM		 2056 stackop_size = '\0';
2057}
2058
78f12dd3
L		 2059static void
2060set_code_flag (int value)
2061{
2062 update_code_flag (value, 0);
2063}
2064
eecb386c 2065static void
e3bb37b5 2066set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2067{
1e9cc1c2 2068 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2069 if (flag_code != CODE_16BIT)
2070 abort ();
2071 cpu_arch_flags.bitfield.cpu64 = 0;
2072 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2073 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2074}
2075
2076static void
e3bb37b5 2077set_intel_syntax (int syntax_flag)
252b5132
RH		 2078{
2079 /* Find out if register prefixing is specified. */
2080 int ask_naked_reg = 0;
2081
2082 SKIP_WHITESPACE ();
29b0f896 2083 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2084 {
2085 char *string = input_line_pointer;
2086 int e = get_symbol_end ();
2087
47926f60 2088 if (strcmp (string, "prefix") == 0)
252b5132 2089 ask_naked_reg = 1;
47926f60 2090 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2091 ask_naked_reg = -1;
2092 else
d0b47220 2093 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2094 *input_line_pointer = e;
2095 }
2096 demand_empty_rest_of_line ();
c3332e24 2097
252b5132
RH		 2098 intel_syntax = syntax_flag;
2099
2100 if (ask_naked_reg == 0)
f86103b7
AM		 2101 allow_naked_reg = (intel_syntax
2102 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2103 else
2104 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2105
ee86248c 2106 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2107
e4a3b5a4 2108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2109 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2110 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2111}
2112
1efbbeb4
L		 2113static void
2114set_intel_mnemonic (int mnemonic_flag)
2115{
e1d4d893 2116 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2117}
2118
db51cc60
L		 2119static void
2120set_allow_index_reg (int flag)
2121{
2122 allow_index_reg = flag;
2123}
2124
cb19c032 2125static void
7bab8ab5 2126set_check (int what)
cb19c032 2127{
7bab8ab5
JB		 2128 enum check_kind *kind;
2129 const char *str;
2130
2131 if (what)
2132 {
2133 kind = &operand_check;
2134 str = "operand";
2135 }
2136 else
2137 {
2138 kind = &sse_check;
2139 str = "sse";
2140 }
2141
cb19c032
L		 2142 SKIP_WHITESPACE ();
2143
2144 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2145 {
2146 char *string = input_line_pointer;
2147 int e = get_symbol_end ();
2148
2149 if (strcmp (string, "none") == 0)
7bab8ab5 2150 *kind = check_none;
cb19c032 2151 else if (strcmp (string, "warning") == 0)
7bab8ab5 2152 *kind = check_warning;
cb19c032 2153 else if (strcmp (string, "error") == 0)
7bab8ab5 2154 *kind = check_error;
cb19c032 2155 else
7bab8ab5 2156 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2157 *input_line_pointer = e;
2158 }
2159 else
7bab8ab5 2160 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2161
2162 demand_empty_rest_of_line ();
2163}
2164
8a9036a4
L		 2165static void
2166check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2167 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2168{
2169#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2170 static const char *arch;
2171
2172 /* Intel LIOM is only supported on ELF. */
2173 if (!IS_ELF)
2174 return;
2175
2176 if (!arch)
2177 {
2178 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2179 use default_arch. */
2180 arch = cpu_arch_name;
2181 if (!arch)
2182 arch = default_arch;
2183 }
2184
3632d14b 2185 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2186 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2187 || new_flag.bitfield.cpul1om)
8a9036a4 2188 return;
76ba9986 2189
7a9068fe
L		 2190 /* If we are targeting Intel K1OM, we must enable it. */
2191 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2192 || new_flag.bitfield.cpuk1om)
2193 return;
2194
8a9036a4
L		 2195 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2196#endif
2197}
2198
e413e4e9 2199static void
e3bb37b5 2200set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2201{
47926f60 2202 SKIP_WHITESPACE ();
e413e4e9 2203
29b0f896 2204 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2205 {
2206 char *string = input_line_pointer;
2207 int e = get_symbol_end ();
91d6fa6a 2208 unsigned int j;
40fb9820 2209 i386_cpu_flags flags;
e413e4e9 2210
91d6fa6a 2211 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2212 {
91d6fa6a 2213 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2214 {
91d6fa6a 2215 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2216
5c6af06e
JB		 2217 if (*string != '.')
2218 {
91d6fa6a 2219 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2220 cpu_sub_arch_name = NULL;
91d6fa6a 2221 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2222 if (flag_code == CODE_64BIT)
2223 {
2224 cpu_arch_flags.bitfield.cpu64 = 1;
2225 cpu_arch_flags.bitfield.cpuno64 = 0;
2226 }
2227 else
2228 {
2229 cpu_arch_flags.bitfield.cpu64 = 0;
2230 cpu_arch_flags.bitfield.cpuno64 = 1;
2231 }
91d6fa6a
NC		 2232 cpu_arch_isa = cpu_arch[j].type;
2233 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2234 if (!cpu_arch_tune_set)
2235 {
2236 cpu_arch_tune = cpu_arch_isa;
2237 cpu_arch_tune_flags = cpu_arch_isa_flags;
2238 }
5c6af06e
JB		 2239 break;
2240 }
40fb9820 2241
22109423 2242 if (!cpu_arch[j].negated)
309d3373 2243 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2244 cpu_arch[j].flags);
309d3373
JB		 2245 else
2246 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2247 cpu_arch[j].flags);
0dfbf9d7 2248 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2249 {
6305a203
L		 2250 if (cpu_sub_arch_name)
2251 {
2252 char *name = cpu_sub_arch_name;
2253 cpu_sub_arch_name = concat (name,
91d6fa6a 2254 cpu_arch[j].name,
1bf57e9f 2255 (const char *) NULL);
6305a203
L		 2256 free (name);
2257 }
2258 else
91d6fa6a 2259 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2260 cpu_arch_flags = flags;
a586129e 2261 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2262 }
2263 *input_line_pointer = e;
2264 demand_empty_rest_of_line ();
2265 return;
e413e4e9
AM		 2266 }
2267 }
91d6fa6a 2268 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2269 as_bad (_("no such architecture: `%s'"), string);
2270
2271 *input_line_pointer = e;
2272 }
2273 else
2274 as_bad (_("missing cpu architecture"));
2275
fddf5b5b
AM		 2276 no_cond_jump_promotion = 0;
2277 if (*input_line_pointer == ','
29b0f896 2278 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2279 {
2280 char *string = ++input_line_pointer;
2281 int e = get_symbol_end ();
2282
2283 if (strcmp (string, "nojumps") == 0)
2284 no_cond_jump_promotion = 1;
2285 else if (strcmp (string, "jumps") == 0)
2286 ;
2287 else
2288 as_bad (_("no such architecture modifier: `%s'"), string);
2289
2290 *input_line_pointer = e;
2291 }
2292
e413e4e9
AM		 2293 demand_empty_rest_of_line ();
2294}
2295
8a9036a4
L		 2296enum bfd_architecture
2297i386_arch (void)
2298{
3632d14b 2299 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2300 {
2301 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2302 || flag_code != CODE_64BIT)
2303 as_fatal (_("Intel L1OM is 64bit ELF only"));
2304 return bfd_arch_l1om;
2305 }
7a9068fe
L		 2306 else if (cpu_arch_isa == PROCESSOR_K1OM)
2307 {
2308 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2309 || flag_code != CODE_64BIT)
2310 as_fatal (_("Intel K1OM is 64bit ELF only"));
2311 return bfd_arch_k1om;
2312 }
8a9036a4
L		 2313 else
2314 return bfd_arch_i386;
2315}
2316
b9d79e03 2317unsigned long
7016a5d5 2318i386_mach (void)
b9d79e03 2319{
351f65ca 2320 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2321 {
3632d14b 2322 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2323 {
351f65ca
L		 2324 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2325 || default_arch[6] != '\0')
8a9036a4
L		 2326 as_fatal (_("Intel L1OM is 64bit ELF only"));
2327 return bfd_mach_l1om;
2328 }
7a9068fe
L		 2329 else if (cpu_arch_isa == PROCESSOR_K1OM)
2330 {
2331 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2332 || default_arch[6] != '\0')
2333 as_fatal (_("Intel K1OM is 64bit ELF only"));
2334 return bfd_mach_k1om;
2335 }
351f65ca 2336 else if (default_arch[6] == '\0')
8a9036a4 2337 return bfd_mach_x86_64;
351f65ca
L		 2338 else
2339 return bfd_mach_x64_32;
8a9036a4 2340 }
b9d79e03
JH		 2341 else if (!strcmp (default_arch, "i386"))
2342 return bfd_mach_i386_i386;
2343 else
2b5d6a91 2344 as_fatal (_("unknown architecture"));
b9d79e03 2345}
b9d79e03 2346\f
252b5132 2347void
7016a5d5 2348md_begin (void)
252b5132
RH		 2349{
2350 const char *hash_err;
2351
47926f60 2352 /* Initialize op_hash hash table. */
252b5132
RH		 2353 op_hash = hash_new ();
2354
2355 {
d3ce72d0 2356 const insn_template *optab;
29b0f896 2357 templates *core_optab;
252b5132 2358
47926f60
KH		 2359 /* Setup for loop. */
2360 optab = i386_optab;
252b5132
RH		 2361 core_optab = (templates *) xmalloc (sizeof (templates));
2362 core_optab->start = optab;
2363
2364 while (1)
2365 {
2366 ++optab;
2367 if (optab->name == NULL
2368 || strcmp (optab->name, (optab - 1)->name) != 0)
2369 {
2370 /* different name --> ship out current template list;
47926f60 2371 add to hash table; & begin anew. */
252b5132
RH		 2372 core_optab->end = optab;
2373 hash_err = hash_insert (op_hash,
2374 (optab - 1)->name,
5a49b8ac 2375 (void *) core_optab);
252b5132
RH		 2376 if (hash_err)
2377 {
b37df7c4 2378 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2379 (optab - 1)->name,
2380 hash_err);
2381 }
2382 if (optab->name == NULL)
2383 break;
2384 core_optab = (templates *) xmalloc (sizeof (templates));
2385 core_optab->start = optab;
2386 }
2387 }
2388 }
2389
47926f60 2390 /* Initialize reg_hash hash table. */
252b5132
RH		 2391 reg_hash = hash_new ();
2392 {
29b0f896 2393 const reg_entry *regtab;
c3fe08fa 2394 unsigned int regtab_size = i386_regtab_size;
252b5132 2395
c3fe08fa 2396 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2397 {
5a49b8ac 2398 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2399 if (hash_err)
b37df7c4 2400 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2401 regtab->reg_name,
2402 hash_err);
252b5132
RH		 2403 }
2404 }
2405
47926f60 2406 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2407 {
29b0f896
AM		 2408 int c;
2409 char *p;
252b5132
RH		 2410
2411 for (c = 0; c < 256; c++)
2412 {
3882b010 2413 if (ISDIGIT (c))
252b5132
RH		 2414 {
2415 digit_chars[c] = c;
2416 mnemonic_chars[c] = c;
2417 register_chars[c] = c;
2418 operand_chars[c] = c;
2419 }
3882b010 2420 else if (ISLOWER (c))
252b5132
RH		 2421 {
2422 mnemonic_chars[c] = c;
2423 register_chars[c] = c;
2424 operand_chars[c] = c;
2425 }
3882b010 2426 else if (ISUPPER (c))
252b5132 2427 {
3882b010 2428 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2429 register_chars[c] = mnemonic_chars[c];
2430 operand_chars[c] = c;
2431 }
2432
3882b010 2433 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2434 identifier_chars[c] = c;
2435 else if (c >= 128)
2436 {
2437 identifier_chars[c] = c;
2438 operand_chars[c] = c;
2439 }
2440 }
2441
2442#ifdef LEX_AT
2443 identifier_chars['@'] = '@';
32137342
NC		 2444#endif
2445#ifdef LEX_QM
2446 identifier_chars['?'] = '?';
2447 operand_chars['?'] = '?';
252b5132 2448#endif
252b5132 2449 digit_chars['-'] = '-';
c0f3af97 2450 mnemonic_chars['_'] = '_';
791fe849 2451 mnemonic_chars['-'] = '-';
0003779b 2452 mnemonic_chars['.'] = '.';
252b5132
RH		 2453 identifier_chars['_'] = '_';
2454 identifier_chars['.'] = '.';
2455
2456 for (p = operand_special_chars; *p != '\0'; p++)
2457 operand_chars[(unsigned char) *p] = *p;
2458 }
2459
2460#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2461 if (IS_ELF)
252b5132
RH		 2462 {
2463 record_alignment (text_section, 2);
2464 record_alignment (data_section, 2);
2465 record_alignment (bss_section, 2);
2466 }
2467#endif
a4447b93
RH		 2468
2469 if (flag_code == CODE_64BIT)
2470 {
ca19b261
KT		 2471#if defined (OBJ_COFF) && defined (TE_PE)
2472 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2473 ? 32 : 16);
2474#else
a4447b93 2475 x86_dwarf2_return_column = 16;
ca19b261 2476#endif
61ff971f 2477 x86_cie_data_alignment = -8;
a4447b93
RH		 2478 }
2479 else
2480 {
2481 x86_dwarf2_return_column = 8;
2482 x86_cie_data_alignment = -4;
2483 }
252b5132
RH		 2484}
2485
2486void
e3bb37b5 2487i386_print_statistics (FILE *file)
252b5132
RH		 2488{
2489 hash_print_statistics (file, "i386 opcode", op_hash);
2490 hash_print_statistics (file, "i386 register", reg_hash);
2491}
2492\f
252b5132
RH		 2493#ifdef DEBUG386
2494
ce8a8b2f 2495/* Debugging routines for md_assemble. */
d3ce72d0 2496static void pte (insn_template *);
40fb9820 2497static void pt (i386_operand_type);
e3bb37b5
L		 2498static void pe (expressionS *);
2499static void ps (symbolS *);
252b5132
RH		 2500
2501static void
e3bb37b5 2502pi (char *line, i386_insn *x)
252b5132 2503{
09137c09 2504 unsigned int j;
252b5132
RH		 2505
2506 fprintf (stdout, "%s: template ", line);
2507 pte (&x->tm);
09f131f2
JH		 2508 fprintf (stdout, " address: base %s index %s scale %x\n",
2509 x->base_reg ? x->base_reg->reg_name : "none",
2510 x->index_reg ? x->index_reg->reg_name : "none",
2511 x->log2_scale_factor);
2512 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2513 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2514 fprintf (stdout, " sib: base %x index %x scale %x\n",
2515 x->sib.base, x->sib.index, x->sib.scale);
2516 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2517 (x->rex & REX_W) != 0,
2518 (x->rex & REX_R) != 0,
2519 (x->rex & REX_X) != 0,
2520 (x->rex & REX_B) != 0);
09137c09 2521 for (j = 0; j < x->operands; j++)
252b5132 2522 {
09137c09
SP		 2523 fprintf (stdout, " #%d: ", j + 1);
2524 pt (x->types[j]);
252b5132 2525 fprintf (stdout, "\n");
09137c09
SP		 2526 if (x->types[j].bitfield.reg8
2527 || x->types[j].bitfield.reg16
2528 || x->types[j].bitfield.reg32
2529 || x->types[j].bitfield.reg64
2530 || x->types[j].bitfield.regmmx
2531 || x->types[j].bitfield.regxmm
2532 || x->types[j].bitfield.regymm
2533 || x->types[j].bitfield.sreg2
2534 || x->types[j].bitfield.sreg3
2535 || x->types[j].bitfield.control
2536 || x->types[j].bitfield.debug
2537 || x->types[j].bitfield.test)
2538 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2539 if (operand_type_check (x->types[j], imm))
2540 pe (x->op[j].imms);
2541 if (operand_type_check (x->types[j], disp))
2542 pe (x->op[j].disps);
252b5132
RH		 2543 }
2544}
2545
2546static void
d3ce72d0 2547pte (insn_template *t)
252b5132 2548{
09137c09 2549 unsigned int j;
252b5132 2550 fprintf (stdout, " %d operands ", t->operands);
47926f60 2551 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2552 if (t->extension_opcode != None)
2553 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2554 if (t->opcode_modifier.d)
252b5132 2555 fprintf (stdout, "D");
40fb9820 2556 if (t->opcode_modifier.w)
252b5132
RH		 2557 fprintf (stdout, "W");
2558 fprintf (stdout, "\n");
09137c09 2559 for (j = 0; j < t->operands; j++)
252b5132 2560 {
09137c09
SP		 2561 fprintf (stdout, " #%d type ", j + 1);
2562 pt (t->operand_types[j]);
252b5132
RH		 2563 fprintf (stdout, "\n");
2564 }
2565}
2566
2567static void
e3bb37b5 2568pe (expressionS *e)
252b5132 2569{
24eab124 2570 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2571 fprintf (stdout, " add_number %ld (%lx)\n",
2572 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2573 if (e->X_add_symbol)
2574 {
2575 fprintf (stdout, " add_symbol ");
2576 ps (e->X_add_symbol);
2577 fprintf (stdout, "\n");
2578 }
2579 if (e->X_op_symbol)
2580 {
2581 fprintf (stdout, " op_symbol ");
2582 ps (e->X_op_symbol);
2583 fprintf (stdout, "\n");
2584 }
2585}
2586
2587static void
e3bb37b5 2588ps (symbolS *s)
252b5132
RH		 2589{
2590 fprintf (stdout, "%s type %s%s",
2591 S_GET_NAME (s),
2592 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2593 segment_name (S_GET_SEGMENT (s)));
2594}
2595
7b81dfbb 2596static struct type_name
252b5132 2597 {
40fb9820
L		 2598 i386_operand_type mask;
2599 const char *name;
252b5132 2600 }
7b81dfbb 2601const type_names[] =
252b5132 2602{
40fb9820
L		 2603 { OPERAND_TYPE_REG8, "r8" },
2604 { OPERAND_TYPE_REG16, "r16" },
2605 { OPERAND_TYPE_REG32, "r32" },
2606 { OPERAND_TYPE_REG64, "r64" },
2607 { OPERAND_TYPE_IMM8, "i8" },
2608 { OPERAND_TYPE_IMM8, "i8s" },
2609 { OPERAND_TYPE_IMM16, "i16" },
2610 { OPERAND_TYPE_IMM32, "i32" },
2611 { OPERAND_TYPE_IMM32S, "i32s" },
2612 { OPERAND_TYPE_IMM64, "i64" },
2613 { OPERAND_TYPE_IMM1, "i1" },
2614 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2615 { OPERAND_TYPE_DISP8, "d8" },
2616 { OPERAND_TYPE_DISP16, "d16" },
2617 { OPERAND_TYPE_DISP32, "d32" },
2618 { OPERAND_TYPE_DISP32S, "d32s" },
2619 { OPERAND_TYPE_DISP64, "d64" },
2620 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2621 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2622 { OPERAND_TYPE_CONTROL, "control reg" },
2623 { OPERAND_TYPE_TEST, "test reg" },
2624 { OPERAND_TYPE_DEBUG, "debug reg" },
2625 { OPERAND_TYPE_FLOATREG, "FReg" },
2626 { OPERAND_TYPE_FLOATACC, "FAcc" },
2627 { OPERAND_TYPE_SREG2, "SReg2" },
2628 { OPERAND_TYPE_SREG3, "SReg3" },
2629 { OPERAND_TYPE_ACC, "Acc" },
2630 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2631 { OPERAND_TYPE_REGMMX, "rMMX" },
2632 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2633 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2634 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2635};
2636
2637static void
40fb9820 2638pt (i386_operand_type t)
252b5132 2639{
40fb9820 2640 unsigned int j;
c6fb90c8 2641 i386_operand_type a;
252b5132 2642
40fb9820 2643 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2644 {
2645 a = operand_type_and (t, type_names[j].mask);
0349dc08 2646 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2647 fprintf (stdout, "%s, ", type_names[j].name);
2648 }
252b5132
RH		 2649 fflush (stdout);
2650}
2651
2652#endif /* DEBUG386 */
2653\f
252b5132 2654static bfd_reloc_code_real_type
3956db08 2655reloc (unsigned int size,
64e74474
AM		 2656 int pcrel,
2657 int sign,
2658 bfd_reloc_code_real_type other)
252b5132 2659{
47926f60 2660 if (other != NO_RELOC)
3956db08 2661 {
91d6fa6a 2662 reloc_howto_type *rel;
3956db08
JB		 2663
2664 if (size == 8)
2665 switch (other)
2666 {
64e74474
AM		 2667 case BFD_RELOC_X86_64_GOT32:
2668 return BFD_RELOC_X86_64_GOT64;
2669 break;
2670 case BFD_RELOC_X86_64_PLTOFF64:
2671 return BFD_RELOC_X86_64_PLTOFF64;
2672 break;
2673 case BFD_RELOC_X86_64_GOTPC32:
2674 other = BFD_RELOC_X86_64_GOTPC64;
2675 break;
2676 case BFD_RELOC_X86_64_GOTPCREL:
2677 other = BFD_RELOC_X86_64_GOTPCREL64;
2678 break;
2679 case BFD_RELOC_X86_64_TPOFF32:
2680 other = BFD_RELOC_X86_64_TPOFF64;
2681 break;
2682 case BFD_RELOC_X86_64_DTPOFF32:
2683 other = BFD_RELOC_X86_64_DTPOFF64;
2684 break;
2685 default:
2686 break;
3956db08 2687 }
e05278af 2688
8fd4256d
L		 2689 if (other == BFD_RELOC_SIZE32)
2690 {
2691 if (size == 8)
2692 return BFD_RELOC_SIZE64;
2693 if (pcrel)
2694 as_bad (_("there are no pc-relative size relocations"));
2695 }
2696
e05278af 2697 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2698 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2699 sign = -1;
2700
91d6fa6a
NC		 2701 rel = bfd_reloc_type_lookup (stdoutput, other);
2702 if (!rel)
3956db08 2703 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2704 else if (size != bfd_get_reloc_size (rel))
3956db08 2705 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2706 bfd_get_reloc_size (rel),
3956db08 2707 size);
91d6fa6a 2708 else if (pcrel && !rel->pc_relative)
3956db08 2709 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2710 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2711 && !sign)
91d6fa6a 2712 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2713 && sign > 0))
3956db08
JB		 2714 as_bad (_("relocated field and relocation type differ in signedness"));
2715 else
2716 return other;
2717 return NO_RELOC;
2718 }
252b5132
RH		 2719
2720 if (pcrel)
2721 {
3e73aa7c 2722 if (!sign)
3956db08 2723 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2724 switch (size)
2725 {
2726 case 1: return BFD_RELOC_8_PCREL;
2727 case 2: return BFD_RELOC_16_PCREL;
2728 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2729 case 8: return BFD_RELOC_64_PCREL;
252b5132 2730 }
3956db08 2731 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2732 }
2733 else
2734 {
3956db08 2735 if (sign > 0)
e5cb08ac 2736 switch (size)
3e73aa7c
JH		 2737 {
2738 case 4: return BFD_RELOC_X86_64_32S;
2739 }
2740 else
2741 switch (size)
2742 {
2743 case 1: return BFD_RELOC_8;
2744 case 2: return BFD_RELOC_16;
2745 case 4: return BFD_RELOC_32;
2746 case 8: return BFD_RELOC_64;
2747 }
3956db08
JB		 2748 as_bad (_("cannot do %s %u byte relocation"),
2749 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2750 }
2751
0cc9e1d3 2752 return NO_RELOC;
252b5132
RH		 2753}
2754
47926f60
KH		 2755/* Here we decide which fixups can be adjusted to make them relative to
2756 the beginning of the section instead of the symbol. Basically we need
2757 to make sure that the dynamic relocations are done correctly, so in
2758 some cases we force the original symbol to be used. */
2759
252b5132 2760int
e3bb37b5 2761tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2762{
6d249963 2763#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2764 if (!IS_ELF)
31312f95
AM		 2765 return 1;
2766
a161fe53
AM		 2767 /* Don't adjust pc-relative references to merge sections in 64-bit
2768 mode. */
2769 if (use_rela_relocations
2770 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2771 && fixP->fx_pcrel)
252b5132 2772 return 0;
31312f95 2773
8d01d9a9
AJ		 2774 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2775 and changed later by validate_fix. */
2776 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2777 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2778 return 0;
2779
8fd4256d
L		 2780 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2781 for size relocations. */
2782 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2783 || fixP->fx_r_type == BFD_RELOC_SIZE64
2784 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2785 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2786 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2787 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2788 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2789 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2790 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2791 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2792 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2793 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2794 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2795 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2796 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2797 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2798 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2799 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2800 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2801 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2802 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2803 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2804 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2805 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2806 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2807 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2808 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2809 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2810 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2811 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2812 return 0;
31312f95 2813#endif
252b5132
RH		 2814 return 1;
2815}
252b5132 2816
b4cac588 2817static int
e3bb37b5 2818intel_float_operand (const char *mnemonic)
252b5132 2819{
9306ca4a
JB		 2820 /* Note that the value returned is meaningful only for opcodes with (memory)
2821 operands, hence the code here is free to improperly handle opcodes that
2822 have no operands (for better performance and smaller code). */
2823
2824 if (mnemonic[0] != 'f')
2825 return 0; /* non-math */
2826
2827 switch (mnemonic[1])
2828 {
2829 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2830 the fs segment override prefix not currently handled because no
2831 call path can make opcodes without operands get here */
2832 case 'i':
2833 return 2 /* integer op */;
2834 case 'l':
2835 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2836 return 3; /* fldcw/fldenv */
2837 break;
2838 case 'n':
2839 if (mnemonic[2] != 'o' /* fnop */)
2840 return 3; /* non-waiting control op */
2841 break;
2842 case 'r':
2843 if (mnemonic[2] == 's')
2844 return 3; /* frstor/frstpm */
2845 break;
2846 case 's':
2847 if (mnemonic[2] == 'a')
2848 return 3; /* fsave */
2849 if (mnemonic[2] == 't')
2850 {
2851 switch (mnemonic[3])
2852 {
2853 case 'c': /* fstcw */
2854 case 'd': /* fstdw */
2855 case 'e': /* fstenv */
2856 case 's': /* fsts[gw] */
2857 return 3;
2858 }
2859 }
2860 break;
2861 case 'x':
2862 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2863 return 0; /* fxsave/fxrstor are not really math ops */
2864 break;
2865 }
252b5132 2866
9306ca4a 2867 return 1;
252b5132
RH		 2868}
2869
c0f3af97
L		 2870/* Build the VEX prefix. */
2871
2872static void
d3ce72d0 2873build_vex_prefix (const insn_template *t)
c0f3af97
L		 2874{
2875 unsigned int register_specifier;
2876 unsigned int implied_prefix;
2877 unsigned int vector_length;
2878
2879 /* Check register specifier. */
2880 if (i.vex.register_specifier)
4c692bc7 2881 register_specifier = ~register_number (i.vex.register_specifier) & 0xf;
c0f3af97
L		 2882 else
2883 register_specifier = 0xf;
2884
fa99fab2
L		 2885 /* Use 2-byte VEX prefix by swappping destination and source
2886 operand. */
2887 if (!i.swap_operand
2888 && i.operands == i.reg_operands
7f399153 2889 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2890 && i.tm.opcode_modifier.s
2891 && i.rex == REX_B)
2892 {
2893 unsigned int xchg = i.operands - 1;
2894 union i386_op temp_op;
2895 i386_operand_type temp_type;
2896
2897 temp_type = i.types[xchg];
2898 i.types[xchg] = i.types[0];
2899 i.types[0] = temp_type;
2900 temp_op = i.op[xchg];
2901 i.op[xchg] = i.op[0];
2902 i.op[0] = temp_op;
2903
9c2799c2 2904 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2905
2906 i.rex = REX_R;
2907 xchg = i.rm.regmem;
2908 i.rm.regmem = i.rm.reg;
2909 i.rm.reg = xchg;
2910
2911 /* Use the next insn. */
2912 i.tm = t[1];
2913 }
2914
539f890d
L		 2915 if (i.tm.opcode_modifier.vex == VEXScalar)
2916 vector_length = avxscalar;
2917 else
2918 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2919
2920 switch ((i.tm.base_opcode >> 8) & 0xff)
2921 {
2922 case 0:
2923 implied_prefix = 0;
2924 break;
2925 case DATA_PREFIX_OPCODE:
2926 implied_prefix = 1;
2927 break;
2928 case REPE_PREFIX_OPCODE:
2929 implied_prefix = 2;
2930 break;
2931 case REPNE_PREFIX_OPCODE:
2932 implied_prefix = 3;
2933 break;
2934 default:
2935 abort ();
2936 }
2937
2938 /* Use 2-byte VEX prefix if possible. */
7f399153 2939 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2940 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2941 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2942 {
2943 /* 2-byte VEX prefix. */
2944 unsigned int r;
2945
2946 i.vex.length = 2;
2947 i.vex.bytes[0] = 0xc5;
2948
2949 /* Check the REX.R bit. */
2950 r = (i.rex & REX_R) ? 0 : 1;
2951 i.vex.bytes[1] = (r << 7
2952 | register_specifier << 3
2953 | vector_length << 2
2954 | implied_prefix);
2955 }
2956 else
2957 {
2958 /* 3-byte VEX prefix. */
2959 unsigned int m, w;
2960
f88c9eb0 2961 i.vex.length = 3;
f88c9eb0 2962
7f399153 2963 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2964 {
7f399153
L		 2965 case VEX0F:
2966 m = 0x1;
80de6e00 2967 i.vex.bytes[0] = 0xc4;
7f399153
L		 2968 break;
2969 case VEX0F38:
2970 m = 0x2;
80de6e00 2971 i.vex.bytes[0] = 0xc4;
7f399153
L		 2972 break;
2973 case VEX0F3A:
2974 m = 0x3;
80de6e00 2975 i.vex.bytes[0] = 0xc4;
7f399153
L		 2976 break;
2977 case XOP08:
5dd85c99
SP		 2978 m = 0x8;
2979 i.vex.bytes[0] = 0x8f;
7f399153
L		 2980 break;
2981 case XOP09:
f88c9eb0
SP		 2982 m = 0x9;
2983 i.vex.bytes[0] = 0x8f;
7f399153
L		 2984 break;
2985 case XOP0A:
f88c9eb0
SP		 2986 m = 0xa;
2987 i.vex.bytes[0] = 0x8f;
7f399153
L		 2988 break;
2989 default:
2990 abort ();
f88c9eb0 2991 }
c0f3af97 2992
c0f3af97
L		 2993 /* The high 3 bits of the second VEX byte are 1's compliment
2994 of RXB bits from REX. */
2995 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2996
2997 /* Check the REX.W bit. */
2998 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2999 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3000 {
3001 if (w)
3002 abort ();
3003
1ef99a7b 3004 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3005 w = 1;
3006 }
3007
3008 i.vex.bytes[2] = (w << 7
3009 | register_specifier << 3
3010 | vector_length << 2
3011 | implied_prefix);
3012 }
3013}
3014
65da13b5
L		 3015static void
3016process_immext (void)
3017{
3018 expressionS *exp;
3019
4c692bc7
JB		 3020 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3021 && i.operands > 0)
65da13b5 3022 {
4c692bc7
JB		 3023 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3024 with an opcode suffix which is coded in the same place as an
3025 8-bit immediate field would be.
3026 Here we check those operands and remove them afterwards. */
65da13b5
L		 3027 unsigned int x;
3028
3029 for (x = 0; x < i.operands; x++)
4c692bc7 3030 if (register_number (i.op[x].regs) != x)
65da13b5 3031 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3032 register_prefix, i.op[x].regs->reg_name, x + 1,
3033 i.tm.name);
3034
3035 i.operands = 0;
65da13b5
L		 3036 }
3037
c0f3af97 3038 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3039 which is coded in the same place as an 8-bit immediate field
3040 would be. Here we fake an 8-bit immediate operand from the
3041 opcode suffix stored in tm.extension_opcode.
3042
c1e679ec 3043 AVX instructions also use this encoding, for some of
c0f3af97 3044 3 argument instructions. */
65da13b5 3045
9c2799c2 3046 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 3047 && (i.operands <= 2
3048 || (i.tm.opcode_modifier.vex
3049 && i.operands <= 4)));
65da13b5
L		 3050
3051 exp = &im_expressions[i.imm_operands++];
3052 i.op[i.operands].imms = exp;
3053 i.types[i.operands] = imm8;
3054 i.operands++;
3055 exp->X_op = O_constant;
3056 exp->X_add_number = i.tm.extension_opcode;
3057 i.tm.extension_opcode = None;
3058}
3059
42164a71
L		 3060
3061static int
3062check_hle (void)
3063{
3064 switch (i.tm.opcode_modifier.hleprefixok)
3065 {
3066 default:
3067 abort ();
82c2def5 3068 case HLEPrefixNone:
42164a71
L		 3069 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3070 as_bad (_("invalid instruction `%s' after `xacquire'"),
3071 i.tm.name);
3072 else
3073 as_bad (_("invalid instruction `%s' after `xrelease'"),
3074 i.tm.name);
3075 return 0;
82c2def5 3076 case HLEPrefixLock:
42164a71
L		 3077 if (i.prefix[LOCK_PREFIX])
3078 return 1;
3079 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3080 as_bad (_("missing `lock' with `xacquire'"));
3081 else
3082 as_bad (_("missing `lock' with `xrelease'"));
3083 return 0;
82c2def5 3084 case HLEPrefixAny:
42164a71 3085 return 1;
82c2def5 3086 case HLEPrefixRelease:
42164a71
L		 3087 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3088 {
3089 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3090 i.tm.name);
3091 return 0;
3092 }
3093 if (i.mem_operands == 0
3094 || !operand_type_check (i.types[i.operands - 1], anymem))
3095 {
3096 as_bad (_("memory destination needed for instruction `%s'"
3097 " after `xrelease'"), i.tm.name);
3098 return 0;
3099 }
3100 return 1;
3101 }
3102}
3103
252b5132
RH		 3104/* This is the guts of the machine-dependent assembler. LINE points to a
3105 machine dependent instruction. This function is supposed to emit
3106 the frags/bytes it assembles to. */
3107
3108void
65da13b5 3109md_assemble (char *line)
252b5132 3110{
40fb9820 3111 unsigned int j;
252b5132 3112 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3113 const insn_template *t;
252b5132 3114
47926f60 3115 /* Initialize globals. */
252b5132
RH		 3116 memset (&i, '\0', sizeof (i));
3117 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3118 i.reloc[j] = NO_RELOC;
252b5132
RH		 3119 memset (disp_expressions, '\0', sizeof (disp_expressions));
3120 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3121 save_stack_p = save_stack;
252b5132
RH		 3122
3123 /* First parse an instruction mnemonic & call i386_operand for the operands.
3124 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3125 start of a (possibly prefixed) mnemonic. */
252b5132 3126
29b0f896
AM		 3127 line = parse_insn (line, mnemonic);
3128 if (line == NULL)
3129 return;
252b5132 3130
29b0f896 3131 line = parse_operands (line, mnemonic);
ee86248c 3132 this_operand = -1;
29b0f896
AM		 3133 if (line == NULL)
3134 return;
252b5132 3135
29b0f896
AM		 3136 /* Now we've parsed the mnemonic into a set of templates, and have the
3137 operands at hand. */
3138
3139 /* All intel opcodes have reversed operands except for "bound" and
3140 "enter". We also don't reverse intersegment "jmp" and "call"
3141 instructions with 2 immediate operands so that the immediate segment
050dfa73 3142 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3143 if (intel_syntax
3144 && i.operands > 1
29b0f896 3145 && (strcmp (mnemonic, "bound") != 0)
30123838 3146 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3147 && !(operand_type_check (i.types[0], imm)
3148 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3149 swap_operands ();
3150
ec56d5c0
JB		 3151 /* The order of the immediates should be reversed
3152 for 2 immediates extrq and insertq instructions */
3153 if (i.imm_operands == 2
3154 && (strcmp (mnemonic, "extrq") == 0
3155 || strcmp (mnemonic, "insertq") == 0))
3156 swap_2_operands (0, 1);
3157
29b0f896
AM		 3158 if (i.imm_operands)
3159 optimize_imm ();
3160
b300c311
L		 3161 /* Don't optimize displacement for movabs since it only takes 64bit
3162 displacement. */
3163 if (i.disp_operands
a501d77e 3164 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3165 && (flag_code != CODE_64BIT
3166 || strcmp (mnemonic, "movabs") != 0))
3167 optimize_disp ();
29b0f896
AM		 3168
3169 /* Next, we find a template that matches the given insn,
3170 making sure the overlap of the given operands types is consistent
3171 with the template operand types. */
252b5132 3172
fa99fab2 3173 if (!(t = match_template ()))
29b0f896 3174 return;
252b5132 3175
7bab8ab5 3176 if (sse_check != check_none
81f8a913 3177 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3178 && (i.tm.cpu_flags.bitfield.cpusse
3179 || i.tm.cpu_flags.bitfield.cpusse2
3180 || i.tm.cpu_flags.bitfield.cpusse3
3181 || i.tm.cpu_flags.bitfield.cpussse3
3182 || i.tm.cpu_flags.bitfield.cpusse4_1
3183 || i.tm.cpu_flags.bitfield.cpusse4_2))
3184 {
7bab8ab5 3185 (sse_check == check_warning
daf50ae7
L		 3186 ? as_warn
3187 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3188 }
3189
321fd21e
L		 3190 /* Zap movzx and movsx suffix. The suffix has been set from
3191 "word ptr" or "byte ptr" on the source operand in Intel syntax
3192 or extracted from mnemonic in AT&T syntax. But we'll use
3193 the destination register to choose the suffix for encoding. */
3194 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3195 {
321fd21e
L		 3196 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3197 there is no suffix, the default will be byte extension. */
3198 if (i.reg_operands != 2
3199 && !i.suffix
7ab9ffdd 3200 && intel_syntax)
321fd21e
L		 3201 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3202
3203 i.suffix = 0;
cd61ebfe 3204 }
24eab124 3205
40fb9820 3206 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3207 if (!add_prefix (FWAIT_OPCODE))
3208 return;
252b5132 3209
c1ba0266
L		 3210 /* Check for lock without a lockable instruction. Destination operand
3211 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3212 if (i.prefix[LOCK_PREFIX]
3213 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3214 || i.mem_operands == 0
3215 || (i.tm.base_opcode != 0x86
3216 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3217 {
3218 as_bad (_("expecting lockable instruction after `lock'"));
3219 return;
3220 }
3221
42164a71
L		 3222 /* Check if HLE prefix is OK. */
3223 if (i.have_hle && !check_hle ())
3224 return;
3225
29b0f896 3226 /* Check string instruction segment overrides. */
40fb9820 3227 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3228 {
3229 if (!check_string ())
5dd0794d 3230 return;
fc0763e6 3231 i.disp_operands = 0;
29b0f896 3232 }
5dd0794d 3233
29b0f896
AM		 3234 if (!process_suffix ())
3235 return;
e413e4e9 3236
bc0844ae
L		 3237 /* Update operand types. */
3238 for (j = 0; j < i.operands; j++)
3239 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3240
29b0f896
AM		 3241 /* Make still unresolved immediate matches conform to size of immediate
3242 given in i.suffix. */
3243 if (!finalize_imm ())
3244 return;
252b5132 3245
40fb9820 3246 if (i.types[0].bitfield.imm1)
29b0f896 3247 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3248
9afe6eb8
L		 3249 /* We only need to check those implicit registers for instructions
3250 with 3 operands or less. */
3251 if (i.operands <= 3)
3252 for (j = 0; j < i.operands; j++)
3253 if (i.types[j].bitfield.inoutportreg
3254 || i.types[j].bitfield.shiftcount
3255 || i.types[j].bitfield.acc
3256 || i.types[j].bitfield.floatacc)
3257 i.reg_operands--;
40fb9820 3258
c0f3af97
L		 3259 /* ImmExt should be processed after SSE2AVX. */
3260 if (!i.tm.opcode_modifier.sse2avx
3261 && i.tm.opcode_modifier.immext)
65da13b5 3262 process_immext ();
252b5132 3263
29b0f896
AM		 3264 /* For insns with operands there are more diddles to do to the opcode. */
3265 if (i.operands)
3266 {
3267 if (!process_operands ())
3268 return;
3269 }
40fb9820 3270 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3271 {
3272 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3273 as_warn (_("translating to `%sp'"), i.tm.name);
3274 }
252b5132 3275
c0f3af97 3276 if (i.tm.opcode_modifier.vex)
fa99fab2 3277 build_vex_prefix (t);
c0f3af97 3278
5dd85c99
SP		 3279 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3280 instructions may define INT_OPCODE as well, so avoid this corner
3281 case for those instructions that use MODRM. */
3282 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3283 && !i.tm.opcode_modifier.modrm
3284 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3285 {
3286 i.tm.base_opcode = INT3_OPCODE;
3287 i.imm_operands = 0;
3288 }
252b5132 3289
40fb9820
L		 3290 if ((i.tm.opcode_modifier.jump
3291 || i.tm.opcode_modifier.jumpbyte
3292 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3293 && i.op[0].disps->X_op == O_constant)
3294 {
3295 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3296 the absolute address given by the constant. Since ix86 jumps and
3297 calls are pc relative, we need to generate a reloc. */
3298 i.op[0].disps->X_add_symbol = &abs_symbol;
3299 i.op[0].disps->X_op = O_symbol;
3300 }
252b5132 3301
40fb9820 3302 if (i.tm.opcode_modifier.rex64)
161a04f6 3303 i.rex |= REX_W;
252b5132 3304
29b0f896
AM		 3305 /* For 8 bit registers we need an empty rex prefix. Also if the
3306 instruction already has a prefix, we need to convert old
3307 registers to new ones. */
773f551c 3308
40fb9820 3309 if ((i.types[0].bitfield.reg8
29b0f896 3310 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3311 || (i.types[1].bitfield.reg8
29b0f896 3312 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3313 || ((i.types[0].bitfield.reg8
3314 || i.types[1].bitfield.reg8)
29b0f896
AM		 3315 && i.rex != 0))
3316 {
3317 int x;
726c5dcd 3318
29b0f896
AM		 3319 i.rex |= REX_OPCODE;
3320 for (x = 0; x < 2; x++)
3321 {
3322 /* Look for 8 bit operand that uses old registers. */
40fb9820 3323 if (i.types[x].bitfield.reg8
29b0f896 3324 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3325 {
29b0f896
AM		 3326 /* In case it is "hi" register, give up. */
3327 if (i.op[x].regs->reg_num > 3)
a540244d 3328 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3329 "instruction requiring REX prefix."),
a540244d 3330 register_prefix, i.op[x].regs->reg_name);
773f551c 3331
29b0f896
AM		 3332 /* Otherwise it is equivalent to the extended register.
3333 Since the encoding doesn't change this is merely
3334 cosmetic cleanup for debug output. */
3335
3336 i.op[x].regs = i.op[x].regs + 8;
773f551c 3337 }
29b0f896
AM		 3338 }
3339 }
773f551c 3340
7ab9ffdd 3341 if (i.rex != 0)
29b0f896
AM		 3342 add_prefix (REX_OPCODE | i.rex);
3343
3344 /* We are ready to output the insn. */
3345 output_insn ();
3346}
3347
3348static char *
e3bb37b5 3349parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3350{
3351 char *l = line;
3352 char *token_start = l;
3353 char *mnem_p;
5c6af06e 3354 int supported;
d3ce72d0 3355 const insn_template *t;
b6169b20 3356 char *dot_p = NULL;
29b0f896
AM		 3357
3358 /* Non-zero if we found a prefix only acceptable with string insns. */
3359 const char *expecting_string_instruction = NULL;
45288df1 3360
29b0f896
AM		 3361 while (1)
3362 {
3363 mnem_p = mnemonic;
3364 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3365 {
b6169b20
L		 3366 if (*mnem_p == '.')
3367 dot_p = mnem_p;
29b0f896
AM		 3368 mnem_p++;
3369 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3370 {
29b0f896
AM		 3371 as_bad (_("no such instruction: `%s'"), token_start);
3372 return NULL;
3373 }
3374 l++;
3375 }
3376 if (!is_space_char (*l)
3377 && *l != END_OF_INSN
e44823cf
JB		 3378 && (intel_syntax
3379 || (*l != PREFIX_SEPARATOR
3380 && *l != ',')))
29b0f896
AM		 3381 {
3382 as_bad (_("invalid character %s in mnemonic"),
3383 output_invalid (*l));
3384 return NULL;
3385 }
3386 if (token_start == l)
3387 {
e44823cf 3388 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3389 as_bad (_("expecting prefix; got nothing"));
3390 else
3391 as_bad (_("expecting mnemonic; got nothing"));
3392 return NULL;
3393 }
45288df1 3394
29b0f896 3395 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3396 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3397
29b0f896
AM		 3398 if (*l != END_OF_INSN
3399 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3400 && current_templates
40fb9820 3401 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3402 {
c6fb90c8 3403 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3404 {
3405 as_bad ((flag_code != CODE_64BIT
3406 ? _("`%s' is only supported in 64-bit mode")
3407 : _("`%s' is not supported in 64-bit mode")),
3408 current_templates->start->name);
3409 return NULL;
3410 }
29b0f896
AM		 3411 /* If we are in 16-bit mode, do not allow addr16 or data16.
3412 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3413 if ((current_templates->start->opcode_modifier.size16
3414 || current_templates->start->opcode_modifier.size32)
29b0f896 3415 && flag_code != CODE_64BIT
40fb9820 3416 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3417 ^ (flag_code == CODE_16BIT)))
3418 {
3419 as_bad (_("redundant %s prefix"),
3420 current_templates->start->name);
3421 return NULL;
45288df1 3422 }
29b0f896
AM		 3423 /* Add prefix, checking for repeated prefixes. */
3424 switch (add_prefix (current_templates->start->base_opcode))
3425 {
c32fa91d 3426 case PREFIX_EXIST:
29b0f896 3427 return NULL;
c32fa91d 3428 case PREFIX_REP:
42164a71
L		 3429 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3430 i.have_hle = 1;
3431 else
3432 expecting_string_instruction = current_templates->start->name;
29b0f896 3433 break;
c32fa91d
L		 3434 default:
3435 break;
29b0f896
AM		 3436 }
3437 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3438 token_start = ++l;
3439 }
3440 else
3441 break;
3442 }
45288df1 3443
30a55f88 3444 if (!current_templates)
b6169b20 3445 {
f8a5c266
L		 3446 /* Check if we should swap operand or force 32bit displacement in
3447 encoding. */
30a55f88
L		 3448 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3449 i.swap_operand = 1;
8d63c93e 3450 else if (mnem_p - 3 == dot_p
a501d77e
L		 3451 && dot_p[1] == 'd'
3452 && dot_p[2] == '8')
3453 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3454 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3455 && dot_p[1] == 'd'
3456 && dot_p[2] == '3'
3457 && dot_p[3] == '2')
a501d77e 3458 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3459 else
3460 goto check_suffix;
3461 mnem_p = dot_p;
3462 *dot_p = '\0';
d3ce72d0 3463 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3464 }
3465
29b0f896
AM		 3466 if (!current_templates)
3467 {
b6169b20 3468check_suffix:
29b0f896
AM		 3469 /* See if we can get a match by trimming off a suffix. */
3470 switch (mnem_p[-1])
3471 {
3472 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3473 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3474 i.suffix = SHORT_MNEM_SUFFIX;
3475 else
29b0f896
AM		 3476 case BYTE_MNEM_SUFFIX:
3477 case QWORD_MNEM_SUFFIX:
3478 i.suffix = mnem_p[-1];
3479 mnem_p[-1] = '\0';
d3ce72d0
NC		 3480 current_templates = (const templates *) hash_find (op_hash,
3481 mnemonic);
29b0f896
AM		 3482 break;
3483 case SHORT_MNEM_SUFFIX:
3484 case LONG_MNEM_SUFFIX:
3485 if (!intel_syntax)
3486 {
3487 i.suffix = mnem_p[-1];
3488 mnem_p[-1] = '\0';
d3ce72d0
NC		 3489 current_templates = (const templates *) hash_find (op_hash,
3490 mnemonic);
29b0f896
AM		 3491 }
3492 break;
252b5132 3493
29b0f896
AM		 3494 /* Intel Syntax. */
3495 case 'd':
3496 if (intel_syntax)
3497 {
9306ca4a 3498 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3499 i.suffix = SHORT_MNEM_SUFFIX;
3500 else
3501 i.suffix = LONG_MNEM_SUFFIX;
3502 mnem_p[-1] = '\0';
d3ce72d0
NC		 3503 current_templates = (const templates *) hash_find (op_hash,
3504 mnemonic);
29b0f896
AM		 3505 }
3506 break;
3507 }
3508 if (!current_templates)
3509 {
3510 as_bad (_("no such instruction: `%s'"), token_start);
3511 return NULL;
3512 }
3513 }
252b5132 3514
40fb9820
L		 3515 if (current_templates->start->opcode_modifier.jump
3516 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3517 {
3518 /* Check for a branch hint. We allow ",pt" and ",pn" for
3519 predict taken and predict not taken respectively.
3520 I'm not sure that branch hints actually do anything on loop
3521 and jcxz insns (JumpByte) for current Pentium4 chips. They
3522 may work in the future and it doesn't hurt to accept them
3523 now. */
3524 if (l[0] == ',' && l[1] == 'p')
3525 {
3526 if (l[2] == 't')
3527 {
3528 if (!add_prefix (DS_PREFIX_OPCODE))
3529 return NULL;
3530 l += 3;
3531 }
3532 else if (l[2] == 'n')
3533 {
3534 if (!add_prefix (CS_PREFIX_OPCODE))
3535 return NULL;
3536 l += 3;
3537 }
3538 }
3539 }
3540 /* Any other comma loses. */
3541 if (*l == ',')
3542 {
3543 as_bad (_("invalid character %s in mnemonic"),
3544 output_invalid (*l));
3545 return NULL;
3546 }
252b5132 3547
29b0f896 3548 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3549 supported = 0;
3550 for (t = current_templates->start; t < current_templates->end; ++t)
3551 {
c0f3af97
L		 3552 supported |= cpu_flags_match (t);
3553 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3554 goto skip;
5c6af06e 3555 }
3629bb00 3556
c0f3af97 3557 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3558 {
3559 as_bad (flag_code == CODE_64BIT
3560 ? _("`%s' is not supported in 64-bit mode")
3561 : _("`%s' is only supported in 64-bit mode"),
3562 current_templates->start->name);
3563 return NULL;
3564 }
c0f3af97 3565 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3566 {
3629bb00 3567 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3568 current_templates->start->name,
41aacd83 3569 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3570 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3571 return NULL;
29b0f896 3572 }
3629bb00
L		 3573
3574skip:
3575 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3576 && (flag_code != CODE_16BIT))
29b0f896
AM		 3577 {
3578 as_warn (_("use .code16 to ensure correct addressing mode"));
3579 }
252b5132 3580
29c048b6 3581 /* Check for rep/repne without a string (or other allowed) instruction. */
f41bbced 3582 if (expecting_string_instruction)
29b0f896 3583 {
f41bbced
JB		 3584 static templates override;
3585
3586 for (t = current_templates->start; t < current_templates->end; ++t)
29c048b6 3587 if (t->opcode_modifier.repprefixok)
f41bbced
JB		 3588 break;
3589 if (t >= current_templates->end)
3590 {
3591 as_bad (_("expecting string instruction after `%s'"),
64e74474 3592 expecting_string_instruction);
f41bbced
JB		 3593 return NULL;
3594 }
3595 for (override.start = t; t < current_templates->end; ++t)
29c048b6 3596 if (!t->opcode_modifier.repprefixok)
f41bbced
JB		 3597 break;
3598 override.end = t;
3599 current_templates = &override;
29b0f896 3600 }
252b5132 3601
29b0f896
AM		 3602 return l;
3603}
252b5132 3604
29b0f896 3605static char *
e3bb37b5 3606parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3607{
3608 char *token_start;
3138f287 3609
29b0f896
AM		 3610 /* 1 if operand is pending after ','. */
3611 unsigned int expecting_operand = 0;
252b5132 3612
29b0f896
AM		 3613 /* Non-zero if operand parens not balanced. */
3614 unsigned int paren_not_balanced;
3615
3616 while (*l != END_OF_INSN)
3617 {
3618 /* Skip optional white space before operand. */
3619 if (is_space_char (*l))
3620 ++l;
3621 if (!is_operand_char (*l) && *l != END_OF_INSN)
3622 {
3623 as_bad (_("invalid character %s before operand %d"),
3624 output_invalid (*l),
3625 i.operands + 1);
3626 return NULL;
3627 }
3628 token_start = l; /* after white space */
3629 paren_not_balanced = 0;
3630 while (paren_not_balanced || *l != ',')
3631 {
3632 if (*l == END_OF_INSN)
3633 {
3634 if (paren_not_balanced)
3635 {
3636 if (!intel_syntax)
3637 as_bad (_("unbalanced parenthesis in operand %d."),
3638 i.operands + 1);
3639 else
3640 as_bad (_("unbalanced brackets in operand %d."),
3641 i.operands + 1);
3642 return NULL;
3643 }
3644 else
3645 break; /* we are done */
3646 }
3647 else if (!is_operand_char (*l) && !is_space_char (*l))
3648 {
3649 as_bad (_("invalid character %s in operand %d"),
3650 output_invalid (*l),
3651 i.operands + 1);
3652 return NULL;
3653 }
3654 if (!intel_syntax)
3655 {
3656 if (*l == '(')
3657 ++paren_not_balanced;
3658 if (*l == ')')
3659 --paren_not_balanced;
3660 }
3661 else
3662 {
3663 if (*l == '[')
3664 ++paren_not_balanced;
3665 if (*l == ']')
3666 --paren_not_balanced;
3667 }
3668 l++;
3669 }
3670 if (l != token_start)
3671 { /* Yes, we've read in another operand. */
3672 unsigned int operand_ok;
3673 this_operand = i.operands++;
7d5e4556 3674 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3675 if (i.operands > MAX_OPERANDS)
3676 {
3677 as_bad (_("spurious operands; (%d operands/instruction max)"),
3678 MAX_OPERANDS);
3679 return NULL;
3680 }
3681 /* Now parse operand adding info to 'i' as we go along. */
3682 END_STRING_AND_SAVE (l);
3683
3684 if (intel_syntax)
3685 operand_ok =
3686 i386_intel_operand (token_start,
3687 intel_float_operand (mnemonic));
3688 else
a7619375 3689 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3690
3691 RESTORE_END_STRING (l);
3692 if (!operand_ok)
3693 return NULL;
3694 }
3695 else
3696 {
3697 if (expecting_operand)
3698 {
3699 expecting_operand_after_comma:
3700 as_bad (_("expecting operand after ','; got nothing"));
3701 return NULL;
3702 }
3703 if (*l == ',')
3704 {
3705 as_bad (_("expecting operand before ','; got nothing"));
3706 return NULL;
3707 }
3708 }
7f3f1ea2 3709
29b0f896
AM		 3710 /* Now *l must be either ',' or END_OF_INSN. */
3711 if (*l == ',')
3712 {
3713 if (*++l == END_OF_INSN)
3714 {
3715 /* Just skip it, if it's \n complain. */
3716 goto expecting_operand_after_comma;
3717 }
3718 expecting_operand = 1;
3719 }
3720 }
3721 return l;
3722}
7f3f1ea2 3723
050dfa73 3724static void
4d456e3d 3725swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3726{
3727 union i386_op temp_op;
40fb9820 3728 i386_operand_type temp_type;
050dfa73 3729 enum bfd_reloc_code_real temp_reloc;
4eed87de 3730
050dfa73
MM		 3731 temp_type = i.types[xchg2];
3732 i.types[xchg2] = i.types[xchg1];
3733 i.types[xchg1] = temp_type;
3734 temp_op = i.op[xchg2];
3735 i.op[xchg2] = i.op[xchg1];
3736 i.op[xchg1] = temp_op;
3737 temp_reloc = i.reloc[xchg2];
3738 i.reloc[xchg2] = i.reloc[xchg1];
3739 i.reloc[xchg1] = temp_reloc;
3740}
3741
29b0f896 3742static void
e3bb37b5 3743swap_operands (void)
29b0f896 3744{
b7c61d9a 3745 switch (i.operands)
050dfa73 3746 {
c0f3af97 3747 case 5:
b7c61d9a 3748 case 4:
4d456e3d 3749 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3750 case 3:
3751 case 2:
4d456e3d 3752 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3753 break;
3754 default:
3755 abort ();
29b0f896 3756 }
29b0f896
AM		 3757
3758 if (i.mem_operands == 2)
3759 {
3760 const seg_entry *temp_seg;
3761 temp_seg = i.seg[0];
3762 i.seg[0] = i.seg[1];
3763 i.seg[1] = temp_seg;
3764 }
3765}
252b5132 3766
29b0f896
AM		 3767/* Try to ensure constant immediates are represented in the smallest
3768 opcode possible. */
3769static void
e3bb37b5 3770optimize_imm (void)
29b0f896
AM		 3771{
3772 char guess_suffix = 0;
3773 int op;
252b5132 3774
29b0f896
AM		 3775 if (i.suffix)
3776 guess_suffix = i.suffix;
3777 else if (i.reg_operands)
3778 {
3779 /* Figure out a suffix from the last register operand specified.
3780 We can't do this properly yet, ie. excluding InOutPortReg,
3781 but the following works for instructions with immediates.
3782 In any case, we can't set i.suffix yet. */
3783 for (op = i.operands; --op >= 0;)
40fb9820 3784 if (i.types[op].bitfield.reg8)
7ab9ffdd 3785 {
40fb9820
L		 3786 guess_suffix = BYTE_MNEM_SUFFIX;
3787 break;
3788 }
3789 else if (i.types[op].bitfield.reg16)
252b5132 3790 {
40fb9820
L		 3791 guess_suffix = WORD_MNEM_SUFFIX;
3792 break;
3793 }
3794 else if (i.types[op].bitfield.reg32)
3795 {
3796 guess_suffix = LONG_MNEM_SUFFIX;
3797 break;
3798 }
3799 else if (i.types[op].bitfield.reg64)
3800 {
3801 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3802 break;
252b5132 3803 }
29b0f896
AM		 3804 }
3805 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3806 guess_suffix = WORD_MNEM_SUFFIX;
3807
3808 for (op = i.operands; --op >= 0;)
40fb9820 3809 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3810 {
3811 switch (i.op[op].imms->X_op)
252b5132 3812 {
29b0f896
AM		 3813 case O_constant:
3814 /* If a suffix is given, this operand may be shortened. */
3815 switch (guess_suffix)
252b5132 3816 {
29b0f896 3817 case LONG_MNEM_SUFFIX:
40fb9820
L		 3818 i.types[op].bitfield.imm32 = 1;
3819 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3820 break;
3821 case WORD_MNEM_SUFFIX:
40fb9820
L		 3822 i.types[op].bitfield.imm16 = 1;
3823 i.types[op].bitfield.imm32 = 1;
3824 i.types[op].bitfield.imm32s = 1;
3825 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3826 break;
3827 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3828 i.types[op].bitfield.imm8 = 1;
3829 i.types[op].bitfield.imm8s = 1;
3830 i.types[op].bitfield.imm16 = 1;
3831 i.types[op].bitfield.imm32 = 1;
3832 i.types[op].bitfield.imm32s = 1;
3833 i.types[op].bitfield.imm64 = 1;
29b0f896 3834 break;
252b5132 3835 }
252b5132 3836
29b0f896
AM		 3837 /* If this operand is at most 16 bits, convert it
3838 to a signed 16 bit number before trying to see
3839 whether it will fit in an even smaller size.
3840 This allows a 16-bit operand such as $0xffe0 to
3841 be recognised as within Imm8S range. */
40fb9820 3842 if ((i.types[op].bitfield.imm16)
29b0f896 3843 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3844 {
29b0f896
AM		 3845 i.op[op].imms->X_add_number =
3846 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3847 }
40fb9820 3848 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3849 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3850 == 0))
3851 {
3852 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3853 ^ ((offsetT) 1 << 31))
3854 - ((offsetT) 1 << 31));
3855 }
40fb9820 3856 i.types[op]
c6fb90c8
L		 3857 = operand_type_or (i.types[op],
3858 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3859
29b0f896
AM		 3860 /* We must avoid matching of Imm32 templates when 64bit
3861 only immediate is available. */
3862 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3863 i.types[op].bitfield.imm32 = 0;
29b0f896 3864 break;
252b5132 3865
29b0f896
AM		 3866 case O_absent:
3867 case O_register:
3868 abort ();
3869
3870 /* Symbols and expressions. */
3871 default:
9cd96992
JB		 3872 /* Convert symbolic operand to proper sizes for matching, but don't
3873 prevent matching a set of insns that only supports sizes other
3874 than those matching the insn suffix. */
3875 {
40fb9820 3876 i386_operand_type mask, allowed;
d3ce72d0 3877 const insn_template *t;
9cd96992 3878
0dfbf9d7
L		 3879 operand_type_set (&mask, 0);
3880 operand_type_set (&allowed, 0);
40fb9820 3881
4eed87de
AM		 3882 for (t = current_templates->start;
3883 t < current_templates->end;
3884 ++t)
c6fb90c8
L		 3885 allowed = operand_type_or (allowed,
3886 t->operand_types[op]);
9cd96992
JB		 3887 switch (guess_suffix)
3888 {
3889 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3890 mask.bitfield.imm64 = 1;
3891 mask.bitfield.imm32s = 1;
9cd96992
JB		 3892 break;
3893 case LONG_MNEM_SUFFIX:
40fb9820 3894 mask.bitfield.imm32 = 1;
9cd96992
JB		 3895 break;
3896 case WORD_MNEM_SUFFIX:
40fb9820 3897 mask.bitfield.imm16 = 1;
9cd96992
JB		 3898 break;
3899 case BYTE_MNEM_SUFFIX:
40fb9820 3900 mask.bitfield.imm8 = 1;
9cd96992
JB		 3901 break;
3902 default:
9cd96992
JB		 3903 break;
3904 }
c6fb90c8 3905 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3906 if (!operand_type_all_zero (&allowed))
c6fb90c8 3907 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3908 }
29b0f896 3909 break;
252b5132 3910 }
29b0f896
AM		 3911 }
3912}
47926f60 3913
29b0f896
AM		 3914/* Try to use the smallest displacement type too. */
3915static void
e3bb37b5 3916optimize_disp (void)
29b0f896
AM		 3917{
3918 int op;
3e73aa7c 3919
29b0f896 3920 for (op = i.operands; --op >= 0;)
40fb9820 3921 if (operand_type_check (i.types[op], disp))
252b5132 3922 {
b300c311 3923 if (i.op[op].disps->X_op == O_constant)
252b5132 3924 {
91d6fa6a 3925 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3926
40fb9820 3927 if (i.types[op].bitfield.disp16
91d6fa6a 3928 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3929 {
3930 /* If this operand is at most 16 bits, convert
3931 to a signed 16 bit number and don't use 64bit
3932 displacement. */
91d6fa6a 3933 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3934 i.types[op].bitfield.disp64 = 0;
b300c311 3935 }
40fb9820 3936 if (i.types[op].bitfield.disp32
91d6fa6a 3937 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3938 {
3939 /* If this operand is at most 32 bits, convert
3940 to a signed 32 bit number and don't use 64bit
3941 displacement. */
91d6fa6a
NC		 3942 op_disp &= (((offsetT) 2 << 31) - 1);
3943 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3944 i.types[op].bitfield.disp64 = 0;
b300c311 3945 }
91d6fa6a 3946 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3947 {
40fb9820
L		 3948 i.types[op].bitfield.disp8 = 0;
3949 i.types[op].bitfield.disp16 = 0;
3950 i.types[op].bitfield.disp32 = 0;
3951 i.types[op].bitfield.disp32s = 0;
3952 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3953 i.op[op].disps = 0;
3954 i.disp_operands--;
3955 }
3956 else if (flag_code == CODE_64BIT)
3957 {
91d6fa6a 3958 if (fits_in_signed_long (op_disp))
28a9d8f5 3959 {
40fb9820
L		 3960 i.types[op].bitfield.disp64 = 0;
3961 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3962 }
0e1147d9 3963 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3964 && fits_in_unsigned_long (op_disp))
40fb9820 3965 i.types[op].bitfield.disp32 = 1;
b300c311 3966 }
40fb9820
L		 3967 if ((i.types[op].bitfield.disp32
3968 || i.types[op].bitfield.disp32s
3969 || i.types[op].bitfield.disp16)
91d6fa6a 3970 && fits_in_signed_byte (op_disp))
40fb9820 3971 i.types[op].bitfield.disp8 = 1;
252b5132 3972 }
67a4f2b7
AO		 3973 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3974 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3975 {
3976 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3977 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3978 i.types[op].bitfield.disp8 = 0;
3979 i.types[op].bitfield.disp16 = 0;
3980 i.types[op].bitfield.disp32 = 0;
3981 i.types[op].bitfield.disp32s = 0;
3982 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3983 }
3984 else
b300c311 3985 /* We only support 64bit displacement on constants. */
40fb9820 3986 i.types[op].bitfield.disp64 = 0;
252b5132 3987 }
29b0f896
AM		 3988}
3989
6c30d220
L		 3990/* Check if operands are valid for the instruction. */
3991
3992static int
3993check_VecOperands (const insn_template *t)
3994{
3995 /* Without VSIB byte, we can't have a vector register for index. */
3996 if (!t->opcode_modifier.vecsib
3997 && i.index_reg
3998 && (i.index_reg->reg_type.bitfield.regxmm
3999 || i.index_reg->reg_type.bitfield.regymm))
4000 {
4001 i.error = unsupported_vector_index_register;
4002 return 1;
4003 }
4004
7bab8ab5
JB		 4005 /* For VSIB byte, we need a vector register for index, and all vector
4006 registers must be distinct. */
4007 if (t->opcode_modifier.vecsib)
4008 {
4009 if (!i.index_reg
6c30d220
L		 4010 || !((t->opcode_modifier.vecsib == VecSIB128
4011 && i.index_reg->reg_type.bitfield.regxmm)
4012 || (t->opcode_modifier.vecsib == VecSIB256
7bab8ab5
JB		 4013 && i.index_reg->reg_type.bitfield.regymm)))
4014 {
4015 i.error = invalid_vsib_address;
4016 return 1;
4017 }
4018
4019 gas_assert (i.reg_operands == 2);
4020 gas_assert (i.types[0].bitfield.regxmm
4021 || i.types[0].bitfield.regymm);
4022 gas_assert (i.types[2].bitfield.regxmm
4023 || i.types[2].bitfield.regymm);
4024
4025 if (operand_check == check_none)
4026 return 0;
4027 if (register_number (i.op[0].regs) != register_number (i.index_reg)
4028 && register_number (i.op[2].regs) != register_number (i.index_reg)
4029 && register_number (i.op[0].regs) != register_number (i.op[2].regs))
4030 return 0;
4031 if (operand_check == check_error)
4032 {
4033 i.error = invalid_vector_register_set;
4034 return 1;
4035 }
4036 as_warn (_("mask, index, and destination registers should be distinct"));
6c30d220
L		 4037 }
4038
4039 return 0;
4040}
4041
43f3e2ee 4042/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4043 operand types. */
4044
4045static int
4046VEX_check_operands (const insn_template *t)
4047{
4048 if (!t->opcode_modifier.vex)
4049 return 0;
4050
4051 /* Only check VEX_Imm4, which must be the first operand. */
4052 if (t->operand_types[0].bitfield.vec_imm4)
4053 {
4054 if (i.op[0].imms->X_op != O_constant
4055 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4056 {
a65babc9 4057 i.error = bad_imm4;
891edac4
L		 4058 return 1;
4059 }
a683cc34
SP		 4060
4061 /* Turn off Imm8 so that update_imm won't complain. */
4062 i.types[0] = vec_imm4;
4063 }
4064
4065 return 0;
4066}
4067
d3ce72d0 4068static const insn_template *
e3bb37b5 4069match_template (void)
29b0f896
AM		 4070{
4071 /* Points to template once we've found it. */
d3ce72d0 4072 const insn_template *t;
40fb9820 4073 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4074 i386_operand_type overlap4;
29b0f896 4075 unsigned int found_reverse_match;
40fb9820
L		 4076 i386_opcode_modifier suffix_check;
4077 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4078 int addr_prefix_disp;
a5c311ca 4079 unsigned int j;
3629bb00 4080 unsigned int found_cpu_match;
45664ddb 4081 unsigned int check_register;
5614d22c 4082 enum i386_error specific_error = 0;
29b0f896 4083
c0f3af97
L		 4084#if MAX_OPERANDS != 5
4085# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4086#endif
4087
29b0f896 4088 found_reverse_match = 0;
539e75ad 4089 addr_prefix_disp = -1;
40fb9820
L		 4090
4091 memset (&suffix_check, 0, sizeof (suffix_check));
4092 if (i.suffix == BYTE_MNEM_SUFFIX)
4093 suffix_check.no_bsuf = 1;
4094 else if (i.suffix == WORD_MNEM_SUFFIX)
4095 suffix_check.no_wsuf = 1;
4096 else if (i.suffix == SHORT_MNEM_SUFFIX)
4097 suffix_check.no_ssuf = 1;
4098 else if (i.suffix == LONG_MNEM_SUFFIX)
4099 suffix_check.no_lsuf = 1;
4100 else if (i.suffix == QWORD_MNEM_SUFFIX)
4101 suffix_check.no_qsuf = 1;
4102 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4103 suffix_check.no_ldsuf = 1;
29b0f896 4104
01559ecc
L		 4105 /* Must have right number of operands. */
4106 i.error = number_of_operands_mismatch;
4107
45aa61fe 4108 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4109 {
539e75ad
L		 4110 addr_prefix_disp = -1;
4111
29b0f896
AM		 4112 if (i.operands != t->operands)
4113 continue;
4114
50aecf8c 4115 /* Check processor support. */
a65babc9 4116 i.error = unsupported;
c0f3af97
L		 4117 found_cpu_match = (cpu_flags_match (t)
4118 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4119 if (!found_cpu_match)
4120 continue;
4121
e1d4d893 4122 /* Check old gcc support. */
a65babc9 4123 i.error = old_gcc_only;
e1d4d893
L		 4124 if (!old_gcc && t->opcode_modifier.oldgcc)
4125 continue;
4126
4127 /* Check AT&T mnemonic. */
a65babc9 4128 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4129 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4130 continue;
4131
891edac4 4132 /* Check AT&T/Intel syntax. */
a65babc9 4133 i.error = unsupported_syntax;
5c07affc
L		 4134 if ((intel_syntax && t->opcode_modifier.attsyntax)
4135 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4136 continue;
4137
20592a94 4138 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4139 i.error = invalid_instruction_suffix;
567e4e96
L		 4140 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4141 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4142 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4143 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4144 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4145 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4146 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4147 continue;
4148
5c07affc 4149 if (!operand_size_match (t))
7d5e4556 4150 continue;
539e75ad 4151
5c07affc
L		 4152 for (j = 0; j < MAX_OPERANDS; j++)
4153 operand_types[j] = t->operand_types[j];
4154
45aa61fe
AM		 4155 /* In general, don't allow 64-bit operands in 32-bit mode. */
4156 if (i.suffix == QWORD_MNEM_SUFFIX
4157 && flag_code != CODE_64BIT
4158 && (intel_syntax
40fb9820 4159 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4160 && !intel_float_operand (t->name))
4161 : intel_float_operand (t->name) != 2)
40fb9820 4162 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4163 && !operand_types[0].bitfield.regxmm
4164 && !operand_types[0].bitfield.regymm)
40fb9820 4165 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4166 && !!operand_types[t->operands > 1].bitfield.regxmm
4167 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4168 && (t->base_opcode != 0x0fc7
4169 || t->extension_opcode != 1 /* cmpxchg8b */))
4170 continue;
4171
192dc9c6
JB		 4172 /* In general, don't allow 32-bit operands on pre-386. */
4173 else if (i.suffix == LONG_MNEM_SUFFIX
4174 && !cpu_arch_flags.bitfield.cpui386
4175 && (intel_syntax
4176 ? (!t->opcode_modifier.ignoresize
4177 && !intel_float_operand (t->name))
4178 : intel_float_operand (t->name) != 2)
4179 && ((!operand_types[0].bitfield.regmmx
4180 && !operand_types[0].bitfield.regxmm)
4181 || (!operand_types[t->operands > 1].bitfield.regmmx
4182 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4183 continue;
4184
29b0f896 4185 /* Do not verify operands when there are none. */
50aecf8c 4186 else
29b0f896 4187 {
c6fb90c8 4188 if (!t->operands)
2dbab7d5
L		 4189 /* We've found a match; break out of loop. */
4190 break;
29b0f896 4191 }
252b5132 4192
539e75ad
L		 4193 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4194 into Disp32/Disp16/Disp32 operand. */
4195 if (i.prefix[ADDR_PREFIX] != 0)
4196 {
40fb9820 4197 /* There should be only one Disp operand. */
539e75ad
L		 4198 switch (flag_code)
4199 {
4200 case CODE_16BIT:
40fb9820
L		 4201 for (j = 0; j < MAX_OPERANDS; j++)
4202 {
4203 if (operand_types[j].bitfield.disp16)
4204 {
4205 addr_prefix_disp = j;
4206 operand_types[j].bitfield.disp32 = 1;
4207 operand_types[j].bitfield.disp16 = 0;
4208 break;
4209 }
4210 }
539e75ad
L		 4211 break;
4212 case CODE_32BIT:
40fb9820
L		 4213 for (j = 0; j < MAX_OPERANDS; j++)
4214 {
4215 if (operand_types[j].bitfield.disp32)
4216 {
4217 addr_prefix_disp = j;
4218 operand_types[j].bitfield.disp32 = 0;
4219 operand_types[j].bitfield.disp16 = 1;
4220 break;
4221 }
4222 }
539e75ad
L		 4223 break;
4224 case CODE_64BIT:
40fb9820
L		 4225 for (j = 0; j < MAX_OPERANDS; j++)
4226 {
4227 if (operand_types[j].bitfield.disp64)
4228 {
4229 addr_prefix_disp = j;
4230 operand_types[j].bitfield.disp64 = 0;
4231 operand_types[j].bitfield.disp32 = 1;
4232 break;
4233 }
4234 }
539e75ad
L		 4235 break;
4236 }
539e75ad
L		 4237 }
4238
56ffb741
L		 4239 /* We check register size if needed. */
4240 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4241 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4242 switch (t->operands)
4243 {
4244 case 1:
40fb9820 4245 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4246 continue;
4247 break;
4248 case 2:
8b38ad71
L		 4249 /* xchg %eax, %eax is a special case. It is an aliase for nop
4250 only in 32bit mode and we can use opcode 0x90. In 64bit
4251 mode, we can't use 0x90 for xchg %eax, %eax since it should
4252 zero-extend %eax to %rax. */
4253 if (flag_code == CODE_64BIT
4254 && t->base_opcode == 0x90
0dfbf9d7
L		 4255 && operand_type_equal (&i.types [0], &acc32)
4256 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4257 continue;
b6169b20
L		 4258 if (i.swap_operand)
4259 {
4260 /* If we swap operand in encoding, we either match
4261 the next one or reverse direction of operands. */
4262 if (t->opcode_modifier.s)
4263 continue;
4264 else if (t->opcode_modifier.d)
4265 goto check_reverse;
4266 }
4267
29b0f896 4268 case 3:
fa99fab2
L		 4269 /* If we swap operand in encoding, we match the next one. */
4270 if (i.swap_operand && t->opcode_modifier.s)
4271 continue;
f48ff2ae 4272 case 4:
c0f3af97 4273 case 5:
c6fb90c8 4274 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4275 if (!operand_type_match (overlap0, i.types[0])
4276 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4277 || (check_register
4278 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4279 operand_types[0],
4280 overlap1, i.types[1],
4281 operand_types[1])))
29b0f896
AM		 4282 {
4283 /* Check if other direction is valid ... */
40fb9820 4284 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4285 continue;
4286
b6169b20 4287check_reverse:
29b0f896 4288 /* Try reversing direction of operands. */
c6fb90c8
L		 4289 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4290 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4291 if (!operand_type_match (overlap0, i.types[0])
4292 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4293 || (check_register
4294 && !operand_type_register_match (overlap0,
4295 i.types[0],
4296 operand_types[1],
4297 overlap1,
4298 i.types[1],
4299 operand_types[0])))
29b0f896
AM		 4300 {
4301 /* Does not match either direction. */
4302 continue;
4303 }
4304 /* found_reverse_match holds which of D or FloatDR
4305 we've found. */
40fb9820 4306 if (t->opcode_modifier.d)
8a2ed489 4307 found_reverse_match = Opcode_D;
40fb9820 4308 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4309 found_reverse_match = Opcode_FloatD;
4310 else
4311 found_reverse_match = 0;
40fb9820 4312 if (t->opcode_modifier.floatr)
8a2ed489 4313 found_reverse_match |= Opcode_FloatR;
29b0f896 4314 }
f48ff2ae 4315 else
29b0f896 4316 {
f48ff2ae 4317 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4318 switch (t->operands)
4319 {
c0f3af97
L		 4320 case 5:
4321 overlap4 = operand_type_and (i.types[4],
4322 operand_types[4]);
d1cbb4db 4323 case 4:
c6fb90c8
L		 4324 overlap3 = operand_type_and (i.types[3],
4325 operand_types[3]);
d1cbb4db 4326 case 3:
c6fb90c8
L		 4327 overlap2 = operand_type_and (i.types[2],
4328 operand_types[2]);
d1cbb4db
L		 4329 break;
4330 }
29b0f896 4331
f48ff2ae
L		 4332 switch (t->operands)
4333 {
c0f3af97
L		 4334 case 5:
4335 if (!operand_type_match (overlap4, i.types[4])
4336 || !operand_type_register_match (overlap3,
4337 i.types[3],
4338 operand_types[3],
4339 overlap4,
4340 i.types[4],
4341 operand_types[4]))
4342 continue;
f48ff2ae 4343 case 4:
40fb9820 4344 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4345 || (check_register
4346 && !operand_type_register_match (overlap2,
4347 i.types[2],
4348 operand_types[2],
4349 overlap3,
4350 i.types[3],
4351 operand_types[3])))
f48ff2ae
L		 4352 continue;
4353 case 3:
4354 /* Here we make use of the fact that there are no
4355 reverse match 3 operand instructions, and all 3
4356 operand instructions only need to be checked for
4357 register consistency between operands 2 and 3. */
40fb9820 4358 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4359 || (check_register
4360 && !operand_type_register_match (overlap1,
4361 i.types[1],
4362 operand_types[1],
4363 overlap2,
4364 i.types[2],
4365 operand_types[2])))
f48ff2ae
L		 4366 continue;
4367 break;
4368 }
29b0f896 4369 }
f48ff2ae 4370 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4371 slip through to break. */
4372 }
3629bb00 4373 if (!found_cpu_match)
29b0f896
AM		 4374 {
4375 found_reverse_match = 0;
4376 continue;
4377 }
c0f3af97 4378
5614d22c
JB		 4379 /* Check if vector and VEX operands are valid. */
4380 if (check_VecOperands (t) || VEX_check_operands (t))
4381 {
4382 specific_error = i.error;
4383 continue;
4384 }
a683cc34 4385
29b0f896
AM		 4386 /* We've found a match; break out of loop. */
4387 break;
4388 }
4389
4390 if (t == current_templates->end)
4391 {
4392 /* We found no match. */
a65babc9 4393 const char *err_msg;
5614d22c 4394 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4395 {
4396 default:
4397 abort ();
86e026a4 4398 case operand_size_mismatch:
a65babc9
L		 4399 err_msg = _("operand size mismatch");
4400 break;
4401 case operand_type_mismatch:
4402 err_msg = _("operand type mismatch");
4403 break;
4404 case register_type_mismatch:
4405 err_msg = _("register type mismatch");
4406 break;
4407 case number_of_operands_mismatch:
4408 err_msg = _("number of operands mismatch");
4409 break;
4410 case invalid_instruction_suffix:
4411 err_msg = _("invalid instruction suffix");
4412 break;
4413 case bad_imm4:
4a2608e3 4414 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4415 break;
4416 case old_gcc_only:
4417 err_msg = _("only supported with old gcc");
4418 break;
4419 case unsupported_with_intel_mnemonic:
4420 err_msg = _("unsupported with Intel mnemonic");
4421 break;
4422 case unsupported_syntax:
4423 err_msg = _("unsupported syntax");
4424 break;
4425 case unsupported:
35262a23 4426 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4427 current_templates->start->name);
4428 return NULL;
6c30d220
L		 4429 case invalid_vsib_address:
4430 err_msg = _("invalid VSIB address");
4431 break;
7bab8ab5
JB		 4432 case invalid_vector_register_set:
4433 err_msg = _("mask, index, and destination registers must be distinct");
4434 break;
6c30d220
L		 4435 case unsupported_vector_index_register:
4436 err_msg = _("unsupported vector index register");
4437 break;
a65babc9
L		 4438 }
4439 as_bad (_("%s for `%s'"), err_msg,
891edac4 4440 current_templates->start->name);
fa99fab2 4441 return NULL;
29b0f896 4442 }
252b5132 4443
29b0f896
AM		 4444 if (!quiet_warnings)
4445 {
4446 if (!intel_syntax
40fb9820
L		 4447 && (i.types[0].bitfield.jumpabsolute
4448 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4449 {
4450 as_warn (_("indirect %s without `*'"), t->name);
4451 }
4452
40fb9820
L		 4453 if (t->opcode_modifier.isprefix
4454 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4455 {
4456 /* Warn them that a data or address size prefix doesn't
4457 affect assembly of the next line of code. */
4458 as_warn (_("stand-alone `%s' prefix"), t->name);
4459 }
4460 }
4461
4462 /* Copy the template we found. */
4463 i.tm = *t;
539e75ad
L		 4464
4465 if (addr_prefix_disp != -1)
4466 i.tm.operand_types[addr_prefix_disp]
4467 = operand_types[addr_prefix_disp];
4468
29b0f896
AM		 4469 if (found_reverse_match)
4470 {
4471 /* If we found a reverse match we must alter the opcode
4472 direction bit. found_reverse_match holds bits to change
4473 (different for int & float insns). */
4474
4475 i.tm.base_opcode ^= found_reverse_match;
4476
539e75ad
L		 4477 i.tm.operand_types[0] = operand_types[1];
4478 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4479 }
4480
fa99fab2 4481 return t;
29b0f896
AM		 4482}
4483
4484static int
e3bb37b5 4485check_string (void)
29b0f896 4486{
40fb9820
L		 4487 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4488 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4489 {
4490 if (i.seg[0] != NULL && i.seg[0] != &es)
4491 {
a87af027 4492 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4493 i.tm.name,
a87af027
JB		 4494 mem_op + 1,
4495 register_prefix);
29b0f896
AM		 4496 return 0;
4497 }
4498 /* There's only ever one segment override allowed per instruction.
4499 This instruction possibly has a legal segment override on the
4500 second operand, so copy the segment to where non-string
4501 instructions store it, allowing common code. */
4502 i.seg[0] = i.seg[1];
4503 }
40fb9820 4504 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4505 {
4506 if (i.seg[1] != NULL && i.seg[1] != &es)
4507 {
a87af027 4508 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4509 i.tm.name,
a87af027
JB		 4510 mem_op + 2,
4511 register_prefix);
29b0f896
AM		 4512 return 0;
4513 }
4514 }
4515 return 1;
4516}
4517
4518static int
543613e9 4519process_suffix (void)
29b0f896
AM		 4520{
4521 /* If matched instruction specifies an explicit instruction mnemonic
4522 suffix, use it. */
40fb9820
L		 4523 if (i.tm.opcode_modifier.size16)
4524 i.suffix = WORD_MNEM_SUFFIX;
4525 else if (i.tm.opcode_modifier.size32)
4526 i.suffix = LONG_MNEM_SUFFIX;
4527 else if (i.tm.opcode_modifier.size64)
4528 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4529 else if (i.reg_operands)
4530 {
4531 /* If there's no instruction mnemonic suffix we try to invent one
4532 based on register operands. */
4533 if (!i.suffix)
4534 {
4535 /* We take i.suffix from the last register operand specified,
4536 Destination register type is more significant than source
381d071f
L		 4537 register type. crc32 in SSE4.2 prefers source register
4538 type. */
4539 if (i.tm.base_opcode == 0xf20f38f1)
4540 {
40fb9820
L		 4541 if (i.types[0].bitfield.reg16)
4542 i.suffix = WORD_MNEM_SUFFIX;
4543 else if (i.types[0].bitfield.reg32)
4544 i.suffix = LONG_MNEM_SUFFIX;
4545 else if (i.types[0].bitfield.reg64)
4546 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4547 }
9344ff29 4548 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4549 {
40fb9820 4550 if (i.types[0].bitfield.reg8)
20592a94
L		 4551 i.suffix = BYTE_MNEM_SUFFIX;
4552 }
381d071f
L		 4553
4554 if (!i.suffix)
4555 {
4556 int op;
4557
20592a94
L		 4558 if (i.tm.base_opcode == 0xf20f38f1
4559 || i.tm.base_opcode == 0xf20f38f0)
4560 {
4561 /* We have to know the operand size for crc32. */
4562 as_bad (_("ambiguous memory operand size for `%s`"),
4563 i.tm.name);
4564 return 0;
4565 }
4566
381d071f 4567 for (op = i.operands; --op >= 0;)
40fb9820 4568 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4569 {
40fb9820
L		 4570 if (i.types[op].bitfield.reg8)
4571 {
4572 i.suffix = BYTE_MNEM_SUFFIX;
4573 break;
4574 }
4575 else if (i.types[op].bitfield.reg16)
4576 {
4577 i.suffix = WORD_MNEM_SUFFIX;
4578 break;
4579 }
4580 else if (i.types[op].bitfield.reg32)
4581 {
4582 i.suffix = LONG_MNEM_SUFFIX;
4583 break;
4584 }
4585 else if (i.types[op].bitfield.reg64)
4586 {
4587 i.suffix = QWORD_MNEM_SUFFIX;
4588 break;
4589 }
381d071f
L		 4590 }
4591 }
29b0f896
AM		 4592 }
4593 else if (i.suffix == BYTE_MNEM_SUFFIX)
4594 {
2eb952a4
L		 4595 if (intel_syntax
4596 && i.tm.opcode_modifier.ignoresize
4597 && i.tm.opcode_modifier.no_bsuf)
4598 i.suffix = 0;
4599 else if (!check_byte_reg ())
29b0f896
AM		 4600 return 0;
4601 }
4602 else if (i.suffix == LONG_MNEM_SUFFIX)
4603 {
2eb952a4
L		 4604 if (intel_syntax
4605 && i.tm.opcode_modifier.ignoresize
4606 && i.tm.opcode_modifier.no_lsuf)
4607 i.suffix = 0;
4608 else if (!check_long_reg ())
29b0f896
AM		 4609 return 0;
4610 }
4611 else if (i.suffix == QWORD_MNEM_SUFFIX)
4612 {
955e1e6a
L		 4613 if (intel_syntax
4614 && i.tm.opcode_modifier.ignoresize
4615 && i.tm.opcode_modifier.no_qsuf)
4616 i.suffix = 0;
4617 else if (!check_qword_reg ())
29b0f896
AM		 4618 return 0;
4619 }
4620 else if (i.suffix == WORD_MNEM_SUFFIX)
4621 {
2eb952a4
L		 4622 if (intel_syntax
4623 && i.tm.opcode_modifier.ignoresize
4624 && i.tm.opcode_modifier.no_wsuf)
4625 i.suffix = 0;
4626 else if (!check_word_reg ())
29b0f896
AM		 4627 return 0;
4628 }
c0f3af97
L		 4629 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4630 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4631 {
c0f3af97 4632 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4633 should check if it is a valid suffix. */
4634 }
40fb9820 4635 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4636 /* Do nothing if the instruction is going to ignore the prefix. */
4637 ;
4638 else
4639 abort ();
4640 }
40fb9820 4641 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4642 && !i.suffix
4643 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4644 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4645 {
4646 i.suffix = stackop_size;
4647 }
9306ca4a
JB		 4648 else if (intel_syntax
4649 && !i.suffix
40fb9820
L		 4650 && (i.tm.operand_types[0].bitfield.jumpabsolute
4651 || i.tm.opcode_modifier.jumpbyte
4652 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4653 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4654 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4655 {
4656 switch (flag_code)
4657 {
4658 case CODE_64BIT:
40fb9820 4659 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4660 {
4661 i.suffix = QWORD_MNEM_SUFFIX;
4662 break;
4663 }
4664 case CODE_32BIT:
40fb9820 4665 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4666 i.suffix = LONG_MNEM_SUFFIX;
4667 break;
4668 case CODE_16BIT:
40fb9820 4669 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4670 i.suffix = WORD_MNEM_SUFFIX;
4671 break;
4672 }
4673 }
252b5132 4674
9306ca4a 4675 if (!i.suffix)
29b0f896 4676 {
9306ca4a
JB		 4677 if (!intel_syntax)
4678 {
40fb9820 4679 if (i.tm.opcode_modifier.w)
9306ca4a 4680 {
4eed87de
AM		 4681 as_bad (_("no instruction mnemonic suffix given and "
4682 "no register operands; can't size instruction"));
9306ca4a
JB		 4683 return 0;
4684 }
4685 }
4686 else
4687 {
40fb9820 4688 unsigned int suffixes;
7ab9ffdd 4689
40fb9820
L		 4690 suffixes = !i.tm.opcode_modifier.no_bsuf;
4691 if (!i.tm.opcode_modifier.no_wsuf)
4692 suffixes |= 1 << 1;
4693 if (!i.tm.opcode_modifier.no_lsuf)
4694 suffixes |= 1 << 2;
fc4adea1 4695 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4696 suffixes |= 1 << 3;
4697 if (!i.tm.opcode_modifier.no_ssuf)
4698 suffixes |= 1 << 4;
4699 if (!i.tm.opcode_modifier.no_qsuf)
4700 suffixes |= 1 << 5;
4701
4702 /* There are more than suffix matches. */
4703 if (i.tm.opcode_modifier.w
9306ca4a 4704 || ((suffixes & (suffixes - 1))
40fb9820
L		 4705 && !i.tm.opcode_modifier.defaultsize
4706 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4707 {
4708 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4709 return 0;
4710 }
4711 }
29b0f896 4712 }
252b5132 4713
9306ca4a
JB		 4714 /* Change the opcode based on the operand size given by i.suffix;
4715 We don't need to change things for byte insns. */
4716
582d5edd
L		 4717 if (i.suffix
4718 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4719 && i.suffix != XMMWORD_MNEM_SUFFIX
4720 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4721 {
4722 /* It's not a byte, select word/dword operation. */
40fb9820 4723 if (i.tm.opcode_modifier.w)
29b0f896 4724 {
40fb9820 4725 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4726 i.tm.base_opcode |= 8;
4727 else
4728 i.tm.base_opcode |= 1;
4729 }
0f3f3d8b 4730
29b0f896
AM		 4731 /* Now select between word & dword operations via the operand
4732 size prefix, except for instructions that will ignore this
4733 prefix anyway. */
ca61edf2 4734 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4735 {
ca61edf2
L		 4736 /* The address size override prefix changes the size of the
4737 first operand. */
40fb9820
L		 4738 if ((flag_code == CODE_32BIT
4739 && i.op->regs[0].reg_type.bitfield.reg16)
4740 || (flag_code != CODE_32BIT
4741 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4742 if (!add_prefix (ADDR_PREFIX_OPCODE))
4743 return 0;
4744 }
4745 else if (i.suffix != QWORD_MNEM_SUFFIX
4746 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4747 && !i.tm.opcode_modifier.ignoresize
4748 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4749 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4750 || (flag_code == CODE_64BIT
40fb9820 4751 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4752 {
4753 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4754
40fb9820 4755 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4756 prefix = ADDR_PREFIX_OPCODE;
252b5132 4757
29b0f896
AM		 4758 if (!add_prefix (prefix))
4759 return 0;
24eab124 4760 }
252b5132 4761
29b0f896
AM		 4762 /* Set mode64 for an operand. */
4763 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4764 && flag_code == CODE_64BIT
40fb9820 4765 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4766 {
4767 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4768 need rex64. cmpxchg8b is also a special case. */
4769 if (! (i.operands == 2
4770 && i.tm.base_opcode == 0x90
4771 && i.tm.extension_opcode == None
0dfbf9d7
L		 4772 && operand_type_equal (&i.types [0], &acc64)
4773 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4774 && ! (i.operands == 1
4775 && i.tm.base_opcode == 0xfc7
4776 && i.tm.extension_opcode == 1
40fb9820
L		 4777 && !operand_type_check (i.types [0], reg)
4778 && operand_type_check (i.types [0], anymem)))
f6bee062 4779 i.rex |= REX_W;
46e883c5 4780 }
3e73aa7c 4781
29b0f896
AM		 4782 /* Size floating point instruction. */
4783 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4784 if (i.tm.opcode_modifier.floatmf)
543613e9 4785 i.tm.base_opcode ^= 4;
29b0f896 4786 }
7ecd2f8b 4787
29b0f896
AM		 4788 return 1;
4789}
3e73aa7c 4790
29b0f896 4791static int
543613e9 4792check_byte_reg (void)
29b0f896
AM		 4793{
4794 int op;
543613e9 4795
29b0f896
AM		 4796 for (op = i.operands; --op >= 0;)
4797 {
4798 /* If this is an eight bit register, it's OK. If it's the 16 or
4799 32 bit version of an eight bit register, we will just use the
4800 low portion, and that's OK too. */
40fb9820 4801 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4802 continue;
4803
5a819eb9
JB		 4804 /* I/O port address operands are OK too. */
4805 if (i.tm.operand_types[op].bitfield.inoutportreg)
4806 continue;
4807
9344ff29
L		 4808 /* crc32 doesn't generate this warning. */
4809 if (i.tm.base_opcode == 0xf20f38f0)
4810 continue;
4811
40fb9820
L		 4812 if ((i.types[op].bitfield.reg16
4813 || i.types[op].bitfield.reg32
4814 || i.types[op].bitfield.reg64)
5a819eb9
JB		 4815 && i.op[op].regs->reg_num < 4
4816 /* Prohibit these changes in 64bit mode, since the lowering
4817 would be more complicated. */
4818 && flag_code != CODE_64BIT)
29b0f896 4819 {
29b0f896 4820#if REGISTER_WARNINGS
5a819eb9 4821 if (!quiet_warnings)
a540244d
L		 4822 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4823 register_prefix,
40fb9820 4824 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4825 ? REGNAM_AL - REGNAM_AX
4826 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4827 register_prefix,
29b0f896
AM		 4828 i.op[op].regs->reg_name,
4829 i.suffix);
4830#endif
4831 continue;
4832 }
4833 /* Any other register is bad. */
40fb9820
L		 4834 if (i.types[op].bitfield.reg16
4835 || i.types[op].bitfield.reg32
4836 || i.types[op].bitfield.reg64
4837 || i.types[op].bitfield.regmmx
4838 || i.types[op].bitfield.regxmm
c0f3af97 4839 || i.types[op].bitfield.regymm
40fb9820
L		 4840 || i.types[op].bitfield.sreg2
4841 || i.types[op].bitfield.sreg3
4842 || i.types[op].bitfield.control
4843 || i.types[op].bitfield.debug
4844 || i.types[op].bitfield.test
4845 || i.types[op].bitfield.floatreg
4846 || i.types[op].bitfield.floatacc)
29b0f896 4847 {
a540244d
L		 4848 as_bad (_("`%s%s' not allowed with `%s%c'"),
4849 register_prefix,
29b0f896
AM		 4850 i.op[op].regs->reg_name,
4851 i.tm.name,
4852 i.suffix);
4853 return 0;
4854 }
4855 }
4856 return 1;
4857}
4858
4859static int
e3bb37b5 4860check_long_reg (void)
29b0f896
AM		 4861{
4862 int op;
4863
4864 for (op = i.operands; --op >= 0;)
4865 /* Reject eight bit registers, except where the template requires
4866 them. (eg. movzb) */
40fb9820
L		 4867 if (i.types[op].bitfield.reg8
4868 && (i.tm.operand_types[op].bitfield.reg16
4869 || i.tm.operand_types[op].bitfield.reg32
4870 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4871 {
a540244d
L		 4872 as_bad (_("`%s%s' not allowed with `%s%c'"),
4873 register_prefix,
29b0f896
AM		 4874 i.op[op].regs->reg_name,
4875 i.tm.name,
4876 i.suffix);
4877 return 0;
4878 }
4879 /* Warn if the e prefix on a general reg is missing. */
4880 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4881 && i.types[op].bitfield.reg16
4882 && (i.tm.operand_types[op].bitfield.reg32
4883 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4884 {
4885 /* Prohibit these changes in the 64bit mode, since the
4886 lowering is more complicated. */
4887 if (flag_code == CODE_64BIT)
252b5132 4888 {
2b5d6a91 4889 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4890 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4891 i.suffix);
4892 return 0;
252b5132 4893 }
29b0f896
AM		 4894#if REGISTER_WARNINGS
4895 else
a540244d
L		 4896 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4897 register_prefix,
29b0f896 4898 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4899 register_prefix,
29b0f896
AM		 4900 i.op[op].regs->reg_name,
4901 i.suffix);
4902#endif
252b5132 4903 }
29b0f896 4904 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4905 else if (i.types[op].bitfield.reg64
4906 && (i.tm.operand_types[op].bitfield.reg32
4907 || i.tm.operand_types[op].bitfield.acc))
252b5132 4908 {
34828aad 4909 if (intel_syntax
ca61edf2 4910 && i.tm.opcode_modifier.toqword
40fb9820 4911 && !i.types[0].bitfield.regxmm)
34828aad 4912 {
ca61edf2 4913 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4914 i.suffix = QWORD_MNEM_SUFFIX;
4915 }
4916 else
4917 {
2b5d6a91 4918 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4919 register_prefix, i.op[op].regs->reg_name,
4920 i.suffix);
4921 return 0;
4922 }
29b0f896
AM		 4923 }
4924 return 1;
4925}
252b5132 4926
29b0f896 4927static int
e3bb37b5 4928check_qword_reg (void)
29b0f896
AM		 4929{
4930 int op;
252b5132 4931
29b0f896
AM		 4932 for (op = i.operands; --op >= 0; )
4933 /* Reject eight bit registers, except where the template requires
4934 them. (eg. movzb) */
40fb9820
L		 4935 if (i.types[op].bitfield.reg8
4936 && (i.tm.operand_types[op].bitfield.reg16
4937 || i.tm.operand_types[op].bitfield.reg32
4938 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4939 {
a540244d
L		 4940 as_bad (_("`%s%s' not allowed with `%s%c'"),
4941 register_prefix,
29b0f896
AM		 4942 i.op[op].regs->reg_name,
4943 i.tm.name,
4944 i.suffix);
4945 return 0;
4946 }
4947 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4948 else if ((i.types[op].bitfield.reg16
4949 || i.types[op].bitfield.reg32)
4950 && (i.tm.operand_types[op].bitfield.reg32
4951 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4952 {
4953 /* Prohibit these changes in the 64bit mode, since the
4954 lowering is more complicated. */
34828aad 4955 if (intel_syntax
ca61edf2 4956 && i.tm.opcode_modifier.todword
40fb9820 4957 && !i.types[0].bitfield.regxmm)
34828aad 4958 {
ca61edf2 4959 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4960 i.suffix = LONG_MNEM_SUFFIX;
4961 }
4962 else
4963 {
2b5d6a91 4964 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4965 register_prefix, i.op[op].regs->reg_name,
4966 i.suffix);
4967 return 0;
4968 }
252b5132 4969 }
29b0f896
AM		 4970 return 1;
4971}
252b5132 4972
29b0f896 4973static int
e3bb37b5 4974check_word_reg (void)
29b0f896
AM		 4975{
4976 int op;
4977 for (op = i.operands; --op >= 0;)
4978 /* Reject eight bit registers, except where the template requires
4979 them. (eg. movzb) */
40fb9820
L		 4980 if (i.types[op].bitfield.reg8
4981 && (i.tm.operand_types[op].bitfield.reg16
4982 || i.tm.operand_types[op].bitfield.reg32
4983 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4984 {
a540244d
L		 4985 as_bad (_("`%s%s' not allowed with `%s%c'"),
4986 register_prefix,
29b0f896
AM		 4987 i.op[op].regs->reg_name,
4988 i.tm.name,
4989 i.suffix);
4990 return 0;
4991 }
4992 /* Warn if the e prefix on a general reg is present. */
4993 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4994 && i.types[op].bitfield.reg32
4995 && (i.tm.operand_types[op].bitfield.reg16
4996 || i.tm.operand_types[op].bitfield.acc))
252b5132 4997 {
29b0f896
AM		 4998 /* Prohibit these changes in the 64bit mode, since the
4999 lowering is more complicated. */
5000 if (flag_code == CODE_64BIT)
252b5132 5001 {
2b5d6a91 5002 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5003 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5004 i.suffix);
5005 return 0;
252b5132 5006 }
29b0f896
AM		 5007 else
5008#if REGISTER_WARNINGS
a540244d
L		 5009 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5010 register_prefix,
29b0f896 5011 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 5012 register_prefix,
29b0f896
AM		 5013 i.op[op].regs->reg_name,
5014 i.suffix);
5015#endif
5016 }
5017 return 1;
5018}
252b5132 5019
29b0f896 5020static int
40fb9820 5021update_imm (unsigned int j)
29b0f896 5022{
bc0844ae 5023 i386_operand_type overlap = i.types[j];
40fb9820
L		 5024 if ((overlap.bitfield.imm8
5025 || overlap.bitfield.imm8s
5026 || overlap.bitfield.imm16
5027 || overlap.bitfield.imm32
5028 || overlap.bitfield.imm32s
5029 || overlap.bitfield.imm64)
0dfbf9d7
L		 5030 && !operand_type_equal (&overlap, &imm8)
5031 && !operand_type_equal (&overlap, &imm8s)
5032 && !operand_type_equal (&overlap, &imm16)
5033 && !operand_type_equal (&overlap, &imm32)
5034 && !operand_type_equal (&overlap, &imm32s)
5035 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5036 {
5037 if (i.suffix)
5038 {
40fb9820
L		 5039 i386_operand_type temp;
5040
0dfbf9d7 5041 operand_type_set (&temp, 0);
7ab9ffdd 5042 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5043 {
5044 temp.bitfield.imm8 = overlap.bitfield.imm8;
5045 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5046 }
5047 else if (i.suffix == WORD_MNEM_SUFFIX)
5048 temp.bitfield.imm16 = overlap.bitfield.imm16;
5049 else if (i.suffix == QWORD_MNEM_SUFFIX)
5050 {
5051 temp.bitfield.imm64 = overlap.bitfield.imm64;
5052 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5053 }
5054 else
5055 temp.bitfield.imm32 = overlap.bitfield.imm32;
5056 overlap = temp;
29b0f896 5057 }
0dfbf9d7
L		 5058 else if (operand_type_equal (&overlap, &imm16_32_32s)
5059 || operand_type_equal (&overlap, &imm16_32)
5060 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5061 {
40fb9820 5062 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5063 overlap = imm16;
40fb9820 5064 else
65da13b5 5065 overlap = imm32s;
29b0f896 5066 }
0dfbf9d7
L		 5067 if (!operand_type_equal (&overlap, &imm8)
5068 && !operand_type_equal (&overlap, &imm8s)
5069 && !operand_type_equal (&overlap, &imm16)
5070 && !operand_type_equal (&overlap, &imm32)
5071 && !operand_type_equal (&overlap, &imm32s)
5072 && !operand_type_equal (&overlap, &imm64))
29b0f896 5073 {
4eed87de
AM		 5074 as_bad (_("no instruction mnemonic suffix given; "
5075 "can't determine immediate size"));
29b0f896
AM		 5076 return 0;
5077 }
5078 }
40fb9820 5079 i.types[j] = overlap;
29b0f896 5080
40fb9820
L		 5081 return 1;
5082}
5083
5084static int
5085finalize_imm (void)
5086{
bc0844ae 5087 unsigned int j, n;
29b0f896 5088
bc0844ae
L		 5089 /* Update the first 2 immediate operands. */
5090 n = i.operands > 2 ? 2 : i.operands;
5091 if (n)
5092 {
5093 for (j = 0; j < n; j++)
5094 if (update_imm (j) == 0)
5095 return 0;
40fb9820 5096
bc0844ae
L		 5097 /* The 3rd operand can't be immediate operand. */
5098 gas_assert (operand_type_check (i.types[2], imm) == 0);
5099 }
29b0f896
AM		 5100
5101 return 1;
5102}
5103
c0f3af97
L		 5104static int
5105bad_implicit_operand (int xmm)
5106{
91d6fa6a
NC		 5107 const char *ireg = xmm ? "xmm0" : "ymm0";
5108
c0f3af97
L		 5109 if (intel_syntax)
5110 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5111 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5112 else
5113 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5114 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5115 return 0;
5116}
5117
29b0f896 5118static int
e3bb37b5 5119process_operands (void)
29b0f896
AM		 5120{
5121 /* Default segment register this instruction will use for memory
5122 accesses. 0 means unknown. This is only for optimizing out
5123 unnecessary segment overrides. */
5124 const seg_entry *default_seg = 0;
5125
2426c15f 5126 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5127 {
91d6fa6a
NC		 5128 unsigned int dupl = i.operands;
5129 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5130 unsigned int j;
5131
c0f3af97 5132 /* The destination must be an xmm register. */
9c2799c2 5133 gas_assert (i.reg_operands
91d6fa6a 5134 && MAX_OPERANDS > dupl
7ab9ffdd 5135 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5136
5137 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5138 {
c0f3af97 5139 /* The first operand is implicit and must be xmm0. */
9c2799c2 5140 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5141 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5142 return bad_implicit_operand (1);
5143
8cd7925b 5144 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5145 {
5146 /* Keep xmm0 for instructions with VEX prefix and 3
5147 sources. */
5148 goto duplicate;
5149 }
e2ec9d29 5150 else
c0f3af97
L		 5151 {
5152 /* We remove the first xmm0 and keep the number of
5153 operands unchanged, which in fact duplicates the
5154 destination. */
5155 for (j = 1; j < i.operands; j++)
5156 {
5157 i.op[j - 1] = i.op[j];
5158 i.types[j - 1] = i.types[j];
5159 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5160 }
5161 }
5162 }
5163 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5164 {
91d6fa6a 5165 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5166 && (i.tm.opcode_modifier.vexsources
5167 == VEX3SOURCES));
c0f3af97
L		 5168
5169 /* Add the implicit xmm0 for instructions with VEX prefix
5170 and 3 sources. */
5171 for (j = i.operands; j > 0; j--)
5172 {
5173 i.op[j] = i.op[j - 1];
5174 i.types[j] = i.types[j - 1];
5175 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5176 }
5177 i.op[0].regs
5178 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5179 i.types[0] = regxmm;
c0f3af97
L		 5180 i.tm.operand_types[0] = regxmm;
5181
5182 i.operands += 2;
5183 i.reg_operands += 2;
5184 i.tm.operands += 2;
5185
91d6fa6a 5186 dupl++;
c0f3af97 5187 dest++;
91d6fa6a
NC		 5188 i.op[dupl] = i.op[dest];
5189 i.types[dupl] = i.types[dest];
5190 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5191 }
c0f3af97
L		 5192 else
5193 {
5194duplicate:
5195 i.operands++;
5196 i.reg_operands++;
5197 i.tm.operands++;
5198
91d6fa6a
NC		 5199 i.op[dupl] = i.op[dest];
5200 i.types[dupl] = i.types[dest];
5201 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5202 }
5203
5204 if (i.tm.opcode_modifier.immext)
5205 process_immext ();
5206 }
5207 else if (i.tm.opcode_modifier.firstxmm0)
5208 {
5209 unsigned int j;
5210
5211 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5212 gas_assert (i.reg_operands
7ab9ffdd
L		 5213 && (operand_type_equal (&i.types[0], &regxmm)
5214 || operand_type_equal (&i.types[0], &regymm)));
4c692bc7 5215 if (register_number (i.op[0].regs) != 0)
c0f3af97 5216 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5217
5218 for (j = 1; j < i.operands; j++)
5219 {
5220 i.op[j - 1] = i.op[j];
5221 i.types[j - 1] = i.types[j];
5222
5223 /* We need to adjust fields in i.tm since they are used by
5224 build_modrm_byte. */
5225 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5226 }
5227
e2ec9d29
L		 5228 i.operands--;
5229 i.reg_operands--;
e2ec9d29
L		 5230 i.tm.operands--;
5231 }
5232 else if (i.tm.opcode_modifier.regkludge)
5233 {
5234 /* The imul $imm, %reg instruction is converted into
5235 imul $imm, %reg, %reg, and the clr %reg instruction
5236 is converted into xor %reg, %reg. */
5237
5238 unsigned int first_reg_op;
5239
5240 if (operand_type_check (i.types[0], reg))
5241 first_reg_op = 0;
5242 else
5243 first_reg_op = 1;
5244 /* Pretend we saw the extra register operand. */
9c2799c2 5245 gas_assert (i.reg_operands == 1
7ab9ffdd 5246 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5247 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5248 i.types[first_reg_op + 1] = i.types[first_reg_op];
5249 i.operands++;
5250 i.reg_operands++;
29b0f896
AM		 5251 }
5252
40fb9820 5253 if (i.tm.opcode_modifier.shortform)
29b0f896 5254 {
40fb9820
L		 5255 if (i.types[0].bitfield.sreg2
5256 || i.types[0].bitfield.sreg3)
29b0f896 5257 {
4eed87de
AM		 5258 if (i.tm.base_opcode == POP_SEG_SHORT
5259 && i.op[0].regs->reg_num == 1)
29b0f896 5260 {
a87af027 5261 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5262 return 0;
29b0f896 5263 }
4eed87de
AM		 5264 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5265 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5266 i.rex |= REX_B;
4eed87de
AM		 5267 }
5268 else
5269 {
7ab9ffdd 5270 /* The register or float register operand is in operand
85f10a01 5271 0 or 1. */
40fb9820 5272 unsigned int op;
7ab9ffdd
L		 5273
5274 if (i.types[0].bitfield.floatreg
5275 || operand_type_check (i.types[0], reg))
5276 op = 0;
5277 else
5278 op = 1;
4eed87de
AM		 5279 /* Register goes in low 3 bits of opcode. */
5280 i.tm.base_opcode |= i.op[op].regs->reg_num;
5281 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5282 i.rex |= REX_B;
40fb9820 5283 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5284 {
4eed87de
AM		 5285 /* Warn about some common errors, but press on regardless.
5286 The first case can be generated by gcc (<= 2.8.1). */
5287 if (i.operands == 2)
5288 {
5289 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5290 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5291 register_prefix, i.op[!intel_syntax].regs->reg_name,
5292 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5293 }
5294 else
5295 {
5296 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5297 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5298 register_prefix, i.op[0].regs->reg_name);
4eed87de 5299 }
29b0f896
AM		 5300 }
5301 }
5302 }
40fb9820 5303 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5304 {
5305 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5306 must be put into the modrm byte). Now, we make the modrm and
5307 index base bytes based on all the info we've collected. */
29b0f896
AM		 5308
5309 default_seg = build_modrm_byte ();
5310 }
8a2ed489 5311 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5312 {
5313 default_seg = &ds;
5314 }
40fb9820 5315 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5316 {
5317 /* For the string instructions that allow a segment override
5318 on one of their operands, the default segment is ds. */
5319 default_seg = &ds;
5320 }
5321
75178d9d
L		 5322 if (i.tm.base_opcode == 0x8d /* lea */
5323 && i.seg[0]
5324 && !quiet_warnings)
30123838 5325 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5326
5327 /* If a segment was explicitly specified, and the specified segment
5328 is not the default, use an opcode prefix to select it. If we
5329 never figured out what the default segment is, then default_seg
5330 will be zero at this point, and the specified segment prefix will
5331 always be used. */
29b0f896
AM		 5332 if ((i.seg[0]) && (i.seg[0] != default_seg))
5333 {
5334 if (!add_prefix (i.seg[0]->seg_prefix))
5335 return 0;
5336 }
5337 return 1;
5338}
5339
5340static const seg_entry *
e3bb37b5 5341build_modrm_byte (void)
29b0f896
AM		 5342{
5343 const seg_entry *default_seg = 0;
c0f3af97 5344 unsigned int source, dest;
8cd7925b 5345 int vex_3_sources;
c0f3af97
L		 5346
5347 /* The first operand of instructions with VEX prefix and 3 sources
5348 must be VEX_Imm4. */
8cd7925b 5349 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5350 if (vex_3_sources)
5351 {
91d6fa6a 5352 unsigned int nds, reg_slot;
4c2c6516 5353 expressionS *exp;
c0f3af97 5354
922d8de8 5355 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5356 && i.tm.opcode_modifier.immext)
5357 {
5358 dest = i.operands - 2;
5359 gas_assert (dest == 3);
5360 }
922d8de8 5361 else
a683cc34 5362 dest = i.operands - 1;
c0f3af97 5363 nds = dest - 1;
922d8de8 5364
a683cc34
SP		 5365 /* There are 2 kinds of instructions:
5366 1. 5 operands: 4 register operands or 3 register operands
5367 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5368 VexW0 or VexW1. The destination must be either XMM or YMM
5369 register.
5370 2. 4 operands: 4 register operands or 3 register operands
5371 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5372 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5373 || (i.reg_operands == 3 && i.mem_operands == 1))
5374 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5375 && (i.tm.opcode_modifier.veximmext
5376 || (i.imm_operands == 1
5377 && i.types[0].bitfield.vec_imm4
5378 && (i.tm.opcode_modifier.vexw == VEXW0
5379 || i.tm.opcode_modifier.vexw == VEXW1)
5380 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5381 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5382
5383 if (i.imm_operands == 0)
5384 {
5385 /* When there is no immediate operand, generate an 8bit
5386 immediate operand to encode the first operand. */
5387 exp = &im_expressions[i.imm_operands++];
5388 i.op[i.operands].imms = exp;
5389 i.types[i.operands] = imm8;
5390 i.operands++;
5391 /* If VexW1 is set, the first operand is the source and
5392 the second operand is encoded in the immediate operand. */
5393 if (i.tm.opcode_modifier.vexw == VEXW1)
5394 {
5395 source = 0;
5396 reg_slot = 1;
5397 }
5398 else
5399 {
5400 source = 1;
5401 reg_slot = 0;
5402 }
5403
5404 /* FMA swaps REG and NDS. */
5405 if (i.tm.cpu_flags.bitfield.cpufma)
5406 {
5407 unsigned int tmp;
5408 tmp = reg_slot;
5409 reg_slot = nds;
5410 nds = tmp;
5411 }
5412
24981e7b
L		 5413 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5414 &regxmm)
a683cc34
SP		 5415 || operand_type_equal (&i.tm.operand_types[reg_slot],
5416 &regymm));
5417 exp->X_op = O_constant;
4c692bc7 5418 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
a683cc34 5419 }
922d8de8 5420 else
a683cc34
SP		 5421 {
5422 unsigned int imm_slot;
5423
5424 if (i.tm.opcode_modifier.vexw == VEXW0)
5425 {
5426 /* If VexW0 is set, the third operand is the source and
5427 the second operand is encoded in the immediate
5428 operand. */
5429 source = 2;
5430 reg_slot = 1;
5431 }
5432 else
5433 {
5434 /* VexW1 is set, the second operand is the source and
5435 the third operand is encoded in the immediate
5436 operand. */
5437 source = 1;
5438 reg_slot = 2;
5439 }
5440
5441 if (i.tm.opcode_modifier.immext)
5442 {
5443 /* When ImmExt is set, the immdiate byte is the last
5444 operand. */
5445 imm_slot = i.operands - 1;
5446 source--;
5447 reg_slot--;
5448 }
5449 else
5450 {
5451 imm_slot = 0;
5452
5453 /* Turn on Imm8 so that output_imm will generate it. */
5454 i.types[imm_slot].bitfield.imm8 = 1;
5455 }
5456
24981e7b
L		 5457 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5458 &regxmm)
5459 || operand_type_equal (&i.tm.operand_types[reg_slot],
5460 &regymm));
a683cc34 5461 i.op[imm_slot].imms->X_add_number
4c692bc7 5462 |= register_number (i.op[reg_slot].regs) << 4;
a683cc34
SP		 5463 }
5464
5465 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5466 || operand_type_equal (&i.tm.operand_types[nds],
5467 &regymm));
dae39acc 5468 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5469 }
5470 else
5471 source = dest = 0;
29b0f896
AM		 5472
5473 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5474 implicit registers do not count. If there are 3 register
5475 operands, it must be a instruction with VexNDS. For a
5476 instruction with VexNDD, the destination register is encoded
5477 in VEX prefix. If there are 4 register operands, it must be
5478 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5479 if (i.mem_operands == 0
5480 && ((i.reg_operands == 2
2426c15f 5481 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5482 || (i.reg_operands == 3
2426c15f 5483 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5484 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5485 {
cab737b9
L		 5486 switch (i.operands)
5487 {
5488 case 2:
5489 source = 0;
5490 break;
5491 case 3:
c81128dc
L		 5492 /* When there are 3 operands, one of them may be immediate,
5493 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5494 the first operand must be shift count register (cl) or it
5495 is an instruction with VexNDS. */
9c2799c2 5496 gas_assert (i.imm_operands == 1
7ab9ffdd 5497 || (i.imm_operands == 0
2426c15f 5498 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5499 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5500 if (operand_type_check (i.types[0], imm)
5501 || i.types[0].bitfield.shiftcount)
5502 source = 1;
5503 else
5504 source = 0;
cab737b9
L		 5505 break;
5506 case 4:
368d64cc
L		 5507 /* When there are 4 operands, the first two must be 8bit
5508 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5509 one.
5510
5511 For instructions with VexNDS, if the first operand
5512 an imm8, the source operand is the 2nd one. If the last
5513 operand is imm8, the source operand is the first one. */
9c2799c2 5514 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5515 && i.types[0].bitfield.imm8
5516 && i.types[1].bitfield.imm8)
2426c15f 5517 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5518 && i.imm_operands == 1
5519 && (i.types[0].bitfield.imm8
5520 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5521 if (i.imm_operands == 2)
5522 source = 2;
5523 else
c0f3af97
L		 5524 {
5525 if (i.types[0].bitfield.imm8)
5526 source = 1;
5527 else
5528 source = 0;
5529 }
c0f3af97
L		 5530 break;
5531 case 5:
cab737b9
L		 5532 break;
5533 default:
5534 abort ();
5535 }
5536
c0f3af97
L		 5537 if (!vex_3_sources)
5538 {
5539 dest = source + 1;
5540
2426c15f 5541 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5542 {
5543 /* For instructions with VexNDS, the register-only
f12dc422
L		 5544 source operand must be 32/64bit integer, XMM or
5545 YMM register. It is encoded in VEX prefix. We
5546 need to clear RegMem bit before calling
5547 operand_type_equal. */
5548
5549 i386_operand_type op;
5550 unsigned int vvvv;
5551
5552 /* Check register-only source operand when two source
5553 operands are swapped. */
5554 if (!i.tm.operand_types[source].bitfield.baseindex
5555 && i.tm.operand_types[dest].bitfield.baseindex)
5556 {
5557 vvvv = source;
5558 source = dest;
5559 }
5560 else
5561 vvvv = dest;
5562
5563 op = i.tm.operand_types[vvvv];
fa99fab2 5564 op.bitfield.regmem = 0;
c0f3af97 5565 if ((dest + 1) >= i.operands
f12dc422
L		 5566 || (op.bitfield.reg32 != 1
5567 && !op.bitfield.reg64 != 1
5568 && !operand_type_equal (&op, &regxmm)
fa99fab2 5569 && !operand_type_equal (&op, &regymm)))
c0f3af97 5570 abort ();
f12dc422 5571 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5572 dest++;
5573 }
5574 }
29b0f896
AM		 5575
5576 i.rm.mode = 3;
5577 /* One of the register operands will be encoded in the i.tm.reg
5578 field, the other in the combined i.tm.mode and i.tm.regmem
5579 fields. If no form of this instruction supports a memory
5580 destination operand, then we assume the source operand may
5581 sometimes be a memory operand and so we need to store the
5582 destination in the i.rm.reg field. */
40fb9820
L		 5583 if (!i.tm.operand_types[dest].bitfield.regmem
5584 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5585 {
5586 i.rm.reg = i.op[dest].regs->reg_num;
5587 i.rm.regmem = i.op[source].regs->reg_num;
5588 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5589 i.rex |= REX_R;
29b0f896 5590 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5591 i.rex |= REX_B;
29b0f896
AM		 5592 }
5593 else
5594 {
5595 i.rm.reg = i.op[source].regs->reg_num;
5596 i.rm.regmem = i.op[dest].regs->reg_num;
5597 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5598 i.rex |= REX_B;
29b0f896 5599 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5600 i.rex |= REX_R;
29b0f896 5601 }
161a04f6 5602 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5603 {
40fb9820
L		 5604 if (!i.types[0].bitfield.control
5605 && !i.types[1].bitfield.control)
c4a530c5 5606 abort ();
161a04f6 5607 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5608 add_prefix (LOCK_PREFIX_OPCODE);
5609 }
29b0f896
AM		 5610 }
5611 else
5612 { /* If it's not 2 reg operands... */
c0f3af97
L		 5613 unsigned int mem;
5614
29b0f896
AM		 5615 if (i.mem_operands)
5616 {
5617 unsigned int fake_zero_displacement = 0;
99018f42 5618 unsigned int op;
4eed87de 5619
7ab9ffdd
L		 5620 for (op = 0; op < i.operands; op++)
5621 if (operand_type_check (i.types[op], anymem))
5622 break;
7ab9ffdd 5623 gas_assert (op < i.operands);
29b0f896 5624
6c30d220
L		 5625 if (i.tm.opcode_modifier.vecsib)
5626 {
5627 if (i.index_reg->reg_num == RegEiz
5628 || i.index_reg->reg_num == RegRiz)
5629 abort ();
5630
5631 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5632 if (!i.base_reg)
5633 {
5634 i.sib.base = NO_BASE_REGISTER;
5635 i.sib.scale = i.log2_scale_factor;
5636 i.types[op].bitfield.disp8 = 0;
5637 i.types[op].bitfield.disp16 = 0;
5638 i.types[op].bitfield.disp64 = 0;
5639 if (flag_code != CODE_64BIT)
5640 {
5641 /* Must be 32 bit */
5642 i.types[op].bitfield.disp32 = 1;
5643 i.types[op].bitfield.disp32s = 0;
5644 }
5645 else
5646 {
5647 i.types[op].bitfield.disp32 = 0;
5648 i.types[op].bitfield.disp32s = 1;
5649 }
5650 }
5651 i.sib.index = i.index_reg->reg_num;
5652 if ((i.index_reg->reg_flags & RegRex) != 0)
5653 i.rex |= REX_X;
5654 }
5655
29b0f896
AM		 5656 default_seg = &ds;
5657
5658 if (i.base_reg == 0)
5659 {
5660 i.rm.mode = 0;
5661 if (!i.disp_operands)
6c30d220
L		 5662 {
5663 fake_zero_displacement = 1;
5664 /* Instructions with VSIB byte need 32bit displacement
5665 if there is no base register. */
5666 if (i.tm.opcode_modifier.vecsib)
5667 i.types[op].bitfield.disp32 = 1;
5668 }
29b0f896
AM		 5669 if (i.index_reg == 0)
5670 {
6c30d220 5671 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5672 /* Operand is just <disp> */
20f0a1fc 5673 if (flag_code == CODE_64BIT)
29b0f896
AM		 5674 {
5675 /* 64bit mode overwrites the 32bit absolute
5676 addressing by RIP relative addressing and
5677 absolute addressing is encoded by one of the
5678 redundant SIB forms. */
5679 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5680 i.sib.base = NO_BASE_REGISTER;
5681 i.sib.index = NO_INDEX_REGISTER;
fc225355 5682 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5683 ? disp32s : disp32);
20f0a1fc 5684 }
fc225355
L		 5685 else if ((flag_code == CODE_16BIT)
5686 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5687 {
5688 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5689 i.types[op] = disp16;
20f0a1fc
NC		 5690 }
5691 else
5692 {
5693 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5694 i.types[op] = disp32;
29b0f896
AM		 5695 }
5696 }
6c30d220 5697 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5698 {
6c30d220 5699 /* !i.base_reg && i.index_reg */
db51cc60
L		 5700 if (i.index_reg->reg_num == RegEiz
5701 || i.index_reg->reg_num == RegRiz)
5702 i.sib.index = NO_INDEX_REGISTER;
5703 else
5704 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5705 i.sib.base = NO_BASE_REGISTER;
5706 i.sib.scale = i.log2_scale_factor;
5707 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5708 i.types[op].bitfield.disp8 = 0;
5709 i.types[op].bitfield.disp16 = 0;
5710 i.types[op].bitfield.disp64 = 0;
29b0f896 5711 if (flag_code != CODE_64BIT)
40fb9820
L		 5712 {
5713 /* Must be 32 bit */
5714 i.types[op].bitfield.disp32 = 1;
5715 i.types[op].bitfield.disp32s = 0;
5716 }
29b0f896 5717 else
40fb9820
L		 5718 {
5719 i.types[op].bitfield.disp32 = 0;
5720 i.types[op].bitfield.disp32s = 1;
5721 }
29b0f896 5722 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5723 i.rex |= REX_X;
29b0f896
AM		 5724 }
5725 }
5726 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5727 else if (i.base_reg->reg_num == RegRip ||
5728 i.base_reg->reg_num == RegEip)
29b0f896 5729 {
6c30d220 5730 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5731 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5732 i.types[op].bitfield.disp8 = 0;
5733 i.types[op].bitfield.disp16 = 0;
5734 i.types[op].bitfield.disp32 = 0;
5735 i.types[op].bitfield.disp32s = 1;
5736 i.types[op].bitfield.disp64 = 0;
71903a11 5737 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5738 if (! i.disp_operands)
5739 fake_zero_displacement = 1;
29b0f896 5740 }
40fb9820 5741 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5742 {
6c30d220 5743 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5744 switch (i.base_reg->reg_num)
5745 {
5746 case 3: /* (%bx) */
5747 if (i.index_reg == 0)
5748 i.rm.regmem = 7;
5749 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5750 i.rm.regmem = i.index_reg->reg_num - 6;
5751 break;
5752 case 5: /* (%bp) */
5753 default_seg = &ss;
5754 if (i.index_reg == 0)
5755 {
5756 i.rm.regmem = 6;
40fb9820 5757 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5758 {
5759 /* fake (%bp) into 0(%bp) */
40fb9820 5760 i.types[op].bitfield.disp8 = 1;
252b5132 5761 fake_zero_displacement = 1;
29b0f896
AM		 5762 }
5763 }
5764 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5765 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5766 break;
5767 default: /* (%si) -> 4 or (%di) -> 5 */
5768 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5769 }
5770 i.rm.mode = mode_from_disp_size (i.types[op]);
5771 }
5772 else /* i.base_reg and 32/64 bit mode */
5773 {
5774 if (flag_code == CODE_64BIT
40fb9820
L		 5775 && operand_type_check (i.types[op], disp))
5776 {
5777 i386_operand_type temp;
0dfbf9d7 5778 operand_type_set (&temp, 0);
40fb9820
L		 5779 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5780 i.types[op] = temp;
5781 if (i.prefix[ADDR_PREFIX] == 0)
5782 i.types[op].bitfield.disp32s = 1;
5783 else
5784 i.types[op].bitfield.disp32 = 1;
5785 }
20f0a1fc 5786
6c30d220
L		 5787 if (!i.tm.opcode_modifier.vecsib)
5788 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5789 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5790 i.rex |= REX_B;
29b0f896
AM		 5791 i.sib.base = i.base_reg->reg_num;
5792 /* x86-64 ignores REX prefix bit here to avoid decoder
5793 complications. */
848930b2
JB		 5794 if (!(i.base_reg->reg_flags & RegRex)
5795 && (i.base_reg->reg_num == EBP_REG_NUM
5796 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 5797 default_seg = &ss;
848930b2 5798 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 5799 {
848930b2
JB		 5800 fake_zero_displacement = 1;
5801 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5802 }
5803 i.sib.scale = i.log2_scale_factor;
5804 if (i.index_reg == 0)
5805 {
6c30d220 5806 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5807 /* <disp>(%esp) becomes two byte modrm with no index
5808 register. We've already stored the code for esp
5809 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5810 Any base register besides %esp will not use the
5811 extra modrm byte. */
5812 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5813 }
6c30d220 5814 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5815 {
db51cc60
L		 5816 if (i.index_reg->reg_num == RegEiz
5817 || i.index_reg->reg_num == RegRiz)
5818 i.sib.index = NO_INDEX_REGISTER;
5819 else
5820 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5821 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5822 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5823 i.rex |= REX_X;
29b0f896 5824 }
67a4f2b7
AO		 5825
5826 if (i.disp_operands
5827 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5828 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5829 i.rm.mode = 0;
5830 else
a501d77e
L		 5831 {
5832 if (!fake_zero_displacement
5833 && !i.disp_operands
5834 && i.disp_encoding)
5835 {
5836 fake_zero_displacement = 1;
5837 if (i.disp_encoding == disp_encoding_8bit)
5838 i.types[op].bitfield.disp8 = 1;
5839 else
5840 i.types[op].bitfield.disp32 = 1;
5841 }
5842 i.rm.mode = mode_from_disp_size (i.types[op]);
5843 }
29b0f896 5844 }
252b5132 5845
29b0f896
AM		 5846 if (fake_zero_displacement)
5847 {
5848 /* Fakes a zero displacement assuming that i.types[op]
5849 holds the correct displacement size. */
5850 expressionS *exp;
5851
9c2799c2 5852 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5853 exp = &disp_expressions[i.disp_operands++];
5854 i.op[op].disps = exp;
5855 exp->X_op = O_constant;
5856 exp->X_add_number = 0;
5857 exp->X_add_symbol = (symbolS *) 0;
5858 exp->X_op_symbol = (symbolS *) 0;
5859 }
c0f3af97
L		 5860
5861 mem = op;
29b0f896 5862 }
c0f3af97
L		 5863 else
5864 mem = ~0;
252b5132 5865
8c43a48b 5866 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5867 {
5868 if (operand_type_check (i.types[0], imm))
5869 i.vex.register_specifier = NULL;
5870 else
5871 {
5872 /* VEX.vvvv encodes one of the sources when the first
5873 operand is not an immediate. */
1ef99a7b 5874 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5875 i.vex.register_specifier = i.op[0].regs;
5876 else
5877 i.vex.register_specifier = i.op[1].regs;
5878 }
5879
5880 /* Destination is a XMM register encoded in the ModRM.reg
5881 and VEX.R bit. */
5882 i.rm.reg = i.op[2].regs->reg_num;
5883 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5884 i.rex |= REX_R;
5885
5886 /* ModRM.rm and VEX.B encodes the other source. */
5887 if (!i.mem_operands)
5888 {
5889 i.rm.mode = 3;
5890
1ef99a7b 5891 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5892 i.rm.regmem = i.op[1].regs->reg_num;
5893 else
5894 i.rm.regmem = i.op[0].regs->reg_num;
5895
5896 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5897 i.rex |= REX_B;
5898 }
5899 }
2426c15f 5900 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5901 {
5902 i.vex.register_specifier = i.op[2].regs;
5903 if (!i.mem_operands)
5904 {
5905 i.rm.mode = 3;
5906 i.rm.regmem = i.op[1].regs->reg_num;
5907 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5908 i.rex |= REX_B;
5909 }
5910 }
29b0f896
AM		 5911 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5912 (if any) based on i.tm.extension_opcode. Again, we must be
5913 careful to make sure that segment/control/debug/test/MMX
5914 registers are coded into the i.rm.reg field. */
f88c9eb0 5915 else if (i.reg_operands)
29b0f896 5916 {
99018f42 5917 unsigned int op;
7ab9ffdd
L		 5918 unsigned int vex_reg = ~0;
5919
5920 for (op = 0; op < i.operands; op++)
5921 if (i.types[op].bitfield.reg8
5922 || i.types[op].bitfield.reg16
5923 || i.types[op].bitfield.reg32
5924 || i.types[op].bitfield.reg64
5925 || i.types[op].bitfield.regmmx
5926 || i.types[op].bitfield.regxmm
5927 || i.types[op].bitfield.regymm
5928 || i.types[op].bitfield.sreg2
5929 || i.types[op].bitfield.sreg3
5930 || i.types[op].bitfield.control
5931 || i.types[op].bitfield.debug
5932 || i.types[op].bitfield.test)
5933 break;
c0209578 5934
7ab9ffdd
L		 5935 if (vex_3_sources)
5936 op = dest;
2426c15f 5937 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5938 {
5939 /* For instructions with VexNDS, the register-only
5940 source operand is encoded in VEX prefix. */
5941 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5942
7ab9ffdd 5943 if (op > mem)
c0f3af97 5944 {
7ab9ffdd
L		 5945 vex_reg = op++;
5946 gas_assert (op < i.operands);
c0f3af97
L		 5947 }
5948 else
c0f3af97 5949 {
f12dc422
L		 5950 /* Check register-only source operand when two source
5951 operands are swapped. */
5952 if (!i.tm.operand_types[op].bitfield.baseindex
5953 && i.tm.operand_types[op + 1].bitfield.baseindex)
5954 {
5955 vex_reg = op;
5956 op += 2;
5957 gas_assert (mem == (vex_reg + 1)
5958 && op < i.operands);
5959 }
5960 else
5961 {
5962 vex_reg = op + 1;
5963 gas_assert (vex_reg < i.operands);
5964 }
c0f3af97 5965 }
7ab9ffdd 5966 }
2426c15f 5967 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5968 {
f12dc422 5969 /* For instructions with VexNDD, the register destination
7ab9ffdd 5970 is encoded in VEX prefix. */
f12dc422
L		 5971 if (i.mem_operands == 0)
5972 {
5973 /* There is no memory operand. */
5974 gas_assert ((op + 2) == i.operands);
5975 vex_reg = op + 1;
5976 }
5977 else
8d63c93e 5978 {
f12dc422
L		 5979 /* There are only 2 operands. */
5980 gas_assert (op < 2 && i.operands == 2);
5981 vex_reg = 1;
5982 }
7ab9ffdd
L		 5983 }
5984 else
5985 gas_assert (op < i.operands);
99018f42 5986
7ab9ffdd
L		 5987 if (vex_reg != (unsigned int) ~0)
5988 {
f12dc422 5989 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5990
f12dc422
L		 5991 if (type->bitfield.reg32 != 1
5992 && type->bitfield.reg64 != 1
5993 && !operand_type_equal (type, &regxmm)
5994 && !operand_type_equal (type, &regymm))
7ab9ffdd 5995 abort ();
f88c9eb0 5996
7ab9ffdd
L		 5997 i.vex.register_specifier = i.op[vex_reg].regs;
5998 }
5999
1b9f0c97
L		 6000 /* Don't set OP operand twice. */
6001 if (vex_reg != op)
7ab9ffdd 6002 {
1b9f0c97
L		 6003 /* If there is an extension opcode to put here, the
6004 register number must be put into the regmem field. */
6005 if (i.tm.extension_opcode != None)
6006 {
6007 i.rm.regmem = i.op[op].regs->reg_num;
6008 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6009 i.rex |= REX_B;
6010 }
6011 else
6012 {
6013 i.rm.reg = i.op[op].regs->reg_num;
6014 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6015 i.rex |= REX_R;
6016 }
7ab9ffdd 6017 }
252b5132 6018
29b0f896
AM		 6019 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6020 must set it to 3 to indicate this is a register operand
6021 in the regmem field. */
6022 if (!i.mem_operands)
6023 i.rm.mode = 3;
6024 }
252b5132 6025
29b0f896 6026 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6027 if (i.tm.extension_opcode != None)
29b0f896
AM		 6028 i.rm.reg = i.tm.extension_opcode;
6029 }
6030 return default_seg;
6031}
252b5132 6032
29b0f896 6033static void
e3bb37b5 6034output_branch (void)
29b0f896
AM		 6035{
6036 char *p;
f8a5c266 6037 int size;
29b0f896
AM		 6038 int code16;
6039 int prefix;
6040 relax_substateT subtype;
6041 symbolS *sym;
6042 offsetT off;
6043
f8a5c266 6044 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6045 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6046
6047 prefix = 0;
6048 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6049 {
29b0f896
AM		 6050 prefix = 1;
6051 i.prefixes -= 1;
6052 code16 ^= CODE16;
252b5132 6053 }
29b0f896
AM		 6054 /* Pentium4 branch hints. */
6055 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6056 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6057 {
29b0f896
AM		 6058 prefix++;
6059 i.prefixes--;
6060 }
6061 if (i.prefix[REX_PREFIX] != 0)
6062 {
6063 prefix++;
6064 i.prefixes--;
2f66722d
AM		 6065 }
6066
29b0f896
AM		 6067 if (i.prefixes != 0 && !intel_syntax)
6068 as_warn (_("skipping prefixes on this instruction"));
6069
6070 /* It's always a symbol; End frag & setup for relax.
6071 Make sure there is enough room in this frag for the largest
6072 instruction we may generate in md_convert_frag. This is 2
6073 bytes for the opcode and room for the prefix and largest
6074 displacement. */
6075 frag_grow (prefix + 2 + 4);
6076 /* Prefix and 1 opcode byte go in fr_fix. */
6077 p = frag_more (prefix + 1);
6078 if (i.prefix[DATA_PREFIX] != 0)
6079 *p++ = DATA_PREFIX_OPCODE;
6080 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6081 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6082 *p++ = i.prefix[SEG_PREFIX];
6083 if (i.prefix[REX_PREFIX] != 0)
6084 *p++ = i.prefix[REX_PREFIX];
6085 *p = i.tm.base_opcode;
6086
6087 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6088 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6089 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6090 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6091 else
f8a5c266 6092 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6093 subtype |= code16;
3e73aa7c 6094
29b0f896
AM		 6095 sym = i.op[0].disps->X_add_symbol;
6096 off = i.op[0].disps->X_add_number;
3e73aa7c 6097
29b0f896
AM		 6098 if (i.op[0].disps->X_op != O_constant
6099 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6100 {
29b0f896
AM		 6101 /* Handle complex expressions. */
6102 sym = make_expr_symbol (i.op[0].disps);
6103 off = 0;
6104 }
3e73aa7c 6105
29b0f896
AM		 6106 /* 1 possible extra opcode + 4 byte displacement go in var part.
6107 Pass reloc in fr_var. */
6108 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6109}
3e73aa7c 6110
29b0f896 6111static void
e3bb37b5 6112output_jump (void)
29b0f896
AM		 6113{
6114 char *p;
6115 int size;
3e02c1cc 6116 fixS *fixP;
29b0f896 6117
40fb9820 6118 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6119 {
6120 /* This is a loop or jecxz type instruction. */
6121 size = 1;
6122 if (i.prefix[ADDR_PREFIX] != 0)
6123 {
6124 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6125 i.prefixes -= 1;
6126 }
6127 /* Pentium4 branch hints. */
6128 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6129 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6130 {
6131 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6132 i.prefixes--;
3e73aa7c
JH		 6133 }
6134 }
29b0f896
AM		 6135 else
6136 {
6137 int code16;
3e73aa7c 6138
29b0f896
AM		 6139 code16 = 0;
6140 if (flag_code == CODE_16BIT)
6141 code16 = CODE16;
3e73aa7c 6142
29b0f896
AM		 6143 if (i.prefix[DATA_PREFIX] != 0)
6144 {
6145 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6146 i.prefixes -= 1;
6147 code16 ^= CODE16;
6148 }
252b5132 6149
29b0f896
AM		 6150 size = 4;
6151 if (code16)
6152 size = 2;
6153 }
9fcc94b6 6154
29b0f896
AM		 6155 if (i.prefix[REX_PREFIX] != 0)
6156 {
6157 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6158 i.prefixes -= 1;
6159 }
252b5132 6160
29b0f896
AM		 6161 if (i.prefixes != 0 && !intel_syntax)
6162 as_warn (_("skipping prefixes on this instruction"));
e0890092 6163
42164a71
L		 6164 p = frag_more (i.tm.opcode_length + size);
6165 switch (i.tm.opcode_length)
6166 {
6167 case 2:
6168 *p++ = i.tm.base_opcode >> 8;
6169 case 1:
6170 *p++ = i.tm.base_opcode;
6171 break;
6172 default:
6173 abort ();
6174 }
e0890092 6175
3e02c1cc
AM		 6176 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6177 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6178
6179 /* All jumps handled here are signed, but don't use a signed limit
6180 check for 32 and 16 bit jumps as we want to allow wrap around at
6181 4G and 64k respectively. */
6182 if (size == 1)
6183 fixP->fx_signed = 1;
29b0f896 6184}
e0890092 6185
29b0f896 6186static void
e3bb37b5 6187output_interseg_jump (void)
29b0f896
AM		 6188{
6189 char *p;
6190 int size;
6191 int prefix;
6192 int code16;
252b5132 6193
29b0f896
AM		 6194 code16 = 0;
6195 if (flag_code == CODE_16BIT)
6196 code16 = CODE16;
a217f122 6197
29b0f896
AM		 6198 prefix = 0;
6199 if (i.prefix[DATA_PREFIX] != 0)
6200 {
6201 prefix = 1;
6202 i.prefixes -= 1;
6203 code16 ^= CODE16;
6204 }
6205 if (i.prefix[REX_PREFIX] != 0)
6206 {
6207 prefix++;
6208 i.prefixes -= 1;
6209 }
252b5132 6210
29b0f896
AM		 6211 size = 4;
6212 if (code16)
6213 size = 2;
252b5132 6214
29b0f896
AM		 6215 if (i.prefixes != 0 && !intel_syntax)
6216 as_warn (_("skipping prefixes on this instruction"));
252b5132 6217
29b0f896
AM		 6218 /* 1 opcode; 2 segment; offset */
6219 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6220
29b0f896
AM		 6221 if (i.prefix[DATA_PREFIX] != 0)
6222 *p++ = DATA_PREFIX_OPCODE;
252b5132 6223
29b0f896
AM		 6224 if (i.prefix[REX_PREFIX] != 0)
6225 *p++ = i.prefix[REX_PREFIX];
252b5132 6226
29b0f896
AM		 6227 *p++ = i.tm.base_opcode;
6228 if (i.op[1].imms->X_op == O_constant)
6229 {
6230 offsetT n = i.op[1].imms->X_add_number;
252b5132 6231
29b0f896
AM		 6232 if (size == 2
6233 && !fits_in_unsigned_word (n)
6234 && !fits_in_signed_word (n))
6235 {
6236 as_bad (_("16-bit jump out of range"));
6237 return;
6238 }
6239 md_number_to_chars (p, n, size);
6240 }
6241 else
6242 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6243 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6244 if (i.op[0].imms->X_op != O_constant)
6245 as_bad (_("can't handle non absolute segment in `%s'"),
6246 i.tm.name);
6247 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6248}
a217f122 6249
29b0f896 6250static void
e3bb37b5 6251output_insn (void)
29b0f896 6252{
2bbd9c25
JJ		 6253 fragS *insn_start_frag;
6254 offsetT insn_start_off;
6255
29b0f896
AM		 6256 /* Tie dwarf2 debug info to the address at the start of the insn.
6257 We can't do this after the insn has been output as the current
6258 frag may have been closed off. eg. by frag_var. */
6259 dwarf2_emit_insn (0);
6260
2bbd9c25
JJ		 6261 insn_start_frag = frag_now;
6262 insn_start_off = frag_now_fix ();
6263
29b0f896 6264 /* Output jumps. */
40fb9820 6265 if (i.tm.opcode_modifier.jump)
29b0f896 6266 output_branch ();
40fb9820
L		 6267 else if (i.tm.opcode_modifier.jumpbyte
6268 || i.tm.opcode_modifier.jumpdword)
29b0f896 6269 output_jump ();
40fb9820 6270 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6271 output_interseg_jump ();
6272 else
6273 {
6274 /* Output normal instructions here. */
6275 char *p;
6276 unsigned char *q;
47465058 6277 unsigned int j;
331d2d0d 6278 unsigned int prefix;
4dffcebc 6279
c0f3af97 6280 /* Since the VEX prefix contains the implicit prefix, we don't
89e71f5c 6281 need the explicit prefix. */
c0f3af97 6282 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6283 {
c0f3af97 6284 switch (i.tm.opcode_length)
bc4bd9ab 6285 {
c0f3af97
L		 6286 case 3:
6287 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6288 {
c0f3af97
L		 6289 prefix = (i.tm.base_opcode >> 24) & 0xff;
6290 goto check_prefix;
6291 }
6292 break;
6293 case 2:
6294 if ((i.tm.base_opcode & 0xff0000) != 0)
6295 {
6296 prefix = (i.tm.base_opcode >> 16) & 0xff;
6297 if (i.tm.cpu_flags.bitfield.cpupadlock)
6298 {
4dffcebc 6299check_prefix:
c0f3af97 6300 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6301 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6302 != REPE_PREFIX_OPCODE))
6303 add_prefix (prefix);
6304 }
6305 else
4dffcebc
L		 6306 add_prefix (prefix);
6307 }
c0f3af97
L		 6308 break;
6309 case 1:
6310 break;
6311 default:
6312 abort ();
bc4bd9ab 6313 }
c0f3af97
L		 6314
6315 /* The prefix bytes. */
6316 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6317 if (*q)
6318 FRAG_APPEND_1_CHAR (*q);
0f10071e 6319 }
ae5c1c7b 6320 else
c0f3af97
L		 6321 {
6322 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6323 if (*q)
6324 switch (j)
6325 {
6326 case REX_PREFIX:
6327 /* REX byte is encoded in VEX prefix. */
6328 break;
6329 case SEG_PREFIX:
6330 case ADDR_PREFIX:
6331 FRAG_APPEND_1_CHAR (*q);
6332 break;
6333 default:
6334 /* There should be no other prefixes for instructions
6335 with VEX prefix. */
6336 abort ();
6337 }
6338
6339 /* Now the VEX prefix. */
6340 p = frag_more (i.vex.length);
6341 for (j = 0; j < i.vex.length; j++)
6342 p[j] = i.vex.bytes[j];
6343 }
252b5132 6344
29b0f896 6345 /* Now the opcode; be careful about word order here! */
4dffcebc 6346 if (i.tm.opcode_length == 1)
29b0f896
AM		 6347 {
6348 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6349 }
6350 else
6351 {
4dffcebc 6352 switch (i.tm.opcode_length)
331d2d0d 6353 {
4dffcebc 6354 case 3:
331d2d0d
L		 6355 p = frag_more (3);
6356 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6357 break;
6358 case 2:
6359 p = frag_more (2);
6360 break;
6361 default:
6362 abort ();
6363 break;
331d2d0d 6364 }
0f10071e 6365
29b0f896
AM		 6366 /* Put out high byte first: can't use md_number_to_chars! */
6367 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6368 *p = i.tm.base_opcode & 0xff;
6369 }
3e73aa7c 6370
29b0f896 6371 /* Now the modrm byte and sib byte (if present). */
40fb9820 6372 if (i.tm.opcode_modifier.modrm)
29b0f896 6373 {
4a3523fa
L		 6374 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6375 | i.rm.reg << 3
6376 | i.rm.mode << 6));
29b0f896
AM		 6377 /* If i.rm.regmem == ESP (4)
6378 && i.rm.mode != (Register mode)
6379 && not 16 bit
6380 ==> need second modrm byte. */
6381 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6382 && i.rm.mode != 3
40fb9820 6383 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6384 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6385 | i.sib.index << 3
6386 | i.sib.scale << 6));
29b0f896 6387 }
3e73aa7c 6388
29b0f896 6389 if (i.disp_operands)
2bbd9c25 6390 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6391
29b0f896 6392 if (i.imm_operands)
2bbd9c25 6393 output_imm (insn_start_frag, insn_start_off);
29b0f896 6394 }
252b5132 6395
29b0f896
AM		 6396#ifdef DEBUG386
6397 if (flag_debug)
6398 {
7b81dfbb 6399 pi ("" /*line*/, &i);
29b0f896
AM		 6400 }
6401#endif /* DEBUG386 */
6402}
252b5132 6403
e205caa7
L		 6404/* Return the size of the displacement operand N. */
6405
6406static int
6407disp_size (unsigned int n)
6408{
6409 int size = 4;
40fb9820
L		 6410 if (i.types[n].bitfield.disp64)
6411 size = 8;
6412 else if (i.types[n].bitfield.disp8)
6413 size = 1;
6414 else if (i.types[n].bitfield.disp16)
6415 size = 2;
e205caa7
L		 6416 return size;
6417}
6418
6419/* Return the size of the immediate operand N. */
6420
6421static int
6422imm_size (unsigned int n)
6423{
6424 int size = 4;
40fb9820
L		 6425 if (i.types[n].bitfield.imm64)
6426 size = 8;
6427 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6428 size = 1;
6429 else if (i.types[n].bitfield.imm16)
6430 size = 2;
e205caa7
L		 6431 return size;
6432}
6433
29b0f896 6434static void
64e74474 6435output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6436{
6437 char *p;
6438 unsigned int n;
252b5132 6439
29b0f896
AM		 6440 for (n = 0; n < i.operands; n++)
6441 {
40fb9820 6442 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6443 {
6444 if (i.op[n].disps->X_op == O_constant)
6445 {
e205caa7 6446 int size = disp_size (n);
29b0f896 6447 offsetT val;
252b5132 6448
29b0f896
AM		 6449 val = offset_in_range (i.op[n].disps->X_add_number,
6450 size);
6451 p = frag_more (size);
6452 md_number_to_chars (p, val, size);
6453 }
6454 else
6455 {
f86103b7 6456 enum bfd_reloc_code_real reloc_type;
e205caa7 6457 int size = disp_size (n);
40fb9820 6458 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6459 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6460
e205caa7 6461 /* We can't have 8 bit displacement here. */
9c2799c2 6462 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6463
29b0f896
AM		 6464 /* The PC relative address is computed relative
6465 to the instruction boundary, so in case immediate
6466 fields follows, we need to adjust the value. */
6467 if (pcrel && i.imm_operands)
6468 {
29b0f896 6469 unsigned int n1;
e205caa7 6470 int sz = 0;
252b5132 6471
29b0f896 6472 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6473 if (operand_type_check (i.types[n1], imm))
252b5132 6474 {
e205caa7
L		 6475 /* Only one immediate is allowed for PC
6476 relative address. */
9c2799c2 6477 gas_assert (sz == 0);
e205caa7
L		 6478 sz = imm_size (n1);
6479 i.op[n].disps->X_add_number -= sz;
252b5132 6480 }
29b0f896 6481 /* We should find the immediate. */
9c2799c2 6482 gas_assert (sz != 0);
29b0f896 6483 }
520dc8e8 6484
29b0f896 6485 p = frag_more (size);
2bbd9c25 6486 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6487 if (GOT_symbol
2bbd9c25 6488 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6489 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6490 || reloc_type == BFD_RELOC_X86_64_32S
6491 || (reloc_type == BFD_RELOC_64
6492 && object_64bit))
d6ab8113
JB		 6493 && (i.op[n].disps->X_op == O_symbol
6494 || (i.op[n].disps->X_op == O_add
6495 && ((symbol_get_value_expression
6496 (i.op[n].disps->X_op_symbol)->X_op)
6497 == O_subtract))))
6498 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6499 {
6500 offsetT add;
6501
6502 if (insn_start_frag == frag_now)
6503 add = (p - frag_now->fr_literal) - insn_start_off;
6504 else
6505 {
6506 fragS *fr;
6507
6508 add = insn_start_frag->fr_fix - insn_start_off;
6509 for (fr = insn_start_frag->fr_next;
6510 fr && fr != frag_now; fr = fr->fr_next)
6511 add += fr->fr_fix;
6512 add += p - frag_now->fr_literal;
6513 }
6514
4fa24527 6515 if (!object_64bit)
7b81dfbb
AJ		 6516 {
6517 reloc_type = BFD_RELOC_386_GOTPC;
6518 i.op[n].imms->X_add_number += add;
6519 }
6520 else if (reloc_type == BFD_RELOC_64)
6521 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6522 else
7b81dfbb
AJ		 6523 /* Don't do the adjustment for x86-64, as there
6524 the pcrel addressing is relative to the _next_
6525 insn, and that is taken care of in other code. */
d6ab8113 6526 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6527 }
062cd5e7 6528 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6529 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6530 }
6531 }
6532 }
6533}
252b5132 6534
29b0f896 6535static void
64e74474 6536output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6537{
6538 char *p;
6539 unsigned int n;
252b5132 6540
29b0f896
AM		 6541 for (n = 0; n < i.operands; n++)
6542 {
40fb9820 6543 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6544 {
6545 if (i.op[n].imms->X_op == O_constant)
6546 {
e205caa7 6547 int size = imm_size (n);
29b0f896 6548 offsetT val;
b4cac588 6549
29b0f896
AM		 6550 val = offset_in_range (i.op[n].imms->X_add_number,
6551 size);
6552 p = frag_more (size);
6553 md_number_to_chars (p, val, size);
6554 }
6555 else
6556 {
6557 /* Not absolute_section.
6558 Need a 32-bit fixup (don't support 8bit
6559 non-absolute imms). Try to support other
6560 sizes ... */
f86103b7 6561 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6562 int size = imm_size (n);
6563 int sign;
29b0f896 6564
40fb9820 6565 if (i.types[n].bitfield.imm32s
a7d61044 6566 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6567 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6568 sign = 1;
e205caa7
L		 6569 else
6570 sign = 0;
520dc8e8 6571
29b0f896
AM		 6572 p = frag_more (size);
6573 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6574
2bbd9c25
JJ		 6575 /* This is tough to explain. We end up with this one if we
6576 * have operands that look like
6577 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6578 * obtain the absolute address of the GOT, and it is strongly
6579 * preferable from a performance point of view to avoid using
6580 * a runtime relocation for this. The actual sequence of
6581 * instructions often look something like:
6582 *
6583 * call .L66
6584 * .L66:
6585 * popl %ebx
6586 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6587 *
6588 * The call and pop essentially return the absolute address
6589 * of the label .L66 and store it in %ebx. The linker itself
6590 * will ultimately change the first operand of the addl so
6591 * that %ebx points to the GOT, but to keep things simple, the
6592 * .o file must have this operand set so that it generates not
6593 * the absolute address of .L66, but the absolute address of
6594 * itself. This allows the linker itself simply treat a GOTPC
6595 * relocation as asking for a pcrel offset to the GOT to be
6596 * added in, and the addend of the relocation is stored in the
6597 * operand field for the instruction itself.
6598 *
6599 * Our job here is to fix the operand so that it would add
6600 * the correct offset so that %ebx would point to itself. The
6601 * thing that is tricky is that .-.L66 will point to the
6602 * beginning of the instruction, so we need to further modify
6603 * the operand so that it will point to itself. There are
6604 * other cases where you have something like:
6605 *
6606 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6607 *
6608 * and here no correction would be required. Internally in
6609 * the assembler we treat operands of this form as not being
6610 * pcrel since the '.' is explicitly mentioned, and I wonder
6611 * whether it would simplify matters to do it this way. Who
6612 * knows. In earlier versions of the PIC patches, the
6613 * pcrel_adjust field was used to store the correction, but
6614 * since the expression is not pcrel, I felt it would be
6615 * confusing to do it this way. */
6616
d6ab8113 6617 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6618 || reloc_type == BFD_RELOC_X86_64_32S
6619 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6620 && GOT_symbol
6621 && GOT_symbol == i.op[n].imms->X_add_symbol
6622 && (i.op[n].imms->X_op == O_symbol
6623 || (i.op[n].imms->X_op == O_add
6624 && ((symbol_get_value_expression
6625 (i.op[n].imms->X_op_symbol)->X_op)
6626 == O_subtract))))
6627 {
2bbd9c25
JJ		 6628 offsetT add;
6629
6630 if (insn_start_frag == frag_now)
6631 add = (p - frag_now->fr_literal) - insn_start_off;
6632 else
6633 {
6634 fragS *fr;
6635
6636 add = insn_start_frag->fr_fix - insn_start_off;
6637 for (fr = insn_start_frag->fr_next;
6638 fr && fr != frag_now; fr = fr->fr_next)
6639 add += fr->fr_fix;
6640 add += p - frag_now->fr_literal;
6641 }
6642
4fa24527 6643 if (!object_64bit)
d6ab8113 6644 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6645 else if (size == 4)
d6ab8113 6646 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6647 else if (size == 8)
6648 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6649 i.op[n].imms->X_add_number += add;
29b0f896 6650 }
29b0f896
AM		 6651 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6652 i.op[n].imms, 0, reloc_type);
6653 }
6654 }
6655 }
252b5132
RH		 6656}
6657\f
d182319b
JB		 6658/* x86_cons_fix_new is called via the expression parsing code when a
6659 reloc is needed. We use this hook to get the correct .got reloc. */
6660static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6661static int cons_sign = -1;
6662
6663void
e3bb37b5 6664x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6665 expressionS *exp)
d182319b
JB		 6666{
6667 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6668
6669 got_reloc = NO_RELOC;
6670
6671#ifdef TE_PE
6672 if (exp->X_op == O_secrel)
6673 {
6674 exp->X_op = O_symbol;
6675 r = BFD_RELOC_32_SECREL;
6676 }
6677#endif
6678
6679 fix_new_exp (frag, off, len, exp, 0, r);
6680}
6681
357d1bd8
L		 6682/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6683 purpose of the `.dc.a' internal pseudo-op. */
6684
6685int
6686x86_address_bytes (void)
6687{
6688 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
6689 return 4;
6690 return stdoutput->arch_info->bits_per_address / 8;
6691}
6692
d382c579
TG		 6693#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6694 || defined (LEX_AT)
718ddfc0
JB		 6695# define lex_got(reloc, adjust, types) NULL
6696#else
f3c180ae
AM		 6697/* Parse operands of the form
6698 <symbol>@GOTOFF+<nnn>
6699 and similar .plt or .got references.
6700
6701 If we find one, set up the correct relocation in RELOC and copy the
6702 input string, minus the `@GOTOFF' into a malloc'd buffer for
6703 parsing by the calling routine. Return this buffer, and if ADJUST
6704 is non-null set it to the length of the string we removed from the
6705 input line. Otherwise return NULL. */
6706static char *
91d6fa6a 6707lex_got (enum bfd_reloc_code_real *rel,
64e74474 6708 int *adjust,
40fb9820 6709 i386_operand_type *types)
f3c180ae 6710{
7b81dfbb
AJ		 6711 /* Some of the relocations depend on the size of what field is to
6712 be relocated. But in our callers i386_immediate and i386_displacement
6713 we don't yet know the operand size (this will be set by insn
6714 matching). Hence we record the word32 relocation here,
6715 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6716 static const struct {
6717 const char *str;
cff8d58a 6718 int len;
4fa24527 6719 const enum bfd_reloc_code_real rel[2];
40fb9820 6720 const i386_operand_type types64;
f3c180ae 6721 } gotrel[] = {
8fd4256d
L		 6722 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
6723 BFD_RELOC_SIZE32 },
6724 OPERAND_TYPE_IMM32_64 },
cff8d58a
L		 6725 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6726 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6727 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6728 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6729 BFD_RELOC_X86_64_PLT32 },
40fb9820 6730 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6731 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6732 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6733 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6734 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6735 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6736 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6737 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6738 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6739 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6740 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6741 BFD_RELOC_X86_64_TLSGD },
40fb9820 6742 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6743 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6744 _dummy_first_bfd_reloc_code_real },
40fb9820 6745 OPERAND_TYPE_NONE },
cff8d58a
L		 6746 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6747 BFD_RELOC_X86_64_TLSLD },
40fb9820 6748 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6749 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6750 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6751 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6752 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6753 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6754 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6755 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6756 _dummy_first_bfd_reloc_code_real },
40fb9820 6757 OPERAND_TYPE_NONE },
cff8d58a
L		 6758 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6759 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6760 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6761 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6762 _dummy_first_bfd_reloc_code_real },
40fb9820 6763 OPERAND_TYPE_NONE },
cff8d58a
L		 6764 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6765 _dummy_first_bfd_reloc_code_real },
40fb9820 6766 OPERAND_TYPE_NONE },
cff8d58a
L		 6767 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6768 BFD_RELOC_X86_64_GOT32 },
40fb9820 6769 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6770 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6771 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6772 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6773 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6774 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6775 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6776 };
6777 char *cp;
6778 unsigned int j;
6779
d382c579 6780#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 6781 if (!IS_ELF)
6782 return NULL;
d382c579 6783#endif
718ddfc0 6784
f3c180ae 6785 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6786 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6787 return NULL;
6788
47465058 6789 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6790 {
cff8d58a 6791 int len = gotrel[j].len;
28f81592 6792 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6793 {
4fa24527 6794 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6795 {
28f81592
AM		 6796 int first, second;
6797 char *tmpbuf, *past_reloc;
f3c180ae 6798
91d6fa6a 6799 *rel = gotrel[j].rel[object_64bit];
f3c180ae 6800
3956db08
JB		 6801 if (types)
6802 {
6803 if (flag_code != CODE_64BIT)
40fb9820
L		 6804 {
6805 types->bitfield.imm32 = 1;
6806 types->bitfield.disp32 = 1;
6807 }
3956db08
JB		 6808 else
6809 *types = gotrel[j].types64;
6810 }
6811
8fd4256d 6812 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 6813 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6814
28f81592 6815 /* The length of the first part of our input line. */
f3c180ae 6816 first = cp - input_line_pointer;
28f81592
AM		 6817
6818 /* The second part goes from after the reloc token until
67c11a9b 6819 (and including) an end_of_line char or comma. */
28f81592 6820 past_reloc = cp + 1 + len;
67c11a9b
AM		 6821 cp = past_reloc;
6822 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6823 ++cp;
6824 second = cp + 1 - past_reloc;
28f81592
AM		 6825
6826 /* Allocate and copy string. The trailing NUL shouldn't
6827 be necessary, but be safe. */
1e9cc1c2 6828 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6829 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6830 if (second != 0 && *past_reloc != ' ')
6831 /* Replace the relocation token with ' ', so that
6832 errors like foo@GOTOFF1 will be detected. */
6833 tmpbuf[first++] = ' ';
af89796a
L		 6834 else
6835 /* Increment length by 1 if the relocation token is
6836 removed. */
6837 len++;
6838 if (adjust)
6839 *adjust = len;
0787a12d
AM		 6840 memcpy (tmpbuf + first, past_reloc, second);
6841 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6842 return tmpbuf;
6843 }
6844
4fa24527
JB		 6845 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6846 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6847 return NULL;
6848 }
6849 }
6850
6851 /* Might be a symbol version string. Don't as_bad here. */
6852 return NULL;
6853}
4e4f7c87 6854#endif
f3c180ae 6855
a988325c
NC		 6856#ifdef TE_PE
6857#ifdef lex_got
6858#undef lex_got
6859#endif
6860/* Parse operands of the form
6861 <symbol>@SECREL32+<nnn>
6862
6863 If we find one, set up the correct relocation in RELOC and copy the
6864 input string, minus the `@SECREL32' into a malloc'd buffer for
6865 parsing by the calling routine. Return this buffer, and if ADJUST
6866 is non-null set it to the length of the string we removed from the
34bca508
L		 6867 input line. Otherwise return NULL.
6868
a988325c
NC		 6869 This function is copied from the ELF version above adjusted for PE targets. */
6870
6871static char *
6872lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
6873 int *adjust ATTRIBUTE_UNUSED,
6874 i386_operand_type *types ATTRIBUTE_UNUSED)
6875{
6876 static const struct
6877 {
6878 const char *str;
6879 int len;
6880 const enum bfd_reloc_code_real rel[2];
6881 const i386_operand_type types64;
6882 }
6883 gotrel[] =
6884 {
6885 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
6886 BFD_RELOC_32_SECREL },
6887 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6888 };
6889
6890 char *cp;
6891 unsigned j;
6892
6893 for (cp = input_line_pointer; *cp != '@'; cp++)
6894 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6895 return NULL;
6896
6897 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6898 {
6899 int len = gotrel[j].len;
6900
6901 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6902 {
6903 if (gotrel[j].rel[object_64bit] != 0)
6904 {
6905 int first, second;
6906 char *tmpbuf, *past_reloc;
6907
6908 *rel = gotrel[j].rel[object_64bit];
6909 if (adjust)
6910 *adjust = len;
6911
6912 if (types)
6913 {
6914 if (flag_code != CODE_64BIT)
6915 {
6916 types->bitfield.imm32 = 1;
6917 types->bitfield.disp32 = 1;
6918 }
6919 else
6920 *types = gotrel[j].types64;
6921 }
6922
6923 /* The length of the first part of our input line. */
6924 first = cp - input_line_pointer;
6925
6926 /* The second part goes from after the reloc token until
6927 (and including) an end_of_line char or comma. */
6928 past_reloc = cp + 1 + len;
6929 cp = past_reloc;
6930 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6931 ++cp;
6932 second = cp + 1 - past_reloc;
6933
6934 /* Allocate and copy string. The trailing NUL shouldn't
6935 be necessary, but be safe. */
6936 tmpbuf = (char *) xmalloc (first + second + 2);
6937 memcpy (tmpbuf, input_line_pointer, first);
6938 if (second != 0 && *past_reloc != ' ')
6939 /* Replace the relocation token with ' ', so that
6940 errors like foo@SECLREL321 will be detected. */
6941 tmpbuf[first++] = ' ';
6942 memcpy (tmpbuf + first, past_reloc, second);
6943 tmpbuf[first + second] = '\0';
6944 return tmpbuf;
6945 }
6946
6947 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6948 gotrel[j].str, 1 << (5 + object_64bit));
6949 return NULL;
6950 }
6951 }
6952
6953 /* Might be a symbol version string. Don't as_bad here. */
6954 return NULL;
6955}
6956
6957#endif /* TE_PE */
6958
f3c180ae 6959void
e3bb37b5 6960x86_cons (expressionS *exp, int size)
f3c180ae 6961{
ee86248c
JB		 6962 intel_syntax = -intel_syntax;
6963
3c7b9c2c 6964 exp->X_md = 0;
4fa24527 6965 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6966 {
6967 /* Handle @GOTOFF and the like in an expression. */
6968 char *save;
6969 char *gotfree_input_line;
4a57f2cf 6970 int adjust = 0;
f3c180ae
AM		 6971
6972 save = input_line_pointer;
3956db08 6973 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6974 if (gotfree_input_line)
6975 input_line_pointer = gotfree_input_line;
6976
6977 expression (exp);
6978
6979 if (gotfree_input_line)
6980 {
6981 /* expression () has merrily parsed up to the end of line,
6982 or a comma - in the wrong buffer. Transfer how far
6983 input_line_pointer has moved to the right buffer. */
6984 input_line_pointer = (save
6985 + (input_line_pointer - gotfree_input_line)
6986 + adjust);
6987 free (gotfree_input_line);
3992d3b7
AM		 6988 if (exp->X_op == O_constant
6989 || exp->X_op == O_absent
6990 || exp->X_op == O_illegal
0398aac5 6991 || exp->X_op == O_register
3992d3b7
AM		 6992 || exp->X_op == O_big)
6993 {
6994 char c = *input_line_pointer;
6995 *input_line_pointer = 0;
6996 as_bad (_("missing or invalid expression `%s'"), save);
6997 *input_line_pointer = c;
6998 }
f3c180ae
AM		 6999 }
7000 }
7001 else
7002 expression (exp);
ee86248c
JB		 7003
7004 intel_syntax = -intel_syntax;
7005
7006 if (intel_syntax)
7007 i386_intel_simplify (exp);
f3c180ae 7008}
f3c180ae 7009
9f32dd5b
L		 7010static void
7011signed_cons (int size)
6482c264 7012{
d182319b
JB		 7013 if (flag_code == CODE_64BIT)
7014 cons_sign = 1;
7015 cons (size);
7016 cons_sign = -1;
6482c264
NC		 7017}
7018
d182319b 7019#ifdef TE_PE
6482c264 7020static void
7016a5d5 7021pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7022{
7023 expressionS exp;
7024
7025 do
7026 {
7027 expression (&exp);
7028 if (exp.X_op == O_symbol)
7029 exp.X_op = O_secrel;
7030
7031 emit_expr (&exp, 4);
7032 }
7033 while (*input_line_pointer++ == ',');
7034
7035 input_line_pointer--;
7036 demand_empty_rest_of_line ();
7037}
6482c264
NC		 7038#endif
7039
252b5132 7040static int
70e41ade 7041i386_immediate (char *imm_start)
252b5132
RH		 7042{
7043 char *save_input_line_pointer;
f3c180ae 7044 char *gotfree_input_line;
252b5132 7045 segT exp_seg = 0;
47926f60 7046 expressionS *exp;
40fb9820
L		 7047 i386_operand_type types;
7048
0dfbf9d7 7049 operand_type_set (&types, ~0);
252b5132
RH		 7050
7051 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7052 {
31b2323c
L		 7053 as_bad (_("at most %d immediate operands are allowed"),
7054 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7055 return 0;
7056 }
7057
7058 exp = &im_expressions[i.imm_operands++];
520dc8e8 7059 i.op[this_operand].imms = exp;
252b5132
RH		 7060
7061 if (is_space_char (*imm_start))
7062 ++imm_start;
7063
7064 save_input_line_pointer = input_line_pointer;
7065 input_line_pointer = imm_start;
7066
3956db08 7067 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7068 if (gotfree_input_line)
7069 input_line_pointer = gotfree_input_line;
252b5132
RH		 7070
7071 exp_seg = expression (exp);
7072
83183c0c 7073 SKIP_WHITESPACE ();
252b5132 7074 if (*input_line_pointer)
f3c180ae 7075 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7076
7077 input_line_pointer = save_input_line_pointer;
f3c180ae 7078 if (gotfree_input_line)
ee86248c
JB		 7079 {
7080 free (gotfree_input_line);
7081
7082 if (exp->X_op == O_constant || exp->X_op == O_register)
7083 exp->X_op = O_illegal;
7084 }
7085
7086 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7087}
252b5132 7088
ee86248c
JB		 7089static int
7090i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7091 i386_operand_type types, const char *imm_start)
7092{
7093 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7094 {
313c53d1
L		 7095 if (imm_start)
7096 as_bad (_("missing or invalid immediate expression `%s'"),
7097 imm_start);
3992d3b7 7098 return 0;
252b5132 7099 }
3e73aa7c 7100 else if (exp->X_op == O_constant)
252b5132 7101 {
47926f60 7102 /* Size it properly later. */
40fb9820 7103 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7104 /* If not 64bit, sign extend val. */
7105 if (flag_code != CODE_64BIT
4eed87de
AM		 7106 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7107 exp->X_add_number
7108 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7109 }
4c63da97 7110#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7111 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7112 && exp_seg != absolute_section
47926f60 7113 && exp_seg != text_section
24eab124
AM		 7114 && exp_seg != data_section
7115 && exp_seg != bss_section
7116 && exp_seg != undefined_section
f86103b7 7117 && !bfd_is_com_section (exp_seg))
252b5132 7118 {
d0b47220 7119 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7120 return 0;
7121 }
7122#endif
bb8f5920
L		 7123 else if (!intel_syntax && exp->X_op == O_register)
7124 {
313c53d1
L		 7125 if (imm_start)
7126 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7127 return 0;
7128 }
252b5132
RH		 7129 else
7130 {
7131 /* This is an address. The size of the address will be
24eab124 7132 determined later, depending on destination register,
3e73aa7c 7133 suffix, or the default for the section. */
40fb9820
L		 7134 i.types[this_operand].bitfield.imm8 = 1;
7135 i.types[this_operand].bitfield.imm16 = 1;
7136 i.types[this_operand].bitfield.imm32 = 1;
7137 i.types[this_operand].bitfield.imm32s = 1;
7138 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7139 i.types[this_operand] = operand_type_and (i.types[this_operand],
7140 types);
252b5132
RH		 7141 }
7142
7143 return 1;
7144}
7145
551c1ca1 7146static char *
e3bb37b5 7147i386_scale (char *scale)
252b5132 7148{
551c1ca1
AM		 7149 offsetT val;
7150 char *save = input_line_pointer;
252b5132 7151
551c1ca1
AM		 7152 input_line_pointer = scale;
7153 val = get_absolute_expression ();
7154
7155 switch (val)
252b5132 7156 {
551c1ca1 7157 case 1:
252b5132
RH		 7158 i.log2_scale_factor = 0;
7159 break;
551c1ca1 7160 case 2:
252b5132
RH		 7161 i.log2_scale_factor = 1;
7162 break;
551c1ca1 7163 case 4:
252b5132
RH		 7164 i.log2_scale_factor = 2;
7165 break;
551c1ca1 7166 case 8:
252b5132
RH		 7167 i.log2_scale_factor = 3;
7168 break;
7169 default:
a724f0f4
JB		 7170 {
7171 char sep = *input_line_pointer;
7172
7173 *input_line_pointer = '\0';
7174 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7175 scale);
7176 *input_line_pointer = sep;
7177 input_line_pointer = save;
7178 return NULL;
7179 }
252b5132 7180 }
29b0f896 7181 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7182 {
7183 as_warn (_("scale factor of %d without an index register"),
24eab124 7184 1 << i.log2_scale_factor);
252b5132 7185 i.log2_scale_factor = 0;
252b5132 7186 }
551c1ca1
AM		 7187 scale = input_line_pointer;
7188 input_line_pointer = save;
7189 return scale;
252b5132
RH		 7190}
7191
252b5132 7192static int
e3bb37b5 7193i386_displacement (char *disp_start, char *disp_end)
252b5132 7194{
29b0f896 7195 expressionS *exp;
252b5132
RH		 7196 segT exp_seg = 0;
7197 char *save_input_line_pointer;
f3c180ae 7198 char *gotfree_input_line;
40fb9820
L		 7199 int override;
7200 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7201 int ret;
252b5132 7202
31b2323c
L		 7203 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7204 {
7205 as_bad (_("at most %d displacement operands are allowed"),
7206 MAX_MEMORY_OPERANDS);
7207 return 0;
7208 }
7209
0dfbf9d7 7210 operand_type_set (&bigdisp, 0);
40fb9820
L		 7211 if ((i.types[this_operand].bitfield.jumpabsolute)
7212 || (!current_templates->start->opcode_modifier.jump
7213 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7214 {
40fb9820 7215 bigdisp.bitfield.disp32 = 1;
e05278af 7216 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7217 if (flag_code == CODE_64BIT)
7218 {
7219 if (!override)
7220 {
7221 bigdisp.bitfield.disp32s = 1;
7222 bigdisp.bitfield.disp64 = 1;
7223 }
7224 }
7225 else if ((flag_code == CODE_16BIT) ^ override)
7226 {
7227 bigdisp.bitfield.disp32 = 0;
7228 bigdisp.bitfield.disp16 = 1;
7229 }
e05278af
JB		 7230 }
7231 else
7232 {
7233 /* For PC-relative branches, the width of the displacement
7234 is dependent upon data size, not address size. */
e05278af 7235 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 7236 if (flag_code == CODE_64BIT)
7237 {
7238 if (override || i.suffix == WORD_MNEM_SUFFIX)
7239 bigdisp.bitfield.disp16 = 1;
7240 else
7241 {
7242 bigdisp.bitfield.disp32 = 1;
7243 bigdisp.bitfield.disp32s = 1;
7244 }
7245 }
7246 else
e05278af
JB		 7247 {
7248 if (!override)
7249 override = (i.suffix == (flag_code != CODE_16BIT
7250 ? WORD_MNEM_SUFFIX
7251 : LONG_MNEM_SUFFIX));
40fb9820
L		 7252 bigdisp.bitfield.disp32 = 1;
7253 if ((flag_code == CODE_16BIT) ^ override)
7254 {
7255 bigdisp.bitfield.disp32 = 0;
7256 bigdisp.bitfield.disp16 = 1;
7257 }
e05278af 7258 }
e05278af 7259 }
c6fb90c8
L		 7260 i.types[this_operand] = operand_type_or (i.types[this_operand],
7261 bigdisp);
252b5132
RH		 7262
7263 exp = &disp_expressions[i.disp_operands];
520dc8e8 7264 i.op[this_operand].disps = exp;
252b5132
RH		 7265 i.disp_operands++;
7266 save_input_line_pointer = input_line_pointer;
7267 input_line_pointer = disp_start;
7268 END_STRING_AND_SAVE (disp_end);
7269
7270#ifndef GCC_ASM_O_HACK
7271#define GCC_ASM_O_HACK 0
7272#endif
7273#if GCC_ASM_O_HACK
7274 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7275 if (i.types[this_operand].bitfield.baseIndex
24eab124 7276 && displacement_string_end[-1] == '+')
252b5132
RH		 7277 {
7278 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7279 constraint within gcc asm statements.
7280 For instance:
7281
7282 #define _set_tssldt_desc(n,addr,limit,type) \
7283 __asm__ __volatile__ ( \
7284 "movw %w2,%0\n\t" \
7285 "movw %w1,2+%0\n\t" \
7286 "rorl $16,%1\n\t" \
7287 "movb %b1,4+%0\n\t" \
7288 "movb %4,5+%0\n\t" \
7289 "movb $0,6+%0\n\t" \
7290 "movb %h1,7+%0\n\t" \
7291 "rorl $16,%1" \
7292 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7293
7294 This works great except that the output assembler ends
7295 up looking a bit weird if it turns out that there is
7296 no offset. You end up producing code that looks like:
7297
7298 #APP
7299 movw $235,(%eax)
7300 movw %dx,2+(%eax)
7301 rorl $16,%edx
7302 movb %dl,4+(%eax)
7303 movb $137,5+(%eax)
7304 movb $0,6+(%eax)
7305 movb %dh,7+(%eax)
7306 rorl $16,%edx
7307 #NO_APP
7308
47926f60 7309 So here we provide the missing zero. */
24eab124
AM		 7310
7311 *displacement_string_end = '0';
252b5132
RH		 7312 }
7313#endif
3956db08 7314 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7315 if (gotfree_input_line)
7316 input_line_pointer = gotfree_input_line;
252b5132 7317
24eab124 7318 exp_seg = expression (exp);
252b5132 7319
636c26b0
AM		 7320 SKIP_WHITESPACE ();
7321 if (*input_line_pointer)
7322 as_bad (_("junk `%s' after expression"), input_line_pointer);
7323#if GCC_ASM_O_HACK
7324 RESTORE_END_STRING (disp_end + 1);
7325#endif
636c26b0 7326 input_line_pointer = save_input_line_pointer;
636c26b0 7327 if (gotfree_input_line)
ee86248c
JB		 7328 {
7329 free (gotfree_input_line);
7330
7331 if (exp->X_op == O_constant || exp->X_op == O_register)
7332 exp->X_op = O_illegal;
7333 }
7334
7335 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7336
7337 RESTORE_END_STRING (disp_end);
7338
7339 return ret;
7340}
7341
7342static int
7343i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7344 i386_operand_type types, const char *disp_start)
7345{
7346 i386_operand_type bigdisp;
7347 int ret = 1;
636c26b0 7348
24eab124
AM		 7349 /* We do this to make sure that the section symbol is in
7350 the symbol table. We will ultimately change the relocation
47926f60 7351 to be relative to the beginning of the section. */
1ae12ab7 7352 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7353 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7354 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7355 {
636c26b0 7356 if (exp->X_op != O_symbol)
3992d3b7 7357 goto inv_disp;
636c26b0 7358
e5cb08ac 7359 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7360 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7361 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7362 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7363 exp->X_op = O_subtract;
7364 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7365 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7366 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7367 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7368 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7369 else
29b0f896 7370 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7371 }
252b5132 7372
3992d3b7
AM		 7373 else if (exp->X_op == O_absent
7374 || exp->X_op == O_illegal
ee86248c 7375 || exp->X_op == O_big)
2daf4fd8 7376 {
3992d3b7
AM		 7377 inv_disp:
7378 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7379 disp_start);
3992d3b7 7380 ret = 0;
2daf4fd8
AM		 7381 }
7382
0e1147d9
L		 7383 else if (flag_code == CODE_64BIT
7384 && !i.prefix[ADDR_PREFIX]
7385 && exp->X_op == O_constant)
7386 {
7387 /* Since displacement is signed extended to 64bit, don't allow
7388 disp32 and turn off disp32s if they are out of range. */
7389 i.types[this_operand].bitfield.disp32 = 0;
7390 if (!fits_in_signed_long (exp->X_add_number))
7391 {
7392 i.types[this_operand].bitfield.disp32s = 0;
7393 if (i.types[this_operand].bitfield.baseindex)
7394 {
7395 as_bad (_("0x%lx out range of signed 32bit displacement"),
7396 (long) exp->X_add_number);
7397 ret = 0;
7398 }
7399 }
7400 }
7401
4c63da97 7402#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7403 else if (exp->X_op != O_constant
7404 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7405 && exp_seg != absolute_section
7406 && exp_seg != text_section
7407 && exp_seg != data_section
7408 && exp_seg != bss_section
7409 && exp_seg != undefined_section
7410 && !bfd_is_com_section (exp_seg))
24eab124 7411 {
d0b47220 7412 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7413 ret = 0;
24eab124 7414 }
252b5132 7415#endif
3956db08 7416
40fb9820
L		 7417 /* Check if this is a displacement only operand. */
7418 bigdisp = i.types[this_operand];
7419 bigdisp.bitfield.disp8 = 0;
7420 bigdisp.bitfield.disp16 = 0;
7421 bigdisp.bitfield.disp32 = 0;
7422 bigdisp.bitfield.disp32s = 0;
7423 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7424 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7425 i.types[this_operand] = operand_type_and (i.types[this_operand],
7426 types);
3956db08 7427
3992d3b7 7428 return ret;
252b5132
RH		 7429}
7430
eecb386c 7431/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7432 Return 1 on success, 0 on a failure. */
7433
252b5132 7434static int
e3bb37b5 7435i386_index_check (const char *operand_string)
252b5132 7436{
3e73aa7c 7437 int ok;
fc0763e6 7438 const char *kind = "base/index";
24eab124 7439#if INFER_ADDR_PREFIX
eecb386c
AM		 7440 int fudged = 0;
7441
24eab124
AM		 7442 tryprefix:
7443#endif
3e73aa7c 7444 ok = 1;
fc0763e6
JB		 7445 if (current_templates->start->opcode_modifier.isstring
7446 && !current_templates->start->opcode_modifier.immext
7447 && (current_templates->end[-1].opcode_modifier.isstring
7448 || i.mem_operands))
7449 {
7450 /* Memory operands of string insns are special in that they only allow
7451 a single register (rDI, rSI, or rBX) as their memory address. */
7452 unsigned int expected;
7453
7454 kind = "string address";
7455
7456 if (current_templates->start->opcode_modifier.w)
7457 {
7458 i386_operand_type type = current_templates->end[-1].operand_types[0];
7459
7460 if (!type.bitfield.baseindex
7461 || ((!i.mem_operands != !intel_syntax)
7462 && current_templates->end[-1].operand_types[1]
7463 .bitfield.baseindex))
7464 type = current_templates->end[-1].operand_types[1];
7465 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7466 }
7467 else
7468 expected = 3 /* rBX */;
7469
7470 if (!i.base_reg || i.index_reg
7471 || operand_type_check (i.types[this_operand], disp))
7472 ok = -1;
7473 else if (!(flag_code == CODE_64BIT
7474 ? i.prefix[ADDR_PREFIX]
7475 ? i.base_reg->reg_type.bitfield.reg32
7476 : i.base_reg->reg_type.bitfield.reg64
7477 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7478 ? i.base_reg->reg_type.bitfield.reg32
7479 : i.base_reg->reg_type.bitfield.reg16))
7480 ok = 0;
4c692bc7 7481 else if (register_number (i.base_reg) != expected)
fc0763e6
JB		 7482 ok = -1;
7483
7484 if (ok < 0)
7485 {
7486 unsigned int j;
7487
7488 for (j = 0; j < i386_regtab_size; ++j)
7489 if ((flag_code == CODE_64BIT
7490 ? i.prefix[ADDR_PREFIX]
7491 ? i386_regtab[j].reg_type.bitfield.reg32
7492 : i386_regtab[j].reg_type.bitfield.reg64
7493 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7494 ? i386_regtab[j].reg_type.bitfield.reg32
7495 : i386_regtab[j].reg_type.bitfield.reg16)
4c692bc7 7496 && register_number(i386_regtab + j) == expected)
fc0763e6 7497 break;
9c2799c2 7498 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7499 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7500 operand_string,
7501 intel_syntax ? '[' : '(',
7502 register_prefix,
7503 i386_regtab[j].reg_name,
7504 intel_syntax ? ']' : ')');
7505 ok = 1;
7506 }
7507 }
7508 else if (flag_code == CODE_64BIT)
64e74474 7509 {
64e74474 7510 if ((i.base_reg
40fb9820
L		 7511 && ((i.prefix[ADDR_PREFIX] == 0
7512 && !i.base_reg->reg_type.bitfield.reg64)
7513 || (i.prefix[ADDR_PREFIX]
7514 && !i.base_reg->reg_type.bitfield.reg32))
7515 && (i.index_reg
9a04903e
JB		 7516 || i.base_reg->reg_num !=
7517 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7518 || (i.index_reg
6c30d220
L		 7519 && !(i.index_reg->reg_type.bitfield.regxmm
7520 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7521 && (!i.index_reg->reg_type.bitfield.baseindex
7522 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7523 && i.index_reg->reg_num != RegRiz
7524 && !i.index_reg->reg_type.bitfield.reg64
7525 )
40fb9820 7526 || (i.prefix[ADDR_PREFIX]
db51cc60 7527 && i.index_reg->reg_num != RegEiz
40fb9820 7528 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7529 ok = 0;
3e73aa7c
JH		 7530 }
7531 else
7532 {
7533 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7534 {
7535 /* 16bit checks. */
7536 if ((i.base_reg
40fb9820
L		 7537 && (!i.base_reg->reg_type.bitfield.reg16
7538 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7539 || (i.index_reg
40fb9820
L		 7540 && (!i.index_reg->reg_type.bitfield.reg16
7541 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7542 || !(i.base_reg
7543 && i.base_reg->reg_num < 6
7544 && i.index_reg->reg_num >= 6
7545 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7546 ok = 0;
7547 }
7548 else
e5cb08ac 7549 {
3e73aa7c
JH		 7550 /* 32bit checks. */
7551 if ((i.base_reg
40fb9820 7552 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7553 || (i.index_reg
6c30d220
L		 7554 && !i.index_reg->reg_type.bitfield.regxmm
7555 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7556 && ((!i.index_reg->reg_type.bitfield.reg32
7557 && i.index_reg->reg_num != RegEiz)
40fb9820 7558 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7559 ok = 0;
3e73aa7c
JH		 7560 }
7561 }
7562 if (!ok)
24eab124
AM		 7563 {
7564#if INFER_ADDR_PREFIX
fc0763e6 7565 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7566 {
7567 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7568 i.prefixes += 1;
b23bac36
AM		 7569 /* Change the size of any displacement too. At most one of
7570 Disp16 or Disp32 is set.
7571 FIXME. There doesn't seem to be any real need for separate
7572 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7573 Removing them would probably clean up the code quite a lot. */
4eed87de 7574 if (flag_code != CODE_64BIT
40fb9820
L		 7575 && (i.types[this_operand].bitfield.disp16
7576 || i.types[this_operand].bitfield.disp32))
7577 i.types[this_operand]
c6fb90c8 7578 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7579 fudged = 1;
24eab124
AM		 7580 goto tryprefix;
7581 }
eecb386c 7582 if (fudged)
fc0763e6
JB		 7583 as_bad (_("`%s' is not a valid %s expression"),
7584 operand_string,
7585 kind);
eecb386c 7586 else
c388dee8 7587#endif
fc0763e6 7588 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7589 operand_string,
fc0763e6
JB		 7590 flag_code_names[i.prefix[ADDR_PREFIX]
7591 ? flag_code == CODE_32BIT
7592 ? CODE_16BIT
7593 : CODE_32BIT
7594 : flag_code],
7595 kind);
24eab124 7596 }
20f0a1fc 7597 return ok;
24eab124 7598}
252b5132 7599
fc0763e6 7600/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7601 on error. */
252b5132 7602
252b5132 7603static int
a7619375 7604i386_att_operand (char *operand_string)
252b5132 7605{
af6bdddf
AM		 7606 const reg_entry *r;
7607 char *end_op;
24eab124 7608 char *op_string = operand_string;
252b5132 7609
24eab124 7610 if (is_space_char (*op_string))
252b5132
RH		 7611 ++op_string;
7612
24eab124 7613 /* We check for an absolute prefix (differentiating,
47926f60 7614 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7615 if (*op_string == ABSOLUTE_PREFIX)
7616 {
7617 ++op_string;
7618 if (is_space_char (*op_string))
7619 ++op_string;
40fb9820 7620 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7621 }
252b5132 7622
47926f60 7623 /* Check if operand is a register. */
4d1bb795 7624 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7625 {
40fb9820
L		 7626 i386_operand_type temp;
7627
24eab124
AM		 7628 /* Check for a segment override by searching for ':' after a
7629 segment register. */
7630 op_string = end_op;
7631 if (is_space_char (*op_string))
7632 ++op_string;
40fb9820
L		 7633 if (*op_string == ':'
7634 && (r->reg_type.bitfield.sreg2
7635 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7636 {
7637 switch (r->reg_num)
7638 {
7639 case 0:
7640 i.seg[i.mem_operands] = &es;
7641 break;
7642 case 1:
7643 i.seg[i.mem_operands] = &cs;
7644 break;
7645 case 2:
7646 i.seg[i.mem_operands] = &ss;
7647 break;
7648 case 3:
7649 i.seg[i.mem_operands] = &ds;
7650 break;
7651 case 4:
7652 i.seg[i.mem_operands] = &fs;
7653 break;
7654 case 5:
7655 i.seg[i.mem_operands] = &gs;
7656 break;
7657 }
252b5132 7658
24eab124 7659 /* Skip the ':' and whitespace. */
252b5132
RH		 7660 ++op_string;
7661 if (is_space_char (*op_string))
24eab124 7662 ++op_string;
252b5132 7663
24eab124
AM		 7664 if (!is_digit_char (*op_string)
7665 && !is_identifier_char (*op_string)
7666 && *op_string != '('
7667 && *op_string != ABSOLUTE_PREFIX)
7668 {
7669 as_bad (_("bad memory operand `%s'"), op_string);
7670 return 0;
7671 }
47926f60 7672 /* Handle case of %es:*foo. */
24eab124
AM		 7673 if (*op_string == ABSOLUTE_PREFIX)
7674 {
7675 ++op_string;
7676 if (is_space_char (*op_string))
7677 ++op_string;
40fb9820 7678 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7679 }
7680 goto do_memory_reference;
7681 }
7682 if (*op_string)
7683 {
d0b47220 7684 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7685 return 0;
7686 }
40fb9820
L		 7687 temp = r->reg_type;
7688 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7689 i.types[this_operand] = operand_type_or (i.types[this_operand],
7690 temp);
7d5e4556 7691 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7692 i.op[this_operand].regs = r;
24eab124
AM		 7693 i.reg_operands++;
7694 }
af6bdddf
AM		 7695 else if (*op_string == REGISTER_PREFIX)
7696 {
7697 as_bad (_("bad register name `%s'"), op_string);
7698 return 0;
7699 }
24eab124 7700 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7701 {
24eab124 7702 ++op_string;
40fb9820 7703 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7704 {
d0b47220 7705 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7706 return 0;
7707 }
7708 if (!i386_immediate (op_string))
7709 return 0;
7710 }
7711 else if (is_digit_char (*op_string)
7712 || is_identifier_char (*op_string)
e5cb08ac 7713 || *op_string == '(')
24eab124 7714 {
47926f60 7715 /* This is a memory reference of some sort. */
af6bdddf 7716 char *base_string;
252b5132 7717
47926f60 7718 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7719 char *displacement_string_start;
7720 char *displacement_string_end;
252b5132 7721
24eab124 7722 do_memory_reference:
24eab124 7723 if ((i.mem_operands == 1
40fb9820 7724 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7725 || i.mem_operands == 2)
7726 {
7727 as_bad (_("too many memory references for `%s'"),
7728 current_templates->start->name);
7729 return 0;
7730 }
252b5132 7731
24eab124
AM		 7732 /* Check for base index form. We detect the base index form by
7733 looking for an ')' at the end of the operand, searching
7734 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7735 after the '('. */
af6bdddf 7736 base_string = op_string + strlen (op_string);
c3332e24 7737
af6bdddf
AM		 7738 --base_string;
7739 if (is_space_char (*base_string))
7740 --base_string;
252b5132 7741
47926f60 7742 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7743 displacement_string_start = op_string;
7744 displacement_string_end = base_string + 1;
252b5132 7745
24eab124
AM		 7746 if (*base_string == ')')
7747 {
af6bdddf 7748 char *temp_string;
24eab124
AM		 7749 unsigned int parens_balanced = 1;
7750 /* We've already checked that the number of left & right ()'s are
47926f60 7751 equal, so this loop will not be infinite. */
24eab124
AM		 7752 do
7753 {
7754 base_string--;
7755 if (*base_string == ')')
7756 parens_balanced++;
7757 if (*base_string == '(')
7758 parens_balanced--;
7759 }
7760 while (parens_balanced);
c3332e24 7761
af6bdddf 7762 temp_string = base_string;
c3332e24 7763
24eab124 7764 /* Skip past '(' and whitespace. */
252b5132
RH		 7765 ++base_string;
7766 if (is_space_char (*base_string))
24eab124 7767 ++base_string;
252b5132 7768
af6bdddf 7769 if (*base_string == ','
4eed87de
AM		 7770 || ((i.base_reg = parse_register (base_string, &end_op))
7771 != NULL))
252b5132 7772 {
af6bdddf 7773 displacement_string_end = temp_string;
252b5132 7774
40fb9820 7775 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7776
af6bdddf 7777 if (i.base_reg)
24eab124 7778 {
24eab124
AM		 7779 base_string = end_op;
7780 if (is_space_char (*base_string))
7781 ++base_string;
af6bdddf
AM		 7782 }
7783
7784 /* There may be an index reg or scale factor here. */
7785 if (*base_string == ',')
7786 {
7787 ++base_string;
7788 if (is_space_char (*base_string))
7789 ++base_string;
7790
4eed87de
AM		 7791 if ((i.index_reg = parse_register (base_string, &end_op))
7792 != NULL)
24eab124 7793 {
af6bdddf 7794 base_string = end_op;
24eab124
AM		 7795 if (is_space_char (*base_string))
7796 ++base_string;
af6bdddf
AM		 7797 if (*base_string == ',')
7798 {
7799 ++base_string;
7800 if (is_space_char (*base_string))
7801 ++base_string;
7802 }
e5cb08ac 7803 else if (*base_string != ')')
af6bdddf 7804 {
4eed87de
AM		 7805 as_bad (_("expecting `,' or `)' "
7806 "after index register in `%s'"),
af6bdddf
AM		 7807 operand_string);
7808 return 0;
7809 }
24eab124 7810 }
af6bdddf 7811 else if (*base_string == REGISTER_PREFIX)
24eab124 7812 {
f76bf5e0
L		 7813 end_op = strchr (base_string, ',');
7814 if (end_op)
7815 *end_op = '\0';
af6bdddf 7816 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7817 return 0;
7818 }
252b5132 7819
47926f60 7820 /* Check for scale factor. */
551c1ca1 7821 if (*base_string != ')')
af6bdddf 7822 {
551c1ca1
AM		 7823 char *end_scale = i386_scale (base_string);
7824
7825 if (!end_scale)
af6bdddf 7826 return 0;
24eab124 7827
551c1ca1 7828 base_string = end_scale;
af6bdddf
AM		 7829 if (is_space_char (*base_string))
7830 ++base_string;
7831 if (*base_string != ')')
7832 {
4eed87de
AM		 7833 as_bad (_("expecting `)' "
7834 "after scale factor in `%s'"),
af6bdddf
AM		 7835 operand_string);
7836 return 0;
7837 }
7838 }
7839 else if (!i.index_reg)
24eab124 7840 {
4eed87de
AM		 7841 as_bad (_("expecting index register or scale factor "
7842 "after `,'; got '%c'"),
af6bdddf 7843 *base_string);
24eab124
AM		 7844 return 0;
7845 }
7846 }
af6bdddf 7847 else if (*base_string != ')')
24eab124 7848 {
4eed87de
AM		 7849 as_bad (_("expecting `,' or `)' "
7850 "after base register in `%s'"),
af6bdddf 7851 operand_string);
24eab124
AM		 7852 return 0;
7853 }
c3332e24 7854 }
af6bdddf 7855 else if (*base_string == REGISTER_PREFIX)
c3332e24 7856 {
f76bf5e0
L		 7857 end_op = strchr (base_string, ',');
7858 if (end_op)
7859 *end_op = '\0';
af6bdddf 7860 as_bad (_("bad register name `%s'"), base_string);
24eab124 7861 return 0;
c3332e24 7862 }
24eab124
AM		 7863 }
7864
7865 /* If there's an expression beginning the operand, parse it,
7866 assuming displacement_string_start and
7867 displacement_string_end are meaningful. */
7868 if (displacement_string_start != displacement_string_end)
7869 {
7870 if (!i386_displacement (displacement_string_start,
7871 displacement_string_end))
7872 return 0;
7873 }
7874
7875 /* Special case for (%dx) while doing input/output op. */
7876 if (i.base_reg
0dfbf9d7
L		 7877 && operand_type_equal (&i.base_reg->reg_type,
7878 &reg16_inoutportreg)
24eab124
AM		 7879 && i.index_reg == 0
7880 && i.log2_scale_factor == 0
7881 && i.seg[i.mem_operands] == 0
40fb9820 7882 && !operand_type_check (i.types[this_operand], disp))
24eab124 7883 {
65da13b5 7884 i.types[this_operand] = inoutportreg;
24eab124
AM		 7885 return 1;
7886 }
7887
eecb386c
AM		 7888 if (i386_index_check (operand_string) == 0)
7889 return 0;
5c07affc 7890 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7891 i.mem_operands++;
7892 }
7893 else
ce8a8b2f
AM		 7894 {
7895 /* It's not a memory operand; argh! */
24eab124
AM		 7896 as_bad (_("invalid char %s beginning operand %d `%s'"),
7897 output_invalid (*op_string),
7898 this_operand + 1,
7899 op_string);
7900 return 0;
7901 }
47926f60 7902 return 1; /* Normal return. */
252b5132
RH		 7903}
7904\f
fa94de6b
RM		 7905/* Calculate the maximum variable size (i.e., excluding fr_fix)
7906 that an rs_machine_dependent frag may reach. */
7907
7908unsigned int
7909i386_frag_max_var (fragS *frag)
7910{
7911 /* The only relaxable frags are for jumps.
7912 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7913 gas_assert (frag->fr_type == rs_machine_dependent);
7914 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
7915}
7916
ee7fcc42
AM		 7917/* md_estimate_size_before_relax()
7918
7919 Called just before relax() for rs_machine_dependent frags. The x86
7920 assembler uses these frags to handle variable size jump
7921 instructions.
7922
7923 Any symbol that is now undefined will not become defined.
7924 Return the correct fr_subtype in the frag.
7925 Return the initial "guess for variable size of frag" to caller.
7926 The guess is actually the growth beyond the fixed part. Whatever
7927 we do to grow the fixed or variable part contributes to our
7928 returned value. */
7929
252b5132 7930int
7016a5d5 7931md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7932{
252b5132 7933 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7934 check for un-relaxable symbols. On an ELF system, we can't relax
7935 an externally visible symbol, because it may be overridden by a
7936 shared library. */
7937 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7939 || (IS_ELF
31312f95 7940 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7941 || S_IS_WEAK (fragP->fr_symbol)
7942 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7943 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7944#endif
7945#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7946 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7947 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7948#endif
7949 )
252b5132 7950 {
b98ef147
AM		 7951 /* Symbol is undefined in this segment, or we need to keep a
7952 reloc so that weak symbols can be overridden. */
7953 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7954 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7955 unsigned char *opcode;
7956 int old_fr_fix;
f6af82bd 7957
ee7fcc42 7958 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7959 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7960 else if (size == 2)
f6af82bd
AM		 7961 reloc_type = BFD_RELOC_16_PCREL;
7962 else
7963 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7964
ee7fcc42
AM		 7965 old_fr_fix = fragP->fr_fix;
7966 opcode = (unsigned char *) fragP->fr_opcode;
7967
fddf5b5b 7968 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7969 {
fddf5b5b
AM		 7970 case UNCOND_JUMP:
7971 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7972 opcode[0] = 0xe9;
252b5132 7973 fragP->fr_fix += size;
062cd5e7
AS		 7974 fix_new (fragP, old_fr_fix, size,
7975 fragP->fr_symbol,
7976 fragP->fr_offset, 1,
7977 reloc_type);
252b5132
RH		 7978 break;
7979
fddf5b5b 7980 case COND_JUMP86:
412167cb
AM		 7981 if (size == 2
7982 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7983 {
7984 /* Negate the condition, and branch past an
7985 unconditional jump. */
7986 opcode[0] ^= 1;
7987 opcode[1] = 3;
7988 /* Insert an unconditional jump. */
7989 opcode[2] = 0xe9;
7990 /* We added two extra opcode bytes, and have a two byte
7991 offset. */
7992 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7993 fix_new (fragP, old_fr_fix + 2, 2,
7994 fragP->fr_symbol,
7995 fragP->fr_offset, 1,
7996 reloc_type);
fddf5b5b
AM		 7997 break;
7998 }
7999 /* Fall through. */
8000
8001 case COND_JUMP:
412167cb
AM		 8002 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8003 {
3e02c1cc
AM		 8004 fixS *fixP;
8005
412167cb 8006 fragP->fr_fix += 1;
3e02c1cc
AM		 8007 fixP = fix_new (fragP, old_fr_fix, 1,
8008 fragP->fr_symbol,
8009 fragP->fr_offset, 1,
8010 BFD_RELOC_8_PCREL);
8011 fixP->fx_signed = 1;
412167cb
AM		 8012 break;
8013 }
93c2a809 8014
24eab124 8015 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8016 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8017 opcode[1] = opcode[0] + 0x10;
f6af82bd 8018 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8019 /* We've added an opcode byte. */
8020 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8021 fix_new (fragP, old_fr_fix + 1, size,
8022 fragP->fr_symbol,
8023 fragP->fr_offset, 1,
8024 reloc_type);
252b5132 8025 break;
fddf5b5b
AM		 8026
8027 default:
8028 BAD_CASE (fragP->fr_subtype);
8029 break;
252b5132
RH		 8030 }
8031 frag_wane (fragP);
ee7fcc42 8032 return fragP->fr_fix - old_fr_fix;
252b5132 8033 }
93c2a809 8034
93c2a809
AM		 8035 /* Guess size depending on current relax state. Initially the relax
8036 state will correspond to a short jump and we return 1, because
8037 the variable part of the frag (the branch offset) is one byte
8038 long. However, we can relax a section more than once and in that
8039 case we must either set fr_subtype back to the unrelaxed state,
8040 or return the value for the appropriate branch. */
8041 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8042}
8043
47926f60
KH		 8044/* Called after relax() is finished.
8045
8046 In: Address of frag.
8047 fr_type == rs_machine_dependent.
8048 fr_subtype is what the address relaxed to.
8049
8050 Out: Any fixSs and constants are set up.
8051 Caller will turn frag into a ".space 0". */
8052
252b5132 8053void
7016a5d5
TG		 8054md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8055 fragS *fragP)
252b5132 8056{
29b0f896 8057 unsigned char *opcode;
252b5132 8058 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8059 offsetT target_address;
8060 offsetT opcode_address;
252b5132 8061 unsigned int extension = 0;
847f7ad4 8062 offsetT displacement_from_opcode_start;
252b5132
RH		 8063
8064 opcode = (unsigned char *) fragP->fr_opcode;
8065
47926f60 8066 /* Address we want to reach in file space. */
252b5132 8067 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8068
47926f60 8069 /* Address opcode resides at in file space. */
252b5132
RH		 8070 opcode_address = fragP->fr_address + fragP->fr_fix;
8071
47926f60 8072 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8073 displacement_from_opcode_start = target_address - opcode_address;
8074
fddf5b5b 8075 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8076 {
47926f60
KH		 8077 /* Don't have to change opcode. */
8078 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8079 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8080 }
8081 else
8082 {
8083 if (no_cond_jump_promotion
8084 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8085 as_warn_where (fragP->fr_file, fragP->fr_line,
8086 _("long jump required"));
252b5132 8087
fddf5b5b
AM		 8088 switch (fragP->fr_subtype)
8089 {
8090 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8091 extension = 4; /* 1 opcode + 4 displacement */
8092 opcode[0] = 0xe9;
8093 where_to_put_displacement = &opcode[1];
8094 break;
252b5132 8095
fddf5b5b
AM		 8096 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8097 extension = 2; /* 1 opcode + 2 displacement */
8098 opcode[0] = 0xe9;
8099 where_to_put_displacement = &opcode[1];
8100 break;
252b5132 8101
fddf5b5b
AM		 8102 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8103 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8104 extension = 5; /* 2 opcode + 4 displacement */
8105 opcode[1] = opcode[0] + 0x10;
8106 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8107 where_to_put_displacement = &opcode[2];
8108 break;
252b5132 8109
fddf5b5b
AM		 8110 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8111 extension = 3; /* 2 opcode + 2 displacement */
8112 opcode[1] = opcode[0] + 0x10;
8113 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8114 where_to_put_displacement = &opcode[2];
8115 break;
252b5132 8116
fddf5b5b
AM		 8117 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8118 extension = 4;
8119 opcode[0] ^= 1;
8120 opcode[1] = 3;
8121 opcode[2] = 0xe9;
8122 where_to_put_displacement = &opcode[3];
8123 break;
8124
8125 default:
8126 BAD_CASE (fragP->fr_subtype);
8127 break;
8128 }
252b5132 8129 }
fddf5b5b 8130
7b81dfbb
AJ		 8131 /* If size if less then four we are sure that the operand fits,
8132 but if it's 4, then it could be that the displacement is larger
8133 then -/+ 2GB. */
8134 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8135 && object_64bit
8136 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8137 + ((addressT) 1 << 31))
8138 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 8139 {
8140 as_bad_where (fragP->fr_file, fragP->fr_line,
8141 _("jump target out of range"));
8142 /* Make us emit 0. */
8143 displacement_from_opcode_start = extension;
8144 }
47926f60 8145 /* Now put displacement after opcode. */
252b5132
RH		 8146 md_number_to_chars ((char *) where_to_put_displacement,
8147 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 8148 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 8149 fragP->fr_fix += extension;
8150}
8151\f
7016a5d5 8152/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 8153 by our caller that we have all the info we need to fix it up.
8154
7016a5d5
TG		 8155 Parameter valP is the pointer to the value of the bits.
8156
252b5132
RH		 8157 On the 386, immediates, displacements, and data pointers are all in
8158 the same (little-endian) format, so we don't need to care about which
8159 we are handling. */
8160
94f592af 8161void
7016a5d5 8162md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 8163{
94f592af 8164 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 8165 valueT value = *valP;
252b5132 8166
f86103b7 8167#if !defined (TE_Mach)
93382f6d
AM		 8168 if (fixP->fx_pcrel)
8169 {
8170 switch (fixP->fx_r_type)
8171 {
5865bb77
ILT		 8172 default:
8173 break;
8174
d6ab8113
JB		 8175 case BFD_RELOC_64:
8176 fixP->fx_r_type = BFD_RELOC_64_PCREL;
8177 break;
93382f6d 8178 case BFD_RELOC_32:
ae8887b5 8179 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 8180 fixP->fx_r_type = BFD_RELOC_32_PCREL;
8181 break;
8182 case BFD_RELOC_16:
8183 fixP->fx_r_type = BFD_RELOC_16_PCREL;
8184 break;
8185 case BFD_RELOC_8:
8186 fixP->fx_r_type = BFD_RELOC_8_PCREL;
8187 break;
8188 }
8189 }
252b5132 8190
a161fe53 8191 if (fixP->fx_addsy != NULL
31312f95 8192 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 8193 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 8194 || fixP->fx_r_type == BFD_RELOC_16_PCREL
8195 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
8196 && !use_rela_relocations)
252b5132 8197 {
31312f95
AM		 8198 /* This is a hack. There should be a better way to handle this.
8199 This covers for the fact that bfd_install_relocation will
8200 subtract the current location (for partial_inplace, PC relative
8201 relocations); see more below. */
252b5132 8202#ifndef OBJ_AOUT
718ddfc0 8203 if (IS_ELF
252b5132
RH		 8204#ifdef TE_PE
8205 || OUTPUT_FLAVOR == bfd_target_coff_flavour
8206#endif
8207 )
8208 value += fixP->fx_where + fixP->fx_frag->fr_address;
8209#endif
8210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8211 if (IS_ELF)
252b5132 8212 {
6539b54b 8213 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 8214
6539b54b 8215 if ((sym_seg == seg
2f66722d 8216 || (symbol_section_p (fixP->fx_addsy)
6539b54b 8217 && sym_seg != absolute_section))
af65af87 8218 && !generic_force_reloc (fixP))
2f66722d
AM		 8219 {
8220 /* Yes, we add the values in twice. This is because
6539b54b
AM		 8221 bfd_install_relocation subtracts them out again. I think
8222 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 8223 it. FIXME. */
8224 value += fixP->fx_where + fixP->fx_frag->fr_address;
8225 }
252b5132
RH		 8226 }
8227#endif
8228#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 8229 /* For some reason, the PE format does not store a
8230 section address offset for a PC relative symbol. */
8231 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 8232 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 8233 value += md_pcrel_from (fixP);
8234#endif
8235 }
fbeb56a4
DK		 8236#if defined (OBJ_COFF) && defined (TE_PE)
8237 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8238 {
8239 value -= S_GET_VALUE (fixP->fx_addsy);
8240 }
8241#endif
252b5132
RH		 8242
8243 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 8244 and we must not disappoint it. */
252b5132 8245#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8246 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 8247 switch (fixP->fx_r_type)
8248 {
8249 case BFD_RELOC_386_PLT32:
3e73aa7c 8250 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 8251 /* Make the jump instruction point to the address of the operand. At
8252 runtime we merely add the offset to the actual PLT entry. */
8253 value = -4;
8254 break;
31312f95 8255
13ae64f3
JJ		 8256 case BFD_RELOC_386_TLS_GD:
8257 case BFD_RELOC_386_TLS_LDM:
13ae64f3 8258 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8259 case BFD_RELOC_386_TLS_IE:
8260 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 8261 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 8262 case BFD_RELOC_X86_64_TLSGD:
8263 case BFD_RELOC_X86_64_TLSLD:
8264 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 8265 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 8266 value = 0; /* Fully resolved at runtime. No addend. */
8267 /* Fallthrough */
8268 case BFD_RELOC_386_TLS_LE:
8269 case BFD_RELOC_386_TLS_LDO_32:
8270 case BFD_RELOC_386_TLS_LE_32:
8271 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8272 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 8273 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 8274 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 8275 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8276 break;
8277
67a4f2b7
AO		 8278 case BFD_RELOC_386_TLS_DESC_CALL:
8279 case BFD_RELOC_X86_64_TLSDESC_CALL:
8280 value = 0; /* Fully resolved at runtime. No addend. */
8281 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8282 fixP->fx_done = 0;
8283 return;
8284
00f7efb6
JJ		 8285 case BFD_RELOC_386_GOT32:
8286 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 8287 value = 0; /* Fully resolved at runtime. No addend. */
8288 break;
47926f60
KH		 8289
8290 case BFD_RELOC_VTABLE_INHERIT:
8291 case BFD_RELOC_VTABLE_ENTRY:
8292 fixP->fx_done = 0;
94f592af 8293 return;
47926f60
KH		 8294
8295 default:
8296 break;
8297 }
8298#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8299 *valP = value;
f86103b7 8300#endif /* !defined (TE_Mach) */
3e73aa7c 8301
3e73aa7c 8302 /* Are we finished with this relocation now? */
c6682705 8303 if (fixP->fx_addsy == NULL)
3e73aa7c 8304 fixP->fx_done = 1;
fbeb56a4
DK		 8305#if defined (OBJ_COFF) && defined (TE_PE)
8306 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8307 {
8308 fixP->fx_done = 0;
8309 /* Remember value for tc_gen_reloc. */
8310 fixP->fx_addnumber = value;
8311 /* Clear out the frag for now. */
8312 value = 0;
8313 }
8314#endif
3e73aa7c
JH		 8315 else if (use_rela_relocations)
8316 {
8317 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8318 /* Remember value for tc_gen_reloc. */
8319 fixP->fx_addnumber = value;
3e73aa7c
JH		 8320 value = 0;
8321 }
f86103b7 8322
94f592af 8323 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8324}
252b5132 8325\f
252b5132 8326char *
499ac353 8327md_atof (int type, char *litP, int *sizeP)
252b5132 8328{
499ac353
NC		 8329 /* This outputs the LITTLENUMs in REVERSE order;
8330 in accord with the bigendian 386. */
8331 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8332}
8333\f
2d545b82 8334static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8335
252b5132 8336static char *
e3bb37b5 8337output_invalid (int c)
252b5132 8338{
3882b010 8339 if (ISPRINT (c))
f9f21a03
L		 8340 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8341 "'%c'", c);
252b5132 8342 else
f9f21a03 8343 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8344 "(0x%x)", (unsigned char) c);
252b5132
RH		 8345 return output_invalid_buf;
8346}
8347
af6bdddf 8348/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8349
8350static const reg_entry *
4d1bb795 8351parse_real_register (char *reg_string, char **end_op)
252b5132 8352{
af6bdddf
AM		 8353 char *s = reg_string;
8354 char *p;
252b5132
RH		 8355 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8356 const reg_entry *r;
8357
8358 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8359 if (*s == REGISTER_PREFIX)
8360 ++s;
8361
8362 if (is_space_char (*s))
8363 ++s;
8364
8365 p = reg_name_given;
af6bdddf 8366 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8367 {
8368 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8369 return (const reg_entry *) NULL;
8370 s++;
252b5132
RH		 8371 }
8372
6588847e
DN		 8373 /* For naked regs, make sure that we are not dealing with an identifier.
8374 This prevents confusing an identifier like `eax_var' with register
8375 `eax'. */
8376 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8377 return (const reg_entry *) NULL;
8378
af6bdddf 8379 *end_op = s;
252b5132
RH		 8380
8381 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8382
5f47d35b 8383 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8384 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8385 {
5f47d35b
AM		 8386 if (is_space_char (*s))
8387 ++s;
8388 if (*s == '(')
8389 {
af6bdddf 8390 ++s;
5f47d35b
AM		 8391 if (is_space_char (*s))
8392 ++s;
8393 if (*s >= '0' && *s <= '7')
8394 {
db557034 8395 int fpr = *s - '0';
af6bdddf 8396 ++s;
5f47d35b
AM		 8397 if (is_space_char (*s))
8398 ++s;
8399 if (*s == ')')
8400 {
8401 *end_op = s + 1;
1e9cc1c2 8402 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8403 know (r);
8404 return r + fpr;
5f47d35b 8405 }
5f47d35b 8406 }
47926f60 8407 /* We have "%st(" then garbage. */
5f47d35b
AM		 8408 return (const reg_entry *) NULL;
8409 }
8410 }
8411
a60de03c
JB		 8412 if (r == NULL || allow_pseudo_reg)
8413 return r;
8414
0dfbf9d7 8415 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8416 return (const reg_entry *) NULL;
8417
192dc9c6
JB		 8418 if ((r->reg_type.bitfield.reg32
8419 || r->reg_type.bitfield.sreg3
8420 || r->reg_type.bitfield.control
8421 || r->reg_type.bitfield.debug
8422 || r->reg_type.bitfield.test)
8423 && !cpu_arch_flags.bitfield.cpui386)
8424 return (const reg_entry *) NULL;
8425
309d3373
JB		 8426 if (r->reg_type.bitfield.floatreg
8427 && !cpu_arch_flags.bitfield.cpu8087
8428 && !cpu_arch_flags.bitfield.cpu287
8429 && !cpu_arch_flags.bitfield.cpu387)
8430 return (const reg_entry *) NULL;
8431
192dc9c6
JB		 8432 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8433 return (const reg_entry *) NULL;
8434
8435 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8436 return (const reg_entry *) NULL;
8437
40f12533
L		 8438 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8439 return (const reg_entry *) NULL;
8440
db51cc60 8441 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8442 if (!allow_index_reg
db51cc60
L		 8443 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8444 return (const reg_entry *) NULL;
8445
a60de03c
JB		 8446 if (((r->reg_flags & (RegRex64 | RegRex))
8447 || r->reg_type.bitfield.reg64)
40fb9820 8448 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8449 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8450 && flag_code != CODE_64BIT)
20f0a1fc 8451 return (const reg_entry *) NULL;
1ae00879 8452
b7240065
JB		 8453 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8454 return (const reg_entry *) NULL;
8455
252b5132
RH		 8456 return r;
8457}
4d1bb795
JB		 8458
8459/* REG_STRING starts *before* REGISTER_PREFIX. */
8460
8461static const reg_entry *
8462parse_register (char *reg_string, char **end_op)
8463{
8464 const reg_entry *r;
8465
8466 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8467 r = parse_real_register (reg_string, end_op);
8468 else
8469 r = NULL;
8470 if (!r)
8471 {
8472 char *save = input_line_pointer;
8473 char c;
8474 symbolS *symbolP;
8475
8476 input_line_pointer = reg_string;
8477 c = get_symbol_end ();
8478 symbolP = symbol_find (reg_string);
8479 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8480 {
8481 const expressionS *e = symbol_get_value_expression (symbolP);
8482
0398aac5 8483 know (e->X_op == O_register);
4eed87de 8484 know (e->X_add_number >= 0
c3fe08fa 8485 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8486 r = i386_regtab + e->X_add_number;
8487 *end_op = input_line_pointer;
8488 }
8489 *input_line_pointer = c;
8490 input_line_pointer = save;
8491 }
8492 return r;
8493}
8494
8495int
8496i386_parse_name (char *name, expressionS *e, char *nextcharP)
8497{
8498 const reg_entry *r;
8499 char *end = input_line_pointer;
8500
8501 *end = *nextcharP;
8502 r = parse_register (name, &input_line_pointer);
8503 if (r && end <= input_line_pointer)
8504 {
8505 *nextcharP = *input_line_pointer;
8506 *input_line_pointer = 0;
8507 e->X_op = O_register;
8508 e->X_add_number = r - i386_regtab;
8509 return 1;
8510 }
8511 input_line_pointer = end;
8512 *end = 0;
ee86248c 8513 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8514}
8515
8516void
8517md_operand (expressionS *e)
8518{
ee86248c
JB		 8519 char *end;
8520 const reg_entry *r;
4d1bb795 8521
ee86248c
JB		 8522 switch (*input_line_pointer)
8523 {
8524 case REGISTER_PREFIX:
8525 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8526 if (r)
8527 {
8528 e->X_op = O_register;
8529 e->X_add_number = r - i386_regtab;
8530 input_line_pointer = end;
8531 }
ee86248c
JB		 8532 break;
8533
8534 case '[':
9c2799c2 8535 gas_assert (intel_syntax);
ee86248c
JB		 8536 end = input_line_pointer++;
8537 expression (e);
8538 if (*input_line_pointer == ']')
8539 {
8540 ++input_line_pointer;
8541 e->X_op_symbol = make_expr_symbol (e);
8542 e->X_add_symbol = NULL;
8543 e->X_add_number = 0;
8544 e->X_op = O_index;
8545 }
8546 else
8547 {
8548 e->X_op = O_absent;
8549 input_line_pointer = end;
8550 }
8551 break;
4d1bb795
JB		 8552 }
8553}
8554
252b5132 8555\f
4cc782b5 8556#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8557const char *md_shortopts = "kVQ:sqn";
252b5132 8558#else
12b55ccc 8559const char *md_shortopts = "qn";
252b5132 8560#endif
6e0b89ee 8561
3e73aa7c 8562#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8563#define OPTION_64 (OPTION_MD_BASE + 1)
8564#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8565#define OPTION_MARCH (OPTION_MD_BASE + 3)
8566#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8567#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8568#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8569#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8570#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8571#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8572#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8573#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 8574#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8575#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8576#define OPTION_X32 (OPTION_MD_BASE + 14)
b3b91714 8577
99ad8390
NC		 8578struct option md_longopts[] =
8579{
3e73aa7c 8580 {"32", no_argument, NULL, OPTION_32},
321098a5 8581#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 8583 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8584#endif
8585#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8586 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8587#endif
b3b91714 8588 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8589 {"march", required_argument, NULL, OPTION_MARCH},
8590 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8591 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8592 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8593 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8594 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8595 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8596 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8597 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 8598 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 8599 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8600 {NULL, no_argument, NULL, 0}
8601};
8602size_t md_longopts_size = sizeof (md_longopts);
8603
8604int
9103f4f4 8605md_parse_option (int c, char *arg)
252b5132 8606{
91d6fa6a 8607 unsigned int j;
6305a203 8608 char *arch, *next;
9103f4f4 8609
252b5132
RH		 8610 switch (c)
8611 {
12b55ccc
L		 8612 case 'n':
8613 optimize_align_code = 0;
8614 break;
8615
a38cf1db
AM		 8616 case 'q':
8617 quiet_warnings = 1;
252b5132
RH		 8618 break;
8619
8620#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8621 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8622 should be emitted or not. FIXME: Not implemented. */
8623 case 'Q':
252b5132
RH		 8624 break;
8625
8626 /* -V: SVR4 argument to print version ID. */
8627 case 'V':
8628 print_version_id ();
8629 break;
8630
a38cf1db
AM		 8631 /* -k: Ignore for FreeBSD compatibility. */
8632 case 'k':
252b5132 8633 break;
4cc782b5
ILT		 8634
8635 case 's':
8636 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8637 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8638 break;
99ad8390 8639#endif
321098a5 8640#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8641 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 8642 case OPTION_64:
8643 {
8644 const char **list, **l;
8645
3e73aa7c
JH		 8646 list = bfd_target_list ();
8647 for (l = list; *l != NULL; l++)
8620418b 8648 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8649 || strcmp (*l, "coff-x86-64") == 0
8650 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 8651 || strcmp (*l, "pei-x86-64") == 0
8652 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 8653 {
8654 default_arch = "x86_64";
8655 break;
8656 }
3e73aa7c 8657 if (*l == NULL)
2b5d6a91 8658 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8659 free (list);
8660 }
8661 break;
8662#endif
252b5132 8663
351f65ca 8664#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8665 case OPTION_X32:
351f65ca
L		 8666 if (IS_ELF)
8667 {
8668 const char **list, **l;
8669
8670 list = bfd_target_list ();
8671 for (l = list; *l != NULL; l++)
8672 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8673 {
8674 default_arch = "x86_64:32";
8675 break;
8676 }
8677 if (*l == NULL)
2b5d6a91 8678 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8679 free (list);
8680 }
8681 else
8682 as_fatal (_("32bit x86_64 is only supported for ELF"));
8683 break;
8684#endif
8685
6e0b89ee
AM		 8686 case OPTION_32:
8687 default_arch = "i386";
8688 break;
8689
b3b91714
AM		 8690 case OPTION_DIVIDE:
8691#ifdef SVR4_COMMENT_CHARS
8692 {
8693 char *n, *t;
8694 const char *s;
8695
8696 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8697 t = n;
8698 for (s = i386_comment_chars; *s != '\0'; s++)
8699 if (*s != '/')
8700 *t++ = *s;
8701 *t = '\0';
8702 i386_comment_chars = n;
8703 }
8704#endif
8705 break;
8706
9103f4f4 8707 case OPTION_MARCH:
6305a203
L		 8708 arch = xstrdup (arg);
8709 do
9103f4f4 8710 {
6305a203 8711 if (*arch == '.')
2b5d6a91 8712 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8713 next = strchr (arch, '+');
8714 if (next)
8715 *next++ = '\0';
91d6fa6a 8716 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8717 {
91d6fa6a 8718 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8719 {
6305a203 8720 /* Processor. */
1ded5609
JB		 8721 if (! cpu_arch[j].flags.bitfield.cpui386)
8722 continue;
8723
91d6fa6a 8724 cpu_arch_name = cpu_arch[j].name;
6305a203 8725 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8726 cpu_arch_flags = cpu_arch[j].flags;
8727 cpu_arch_isa = cpu_arch[j].type;
8728 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8729 if (!cpu_arch_tune_set)
8730 {
8731 cpu_arch_tune = cpu_arch_isa;
8732 cpu_arch_tune_flags = cpu_arch_isa_flags;
8733 }
8734 break;
8735 }
91d6fa6a
NC		 8736 else if (*cpu_arch [j].name == '.'
8737 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8738 {
8739 /* ISA entension. */
8740 i386_cpu_flags flags;
309d3373 8741
49021df2 8742 if (!cpu_arch[j].negated)
309d3373 8743 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8744 cpu_arch[j].flags);
309d3373
JB		 8745 else
8746 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8747 cpu_arch[j].flags);
0dfbf9d7 8748 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8749 {
8750 if (cpu_sub_arch_name)
8751 {
8752 char *name = cpu_sub_arch_name;
8753 cpu_sub_arch_name = concat (name,
91d6fa6a 8754 cpu_arch[j].name,
1bf57e9f 8755 (const char *) NULL);
6305a203
L		 8756 free (name);
8757 }
8758 else
91d6fa6a 8759 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8760 cpu_arch_flags = flags;
a586129e 8761 cpu_arch_isa_flags = flags;
6305a203
L		 8762 }
8763 break;
ccc9c027 8764 }
9103f4f4 8765 }
6305a203 8766
91d6fa6a 8767 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8768 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8769
8770 arch = next;
9103f4f4 8771 }
6305a203 8772 while (next != NULL );
9103f4f4
L		 8773 break;
8774
8775 case OPTION_MTUNE:
8776 if (*arg == '.')
2b5d6a91 8777 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8778 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8779 {
91d6fa6a 8780 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8781 {
ccc9c027 8782 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8783 cpu_arch_tune = cpu_arch [j].type;
8784 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8785 break;
8786 }
8787 }
91d6fa6a 8788 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8789 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8790 break;
8791
1efbbeb4
L		 8792 case OPTION_MMNEMONIC:
8793 if (strcasecmp (arg, "att") == 0)
8794 intel_mnemonic = 0;
8795 else if (strcasecmp (arg, "intel") == 0)
8796 intel_mnemonic = 1;
8797 else
2b5d6a91 8798 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8799 break;
8800
8801 case OPTION_MSYNTAX:
8802 if (strcasecmp (arg, "att") == 0)
8803 intel_syntax = 0;
8804 else if (strcasecmp (arg, "intel") == 0)
8805 intel_syntax = 1;
8806 else
2b5d6a91 8807 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8808 break;
8809
8810 case OPTION_MINDEX_REG:
8811 allow_index_reg = 1;
8812 break;
8813
8814 case OPTION_MNAKED_REG:
8815 allow_naked_reg = 1;
8816 break;
8817
8818 case OPTION_MOLD_GCC:
8819 old_gcc = 1;
1efbbeb4
L		 8820 break;
8821
c0f3af97
L		 8822 case OPTION_MSSE2AVX:
8823 sse2avx = 1;
8824 break;
8825
daf50ae7
L		 8826 case OPTION_MSSE_CHECK:
8827 if (strcasecmp (arg, "error") == 0)
7bab8ab5 8828 sse_check = check_error;
daf50ae7 8829 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 8830 sse_check = check_warning;
daf50ae7 8831 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 8832 sse_check = check_none;
daf50ae7 8833 else
2b5d6a91 8834 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8835 break;
8836
7bab8ab5
JB		 8837 case OPTION_MOPERAND_CHECK:
8838 if (strcasecmp (arg, "error") == 0)
8839 operand_check = check_error;
8840 else if (strcasecmp (arg, "warning") == 0)
8841 operand_check = check_warning;
8842 else if (strcasecmp (arg, "none") == 0)
8843 operand_check = check_none;
8844 else
8845 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
8846 break;
8847
539f890d
L		 8848 case OPTION_MAVXSCALAR:
8849 if (strcasecmp (arg, "128") == 0)
8850 avxscalar = vex128;
8851 else if (strcasecmp (arg, "256") == 0)
8852 avxscalar = vex256;
8853 else
2b5d6a91 8854 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8855 break;
8856
252b5132
RH		 8857 default:
8858 return 0;
8859 }
8860 return 1;
8861}
8862
8a2c8fef
L		 8863#define MESSAGE_TEMPLATE \
8864" "
8865
8866static void
1ded5609 8867show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8868{
8869 static char message[] = MESSAGE_TEMPLATE;
8870 char *start = message + 27;
8871 char *p;
8872 int size = sizeof (MESSAGE_TEMPLATE);
8873 int left;
8874 const char *name;
8875 int len;
8876 unsigned int j;
8877
8878 p = start;
8879 left = size - (start - message);
8880 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8881 {
8882 /* Should it be skipped? */
8883 if (cpu_arch [j].skip)
8884 continue;
8885
8886 name = cpu_arch [j].name;
8887 len = cpu_arch [j].len;
8888 if (*name == '.')
8889 {
8890 /* It is an extension. Skip if we aren't asked to show it. */
8891 if (ext)
8892 {
8893 name++;
8894 len--;
8895 }
8896 else
8897 continue;
8898 }
8899 else if (ext)
8900 {
8901 /* It is an processor. Skip if we show only extension. */
8902 continue;
8903 }
1ded5609
JB		 8904 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8905 {
8906 /* It is an impossible processor - skip. */
8907 continue;
8908 }
8a2c8fef
L		 8909
8910 /* Reserve 2 spaces for ", " or ",\0" */
8911 left -= len + 2;
8912
8913 /* Check if there is any room. */
8914 if (left >= 0)
8915 {
8916 if (p != start)
8917 {
8918 *p++ = ',';
8919 *p++ = ' ';
8920 }
8921 p = mempcpy (p, name, len);
8922 }
8923 else
8924 {
8925 /* Output the current message now and start a new one. */
8926 *p++ = ',';
8927 *p = '\0';
8928 fprintf (stream, "%s\n", message);
8929 p = start;
8930 left = size - (start - message) - len - 2;
8d63c93e 8931
8a2c8fef
L		 8932 gas_assert (left >= 0);
8933
8934 p = mempcpy (p, name, len);
8935 }
8936 }
8937
8938 *p = '\0';
8939 fprintf (stream, "%s\n", message);
8940}
8941
252b5132 8942void
8a2c8fef 8943md_show_usage (FILE *stream)
252b5132 8944{
4cc782b5
ILT		 8945#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8946 fprintf (stream, _("\
a38cf1db
AM		 8947 -Q ignored\n\
8948 -V print assembler version number\n\
b3b91714
AM		 8949 -k ignored\n"));
8950#endif
8951 fprintf (stream, _("\
12b55ccc 8952 -n Do not optimize code alignment\n\
b3b91714
AM		 8953 -q quieten some warnings\n"));
8954#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8955 fprintf (stream, _("\
a38cf1db 8956 -s ignored\n"));
b3b91714 8957#endif
321098a5
L		 8958#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8959 || defined (TE_PE) || defined (TE_PEP))
751d281c 8960 fprintf (stream, _("\
570561f7 8961 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8962#endif
b3b91714
AM		 8963#ifdef SVR4_COMMENT_CHARS
8964 fprintf (stream, _("\
8965 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8966#else
8967 fprintf (stream, _("\
b3b91714 8968 --divide ignored\n"));
4cc782b5 8969#endif
9103f4f4 8970 fprintf (stream, _("\
6305a203 8971 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8972 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8973 show_arch (stream, 0, 1);
8a2c8fef
L		 8974 fprintf (stream, _("\
8975 EXTENSION is combination of:\n"));
1ded5609 8976 show_arch (stream, 1, 0);
6305a203 8977 fprintf (stream, _("\
8a2c8fef 8978 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8979 show_arch (stream, 0, 0);
ba104c83 8980 fprintf (stream, _("\
c0f3af97
L		 8981 -msse2avx encode SSE instructions with VEX prefix\n"));
8982 fprintf (stream, _("\
daf50ae7
L		 8983 -msse-check=[none|error|warning]\n\
8984 check SSE instructions\n"));
8985 fprintf (stream, _("\
7bab8ab5
JB		 8986 -moperand-check=[none|error|warning]\n\
8987 check operand combinations for validity\n"));
8988 fprintf (stream, _("\
539f890d
L		 8989 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8990 length\n"));
8991 fprintf (stream, _("\
ba104c83
L		 8992 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8993 fprintf (stream, _("\
8994 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8995 fprintf (stream, _("\
8996 -mindex-reg support pseudo index registers\n"));
8997 fprintf (stream, _("\
8998 -mnaked-reg don't require `%%' prefix for registers\n"));
8999 fprintf (stream, _("\
9000 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 9001}
9002
3e73aa7c 9003#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9004 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9005 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9006
9007/* Pick the target format to use. */
9008
47926f60 9009const char *
e3bb37b5 9010i386_target_format (void)
252b5132 9011{
351f65ca
L		 9012 if (!strncmp (default_arch, "x86_64", 6))
9013 {
9014 update_code_flag (CODE_64BIT, 1);
9015 if (default_arch[6] == '\0')
7f56bc95 9016 x86_elf_abi = X86_64_ABI;
351f65ca 9017 else
7f56bc95 9018 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9019 }
3e73aa7c 9020 else if (!strcmp (default_arch, "i386"))
78f12dd3 9021 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9022 else
2b5d6a91 9023 as_fatal (_("unknown architecture"));
89507696
JB		 9024
9025 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9026 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9027 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9028 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9029
252b5132
RH		 9030 switch (OUTPUT_FLAVOR)
9031 {
9384f2ff 9032#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9033 case bfd_target_aout_flavour:
47926f60 9034 return AOUT_TARGET_FORMAT;
4c63da97 9035#endif
9384f2ff
AM		 9036#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9037# if defined (TE_PE) || defined (TE_PEP)
9038 case bfd_target_coff_flavour:
9039 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9040# elif defined (TE_GO32)
0561d57c
JK		 9041 case bfd_target_coff_flavour:
9042 return "coff-go32";
9384f2ff 9043# else
252b5132
RH		 9044 case bfd_target_coff_flavour:
9045 return "coff-i386";
9384f2ff 9046# endif
4c63da97 9047#endif
3e73aa7c 9048#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 9049 case bfd_target_elf_flavour:
3e73aa7c 9050 {
351f65ca
L		 9051 const char *format;
9052
9053 switch (x86_elf_abi)
4fa24527 9054 {
351f65ca
L		 9055 default:
9056 format = ELF_TARGET_FORMAT;
9057 break;
7f56bc95 9058 case X86_64_ABI:
351f65ca 9059 use_rela_relocations = 1;
4fa24527 9060 object_64bit = 1;
351f65ca
L		 9061 format = ELF_TARGET_FORMAT64;
9062 break;
7f56bc95 9063 case X86_64_X32_ABI:
4fa24527 9064 use_rela_relocations = 1;
351f65ca 9065 object_64bit = 1;
862be3fb 9066 disallow_64bit_reloc = 1;
351f65ca
L		 9067 format = ELF_TARGET_FORMAT32;
9068 break;
4fa24527 9069 }
3632d14b 9070 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 9071 {
7f56bc95 9072 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 9073 as_fatal (_("Intel L1OM is 64bit only"));
9074 return ELF_TARGET_L1OM_FORMAT;
9075 }
7a9068fe
L		 9076 if (cpu_arch_isa == PROCESSOR_K1OM)
9077 {
9078 if (x86_elf_abi != X86_64_ABI)
9079 as_fatal (_("Intel K1OM is 64bit only"));
9080 return ELF_TARGET_K1OM_FORMAT;
9081 }
8a9036a4 9082 else
351f65ca 9083 return format;
3e73aa7c 9084 }
e57f8c65
TG		 9085#endif
9086#if defined (OBJ_MACH_O)
9087 case bfd_target_mach_o_flavour:
d382c579
TG		 9088 if (flag_code == CODE_64BIT)
9089 {
9090 use_rela_relocations = 1;
9091 object_64bit = 1;
9092 return "mach-o-x86-64";
9093 }
9094 else
9095 return "mach-o-i386";
4c63da97 9096#endif
252b5132
RH		 9097 default:
9098 abort ();
9099 return NULL;
9100 }
9101}
9102
47926f60 9103#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 9104
9105#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 9106void
9107i386_elf_emit_arch_note (void)
a847613f 9108{
718ddfc0 9109 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 9110 {
9111 char *p;
9112 asection *seg = now_seg;
9113 subsegT subseg = now_subseg;
9114 Elf_Internal_Note i_note;
9115 Elf_External_Note e_note;
9116 asection *note_secp;
9117 int len;
9118
9119 /* Create the .note section. */
9120 note_secp = subseg_new (".note", 0);
9121 bfd_set_section_flags (stdoutput,
9122 note_secp,
9123 SEC_HAS_CONTENTS | SEC_READONLY);
9124
9125 /* Process the arch string. */
9126 len = strlen (cpu_arch_name);
9127
9128 i_note.namesz = len + 1;
9129 i_note.descsz = 0;
9130 i_note.type = NT_ARCH;
9131 p = frag_more (sizeof (e_note.namesz));
9132 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
9133 p = frag_more (sizeof (e_note.descsz));
9134 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
9135 p = frag_more (sizeof (e_note.type));
9136 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
9137 p = frag_more (len + 1);
9138 strcpy (p, cpu_arch_name);
9139
9140 frag_align (2, 0, 0);
9141
9142 subseg_set (seg, subseg);
9143 }
9144}
9145#endif
252b5132 9146\f
252b5132 9147symbolS *
7016a5d5 9148md_undefined_symbol (char *name)
252b5132 9149{
18dc2407
ILT		 9150 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
9151 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
9152 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
9153 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 9154 {
9155 if (!GOT_symbol)
9156 {
9157 if (symbol_find (name))
9158 as_bad (_("GOT already in symbol table"));
9159 GOT_symbol = symbol_new (name, undefined_section,
9160 (valueT) 0, &zero_address_frag);
9161 };
9162 return GOT_symbol;
9163 }
252b5132
RH		 9164 return 0;
9165}
9166
9167/* Round up a section size to the appropriate boundary. */
47926f60 9168
252b5132 9169valueT
7016a5d5 9170md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 9171{
4c63da97
AM		 9172#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9173 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
9174 {
9175 /* For a.out, force the section size to be aligned. If we don't do
9176 this, BFD will align it for us, but it will not write out the
9177 final bytes of the section. This may be a bug in BFD, but it is
9178 easier to fix it here since that is how the other a.out targets
9179 work. */
9180 int align;
9181
9182 align = bfd_get_section_alignment (stdoutput, segment);
9183 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
9184 }
252b5132
RH		 9185#endif
9186
9187 return size;
9188}
9189
9190/* On the i386, PC-relative offsets are relative to the start of the
9191 next instruction. That is, the address of the offset, plus its
9192 size, since the offset is always the last part of the insn. */
9193
9194long
e3bb37b5 9195md_pcrel_from (fixS *fixP)
252b5132
RH		 9196{
9197 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
9198}
9199
9200#ifndef I386COFF
9201
9202static void
e3bb37b5 9203s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 9204{
29b0f896 9205 int temp;
252b5132 9206
8a75718c
JB		 9207#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9208 if (IS_ELF)
9209 obj_elf_section_change_hook ();
9210#endif
252b5132
RH		 9211 temp = get_absolute_expression ();
9212 subseg_set (bss_section, (subsegT) temp);
9213 demand_empty_rest_of_line ();
9214}
9215
9216#endif
9217
252b5132 9218void
e3bb37b5 9219i386_validate_fix (fixS *fixp)
252b5132
RH		 9220{
9221 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
9222 {
23df1078
JH		 9223 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
9224 {
4fa24527 9225 if (!object_64bit)
23df1078
JH		 9226 abort ();
9227 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
9228 }
9229 else
9230 {
4fa24527 9231 if (!object_64bit)
d6ab8113
JB		 9232 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
9233 else
9234 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 9235 }
252b5132
RH		 9236 fixp->fx_subsy = 0;
9237 }
9238}
9239
252b5132 9240arelent *
7016a5d5 9241tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 9242{
9243 arelent *rel;
9244 bfd_reloc_code_real_type code;
9245
9246 switch (fixp->fx_r_type)
9247 {
8fd4256d
L		 9248 case BFD_RELOC_SIZE32:
9249 case BFD_RELOC_SIZE64:
9250 if (S_IS_DEFINED (fixp->fx_addsy)
9251 && !S_IS_EXTERNAL (fixp->fx_addsy))
9252 {
9253 /* Resolve size relocation against local symbol to size of
9254 the symbol plus addend. */
9255 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
9256 if (fixp->fx_r_type == BFD_RELOC_SIZE32
9257 && !fits_in_unsigned_long (value))
9258 as_bad_where (fixp->fx_file, fixp->fx_line,
9259 _("symbol size computation overflow"));
9260 fixp->fx_addsy = NULL;
9261 fixp->fx_subsy = NULL;
9262 md_apply_fix (fixp, (valueT *) &value, NULL);
9263 return NULL;
9264 }
9265
3e73aa7c
JH		 9266 case BFD_RELOC_X86_64_PLT32:
9267 case BFD_RELOC_X86_64_GOT32:
9268 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 9269 case BFD_RELOC_386_PLT32:
9270 case BFD_RELOC_386_GOT32:
9271 case BFD_RELOC_386_GOTOFF:
9272 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 9273 case BFD_RELOC_386_TLS_GD:
9274 case BFD_RELOC_386_TLS_LDM:
9275 case BFD_RELOC_386_TLS_LDO_32:
9276 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9277 case BFD_RELOC_386_TLS_IE:
9278 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 9279 case BFD_RELOC_386_TLS_LE_32:
9280 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 9281 case BFD_RELOC_386_TLS_GOTDESC:
9282 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 9283 case BFD_RELOC_X86_64_TLSGD:
9284 case BFD_RELOC_X86_64_TLSLD:
9285 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9286 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 9287 case BFD_RELOC_X86_64_GOTTPOFF:
9288 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 9289 case BFD_RELOC_X86_64_TPOFF64:
9290 case BFD_RELOC_X86_64_GOTOFF64:
9291 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 9292 case BFD_RELOC_X86_64_GOT64:
9293 case BFD_RELOC_X86_64_GOTPCREL64:
9294 case BFD_RELOC_X86_64_GOTPC64:
9295 case BFD_RELOC_X86_64_GOTPLT64:
9296 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 9297 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9298 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 9299 case BFD_RELOC_RVA:
9300 case BFD_RELOC_VTABLE_ENTRY:
9301 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 9302#ifdef TE_PE
9303 case BFD_RELOC_32_SECREL:
9304#endif
252b5132
RH		 9305 code = fixp->fx_r_type;
9306 break;
dbbaec26
L		 9307 case BFD_RELOC_X86_64_32S:
9308 if (!fixp->fx_pcrel)
9309 {
9310 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9311 code = fixp->fx_r_type;
9312 break;
9313 }
252b5132 9314 default:
93382f6d 9315 if (fixp->fx_pcrel)
252b5132 9316 {
93382f6d
AM		 9317 switch (fixp->fx_size)
9318 {
9319 default:
b091f402
AM		 9320 as_bad_where (fixp->fx_file, fixp->fx_line,
9321 _("can not do %d byte pc-relative relocation"),
9322 fixp->fx_size);
93382f6d
AM		 9323 code = BFD_RELOC_32_PCREL;
9324 break;
9325 case 1: code = BFD_RELOC_8_PCREL; break;
9326 case 2: code = BFD_RELOC_16_PCREL; break;
9327 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 9328#ifdef BFD64
9329 case 8: code = BFD_RELOC_64_PCREL; break;
9330#endif
93382f6d
AM		 9331 }
9332 }
9333 else
9334 {
9335 switch (fixp->fx_size)
9336 {
9337 default:
b091f402
AM		 9338 as_bad_where (fixp->fx_file, fixp->fx_line,
9339 _("can not do %d byte relocation"),
9340 fixp->fx_size);
93382f6d
AM		 9341 code = BFD_RELOC_32;
9342 break;
9343 case 1: code = BFD_RELOC_8; break;
9344 case 2: code = BFD_RELOC_16; break;
9345 case 4: code = BFD_RELOC_32; break;
937149dd 9346#ifdef BFD64
3e73aa7c 9347 case 8: code = BFD_RELOC_64; break;
937149dd 9348#endif
93382f6d 9349 }
252b5132
RH		 9350 }
9351 break;
9352 }
252b5132 9353
d182319b
JB		 9354 if ((code == BFD_RELOC_32
9355 || code == BFD_RELOC_32_PCREL
9356 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9357 && GOT_symbol
9358 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9359 {
4fa24527 9360 if (!object_64bit)
d6ab8113
JB		 9361 code = BFD_RELOC_386_GOTPC;
9362 else
9363 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9364 }
7b81dfbb
AJ		 9365 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9366 && GOT_symbol
9367 && fixp->fx_addsy == GOT_symbol)
9368 {
9369 code = BFD_RELOC_X86_64_GOTPC64;
9370 }
252b5132
RH		 9371
9372 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9373 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9374 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9375
9376 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9377
3e73aa7c
JH		 9378 if (!use_rela_relocations)
9379 {
9380 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9381 vtable entry to be used in the relocation's section offset. */
9382 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9383 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9384#if defined (OBJ_COFF) && defined (TE_PE)
9385 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9386 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9387 else
9388#endif
c6682705 9389 rel->addend = 0;
3e73aa7c
JH		 9390 }
9391 /* Use the rela in 64bit mode. */
252b5132 9392 else
3e73aa7c 9393 {
862be3fb
L		 9394 if (disallow_64bit_reloc)
9395 switch (code)
9396 {
862be3fb
L		 9397 case BFD_RELOC_X86_64_DTPOFF64:
9398 case BFD_RELOC_X86_64_TPOFF64:
9399 case BFD_RELOC_64_PCREL:
9400 case BFD_RELOC_X86_64_GOTOFF64:
9401 case BFD_RELOC_X86_64_GOT64:
9402 case BFD_RELOC_X86_64_GOTPCREL64:
9403 case BFD_RELOC_X86_64_GOTPC64:
9404 case BFD_RELOC_X86_64_GOTPLT64:
9405 case BFD_RELOC_X86_64_PLTOFF64:
9406 as_bad_where (fixp->fx_file, fixp->fx_line,
9407 _("cannot represent relocation type %s in x32 mode"),
9408 bfd_get_reloc_code_name (code));
9409 break;
9410 default:
9411 break;
9412 }
9413
062cd5e7
AS		 9414 if (!fixp->fx_pcrel)
9415 rel->addend = fixp->fx_offset;
9416 else
9417 switch (code)
9418 {
9419 case BFD_RELOC_X86_64_PLT32:
9420 case BFD_RELOC_X86_64_GOT32:
9421 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9422 case BFD_RELOC_X86_64_TLSGD:
9423 case BFD_RELOC_X86_64_TLSLD:
9424 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9425 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9426 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9427 rel->addend = fixp->fx_offset - fixp->fx_size;
9428 break;
9429 default:
9430 rel->addend = (section->vma
9431 - fixp->fx_size
9432 + fixp->fx_addnumber
9433 + md_pcrel_from (fixp));
9434 break;
9435 }
3e73aa7c
JH		 9436 }
9437
252b5132
RH		 9438 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9439 if (rel->howto == NULL)
9440 {
9441 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9442 _("cannot represent relocation type %s"),
252b5132
RH		 9443 bfd_get_reloc_code_name (code));
9444 /* Set howto to a garbage value so that we can keep going. */
9445 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9446 gas_assert (rel->howto != NULL);
252b5132
RH		 9447 }
9448
9449 return rel;
9450}
9451
ee86248c 9452#include "tc-i386-intel.c"
54cfded0 9453
a60de03c
JB		 9454void
9455tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9456{
a60de03c
JB		 9457 int saved_naked_reg;
9458 char saved_register_dot;
54cfded0 9459
a60de03c
JB		 9460 saved_naked_reg = allow_naked_reg;
9461 allow_naked_reg = 1;
9462 saved_register_dot = register_chars['.'];
9463 register_chars['.'] = '.';
9464 allow_pseudo_reg = 1;
9465 expression_and_evaluate (exp);
9466 allow_pseudo_reg = 0;
9467 register_chars['.'] = saved_register_dot;
9468 allow_naked_reg = saved_naked_reg;
9469
e96d56a1 9470 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9471 {
a60de03c
JB		 9472 if ((addressT) exp->X_add_number < i386_regtab_size)
9473 {
9474 exp->X_op = O_constant;
9475 exp->X_add_number = i386_regtab[exp->X_add_number]
9476 .dw2_regnum[flag_code >> 1];
9477 }
9478 else
9479 exp->X_op = O_illegal;
54cfded0 9480 }
54cfded0
AM		 9481}
9482
9483void
9484tc_x86_frame_initial_instructions (void)
9485{
a60de03c
JB		 9486 static unsigned int sp_regno[2];
9487
9488 if (!sp_regno[flag_code >> 1])
9489 {
9490 char *saved_input = input_line_pointer;
9491 char sp[][4] = {"esp", "rsp"};
9492 expressionS exp;
a4447b93 9493
a60de03c
JB		 9494 input_line_pointer = sp[flag_code >> 1];
9495 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9496 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9497 sp_regno[flag_code >> 1] = exp.X_add_number;
9498 input_line_pointer = saved_input;
9499 }
a4447b93 9500
61ff971f
L		 9501 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9502 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9503}
d2b2c203 9504
d7921315
L		 9505int
9506x86_dwarf2_addr_size (void)
9507{
9508#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9509 if (x86_elf_abi == X86_64_X32_ABI)
9510 return 4;
9511#endif
9512 return bfd_arch_bits_per_address (stdoutput) / 8;
9513}
9514
d2b2c203
DJ		 9515int
9516i386_elf_section_type (const char *str, size_t len)
9517{
9518 if (flag_code == CODE_64BIT
9519 && len == sizeof ("unwind") - 1
9520 && strncmp (str, "unwind", 6) == 0)
9521 return SHT_X86_64_UNWIND;
9522
9523 return -1;
9524}
bb41ade5 9525
ad5fec3b
EB		 9526#ifdef TE_SOLARIS
9527void
9528i386_solaris_fix_up_eh_frame (segT sec)
9529{
9530 if (flag_code == CODE_64BIT)
9531 elf_section_type (sec) = SHT_X86_64_UNWIND;
9532}
9533#endif
9534
bb41ade5
AM		 9535#ifdef TE_PE
9536void
9537tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9538{
91d6fa6a 9539 expressionS exp;
bb41ade5 9540
91d6fa6a
NC		 9541 exp.X_op = O_secrel;
9542 exp.X_add_symbol = symbol;
9543 exp.X_add_number = 0;
9544 emit_expr (&exp, size);
bb41ade5
AM		 9545}
9546#endif
3b22753a
L		 9547
9548#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9549/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9550
01e1a5bc 9551bfd_vma
3b22753a
L		 9552x86_64_section_letter (int letter, char **ptr_msg)
9553{
9554 if (flag_code == CODE_64BIT)
9555 {
9556 if (letter == 'l')
9557 return SHF_X86_64_LARGE;
9558
8f3bae45 9559 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9560 }
3b22753a 9561 else
8f3bae45 9562 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9563 return -1;
9564}
9565
01e1a5bc 9566bfd_vma
3b22753a
L		 9567x86_64_section_word (char *str, size_t len)
9568{
8620418b 9569 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9570 return SHF_X86_64_LARGE;
9571
9572 return -1;
9573}
9574
9575static void
9576handle_large_common (int small ATTRIBUTE_UNUSED)
9577{
9578 if (flag_code != CODE_64BIT)
9579 {
9580 s_comm_internal (0, elf_common_parse);
9581 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9582 }
9583 else
9584 {
9585 static segT lbss_section;
9586 asection *saved_com_section_ptr = elf_com_section_ptr;
9587 asection *saved_bss_section = bss_section;
9588
9589 if (lbss_section == NULL)
9590 {
9591 flagword applicable;
9592 segT seg = now_seg;
9593 subsegT subseg = now_subseg;
9594
9595 /* The .lbss section is for local .largecomm symbols. */
9596 lbss_section = subseg_new (".lbss", 0);
9597 applicable = bfd_applicable_section_flags (stdoutput);
9598 bfd_set_section_flags (stdoutput, lbss_section,
9599 applicable & SEC_ALLOC);
9600 seg_info (lbss_section)->bss = 1;
9601
9602 subseg_set (seg, subseg);
9603 }
9604
9605 elf_com_section_ptr = &_bfd_elf_large_com_section;
9606 bss_section = lbss_section;
9607
9608 s_comm_internal (0, elf_common_parse);
9609
9610 elf_com_section_ptr = saved_com_section_ptr;
9611 bss_section = saved_bss_section;
9612 }
9613}
9614#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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