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* dwarf2expr.c (execute_stack_op) <DW_OP_shr>: Unconditionally
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
314a59d5 185static void handle_quad (int);
17d4e2a2 186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
c0f3af97
L		 190/* VEX prefix. */
191typedef struct
192{
193 /* VEX prefix is either 2 byte or 3 byte. */
194 unsigned char bytes[3];
195 unsigned int length;
196 /* Destination or source register specifier. */
197 const reg_entry *register_specifier;
198} vex_prefix;
199
252b5132 200/* 'md_assemble ()' gathers together information and puts it into a
47926f60 201 i386_insn. */
252b5132 202
520dc8e8
AM		 203union i386_op
204 {
205 expressionS *disps;
206 expressionS *imms;
207 const reg_entry *regs;
208 };
209
a65babc9
L		 210enum i386_error
211 {
86e026a4 212 operand_size_mismatch,
a65babc9
L		 213 operand_type_mismatch,
214 register_type_mismatch,
215 number_of_operands_mismatch,
216 invalid_instruction_suffix,
217 bad_imm4,
218 old_gcc_only,
219 unsupported_with_intel_mnemonic,
220 unsupported_syntax,
221 unsupported
222 };
223
252b5132
RH		 224struct _i386_insn
225 {
47926f60 226 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 227 insn_template tm;
252b5132 228
7d5e4556
L		 229 /* SUFFIX holds the instruction size suffix for byte, word, dword
230 or qword, if given. */
252b5132
RH		 231 char suffix;
232
47926f60 233 /* OPERANDS gives the number of given operands. */
252b5132
RH		 234 unsigned int operands;
235
236 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
237 of given register, displacement, memory operands and immediate
47926f60 238 operands. */
252b5132
RH		 239 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
240
241 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 242 use OP[i] for the corresponding operand. */
40fb9820 243 i386_operand_type types[MAX_OPERANDS];
252b5132 244
520dc8e8
AM		 245 /* Displacement expression, immediate expression, or register for each
246 operand. */
247 union i386_op op[MAX_OPERANDS];
252b5132 248
3e73aa7c
JH		 249 /* Flags for operands. */
250 unsigned int flags[MAX_OPERANDS];
251#define Operand_PCrel 1
252
252b5132 253 /* Relocation type for operand */
f86103b7 254 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 255
252b5132
RH		 256 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
257 the base index byte below. */
258 const reg_entry *base_reg;
259 const reg_entry *index_reg;
260 unsigned int log2_scale_factor;
261
262 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 263 explicit segment overrides are given. */
ce8a8b2f 264 const seg_entry *seg[2];
252b5132
RH		 265
266 /* PREFIX holds all the given prefix opcodes (usually null).
267 PREFIXES is the number of prefix opcodes. */
268 unsigned int prefixes;
269 unsigned char prefix[MAX_PREFIXES];
270
271 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 272 addressing modes of this insn are encoded. */
252b5132 273 modrm_byte rm;
3e73aa7c 274 rex_byte rex;
252b5132 275 sib_byte sib;
c0f3af97 276 vex_prefix vex;
b6169b20
L		 277
278 /* Swap operand in encoding. */
4473e004 279 unsigned int swap_operand;
891edac4 280
f8a5c266
L		 281 /* Force 32bit displacement in encoding. */
282 unsigned int disp32_encoding;
283
891edac4 284 /* Error message. */
a65babc9 285 enum i386_error error;
252b5132
RH		 286 };
287
288typedef struct _i386_insn i386_insn;
289
290/* List of chars besides those in app.c:symbol_chars that can start an
291 operand. Used to prevent the scrubber eating vital white-space. */
32137342 292const char extra_symbol_chars[] = "*%-(["
252b5132 293#ifdef LEX_AT
32137342
NC		 294 "@"
295#endif
296#ifdef LEX_QM
297 "?"
252b5132 298#endif
32137342 299 ;
252b5132 300
29b0f896
AM		 301#if (defined (TE_I386AIX) \
302 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 303 && !defined (TE_GNU) \
29b0f896 304 && !defined (TE_LINUX) \
32137342 305 && !defined (TE_NETWARE) \
29b0f896 306 && !defined (TE_FreeBSD) \
5b806d27 307 && !defined (TE_DragonFly) \
29b0f896 308 && !defined (TE_NetBSD)))
252b5132 309/* This array holds the chars that always start a comment. If the
b3b91714
AM		 310 pre-processor is disabled, these aren't very useful. The option
311 --divide will remove '/' from this list. */
312const char *i386_comment_chars = "#/";
313#define SVR4_COMMENT_CHARS 1
252b5132 314#define PREFIX_SEPARATOR '\\'
252b5132 315
b3b91714
AM		 316#else
317const char *i386_comment_chars = "#";
318#define PREFIX_SEPARATOR '/'
319#endif
320
252b5132
RH		 321/* This array holds the chars that only start a comment at the beginning of
322 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 323 .line and .file directives will appear in the pre-processed output.
324 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 325 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 326 #NO_APP at the beginning of its output.
327 Also note that comments started like this one will always work if
252b5132 328 '/' isn't otherwise defined. */
b3b91714 329const char line_comment_chars[] = "#/";
252b5132 330
63a0b638 331const char line_separator_chars[] = ";";
252b5132 332
ce8a8b2f
AM		 333/* Chars that can be used to separate mant from exp in floating point
334 nums. */
252b5132
RH		 335const char EXP_CHARS[] = "eE";
336
ce8a8b2f
AM		 337/* Chars that mean this number is a floating point constant
338 As in 0f12.456
339 or 0d1.2345e12. */
252b5132
RH		 340const char FLT_CHARS[] = "fFdDxX";
341
ce8a8b2f 342/* Tables for lexical analysis. */
252b5132
RH		 343static char mnemonic_chars[256];
344static char register_chars[256];
345static char operand_chars[256];
346static char identifier_chars[256];
347static char digit_chars[256];
348
ce8a8b2f 349/* Lexical macros. */
252b5132
RH		 350#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
351#define is_operand_char(x) (operand_chars[(unsigned char) x])
352#define is_register_char(x) (register_chars[(unsigned char) x])
353#define is_space_char(x) ((x) == ' ')
354#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
355#define is_digit_char(x) (digit_chars[(unsigned char) x])
356
0234cb7c 357/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 358static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
359
360/* md_assemble() always leaves the strings it's passed unaltered. To
361 effect this we maintain a stack of saved characters that we've smashed
362 with '\0's (indicating end of strings for various sub-fields of the
47926f60 363 assembler instruction). */
252b5132 364static char save_stack[32];
ce8a8b2f 365static char *save_stack_p;
252b5132
RH		 366#define END_STRING_AND_SAVE(s) \
367 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
368#define RESTORE_END_STRING(s) \
369 do { *(s) = *--save_stack_p; } while (0)
370
47926f60 371/* The instruction we're assembling. */
252b5132
RH		 372static i386_insn i;
373
374/* Possible templates for current insn. */
375static const templates *current_templates;
376
31b2323c
L		 377/* Per instruction expressionS buffers: max displacements & immediates. */
378static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
379static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 380
47926f60 381/* Current operand we are working on. */
ee86248c 382static int this_operand = -1;
252b5132 383
3e73aa7c
JH		 384/* We support four different modes. FLAG_CODE variable is used to distinguish
385 these. */
386
387enum flag_code {
388 CODE_32BIT,
389 CODE_16BIT,
390 CODE_64BIT };
391
392static enum flag_code flag_code;
4fa24527 393static unsigned int object_64bit;
862be3fb 394static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 395static int use_rela_relocations = 0;
396
7af8ed2d
NC		 397#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
398 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
399 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
400
351f65ca
L		 401/* The ELF ABI to use. */
402enum x86_elf_abi
403{
404 I386_ABI,
7f56bc95
L		 405 X86_64_ABI,
406 X86_64_X32_ABI
351f65ca
L		 407};
408
409static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 410#endif
351f65ca 411
3e73aa7c 412/* The names used to print error messages. */
b77a7acd 413static const char *flag_code_names[] =
3e73aa7c
JH		 414 {
415 "32",
416 "16",
417 "64"
418 };
252b5132 419
47926f60
KH		 420/* 1 for intel syntax,
421 0 if att syntax. */
422static int intel_syntax = 0;
252b5132 423
1efbbeb4
L		 424/* 1 for intel mnemonic,
425 0 if att mnemonic. */
426static int intel_mnemonic = !SYSV386_COMPAT;
427
5209009a 428/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 429static int old_gcc = OLDGCC_COMPAT;
430
a60de03c
JB		 431/* 1 if pseudo registers are permitted. */
432static int allow_pseudo_reg = 0;
433
47926f60
KH		 434/* 1 if register prefix % not required. */
435static int allow_naked_reg = 0;
252b5132 436
ba104c83 437/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 438static int allow_index_reg = 0;
439
daf50ae7
L		 440static enum
441 {
442 sse_check_none = 0,
443 sse_check_warning,
444 sse_check_error
445 }
446sse_check;
447
2ca3ace5
L		 448/* Register prefix used for error message. */
449static const char *register_prefix = "%";
450
47926f60
KH		 451/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
452 leave, push, and pop instructions so that gcc has the same stack
453 frame as in 32 bit mode. */
454static char stackop_size = '\0';
eecb386c 455
12b55ccc
L		 456/* Non-zero to optimize code alignment. */
457int optimize_align_code = 1;
458
47926f60
KH		 459/* Non-zero to quieten some warnings. */
460static int quiet_warnings = 0;
a38cf1db 461
47926f60
KH		 462/* CPU name. */
463static const char *cpu_arch_name = NULL;
6305a203 464static char *cpu_sub_arch_name = NULL;
a38cf1db 465
47926f60 466/* CPU feature flags. */
40fb9820
L		 467static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
468
ccc9c027
L		 469/* If we have selected a cpu we are generating instructions for. */
470static int cpu_arch_tune_set = 0;
471
9103f4f4 472/* Cpu we are generating instructions for. */
fbf3f584 473enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 474
475/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 476static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 477
ccc9c027 478/* CPU instruction set architecture used. */
fbf3f584 479enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 480
9103f4f4 481/* CPU feature flags of instruction set architecture used. */
fbf3f584 482i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 483
fddf5b5b
AM		 484/* If set, conditional jumps are not automatically promoted to handle
485 larger than a byte offset. */
486static unsigned int no_cond_jump_promotion = 0;
487
c0f3af97
L		 488/* Encode SSE instructions with VEX prefix. */
489static unsigned int sse2avx;
490
539f890d
L		 491/* Encode scalar AVX instructions with specific vector length. */
492static enum
493 {
494 vex128 = 0,
495 vex256
496 } avxscalar;
497
29b0f896 498/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 499static symbolS *GOT_symbol;
29b0f896 500
a4447b93
RH		 501/* The dwarf2 return column, adjusted for 32 or 64 bit. */
502unsigned int x86_dwarf2_return_column;
503
504/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
505int x86_cie_data_alignment;
506
252b5132 507/* Interface to relax_segment.
fddf5b5b
AM		 508 There are 3 major relax states for 386 jump insns because the
509 different types of jumps add different sizes to frags when we're
510 figuring out what sort of jump to choose to reach a given label. */
252b5132 511
47926f60 512/* Types. */
93c2a809
AM		 513#define UNCOND_JUMP 0
514#define COND_JUMP 1
515#define COND_JUMP86 2
fddf5b5b 516
47926f60 517/* Sizes. */
252b5132
RH		 518#define CODE16 1
519#define SMALL 0
29b0f896 520#define SMALL16 (SMALL | CODE16)
252b5132 521#define BIG 2
29b0f896 522#define BIG16 (BIG | CODE16)
252b5132
RH		 523
524#ifndef INLINE
525#ifdef __GNUC__
526#define INLINE __inline__
527#else
528#define INLINE
529#endif
530#endif
531
fddf5b5b
AM		 532#define ENCODE_RELAX_STATE(type, size) \
533 ((relax_substateT) (((type) << 2) | (size)))
534#define TYPE_FROM_RELAX_STATE(s) \
535 ((s) >> 2)
536#define DISP_SIZE_FROM_RELAX_STATE(s) \
537 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 538
539/* This table is used by relax_frag to promote short jumps to long
540 ones where necessary. SMALL (short) jumps may be promoted to BIG
541 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
542 don't allow a short jump in a 32 bit code segment to be promoted to
543 a 16 bit offset jump because it's slower (requires data size
544 prefix), and doesn't work, unless the destination is in the bottom
545 64k of the code segment (The top 16 bits of eip are zeroed). */
546
547const relax_typeS md_relax_table[] =
548{
24eab124
AM		 549 /* The fields are:
550 1) most positive reach of this state,
551 2) most negative reach of this state,
93c2a809 552 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 553 4) which index into the table to try if we can't fit into this one. */
252b5132 554
fddf5b5b 555 /* UNCOND_JUMP states. */
93c2a809
AM		 556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
558 /* dword jmp adds 4 bytes to frag:
559 0 extra opcode bytes, 4 displacement bytes. */
252b5132 560 {0, 0, 4, 0},
93c2a809
AM		 561 /* word jmp adds 2 byte2 to frag:
562 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 563 {0, 0, 2, 0},
564
93c2a809
AM		 565 /* COND_JUMP states. */
566 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
568 /* dword conditionals adds 5 bytes to frag:
569 1 extra opcode byte, 4 displacement bytes. */
570 {0, 0, 5, 0},
fddf5b5b 571 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 572 1 extra opcode byte, 2 displacement bytes. */
573 {0, 0, 3, 0},
574
575 /* COND_JUMP86 states. */
576 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
577 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
578 /* dword conditionals adds 5 bytes to frag:
579 1 extra opcode byte, 4 displacement bytes. */
580 {0, 0, 5, 0},
581 /* word conditionals add 4 bytes to frag:
582 1 displacement byte and a 3 byte long branch insn. */
583 {0, 0, 4, 0}
252b5132
RH		 584};
585
9103f4f4
L		 586static const arch_entry cpu_arch[] =
587{
89507696
JB		 588 /* Do not replace the first two entries - i386_target_format()
589 relies on them being there in this order. */
8a2c8fef 590 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 591 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 592 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 593 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 594 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 595 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 596 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 597 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 598 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 599 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 601 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 603 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 605 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 607 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 609 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 611 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 613 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 615 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 617 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 619 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 621 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 623 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 625 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 627 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 629 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 631 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 633 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 635 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 637 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 639 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 641 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 642 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 643 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 645 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 646 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 647 CPU_AMDFAM10_FLAGS, 0, 0 },
af2f724e 648 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER,
22109423 649 CPU_BDVER1_FLAGS, 0, 0 },
af2f724e
QN		 650 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BDVER,
651 CPU_BDVER2_FLAGS, 0, 0 },
8a2c8fef 652 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 653 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 654 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 655 CPU_287_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 657 CPU_387_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 659 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 660 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 661 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 662 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 663 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 664 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 665 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 667 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 669 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 670 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 671 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 673 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 674 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 675 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 677 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 679 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 680 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 681 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 683 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 684 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 685 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 687 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 688 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 689 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 690 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 691 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 693 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 695 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 696 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 697 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 698 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 699 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 700 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 701 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 702 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 703 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 704 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 705 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 706 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 707 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 708 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 709 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 711 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 713 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 715 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 717 CPU_CLFLUSH_FLAGS, 0, 0 },
718 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
719 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 721 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 723 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 725 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 727 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 729 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 731 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 732 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 733 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 735 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 737 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 738 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
739 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 740 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
741 CPU_TBM_FLAGS, 0, 0 },
e413e4e9
AM		 742};
743
704209c0 744#ifdef I386COFF
a6c24e68
NC		 745/* Like s_lcomm_internal in gas/read.c but the alignment string
746 is allowed to be optional. */
747
748static symbolS *
749pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
750{
751 addressT align = 0;
752
753 SKIP_WHITESPACE ();
754
7ab9ffdd 755 if (needs_align
a6c24e68
NC		 756 && *input_line_pointer == ',')
757 {
758 align = parse_align (needs_align - 1);
7ab9ffdd 759
a6c24e68
NC		 760 if (align == (addressT) -1)
761 return NULL;
762 }
763 else
764 {
765 if (size >= 8)
766 align = 3;
767 else if (size >= 4)
768 align = 2;
769 else if (size >= 2)
770 align = 1;
771 else
772 align = 0;
773 }
774
775 bss_alloc (symbolP, size, align);
776 return symbolP;
777}
778
704209c0 779static void
a6c24e68
NC		 780pe_lcomm (int needs_align)
781{
782 s_comm_internal (needs_align * 2, pe_lcomm_internal);
783}
704209c0 784#endif
a6c24e68 785
29b0f896
AM		 786const pseudo_typeS md_pseudo_table[] =
787{
788#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
789 {"align", s_align_bytes, 0},
790#else
791 {"align", s_align_ptwo, 0},
792#endif
793 {"arch", set_cpu_arch, 0},
794#ifndef I386COFF
795 {"bss", s_bss, 0},
a6c24e68
NC		 796#else
797 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 798#endif
799 {"ffloat", float_cons, 'f'},
800 {"dfloat", float_cons, 'd'},
801 {"tfloat", float_cons, 'x'},
802 {"value", cons, 2},
d182319b 803 {"slong", signed_cons, 4},
29b0f896
AM		 804 {"noopt", s_ignore, 0},
805 {"optim", s_ignore, 0},
806 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
807 {"code16", set_code_flag, CODE_16BIT},
808 {"code32", set_code_flag, CODE_32BIT},
809 {"code64", set_code_flag, CODE_64BIT},
810 {"intel_syntax", set_intel_syntax, 1},
811 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 812 {"intel_mnemonic", set_intel_mnemonic, 1},
813 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 814 {"allow_index_reg", set_allow_index_reg, 1},
815 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 816 {"sse_check", set_sse_check, 0},
3b22753a
L		 817#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
818 {"largecomm", handle_large_common, 0},
314a59d5 819 {"quad", handle_quad, 8},
07a53e5c 820#else
e3bb37b5 821 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 822 {"loc", dwarf2_directive_loc, 0},
823 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 824#endif
6482c264
NC		 825#ifdef TE_PE
826 {"secrel32", pe_directive_secrel, 0},
827#endif
29b0f896
AM		 828 {0, 0, 0}
829};
830
831/* For interface with expression (). */
832extern char *input_line_pointer;
833
834/* Hash table for instruction mnemonic lookup. */
835static struct hash_control *op_hash;
836
837/* Hash table for register lookup. */
838static struct hash_control *reg_hash;
839\f
252b5132 840void
e3bb37b5 841i386_align_code (fragS *fragP, int count)
252b5132 842{
ce8a8b2f
AM		 843 /* Various efficient no-op patterns for aligning code labels.
844 Note: Don't try to assemble the instructions in the comments.
845 0L and 0w are not legal. */
252b5132
RH		 846 static const char f32_1[] =
847 {0x90}; /* nop */
848 static const char f32_2[] =
ccc9c027 849 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 850 static const char f32_3[] =
851 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
852 static const char f32_4[] =
853 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
854 static const char f32_5[] =
855 {0x90, /* nop */
856 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
857 static const char f32_6[] =
858 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
859 static const char f32_7[] =
860 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
861 static const char f32_8[] =
862 {0x90, /* nop */
863 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
864 static const char f32_9[] =
865 {0x89,0xf6, /* movl %esi,%esi */
866 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
867 static const char f32_10[] =
868 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
869 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
870 static const char f32_11[] =
871 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
872 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
873 static const char f32_12[] =
874 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
875 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
876 static const char f32_13[] =
877 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
878 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
879 static const char f32_14[] =
880 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
881 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 882 static const char f16_3[] =
883 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 884 static const char f16_4[] =
885 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
886 static const char f16_5[] =
887 {0x90, /* nop */
888 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
889 static const char f16_6[] =
890 {0x89,0xf6, /* mov %si,%si */
891 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
892 static const char f16_7[] =
893 {0x8d,0x74,0x00, /* lea 0(%si),%si */
894 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
895 static const char f16_8[] =
896 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
897 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 898 static const char jump_31[] =
899 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
900 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
901 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
902 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 903 static const char *const f32_patt[] = {
904 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 905 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 906 };
907 static const char *const f16_patt[] = {
76bc74dc 908 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 909 };
ccc9c027
L		 910 /* nopl (%[re]ax) */
911 static const char alt_3[] =
912 {0x0f,0x1f,0x00};
913 /* nopl 0(%[re]ax) */
914 static const char alt_4[] =
915 {0x0f,0x1f,0x40,0x00};
916 /* nopl 0(%[re]ax,%[re]ax,1) */
917 static const char alt_5[] =
918 {0x0f,0x1f,0x44,0x00,0x00};
919 /* nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_6[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00};
922 /* nopl 0L(%[re]ax) */
923 static const char alt_7[] =
924 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 /* nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_8[] =
927 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
928 /* nopw 0L(%[re]ax,%[re]ax,1) */
929 static const char alt_9[] =
930 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_10[] =
933 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
934 /* data16
935 nopw %cs:0L(%[re]ax,%[re]ax,1) */
936 static const char alt_long_11[] =
937 {0x66,
938 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
939 /* data16
940 data16
941 nopw %cs:0L(%[re]ax,%[re]ax,1) */
942 static const char alt_long_12[] =
943 {0x66,
944 0x66,
945 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
946 /* data16
947 data16
948 data16
949 nopw %cs:0L(%[re]ax,%[re]ax,1) */
950 static const char alt_long_13[] =
951 {0x66,
952 0x66,
953 0x66,
954 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
955 /* data16
956 data16
957 data16
958 data16
959 nopw %cs:0L(%[re]ax,%[re]ax,1) */
960 static const char alt_long_14[] =
961 {0x66,
962 0x66,
963 0x66,
964 0x66,
965 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
966 /* data16
967 data16
968 data16
969 data16
970 data16
971 nopw %cs:0L(%[re]ax,%[re]ax,1) */
972 static const char alt_long_15[] =
973 {0x66,
974 0x66,
975 0x66,
976 0x66,
977 0x66,
978 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* nopl 0(%[re]ax,%[re]ax,1)
980 nopw 0(%[re]ax,%[re]ax,1) */
981 static const char alt_short_11[] =
982 {0x0f,0x1f,0x44,0x00,0x00,
983 0x66,0x0f,0x1f,0x44,0x00,0x00};
984 /* nopw 0(%[re]ax,%[re]ax,1)
985 nopw 0(%[re]ax,%[re]ax,1) */
986 static const char alt_short_12[] =
987 {0x66,0x0f,0x1f,0x44,0x00,0x00,
988 0x66,0x0f,0x1f,0x44,0x00,0x00};
989 /* nopw 0(%[re]ax,%[re]ax,1)
990 nopl 0L(%[re]ax) */
991 static const char alt_short_13[] =
992 {0x66,0x0f,0x1f,0x44,0x00,0x00,
993 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
994 /* nopl 0L(%[re]ax)
995 nopl 0L(%[re]ax) */
996 static const char alt_short_14[] =
997 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
998 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
999 /* nopl 0L(%[re]ax)
1000 nopl 0L(%[re]ax,%[re]ax,1) */
1001 static const char alt_short_15[] =
1002 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1003 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1004 static const char *const alt_short_patt[] = {
1005 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1006 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1007 alt_short_14, alt_short_15
1008 };
1009 static const char *const alt_long_patt[] = {
1010 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1011 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1012 alt_long_14, alt_long_15
1013 };
252b5132 1014
76bc74dc
L		 1015 /* Only align for at least a positive non-zero boundary. */
1016 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1017 return;
3e73aa7c 1018
ccc9c027
L		 1019 /* We need to decide which NOP sequence to use for 32bit and
1020 64bit. When -mtune= is used:
4eed87de 1021
76bc74dc
L		 1022 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1023 PROCESSOR_GENERIC32, f32_patt will be used.
1024 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1025 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1026 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1027 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
af2f724e 1028 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER, alt_short_patt
69dd9865 1029 will be used.
ccc9c027 1030
76bc74dc 1031 When -mtune= isn't used, alt_long_patt will be used if
22109423 1032 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1033 be used.
ccc9c027
L		 1034
1035 When -march= or .arch is used, we can't use anything beyond
1036 cpu_arch_isa_flags. */
1037
1038 if (flag_code == CODE_16BIT)
1039 {
ccc9c027 1040 if (count > 8)
33fef721 1041 {
76bc74dc
L		 1042 memcpy (fragP->fr_literal + fragP->fr_fix,
1043 jump_31, count);
1044 /* Adjust jump offset. */
1045 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1046 }
76bc74dc
L		 1047 else
1048 memcpy (fragP->fr_literal + fragP->fr_fix,
1049 f16_patt[count - 1], count);
252b5132 1050 }
33fef721 1051 else
ccc9c027
L		 1052 {
1053 const char *const *patt = NULL;
1054
fbf3f584 1055 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1056 {
1057 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1058 switch (cpu_arch_tune)
1059 {
1060 case PROCESSOR_UNKNOWN:
1061 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1062 optimize with nops. */
1063 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1064 patt = alt_long_patt;
ccc9c027
L		 1065 else
1066 patt = f32_patt;
1067 break;
ccc9c027
L		 1068 case PROCESSOR_PENTIUM4:
1069 case PROCESSOR_NOCONA:
ef05d495 1070 case PROCESSOR_CORE:
76bc74dc 1071 case PROCESSOR_CORE2:
bd5295b2 1072 case PROCESSOR_COREI7:
3632d14b 1073 case PROCESSOR_L1OM:
76bc74dc
L		 1074 case PROCESSOR_GENERIC64:
1075 patt = alt_long_patt;
1076 break;
ccc9c027
L		 1077 case PROCESSOR_K6:
1078 case PROCESSOR_ATHLON:
1079 case PROCESSOR_K8:
4eed87de 1080 case PROCESSOR_AMDFAM10:
af2f724e 1081 case PROCESSOR_BDVER:
ccc9c027
L		 1082 patt = alt_short_patt;
1083 break;
76bc74dc 1084 case PROCESSOR_I386:
ccc9c027
L		 1085 case PROCESSOR_I486:
1086 case PROCESSOR_PENTIUM:
2dde1948 1087 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1088 case PROCESSOR_GENERIC32:
1089 patt = f32_patt;
1090 break;
4eed87de 1091 }
ccc9c027
L		 1092 }
1093 else
1094 {
fbf3f584 1095 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1096 {
1097 case PROCESSOR_UNKNOWN:
e6a14101 1098 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1099 PROCESSOR_UNKNOWN. */
1100 abort ();
1101 break;
1102
76bc74dc 1103 case PROCESSOR_I386:
ccc9c027
L		 1104 case PROCESSOR_I486:
1105 case PROCESSOR_PENTIUM:
ccc9c027
L		 1106 case PROCESSOR_K6:
1107 case PROCESSOR_ATHLON:
1108 case PROCESSOR_K8:
4eed87de 1109 case PROCESSOR_AMDFAM10:
af2f724e 1110 case PROCESSOR_BDVER:
ccc9c027
L		 1111 case PROCESSOR_GENERIC32:
1112 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1113 with nops. */
1114 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1115 patt = alt_short_patt;
1116 else
1117 patt = f32_patt;
1118 break;
76bc74dc
L		 1119 case PROCESSOR_PENTIUMPRO:
1120 case PROCESSOR_PENTIUM4:
1121 case PROCESSOR_NOCONA:
1122 case PROCESSOR_CORE:
ef05d495 1123 case PROCESSOR_CORE2:
bd5295b2 1124 case PROCESSOR_COREI7:
3632d14b 1125 case PROCESSOR_L1OM:
22109423 1126 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1127 patt = alt_long_patt;
1128 else
1129 patt = f32_patt;
1130 break;
1131 case PROCESSOR_GENERIC64:
76bc74dc 1132 patt = alt_long_patt;
ccc9c027 1133 break;
4eed87de 1134 }
ccc9c027
L		 1135 }
1136
76bc74dc
L		 1137 if (patt == f32_patt)
1138 {
1139 /* If the padding is less than 15 bytes, we use the normal
1140 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1141 its offset. */
1142 int limit;
76ba9986 1143
711eedef
L		 1144 /* For 64bit, the limit is 3 bytes. */
1145 if (flag_code == CODE_64BIT
1146 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1147 limit = 3;
1148 else
1149 limit = 15;
1150 if (count < limit)
76bc74dc
L		 1151 memcpy (fragP->fr_literal + fragP->fr_fix,
1152 patt[count - 1], count);
1153 else
1154 {
1155 memcpy (fragP->fr_literal + fragP->fr_fix,
1156 jump_31, count);
1157 /* Adjust jump offset. */
1158 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1159 }
1160 }
1161 else
1162 {
1163 /* Maximum length of an instruction is 15 byte. If the
1164 padding is greater than 15 bytes and we don't use jump,
1165 we have to break it into smaller pieces. */
1166 int padding = count;
1167 while (padding > 15)
1168 {
1169 padding -= 15;
1170 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1171 patt [14], 15);
1172 }
1173
1174 if (padding)
1175 memcpy (fragP->fr_literal + fragP->fr_fix,
1176 patt [padding - 1], padding);
1177 }
ccc9c027 1178 }
33fef721 1179 fragP->fr_var = count;
252b5132
RH		 1180}
1181
c6fb90c8 1182static INLINE int
0dfbf9d7 1183operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1184{
0dfbf9d7 1185 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1186 {
1187 case 3:
0dfbf9d7 1188 if (x->array[2])
c6fb90c8
L		 1189 return 0;
1190 case 2:
0dfbf9d7 1191 if (x->array[1])
c6fb90c8
L		 1192 return 0;
1193 case 1:
0dfbf9d7 1194 return !x->array[0];
c6fb90c8
L		 1195 default:
1196 abort ();
1197 }
40fb9820
L		 1198}
1199
c6fb90c8 1200static INLINE void
0dfbf9d7 1201operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1202{
0dfbf9d7 1203 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1204 {
1205 case 3:
0dfbf9d7 1206 x->array[2] = v;
c6fb90c8 1207 case 2:
0dfbf9d7 1208 x->array[1] = v;
c6fb90c8 1209 case 1:
0dfbf9d7 1210 x->array[0] = v;
c6fb90c8
L		 1211 break;
1212 default:
1213 abort ();
1214 }
1215}
40fb9820 1216
c6fb90c8 1217static INLINE int
0dfbf9d7
L		 1218operand_type_equal (const union i386_operand_type *x,
1219 const union i386_operand_type *y)
c6fb90c8 1220{
0dfbf9d7 1221 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1222 {
1223 case 3:
0dfbf9d7 1224 if (x->array[2] != y->array[2])
c6fb90c8
L		 1225 return 0;
1226 case 2:
0dfbf9d7 1227 if (x->array[1] != y->array[1])
c6fb90c8
L		 1228 return 0;
1229 case 1:
0dfbf9d7 1230 return x->array[0] == y->array[0];
c6fb90c8
L		 1231 break;
1232 default:
1233 abort ();
1234 }
1235}
40fb9820 1236
0dfbf9d7
L		 1237static INLINE int
1238cpu_flags_all_zero (const union i386_cpu_flags *x)
1239{
1240 switch (ARRAY_SIZE(x->array))
1241 {
1242 case 3:
1243 if (x->array[2])
1244 return 0;
1245 case 2:
1246 if (x->array[1])
1247 return 0;
1248 case 1:
1249 return !x->array[0];
1250 default:
1251 abort ();
1252 }
1253}
1254
1255static INLINE void
1256cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1257{
1258 switch (ARRAY_SIZE(x->array))
1259 {
1260 case 3:
1261 x->array[2] = v;
1262 case 2:
1263 x->array[1] = v;
1264 case 1:
1265 x->array[0] = v;
1266 break;
1267 default:
1268 abort ();
1269 }
1270}
1271
1272static INLINE int
1273cpu_flags_equal (const union i386_cpu_flags *x,
1274 const union i386_cpu_flags *y)
1275{
1276 switch (ARRAY_SIZE(x->array))
1277 {
1278 case 3:
1279 if (x->array[2] != y->array[2])
1280 return 0;
1281 case 2:
1282 if (x->array[1] != y->array[1])
1283 return 0;
1284 case 1:
1285 return x->array[0] == y->array[0];
1286 break;
1287 default:
1288 abort ();
1289 }
1290}
c6fb90c8
L		 1291
1292static INLINE int
1293cpu_flags_check_cpu64 (i386_cpu_flags f)
1294{
1295 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1296 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1297}
1298
c6fb90c8
L		 1299static INLINE i386_cpu_flags
1300cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1301{
c6fb90c8
L		 1302 switch (ARRAY_SIZE (x.array))
1303 {
1304 case 3:
1305 x.array [2] &= y.array [2];
1306 case 2:
1307 x.array [1] &= y.array [1];
1308 case 1:
1309 x.array [0] &= y.array [0];
1310 break;
1311 default:
1312 abort ();
1313 }
1314 return x;
1315}
40fb9820 1316
c6fb90c8
L		 1317static INLINE i386_cpu_flags
1318cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1319{
c6fb90c8 1320 switch (ARRAY_SIZE (x.array))
40fb9820 1321 {
c6fb90c8
L		 1322 case 3:
1323 x.array [2] |= y.array [2];
1324 case 2:
1325 x.array [1] |= y.array [1];
1326 case 1:
1327 x.array [0] |= y.array [0];
40fb9820
L		 1328 break;
1329 default:
1330 abort ();
1331 }
40fb9820
L		 1332 return x;
1333}
1334
309d3373
JB		 1335static INLINE i386_cpu_flags
1336cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1337{
1338 switch (ARRAY_SIZE (x.array))
1339 {
1340 case 3:
1341 x.array [2] &= ~y.array [2];
1342 case 2:
1343 x.array [1] &= ~y.array [1];
1344 case 1:
1345 x.array [0] &= ~y.array [0];
1346 break;
1347 default:
1348 abort ();
1349 }
1350 return x;
1351}
1352
c0f3af97
L		 1353#define CPU_FLAGS_ARCH_MATCH 0x1
1354#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1355#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1356#define CPU_FLAGS_PCLMUL_MATCH 0x8
1357#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1358
a5ff0eb2 1359#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1360 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1361 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1362#define CPU_FLAGS_PERFECT_MATCH \
1363 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1364
1365/* Return CPU flags match bits. */
3629bb00 1366
40fb9820 1367static int
d3ce72d0 1368cpu_flags_match (const insn_template *t)
40fb9820 1369{
c0f3af97
L		 1370 i386_cpu_flags x = t->cpu_flags;
1371 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1372
1373 x.bitfield.cpu64 = 0;
1374 x.bitfield.cpuno64 = 0;
1375
0dfbf9d7 1376 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1377 {
1378 /* This instruction is available on all archs. */
1379 match |= CPU_FLAGS_32BIT_MATCH;
1380 }
3629bb00
L		 1381 else
1382 {
c0f3af97 1383 /* This instruction is available only on some archs. */
3629bb00
L		 1384 i386_cpu_flags cpu = cpu_arch_flags;
1385
1386 cpu.bitfield.cpu64 = 0;
1387 cpu.bitfield.cpuno64 = 0;
1388 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1389 if (!cpu_flags_all_zero (&cpu))
1390 {
a5ff0eb2
L		 1391 if (x.bitfield.cpuavx)
1392 {
ce2f5b3c 1393 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1394 if (cpu.bitfield.cpuavx)
1395 {
1396 /* Check SSE2AVX. */
1397 if (!t->opcode_modifier.sse2avx|| sse2avx)
1398 {
1399 match |= (CPU_FLAGS_ARCH_MATCH
1400 | CPU_FLAGS_AVX_MATCH);
1401 /* Check AES. */
1402 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1403 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1404 /* Check PCLMUL. */
1405 if (!x.bitfield.cpupclmul
1406 || cpu.bitfield.cpupclmul)
1407 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1408 }
1409 }
1410 else
1411 match |= CPU_FLAGS_ARCH_MATCH;
1412 }
1413 else
c0f3af97
L		 1414 match |= CPU_FLAGS_32BIT_MATCH;
1415 }
3629bb00 1416 }
c0f3af97 1417 return match;
40fb9820
L		 1418}
1419
c6fb90c8
L		 1420static INLINE i386_operand_type
1421operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1422{
c6fb90c8
L		 1423 switch (ARRAY_SIZE (x.array))
1424 {
1425 case 3:
1426 x.array [2] &= y.array [2];
1427 case 2:
1428 x.array [1] &= y.array [1];
1429 case 1:
1430 x.array [0] &= y.array [0];
1431 break;
1432 default:
1433 abort ();
1434 }
1435 return x;
40fb9820
L		 1436}
1437
c6fb90c8
L		 1438static INLINE i386_operand_type
1439operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1440{
c6fb90c8 1441 switch (ARRAY_SIZE (x.array))
40fb9820 1442 {
c6fb90c8
L		 1443 case 3:
1444 x.array [2] |= y.array [2];
1445 case 2:
1446 x.array [1] |= y.array [1];
1447 case 1:
1448 x.array [0] |= y.array [0];
40fb9820
L		 1449 break;
1450 default:
1451 abort ();
1452 }
c6fb90c8
L		 1453 return x;
1454}
40fb9820 1455
c6fb90c8
L		 1456static INLINE i386_operand_type
1457operand_type_xor (i386_operand_type x, i386_operand_type y)
1458{
1459 switch (ARRAY_SIZE (x.array))
1460 {
1461 case 3:
1462 x.array [2] ^= y.array [2];
1463 case 2:
1464 x.array [1] ^= y.array [1];
1465 case 1:
1466 x.array [0] ^= y.array [0];
1467 break;
1468 default:
1469 abort ();
1470 }
40fb9820
L		 1471 return x;
1472}
1473
1474static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1475static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1476static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1477static const i386_operand_type inoutportreg
1478 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1479static const i386_operand_type reg16_inoutportreg
1480 = OPERAND_TYPE_REG16_INOUTPORTREG;
1481static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1482static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1483static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1484static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1485static const i386_operand_type anydisp
1486 = OPERAND_TYPE_ANYDISP;
40fb9820 1487static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1488static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1489static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1490static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1491static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1492static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1493static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1494static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1495static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1496static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1497static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1498static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1499
1500enum operand_type
1501{
1502 reg,
40fb9820
L		 1503 imm,
1504 disp,
1505 anymem
1506};
1507
c6fb90c8 1508static INLINE int
40fb9820
L		 1509operand_type_check (i386_operand_type t, enum operand_type c)
1510{
1511 switch (c)
1512 {
1513 case reg:
1514 return (t.bitfield.reg8
1515 || t.bitfield.reg16
1516 || t.bitfield.reg32
1517 || t.bitfield.reg64);
1518
40fb9820
L		 1519 case imm:
1520 return (t.bitfield.imm8
1521 || t.bitfield.imm8s
1522 || t.bitfield.imm16
1523 || t.bitfield.imm32
1524 || t.bitfield.imm32s
1525 || t.bitfield.imm64);
1526
1527 case disp:
1528 return (t.bitfield.disp8
1529 || t.bitfield.disp16
1530 || t.bitfield.disp32
1531 || t.bitfield.disp32s
1532 || t.bitfield.disp64);
1533
1534 case anymem:
1535 return (t.bitfield.disp8
1536 || t.bitfield.disp16
1537 || t.bitfield.disp32
1538 || t.bitfield.disp32s
1539 || t.bitfield.disp64
1540 || t.bitfield.baseindex);
1541
1542 default:
1543 abort ();
1544 }
2cfe26b6
AM		 1545
1546 return 0;
40fb9820
L		 1547}
1548
5c07affc
L		 1549/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1550 operand J for instruction template T. */
1551
1552static INLINE int
d3ce72d0 1553match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1554{
1555 return !((i.types[j].bitfield.byte
1556 && !t->operand_types[j].bitfield.byte)
1557 || (i.types[j].bitfield.word
1558 && !t->operand_types[j].bitfield.word)
1559 || (i.types[j].bitfield.dword
1560 && !t->operand_types[j].bitfield.dword)
1561 || (i.types[j].bitfield.qword
1562 && !t->operand_types[j].bitfield.qword));
1563}
1564
1565/* Return 1 if there is no conflict in any size on operand J for
1566 instruction template T. */
1567
1568static INLINE int
d3ce72d0 1569match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1570{
1571 return (match_reg_size (t, j)
1572 && !((i.types[j].bitfield.unspecified
1573 && !t->operand_types[j].bitfield.unspecified)
1574 || (i.types[j].bitfield.fword
1575 && !t->operand_types[j].bitfield.fword)
1576 || (i.types[j].bitfield.tbyte
1577 && !t->operand_types[j].bitfield.tbyte)
1578 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1579 && !t->operand_types[j].bitfield.xmmword)
1580 || (i.types[j].bitfield.ymmword
1581 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1582}
1583
1584/* Return 1 if there is no size conflict on any operands for
1585 instruction template T. */
1586
1587static INLINE int
d3ce72d0 1588operand_size_match (const insn_template *t)
5c07affc
L		 1589{
1590 unsigned int j;
1591 int match = 1;
1592
1593 /* Don't check jump instructions. */
1594 if (t->opcode_modifier.jump
1595 || t->opcode_modifier.jumpbyte
1596 || t->opcode_modifier.jumpdword
1597 || t->opcode_modifier.jumpintersegment)
1598 return match;
1599
1600 /* Check memory and accumulator operand size. */
1601 for (j = 0; j < i.operands; j++)
1602 {
1603 if (t->operand_types[j].bitfield.anysize)
1604 continue;
1605
1606 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1607 {
1608 match = 0;
1609 break;
1610 }
1611
1612 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1613 {
1614 match = 0;
1615 break;
1616 }
1617 }
1618
891edac4 1619 if (match)
5c07affc 1620 return match;
891edac4
L		 1621 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1622 {
1623mismatch:
86e026a4 1624 i.error = operand_size_mismatch;
891edac4
L		 1625 return 0;
1626 }
5c07affc
L		 1627
1628 /* Check reverse. */
9c2799c2 1629 gas_assert (i.operands == 2);
5c07affc
L		 1630
1631 match = 1;
1632 for (j = 0; j < 2; j++)
1633 {
1634 if (t->operand_types[j].bitfield.acc
1635 && !match_reg_size (t, j ? 0 : 1))
891edac4 1636 goto mismatch;
5c07affc
L		 1637
1638 if (i.types[j].bitfield.mem
1639 && !match_mem_size (t, j ? 0 : 1))
891edac4 1640 goto mismatch;
5c07affc
L		 1641 }
1642
1643 return match;
1644}
1645
c6fb90c8 1646static INLINE int
40fb9820
L		 1647operand_type_match (i386_operand_type overlap,
1648 i386_operand_type given)
1649{
1650 i386_operand_type temp = overlap;
1651
1652 temp.bitfield.jumpabsolute = 0;
7d5e4556 1653 temp.bitfield.unspecified = 0;
5c07affc
L		 1654 temp.bitfield.byte = 0;
1655 temp.bitfield.word = 0;
1656 temp.bitfield.dword = 0;
1657 temp.bitfield.fword = 0;
1658 temp.bitfield.qword = 0;
1659 temp.bitfield.tbyte = 0;
1660 temp.bitfield.xmmword = 0;
c0f3af97 1661 temp.bitfield.ymmword = 0;
0dfbf9d7 1662 if (operand_type_all_zero (&temp))
891edac4 1663 goto mismatch;
40fb9820 1664
891edac4
L		 1665 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1666 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1667 return 1;
1668
1669mismatch:
a65babc9 1670 i.error = operand_type_mismatch;
891edac4 1671 return 0;
40fb9820
L		 1672}
1673
7d5e4556 1674/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1675 unless the expected operand type register overlap is null.
1676 Note that Acc in a template matches every size of reg. */
1677
c6fb90c8 1678static INLINE int
40fb9820
L		 1679operand_type_register_match (i386_operand_type m0,
1680 i386_operand_type g0,
1681 i386_operand_type t0,
1682 i386_operand_type m1,
1683 i386_operand_type g1,
1684 i386_operand_type t1)
1685{
1686 if (!operand_type_check (g0, reg))
1687 return 1;
1688
1689 if (!operand_type_check (g1, reg))
1690 return 1;
1691
1692 if (g0.bitfield.reg8 == g1.bitfield.reg8
1693 && g0.bitfield.reg16 == g1.bitfield.reg16
1694 && g0.bitfield.reg32 == g1.bitfield.reg32
1695 && g0.bitfield.reg64 == g1.bitfield.reg64)
1696 return 1;
1697
1698 if (m0.bitfield.acc)
1699 {
1700 t0.bitfield.reg8 = 1;
1701 t0.bitfield.reg16 = 1;
1702 t0.bitfield.reg32 = 1;
1703 t0.bitfield.reg64 = 1;
1704 }
1705
1706 if (m1.bitfield.acc)
1707 {
1708 t1.bitfield.reg8 = 1;
1709 t1.bitfield.reg16 = 1;
1710 t1.bitfield.reg32 = 1;
1711 t1.bitfield.reg64 = 1;
1712 }
1713
891edac4
L		 1714 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1715 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1716 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1717 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1718 return 1;
1719
a65babc9 1720 i.error = register_type_mismatch;
891edac4
L		 1721
1722 return 0;
40fb9820
L		 1723}
1724
252b5132 1725static INLINE unsigned int
40fb9820 1726mode_from_disp_size (i386_operand_type t)
252b5132 1727{
40fb9820
L		 1728 if (t.bitfield.disp8)
1729 return 1;
1730 else if (t.bitfield.disp16
1731 || t.bitfield.disp32
1732 || t.bitfield.disp32s)
1733 return 2;
1734 else
1735 return 0;
252b5132
RH		 1736}
1737
1738static INLINE int
e3bb37b5 1739fits_in_signed_byte (offsetT num)
252b5132
RH		 1740{
1741 return (num >= -128) && (num <= 127);
47926f60 1742}
252b5132
RH		 1743
1744static INLINE int
e3bb37b5 1745fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1746{
1747 return (num & 0xff) == num;
47926f60 1748}
252b5132
RH		 1749
1750static INLINE int
e3bb37b5 1751fits_in_unsigned_word (offsetT num)
252b5132
RH		 1752{
1753 return (num & 0xffff) == num;
47926f60 1754}
252b5132
RH		 1755
1756static INLINE int
e3bb37b5 1757fits_in_signed_word (offsetT num)
252b5132
RH		 1758{
1759 return (-32768 <= num) && (num <= 32767);
47926f60 1760}
2a962e6d 1761
3e73aa7c 1762static INLINE int
e3bb37b5 1763fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1764{
1765#ifndef BFD64
1766 return 1;
1767#else
1768 return (!(((offsetT) -1 << 31) & num)
1769 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1770#endif
1771} /* fits_in_signed_long() */
2a962e6d 1772
3e73aa7c 1773static INLINE int
e3bb37b5 1774fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1775{
1776#ifndef BFD64
1777 return 1;
1778#else
1779 return (num & (((offsetT) 2 << 31) - 1)) == num;
1780#endif
1781} /* fits_in_unsigned_long() */
252b5132 1782
a683cc34
SP		 1783static INLINE int
1784fits_in_imm4 (offsetT num)
1785{
1786 return (num & 0xf) == num;
1787}
1788
40fb9820 1789static i386_operand_type
e3bb37b5 1790smallest_imm_type (offsetT num)
252b5132 1791{
40fb9820 1792 i386_operand_type t;
7ab9ffdd 1793
0dfbf9d7 1794 operand_type_set (&t, 0);
40fb9820
L		 1795 t.bitfield.imm64 = 1;
1796
1797 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1798 {
1799 /* This code is disabled on the 486 because all the Imm1 forms
1800 in the opcode table are slower on the i486. They're the
1801 versions with the implicitly specified single-position
1802 displacement, which has another syntax if you really want to
1803 use that form. */
40fb9820
L		 1804 t.bitfield.imm1 = 1;
1805 t.bitfield.imm8 = 1;
1806 t.bitfield.imm8s = 1;
1807 t.bitfield.imm16 = 1;
1808 t.bitfield.imm32 = 1;
1809 t.bitfield.imm32s = 1;
1810 }
1811 else if (fits_in_signed_byte (num))
1812 {
1813 t.bitfield.imm8 = 1;
1814 t.bitfield.imm8s = 1;
1815 t.bitfield.imm16 = 1;
1816 t.bitfield.imm32 = 1;
1817 t.bitfield.imm32s = 1;
1818 }
1819 else if (fits_in_unsigned_byte (num))
1820 {
1821 t.bitfield.imm8 = 1;
1822 t.bitfield.imm16 = 1;
1823 t.bitfield.imm32 = 1;
1824 t.bitfield.imm32s = 1;
1825 }
1826 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1827 {
1828 t.bitfield.imm16 = 1;
1829 t.bitfield.imm32 = 1;
1830 t.bitfield.imm32s = 1;
1831 }
1832 else if (fits_in_signed_long (num))
1833 {
1834 t.bitfield.imm32 = 1;
1835 t.bitfield.imm32s = 1;
1836 }
1837 else if (fits_in_unsigned_long (num))
1838 t.bitfield.imm32 = 1;
1839
1840 return t;
47926f60 1841}
252b5132 1842
847f7ad4 1843static offsetT
e3bb37b5 1844offset_in_range (offsetT val, int size)
847f7ad4 1845{
508866be 1846 addressT mask;
ba2adb93 1847
847f7ad4
AM		 1848 switch (size)
1849 {
508866be
L		 1850 case 1: mask = ((addressT) 1 << 8) - 1; break;
1851 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1852 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1853#ifdef BFD64
1854 case 8: mask = ((addressT) 2 << 63) - 1; break;
1855#endif
47926f60 1856 default: abort ();
847f7ad4
AM		 1857 }
1858
9de868bf
L		 1859#ifdef BFD64
1860 /* If BFD64, sign extend val for 32bit address mode. */
1861 if (flag_code != CODE_64BIT
1862 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1863 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1864 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1865#endif
ba2adb93 1866
47926f60 1867 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1868 {
1869 char buf1[40], buf2[40];
1870
1871 sprint_value (buf1, val);
1872 sprint_value (buf2, val & mask);
1873 as_warn (_("%s shortened to %s"), buf1, buf2);
1874 }
1875 return val & mask;
1876}
1877
c32fa91d
L		 1878enum PREFIX_GROUP
1879{
1880 PREFIX_EXIST = 0,
1881 PREFIX_LOCK,
1882 PREFIX_REP,
1883 PREFIX_OTHER
1884};
1885
1886/* Returns
1887 a. PREFIX_EXIST if attempting to add a prefix where one from the
1888 same class already exists.
1889 b. PREFIX_LOCK if lock prefix is added.
1890 c. PREFIX_REP if rep/repne prefix is added.
1891 d. PREFIX_OTHER if other prefix is added.
1892 */
1893
1894static enum PREFIX_GROUP
e3bb37b5 1895add_prefix (unsigned int prefix)
252b5132 1896{
c32fa91d 1897 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1898 unsigned int q;
252b5132 1899
29b0f896
AM		 1900 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1901 && flag_code == CODE_64BIT)
b1905489 1902 {
161a04f6
L		 1903 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1904 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1905 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1906 ret = PREFIX_EXIST;
b1905489
JB		 1907 q = REX_PREFIX;
1908 }
3e73aa7c 1909 else
b1905489
JB		 1910 {
1911 switch (prefix)
1912 {
1913 default:
1914 abort ();
1915
1916 case CS_PREFIX_OPCODE:
1917 case DS_PREFIX_OPCODE:
1918 case ES_PREFIX_OPCODE:
1919 case FS_PREFIX_OPCODE:
1920 case GS_PREFIX_OPCODE:
1921 case SS_PREFIX_OPCODE:
1922 q = SEG_PREFIX;
1923 break;
1924
1925 case REPNE_PREFIX_OPCODE:
1926 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1927 q = REP_PREFIX;
1928 ret = PREFIX_REP;
1929 break;
1930
b1905489 1931 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1932 q = LOCK_PREFIX;
1933 ret = PREFIX_LOCK;
b1905489
JB		 1934 break;
1935
1936 case FWAIT_OPCODE:
1937 q = WAIT_PREFIX;
1938 break;
1939
1940 case ADDR_PREFIX_OPCODE:
1941 q = ADDR_PREFIX;
1942 break;
1943
1944 case DATA_PREFIX_OPCODE:
1945 q = DATA_PREFIX;
1946 break;
1947 }
1948 if (i.prefix[q] != 0)
c32fa91d 1949 ret = PREFIX_EXIST;
b1905489 1950 }
252b5132 1951
b1905489 1952 if (ret)
252b5132 1953 {
b1905489
JB		 1954 if (!i.prefix[q])
1955 ++i.prefixes;
1956 i.prefix[q] |= prefix;
252b5132 1957 }
b1905489
JB		 1958 else
1959 as_bad (_("same type of prefix used twice"));
252b5132 1960
252b5132
RH		 1961 return ret;
1962}
1963
1964static void
78f12dd3 1965update_code_flag (int value, int check)
eecb386c 1966{
78f12dd3
L		 1967 PRINTF_LIKE ((*as_error));
1968
1e9cc1c2 1969 flag_code = (enum flag_code) value;
40fb9820
L		 1970 if (flag_code == CODE_64BIT)
1971 {
1972 cpu_arch_flags.bitfield.cpu64 = 1;
1973 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1974 }
1975 else
1976 {
1977 cpu_arch_flags.bitfield.cpu64 = 0;
1978 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1979 }
1980 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1981 {
78f12dd3
L		 1982 if (check)
1983 as_error = as_fatal;
1984 else
1985 as_error = as_bad;
1986 (*as_error) (_("64bit mode not supported on `%s'."),
1987 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1988 }
40fb9820 1989 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1990 {
78f12dd3
L		 1991 if (check)
1992 as_error = as_fatal;
1993 else
1994 as_error = as_bad;
1995 (*as_error) (_("32bit mode not supported on `%s'."),
1996 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1997 }
eecb386c
AM		 1998 stackop_size = '\0';
1999}
2000
78f12dd3
L		 2001static void
2002set_code_flag (int value)
2003{
2004 update_code_flag (value, 0);
2005}
2006
eecb386c 2007static void
e3bb37b5 2008set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2009{
1e9cc1c2 2010 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2011 if (flag_code != CODE_16BIT)
2012 abort ();
2013 cpu_arch_flags.bitfield.cpu64 = 0;
2014 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2015 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2016}
2017
2018static void
e3bb37b5 2019set_intel_syntax (int syntax_flag)
252b5132
RH		 2020{
2021 /* Find out if register prefixing is specified. */
2022 int ask_naked_reg = 0;
2023
2024 SKIP_WHITESPACE ();
29b0f896 2025 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2026 {
2027 char *string = input_line_pointer;
2028 int e = get_symbol_end ();
2029
47926f60 2030 if (strcmp (string, "prefix") == 0)
252b5132 2031 ask_naked_reg = 1;
47926f60 2032 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2033 ask_naked_reg = -1;
2034 else
d0b47220 2035 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2036 *input_line_pointer = e;
2037 }
2038 demand_empty_rest_of_line ();
c3332e24 2039
252b5132
RH		 2040 intel_syntax = syntax_flag;
2041
2042 if (ask_naked_reg == 0)
f86103b7
AM		 2043 allow_naked_reg = (intel_syntax
2044 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2045 else
2046 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2047
ee86248c 2048 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2049
e4a3b5a4 2050 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2051 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2052 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2053}
2054
1efbbeb4
L		 2055static void
2056set_intel_mnemonic (int mnemonic_flag)
2057{
e1d4d893 2058 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2059}
2060
db51cc60
L		 2061static void
2062set_allow_index_reg (int flag)
2063{
2064 allow_index_reg = flag;
2065}
2066
cb19c032
L		 2067static void
2068set_sse_check (int dummy ATTRIBUTE_UNUSED)
2069{
2070 SKIP_WHITESPACE ();
2071
2072 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2073 {
2074 char *string = input_line_pointer;
2075 int e = get_symbol_end ();
2076
2077 if (strcmp (string, "none") == 0)
2078 sse_check = sse_check_none;
2079 else if (strcmp (string, "warning") == 0)
2080 sse_check = sse_check_warning;
2081 else if (strcmp (string, "error") == 0)
2082 sse_check = sse_check_error;
2083 else
2084 as_bad (_("bad argument to sse_check directive."));
2085 *input_line_pointer = e;
2086 }
2087 else
2088 as_bad (_("missing argument for sse_check directive"));
2089
2090 demand_empty_rest_of_line ();
2091}
2092
8a9036a4
L		 2093static void
2094check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2095 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2096{
2097#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2098 static const char *arch;
2099
2100 /* Intel LIOM is only supported on ELF. */
2101 if (!IS_ELF)
2102 return;
2103
2104 if (!arch)
2105 {
2106 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2107 use default_arch. */
2108 arch = cpu_arch_name;
2109 if (!arch)
2110 arch = default_arch;
2111 }
2112
3632d14b 2113 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2114 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2115 || new_flag.bitfield.cpul1om)
8a9036a4 2116 return;
76ba9986 2117
8a9036a4
L		 2118 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2119#endif
2120}
2121
e413e4e9 2122static void
e3bb37b5 2123set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2124{
47926f60 2125 SKIP_WHITESPACE ();
e413e4e9 2126
29b0f896 2127 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2128 {
2129 char *string = input_line_pointer;
2130 int e = get_symbol_end ();
91d6fa6a 2131 unsigned int j;
40fb9820 2132 i386_cpu_flags flags;
e413e4e9 2133
91d6fa6a 2134 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2135 {
91d6fa6a 2136 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2137 {
91d6fa6a 2138 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2139
5c6af06e
JB		 2140 if (*string != '.')
2141 {
91d6fa6a 2142 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2143 cpu_sub_arch_name = NULL;
91d6fa6a 2144 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2145 if (flag_code == CODE_64BIT)
2146 {
2147 cpu_arch_flags.bitfield.cpu64 = 1;
2148 cpu_arch_flags.bitfield.cpuno64 = 0;
2149 }
2150 else
2151 {
2152 cpu_arch_flags.bitfield.cpu64 = 0;
2153 cpu_arch_flags.bitfield.cpuno64 = 1;
2154 }
91d6fa6a
NC		 2155 cpu_arch_isa = cpu_arch[j].type;
2156 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2157 if (!cpu_arch_tune_set)
2158 {
2159 cpu_arch_tune = cpu_arch_isa;
2160 cpu_arch_tune_flags = cpu_arch_isa_flags;
2161 }
5c6af06e
JB		 2162 break;
2163 }
40fb9820 2164
22109423 2165 if (!cpu_arch[j].negated)
309d3373 2166 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2167 cpu_arch[j].flags);
309d3373
JB		 2168 else
2169 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2170 cpu_arch[j].flags);
0dfbf9d7 2171 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2172 {
6305a203
L		 2173 if (cpu_sub_arch_name)
2174 {
2175 char *name = cpu_sub_arch_name;
2176 cpu_sub_arch_name = concat (name,
91d6fa6a 2177 cpu_arch[j].name,
1bf57e9f 2178 (const char *) NULL);
6305a203
L		 2179 free (name);
2180 }
2181 else
91d6fa6a 2182 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2183 cpu_arch_flags = flags;
a586129e 2184 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2185 }
2186 *input_line_pointer = e;
2187 demand_empty_rest_of_line ();
2188 return;
e413e4e9
AM		 2189 }
2190 }
91d6fa6a 2191 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2192 as_bad (_("no such architecture: `%s'"), string);
2193
2194 *input_line_pointer = e;
2195 }
2196 else
2197 as_bad (_("missing cpu architecture"));
2198
fddf5b5b
AM		 2199 no_cond_jump_promotion = 0;
2200 if (*input_line_pointer == ','
29b0f896 2201 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2202 {
2203 char *string = ++input_line_pointer;
2204 int e = get_symbol_end ();
2205
2206 if (strcmp (string, "nojumps") == 0)
2207 no_cond_jump_promotion = 1;
2208 else if (strcmp (string, "jumps") == 0)
2209 ;
2210 else
2211 as_bad (_("no such architecture modifier: `%s'"), string);
2212
2213 *input_line_pointer = e;
2214 }
2215
e413e4e9
AM		 2216 demand_empty_rest_of_line ();
2217}
2218
8a9036a4
L		 2219enum bfd_architecture
2220i386_arch (void)
2221{
3632d14b 2222 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2223 {
2224 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2225 || flag_code != CODE_64BIT)
2226 as_fatal (_("Intel L1OM is 64bit ELF only"));
2227 return bfd_arch_l1om;
2228 }
2229 else
2230 return bfd_arch_i386;
2231}
2232
b9d79e03
JH		 2233unsigned long
2234i386_mach ()
2235{
351f65ca 2236 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2237 {
3632d14b 2238 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2239 {
351f65ca
L		 2240 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2241 || default_arch[6] != '\0')
8a9036a4
L		 2242 as_fatal (_("Intel L1OM is 64bit ELF only"));
2243 return bfd_mach_l1om;
2244 }
351f65ca 2245 else if (default_arch[6] == '\0')
8a9036a4 2246 return bfd_mach_x86_64;
351f65ca
L		 2247 else
2248 return bfd_mach_x64_32;
8a9036a4 2249 }
b9d79e03
JH		 2250 else if (!strcmp (default_arch, "i386"))
2251 return bfd_mach_i386_i386;
2252 else
2b5d6a91 2253 as_fatal (_("unknown architecture"));
b9d79e03 2254}
b9d79e03 2255\f
252b5132
RH		 2256void
2257md_begin ()
2258{
2259 const char *hash_err;
2260
47926f60 2261 /* Initialize op_hash hash table. */
252b5132
RH		 2262 op_hash = hash_new ();
2263
2264 {
d3ce72d0 2265 const insn_template *optab;
29b0f896 2266 templates *core_optab;
252b5132 2267
47926f60
KH		 2268 /* Setup for loop. */
2269 optab = i386_optab;
252b5132
RH		 2270 core_optab = (templates *) xmalloc (sizeof (templates));
2271 core_optab->start = optab;
2272
2273 while (1)
2274 {
2275 ++optab;
2276 if (optab->name == NULL
2277 || strcmp (optab->name, (optab - 1)->name) != 0)
2278 {
2279 /* different name --> ship out current template list;
47926f60 2280 add to hash table; & begin anew. */
252b5132
RH		 2281 core_optab->end = optab;
2282 hash_err = hash_insert (op_hash,
2283 (optab - 1)->name,
5a49b8ac 2284 (void *) core_optab);
252b5132
RH		 2285 if (hash_err)
2286 {
2b5d6a91 2287 as_fatal (_("internal Error: Can't hash %s: %s"),
252b5132
RH		 2288 (optab - 1)->name,
2289 hash_err);
2290 }
2291 if (optab->name == NULL)
2292 break;
2293 core_optab = (templates *) xmalloc (sizeof (templates));
2294 core_optab->start = optab;
2295 }
2296 }
2297 }
2298
47926f60 2299 /* Initialize reg_hash hash table. */
252b5132
RH		 2300 reg_hash = hash_new ();
2301 {
29b0f896 2302 const reg_entry *regtab;
c3fe08fa 2303 unsigned int regtab_size = i386_regtab_size;
252b5132 2304
c3fe08fa 2305 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2306 {
5a49b8ac 2307 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2308 if (hash_err)
2b5d6a91 2309 as_fatal (_("internal Error: Can't hash %s: %s"),
3e73aa7c
JH		 2310 regtab->reg_name,
2311 hash_err);
252b5132
RH		 2312 }
2313 }
2314
47926f60 2315 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2316 {
29b0f896
AM		 2317 int c;
2318 char *p;
252b5132
RH		 2319
2320 for (c = 0; c < 256; c++)
2321 {
3882b010 2322 if (ISDIGIT (c))
252b5132
RH		 2323 {
2324 digit_chars[c] = c;
2325 mnemonic_chars[c] = c;
2326 register_chars[c] = c;
2327 operand_chars[c] = c;
2328 }
3882b010 2329 else if (ISLOWER (c))
252b5132
RH		 2330 {
2331 mnemonic_chars[c] = c;
2332 register_chars[c] = c;
2333 operand_chars[c] = c;
2334 }
3882b010 2335 else if (ISUPPER (c))
252b5132 2336 {
3882b010 2337 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2338 register_chars[c] = mnemonic_chars[c];
2339 operand_chars[c] = c;
2340 }
2341
3882b010 2342 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2343 identifier_chars[c] = c;
2344 else if (c >= 128)
2345 {
2346 identifier_chars[c] = c;
2347 operand_chars[c] = c;
2348 }
2349 }
2350
2351#ifdef LEX_AT
2352 identifier_chars['@'] = '@';
32137342
NC		 2353#endif
2354#ifdef LEX_QM
2355 identifier_chars['?'] = '?';
2356 operand_chars['?'] = '?';
252b5132 2357#endif
252b5132 2358 digit_chars['-'] = '-';
c0f3af97 2359 mnemonic_chars['_'] = '_';
791fe849 2360 mnemonic_chars['-'] = '-';
0003779b 2361 mnemonic_chars['.'] = '.';
252b5132
RH		 2362 identifier_chars['_'] = '_';
2363 identifier_chars['.'] = '.';
2364
2365 for (p = operand_special_chars; *p != '\0'; p++)
2366 operand_chars[(unsigned char) *p] = *p;
2367 }
2368
2369#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2370 if (IS_ELF)
252b5132
RH		 2371 {
2372 record_alignment (text_section, 2);
2373 record_alignment (data_section, 2);
2374 record_alignment (bss_section, 2);
2375 }
2376#endif
a4447b93
RH		 2377
2378 if (flag_code == CODE_64BIT)
2379 {
ca19b261
KT		 2380#if defined (OBJ_COFF) && defined (TE_PE)
2381 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2382 ? 32 : 16);
2383#else
a4447b93 2384 x86_dwarf2_return_column = 16;
ca19b261 2385#endif
61ff971f 2386 x86_cie_data_alignment = -8;
a4447b93
RH		 2387 }
2388 else
2389 {
2390 x86_dwarf2_return_column = 8;
2391 x86_cie_data_alignment = -4;
2392 }
252b5132
RH		 2393}
2394
2395void
e3bb37b5 2396i386_print_statistics (FILE *file)
252b5132
RH		 2397{
2398 hash_print_statistics (file, "i386 opcode", op_hash);
2399 hash_print_statistics (file, "i386 register", reg_hash);
2400}
2401\f
252b5132
RH		 2402#ifdef DEBUG386
2403
ce8a8b2f 2404/* Debugging routines for md_assemble. */
d3ce72d0 2405static void pte (insn_template *);
40fb9820 2406static void pt (i386_operand_type);
e3bb37b5
L		 2407static void pe (expressionS *);
2408static void ps (symbolS *);
252b5132
RH		 2409
2410static void
e3bb37b5 2411pi (char *line, i386_insn *x)
252b5132 2412{
09137c09 2413 unsigned int j;
252b5132
RH		 2414
2415 fprintf (stdout, "%s: template ", line);
2416 pte (&x->tm);
09f131f2
JH		 2417 fprintf (stdout, " address: base %s index %s scale %x\n",
2418 x->base_reg ? x->base_reg->reg_name : "none",
2419 x->index_reg ? x->index_reg->reg_name : "none",
2420 x->log2_scale_factor);
2421 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2422 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2423 fprintf (stdout, " sib: base %x index %x scale %x\n",
2424 x->sib.base, x->sib.index, x->sib.scale);
2425 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2426 (x->rex & REX_W) != 0,
2427 (x->rex & REX_R) != 0,
2428 (x->rex & REX_X) != 0,
2429 (x->rex & REX_B) != 0);
09137c09 2430 for (j = 0; j < x->operands; j++)
252b5132 2431 {
09137c09
SP		 2432 fprintf (stdout, " #%d: ", j + 1);
2433 pt (x->types[j]);
252b5132 2434 fprintf (stdout, "\n");
09137c09
SP		 2435 if (x->types[j].bitfield.reg8
2436 || x->types[j].bitfield.reg16
2437 || x->types[j].bitfield.reg32
2438 || x->types[j].bitfield.reg64
2439 || x->types[j].bitfield.regmmx
2440 || x->types[j].bitfield.regxmm
2441 || x->types[j].bitfield.regymm
2442 || x->types[j].bitfield.sreg2
2443 || x->types[j].bitfield.sreg3
2444 || x->types[j].bitfield.control
2445 || x->types[j].bitfield.debug
2446 || x->types[j].bitfield.test)
2447 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2448 if (operand_type_check (x->types[j], imm))
2449 pe (x->op[j].imms);
2450 if (operand_type_check (x->types[j], disp))
2451 pe (x->op[j].disps);
252b5132
RH		 2452 }
2453}
2454
2455static void
d3ce72d0 2456pte (insn_template *t)
252b5132 2457{
09137c09 2458 unsigned int j;
252b5132 2459 fprintf (stdout, " %d operands ", t->operands);
47926f60 2460 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2461 if (t->extension_opcode != None)
2462 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2463 if (t->opcode_modifier.d)
252b5132 2464 fprintf (stdout, "D");
40fb9820 2465 if (t->opcode_modifier.w)
252b5132
RH		 2466 fprintf (stdout, "W");
2467 fprintf (stdout, "\n");
09137c09 2468 for (j = 0; j < t->operands; j++)
252b5132 2469 {
09137c09
SP		 2470 fprintf (stdout, " #%d type ", j + 1);
2471 pt (t->operand_types[j]);
252b5132
RH		 2472 fprintf (stdout, "\n");
2473 }
2474}
2475
2476static void
e3bb37b5 2477pe (expressionS *e)
252b5132 2478{
24eab124 2479 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2480 fprintf (stdout, " add_number %ld (%lx)\n",
2481 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2482 if (e->X_add_symbol)
2483 {
2484 fprintf (stdout, " add_symbol ");
2485 ps (e->X_add_symbol);
2486 fprintf (stdout, "\n");
2487 }
2488 if (e->X_op_symbol)
2489 {
2490 fprintf (stdout, " op_symbol ");
2491 ps (e->X_op_symbol);
2492 fprintf (stdout, "\n");
2493 }
2494}
2495
2496static void
e3bb37b5 2497ps (symbolS *s)
252b5132
RH		 2498{
2499 fprintf (stdout, "%s type %s%s",
2500 S_GET_NAME (s),
2501 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2502 segment_name (S_GET_SEGMENT (s)));
2503}
2504
7b81dfbb 2505static struct type_name
252b5132 2506 {
40fb9820
L		 2507 i386_operand_type mask;
2508 const char *name;
252b5132 2509 }
7b81dfbb 2510const type_names[] =
252b5132 2511{
40fb9820
L		 2512 { OPERAND_TYPE_REG8, "r8" },
2513 { OPERAND_TYPE_REG16, "r16" },
2514 { OPERAND_TYPE_REG32, "r32" },
2515 { OPERAND_TYPE_REG64, "r64" },
2516 { OPERAND_TYPE_IMM8, "i8" },
2517 { OPERAND_TYPE_IMM8, "i8s" },
2518 { OPERAND_TYPE_IMM16, "i16" },
2519 { OPERAND_TYPE_IMM32, "i32" },
2520 { OPERAND_TYPE_IMM32S, "i32s" },
2521 { OPERAND_TYPE_IMM64, "i64" },
2522 { OPERAND_TYPE_IMM1, "i1" },
2523 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2524 { OPERAND_TYPE_DISP8, "d8" },
2525 { OPERAND_TYPE_DISP16, "d16" },
2526 { OPERAND_TYPE_DISP32, "d32" },
2527 { OPERAND_TYPE_DISP32S, "d32s" },
2528 { OPERAND_TYPE_DISP64, "d64" },
2529 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2530 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2531 { OPERAND_TYPE_CONTROL, "control reg" },
2532 { OPERAND_TYPE_TEST, "test reg" },
2533 { OPERAND_TYPE_DEBUG, "debug reg" },
2534 { OPERAND_TYPE_FLOATREG, "FReg" },
2535 { OPERAND_TYPE_FLOATACC, "FAcc" },
2536 { OPERAND_TYPE_SREG2, "SReg2" },
2537 { OPERAND_TYPE_SREG3, "SReg3" },
2538 { OPERAND_TYPE_ACC, "Acc" },
2539 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2540 { OPERAND_TYPE_REGMMX, "rMMX" },
2541 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2542 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2543 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2544};
2545
2546static void
40fb9820 2547pt (i386_operand_type t)
252b5132 2548{
40fb9820 2549 unsigned int j;
c6fb90c8 2550 i386_operand_type a;
252b5132 2551
40fb9820 2552 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2553 {
2554 a = operand_type_and (t, type_names[j].mask);
0349dc08 2555 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2556 fprintf (stdout, "%s, ", type_names[j].name);
2557 }
252b5132
RH		 2558 fflush (stdout);
2559}
2560
2561#endif /* DEBUG386 */
2562\f
252b5132 2563static bfd_reloc_code_real_type
3956db08 2564reloc (unsigned int size,
64e74474
AM		 2565 int pcrel,
2566 int sign,
2567 bfd_reloc_code_real_type other)
252b5132 2568{
47926f60 2569 if (other != NO_RELOC)
3956db08 2570 {
91d6fa6a 2571 reloc_howto_type *rel;
3956db08
JB		 2572
2573 if (size == 8)
2574 switch (other)
2575 {
64e74474
AM		 2576 case BFD_RELOC_X86_64_GOT32:
2577 return BFD_RELOC_X86_64_GOT64;
2578 break;
2579 case BFD_RELOC_X86_64_PLTOFF64:
2580 return BFD_RELOC_X86_64_PLTOFF64;
2581 break;
2582 case BFD_RELOC_X86_64_GOTPC32:
2583 other = BFD_RELOC_X86_64_GOTPC64;
2584 break;
2585 case BFD_RELOC_X86_64_GOTPCREL:
2586 other = BFD_RELOC_X86_64_GOTPCREL64;
2587 break;
2588 case BFD_RELOC_X86_64_TPOFF32:
2589 other = BFD_RELOC_X86_64_TPOFF64;
2590 break;
2591 case BFD_RELOC_X86_64_DTPOFF32:
2592 other = BFD_RELOC_X86_64_DTPOFF64;
2593 break;
2594 default:
2595 break;
3956db08 2596 }
e05278af
JB		 2597
2598 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2599 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2600 sign = -1;
2601
91d6fa6a
NC		 2602 rel = bfd_reloc_type_lookup (stdoutput, other);
2603 if (!rel)
3956db08 2604 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2605 else if (size != bfd_get_reloc_size (rel))
3956db08 2606 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2607 bfd_get_reloc_size (rel),
3956db08 2608 size);
91d6fa6a 2609 else if (pcrel && !rel->pc_relative)
3956db08 2610 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2611 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2612 && !sign)
91d6fa6a 2613 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2614 && sign > 0))
3956db08
JB		 2615 as_bad (_("relocated field and relocation type differ in signedness"));
2616 else
2617 return other;
2618 return NO_RELOC;
2619 }
252b5132
RH		 2620
2621 if (pcrel)
2622 {
3e73aa7c 2623 if (!sign)
3956db08 2624 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2625 switch (size)
2626 {
2627 case 1: return BFD_RELOC_8_PCREL;
2628 case 2: return BFD_RELOC_16_PCREL;
2629 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2630 case 8: return BFD_RELOC_64_PCREL;
252b5132 2631 }
3956db08 2632 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2633 }
2634 else
2635 {
3956db08 2636 if (sign > 0)
e5cb08ac 2637 switch (size)
3e73aa7c
JH		 2638 {
2639 case 4: return BFD_RELOC_X86_64_32S;
2640 }
2641 else
2642 switch (size)
2643 {
2644 case 1: return BFD_RELOC_8;
2645 case 2: return BFD_RELOC_16;
2646 case 4: return BFD_RELOC_32;
2647 case 8: return BFD_RELOC_64;
2648 }
3956db08
JB		 2649 as_bad (_("cannot do %s %u byte relocation"),
2650 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2651 }
2652
0cc9e1d3 2653 return NO_RELOC;
252b5132
RH		 2654}
2655
47926f60
KH		 2656/* Here we decide which fixups can be adjusted to make them relative to
2657 the beginning of the section instead of the symbol. Basically we need
2658 to make sure that the dynamic relocations are done correctly, so in
2659 some cases we force the original symbol to be used. */
2660
252b5132 2661int
e3bb37b5 2662tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2663{
6d249963 2664#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2665 if (!IS_ELF)
31312f95
AM		 2666 return 1;
2667
a161fe53
AM		 2668 /* Don't adjust pc-relative references to merge sections in 64-bit
2669 mode. */
2670 if (use_rela_relocations
2671 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2672 && fixP->fx_pcrel)
252b5132 2673 return 0;
31312f95 2674
8d01d9a9
AJ		 2675 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2676 and changed later by validate_fix. */
2677 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2678 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2679 return 0;
2680
ce8a8b2f 2681 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2682 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2683 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2684 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2685 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2686 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2687 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2688 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2689 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2690 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2691 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2692 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2693 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2694 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2695 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2696 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2697 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2698 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2699 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2700 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2701 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2702 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2703 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2704 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2705 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2706 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2707 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2708 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2709 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2710 return 0;
31312f95 2711#endif
252b5132
RH		 2712 return 1;
2713}
252b5132 2714
b4cac588 2715static int
e3bb37b5 2716intel_float_operand (const char *mnemonic)
252b5132 2717{
9306ca4a
JB		 2718 /* Note that the value returned is meaningful only for opcodes with (memory)
2719 operands, hence the code here is free to improperly handle opcodes that
2720 have no operands (for better performance and smaller code). */
2721
2722 if (mnemonic[0] != 'f')
2723 return 0; /* non-math */
2724
2725 switch (mnemonic[1])
2726 {
2727 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2728 the fs segment override prefix not currently handled because no
2729 call path can make opcodes without operands get here */
2730 case 'i':
2731 return 2 /* integer op */;
2732 case 'l':
2733 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2734 return 3; /* fldcw/fldenv */
2735 break;
2736 case 'n':
2737 if (mnemonic[2] != 'o' /* fnop */)
2738 return 3; /* non-waiting control op */
2739 break;
2740 case 'r':
2741 if (mnemonic[2] == 's')
2742 return 3; /* frstor/frstpm */
2743 break;
2744 case 's':
2745 if (mnemonic[2] == 'a')
2746 return 3; /* fsave */
2747 if (mnemonic[2] == 't')
2748 {
2749 switch (mnemonic[3])
2750 {
2751 case 'c': /* fstcw */
2752 case 'd': /* fstdw */
2753 case 'e': /* fstenv */
2754 case 's': /* fsts[gw] */
2755 return 3;
2756 }
2757 }
2758 break;
2759 case 'x':
2760 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2761 return 0; /* fxsave/fxrstor are not really math ops */
2762 break;
2763 }
252b5132 2764
9306ca4a 2765 return 1;
252b5132
RH		 2766}
2767
c0f3af97
L		 2768/* Build the VEX prefix. */
2769
2770static void
d3ce72d0 2771build_vex_prefix (const insn_template *t)
c0f3af97
L		 2772{
2773 unsigned int register_specifier;
2774 unsigned int implied_prefix;
2775 unsigned int vector_length;
2776
2777 /* Check register specifier. */
2778 if (i.vex.register_specifier)
2779 {
2780 register_specifier = i.vex.register_specifier->reg_num;
2781 if ((i.vex.register_specifier->reg_flags & RegRex))
2782 register_specifier += 8;
2783 register_specifier = ~register_specifier & 0xf;
2784 }
2785 else
2786 register_specifier = 0xf;
2787
fa99fab2
L		 2788 /* Use 2-byte VEX prefix by swappping destination and source
2789 operand. */
2790 if (!i.swap_operand
2791 && i.operands == i.reg_operands
7f399153 2792 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2793 && i.tm.opcode_modifier.s
2794 && i.rex == REX_B)
2795 {
2796 unsigned int xchg = i.operands - 1;
2797 union i386_op temp_op;
2798 i386_operand_type temp_type;
2799
2800 temp_type = i.types[xchg];
2801 i.types[xchg] = i.types[0];
2802 i.types[0] = temp_type;
2803 temp_op = i.op[xchg];
2804 i.op[xchg] = i.op[0];
2805 i.op[0] = temp_op;
2806
9c2799c2 2807 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2808
2809 i.rex = REX_R;
2810 xchg = i.rm.regmem;
2811 i.rm.regmem = i.rm.reg;
2812 i.rm.reg = xchg;
2813
2814 /* Use the next insn. */
2815 i.tm = t[1];
2816 }
2817
539f890d
L		 2818 if (i.tm.opcode_modifier.vex == VEXScalar)
2819 vector_length = avxscalar;
2820 else
2821 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2822
2823 switch ((i.tm.base_opcode >> 8) & 0xff)
2824 {
2825 case 0:
2826 implied_prefix = 0;
2827 break;
2828 case DATA_PREFIX_OPCODE:
2829 implied_prefix = 1;
2830 break;
2831 case REPE_PREFIX_OPCODE:
2832 implied_prefix = 2;
2833 break;
2834 case REPNE_PREFIX_OPCODE:
2835 implied_prefix = 3;
2836 break;
2837 default:
2838 abort ();
2839 }
2840
2841 /* Use 2-byte VEX prefix if possible. */
7f399153 2842 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2843 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2844 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2845 {
2846 /* 2-byte VEX prefix. */
2847 unsigned int r;
2848
2849 i.vex.length = 2;
2850 i.vex.bytes[0] = 0xc5;
2851
2852 /* Check the REX.R bit. */
2853 r = (i.rex & REX_R) ? 0 : 1;
2854 i.vex.bytes[1] = (r << 7
2855 | register_specifier << 3
2856 | vector_length << 2
2857 | implied_prefix);
2858 }
2859 else
2860 {
2861 /* 3-byte VEX prefix. */
2862 unsigned int m, w;
2863
f88c9eb0 2864 i.vex.length = 3;
f88c9eb0 2865
7f399153 2866 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2867 {
7f399153
L		 2868 case VEX0F:
2869 m = 0x1;
80de6e00 2870 i.vex.bytes[0] = 0xc4;
7f399153
L		 2871 break;
2872 case VEX0F38:
2873 m = 0x2;
80de6e00 2874 i.vex.bytes[0] = 0xc4;
7f399153
L		 2875 break;
2876 case VEX0F3A:
2877 m = 0x3;
80de6e00 2878 i.vex.bytes[0] = 0xc4;
7f399153
L		 2879 break;
2880 case XOP08:
5dd85c99
SP		 2881 m = 0x8;
2882 i.vex.bytes[0] = 0x8f;
7f399153
L		 2883 break;
2884 case XOP09:
f88c9eb0
SP		 2885 m = 0x9;
2886 i.vex.bytes[0] = 0x8f;
7f399153
L		 2887 break;
2888 case XOP0A:
f88c9eb0
SP		 2889 m = 0xa;
2890 i.vex.bytes[0] = 0x8f;
7f399153
L		 2891 break;
2892 default:
2893 abort ();
f88c9eb0 2894 }
c0f3af97 2895
c0f3af97
L		 2896 /* The high 3 bits of the second VEX byte are 1's compliment
2897 of RXB bits from REX. */
2898 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2899
2900 /* Check the REX.W bit. */
2901 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2902 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2903 {
2904 if (w)
2905 abort ();
2906
1ef99a7b 2907 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2908 w = 1;
2909 }
2910
2911 i.vex.bytes[2] = (w << 7
2912 | register_specifier << 3
2913 | vector_length << 2
2914 | implied_prefix);
2915 }
2916}
2917
65da13b5
L		 2918static void
2919process_immext (void)
2920{
2921 expressionS *exp;
2922
2923 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2924 {
1fed0ba1
L		 2925 /* SSE3 Instructions have the fixed operands with an opcode
2926 suffix which is coded in the same place as an 8-bit immediate
2927 field would be. Here we check those operands and remove them
2928 afterwards. */
65da13b5
L		 2929 unsigned int x;
2930
2931 for (x = 0; x < i.operands; x++)
2932 if (i.op[x].regs->reg_num != x)
2933 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2934 register_prefix, i.op[x].regs->reg_name, x + 1,
2935 i.tm.name);
2936
2937 i.operands = 0;
65da13b5
L		 2938 }
2939
c0f3af97 2940 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2941 which is coded in the same place as an 8-bit immediate field
2942 would be. Here we fake an 8-bit immediate operand from the
2943 opcode suffix stored in tm.extension_opcode.
2944
c1e679ec 2945 AVX instructions also use this encoding, for some of
c0f3af97 2946 3 argument instructions. */
65da13b5 2947
9c2799c2 2948 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2949 && (i.operands <= 2
2950 || (i.tm.opcode_modifier.vex
2951 && i.operands <= 4)));
65da13b5
L		 2952
2953 exp = &im_expressions[i.imm_operands++];
2954 i.op[i.operands].imms = exp;
2955 i.types[i.operands] = imm8;
2956 i.operands++;
2957 exp->X_op = O_constant;
2958 exp->X_add_number = i.tm.extension_opcode;
2959 i.tm.extension_opcode = None;
2960}
2961
252b5132
RH		 2962/* This is the guts of the machine-dependent assembler. LINE points to a
2963 machine dependent instruction. This function is supposed to emit
2964 the frags/bytes it assembles to. */
2965
2966void
65da13b5 2967md_assemble (char *line)
252b5132 2968{
40fb9820 2969 unsigned int j;
252b5132 2970 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2971 const insn_template *t;
252b5132 2972
47926f60 2973 /* Initialize globals. */
252b5132
RH		 2974 memset (&i, '\0', sizeof (i));
2975 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2976 i.reloc[j] = NO_RELOC;
252b5132
RH		 2977 memset (disp_expressions, '\0', sizeof (disp_expressions));
2978 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2979 save_stack_p = save_stack;
252b5132
RH		 2980
2981 /* First parse an instruction mnemonic & call i386_operand for the operands.
2982 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2983 start of a (possibly prefixed) mnemonic. */
252b5132 2984
29b0f896
AM		 2985 line = parse_insn (line, mnemonic);
2986 if (line == NULL)
2987 return;
252b5132 2988
29b0f896 2989 line = parse_operands (line, mnemonic);
ee86248c 2990 this_operand = -1;
29b0f896
AM		 2991 if (line == NULL)
2992 return;
252b5132 2993
29b0f896
AM		 2994 /* Now we've parsed the mnemonic into a set of templates, and have the
2995 operands at hand. */
2996
2997 /* All intel opcodes have reversed operands except for "bound" and
2998 "enter". We also don't reverse intersegment "jmp" and "call"
2999 instructions with 2 immediate operands so that the immediate segment
050dfa73 3000 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3001 if (intel_syntax
3002 && i.operands > 1
29b0f896 3003 && (strcmp (mnemonic, "bound") != 0)
30123838 3004 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3005 && !(operand_type_check (i.types[0], imm)
3006 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3007 swap_operands ();
3008
ec56d5c0
JB		 3009 /* The order of the immediates should be reversed
3010 for 2 immediates extrq and insertq instructions */
3011 if (i.imm_operands == 2
3012 && (strcmp (mnemonic, "extrq") == 0
3013 || strcmp (mnemonic, "insertq") == 0))
3014 swap_2_operands (0, 1);
3015
29b0f896
AM		 3016 if (i.imm_operands)
3017 optimize_imm ();
3018
b300c311
L		 3019 /* Don't optimize displacement for movabs since it only takes 64bit
3020 displacement. */
3021 if (i.disp_operands
862be3fb
L		 3022 && !i.disp32_encoding
3023 && (flag_code != CODE_64BIT
3024 || strcmp (mnemonic, "movabs") != 0))
3025 optimize_disp ();
29b0f896
AM		 3026
3027 /* Next, we find a template that matches the given insn,
3028 making sure the overlap of the given operands types is consistent
3029 with the template operand types. */
252b5132 3030
fa99fab2 3031 if (!(t = match_template ()))
29b0f896 3032 return;
252b5132 3033
daf50ae7 3034 if (sse_check != sse_check_none
81f8a913 3035 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3036 && (i.tm.cpu_flags.bitfield.cpusse
3037 || i.tm.cpu_flags.bitfield.cpusse2
3038 || i.tm.cpu_flags.bitfield.cpusse3
3039 || i.tm.cpu_flags.bitfield.cpussse3
3040 || i.tm.cpu_flags.bitfield.cpusse4_1
3041 || i.tm.cpu_flags.bitfield.cpusse4_2))
3042 {
3043 (sse_check == sse_check_warning
3044 ? as_warn
3045 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3046 }
3047
321fd21e
L		 3048 /* Zap movzx and movsx suffix. The suffix has been set from
3049 "word ptr" or "byte ptr" on the source operand in Intel syntax
3050 or extracted from mnemonic in AT&T syntax. But we'll use
3051 the destination register to choose the suffix for encoding. */
3052 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3053 {
321fd21e
L		 3054 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3055 there is no suffix, the default will be byte extension. */
3056 if (i.reg_operands != 2
3057 && !i.suffix
7ab9ffdd 3058 && intel_syntax)
321fd21e
L		 3059 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3060
3061 i.suffix = 0;
cd61ebfe 3062 }
24eab124 3063
40fb9820 3064 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3065 if (!add_prefix (FWAIT_OPCODE))
3066 return;
252b5132 3067
c1ba0266
L		 3068 /* Check for lock without a lockable instruction. Destination operand
3069 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3070 if (i.prefix[LOCK_PREFIX]
3071 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3072 || i.mem_operands == 0
3073 || (i.tm.base_opcode != 0x86
3074 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3075 {
3076 as_bad (_("expecting lockable instruction after `lock'"));
3077 return;
3078 }
3079
29b0f896 3080 /* Check string instruction segment overrides. */
40fb9820 3081 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3082 {
3083 if (!check_string ())
5dd0794d 3084 return;
fc0763e6 3085 i.disp_operands = 0;
29b0f896 3086 }
5dd0794d 3087
29b0f896
AM		 3088 if (!process_suffix ())
3089 return;
e413e4e9 3090
bc0844ae
L		 3091 /* Update operand types. */
3092 for (j = 0; j < i.operands; j++)
3093 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3094
29b0f896
AM		 3095 /* Make still unresolved immediate matches conform to size of immediate
3096 given in i.suffix. */
3097 if (!finalize_imm ())
3098 return;
252b5132 3099
40fb9820 3100 if (i.types[0].bitfield.imm1)
29b0f896 3101 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3102
9afe6eb8
L		 3103 /* We only need to check those implicit registers for instructions
3104 with 3 operands or less. */
3105 if (i.operands <= 3)
3106 for (j = 0; j < i.operands; j++)
3107 if (i.types[j].bitfield.inoutportreg
3108 || i.types[j].bitfield.shiftcount
3109 || i.types[j].bitfield.acc
3110 || i.types[j].bitfield.floatacc)
3111 i.reg_operands--;
40fb9820 3112
c0f3af97
L		 3113 /* ImmExt should be processed after SSE2AVX. */
3114 if (!i.tm.opcode_modifier.sse2avx
3115 && i.tm.opcode_modifier.immext)
65da13b5 3116 process_immext ();
252b5132 3117
29b0f896
AM		 3118 /* For insns with operands there are more diddles to do to the opcode. */
3119 if (i.operands)
3120 {
3121 if (!process_operands ())
3122 return;
3123 }
40fb9820 3124 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3125 {
3126 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3127 as_warn (_("translating to `%sp'"), i.tm.name);
3128 }
252b5132 3129
c0f3af97 3130 if (i.tm.opcode_modifier.vex)
fa99fab2 3131 build_vex_prefix (t);
c0f3af97 3132
5dd85c99
SP		 3133 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3134 instructions may define INT_OPCODE as well, so avoid this corner
3135 case for those instructions that use MODRM. */
3136 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3137 && !i.tm.opcode_modifier.modrm
3138 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3139 {
3140 i.tm.base_opcode = INT3_OPCODE;
3141 i.imm_operands = 0;
3142 }
252b5132 3143
40fb9820
L		 3144 if ((i.tm.opcode_modifier.jump
3145 || i.tm.opcode_modifier.jumpbyte
3146 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3147 && i.op[0].disps->X_op == O_constant)
3148 {
3149 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3150 the absolute address given by the constant. Since ix86 jumps and
3151 calls are pc relative, we need to generate a reloc. */
3152 i.op[0].disps->X_add_symbol = &abs_symbol;
3153 i.op[0].disps->X_op = O_symbol;
3154 }
252b5132 3155
40fb9820 3156 if (i.tm.opcode_modifier.rex64)
161a04f6 3157 i.rex |= REX_W;
252b5132 3158
29b0f896
AM		 3159 /* For 8 bit registers we need an empty rex prefix. Also if the
3160 instruction already has a prefix, we need to convert old
3161 registers to new ones. */
773f551c 3162
40fb9820 3163 if ((i.types[0].bitfield.reg8
29b0f896 3164 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3165 || (i.types[1].bitfield.reg8
29b0f896 3166 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3167 || ((i.types[0].bitfield.reg8
3168 || i.types[1].bitfield.reg8)
29b0f896
AM		 3169 && i.rex != 0))
3170 {
3171 int x;
726c5dcd 3172
29b0f896
AM		 3173 i.rex |= REX_OPCODE;
3174 for (x = 0; x < 2; x++)
3175 {
3176 /* Look for 8 bit operand that uses old registers. */
40fb9820 3177 if (i.types[x].bitfield.reg8
29b0f896 3178 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3179 {
29b0f896
AM		 3180 /* In case it is "hi" register, give up. */
3181 if (i.op[x].regs->reg_num > 3)
a540244d 3182 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3183 "instruction requiring REX prefix."),
a540244d 3184 register_prefix, i.op[x].regs->reg_name);
773f551c 3185
29b0f896
AM		 3186 /* Otherwise it is equivalent to the extended register.
3187 Since the encoding doesn't change this is merely
3188 cosmetic cleanup for debug output. */
3189
3190 i.op[x].regs = i.op[x].regs + 8;
773f551c 3191 }
29b0f896
AM		 3192 }
3193 }
773f551c 3194
7ab9ffdd 3195 if (i.rex != 0)
29b0f896
AM		 3196 add_prefix (REX_OPCODE | i.rex);
3197
3198 /* We are ready to output the insn. */
3199 output_insn ();
3200}
3201
3202static char *
e3bb37b5 3203parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3204{
3205 char *l = line;
3206 char *token_start = l;
3207 char *mnem_p;
5c6af06e 3208 int supported;
d3ce72d0 3209 const insn_template *t;
b6169b20 3210 char *dot_p = NULL;
29b0f896
AM		 3211
3212 /* Non-zero if we found a prefix only acceptable with string insns. */
3213 const char *expecting_string_instruction = NULL;
45288df1 3214
29b0f896
AM		 3215 while (1)
3216 {
3217 mnem_p = mnemonic;
3218 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3219 {
b6169b20
L		 3220 if (*mnem_p == '.')
3221 dot_p = mnem_p;
29b0f896
AM		 3222 mnem_p++;
3223 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3224 {
29b0f896
AM		 3225 as_bad (_("no such instruction: `%s'"), token_start);
3226 return NULL;
3227 }
3228 l++;
3229 }
3230 if (!is_space_char (*l)
3231 && *l != END_OF_INSN
e44823cf
JB		 3232 && (intel_syntax
3233 || (*l != PREFIX_SEPARATOR
3234 && *l != ',')))
29b0f896
AM		 3235 {
3236 as_bad (_("invalid character %s in mnemonic"),
3237 output_invalid (*l));
3238 return NULL;
3239 }
3240 if (token_start == l)
3241 {
e44823cf 3242 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3243 as_bad (_("expecting prefix; got nothing"));
3244 else
3245 as_bad (_("expecting mnemonic; got nothing"));
3246 return NULL;
3247 }
45288df1 3248
29b0f896 3249 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3250 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3251
29b0f896
AM		 3252 if (*l != END_OF_INSN
3253 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3254 && current_templates
40fb9820 3255 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3256 {
c6fb90c8 3257 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3258 {
3259 as_bad ((flag_code != CODE_64BIT
3260 ? _("`%s' is only supported in 64-bit mode")
3261 : _("`%s' is not supported in 64-bit mode")),
3262 current_templates->start->name);
3263 return NULL;
3264 }
29b0f896
AM		 3265 /* If we are in 16-bit mode, do not allow addr16 or data16.
3266 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3267 if ((current_templates->start->opcode_modifier.size16
3268 || current_templates->start->opcode_modifier.size32)
29b0f896 3269 && flag_code != CODE_64BIT
40fb9820 3270 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3271 ^ (flag_code == CODE_16BIT)))
3272 {
3273 as_bad (_("redundant %s prefix"),
3274 current_templates->start->name);
3275 return NULL;
45288df1 3276 }
29b0f896
AM		 3277 /* Add prefix, checking for repeated prefixes. */
3278 switch (add_prefix (current_templates->start->base_opcode))
3279 {
c32fa91d 3280 case PREFIX_EXIST:
29b0f896 3281 return NULL;
c32fa91d 3282 case PREFIX_REP:
29b0f896
AM		 3283 expecting_string_instruction = current_templates->start->name;
3284 break;
c32fa91d
L		 3285 default:
3286 break;
29b0f896
AM		 3287 }
3288 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3289 token_start = ++l;
3290 }
3291 else
3292 break;
3293 }
45288df1 3294
30a55f88 3295 if (!current_templates)
b6169b20 3296 {
f8a5c266
L		 3297 /* Check if we should swap operand or force 32bit displacement in
3298 encoding. */
30a55f88
L		 3299 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3300 i.swap_operand = 1;
f8a5c266
L		 3301 else if (mnem_p - 4 == dot_p
3302 && dot_p[1] == 'd'
3303 && dot_p[2] == '3'
3304 && dot_p[3] == '2')
3305 i.disp32_encoding = 1;
30a55f88
L		 3306 else
3307 goto check_suffix;
3308 mnem_p = dot_p;
3309 *dot_p = '\0';
d3ce72d0 3310 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3311 }
3312
29b0f896
AM		 3313 if (!current_templates)
3314 {
b6169b20 3315check_suffix:
29b0f896
AM		 3316 /* See if we can get a match by trimming off a suffix. */
3317 switch (mnem_p[-1])
3318 {
3319 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3320 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3321 i.suffix = SHORT_MNEM_SUFFIX;
3322 else
29b0f896
AM		 3323 case BYTE_MNEM_SUFFIX:
3324 case QWORD_MNEM_SUFFIX:
3325 i.suffix = mnem_p[-1];
3326 mnem_p[-1] = '\0';
d3ce72d0
NC		 3327 current_templates = (const templates *) hash_find (op_hash,
3328 mnemonic);
29b0f896
AM		 3329 break;
3330 case SHORT_MNEM_SUFFIX:
3331 case LONG_MNEM_SUFFIX:
3332 if (!intel_syntax)
3333 {
3334 i.suffix = mnem_p[-1];
3335 mnem_p[-1] = '\0';
d3ce72d0
NC		 3336 current_templates = (const templates *) hash_find (op_hash,
3337 mnemonic);
29b0f896
AM		 3338 }
3339 break;
252b5132 3340
29b0f896
AM		 3341 /* Intel Syntax. */
3342 case 'd':
3343 if (intel_syntax)
3344 {
9306ca4a 3345 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3346 i.suffix = SHORT_MNEM_SUFFIX;
3347 else
3348 i.suffix = LONG_MNEM_SUFFIX;
3349 mnem_p[-1] = '\0';
d3ce72d0
NC		 3350 current_templates = (const templates *) hash_find (op_hash,
3351 mnemonic);
29b0f896
AM		 3352 }
3353 break;
3354 }
3355 if (!current_templates)
3356 {
3357 as_bad (_("no such instruction: `%s'"), token_start);
3358 return NULL;
3359 }
3360 }
252b5132 3361
40fb9820
L		 3362 if (current_templates->start->opcode_modifier.jump
3363 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3364 {
3365 /* Check for a branch hint. We allow ",pt" and ",pn" for
3366 predict taken and predict not taken respectively.
3367 I'm not sure that branch hints actually do anything on loop
3368 and jcxz insns (JumpByte) for current Pentium4 chips. They
3369 may work in the future and it doesn't hurt to accept them
3370 now. */
3371 if (l[0] == ',' && l[1] == 'p')
3372 {
3373 if (l[2] == 't')
3374 {
3375 if (!add_prefix (DS_PREFIX_OPCODE))
3376 return NULL;
3377 l += 3;
3378 }
3379 else if (l[2] == 'n')
3380 {
3381 if (!add_prefix (CS_PREFIX_OPCODE))
3382 return NULL;
3383 l += 3;
3384 }
3385 }
3386 }
3387 /* Any other comma loses. */
3388 if (*l == ',')
3389 {
3390 as_bad (_("invalid character %s in mnemonic"),
3391 output_invalid (*l));
3392 return NULL;
3393 }
252b5132 3394
29b0f896 3395 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3396 supported = 0;
3397 for (t = current_templates->start; t < current_templates->end; ++t)
3398 {
c0f3af97
L		 3399 supported |= cpu_flags_match (t);
3400 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3401 goto skip;
5c6af06e 3402 }
3629bb00 3403
c0f3af97 3404 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3405 {
3406 as_bad (flag_code == CODE_64BIT
3407 ? _("`%s' is not supported in 64-bit mode")
3408 : _("`%s' is only supported in 64-bit mode"),
3409 current_templates->start->name);
3410 return NULL;
3411 }
c0f3af97 3412 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3413 {
3629bb00 3414 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3415 current_templates->start->name,
41aacd83 3416 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3417 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3418 return NULL;
29b0f896 3419 }
3629bb00
L		 3420
3421skip:
3422 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3423 && (flag_code != CODE_16BIT))
29b0f896
AM		 3424 {
3425 as_warn (_("use .code16 to ensure correct addressing mode"));
3426 }
252b5132 3427
29b0f896 3428 /* Check for rep/repne without a string instruction. */
f41bbced 3429 if (expecting_string_instruction)
29b0f896 3430 {
f41bbced
JB		 3431 static templates override;
3432
3433 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3434 if (t->opcode_modifier.isstring)
f41bbced
JB		 3435 break;
3436 if (t >= current_templates->end)
3437 {
3438 as_bad (_("expecting string instruction after `%s'"),
64e74474 3439 expecting_string_instruction);
f41bbced
JB		 3440 return NULL;
3441 }
3442 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3443 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3444 break;
3445 override.end = t;
3446 current_templates = &override;
29b0f896 3447 }
252b5132 3448
29b0f896
AM		 3449 return l;
3450}
252b5132 3451
29b0f896 3452static char *
e3bb37b5 3453parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3454{
3455 char *token_start;
3138f287 3456
29b0f896
AM		 3457 /* 1 if operand is pending after ','. */
3458 unsigned int expecting_operand = 0;
252b5132 3459
29b0f896
AM		 3460 /* Non-zero if operand parens not balanced. */
3461 unsigned int paren_not_balanced;
3462
3463 while (*l != END_OF_INSN)
3464 {
3465 /* Skip optional white space before operand. */
3466 if (is_space_char (*l))
3467 ++l;
3468 if (!is_operand_char (*l) && *l != END_OF_INSN)
3469 {
3470 as_bad (_("invalid character %s before operand %d"),
3471 output_invalid (*l),
3472 i.operands + 1);
3473 return NULL;
3474 }
3475 token_start = l; /* after white space */
3476 paren_not_balanced = 0;
3477 while (paren_not_balanced || *l != ',')
3478 {
3479 if (*l == END_OF_INSN)
3480 {
3481 if (paren_not_balanced)
3482 {
3483 if (!intel_syntax)
3484 as_bad (_("unbalanced parenthesis in operand %d."),
3485 i.operands + 1);
3486 else
3487 as_bad (_("unbalanced brackets in operand %d."),
3488 i.operands + 1);
3489 return NULL;
3490 }
3491 else
3492 break; /* we are done */
3493 }
3494 else if (!is_operand_char (*l) && !is_space_char (*l))
3495 {
3496 as_bad (_("invalid character %s in operand %d"),
3497 output_invalid (*l),
3498 i.operands + 1);
3499 return NULL;
3500 }
3501 if (!intel_syntax)
3502 {
3503 if (*l == '(')
3504 ++paren_not_balanced;
3505 if (*l == ')')
3506 --paren_not_balanced;
3507 }
3508 else
3509 {
3510 if (*l == '[')
3511 ++paren_not_balanced;
3512 if (*l == ']')
3513 --paren_not_balanced;
3514 }
3515 l++;
3516 }
3517 if (l != token_start)
3518 { /* Yes, we've read in another operand. */
3519 unsigned int operand_ok;
3520 this_operand = i.operands++;
7d5e4556 3521 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3522 if (i.operands > MAX_OPERANDS)
3523 {
3524 as_bad (_("spurious operands; (%d operands/instruction max)"),
3525 MAX_OPERANDS);
3526 return NULL;
3527 }
3528 /* Now parse operand adding info to 'i' as we go along. */
3529 END_STRING_AND_SAVE (l);
3530
3531 if (intel_syntax)
3532 operand_ok =
3533 i386_intel_operand (token_start,
3534 intel_float_operand (mnemonic));
3535 else
a7619375 3536 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3537
3538 RESTORE_END_STRING (l);
3539 if (!operand_ok)
3540 return NULL;
3541 }
3542 else
3543 {
3544 if (expecting_operand)
3545 {
3546 expecting_operand_after_comma:
3547 as_bad (_("expecting operand after ','; got nothing"));
3548 return NULL;
3549 }
3550 if (*l == ',')
3551 {
3552 as_bad (_("expecting operand before ','; got nothing"));
3553 return NULL;
3554 }
3555 }
7f3f1ea2 3556
29b0f896
AM		 3557 /* Now *l must be either ',' or END_OF_INSN. */
3558 if (*l == ',')
3559 {
3560 if (*++l == END_OF_INSN)
3561 {
3562 /* Just skip it, if it's \n complain. */
3563 goto expecting_operand_after_comma;
3564 }
3565 expecting_operand = 1;
3566 }
3567 }
3568 return l;
3569}
7f3f1ea2 3570
050dfa73 3571static void
4d456e3d 3572swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3573{
3574 union i386_op temp_op;
40fb9820 3575 i386_operand_type temp_type;
050dfa73 3576 enum bfd_reloc_code_real temp_reloc;
4eed87de 3577
050dfa73
MM		 3578 temp_type = i.types[xchg2];
3579 i.types[xchg2] = i.types[xchg1];
3580 i.types[xchg1] = temp_type;
3581 temp_op = i.op[xchg2];
3582 i.op[xchg2] = i.op[xchg1];
3583 i.op[xchg1] = temp_op;
3584 temp_reloc = i.reloc[xchg2];
3585 i.reloc[xchg2] = i.reloc[xchg1];
3586 i.reloc[xchg1] = temp_reloc;
3587}
3588
29b0f896 3589static void
e3bb37b5 3590swap_operands (void)
29b0f896 3591{
b7c61d9a 3592 switch (i.operands)
050dfa73 3593 {
c0f3af97 3594 case 5:
b7c61d9a 3595 case 4:
4d456e3d 3596 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3597 case 3:
3598 case 2:
4d456e3d 3599 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3600 break;
3601 default:
3602 abort ();
29b0f896 3603 }
29b0f896
AM		 3604
3605 if (i.mem_operands == 2)
3606 {
3607 const seg_entry *temp_seg;
3608 temp_seg = i.seg[0];
3609 i.seg[0] = i.seg[1];
3610 i.seg[1] = temp_seg;
3611 }
3612}
252b5132 3613
29b0f896
AM		 3614/* Try to ensure constant immediates are represented in the smallest
3615 opcode possible. */
3616static void
e3bb37b5 3617optimize_imm (void)
29b0f896
AM		 3618{
3619 char guess_suffix = 0;
3620 int op;
252b5132 3621
29b0f896
AM		 3622 if (i.suffix)
3623 guess_suffix = i.suffix;
3624 else if (i.reg_operands)
3625 {
3626 /* Figure out a suffix from the last register operand specified.
3627 We can't do this properly yet, ie. excluding InOutPortReg,
3628 but the following works for instructions with immediates.
3629 In any case, we can't set i.suffix yet. */
3630 for (op = i.operands; --op >= 0;)
40fb9820 3631 if (i.types[op].bitfield.reg8)
7ab9ffdd 3632 {
40fb9820
L		 3633 guess_suffix = BYTE_MNEM_SUFFIX;
3634 break;
3635 }
3636 else if (i.types[op].bitfield.reg16)
252b5132 3637 {
40fb9820
L		 3638 guess_suffix = WORD_MNEM_SUFFIX;
3639 break;
3640 }
3641 else if (i.types[op].bitfield.reg32)
3642 {
3643 guess_suffix = LONG_MNEM_SUFFIX;
3644 break;
3645 }
3646 else if (i.types[op].bitfield.reg64)
3647 {
3648 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3649 break;
252b5132 3650 }
29b0f896
AM		 3651 }
3652 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3653 guess_suffix = WORD_MNEM_SUFFIX;
3654
3655 for (op = i.operands; --op >= 0;)
40fb9820 3656 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3657 {
3658 switch (i.op[op].imms->X_op)
252b5132 3659 {
29b0f896
AM		 3660 case O_constant:
3661 /* If a suffix is given, this operand may be shortened. */
3662 switch (guess_suffix)
252b5132 3663 {
29b0f896 3664 case LONG_MNEM_SUFFIX:
40fb9820
L		 3665 i.types[op].bitfield.imm32 = 1;
3666 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3667 break;
3668 case WORD_MNEM_SUFFIX:
40fb9820
L		 3669 i.types[op].bitfield.imm16 = 1;
3670 i.types[op].bitfield.imm32 = 1;
3671 i.types[op].bitfield.imm32s = 1;
3672 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3673 break;
3674 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3675 i.types[op].bitfield.imm8 = 1;
3676 i.types[op].bitfield.imm8s = 1;
3677 i.types[op].bitfield.imm16 = 1;
3678 i.types[op].bitfield.imm32 = 1;
3679 i.types[op].bitfield.imm32s = 1;
3680 i.types[op].bitfield.imm64 = 1;
29b0f896 3681 break;
252b5132 3682 }
252b5132 3683
29b0f896
AM		 3684 /* If this operand is at most 16 bits, convert it
3685 to a signed 16 bit number before trying to see
3686 whether it will fit in an even smaller size.
3687 This allows a 16-bit operand such as $0xffe0 to
3688 be recognised as within Imm8S range. */
40fb9820 3689 if ((i.types[op].bitfield.imm16)
29b0f896 3690 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3691 {
29b0f896
AM		 3692 i.op[op].imms->X_add_number =
3693 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3694 }
40fb9820 3695 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3696 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3697 == 0))
3698 {
3699 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3700 ^ ((offsetT) 1 << 31))
3701 - ((offsetT) 1 << 31));
3702 }
40fb9820 3703 i.types[op]
c6fb90c8
L		 3704 = operand_type_or (i.types[op],
3705 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3706
29b0f896
AM		 3707 /* We must avoid matching of Imm32 templates when 64bit
3708 only immediate is available. */
3709 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3710 i.types[op].bitfield.imm32 = 0;
29b0f896 3711 break;
252b5132 3712
29b0f896
AM		 3713 case O_absent:
3714 case O_register:
3715 abort ();
3716
3717 /* Symbols and expressions. */
3718 default:
9cd96992
JB		 3719 /* Convert symbolic operand to proper sizes for matching, but don't
3720 prevent matching a set of insns that only supports sizes other
3721 than those matching the insn suffix. */
3722 {
40fb9820 3723 i386_operand_type mask, allowed;
d3ce72d0 3724 const insn_template *t;
9cd96992 3725
0dfbf9d7
L		 3726 operand_type_set (&mask, 0);
3727 operand_type_set (&allowed, 0);
40fb9820 3728
4eed87de
AM		 3729 for (t = current_templates->start;
3730 t < current_templates->end;
3731 ++t)
c6fb90c8
L		 3732 allowed = operand_type_or (allowed,
3733 t->operand_types[op]);
9cd96992
JB		 3734 switch (guess_suffix)
3735 {
3736 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3737 mask.bitfield.imm64 = 1;
3738 mask.bitfield.imm32s = 1;
9cd96992
JB		 3739 break;
3740 case LONG_MNEM_SUFFIX:
40fb9820 3741 mask.bitfield.imm32 = 1;
9cd96992
JB		 3742 break;
3743 case WORD_MNEM_SUFFIX:
40fb9820 3744 mask.bitfield.imm16 = 1;
9cd96992
JB		 3745 break;
3746 case BYTE_MNEM_SUFFIX:
40fb9820 3747 mask.bitfield.imm8 = 1;
9cd96992
JB		 3748 break;
3749 default:
9cd96992
JB		 3750 break;
3751 }
c6fb90c8 3752 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3753 if (!operand_type_all_zero (&allowed))
c6fb90c8 3754 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3755 }
29b0f896 3756 break;
252b5132 3757 }
29b0f896
AM		 3758 }
3759}
47926f60 3760
29b0f896
AM		 3761/* Try to use the smallest displacement type too. */
3762static void
e3bb37b5 3763optimize_disp (void)
29b0f896
AM		 3764{
3765 int op;
3e73aa7c 3766
29b0f896 3767 for (op = i.operands; --op >= 0;)
40fb9820 3768 if (operand_type_check (i.types[op], disp))
252b5132 3769 {
b300c311 3770 if (i.op[op].disps->X_op == O_constant)
252b5132 3771 {
91d6fa6a 3772 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3773
40fb9820 3774 if (i.types[op].bitfield.disp16
91d6fa6a 3775 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3776 {
3777 /* If this operand is at most 16 bits, convert
3778 to a signed 16 bit number and don't use 64bit
3779 displacement. */
91d6fa6a 3780 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3781 i.types[op].bitfield.disp64 = 0;
b300c311 3782 }
40fb9820 3783 if (i.types[op].bitfield.disp32
91d6fa6a 3784 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3785 {
3786 /* If this operand is at most 32 bits, convert
3787 to a signed 32 bit number and don't use 64bit
3788 displacement. */
91d6fa6a
NC		 3789 op_disp &= (((offsetT) 2 << 31) - 1);
3790 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3791 i.types[op].bitfield.disp64 = 0;
b300c311 3792 }
91d6fa6a 3793 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3794 {
40fb9820
L		 3795 i.types[op].bitfield.disp8 = 0;
3796 i.types[op].bitfield.disp16 = 0;
3797 i.types[op].bitfield.disp32 = 0;
3798 i.types[op].bitfield.disp32s = 0;
3799 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3800 i.op[op].disps = 0;
3801 i.disp_operands--;
3802 }
3803 else if (flag_code == CODE_64BIT)
3804 {
91d6fa6a 3805 if (fits_in_signed_long (op_disp))
28a9d8f5 3806 {
40fb9820
L		 3807 i.types[op].bitfield.disp64 = 0;
3808 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3809 }
0e1147d9 3810 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3811 && fits_in_unsigned_long (op_disp))
40fb9820 3812 i.types[op].bitfield.disp32 = 1;
b300c311 3813 }
40fb9820
L		 3814 if ((i.types[op].bitfield.disp32
3815 || i.types[op].bitfield.disp32s
3816 || i.types[op].bitfield.disp16)
91d6fa6a 3817 && fits_in_signed_byte (op_disp))
40fb9820 3818 i.types[op].bitfield.disp8 = 1;
252b5132 3819 }
67a4f2b7
AO		 3820 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3821 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3822 {
3823 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3824 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3825 i.types[op].bitfield.disp8 = 0;
3826 i.types[op].bitfield.disp16 = 0;
3827 i.types[op].bitfield.disp32 = 0;
3828 i.types[op].bitfield.disp32s = 0;
3829 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3830 }
3831 else
b300c311 3832 /* We only support 64bit displacement on constants. */
40fb9820 3833 i.types[op].bitfield.disp64 = 0;
252b5132 3834 }
29b0f896
AM		 3835}
3836
43f3e2ee 3837/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3838 operand types. */
3839
3840static int
3841VEX_check_operands (const insn_template *t)
3842{
3843 if (!t->opcode_modifier.vex)
3844 return 0;
3845
3846 /* Only check VEX_Imm4, which must be the first operand. */
3847 if (t->operand_types[0].bitfield.vec_imm4)
3848 {
3849 if (i.op[0].imms->X_op != O_constant
3850 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3851 {
a65babc9 3852 i.error = bad_imm4;
891edac4
L		 3853 return 1;
3854 }
a683cc34
SP		 3855
3856 /* Turn off Imm8 so that update_imm won't complain. */
3857 i.types[0] = vec_imm4;
3858 }
3859
3860 return 0;
3861}
3862
d3ce72d0 3863static const insn_template *
e3bb37b5 3864match_template (void)
29b0f896
AM		 3865{
3866 /* Points to template once we've found it. */
d3ce72d0 3867 const insn_template *t;
40fb9820 3868 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3869 i386_operand_type overlap4;
29b0f896 3870 unsigned int found_reverse_match;
40fb9820
L		 3871 i386_opcode_modifier suffix_check;
3872 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3873 int addr_prefix_disp;
a5c311ca 3874 unsigned int j;
3629bb00 3875 unsigned int found_cpu_match;
45664ddb 3876 unsigned int check_register;
29b0f896 3877
c0f3af97
L		 3878#if MAX_OPERANDS != 5
3879# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3880#endif
3881
29b0f896 3882 found_reverse_match = 0;
539e75ad 3883 addr_prefix_disp = -1;
40fb9820
L		 3884
3885 memset (&suffix_check, 0, sizeof (suffix_check));
3886 if (i.suffix == BYTE_MNEM_SUFFIX)
3887 suffix_check.no_bsuf = 1;
3888 else if (i.suffix == WORD_MNEM_SUFFIX)
3889 suffix_check.no_wsuf = 1;
3890 else if (i.suffix == SHORT_MNEM_SUFFIX)
3891 suffix_check.no_ssuf = 1;
3892 else if (i.suffix == LONG_MNEM_SUFFIX)
3893 suffix_check.no_lsuf = 1;
3894 else if (i.suffix == QWORD_MNEM_SUFFIX)
3895 suffix_check.no_qsuf = 1;
3896 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3897 suffix_check.no_ldsuf = 1;
29b0f896 3898
01559ecc
L		 3899 /* Must have right number of operands. */
3900 i.error = number_of_operands_mismatch;
3901
45aa61fe 3902 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3903 {
539e75ad
L		 3904 addr_prefix_disp = -1;
3905
29b0f896
AM		 3906 if (i.operands != t->operands)
3907 continue;
3908
50aecf8c 3909 /* Check processor support. */
a65babc9 3910 i.error = unsupported;
c0f3af97
L		 3911 found_cpu_match = (cpu_flags_match (t)
3912 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3913 if (!found_cpu_match)
3914 continue;
3915
e1d4d893 3916 /* Check old gcc support. */
a65babc9 3917 i.error = old_gcc_only;
e1d4d893
L		 3918 if (!old_gcc && t->opcode_modifier.oldgcc)
3919 continue;
3920
3921 /* Check AT&T mnemonic. */
a65babc9 3922 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3923 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3924 continue;
3925
891edac4 3926 /* Check AT&T/Intel syntax. */
a65babc9 3927 i.error = unsupported_syntax;
5c07affc
L		 3928 if ((intel_syntax && t->opcode_modifier.attsyntax)
3929 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3930 continue;
3931
20592a94 3932 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3933 i.error = invalid_instruction_suffix;
567e4e96
L		 3934 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3935 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3936 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3937 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3938 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3939 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3940 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3941 continue;
3942
5c07affc 3943 if (!operand_size_match (t))
7d5e4556 3944 continue;
539e75ad 3945
5c07affc
L		 3946 for (j = 0; j < MAX_OPERANDS; j++)
3947 operand_types[j] = t->operand_types[j];
3948
45aa61fe
AM		 3949 /* In general, don't allow 64-bit operands in 32-bit mode. */
3950 if (i.suffix == QWORD_MNEM_SUFFIX
3951 && flag_code != CODE_64BIT
3952 && (intel_syntax
40fb9820 3953 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3954 && !intel_float_operand (t->name))
3955 : intel_float_operand (t->name) != 2)
40fb9820 3956 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3957 && !operand_types[0].bitfield.regxmm
3958 && !operand_types[0].bitfield.regymm)
40fb9820 3959 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3960 && !!operand_types[t->operands > 1].bitfield.regxmm
3961 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3962 && (t->base_opcode != 0x0fc7
3963 || t->extension_opcode != 1 /* cmpxchg8b */))
3964 continue;
3965
192dc9c6
JB		 3966 /* In general, don't allow 32-bit operands on pre-386. */
3967 else if (i.suffix == LONG_MNEM_SUFFIX
3968 && !cpu_arch_flags.bitfield.cpui386
3969 && (intel_syntax
3970 ? (!t->opcode_modifier.ignoresize
3971 && !intel_float_operand (t->name))
3972 : intel_float_operand (t->name) != 2)
3973 && ((!operand_types[0].bitfield.regmmx
3974 && !operand_types[0].bitfield.regxmm)
3975 || (!operand_types[t->operands > 1].bitfield.regmmx
3976 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3977 continue;
3978
29b0f896 3979 /* Do not verify operands when there are none. */
50aecf8c 3980 else
29b0f896 3981 {
c6fb90c8 3982 if (!t->operands)
2dbab7d5
L		 3983 /* We've found a match; break out of loop. */
3984 break;
29b0f896 3985 }
252b5132 3986
539e75ad
L		 3987 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3988 into Disp32/Disp16/Disp32 operand. */
3989 if (i.prefix[ADDR_PREFIX] != 0)
3990 {
40fb9820 3991 /* There should be only one Disp operand. */
539e75ad
L		 3992 switch (flag_code)
3993 {
3994 case CODE_16BIT:
40fb9820
L		 3995 for (j = 0; j < MAX_OPERANDS; j++)
3996 {
3997 if (operand_types[j].bitfield.disp16)
3998 {
3999 addr_prefix_disp = j;
4000 operand_types[j].bitfield.disp32 = 1;
4001 operand_types[j].bitfield.disp16 = 0;
4002 break;
4003 }
4004 }
539e75ad
L		 4005 break;
4006 case CODE_32BIT:
40fb9820
L		 4007 for (j = 0; j < MAX_OPERANDS; j++)
4008 {
4009 if (operand_types[j].bitfield.disp32)
4010 {
4011 addr_prefix_disp = j;
4012 operand_types[j].bitfield.disp32 = 0;
4013 operand_types[j].bitfield.disp16 = 1;
4014 break;
4015 }
4016 }
539e75ad
L		 4017 break;
4018 case CODE_64BIT:
40fb9820
L		 4019 for (j = 0; j < MAX_OPERANDS; j++)
4020 {
4021 if (operand_types[j].bitfield.disp64)
4022 {
4023 addr_prefix_disp = j;
4024 operand_types[j].bitfield.disp64 = 0;
4025 operand_types[j].bitfield.disp32 = 1;
4026 break;
4027 }
4028 }
539e75ad
L		 4029 break;
4030 }
539e75ad
L		 4031 }
4032
56ffb741
L		 4033 /* We check register size if needed. */
4034 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4035 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4036 switch (t->operands)
4037 {
4038 case 1:
40fb9820 4039 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4040 continue;
4041 break;
4042 case 2:
8b38ad71
L		 4043 /* xchg %eax, %eax is a special case. It is an aliase for nop
4044 only in 32bit mode and we can use opcode 0x90. In 64bit
4045 mode, we can't use 0x90 for xchg %eax, %eax since it should
4046 zero-extend %eax to %rax. */
4047 if (flag_code == CODE_64BIT
4048 && t->base_opcode == 0x90
0dfbf9d7
L		 4049 && operand_type_equal (&i.types [0], &acc32)
4050 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4051 continue;
b6169b20
L		 4052 if (i.swap_operand)
4053 {
4054 /* If we swap operand in encoding, we either match
4055 the next one or reverse direction of operands. */
4056 if (t->opcode_modifier.s)
4057 continue;
4058 else if (t->opcode_modifier.d)
4059 goto check_reverse;
4060 }
4061
29b0f896 4062 case 3:
fa99fab2
L		 4063 /* If we swap operand in encoding, we match the next one. */
4064 if (i.swap_operand && t->opcode_modifier.s)
4065 continue;
f48ff2ae 4066 case 4:
c0f3af97 4067 case 5:
c6fb90c8 4068 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4069 if (!operand_type_match (overlap0, i.types[0])
4070 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4071 || (check_register
4072 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4073 operand_types[0],
4074 overlap1, i.types[1],
4075 operand_types[1])))
29b0f896
AM		 4076 {
4077 /* Check if other direction is valid ... */
40fb9820 4078 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4079 continue;
4080
b6169b20 4081check_reverse:
29b0f896 4082 /* Try reversing direction of operands. */
c6fb90c8
L		 4083 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4084 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4085 if (!operand_type_match (overlap0, i.types[0])
4086 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4087 || (check_register
4088 && !operand_type_register_match (overlap0,
4089 i.types[0],
4090 operand_types[1],
4091 overlap1,
4092 i.types[1],
4093 operand_types[0])))
29b0f896
AM		 4094 {
4095 /* Does not match either direction. */
4096 continue;
4097 }
4098 /* found_reverse_match holds which of D or FloatDR
4099 we've found. */
40fb9820 4100 if (t->opcode_modifier.d)
8a2ed489 4101 found_reverse_match = Opcode_D;
40fb9820 4102 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4103 found_reverse_match = Opcode_FloatD;
4104 else
4105 found_reverse_match = 0;
40fb9820 4106 if (t->opcode_modifier.floatr)
8a2ed489 4107 found_reverse_match |= Opcode_FloatR;
29b0f896 4108 }
f48ff2ae 4109 else
29b0f896 4110 {
f48ff2ae 4111 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4112 switch (t->operands)
4113 {
c0f3af97
L		 4114 case 5:
4115 overlap4 = operand_type_and (i.types[4],
4116 operand_types[4]);
d1cbb4db 4117 case 4:
c6fb90c8
L		 4118 overlap3 = operand_type_and (i.types[3],
4119 operand_types[3]);
d1cbb4db 4120 case 3:
c6fb90c8
L		 4121 overlap2 = operand_type_and (i.types[2],
4122 operand_types[2]);
d1cbb4db
L		 4123 break;
4124 }
29b0f896 4125
f48ff2ae
L		 4126 switch (t->operands)
4127 {
c0f3af97
L		 4128 case 5:
4129 if (!operand_type_match (overlap4, i.types[4])
4130 || !operand_type_register_match (overlap3,
4131 i.types[3],
4132 operand_types[3],
4133 overlap4,
4134 i.types[4],
4135 operand_types[4]))
4136 continue;
f48ff2ae 4137 case 4:
40fb9820 4138 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4139 || (check_register
4140 && !operand_type_register_match (overlap2,
4141 i.types[2],
4142 operand_types[2],
4143 overlap3,
4144 i.types[3],
4145 operand_types[3])))
f48ff2ae
L		 4146 continue;
4147 case 3:
4148 /* Here we make use of the fact that there are no
4149 reverse match 3 operand instructions, and all 3
4150 operand instructions only need to be checked for
4151 register consistency between operands 2 and 3. */
40fb9820 4152 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4153 || (check_register
4154 && !operand_type_register_match (overlap1,
4155 i.types[1],
4156 operand_types[1],
4157 overlap2,
4158 i.types[2],
4159 operand_types[2])))
f48ff2ae
L		 4160 continue;
4161 break;
4162 }
29b0f896 4163 }
f48ff2ae 4164 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4165 slip through to break. */
4166 }
3629bb00 4167 if (!found_cpu_match)
29b0f896
AM		 4168 {
4169 found_reverse_match = 0;
4170 continue;
4171 }
c0f3af97 4172
a683cc34
SP		 4173 /* Check if VEX operands are valid. */
4174 if (VEX_check_operands (t))
4175 continue;
4176
29b0f896
AM		 4177 /* We've found a match; break out of loop. */
4178 break;
4179 }
4180
4181 if (t == current_templates->end)
4182 {
4183 /* We found no match. */
a65babc9
L		 4184 const char *err_msg;
4185 switch (i.error)
4186 {
4187 default:
4188 abort ();
86e026a4 4189 case operand_size_mismatch:
a65babc9
L		 4190 err_msg = _("operand size mismatch");
4191 break;
4192 case operand_type_mismatch:
4193 err_msg = _("operand type mismatch");
4194 break;
4195 case register_type_mismatch:
4196 err_msg = _("register type mismatch");
4197 break;
4198 case number_of_operands_mismatch:
4199 err_msg = _("number of operands mismatch");
4200 break;
4201 case invalid_instruction_suffix:
4202 err_msg = _("invalid instruction suffix");
4203 break;
4204 case bad_imm4:
4205 err_msg = _("Imm4 isn't the first operand");
4206 break;
4207 case old_gcc_only:
4208 err_msg = _("only supported with old gcc");
4209 break;
4210 case unsupported_with_intel_mnemonic:
4211 err_msg = _("unsupported with Intel mnemonic");
4212 break;
4213 case unsupported_syntax:
4214 err_msg = _("unsupported syntax");
4215 break;
4216 case unsupported:
4217 err_msg = _("unsupported");
4218 break;
4219 }
4220 as_bad (_("%s for `%s'"), err_msg,
891edac4 4221 current_templates->start->name);
fa99fab2 4222 return NULL;
29b0f896 4223 }
252b5132 4224
29b0f896
AM		 4225 if (!quiet_warnings)
4226 {
4227 if (!intel_syntax
40fb9820
L		 4228 && (i.types[0].bitfield.jumpabsolute
4229 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4230 {
4231 as_warn (_("indirect %s without `*'"), t->name);
4232 }
4233
40fb9820
L		 4234 if (t->opcode_modifier.isprefix
4235 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4236 {
4237 /* Warn them that a data or address size prefix doesn't
4238 affect assembly of the next line of code. */
4239 as_warn (_("stand-alone `%s' prefix"), t->name);
4240 }
4241 }
4242
4243 /* Copy the template we found. */
4244 i.tm = *t;
539e75ad
L		 4245
4246 if (addr_prefix_disp != -1)
4247 i.tm.operand_types[addr_prefix_disp]
4248 = operand_types[addr_prefix_disp];
4249
29b0f896
AM		 4250 if (found_reverse_match)
4251 {
4252 /* If we found a reverse match we must alter the opcode
4253 direction bit. found_reverse_match holds bits to change
4254 (different for int & float insns). */
4255
4256 i.tm.base_opcode ^= found_reverse_match;
4257
539e75ad
L		 4258 i.tm.operand_types[0] = operand_types[1];
4259 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4260 }
4261
fa99fab2 4262 return t;
29b0f896
AM		 4263}
4264
4265static int
e3bb37b5 4266check_string (void)
29b0f896 4267{
40fb9820
L		 4268 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4269 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4270 {
4271 if (i.seg[0] != NULL && i.seg[0] != &es)
4272 {
a87af027 4273 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4274 i.tm.name,
a87af027
JB		 4275 mem_op + 1,
4276 register_prefix);
29b0f896
AM		 4277 return 0;
4278 }
4279 /* There's only ever one segment override allowed per instruction.
4280 This instruction possibly has a legal segment override on the
4281 second operand, so copy the segment to where non-string
4282 instructions store it, allowing common code. */
4283 i.seg[0] = i.seg[1];
4284 }
40fb9820 4285 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4286 {
4287 if (i.seg[1] != NULL && i.seg[1] != &es)
4288 {
a87af027 4289 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4290 i.tm.name,
a87af027
JB		 4291 mem_op + 2,
4292 register_prefix);
29b0f896
AM		 4293 return 0;
4294 }
4295 }
4296 return 1;
4297}
4298
4299static int
543613e9 4300process_suffix (void)
29b0f896
AM		 4301{
4302 /* If matched instruction specifies an explicit instruction mnemonic
4303 suffix, use it. */
40fb9820
L		 4304 if (i.tm.opcode_modifier.size16)
4305 i.suffix = WORD_MNEM_SUFFIX;
4306 else if (i.tm.opcode_modifier.size32)
4307 i.suffix = LONG_MNEM_SUFFIX;
4308 else if (i.tm.opcode_modifier.size64)
4309 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4310 else if (i.reg_operands)
4311 {
4312 /* If there's no instruction mnemonic suffix we try to invent one
4313 based on register operands. */
4314 if (!i.suffix)
4315 {
4316 /* We take i.suffix from the last register operand specified,
4317 Destination register type is more significant than source
381d071f
L		 4318 register type. crc32 in SSE4.2 prefers source register
4319 type. */
4320 if (i.tm.base_opcode == 0xf20f38f1)
4321 {
40fb9820
L		 4322 if (i.types[0].bitfield.reg16)
4323 i.suffix = WORD_MNEM_SUFFIX;
4324 else if (i.types[0].bitfield.reg32)
4325 i.suffix = LONG_MNEM_SUFFIX;
4326 else if (i.types[0].bitfield.reg64)
4327 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4328 }
9344ff29 4329 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4330 {
40fb9820 4331 if (i.types[0].bitfield.reg8)
20592a94
L		 4332 i.suffix = BYTE_MNEM_SUFFIX;
4333 }
381d071f
L		 4334
4335 if (!i.suffix)
4336 {
4337 int op;
4338
20592a94
L		 4339 if (i.tm.base_opcode == 0xf20f38f1
4340 || i.tm.base_opcode == 0xf20f38f0)
4341 {
4342 /* We have to know the operand size for crc32. */
4343 as_bad (_("ambiguous memory operand size for `%s`"),
4344 i.tm.name);
4345 return 0;
4346 }
4347
381d071f 4348 for (op = i.operands; --op >= 0;)
40fb9820 4349 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4350 {
40fb9820
L		 4351 if (i.types[op].bitfield.reg8)
4352 {
4353 i.suffix = BYTE_MNEM_SUFFIX;
4354 break;
4355 }
4356 else if (i.types[op].bitfield.reg16)
4357 {
4358 i.suffix = WORD_MNEM_SUFFIX;
4359 break;
4360 }
4361 else if (i.types[op].bitfield.reg32)
4362 {
4363 i.suffix = LONG_MNEM_SUFFIX;
4364 break;
4365 }
4366 else if (i.types[op].bitfield.reg64)
4367 {
4368 i.suffix = QWORD_MNEM_SUFFIX;
4369 break;
4370 }
381d071f
L		 4371 }
4372 }
29b0f896
AM		 4373 }
4374 else if (i.suffix == BYTE_MNEM_SUFFIX)
4375 {
2eb952a4
L		 4376 if (intel_syntax
4377 && i.tm.opcode_modifier.ignoresize
4378 && i.tm.opcode_modifier.no_bsuf)
4379 i.suffix = 0;
4380 else if (!check_byte_reg ())
29b0f896
AM		 4381 return 0;
4382 }
4383 else if (i.suffix == LONG_MNEM_SUFFIX)
4384 {
2eb952a4
L		 4385 if (intel_syntax
4386 && i.tm.opcode_modifier.ignoresize
4387 && i.tm.opcode_modifier.no_lsuf)
4388 i.suffix = 0;
4389 else if (!check_long_reg ())
29b0f896
AM		 4390 return 0;
4391 }
4392 else if (i.suffix == QWORD_MNEM_SUFFIX)
4393 {
955e1e6a
L		 4394 if (intel_syntax
4395 && i.tm.opcode_modifier.ignoresize
4396 && i.tm.opcode_modifier.no_qsuf)
4397 i.suffix = 0;
4398 else if (!check_qword_reg ())
29b0f896
AM		 4399 return 0;
4400 }
4401 else if (i.suffix == WORD_MNEM_SUFFIX)
4402 {
2eb952a4
L		 4403 if (intel_syntax
4404 && i.tm.opcode_modifier.ignoresize
4405 && i.tm.opcode_modifier.no_wsuf)
4406 i.suffix = 0;
4407 else if (!check_word_reg ())
29b0f896
AM		 4408 return 0;
4409 }
c0f3af97
L		 4410 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4411 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4412 {
c0f3af97 4413 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4414 should check if it is a valid suffix. */
4415 }
40fb9820 4416 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4417 /* Do nothing if the instruction is going to ignore the prefix. */
4418 ;
4419 else
4420 abort ();
4421 }
40fb9820 4422 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4423 && !i.suffix
4424 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4425 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4426 {
4427 i.suffix = stackop_size;
4428 }
9306ca4a
JB		 4429 else if (intel_syntax
4430 && !i.suffix
40fb9820
L		 4431 && (i.tm.operand_types[0].bitfield.jumpabsolute
4432 || i.tm.opcode_modifier.jumpbyte
4433 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4434 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4435 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4436 {
4437 switch (flag_code)
4438 {
4439 case CODE_64BIT:
40fb9820 4440 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4441 {
4442 i.suffix = QWORD_MNEM_SUFFIX;
4443 break;
4444 }
4445 case CODE_32BIT:
40fb9820 4446 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4447 i.suffix = LONG_MNEM_SUFFIX;
4448 break;
4449 case CODE_16BIT:
40fb9820 4450 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4451 i.suffix = WORD_MNEM_SUFFIX;
4452 break;
4453 }
4454 }
252b5132 4455
9306ca4a 4456 if (!i.suffix)
29b0f896 4457 {
9306ca4a
JB		 4458 if (!intel_syntax)
4459 {
40fb9820 4460 if (i.tm.opcode_modifier.w)
9306ca4a 4461 {
4eed87de
AM		 4462 as_bad (_("no instruction mnemonic suffix given and "
4463 "no register operands; can't size instruction"));
9306ca4a
JB		 4464 return 0;
4465 }
4466 }
4467 else
4468 {
40fb9820 4469 unsigned int suffixes;
7ab9ffdd 4470
40fb9820
L		 4471 suffixes = !i.tm.opcode_modifier.no_bsuf;
4472 if (!i.tm.opcode_modifier.no_wsuf)
4473 suffixes |= 1 << 1;
4474 if (!i.tm.opcode_modifier.no_lsuf)
4475 suffixes |= 1 << 2;
fc4adea1 4476 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4477 suffixes |= 1 << 3;
4478 if (!i.tm.opcode_modifier.no_ssuf)
4479 suffixes |= 1 << 4;
4480 if (!i.tm.opcode_modifier.no_qsuf)
4481 suffixes |= 1 << 5;
4482
4483 /* There are more than suffix matches. */
4484 if (i.tm.opcode_modifier.w
9306ca4a 4485 || ((suffixes & (suffixes - 1))
40fb9820
L		 4486 && !i.tm.opcode_modifier.defaultsize
4487 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4488 {
4489 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4490 return 0;
4491 }
4492 }
29b0f896 4493 }
252b5132 4494
9306ca4a
JB		 4495 /* Change the opcode based on the operand size given by i.suffix;
4496 We don't need to change things for byte insns. */
4497
582d5edd
L		 4498 if (i.suffix
4499 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4500 && i.suffix != XMMWORD_MNEM_SUFFIX
4501 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4502 {
4503 /* It's not a byte, select word/dword operation. */
40fb9820 4504 if (i.tm.opcode_modifier.w)
29b0f896 4505 {
40fb9820 4506 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4507 i.tm.base_opcode |= 8;
4508 else
4509 i.tm.base_opcode |= 1;
4510 }
0f3f3d8b 4511
29b0f896
AM		 4512 /* Now select between word & dword operations via the operand
4513 size prefix, except for instructions that will ignore this
4514 prefix anyway. */
ca61edf2 4515 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4516 {
ca61edf2
L		 4517 /* The address size override prefix changes the size of the
4518 first operand. */
40fb9820
L		 4519 if ((flag_code == CODE_32BIT
4520 && i.op->regs[0].reg_type.bitfield.reg16)
4521 || (flag_code != CODE_32BIT
4522 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4523 if (!add_prefix (ADDR_PREFIX_OPCODE))
4524 return 0;
4525 }
4526 else if (i.suffix != QWORD_MNEM_SUFFIX
4527 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4528 && !i.tm.opcode_modifier.ignoresize
4529 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4530 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4531 || (flag_code == CODE_64BIT
40fb9820 4532 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4533 {
4534 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4535
40fb9820 4536 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4537 prefix = ADDR_PREFIX_OPCODE;
252b5132 4538
29b0f896
AM		 4539 if (!add_prefix (prefix))
4540 return 0;
24eab124 4541 }
252b5132 4542
29b0f896
AM		 4543 /* Set mode64 for an operand. */
4544 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4545 && flag_code == CODE_64BIT
40fb9820 4546 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4547 {
4548 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4549 need rex64. cmpxchg8b is also a special case. */
4550 if (! (i.operands == 2
4551 && i.tm.base_opcode == 0x90
4552 && i.tm.extension_opcode == None
0dfbf9d7
L		 4553 && operand_type_equal (&i.types [0], &acc64)
4554 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4555 && ! (i.operands == 1
4556 && i.tm.base_opcode == 0xfc7
4557 && i.tm.extension_opcode == 1
40fb9820
L		 4558 && !operand_type_check (i.types [0], reg)
4559 && operand_type_check (i.types [0], anymem)))
f6bee062 4560 i.rex |= REX_W;
46e883c5 4561 }
3e73aa7c 4562
29b0f896
AM		 4563 /* Size floating point instruction. */
4564 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4565 if (i.tm.opcode_modifier.floatmf)
543613e9 4566 i.tm.base_opcode ^= 4;
29b0f896 4567 }
7ecd2f8b 4568
29b0f896
AM		 4569 return 1;
4570}
3e73aa7c 4571
29b0f896 4572static int
543613e9 4573check_byte_reg (void)
29b0f896
AM		 4574{
4575 int op;
543613e9 4576
29b0f896
AM		 4577 for (op = i.operands; --op >= 0;)
4578 {
4579 /* If this is an eight bit register, it's OK. If it's the 16 or
4580 32 bit version of an eight bit register, we will just use the
4581 low portion, and that's OK too. */
40fb9820 4582 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4583 continue;
4584
9344ff29
L		 4585 /* crc32 doesn't generate this warning. */
4586 if (i.tm.base_opcode == 0xf20f38f0)
4587 continue;
4588
40fb9820
L		 4589 if ((i.types[op].bitfield.reg16
4590 || i.types[op].bitfield.reg32
4591 || i.types[op].bitfield.reg64)
4592 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4593 {
4594 /* Prohibit these changes in the 64bit mode, since the
4595 lowering is more complicated. */
4596 if (flag_code == CODE_64BIT
40fb9820 4597 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4598 {
2b5d6a91 4599 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4600 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4601 i.suffix);
4602 return 0;
4603 }
4604#if REGISTER_WARNINGS
4605 if (!quiet_warnings
40fb9820 4606 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4607 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4608 register_prefix,
40fb9820 4609 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4610 ? REGNAM_AL - REGNAM_AX
4611 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4612 register_prefix,
29b0f896
AM		 4613 i.op[op].regs->reg_name,
4614 i.suffix);
4615#endif
4616 continue;
4617 }
4618 /* Any other register is bad. */
40fb9820
L		 4619 if (i.types[op].bitfield.reg16
4620 || i.types[op].bitfield.reg32
4621 || i.types[op].bitfield.reg64
4622 || i.types[op].bitfield.regmmx
4623 || i.types[op].bitfield.regxmm
c0f3af97 4624 || i.types[op].bitfield.regymm
40fb9820
L		 4625 || i.types[op].bitfield.sreg2
4626 || i.types[op].bitfield.sreg3
4627 || i.types[op].bitfield.control
4628 || i.types[op].bitfield.debug
4629 || i.types[op].bitfield.test
4630 || i.types[op].bitfield.floatreg
4631 || i.types[op].bitfield.floatacc)
29b0f896 4632 {
a540244d
L		 4633 as_bad (_("`%s%s' not allowed with `%s%c'"),
4634 register_prefix,
29b0f896
AM		 4635 i.op[op].regs->reg_name,
4636 i.tm.name,
4637 i.suffix);
4638 return 0;
4639 }
4640 }
4641 return 1;
4642}
4643
4644static int
e3bb37b5 4645check_long_reg (void)
29b0f896
AM		 4646{
4647 int op;
4648
4649 for (op = i.operands; --op >= 0;)
4650 /* Reject eight bit registers, except where the template requires
4651 them. (eg. movzb) */
40fb9820
L		 4652 if (i.types[op].bitfield.reg8
4653 && (i.tm.operand_types[op].bitfield.reg16
4654 || i.tm.operand_types[op].bitfield.reg32
4655 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4656 {
a540244d
L		 4657 as_bad (_("`%s%s' not allowed with `%s%c'"),
4658 register_prefix,
29b0f896
AM		 4659 i.op[op].regs->reg_name,
4660 i.tm.name,
4661 i.suffix);
4662 return 0;
4663 }
4664 /* Warn if the e prefix on a general reg is missing. */
4665 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4666 && i.types[op].bitfield.reg16
4667 && (i.tm.operand_types[op].bitfield.reg32
4668 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4669 {
4670 /* Prohibit these changes in the 64bit mode, since the
4671 lowering is more complicated. */
4672 if (flag_code == CODE_64BIT)
252b5132 4673 {
2b5d6a91 4674 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4675 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4676 i.suffix);
4677 return 0;
252b5132 4678 }
29b0f896
AM		 4679#if REGISTER_WARNINGS
4680 else
a540244d
L		 4681 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4682 register_prefix,
29b0f896 4683 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4684 register_prefix,
29b0f896
AM		 4685 i.op[op].regs->reg_name,
4686 i.suffix);
4687#endif
252b5132 4688 }
29b0f896 4689 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4690 else if (i.types[op].bitfield.reg64
4691 && (i.tm.operand_types[op].bitfield.reg32
4692 || i.tm.operand_types[op].bitfield.acc))
252b5132 4693 {
34828aad 4694 if (intel_syntax
ca61edf2 4695 && i.tm.opcode_modifier.toqword
40fb9820 4696 && !i.types[0].bitfield.regxmm)
34828aad 4697 {
ca61edf2 4698 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4699 i.suffix = QWORD_MNEM_SUFFIX;
4700 }
4701 else
4702 {
2b5d6a91 4703 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4704 register_prefix, i.op[op].regs->reg_name,
4705 i.suffix);
4706 return 0;
4707 }
29b0f896
AM		 4708 }
4709 return 1;
4710}
252b5132 4711
29b0f896 4712static int
e3bb37b5 4713check_qword_reg (void)
29b0f896
AM		 4714{
4715 int op;
252b5132 4716
29b0f896
AM		 4717 for (op = i.operands; --op >= 0; )
4718 /* Reject eight bit registers, except where the template requires
4719 them. (eg. movzb) */
40fb9820
L		 4720 if (i.types[op].bitfield.reg8
4721 && (i.tm.operand_types[op].bitfield.reg16
4722 || i.tm.operand_types[op].bitfield.reg32
4723 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4724 {
a540244d
L		 4725 as_bad (_("`%s%s' not allowed with `%s%c'"),
4726 register_prefix,
29b0f896
AM		 4727 i.op[op].regs->reg_name,
4728 i.tm.name,
4729 i.suffix);
4730 return 0;
4731 }
4732 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4733 else if ((i.types[op].bitfield.reg16
4734 || i.types[op].bitfield.reg32)
4735 && (i.tm.operand_types[op].bitfield.reg32
4736 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4737 {
4738 /* Prohibit these changes in the 64bit mode, since the
4739 lowering is more complicated. */
34828aad 4740 if (intel_syntax
ca61edf2 4741 && i.tm.opcode_modifier.todword
40fb9820 4742 && !i.types[0].bitfield.regxmm)
34828aad 4743 {
ca61edf2 4744 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4745 i.suffix = LONG_MNEM_SUFFIX;
4746 }
4747 else
4748 {
2b5d6a91 4749 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4750 register_prefix, i.op[op].regs->reg_name,
4751 i.suffix);
4752 return 0;
4753 }
252b5132 4754 }
29b0f896
AM		 4755 return 1;
4756}
252b5132 4757
29b0f896 4758static int
e3bb37b5 4759check_word_reg (void)
29b0f896
AM		 4760{
4761 int op;
4762 for (op = i.operands; --op >= 0;)
4763 /* Reject eight bit registers, except where the template requires
4764 them. (eg. movzb) */
40fb9820
L		 4765 if (i.types[op].bitfield.reg8
4766 && (i.tm.operand_types[op].bitfield.reg16
4767 || i.tm.operand_types[op].bitfield.reg32
4768 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4769 {
a540244d
L		 4770 as_bad (_("`%s%s' not allowed with `%s%c'"),
4771 register_prefix,
29b0f896
AM		 4772 i.op[op].regs->reg_name,
4773 i.tm.name,
4774 i.suffix);
4775 return 0;
4776 }
4777 /* Warn if the e prefix on a general reg is present. */
4778 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4779 && i.types[op].bitfield.reg32
4780 && (i.tm.operand_types[op].bitfield.reg16
4781 || i.tm.operand_types[op].bitfield.acc))
252b5132 4782 {
29b0f896
AM		 4783 /* Prohibit these changes in the 64bit mode, since the
4784 lowering is more complicated. */
4785 if (flag_code == CODE_64BIT)
252b5132 4786 {
2b5d6a91 4787 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4788 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4789 i.suffix);
4790 return 0;
252b5132 4791 }
29b0f896
AM		 4792 else
4793#if REGISTER_WARNINGS
a540244d
L		 4794 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4795 register_prefix,
29b0f896 4796 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4797 register_prefix,
29b0f896
AM		 4798 i.op[op].regs->reg_name,
4799 i.suffix);
4800#endif
4801 }
4802 return 1;
4803}
252b5132 4804
29b0f896 4805static int
40fb9820 4806update_imm (unsigned int j)
29b0f896 4807{
bc0844ae 4808 i386_operand_type overlap = i.types[j];
40fb9820
L		 4809 if ((overlap.bitfield.imm8
4810 || overlap.bitfield.imm8s
4811 || overlap.bitfield.imm16
4812 || overlap.bitfield.imm32
4813 || overlap.bitfield.imm32s
4814 || overlap.bitfield.imm64)
0dfbf9d7
L		 4815 && !operand_type_equal (&overlap, &imm8)
4816 && !operand_type_equal (&overlap, &imm8s)
4817 && !operand_type_equal (&overlap, &imm16)
4818 && !operand_type_equal (&overlap, &imm32)
4819 && !operand_type_equal (&overlap, &imm32s)
4820 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4821 {
4822 if (i.suffix)
4823 {
40fb9820
L		 4824 i386_operand_type temp;
4825
0dfbf9d7 4826 operand_type_set (&temp, 0);
7ab9ffdd 4827 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4828 {
4829 temp.bitfield.imm8 = overlap.bitfield.imm8;
4830 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4831 }
4832 else if (i.suffix == WORD_MNEM_SUFFIX)
4833 temp.bitfield.imm16 = overlap.bitfield.imm16;
4834 else if (i.suffix == QWORD_MNEM_SUFFIX)
4835 {
4836 temp.bitfield.imm64 = overlap.bitfield.imm64;
4837 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4838 }
4839 else
4840 temp.bitfield.imm32 = overlap.bitfield.imm32;
4841 overlap = temp;
29b0f896 4842 }
0dfbf9d7
L		 4843 else if (operand_type_equal (&overlap, &imm16_32_32s)
4844 || operand_type_equal (&overlap, &imm16_32)
4845 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4846 {
40fb9820 4847 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4848 overlap = imm16;
40fb9820 4849 else
65da13b5 4850 overlap = imm32s;
29b0f896 4851 }
0dfbf9d7
L		 4852 if (!operand_type_equal (&overlap, &imm8)
4853 && !operand_type_equal (&overlap, &imm8s)
4854 && !operand_type_equal (&overlap, &imm16)
4855 && !operand_type_equal (&overlap, &imm32)
4856 && !operand_type_equal (&overlap, &imm32s)
4857 && !operand_type_equal (&overlap, &imm64))
29b0f896 4858 {
4eed87de
AM		 4859 as_bad (_("no instruction mnemonic suffix given; "
4860 "can't determine immediate size"));
29b0f896
AM		 4861 return 0;
4862 }
4863 }
40fb9820 4864 i.types[j] = overlap;
29b0f896 4865
40fb9820
L		 4866 return 1;
4867}
4868
4869static int
4870finalize_imm (void)
4871{
bc0844ae 4872 unsigned int j, n;
29b0f896 4873
bc0844ae
L		 4874 /* Update the first 2 immediate operands. */
4875 n = i.operands > 2 ? 2 : i.operands;
4876 if (n)
4877 {
4878 for (j = 0; j < n; j++)
4879 if (update_imm (j) == 0)
4880 return 0;
40fb9820 4881
bc0844ae
L		 4882 /* The 3rd operand can't be immediate operand. */
4883 gas_assert (operand_type_check (i.types[2], imm) == 0);
4884 }
29b0f896
AM		 4885
4886 return 1;
4887}
4888
c0f3af97
L		 4889static int
4890bad_implicit_operand (int xmm)
4891{
91d6fa6a
NC		 4892 const char *ireg = xmm ? "xmm0" : "ymm0";
4893
c0f3af97
L		 4894 if (intel_syntax)
4895 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4896 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4897 else
4898 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4899 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4900 return 0;
4901}
4902
29b0f896 4903static int
e3bb37b5 4904process_operands (void)
29b0f896
AM		 4905{
4906 /* Default segment register this instruction will use for memory
4907 accesses. 0 means unknown. This is only for optimizing out
4908 unnecessary segment overrides. */
4909 const seg_entry *default_seg = 0;
4910
2426c15f 4911 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4912 {
91d6fa6a
NC		 4913 unsigned int dupl = i.operands;
4914 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4915 unsigned int j;
4916
c0f3af97 4917 /* The destination must be an xmm register. */
9c2799c2 4918 gas_assert (i.reg_operands
91d6fa6a 4919 && MAX_OPERANDS > dupl
7ab9ffdd 4920 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4921
4922 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4923 {
c0f3af97 4924 /* The first operand is implicit and must be xmm0. */
9c2799c2 4925 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4926 if (i.op[0].regs->reg_num != 0)
4927 return bad_implicit_operand (1);
4928
8cd7925b 4929 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4930 {
4931 /* Keep xmm0 for instructions with VEX prefix and 3
4932 sources. */
4933 goto duplicate;
4934 }
e2ec9d29 4935 else
c0f3af97
L		 4936 {
4937 /* We remove the first xmm0 and keep the number of
4938 operands unchanged, which in fact duplicates the
4939 destination. */
4940 for (j = 1; j < i.operands; j++)
4941 {
4942 i.op[j - 1] = i.op[j];
4943 i.types[j - 1] = i.types[j];
4944 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4945 }
4946 }
4947 }
4948 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4949 {
91d6fa6a 4950 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4951 && (i.tm.opcode_modifier.vexsources
4952 == VEX3SOURCES));
c0f3af97
L		 4953
4954 /* Add the implicit xmm0 for instructions with VEX prefix
4955 and 3 sources. */
4956 for (j = i.operands; j > 0; j--)
4957 {
4958 i.op[j] = i.op[j - 1];
4959 i.types[j] = i.types[j - 1];
4960 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4961 }
4962 i.op[0].regs
4963 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4964 i.types[0] = regxmm;
c0f3af97
L		 4965 i.tm.operand_types[0] = regxmm;
4966
4967 i.operands += 2;
4968 i.reg_operands += 2;
4969 i.tm.operands += 2;
4970
91d6fa6a 4971 dupl++;
c0f3af97 4972 dest++;
91d6fa6a
NC		 4973 i.op[dupl] = i.op[dest];
4974 i.types[dupl] = i.types[dest];
4975 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4976 }
c0f3af97
L		 4977 else
4978 {
4979duplicate:
4980 i.operands++;
4981 i.reg_operands++;
4982 i.tm.operands++;
4983
91d6fa6a
NC		 4984 i.op[dupl] = i.op[dest];
4985 i.types[dupl] = i.types[dest];
4986 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4987 }
4988
4989 if (i.tm.opcode_modifier.immext)
4990 process_immext ();
4991 }
4992 else if (i.tm.opcode_modifier.firstxmm0)
4993 {
4994 unsigned int j;
4995
4996 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4997 gas_assert (i.reg_operands
7ab9ffdd
L		 4998 && (operand_type_equal (&i.types[0], &regxmm)
4999 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 5000 if (i.op[0].regs->reg_num != 0)
5001 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5002
5003 for (j = 1; j < i.operands; j++)
5004 {
5005 i.op[j - 1] = i.op[j];
5006 i.types[j - 1] = i.types[j];
5007
5008 /* We need to adjust fields in i.tm since they are used by
5009 build_modrm_byte. */
5010 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5011 }
5012
e2ec9d29
L		 5013 i.operands--;
5014 i.reg_operands--;
e2ec9d29
L		 5015 i.tm.operands--;
5016 }
5017 else if (i.tm.opcode_modifier.regkludge)
5018 {
5019 /* The imul $imm, %reg instruction is converted into
5020 imul $imm, %reg, %reg, and the clr %reg instruction
5021 is converted into xor %reg, %reg. */
5022
5023 unsigned int first_reg_op;
5024
5025 if (operand_type_check (i.types[0], reg))
5026 first_reg_op = 0;
5027 else
5028 first_reg_op = 1;
5029 /* Pretend we saw the extra register operand. */
9c2799c2 5030 gas_assert (i.reg_operands == 1
7ab9ffdd 5031 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5032 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5033 i.types[first_reg_op + 1] = i.types[first_reg_op];
5034 i.operands++;
5035 i.reg_operands++;
29b0f896
AM		 5036 }
5037
40fb9820 5038 if (i.tm.opcode_modifier.shortform)
29b0f896 5039 {
40fb9820
L		 5040 if (i.types[0].bitfield.sreg2
5041 || i.types[0].bitfield.sreg3)
29b0f896 5042 {
4eed87de
AM		 5043 if (i.tm.base_opcode == POP_SEG_SHORT
5044 && i.op[0].regs->reg_num == 1)
29b0f896 5045 {
a87af027 5046 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5047 return 0;
29b0f896 5048 }
4eed87de
AM		 5049 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5050 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5051 i.rex |= REX_B;
4eed87de
AM		 5052 }
5053 else
5054 {
7ab9ffdd 5055 /* The register or float register operand is in operand
85f10a01 5056 0 or 1. */
40fb9820 5057 unsigned int op;
7ab9ffdd
L		 5058
5059 if (i.types[0].bitfield.floatreg
5060 || operand_type_check (i.types[0], reg))
5061 op = 0;
5062 else
5063 op = 1;
4eed87de
AM		 5064 /* Register goes in low 3 bits of opcode. */
5065 i.tm.base_opcode |= i.op[op].regs->reg_num;
5066 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5067 i.rex |= REX_B;
40fb9820 5068 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5069 {
4eed87de
AM		 5070 /* Warn about some common errors, but press on regardless.
5071 The first case can be generated by gcc (<= 2.8.1). */
5072 if (i.operands == 2)
5073 {
5074 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5075 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5076 register_prefix, i.op[!intel_syntax].regs->reg_name,
5077 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5078 }
5079 else
5080 {
5081 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5082 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5083 register_prefix, i.op[0].regs->reg_name);
4eed87de 5084 }
29b0f896
AM		 5085 }
5086 }
5087 }
40fb9820 5088 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5089 {
5090 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5091 must be put into the modrm byte). Now, we make the modrm and
5092 index base bytes based on all the info we've collected. */
29b0f896
AM		 5093
5094 default_seg = build_modrm_byte ();
5095 }
8a2ed489 5096 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5097 {
5098 default_seg = &ds;
5099 }
40fb9820 5100 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5101 {
5102 /* For the string instructions that allow a segment override
5103 on one of their operands, the default segment is ds. */
5104 default_seg = &ds;
5105 }
5106
75178d9d
L		 5107 if (i.tm.base_opcode == 0x8d /* lea */
5108 && i.seg[0]
5109 && !quiet_warnings)
30123838 5110 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5111
5112 /* If a segment was explicitly specified, and the specified segment
5113 is not the default, use an opcode prefix to select it. If we
5114 never figured out what the default segment is, then default_seg
5115 will be zero at this point, and the specified segment prefix will
5116 always be used. */
29b0f896
AM		 5117 if ((i.seg[0]) && (i.seg[0] != default_seg))
5118 {
5119 if (!add_prefix (i.seg[0]->seg_prefix))
5120 return 0;
5121 }
5122 return 1;
5123}
5124
5125static const seg_entry *
e3bb37b5 5126build_modrm_byte (void)
29b0f896
AM		 5127{
5128 const seg_entry *default_seg = 0;
c0f3af97 5129 unsigned int source, dest;
8cd7925b 5130 int vex_3_sources;
c0f3af97
L		 5131
5132 /* The first operand of instructions with VEX prefix and 3 sources
5133 must be VEX_Imm4. */
8cd7925b 5134 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5135 if (vex_3_sources)
5136 {
91d6fa6a 5137 unsigned int nds, reg_slot;
4c2c6516 5138 expressionS *exp;
c0f3af97 5139
922d8de8 5140 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5141 && i.tm.opcode_modifier.immext)
5142 {
5143 dest = i.operands - 2;
5144 gas_assert (dest == 3);
5145 }
922d8de8 5146 else
a683cc34 5147 dest = i.operands - 1;
c0f3af97 5148 nds = dest - 1;
922d8de8 5149
a683cc34
SP		 5150 /* There are 2 kinds of instructions:
5151 1. 5 operands: 4 register operands or 3 register operands
5152 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5153 VexW0 or VexW1. The destination must be either XMM or YMM
5154 register.
5155 2. 4 operands: 4 register operands or 3 register operands
5156 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5157 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5158 || (i.reg_operands == 3 && i.mem_operands == 1))
5159 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5160 && (i.tm.opcode_modifier.veximmext
5161 || (i.imm_operands == 1
5162 && i.types[0].bitfield.vec_imm4
5163 && (i.tm.opcode_modifier.vexw == VEXW0
5164 || i.tm.opcode_modifier.vexw == VEXW1)
5165 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5166 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5167
5168 if (i.imm_operands == 0)
5169 {
5170 /* When there is no immediate operand, generate an 8bit
5171 immediate operand to encode the first operand. */
5172 exp = &im_expressions[i.imm_operands++];
5173 i.op[i.operands].imms = exp;
5174 i.types[i.operands] = imm8;
5175 i.operands++;
5176 /* If VexW1 is set, the first operand is the source and
5177 the second operand is encoded in the immediate operand. */
5178 if (i.tm.opcode_modifier.vexw == VEXW1)
5179 {
5180 source = 0;
5181 reg_slot = 1;
5182 }
5183 else
5184 {
5185 source = 1;
5186 reg_slot = 0;
5187 }
5188
5189 /* FMA swaps REG and NDS. */
5190 if (i.tm.cpu_flags.bitfield.cpufma)
5191 {
5192 unsigned int tmp;
5193 tmp = reg_slot;
5194 reg_slot = nds;
5195 nds = tmp;
5196 }
5197
24981e7b
L		 5198 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5199 &regxmm)
a683cc34
SP		 5200 || operand_type_equal (&i.tm.operand_types[reg_slot],
5201 &regymm));
5202 exp->X_op = O_constant;
5203 exp->X_add_number
5204 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5205 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5206 << 4);
a683cc34 5207 }
922d8de8 5208 else
a683cc34
SP		 5209 {
5210 unsigned int imm_slot;
5211
5212 if (i.tm.opcode_modifier.vexw == VEXW0)
5213 {
5214 /* If VexW0 is set, the third operand is the source and
5215 the second operand is encoded in the immediate
5216 operand. */
5217 source = 2;
5218 reg_slot = 1;
5219 }
5220 else
5221 {
5222 /* VexW1 is set, the second operand is the source and
5223 the third operand is encoded in the immediate
5224 operand. */
5225 source = 1;
5226 reg_slot = 2;
5227 }
5228
5229 if (i.tm.opcode_modifier.immext)
5230 {
5231 /* When ImmExt is set, the immdiate byte is the last
5232 operand. */
5233 imm_slot = i.operands - 1;
5234 source--;
5235 reg_slot--;
5236 }
5237 else
5238 {
5239 imm_slot = 0;
5240
5241 /* Turn on Imm8 so that output_imm will generate it. */
5242 i.types[imm_slot].bitfield.imm8 = 1;
5243 }
5244
24981e7b
L		 5245 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5246 &regxmm)
5247 || operand_type_equal (&i.tm.operand_types[reg_slot],
5248 &regymm));
a683cc34
SP		 5249 i.op[imm_slot].imms->X_add_number
5250 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5251 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5252 << 4);
a683cc34
SP		 5253 }
5254
5255 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5256 || operand_type_equal (&i.tm.operand_types[nds],
5257 &regymm));
dae39acc 5258 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5259 }
5260 else
5261 source = dest = 0;
29b0f896
AM		 5262
5263 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5264 implicit registers do not count. If there are 3 register
5265 operands, it must be a instruction with VexNDS. For a
5266 instruction with VexNDD, the destination register is encoded
5267 in VEX prefix. If there are 4 register operands, it must be
5268 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5269 if (i.mem_operands == 0
5270 && ((i.reg_operands == 2
2426c15f 5271 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5272 || (i.reg_operands == 3
2426c15f 5273 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5274 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5275 {
cab737b9
L		 5276 switch (i.operands)
5277 {
5278 case 2:
5279 source = 0;
5280 break;
5281 case 3:
c81128dc
L		 5282 /* When there are 3 operands, one of them may be immediate,
5283 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5284 the first operand must be shift count register (cl) or it
5285 is an instruction with VexNDS. */
9c2799c2 5286 gas_assert (i.imm_operands == 1
7ab9ffdd 5287 || (i.imm_operands == 0
2426c15f 5288 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5289 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5290 if (operand_type_check (i.types[0], imm)
5291 || i.types[0].bitfield.shiftcount)
5292 source = 1;
5293 else
5294 source = 0;
cab737b9
L		 5295 break;
5296 case 4:
368d64cc
L		 5297 /* When there are 4 operands, the first two must be 8bit
5298 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5299 one.
5300
5301 For instructions with VexNDS, if the first operand
5302 an imm8, the source operand is the 2nd one. If the last
5303 operand is imm8, the source operand is the first one. */
9c2799c2 5304 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5305 && i.types[0].bitfield.imm8
5306 && i.types[1].bitfield.imm8)
2426c15f 5307 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5308 && i.imm_operands == 1
5309 && (i.types[0].bitfield.imm8
5310 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5311 if (i.imm_operands == 2)
5312 source = 2;
5313 else
c0f3af97
L		 5314 {
5315 if (i.types[0].bitfield.imm8)
5316 source = 1;
5317 else
5318 source = 0;
5319 }
c0f3af97
L		 5320 break;
5321 case 5:
cab737b9
L		 5322 break;
5323 default:
5324 abort ();
5325 }
5326
c0f3af97
L		 5327 if (!vex_3_sources)
5328 {
5329 dest = source + 1;
5330
2426c15f 5331 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5332 {
5333 /* For instructions with VexNDS, the register-only
f12dc422
L		 5334 source operand must be 32/64bit integer, XMM or
5335 YMM register. It is encoded in VEX prefix. We
5336 need to clear RegMem bit before calling
5337 operand_type_equal. */
5338
5339 i386_operand_type op;
5340 unsigned int vvvv;
5341
5342 /* Check register-only source operand when two source
5343 operands are swapped. */
5344 if (!i.tm.operand_types[source].bitfield.baseindex
5345 && i.tm.operand_types[dest].bitfield.baseindex)
5346 {
5347 vvvv = source;
5348 source = dest;
5349 }
5350 else
5351 vvvv = dest;
5352
5353 op = i.tm.operand_types[vvvv];
fa99fab2 5354 op.bitfield.regmem = 0;
c0f3af97 5355 if ((dest + 1) >= i.operands
f12dc422
L		 5356 || (op.bitfield.reg32 != 1
5357 && !op.bitfield.reg64 != 1
5358 && !operand_type_equal (&op, &regxmm)
fa99fab2 5359 && !operand_type_equal (&op, &regymm)))
c0f3af97 5360 abort ();
f12dc422 5361 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5362 dest++;
5363 }
5364 }
29b0f896
AM		 5365
5366 i.rm.mode = 3;
5367 /* One of the register operands will be encoded in the i.tm.reg
5368 field, the other in the combined i.tm.mode and i.tm.regmem
5369 fields. If no form of this instruction supports a memory
5370 destination operand, then we assume the source operand may
5371 sometimes be a memory operand and so we need to store the
5372 destination in the i.rm.reg field. */
40fb9820
L		 5373 if (!i.tm.operand_types[dest].bitfield.regmem
5374 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5375 {
5376 i.rm.reg = i.op[dest].regs->reg_num;
5377 i.rm.regmem = i.op[source].regs->reg_num;
5378 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5379 i.rex |= REX_R;
29b0f896 5380 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5381 i.rex |= REX_B;
29b0f896
AM		 5382 }
5383 else
5384 {
5385 i.rm.reg = i.op[source].regs->reg_num;
5386 i.rm.regmem = i.op[dest].regs->reg_num;
5387 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5388 i.rex |= REX_B;
29b0f896 5389 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5390 i.rex |= REX_R;
29b0f896 5391 }
161a04f6 5392 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5393 {
40fb9820
L		 5394 if (!i.types[0].bitfield.control
5395 && !i.types[1].bitfield.control)
c4a530c5 5396 abort ();
161a04f6 5397 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5398 add_prefix (LOCK_PREFIX_OPCODE);
5399 }
29b0f896
AM		 5400 }
5401 else
5402 { /* If it's not 2 reg operands... */
c0f3af97
L		 5403 unsigned int mem;
5404
29b0f896
AM		 5405 if (i.mem_operands)
5406 {
5407 unsigned int fake_zero_displacement = 0;
99018f42 5408 unsigned int op;
4eed87de 5409
7ab9ffdd
L		 5410 for (op = 0; op < i.operands; op++)
5411 if (operand_type_check (i.types[op], anymem))
5412 break;
7ab9ffdd 5413 gas_assert (op < i.operands);
29b0f896
AM		 5414
5415 default_seg = &ds;
5416
5417 if (i.base_reg == 0)
5418 {
5419 i.rm.mode = 0;
5420 if (!i.disp_operands)
5421 fake_zero_displacement = 1;
5422 if (i.index_reg == 0)
5423 {
5424 /* Operand is just <disp> */
20f0a1fc 5425 if (flag_code == CODE_64BIT)
29b0f896
AM		 5426 {
5427 /* 64bit mode overwrites the 32bit absolute
5428 addressing by RIP relative addressing and
5429 absolute addressing is encoded by one of the
5430 redundant SIB forms. */
5431 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5432 i.sib.base = NO_BASE_REGISTER;
5433 i.sib.index = NO_INDEX_REGISTER;
fc225355 5434 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5435 ? disp32s : disp32);
20f0a1fc 5436 }
fc225355
L		 5437 else if ((flag_code == CODE_16BIT)
5438 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5439 {
5440 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5441 i.types[op] = disp16;
20f0a1fc
NC		 5442 }
5443 else
5444 {
5445 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5446 i.types[op] = disp32;
29b0f896
AM		 5447 }
5448 }
5449 else /* !i.base_reg && i.index_reg */
5450 {
db51cc60
L		 5451 if (i.index_reg->reg_num == RegEiz
5452 || i.index_reg->reg_num == RegRiz)
5453 i.sib.index = NO_INDEX_REGISTER;
5454 else
5455 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5456 i.sib.base = NO_BASE_REGISTER;
5457 i.sib.scale = i.log2_scale_factor;
5458 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5459 i.types[op].bitfield.disp8 = 0;
5460 i.types[op].bitfield.disp16 = 0;
5461 i.types[op].bitfield.disp64 = 0;
29b0f896 5462 if (flag_code != CODE_64BIT)
40fb9820
L		 5463 {
5464 /* Must be 32 bit */
5465 i.types[op].bitfield.disp32 = 1;
5466 i.types[op].bitfield.disp32s = 0;
5467 }
29b0f896 5468 else
40fb9820
L		 5469 {
5470 i.types[op].bitfield.disp32 = 0;
5471 i.types[op].bitfield.disp32s = 1;
5472 }
29b0f896 5473 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5474 i.rex |= REX_X;
29b0f896
AM		 5475 }
5476 }
5477 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5478 else if (i.base_reg->reg_num == RegRip ||
5479 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5480 {
5481 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5482 i.types[op].bitfield.disp8 = 0;
5483 i.types[op].bitfield.disp16 = 0;
5484 i.types[op].bitfield.disp32 = 0;
5485 i.types[op].bitfield.disp32s = 1;
5486 i.types[op].bitfield.disp64 = 0;
71903a11 5487 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5488 if (! i.disp_operands)
5489 fake_zero_displacement = 1;
29b0f896 5490 }
40fb9820 5491 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5492 {
5493 switch (i.base_reg->reg_num)
5494 {
5495 case 3: /* (%bx) */
5496 if (i.index_reg == 0)
5497 i.rm.regmem = 7;
5498 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5499 i.rm.regmem = i.index_reg->reg_num - 6;
5500 break;
5501 case 5: /* (%bp) */
5502 default_seg = &ss;
5503 if (i.index_reg == 0)
5504 {
5505 i.rm.regmem = 6;
40fb9820 5506 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5507 {
5508 /* fake (%bp) into 0(%bp) */
40fb9820 5509 i.types[op].bitfield.disp8 = 1;
252b5132 5510 fake_zero_displacement = 1;
29b0f896
AM		 5511 }
5512 }
5513 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5514 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5515 break;
5516 default: /* (%si) -> 4 or (%di) -> 5 */
5517 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5518 }
5519 i.rm.mode = mode_from_disp_size (i.types[op]);
5520 }
5521 else /* i.base_reg and 32/64 bit mode */
5522 {
5523 if (flag_code == CODE_64BIT
40fb9820
L		 5524 && operand_type_check (i.types[op], disp))
5525 {
5526 i386_operand_type temp;
0dfbf9d7 5527 operand_type_set (&temp, 0);
40fb9820
L		 5528 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5529 i.types[op] = temp;
5530 if (i.prefix[ADDR_PREFIX] == 0)
5531 i.types[op].bitfield.disp32s = 1;
5532 else
5533 i.types[op].bitfield.disp32 = 1;
5534 }
20f0a1fc 5535
29b0f896
AM		 5536 i.rm.regmem = i.base_reg->reg_num;
5537 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5538 i.rex |= REX_B;
29b0f896
AM		 5539 i.sib.base = i.base_reg->reg_num;
5540 /* x86-64 ignores REX prefix bit here to avoid decoder
5541 complications. */
5542 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5543 {
5544 default_seg = &ss;
5545 if (i.disp_operands == 0)
5546 {
5547 fake_zero_displacement = 1;
40fb9820 5548 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5549 }
5550 }
5551 else if (i.base_reg->reg_num == ESP_REG_NUM)
5552 {
5553 default_seg = &ss;
5554 }
5555 i.sib.scale = i.log2_scale_factor;
5556 if (i.index_reg == 0)
5557 {
5558 /* <disp>(%esp) becomes two byte modrm with no index
5559 register. We've already stored the code for esp
5560 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5561 Any base register besides %esp will not use the
5562 extra modrm byte. */
5563 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5564 }
5565 else
5566 {
db51cc60
L		 5567 if (i.index_reg->reg_num == RegEiz
5568 || i.index_reg->reg_num == RegRiz)
5569 i.sib.index = NO_INDEX_REGISTER;
5570 else
5571 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5572 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5573 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5574 i.rex |= REX_X;
29b0f896 5575 }
67a4f2b7
AO		 5576
5577 if (i.disp_operands
5578 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5579 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5580 i.rm.mode = 0;
5581 else
5582 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5583 }
252b5132 5584
29b0f896
AM		 5585 if (fake_zero_displacement)
5586 {
5587 /* Fakes a zero displacement assuming that i.types[op]
5588 holds the correct displacement size. */
5589 expressionS *exp;
5590
9c2799c2 5591 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5592 exp = &disp_expressions[i.disp_operands++];
5593 i.op[op].disps = exp;
5594 exp->X_op = O_constant;
5595 exp->X_add_number = 0;
5596 exp->X_add_symbol = (symbolS *) 0;
5597 exp->X_op_symbol = (symbolS *) 0;
5598 }
c0f3af97
L		 5599
5600 mem = op;
29b0f896 5601 }
c0f3af97
L		 5602 else
5603 mem = ~0;
252b5132 5604
8c43a48b 5605 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5606 {
5607 if (operand_type_check (i.types[0], imm))
5608 i.vex.register_specifier = NULL;
5609 else
5610 {
5611 /* VEX.vvvv encodes one of the sources when the first
5612 operand is not an immediate. */
1ef99a7b 5613 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5614 i.vex.register_specifier = i.op[0].regs;
5615 else
5616 i.vex.register_specifier = i.op[1].regs;
5617 }
5618
5619 /* Destination is a XMM register encoded in the ModRM.reg
5620 and VEX.R bit. */
5621 i.rm.reg = i.op[2].regs->reg_num;
5622 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5623 i.rex |= REX_R;
5624
5625 /* ModRM.rm and VEX.B encodes the other source. */
5626 if (!i.mem_operands)
5627 {
5628 i.rm.mode = 3;
5629
1ef99a7b 5630 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5631 i.rm.regmem = i.op[1].regs->reg_num;
5632 else
5633 i.rm.regmem = i.op[0].regs->reg_num;
5634
5635 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5636 i.rex |= REX_B;
5637 }
5638 }
2426c15f 5639 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5640 {
5641 i.vex.register_specifier = i.op[2].regs;
5642 if (!i.mem_operands)
5643 {
5644 i.rm.mode = 3;
5645 i.rm.regmem = i.op[1].regs->reg_num;
5646 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5647 i.rex |= REX_B;
5648 }
5649 }
29b0f896
AM		 5650 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5651 (if any) based on i.tm.extension_opcode. Again, we must be
5652 careful to make sure that segment/control/debug/test/MMX
5653 registers are coded into the i.rm.reg field. */
f88c9eb0 5654 else if (i.reg_operands)
29b0f896 5655 {
99018f42 5656 unsigned int op;
7ab9ffdd
L		 5657 unsigned int vex_reg = ~0;
5658
5659 for (op = 0; op < i.operands; op++)
5660 if (i.types[op].bitfield.reg8
5661 || i.types[op].bitfield.reg16
5662 || i.types[op].bitfield.reg32
5663 || i.types[op].bitfield.reg64
5664 || i.types[op].bitfield.regmmx
5665 || i.types[op].bitfield.regxmm
5666 || i.types[op].bitfield.regymm
5667 || i.types[op].bitfield.sreg2
5668 || i.types[op].bitfield.sreg3
5669 || i.types[op].bitfield.control
5670 || i.types[op].bitfield.debug
5671 || i.types[op].bitfield.test)
5672 break;
c0209578 5673
7ab9ffdd
L		 5674 if (vex_3_sources)
5675 op = dest;
2426c15f 5676 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5677 {
5678 /* For instructions with VexNDS, the register-only
5679 source operand is encoded in VEX prefix. */
5680 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5681
7ab9ffdd 5682 if (op > mem)
c0f3af97 5683 {
7ab9ffdd
L		 5684 vex_reg = op++;
5685 gas_assert (op < i.operands);
c0f3af97
L		 5686 }
5687 else
c0f3af97 5688 {
f12dc422
L		 5689 /* Check register-only source operand when two source
5690 operands are swapped. */
5691 if (!i.tm.operand_types[op].bitfield.baseindex
5692 && i.tm.operand_types[op + 1].bitfield.baseindex)
5693 {
5694 vex_reg = op;
5695 op += 2;
5696 gas_assert (mem == (vex_reg + 1)
5697 && op < i.operands);
5698 }
5699 else
5700 {
5701 vex_reg = op + 1;
5702 gas_assert (vex_reg < i.operands);
5703 }
c0f3af97 5704 }
7ab9ffdd 5705 }
2426c15f 5706 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5707 {
f12dc422 5708 /* For instructions with VexNDD, the register destination
7ab9ffdd 5709 is encoded in VEX prefix. */
f12dc422
L		 5710 if (i.mem_operands == 0)
5711 {
5712 /* There is no memory operand. */
5713 gas_assert ((op + 2) == i.operands);
5714 vex_reg = op + 1;
5715 }
5716 else
5717 {
5718 /* There are only 2 operands. */
5719 gas_assert (op < 2 && i.operands == 2);
5720 vex_reg = 1;
5721 }
7ab9ffdd
L		 5722 }
5723 else
5724 gas_assert (op < i.operands);
99018f42 5725
7ab9ffdd
L		 5726 if (vex_reg != (unsigned int) ~0)
5727 {
f12dc422 5728 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5729
f12dc422
L		 5730 if (type->bitfield.reg32 != 1
5731 && type->bitfield.reg64 != 1
5732 && !operand_type_equal (type, &regxmm)
5733 && !operand_type_equal (type, &regymm))
7ab9ffdd 5734 abort ();
f88c9eb0 5735
7ab9ffdd
L		 5736 i.vex.register_specifier = i.op[vex_reg].regs;
5737 }
5738
1b9f0c97
L		 5739 /* Don't set OP operand twice. */
5740 if (vex_reg != op)
7ab9ffdd 5741 {
1b9f0c97
L		 5742 /* If there is an extension opcode to put here, the
5743 register number must be put into the regmem field. */
5744 if (i.tm.extension_opcode != None)
5745 {
5746 i.rm.regmem = i.op[op].regs->reg_num;
5747 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5748 i.rex |= REX_B;
5749 }
5750 else
5751 {
5752 i.rm.reg = i.op[op].regs->reg_num;
5753 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5754 i.rex |= REX_R;
5755 }
7ab9ffdd 5756 }
252b5132 5757
29b0f896
AM		 5758 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5759 must set it to 3 to indicate this is a register operand
5760 in the regmem field. */
5761 if (!i.mem_operands)
5762 i.rm.mode = 3;
5763 }
252b5132 5764
29b0f896 5765 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5766 if (i.tm.extension_opcode != None)
29b0f896
AM		 5767 i.rm.reg = i.tm.extension_opcode;
5768 }
5769 return default_seg;
5770}
252b5132 5771
29b0f896 5772static void
e3bb37b5 5773output_branch (void)
29b0f896
AM		 5774{
5775 char *p;
f8a5c266 5776 int size;
29b0f896
AM		 5777 int code16;
5778 int prefix;
5779 relax_substateT subtype;
5780 symbolS *sym;
5781 offsetT off;
5782
f8a5c266
L		 5783 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5784 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5785
5786 prefix = 0;
5787 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5788 {
29b0f896
AM		 5789 prefix = 1;
5790 i.prefixes -= 1;
5791 code16 ^= CODE16;
252b5132 5792 }
29b0f896
AM		 5793 /* Pentium4 branch hints. */
5794 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5795 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5796 {
29b0f896
AM		 5797 prefix++;
5798 i.prefixes--;
5799 }
5800 if (i.prefix[REX_PREFIX] != 0)
5801 {
5802 prefix++;
5803 i.prefixes--;
2f66722d
AM		 5804 }
5805
29b0f896
AM		 5806 if (i.prefixes != 0 && !intel_syntax)
5807 as_warn (_("skipping prefixes on this instruction"));
5808
5809 /* It's always a symbol; End frag & setup for relax.
5810 Make sure there is enough room in this frag for the largest
5811 instruction we may generate in md_convert_frag. This is 2
5812 bytes for the opcode and room for the prefix and largest
5813 displacement. */
5814 frag_grow (prefix + 2 + 4);
5815 /* Prefix and 1 opcode byte go in fr_fix. */
5816 p = frag_more (prefix + 1);
5817 if (i.prefix[DATA_PREFIX] != 0)
5818 *p++ = DATA_PREFIX_OPCODE;
5819 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5820 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5821 *p++ = i.prefix[SEG_PREFIX];
5822 if (i.prefix[REX_PREFIX] != 0)
5823 *p++ = i.prefix[REX_PREFIX];
5824 *p = i.tm.base_opcode;
5825
5826 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5827 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5828 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5829 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5830 else
f8a5c266 5831 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5832 subtype |= code16;
3e73aa7c 5833
29b0f896
AM		 5834 sym = i.op[0].disps->X_add_symbol;
5835 off = i.op[0].disps->X_add_number;
3e73aa7c 5836
29b0f896
AM		 5837 if (i.op[0].disps->X_op != O_constant
5838 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5839 {
29b0f896
AM		 5840 /* Handle complex expressions. */
5841 sym = make_expr_symbol (i.op[0].disps);
5842 off = 0;
5843 }
3e73aa7c 5844
29b0f896
AM		 5845 /* 1 possible extra opcode + 4 byte displacement go in var part.
5846 Pass reloc in fr_var. */
5847 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5848}
3e73aa7c 5849
29b0f896 5850static void
e3bb37b5 5851output_jump (void)
29b0f896
AM		 5852{
5853 char *p;
5854 int size;
3e02c1cc 5855 fixS *fixP;
29b0f896 5856
40fb9820 5857 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5858 {
5859 /* This is a loop or jecxz type instruction. */
5860 size = 1;
5861 if (i.prefix[ADDR_PREFIX] != 0)
5862 {
5863 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5864 i.prefixes -= 1;
5865 }
5866 /* Pentium4 branch hints. */
5867 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5868 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5869 {
5870 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5871 i.prefixes--;
3e73aa7c
JH		 5872 }
5873 }
29b0f896
AM		 5874 else
5875 {
5876 int code16;
3e73aa7c 5877
29b0f896
AM		 5878 code16 = 0;
5879 if (flag_code == CODE_16BIT)
5880 code16 = CODE16;
3e73aa7c 5881
29b0f896
AM		 5882 if (i.prefix[DATA_PREFIX] != 0)
5883 {
5884 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5885 i.prefixes -= 1;
5886 code16 ^= CODE16;
5887 }
252b5132 5888
29b0f896
AM		 5889 size = 4;
5890 if (code16)
5891 size = 2;
5892 }
9fcc94b6 5893
29b0f896
AM		 5894 if (i.prefix[REX_PREFIX] != 0)
5895 {
5896 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5897 i.prefixes -= 1;
5898 }
252b5132 5899
29b0f896
AM		 5900 if (i.prefixes != 0 && !intel_syntax)
5901 as_warn (_("skipping prefixes on this instruction"));
e0890092 5902
29b0f896
AM		 5903 p = frag_more (1 + size);
5904 *p++ = i.tm.base_opcode;
e0890092 5905
3e02c1cc
AM		 5906 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5907 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5908
5909 /* All jumps handled here are signed, but don't use a signed limit
5910 check for 32 and 16 bit jumps as we want to allow wrap around at
5911 4G and 64k respectively. */
5912 if (size == 1)
5913 fixP->fx_signed = 1;
29b0f896 5914}
e0890092 5915
29b0f896 5916static void
e3bb37b5 5917output_interseg_jump (void)
29b0f896
AM		 5918{
5919 char *p;
5920 int size;
5921 int prefix;
5922 int code16;
252b5132 5923
29b0f896
AM		 5924 code16 = 0;
5925 if (flag_code == CODE_16BIT)
5926 code16 = CODE16;
a217f122 5927
29b0f896
AM		 5928 prefix = 0;
5929 if (i.prefix[DATA_PREFIX] != 0)
5930 {
5931 prefix = 1;
5932 i.prefixes -= 1;
5933 code16 ^= CODE16;
5934 }
5935 if (i.prefix[REX_PREFIX] != 0)
5936 {
5937 prefix++;
5938 i.prefixes -= 1;
5939 }
252b5132 5940
29b0f896
AM		 5941 size = 4;
5942 if (code16)
5943 size = 2;
252b5132 5944
29b0f896
AM		 5945 if (i.prefixes != 0 && !intel_syntax)
5946 as_warn (_("skipping prefixes on this instruction"));
252b5132 5947
29b0f896
AM		 5948 /* 1 opcode; 2 segment; offset */
5949 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5950
29b0f896
AM		 5951 if (i.prefix[DATA_PREFIX] != 0)
5952 *p++ = DATA_PREFIX_OPCODE;
252b5132 5953
29b0f896
AM		 5954 if (i.prefix[REX_PREFIX] != 0)
5955 *p++ = i.prefix[REX_PREFIX];
252b5132 5956
29b0f896
AM		 5957 *p++ = i.tm.base_opcode;
5958 if (i.op[1].imms->X_op == O_constant)
5959 {
5960 offsetT n = i.op[1].imms->X_add_number;
252b5132 5961
29b0f896
AM		 5962 if (size == 2
5963 && !fits_in_unsigned_word (n)
5964 && !fits_in_signed_word (n))
5965 {
5966 as_bad (_("16-bit jump out of range"));
5967 return;
5968 }
5969 md_number_to_chars (p, n, size);
5970 }
5971 else
5972 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5973 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5974 if (i.op[0].imms->X_op != O_constant)
5975 as_bad (_("can't handle non absolute segment in `%s'"),
5976 i.tm.name);
5977 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5978}
a217f122 5979
29b0f896 5980static void
e3bb37b5 5981output_insn (void)
29b0f896 5982{
2bbd9c25
JJ		 5983 fragS *insn_start_frag;
5984 offsetT insn_start_off;
5985
29b0f896
AM		 5986 /* Tie dwarf2 debug info to the address at the start of the insn.
5987 We can't do this after the insn has been output as the current
5988 frag may have been closed off. eg. by frag_var. */
5989 dwarf2_emit_insn (0);
5990
2bbd9c25
JJ		 5991 insn_start_frag = frag_now;
5992 insn_start_off = frag_now_fix ();
5993
29b0f896 5994 /* Output jumps. */
40fb9820 5995 if (i.tm.opcode_modifier.jump)
29b0f896 5996 output_branch ();
40fb9820
L		 5997 else if (i.tm.opcode_modifier.jumpbyte
5998 || i.tm.opcode_modifier.jumpdword)
29b0f896 5999 output_jump ();
40fb9820 6000 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6001 output_interseg_jump ();
6002 else
6003 {
6004 /* Output normal instructions here. */
6005 char *p;
6006 unsigned char *q;
47465058 6007 unsigned int j;
331d2d0d 6008 unsigned int prefix;
4dffcebc 6009
c0f3af97
L		 6010 /* Since the VEX prefix contains the implicit prefix, we don't
6011 need the explicit prefix. */
6012 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6013 {
c0f3af97 6014 switch (i.tm.opcode_length)
bc4bd9ab 6015 {
c0f3af97
L		 6016 case 3:
6017 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6018 {
c0f3af97
L		 6019 prefix = (i.tm.base_opcode >> 24) & 0xff;
6020 goto check_prefix;
6021 }
6022 break;
6023 case 2:
6024 if ((i.tm.base_opcode & 0xff0000) != 0)
6025 {
6026 prefix = (i.tm.base_opcode >> 16) & 0xff;
6027 if (i.tm.cpu_flags.bitfield.cpupadlock)
6028 {
4dffcebc 6029check_prefix:
c0f3af97 6030 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6031 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6032 != REPE_PREFIX_OPCODE))
6033 add_prefix (prefix);
6034 }
6035 else
4dffcebc
L		 6036 add_prefix (prefix);
6037 }
c0f3af97
L		 6038 break;
6039 case 1:
6040 break;
6041 default:
6042 abort ();
bc4bd9ab 6043 }
c0f3af97
L		 6044
6045 /* The prefix bytes. */
6046 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6047 if (*q)
6048 FRAG_APPEND_1_CHAR (*q);
0f10071e 6049 }
252b5132 6050
c0f3af97
L		 6051 if (i.tm.opcode_modifier.vex)
6052 {
6053 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6054 if (*q)
6055 switch (j)
6056 {
6057 case REX_PREFIX:
6058 /* REX byte is encoded in VEX prefix. */
6059 break;
6060 case SEG_PREFIX:
6061 case ADDR_PREFIX:
6062 FRAG_APPEND_1_CHAR (*q);
6063 break;
6064 default:
6065 /* There should be no other prefixes for instructions
6066 with VEX prefix. */
6067 abort ();
6068 }
6069
6070 /* Now the VEX prefix. */
6071 p = frag_more (i.vex.length);
6072 for (j = 0; j < i.vex.length; j++)
6073 p[j] = i.vex.bytes[j];
6074 }
252b5132 6075
29b0f896 6076 /* Now the opcode; be careful about word order here! */
4dffcebc 6077 if (i.tm.opcode_length == 1)
29b0f896
AM		 6078 {
6079 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6080 }
6081 else
6082 {
4dffcebc 6083 switch (i.tm.opcode_length)
331d2d0d 6084 {
4dffcebc 6085 case 3:
331d2d0d
L		 6086 p = frag_more (3);
6087 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6088 break;
6089 case 2:
6090 p = frag_more (2);
6091 break;
6092 default:
6093 abort ();
6094 break;
331d2d0d 6095 }
0f10071e 6096
29b0f896
AM		 6097 /* Put out high byte first: can't use md_number_to_chars! */
6098 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6099 *p = i.tm.base_opcode & 0xff;
6100 }
3e73aa7c 6101
29b0f896 6102 /* Now the modrm byte and sib byte (if present). */
40fb9820 6103 if (i.tm.opcode_modifier.modrm)
29b0f896 6104 {
4a3523fa
L		 6105 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6106 | i.rm.reg << 3
6107 | i.rm.mode << 6));
29b0f896
AM		 6108 /* If i.rm.regmem == ESP (4)
6109 && i.rm.mode != (Register mode)
6110 && not 16 bit
6111 ==> need second modrm byte. */
6112 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6113 && i.rm.mode != 3
40fb9820 6114 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6115 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6116 | i.sib.index << 3
6117 | i.sib.scale << 6));
29b0f896 6118 }
3e73aa7c 6119
29b0f896 6120 if (i.disp_operands)
2bbd9c25 6121 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6122
29b0f896 6123 if (i.imm_operands)
2bbd9c25 6124 output_imm (insn_start_frag, insn_start_off);
29b0f896 6125 }
252b5132 6126
29b0f896
AM		 6127#ifdef DEBUG386
6128 if (flag_debug)
6129 {
7b81dfbb 6130 pi ("" /*line*/, &i);
29b0f896
AM		 6131 }
6132#endif /* DEBUG386 */
6133}
252b5132 6134
e205caa7
L		 6135/* Return the size of the displacement operand N. */
6136
6137static int
6138disp_size (unsigned int n)
6139{
6140 int size = 4;
40fb9820
L		 6141 if (i.types[n].bitfield.disp64)
6142 size = 8;
6143 else if (i.types[n].bitfield.disp8)
6144 size = 1;
6145 else if (i.types[n].bitfield.disp16)
6146 size = 2;
e205caa7
L		 6147 return size;
6148}
6149
6150/* Return the size of the immediate operand N. */
6151
6152static int
6153imm_size (unsigned int n)
6154{
6155 int size = 4;
40fb9820
L		 6156 if (i.types[n].bitfield.imm64)
6157 size = 8;
6158 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6159 size = 1;
6160 else if (i.types[n].bitfield.imm16)
6161 size = 2;
e205caa7
L		 6162 return size;
6163}
6164
29b0f896 6165static void
64e74474 6166output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6167{
6168 char *p;
6169 unsigned int n;
252b5132 6170
29b0f896
AM		 6171 for (n = 0; n < i.operands; n++)
6172 {
40fb9820 6173 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6174 {
6175 if (i.op[n].disps->X_op == O_constant)
6176 {
e205caa7 6177 int size = disp_size (n);
29b0f896 6178 offsetT val;
252b5132 6179
29b0f896
AM		 6180 val = offset_in_range (i.op[n].disps->X_add_number,
6181 size);
6182 p = frag_more (size);
6183 md_number_to_chars (p, val, size);
6184 }
6185 else
6186 {
f86103b7 6187 enum bfd_reloc_code_real reloc_type;
e205caa7 6188 int size = disp_size (n);
40fb9820 6189 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6190 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6191
e205caa7 6192 /* We can't have 8 bit displacement here. */
9c2799c2 6193 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6194
29b0f896
AM		 6195 /* The PC relative address is computed relative
6196 to the instruction boundary, so in case immediate
6197 fields follows, we need to adjust the value. */
6198 if (pcrel && i.imm_operands)
6199 {
29b0f896 6200 unsigned int n1;
e205caa7 6201 int sz = 0;
252b5132 6202
29b0f896 6203 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6204 if (operand_type_check (i.types[n1], imm))
252b5132 6205 {
e205caa7
L		 6206 /* Only one immediate is allowed for PC
6207 relative address. */
9c2799c2 6208 gas_assert (sz == 0);
e205caa7
L		 6209 sz = imm_size (n1);
6210 i.op[n].disps->X_add_number -= sz;
252b5132 6211 }
29b0f896 6212 /* We should find the immediate. */
9c2799c2 6213 gas_assert (sz != 0);
29b0f896 6214 }
520dc8e8 6215
29b0f896 6216 p = frag_more (size);
2bbd9c25 6217 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6218 if (GOT_symbol
2bbd9c25 6219 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6220 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6221 || reloc_type == BFD_RELOC_X86_64_32S
6222 || (reloc_type == BFD_RELOC_64
6223 && object_64bit))
d6ab8113
JB		 6224 && (i.op[n].disps->X_op == O_symbol
6225 || (i.op[n].disps->X_op == O_add
6226 && ((symbol_get_value_expression
6227 (i.op[n].disps->X_op_symbol)->X_op)
6228 == O_subtract))))
6229 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6230 {
6231 offsetT add;
6232
6233 if (insn_start_frag == frag_now)
6234 add = (p - frag_now->fr_literal) - insn_start_off;
6235 else
6236 {
6237 fragS *fr;
6238
6239 add = insn_start_frag->fr_fix - insn_start_off;
6240 for (fr = insn_start_frag->fr_next;
6241 fr && fr != frag_now; fr = fr->fr_next)
6242 add += fr->fr_fix;
6243 add += p - frag_now->fr_literal;
6244 }
6245
4fa24527 6246 if (!object_64bit)
7b81dfbb
AJ		 6247 {
6248 reloc_type = BFD_RELOC_386_GOTPC;
6249 i.op[n].imms->X_add_number += add;
6250 }
6251 else if (reloc_type == BFD_RELOC_64)
6252 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6253 else
7b81dfbb
AJ		 6254 /* Don't do the adjustment for x86-64, as there
6255 the pcrel addressing is relative to the _next_
6256 insn, and that is taken care of in other code. */
d6ab8113 6257 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6258 }
062cd5e7 6259 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6260 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6261 }
6262 }
6263 }
6264}
252b5132 6265
29b0f896 6266static void
64e74474 6267output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6268{
6269 char *p;
6270 unsigned int n;
252b5132 6271
29b0f896
AM		 6272 for (n = 0; n < i.operands; n++)
6273 {
40fb9820 6274 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6275 {
6276 if (i.op[n].imms->X_op == O_constant)
6277 {
e205caa7 6278 int size = imm_size (n);
29b0f896 6279 offsetT val;
b4cac588 6280
29b0f896
AM		 6281 val = offset_in_range (i.op[n].imms->X_add_number,
6282 size);
6283 p = frag_more (size);
6284 md_number_to_chars (p, val, size);
6285 }
6286 else
6287 {
6288 /* Not absolute_section.
6289 Need a 32-bit fixup (don't support 8bit
6290 non-absolute imms). Try to support other
6291 sizes ... */
f86103b7 6292 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6293 int size = imm_size (n);
6294 int sign;
29b0f896 6295
40fb9820 6296 if (i.types[n].bitfield.imm32s
a7d61044 6297 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6298 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6299 sign = 1;
e205caa7
L		 6300 else
6301 sign = 0;
520dc8e8 6302
29b0f896
AM		 6303 p = frag_more (size);
6304 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6305
2bbd9c25
JJ		 6306 /* This is tough to explain. We end up with this one if we
6307 * have operands that look like
6308 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6309 * obtain the absolute address of the GOT, and it is strongly
6310 * preferable from a performance point of view to avoid using
6311 * a runtime relocation for this. The actual sequence of
6312 * instructions often look something like:
6313 *
6314 * call .L66
6315 * .L66:
6316 * popl %ebx
6317 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6318 *
6319 * The call and pop essentially return the absolute address
6320 * of the label .L66 and store it in %ebx. The linker itself
6321 * will ultimately change the first operand of the addl so
6322 * that %ebx points to the GOT, but to keep things simple, the
6323 * .o file must have this operand set so that it generates not
6324 * the absolute address of .L66, but the absolute address of
6325 * itself. This allows the linker itself simply treat a GOTPC
6326 * relocation as asking for a pcrel offset to the GOT to be
6327 * added in, and the addend of the relocation is stored in the
6328 * operand field for the instruction itself.
6329 *
6330 * Our job here is to fix the operand so that it would add
6331 * the correct offset so that %ebx would point to itself. The
6332 * thing that is tricky is that .-.L66 will point to the
6333 * beginning of the instruction, so we need to further modify
6334 * the operand so that it will point to itself. There are
6335 * other cases where you have something like:
6336 *
6337 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6338 *
6339 * and here no correction would be required. Internally in
6340 * the assembler we treat operands of this form as not being
6341 * pcrel since the '.' is explicitly mentioned, and I wonder
6342 * whether it would simplify matters to do it this way. Who
6343 * knows. In earlier versions of the PIC patches, the
6344 * pcrel_adjust field was used to store the correction, but
6345 * since the expression is not pcrel, I felt it would be
6346 * confusing to do it this way. */
6347
d6ab8113 6348 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6349 || reloc_type == BFD_RELOC_X86_64_32S
6350 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6351 && GOT_symbol
6352 && GOT_symbol == i.op[n].imms->X_add_symbol
6353 && (i.op[n].imms->X_op == O_symbol
6354 || (i.op[n].imms->X_op == O_add
6355 && ((symbol_get_value_expression
6356 (i.op[n].imms->X_op_symbol)->X_op)
6357 == O_subtract))))
6358 {
2bbd9c25
JJ		 6359 offsetT add;
6360
6361 if (insn_start_frag == frag_now)
6362 add = (p - frag_now->fr_literal) - insn_start_off;
6363 else
6364 {
6365 fragS *fr;
6366
6367 add = insn_start_frag->fr_fix - insn_start_off;
6368 for (fr = insn_start_frag->fr_next;
6369 fr && fr != frag_now; fr = fr->fr_next)
6370 add += fr->fr_fix;
6371 add += p - frag_now->fr_literal;
6372 }
6373
4fa24527 6374 if (!object_64bit)
d6ab8113 6375 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6376 else if (size == 4)
d6ab8113 6377 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6378 else if (size == 8)
6379 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6380 i.op[n].imms->X_add_number += add;
29b0f896 6381 }
29b0f896
AM		 6382 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6383 i.op[n].imms, 0, reloc_type);
6384 }
6385 }
6386 }
252b5132
RH		 6387}
6388\f
d182319b
JB		 6389/* x86_cons_fix_new is called via the expression parsing code when a
6390 reloc is needed. We use this hook to get the correct .got reloc. */
6391static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6392static int cons_sign = -1;
6393
6394void
e3bb37b5 6395x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6396 expressionS *exp)
d182319b
JB		 6397{
6398 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6399
6400 got_reloc = NO_RELOC;
6401
6402#ifdef TE_PE
6403 if (exp->X_op == O_secrel)
6404 {
6405 exp->X_op = O_symbol;
6406 r = BFD_RELOC_32_SECREL;
6407 }
6408#endif
6409
6410 fix_new_exp (frag, off, len, exp, 0, r);
6411}
6412
718ddfc0
JB		 6413#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6414# define lex_got(reloc, adjust, types) NULL
6415#else
f3c180ae
AM		 6416/* Parse operands of the form
6417 <symbol>@GOTOFF+<nnn>
6418 and similar .plt or .got references.
6419
6420 If we find one, set up the correct relocation in RELOC and copy the
6421 input string, minus the `@GOTOFF' into a malloc'd buffer for
6422 parsing by the calling routine. Return this buffer, and if ADJUST
6423 is non-null set it to the length of the string we removed from the
6424 input line. Otherwise return NULL. */
6425static char *
91d6fa6a 6426lex_got (enum bfd_reloc_code_real *rel,
64e74474 6427 int *adjust,
40fb9820 6428 i386_operand_type *types)
f3c180ae 6429{
7b81dfbb
AJ		 6430 /* Some of the relocations depend on the size of what field is to
6431 be relocated. But in our callers i386_immediate and i386_displacement
6432 we don't yet know the operand size (this will be set by insn
6433 matching). Hence we record the word32 relocation here,
6434 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6435 static const struct {
6436 const char *str;
cff8d58a 6437 int len;
4fa24527 6438 const enum bfd_reloc_code_real rel[2];
40fb9820 6439 const i386_operand_type types64;
f3c180ae 6440 } gotrel[] = {
cff8d58a
L		 6441 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6442 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6443 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6444 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6445 BFD_RELOC_X86_64_PLT32 },
40fb9820 6446 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6447 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6448 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6449 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6450 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6451 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6452 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6453 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6454 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6455 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6456 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6457 BFD_RELOC_X86_64_TLSGD },
40fb9820 6458 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6459 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6460 _dummy_first_bfd_reloc_code_real },
40fb9820 6461 OPERAND_TYPE_NONE },
cff8d58a
L		 6462 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6463 BFD_RELOC_X86_64_TLSLD },
40fb9820 6464 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6465 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6466 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6467 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6468 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6469 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6470 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6471 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6472 _dummy_first_bfd_reloc_code_real },
40fb9820 6473 OPERAND_TYPE_NONE },
cff8d58a
L		 6474 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6475 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6476 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6477 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6478 _dummy_first_bfd_reloc_code_real },
40fb9820 6479 OPERAND_TYPE_NONE },
cff8d58a
L		 6480 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6481 _dummy_first_bfd_reloc_code_real },
40fb9820 6482 OPERAND_TYPE_NONE },
cff8d58a
L		 6483 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6484 BFD_RELOC_X86_64_GOT32 },
40fb9820 6485 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6486 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6487 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6488 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6489 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6490 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6491 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6492 };
6493 char *cp;
6494 unsigned int j;
6495
718ddfc0
JB		 6496 if (!IS_ELF)
6497 return NULL;
6498
f3c180ae 6499 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6500 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6501 return NULL;
6502
47465058 6503 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6504 {
cff8d58a 6505 int len = gotrel[j].len;
28f81592 6506 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6507 {
4fa24527 6508 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6509 {
28f81592
AM		 6510 int first, second;
6511 char *tmpbuf, *past_reloc;
f3c180ae 6512
91d6fa6a 6513 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6514 if (adjust)
6515 *adjust = len;
f3c180ae 6516
3956db08
JB		 6517 if (types)
6518 {
6519 if (flag_code != CODE_64BIT)
40fb9820
L		 6520 {
6521 types->bitfield.imm32 = 1;
6522 types->bitfield.disp32 = 1;
6523 }
3956db08
JB		 6524 else
6525 *types = gotrel[j].types64;
6526 }
6527
f3c180ae
AM		 6528 if (GOT_symbol == NULL)
6529 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6530
28f81592 6531 /* The length of the first part of our input line. */
f3c180ae 6532 first = cp - input_line_pointer;
28f81592
AM		 6533
6534 /* The second part goes from after the reloc token until
67c11a9b 6535 (and including) an end_of_line char or comma. */
28f81592 6536 past_reloc = cp + 1 + len;
67c11a9b
AM		 6537 cp = past_reloc;
6538 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6539 ++cp;
6540 second = cp + 1 - past_reloc;
28f81592
AM		 6541
6542 /* Allocate and copy string. The trailing NUL shouldn't
6543 be necessary, but be safe. */
1e9cc1c2 6544 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6545 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6546 if (second != 0 && *past_reloc != ' ')
6547 /* Replace the relocation token with ' ', so that
6548 errors like foo@GOTOFF1 will be detected. */
6549 tmpbuf[first++] = ' ';
6550 memcpy (tmpbuf + first, past_reloc, second);
6551 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6552 return tmpbuf;
6553 }
6554
4fa24527
JB		 6555 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6556 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6557 return NULL;
6558 }
6559 }
6560
6561 /* Might be a symbol version string. Don't as_bad here. */
6562 return NULL;
6563}
4e4f7c87 6564#endif
f3c180ae 6565
f3c180ae 6566void
e3bb37b5 6567x86_cons (expressionS *exp, int size)
f3c180ae 6568{
ee86248c
JB		 6569 intel_syntax = -intel_syntax;
6570
3c7b9c2c 6571 exp->X_md = 0;
4fa24527 6572 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6573 {
6574 /* Handle @GOTOFF and the like in an expression. */
6575 char *save;
6576 char *gotfree_input_line;
4a57f2cf 6577 int adjust = 0;
f3c180ae
AM		 6578
6579 save = input_line_pointer;
3956db08 6580 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6581 if (gotfree_input_line)
6582 input_line_pointer = gotfree_input_line;
6583
6584 expression (exp);
6585
6586 if (gotfree_input_line)
6587 {
6588 /* expression () has merrily parsed up to the end of line,
6589 or a comma - in the wrong buffer. Transfer how far
6590 input_line_pointer has moved to the right buffer. */
6591 input_line_pointer = (save
6592 + (input_line_pointer - gotfree_input_line)
6593 + adjust);
6594 free (gotfree_input_line);
3992d3b7
AM		 6595 if (exp->X_op == O_constant
6596 || exp->X_op == O_absent
6597 || exp->X_op == O_illegal
0398aac5 6598 || exp->X_op == O_register
3992d3b7
AM		 6599 || exp->X_op == O_big)
6600 {
6601 char c = *input_line_pointer;
6602 *input_line_pointer = 0;
6603 as_bad (_("missing or invalid expression `%s'"), save);
6604 *input_line_pointer = c;
6605 }
f3c180ae
AM		 6606 }
6607 }
6608 else
6609 expression (exp);
ee86248c
JB		 6610
6611 intel_syntax = -intel_syntax;
6612
6613 if (intel_syntax)
6614 i386_intel_simplify (exp);
f3c180ae 6615}
f3c180ae 6616
9f32dd5b
L		 6617static void
6618signed_cons (int size)
6482c264 6619{
d182319b
JB		 6620 if (flag_code == CODE_64BIT)
6621 cons_sign = 1;
6622 cons (size);
6623 cons_sign = -1;
6482c264
NC		 6624}
6625
d182319b 6626#ifdef TE_PE
6482c264
NC		 6627static void
6628pe_directive_secrel (dummy)
6629 int dummy ATTRIBUTE_UNUSED;
6630{
6631 expressionS exp;
6632
6633 do
6634 {
6635 expression (&exp);
6636 if (exp.X_op == O_symbol)
6637 exp.X_op = O_secrel;
6638
6639 emit_expr (&exp, 4);
6640 }
6641 while (*input_line_pointer++ == ',');
6642
6643 input_line_pointer--;
6644 demand_empty_rest_of_line ();
6645}
6482c264
NC		 6646#endif
6647
252b5132 6648static int
70e41ade 6649i386_immediate (char *imm_start)
252b5132
RH		 6650{
6651 char *save_input_line_pointer;
f3c180ae 6652 char *gotfree_input_line;
252b5132 6653 segT exp_seg = 0;
47926f60 6654 expressionS *exp;
40fb9820
L		 6655 i386_operand_type types;
6656
0dfbf9d7 6657 operand_type_set (&types, ~0);
252b5132
RH		 6658
6659 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6660 {
31b2323c
L		 6661 as_bad (_("at most %d immediate operands are allowed"),
6662 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6663 return 0;
6664 }
6665
6666 exp = &im_expressions[i.imm_operands++];
520dc8e8 6667 i.op[this_operand].imms = exp;
252b5132
RH		 6668
6669 if (is_space_char (*imm_start))
6670 ++imm_start;
6671
6672 save_input_line_pointer = input_line_pointer;
6673 input_line_pointer = imm_start;
6674
3956db08 6675 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6676 if (gotfree_input_line)
6677 input_line_pointer = gotfree_input_line;
252b5132
RH		 6678
6679 exp_seg = expression (exp);
6680
83183c0c 6681 SKIP_WHITESPACE ();
252b5132 6682 if (*input_line_pointer)
f3c180ae 6683 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6684
6685 input_line_pointer = save_input_line_pointer;
f3c180ae 6686 if (gotfree_input_line)
ee86248c
JB		 6687 {
6688 free (gotfree_input_line);
6689
6690 if (exp->X_op == O_constant || exp->X_op == O_register)
6691 exp->X_op = O_illegal;
6692 }
6693
6694 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6695}
252b5132 6696
ee86248c
JB		 6697static int
6698i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6699 i386_operand_type types, const char *imm_start)
6700{
6701 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6702 {
313c53d1
L		 6703 if (imm_start)
6704 as_bad (_("missing or invalid immediate expression `%s'"),
6705 imm_start);
3992d3b7 6706 return 0;
252b5132 6707 }
3e73aa7c 6708 else if (exp->X_op == O_constant)
252b5132 6709 {
47926f60 6710 /* Size it properly later. */
40fb9820 6711 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6712 /* If not 64bit, sign extend val. */
6713 if (flag_code != CODE_64BIT
4eed87de
AM		 6714 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6715 exp->X_add_number
6716 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6717 }
4c63da97 6718#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6719 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6720 && exp_seg != absolute_section
47926f60 6721 && exp_seg != text_section
24eab124
AM		 6722 && exp_seg != data_section
6723 && exp_seg != bss_section
6724 && exp_seg != undefined_section
f86103b7 6725 && !bfd_is_com_section (exp_seg))
252b5132 6726 {
d0b47220 6727 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6728 return 0;
6729 }
6730#endif
bb8f5920
L		 6731 else if (!intel_syntax && exp->X_op == O_register)
6732 {
313c53d1
L		 6733 if (imm_start)
6734 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6735 return 0;
6736 }
252b5132
RH		 6737 else
6738 {
6739 /* This is an address. The size of the address will be
24eab124 6740 determined later, depending on destination register,
3e73aa7c 6741 suffix, or the default for the section. */
40fb9820
L		 6742 i.types[this_operand].bitfield.imm8 = 1;
6743 i.types[this_operand].bitfield.imm16 = 1;
6744 i.types[this_operand].bitfield.imm32 = 1;
6745 i.types[this_operand].bitfield.imm32s = 1;
6746 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6747 i.types[this_operand] = operand_type_and (i.types[this_operand],
6748 types);
252b5132
RH		 6749 }
6750
6751 return 1;
6752}
6753
551c1ca1 6754static char *
e3bb37b5 6755i386_scale (char *scale)
252b5132 6756{
551c1ca1
AM		 6757 offsetT val;
6758 char *save = input_line_pointer;
252b5132 6759
551c1ca1
AM		 6760 input_line_pointer = scale;
6761 val = get_absolute_expression ();
6762
6763 switch (val)
252b5132 6764 {
551c1ca1 6765 case 1:
252b5132
RH		 6766 i.log2_scale_factor = 0;
6767 break;
551c1ca1 6768 case 2:
252b5132
RH		 6769 i.log2_scale_factor = 1;
6770 break;
551c1ca1 6771 case 4:
252b5132
RH		 6772 i.log2_scale_factor = 2;
6773 break;
551c1ca1 6774 case 8:
252b5132
RH		 6775 i.log2_scale_factor = 3;
6776 break;
6777 default:
a724f0f4
JB		 6778 {
6779 char sep = *input_line_pointer;
6780
6781 *input_line_pointer = '\0';
6782 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6783 scale);
6784 *input_line_pointer = sep;
6785 input_line_pointer = save;
6786 return NULL;
6787 }
252b5132 6788 }
29b0f896 6789 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6790 {
6791 as_warn (_("scale factor of %d without an index register"),
24eab124 6792 1 << i.log2_scale_factor);
252b5132 6793 i.log2_scale_factor = 0;
252b5132 6794 }
551c1ca1
AM		 6795 scale = input_line_pointer;
6796 input_line_pointer = save;
6797 return scale;
252b5132
RH		 6798}
6799
252b5132 6800static int
e3bb37b5 6801i386_displacement (char *disp_start, char *disp_end)
252b5132 6802{
29b0f896 6803 expressionS *exp;
252b5132
RH		 6804 segT exp_seg = 0;
6805 char *save_input_line_pointer;
f3c180ae 6806 char *gotfree_input_line;
40fb9820
L		 6807 int override;
6808 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6809 int ret;
252b5132 6810
31b2323c
L		 6811 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6812 {
6813 as_bad (_("at most %d displacement operands are allowed"),
6814 MAX_MEMORY_OPERANDS);
6815 return 0;
6816 }
6817
0dfbf9d7 6818 operand_type_set (&bigdisp, 0);
40fb9820
L		 6819 if ((i.types[this_operand].bitfield.jumpabsolute)
6820 || (!current_templates->start->opcode_modifier.jump
6821 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6822 {
40fb9820 6823 bigdisp.bitfield.disp32 = 1;
e05278af 6824 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6825 if (flag_code == CODE_64BIT)
6826 {
6827 if (!override)
6828 {
6829 bigdisp.bitfield.disp32s = 1;
6830 bigdisp.bitfield.disp64 = 1;
6831 }
6832 }
6833 else if ((flag_code == CODE_16BIT) ^ override)
6834 {
6835 bigdisp.bitfield.disp32 = 0;
6836 bigdisp.bitfield.disp16 = 1;
6837 }
e05278af
JB		 6838 }
6839 else
6840 {
6841 /* For PC-relative branches, the width of the displacement
6842 is dependent upon data size, not address size. */
e05278af 6843 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6844 if (flag_code == CODE_64BIT)
6845 {
6846 if (override || i.suffix == WORD_MNEM_SUFFIX)
6847 bigdisp.bitfield.disp16 = 1;
6848 else
6849 {
6850 bigdisp.bitfield.disp32 = 1;
6851 bigdisp.bitfield.disp32s = 1;
6852 }
6853 }
6854 else
e05278af
JB		 6855 {
6856 if (!override)
6857 override = (i.suffix == (flag_code != CODE_16BIT
6858 ? WORD_MNEM_SUFFIX
6859 : LONG_MNEM_SUFFIX));
40fb9820
L		 6860 bigdisp.bitfield.disp32 = 1;
6861 if ((flag_code == CODE_16BIT) ^ override)
6862 {
6863 bigdisp.bitfield.disp32 = 0;
6864 bigdisp.bitfield.disp16 = 1;
6865 }
e05278af 6866 }
e05278af 6867 }
c6fb90c8
L		 6868 i.types[this_operand] = operand_type_or (i.types[this_operand],
6869 bigdisp);
252b5132
RH		 6870
6871 exp = &disp_expressions[i.disp_operands];
520dc8e8 6872 i.op[this_operand].disps = exp;
252b5132
RH		 6873 i.disp_operands++;
6874 save_input_line_pointer = input_line_pointer;
6875 input_line_pointer = disp_start;
6876 END_STRING_AND_SAVE (disp_end);
6877
6878#ifndef GCC_ASM_O_HACK
6879#define GCC_ASM_O_HACK 0
6880#endif
6881#if GCC_ASM_O_HACK
6882 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6883 if (i.types[this_operand].bitfield.baseIndex
24eab124 6884 && displacement_string_end[-1] == '+')
252b5132
RH		 6885 {
6886 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6887 constraint within gcc asm statements.
6888 For instance:
6889
6890 #define _set_tssldt_desc(n,addr,limit,type) \
6891 __asm__ __volatile__ ( \
6892 "movw %w2,%0\n\t" \
6893 "movw %w1,2+%0\n\t" \
6894 "rorl $16,%1\n\t" \
6895 "movb %b1,4+%0\n\t" \
6896 "movb %4,5+%0\n\t" \
6897 "movb $0,6+%0\n\t" \
6898 "movb %h1,7+%0\n\t" \
6899 "rorl $16,%1" \
6900 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6901
6902 This works great except that the output assembler ends
6903 up looking a bit weird if it turns out that there is
6904 no offset. You end up producing code that looks like:
6905
6906 #APP
6907 movw $235,(%eax)
6908 movw %dx,2+(%eax)
6909 rorl $16,%edx
6910 movb %dl,4+(%eax)
6911 movb $137,5+(%eax)
6912 movb $0,6+(%eax)
6913 movb %dh,7+(%eax)
6914 rorl $16,%edx
6915 #NO_APP
6916
47926f60 6917 So here we provide the missing zero. */
24eab124
AM		 6918
6919 *displacement_string_end = '0';
252b5132
RH		 6920 }
6921#endif
3956db08 6922 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6923 if (gotfree_input_line)
6924 input_line_pointer = gotfree_input_line;
252b5132 6925
24eab124 6926 exp_seg = expression (exp);
252b5132 6927
636c26b0
AM		 6928 SKIP_WHITESPACE ();
6929 if (*input_line_pointer)
6930 as_bad (_("junk `%s' after expression"), input_line_pointer);
6931#if GCC_ASM_O_HACK
6932 RESTORE_END_STRING (disp_end + 1);
6933#endif
636c26b0 6934 input_line_pointer = save_input_line_pointer;
636c26b0 6935 if (gotfree_input_line)
ee86248c
JB		 6936 {
6937 free (gotfree_input_line);
6938
6939 if (exp->X_op == O_constant || exp->X_op == O_register)
6940 exp->X_op = O_illegal;
6941 }
6942
6943 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6944
6945 RESTORE_END_STRING (disp_end);
6946
6947 return ret;
6948}
6949
6950static int
6951i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6952 i386_operand_type types, const char *disp_start)
6953{
6954 i386_operand_type bigdisp;
6955 int ret = 1;
636c26b0 6956
24eab124
AM		 6957 /* We do this to make sure that the section symbol is in
6958 the symbol table. We will ultimately change the relocation
47926f60 6959 to be relative to the beginning of the section. */
1ae12ab7 6960 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6961 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6962 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6963 {
636c26b0 6964 if (exp->X_op != O_symbol)
3992d3b7 6965 goto inv_disp;
636c26b0 6966
e5cb08ac 6967 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6968 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6969 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6970 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6971 exp->X_op = O_subtract;
6972 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6973 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6974 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6975 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6976 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6977 else
29b0f896 6978 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6979 }
252b5132 6980
3992d3b7
AM		 6981 else if (exp->X_op == O_absent
6982 || exp->X_op == O_illegal
ee86248c 6983 || exp->X_op == O_big)
2daf4fd8 6984 {
3992d3b7
AM		 6985 inv_disp:
6986 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6987 disp_start);
3992d3b7 6988 ret = 0;
2daf4fd8
AM		 6989 }
6990
0e1147d9
L		 6991 else if (flag_code == CODE_64BIT
6992 && !i.prefix[ADDR_PREFIX]
6993 && exp->X_op == O_constant)
6994 {
6995 /* Since displacement is signed extended to 64bit, don't allow
6996 disp32 and turn off disp32s if they are out of range. */
6997 i.types[this_operand].bitfield.disp32 = 0;
6998 if (!fits_in_signed_long (exp->X_add_number))
6999 {
7000 i.types[this_operand].bitfield.disp32s = 0;
7001 if (i.types[this_operand].bitfield.baseindex)
7002 {
7003 as_bad (_("0x%lx out range of signed 32bit displacement"),
7004 (long) exp->X_add_number);
7005 ret = 0;
7006 }
7007 }
7008 }
7009
4c63da97 7010#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7011 else if (exp->X_op != O_constant
7012 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7013 && exp_seg != absolute_section
7014 && exp_seg != text_section
7015 && exp_seg != data_section
7016 && exp_seg != bss_section
7017 && exp_seg != undefined_section
7018 && !bfd_is_com_section (exp_seg))
24eab124 7019 {
d0b47220 7020 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7021 ret = 0;
24eab124 7022 }
252b5132 7023#endif
3956db08 7024
40fb9820
L		 7025 /* Check if this is a displacement only operand. */
7026 bigdisp = i.types[this_operand];
7027 bigdisp.bitfield.disp8 = 0;
7028 bigdisp.bitfield.disp16 = 0;
7029 bigdisp.bitfield.disp32 = 0;
7030 bigdisp.bitfield.disp32s = 0;
7031 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7032 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7033 i.types[this_operand] = operand_type_and (i.types[this_operand],
7034 types);
3956db08 7035
3992d3b7 7036 return ret;
252b5132
RH		 7037}
7038
eecb386c 7039/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7040 Return 1 on success, 0 on a failure. */
7041
252b5132 7042static int
e3bb37b5 7043i386_index_check (const char *operand_string)
252b5132 7044{
3e73aa7c 7045 int ok;
fc0763e6 7046 const char *kind = "base/index";
24eab124 7047#if INFER_ADDR_PREFIX
eecb386c
AM		 7048 int fudged = 0;
7049
24eab124
AM		 7050 tryprefix:
7051#endif
3e73aa7c 7052 ok = 1;
fc0763e6
JB		 7053 if (current_templates->start->opcode_modifier.isstring
7054 && !current_templates->start->opcode_modifier.immext
7055 && (current_templates->end[-1].opcode_modifier.isstring
7056 || i.mem_operands))
7057 {
7058 /* Memory operands of string insns are special in that they only allow
7059 a single register (rDI, rSI, or rBX) as their memory address. */
7060 unsigned int expected;
7061
7062 kind = "string address";
7063
7064 if (current_templates->start->opcode_modifier.w)
7065 {
7066 i386_operand_type type = current_templates->end[-1].operand_types[0];
7067
7068 if (!type.bitfield.baseindex
7069 || ((!i.mem_operands != !intel_syntax)
7070 && current_templates->end[-1].operand_types[1]
7071 .bitfield.baseindex))
7072 type = current_templates->end[-1].operand_types[1];
7073 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7074 }
7075 else
7076 expected = 3 /* rBX */;
7077
7078 if (!i.base_reg || i.index_reg
7079 || operand_type_check (i.types[this_operand], disp))
7080 ok = -1;
7081 else if (!(flag_code == CODE_64BIT
7082 ? i.prefix[ADDR_PREFIX]
7083 ? i.base_reg->reg_type.bitfield.reg32
7084 : i.base_reg->reg_type.bitfield.reg64
7085 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7086 ? i.base_reg->reg_type.bitfield.reg32
7087 : i.base_reg->reg_type.bitfield.reg16))
7088 ok = 0;
7089 else if (i.base_reg->reg_num != expected)
7090 ok = -1;
7091
7092 if (ok < 0)
7093 {
7094 unsigned int j;
7095
7096 for (j = 0; j < i386_regtab_size; ++j)
7097 if ((flag_code == CODE_64BIT
7098 ? i.prefix[ADDR_PREFIX]
7099 ? i386_regtab[j].reg_type.bitfield.reg32
7100 : i386_regtab[j].reg_type.bitfield.reg64
7101 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7102 ? i386_regtab[j].reg_type.bitfield.reg32
7103 : i386_regtab[j].reg_type.bitfield.reg16)
7104 && i386_regtab[j].reg_num == expected)
7105 break;
9c2799c2 7106 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7107 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7108 operand_string,
7109 intel_syntax ? '[' : '(',
7110 register_prefix,
7111 i386_regtab[j].reg_name,
7112 intel_syntax ? ']' : ')');
7113 ok = 1;
7114 }
7115 }
7116 else if (flag_code == CODE_64BIT)
64e74474 7117 {
64e74474 7118 if ((i.base_reg
40fb9820
L		 7119 && ((i.prefix[ADDR_PREFIX] == 0
7120 && !i.base_reg->reg_type.bitfield.reg64)
7121 || (i.prefix[ADDR_PREFIX]
7122 && !i.base_reg->reg_type.bitfield.reg32))
7123 && (i.index_reg
9a04903e
JB		 7124 || i.base_reg->reg_num !=
7125 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7126 || (i.index_reg
40fb9820
L		 7127 && (!i.index_reg->reg_type.bitfield.baseindex
7128 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7129 && i.index_reg->reg_num != RegRiz
7130 && !i.index_reg->reg_type.bitfield.reg64
7131 )
40fb9820 7132 || (i.prefix[ADDR_PREFIX]
db51cc60 7133 && i.index_reg->reg_num != RegEiz
40fb9820 7134 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7135 ok = 0;
3e73aa7c
JH		 7136 }
7137 else
7138 {
7139 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7140 {
7141 /* 16bit checks. */
7142 if ((i.base_reg
40fb9820
L		 7143 && (!i.base_reg->reg_type.bitfield.reg16
7144 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7145 || (i.index_reg
40fb9820
L		 7146 && (!i.index_reg->reg_type.bitfield.reg16
7147 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7148 || !(i.base_reg
7149 && i.base_reg->reg_num < 6
7150 && i.index_reg->reg_num >= 6
7151 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7152 ok = 0;
7153 }
7154 else
e5cb08ac 7155 {
3e73aa7c
JH		 7156 /* 32bit checks. */
7157 if ((i.base_reg
40fb9820 7158 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7159 || (i.index_reg
db51cc60
L		 7160 && ((!i.index_reg->reg_type.bitfield.reg32
7161 && i.index_reg->reg_num != RegEiz)
40fb9820 7162 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7163 ok = 0;
3e73aa7c
JH		 7164 }
7165 }
7166 if (!ok)
24eab124
AM		 7167 {
7168#if INFER_ADDR_PREFIX
fc0763e6 7169 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7170 {
7171 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7172 i.prefixes += 1;
b23bac36
AM		 7173 /* Change the size of any displacement too. At most one of
7174 Disp16 or Disp32 is set.
7175 FIXME. There doesn't seem to be any real need for separate
7176 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7177 Removing them would probably clean up the code quite a lot. */
4eed87de 7178 if (flag_code != CODE_64BIT
40fb9820
L		 7179 && (i.types[this_operand].bitfield.disp16
7180 || i.types[this_operand].bitfield.disp32))
7181 i.types[this_operand]
c6fb90c8 7182 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7183 fudged = 1;
24eab124
AM		 7184 goto tryprefix;
7185 }
eecb386c 7186 if (fudged)
fc0763e6
JB		 7187 as_bad (_("`%s' is not a valid %s expression"),
7188 operand_string,
7189 kind);
eecb386c 7190 else
c388dee8 7191#endif
fc0763e6 7192 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7193 operand_string,
fc0763e6
JB		 7194 flag_code_names[i.prefix[ADDR_PREFIX]
7195 ? flag_code == CODE_32BIT
7196 ? CODE_16BIT
7197 : CODE_32BIT
7198 : flag_code],
7199 kind);
24eab124 7200 }
20f0a1fc 7201 return ok;
24eab124 7202}
252b5132 7203
fc0763e6 7204/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7205 on error. */
252b5132 7206
252b5132 7207static int
a7619375 7208i386_att_operand (char *operand_string)
252b5132 7209{
af6bdddf
AM		 7210 const reg_entry *r;
7211 char *end_op;
24eab124 7212 char *op_string = operand_string;
252b5132 7213
24eab124 7214 if (is_space_char (*op_string))
252b5132
RH		 7215 ++op_string;
7216
24eab124 7217 /* We check for an absolute prefix (differentiating,
47926f60 7218 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7219 if (*op_string == ABSOLUTE_PREFIX)
7220 {
7221 ++op_string;
7222 if (is_space_char (*op_string))
7223 ++op_string;
40fb9820 7224 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7225 }
252b5132 7226
47926f60 7227 /* Check if operand is a register. */
4d1bb795 7228 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7229 {
40fb9820
L		 7230 i386_operand_type temp;
7231
24eab124
AM		 7232 /* Check for a segment override by searching for ':' after a
7233 segment register. */
7234 op_string = end_op;
7235 if (is_space_char (*op_string))
7236 ++op_string;
40fb9820
L		 7237 if (*op_string == ':'
7238 && (r->reg_type.bitfield.sreg2
7239 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7240 {
7241 switch (r->reg_num)
7242 {
7243 case 0:
7244 i.seg[i.mem_operands] = &es;
7245 break;
7246 case 1:
7247 i.seg[i.mem_operands] = &cs;
7248 break;
7249 case 2:
7250 i.seg[i.mem_operands] = &ss;
7251 break;
7252 case 3:
7253 i.seg[i.mem_operands] = &ds;
7254 break;
7255 case 4:
7256 i.seg[i.mem_operands] = &fs;
7257 break;
7258 case 5:
7259 i.seg[i.mem_operands] = &gs;
7260 break;
7261 }
252b5132 7262
24eab124 7263 /* Skip the ':' and whitespace. */
252b5132
RH		 7264 ++op_string;
7265 if (is_space_char (*op_string))
24eab124 7266 ++op_string;
252b5132 7267
24eab124
AM		 7268 if (!is_digit_char (*op_string)
7269 && !is_identifier_char (*op_string)
7270 && *op_string != '('
7271 && *op_string != ABSOLUTE_PREFIX)
7272 {
7273 as_bad (_("bad memory operand `%s'"), op_string);
7274 return 0;
7275 }
47926f60 7276 /* Handle case of %es:*foo. */
24eab124
AM		 7277 if (*op_string == ABSOLUTE_PREFIX)
7278 {
7279 ++op_string;
7280 if (is_space_char (*op_string))
7281 ++op_string;
40fb9820 7282 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7283 }
7284 goto do_memory_reference;
7285 }
7286 if (*op_string)
7287 {
d0b47220 7288 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7289 return 0;
7290 }
40fb9820
L		 7291 temp = r->reg_type;
7292 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7293 i.types[this_operand] = operand_type_or (i.types[this_operand],
7294 temp);
7d5e4556 7295 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7296 i.op[this_operand].regs = r;
24eab124
AM		 7297 i.reg_operands++;
7298 }
af6bdddf
AM		 7299 else if (*op_string == REGISTER_PREFIX)
7300 {
7301 as_bad (_("bad register name `%s'"), op_string);
7302 return 0;
7303 }
24eab124 7304 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7305 {
24eab124 7306 ++op_string;
40fb9820 7307 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7308 {
d0b47220 7309 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7310 return 0;
7311 }
7312 if (!i386_immediate (op_string))
7313 return 0;
7314 }
7315 else if (is_digit_char (*op_string)
7316 || is_identifier_char (*op_string)
e5cb08ac 7317 || *op_string == '(')
24eab124 7318 {
47926f60 7319 /* This is a memory reference of some sort. */
af6bdddf 7320 char *base_string;
252b5132 7321
47926f60 7322 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7323 char *displacement_string_start;
7324 char *displacement_string_end;
252b5132 7325
24eab124 7326 do_memory_reference:
24eab124 7327 if ((i.mem_operands == 1
40fb9820 7328 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7329 || i.mem_operands == 2)
7330 {
7331 as_bad (_("too many memory references for `%s'"),
7332 current_templates->start->name);
7333 return 0;
7334 }
252b5132 7335
24eab124
AM		 7336 /* Check for base index form. We detect the base index form by
7337 looking for an ')' at the end of the operand, searching
7338 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7339 after the '('. */
af6bdddf 7340 base_string = op_string + strlen (op_string);
c3332e24 7341
af6bdddf
AM		 7342 --base_string;
7343 if (is_space_char (*base_string))
7344 --base_string;
252b5132 7345
47926f60 7346 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7347 displacement_string_start = op_string;
7348 displacement_string_end = base_string + 1;
252b5132 7349
24eab124
AM		 7350 if (*base_string == ')')
7351 {
af6bdddf 7352 char *temp_string;
24eab124
AM		 7353 unsigned int parens_balanced = 1;
7354 /* We've already checked that the number of left & right ()'s are
47926f60 7355 equal, so this loop will not be infinite. */
24eab124
AM		 7356 do
7357 {
7358 base_string--;
7359 if (*base_string == ')')
7360 parens_balanced++;
7361 if (*base_string == '(')
7362 parens_balanced--;
7363 }
7364 while (parens_balanced);
c3332e24 7365
af6bdddf 7366 temp_string = base_string;
c3332e24 7367
24eab124 7368 /* Skip past '(' and whitespace. */
252b5132
RH		 7369 ++base_string;
7370 if (is_space_char (*base_string))
24eab124 7371 ++base_string;
252b5132 7372
af6bdddf 7373 if (*base_string == ','
4eed87de
AM		 7374 || ((i.base_reg = parse_register (base_string, &end_op))
7375 != NULL))
252b5132 7376 {
af6bdddf 7377 displacement_string_end = temp_string;
252b5132 7378
40fb9820 7379 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7380
af6bdddf 7381 if (i.base_reg)
24eab124 7382 {
24eab124
AM		 7383 base_string = end_op;
7384 if (is_space_char (*base_string))
7385 ++base_string;
af6bdddf
AM		 7386 }
7387
7388 /* There may be an index reg or scale factor here. */
7389 if (*base_string == ',')
7390 {
7391 ++base_string;
7392 if (is_space_char (*base_string))
7393 ++base_string;
7394
4eed87de
AM		 7395 if ((i.index_reg = parse_register (base_string, &end_op))
7396 != NULL)
24eab124 7397 {
af6bdddf 7398 base_string = end_op;
24eab124
AM		 7399 if (is_space_char (*base_string))
7400 ++base_string;
af6bdddf
AM		 7401 if (*base_string == ',')
7402 {
7403 ++base_string;
7404 if (is_space_char (*base_string))
7405 ++base_string;
7406 }
e5cb08ac 7407 else if (*base_string != ')')
af6bdddf 7408 {
4eed87de
AM		 7409 as_bad (_("expecting `,' or `)' "
7410 "after index register in `%s'"),
af6bdddf
AM		 7411 operand_string);
7412 return 0;
7413 }
24eab124 7414 }
af6bdddf 7415 else if (*base_string == REGISTER_PREFIX)
24eab124 7416 {
af6bdddf 7417 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7418 return 0;
7419 }
252b5132 7420
47926f60 7421 /* Check for scale factor. */
551c1ca1 7422 if (*base_string != ')')
af6bdddf 7423 {
551c1ca1
AM		 7424 char *end_scale = i386_scale (base_string);
7425
7426 if (!end_scale)
af6bdddf 7427 return 0;
24eab124 7428
551c1ca1 7429 base_string = end_scale;
af6bdddf
AM		 7430 if (is_space_char (*base_string))
7431 ++base_string;
7432 if (*base_string != ')')
7433 {
4eed87de
AM		 7434 as_bad (_("expecting `)' "
7435 "after scale factor in `%s'"),
af6bdddf
AM		 7436 operand_string);
7437 return 0;
7438 }
7439 }
7440 else if (!i.index_reg)
24eab124 7441 {
4eed87de
AM		 7442 as_bad (_("expecting index register or scale factor "
7443 "after `,'; got '%c'"),
af6bdddf 7444 *base_string);
24eab124
AM		 7445 return 0;
7446 }
7447 }
af6bdddf 7448 else if (*base_string != ')')
24eab124 7449 {
4eed87de
AM		 7450 as_bad (_("expecting `,' or `)' "
7451 "after base register in `%s'"),
af6bdddf 7452 operand_string);
24eab124
AM		 7453 return 0;
7454 }
c3332e24 7455 }
af6bdddf 7456 else if (*base_string == REGISTER_PREFIX)
c3332e24 7457 {
af6bdddf 7458 as_bad (_("bad register name `%s'"), base_string);
24eab124 7459 return 0;
c3332e24 7460 }
24eab124
AM		 7461 }
7462
7463 /* If there's an expression beginning the operand, parse it,
7464 assuming displacement_string_start and
7465 displacement_string_end are meaningful. */
7466 if (displacement_string_start != displacement_string_end)
7467 {
7468 if (!i386_displacement (displacement_string_start,
7469 displacement_string_end))
7470 return 0;
7471 }
7472
7473 /* Special case for (%dx) while doing input/output op. */
7474 if (i.base_reg
0dfbf9d7
L		 7475 && operand_type_equal (&i.base_reg->reg_type,
7476 &reg16_inoutportreg)
24eab124
AM		 7477 && i.index_reg == 0
7478 && i.log2_scale_factor == 0
7479 && i.seg[i.mem_operands] == 0
40fb9820 7480 && !operand_type_check (i.types[this_operand], disp))
24eab124 7481 {
65da13b5 7482 i.types[this_operand] = inoutportreg;
24eab124
AM		 7483 return 1;
7484 }
7485
eecb386c
AM		 7486 if (i386_index_check (operand_string) == 0)
7487 return 0;
5c07affc 7488 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7489 i.mem_operands++;
7490 }
7491 else
ce8a8b2f
AM		 7492 {
7493 /* It's not a memory operand; argh! */
24eab124
AM		 7494 as_bad (_("invalid char %s beginning operand %d `%s'"),
7495 output_invalid (*op_string),
7496 this_operand + 1,
7497 op_string);
7498 return 0;
7499 }
47926f60 7500 return 1; /* Normal return. */
252b5132
RH		 7501}
7502\f
ee7fcc42
AM		 7503/* md_estimate_size_before_relax()
7504
7505 Called just before relax() for rs_machine_dependent frags. The x86
7506 assembler uses these frags to handle variable size jump
7507 instructions.
7508
7509 Any symbol that is now undefined will not become defined.
7510 Return the correct fr_subtype in the frag.
7511 Return the initial "guess for variable size of frag" to caller.
7512 The guess is actually the growth beyond the fixed part. Whatever
7513 we do to grow the fixed or variable part contributes to our
7514 returned value. */
7515
252b5132
RH		 7516int
7517md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7518 fragS *fragP;
7519 segT segment;
252b5132 7520{
252b5132 7521 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7522 check for un-relaxable symbols. On an ELF system, we can't relax
7523 an externally visible symbol, because it may be overridden by a
7524 shared library. */
7525 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7526#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7527 || (IS_ELF
31312f95 7528 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7529 || S_IS_WEAK (fragP->fr_symbol)
7530 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7531 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7532#endif
7533#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7534 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7535 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7536#endif
7537 )
252b5132 7538 {
b98ef147
AM		 7539 /* Symbol is undefined in this segment, or we need to keep a
7540 reloc so that weak symbols can be overridden. */
7541 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7542 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7543 unsigned char *opcode;
7544 int old_fr_fix;
f6af82bd 7545
ee7fcc42 7546 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7547 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7548 else if (size == 2)
f6af82bd
AM		 7549 reloc_type = BFD_RELOC_16_PCREL;
7550 else
7551 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7552
ee7fcc42
AM		 7553 old_fr_fix = fragP->fr_fix;
7554 opcode = (unsigned char *) fragP->fr_opcode;
7555
fddf5b5b 7556 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7557 {
fddf5b5b
AM		 7558 case UNCOND_JUMP:
7559 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7560 opcode[0] = 0xe9;
252b5132 7561 fragP->fr_fix += size;
062cd5e7
AS		 7562 fix_new (fragP, old_fr_fix, size,
7563 fragP->fr_symbol,
7564 fragP->fr_offset, 1,
7565 reloc_type);
252b5132
RH		 7566 break;
7567
fddf5b5b 7568 case COND_JUMP86:
412167cb
AM		 7569 if (size == 2
7570 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7571 {
7572 /* Negate the condition, and branch past an
7573 unconditional jump. */
7574 opcode[0] ^= 1;
7575 opcode[1] = 3;
7576 /* Insert an unconditional jump. */
7577 opcode[2] = 0xe9;
7578 /* We added two extra opcode bytes, and have a two byte
7579 offset. */
7580 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7581 fix_new (fragP, old_fr_fix + 2, 2,
7582 fragP->fr_symbol,
7583 fragP->fr_offset, 1,
7584 reloc_type);
fddf5b5b
AM		 7585 break;
7586 }
7587 /* Fall through. */
7588
7589 case COND_JUMP:
412167cb
AM		 7590 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7591 {
3e02c1cc
AM		 7592 fixS *fixP;
7593
412167cb 7594 fragP->fr_fix += 1;
3e02c1cc
AM		 7595 fixP = fix_new (fragP, old_fr_fix, 1,
7596 fragP->fr_symbol,
7597 fragP->fr_offset, 1,
7598 BFD_RELOC_8_PCREL);
7599 fixP->fx_signed = 1;
412167cb
AM		 7600 break;
7601 }
93c2a809 7602
24eab124 7603 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7604 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7605 opcode[1] = opcode[0] + 0x10;
f6af82bd 7606 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7607 /* We've added an opcode byte. */
7608 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7609 fix_new (fragP, old_fr_fix + 1, size,
7610 fragP->fr_symbol,
7611 fragP->fr_offset, 1,
7612 reloc_type);
252b5132 7613 break;
fddf5b5b
AM		 7614
7615 default:
7616 BAD_CASE (fragP->fr_subtype);
7617 break;
252b5132
RH		 7618 }
7619 frag_wane (fragP);
ee7fcc42 7620 return fragP->fr_fix - old_fr_fix;
252b5132 7621 }
93c2a809 7622
93c2a809
AM		 7623 /* Guess size depending on current relax state. Initially the relax
7624 state will correspond to a short jump and we return 1, because
7625 the variable part of the frag (the branch offset) is one byte
7626 long. However, we can relax a section more than once and in that
7627 case we must either set fr_subtype back to the unrelaxed state,
7628 or return the value for the appropriate branch. */
7629 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7630}
7631
47926f60
KH		 7632/* Called after relax() is finished.
7633
7634 In: Address of frag.
7635 fr_type == rs_machine_dependent.
7636 fr_subtype is what the address relaxed to.
7637
7638 Out: Any fixSs and constants are set up.
7639 Caller will turn frag into a ".space 0". */
7640
252b5132
RH		 7641void
7642md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7643 bfd *abfd ATTRIBUTE_UNUSED;
7644 segT sec ATTRIBUTE_UNUSED;
29b0f896 7645 fragS *fragP;
252b5132 7646{
29b0f896 7647 unsigned char *opcode;
252b5132 7648 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7649 offsetT target_address;
7650 offsetT opcode_address;
252b5132 7651 unsigned int extension = 0;
847f7ad4 7652 offsetT displacement_from_opcode_start;
252b5132
RH		 7653
7654 opcode = (unsigned char *) fragP->fr_opcode;
7655
47926f60 7656 /* Address we want to reach in file space. */
252b5132 7657 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7658
47926f60 7659 /* Address opcode resides at in file space. */
252b5132
RH		 7660 opcode_address = fragP->fr_address + fragP->fr_fix;
7661
47926f60 7662 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7663 displacement_from_opcode_start = target_address - opcode_address;
7664
fddf5b5b 7665 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7666 {
47926f60
KH		 7667 /* Don't have to change opcode. */
7668 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7669 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7670 }
7671 else
7672 {
7673 if (no_cond_jump_promotion
7674 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7675 as_warn_where (fragP->fr_file, fragP->fr_line,
7676 _("long jump required"));
252b5132 7677
fddf5b5b
AM		 7678 switch (fragP->fr_subtype)
7679 {
7680 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7681 extension = 4; /* 1 opcode + 4 displacement */
7682 opcode[0] = 0xe9;
7683 where_to_put_displacement = &opcode[1];
7684 break;
252b5132 7685
fddf5b5b
AM		 7686 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7687 extension = 2; /* 1 opcode + 2 displacement */
7688 opcode[0] = 0xe9;
7689 where_to_put_displacement = &opcode[1];
7690 break;
252b5132 7691
fddf5b5b
AM		 7692 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7693 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7694 extension = 5; /* 2 opcode + 4 displacement */
7695 opcode[1] = opcode[0] + 0x10;
7696 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7697 where_to_put_displacement = &opcode[2];
7698 break;
252b5132 7699
fddf5b5b
AM		 7700 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7701 extension = 3; /* 2 opcode + 2 displacement */
7702 opcode[1] = opcode[0] + 0x10;
7703 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7704 where_to_put_displacement = &opcode[2];
7705 break;
252b5132 7706
fddf5b5b
AM		 7707 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7708 extension = 4;
7709 opcode[0] ^= 1;
7710 opcode[1] = 3;
7711 opcode[2] = 0xe9;
7712 where_to_put_displacement = &opcode[3];
7713 break;
7714
7715 default:
7716 BAD_CASE (fragP->fr_subtype);
7717 break;
7718 }
252b5132 7719 }
fddf5b5b 7720
7b81dfbb
AJ		 7721 /* If size if less then four we are sure that the operand fits,
7722 but if it's 4, then it could be that the displacement is larger
7723 then -/+ 2GB. */
7724 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7725 && object_64bit
7726 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7727 + ((addressT) 1 << 31))
7728 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7729 {
7730 as_bad_where (fragP->fr_file, fragP->fr_line,
7731 _("jump target out of range"));
7732 /* Make us emit 0. */
7733 displacement_from_opcode_start = extension;
7734 }
47926f60 7735 /* Now put displacement after opcode. */
252b5132
RH		 7736 md_number_to_chars ((char *) where_to_put_displacement,
7737 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7738 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7739 fragP->fr_fix += extension;
7740}
7741\f
252b5132
RH		 7742/* Apply a fixup (fixS) to segment data, once it has been determined
7743 by our caller that we have all the info we need to fix it up.
7744
7745 On the 386, immediates, displacements, and data pointers are all in
7746 the same (little-endian) format, so we don't need to care about which
7747 we are handling. */
7748
94f592af 7749void
55cf6793 7750md_apply_fix (fixP, valP, seg)
47926f60
KH		 7751 /* The fix we're to put in. */
7752 fixS *fixP;
47926f60 7753 /* Pointer to the value of the bits. */
c6682705 7754 valueT *valP;
47926f60
KH		 7755 /* Segment fix is from. */
7756 segT seg ATTRIBUTE_UNUSED;
252b5132 7757{
94f592af 7758 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7759 valueT value = *valP;
252b5132 7760
f86103b7 7761#if !defined (TE_Mach)
93382f6d
AM		 7762 if (fixP->fx_pcrel)
7763 {
7764 switch (fixP->fx_r_type)
7765 {
5865bb77
ILT		 7766 default:
7767 break;
7768
d6ab8113
JB		 7769 case BFD_RELOC_64:
7770 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7771 break;
93382f6d 7772 case BFD_RELOC_32:
ae8887b5 7773 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7774 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7775 break;
7776 case BFD_RELOC_16:
7777 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7778 break;
7779 case BFD_RELOC_8:
7780 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7781 break;
7782 }
7783 }
252b5132 7784
a161fe53 7785 if (fixP->fx_addsy != NULL
31312f95 7786 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7787 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7788 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7789 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7790 && !use_rela_relocations)
252b5132 7791 {
31312f95
AM		 7792 /* This is a hack. There should be a better way to handle this.
7793 This covers for the fact that bfd_install_relocation will
7794 subtract the current location (for partial_inplace, PC relative
7795 relocations); see more below. */
252b5132 7796#ifndef OBJ_AOUT
718ddfc0 7797 if (IS_ELF
252b5132
RH		 7798#ifdef TE_PE
7799 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7800#endif
7801 )
7802 value += fixP->fx_where + fixP->fx_frag->fr_address;
7803#endif
7804#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7805 if (IS_ELF)
252b5132 7806 {
6539b54b 7807 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7808
6539b54b 7809 if ((sym_seg == seg
2f66722d 7810 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7811 && sym_seg != absolute_section))
af65af87 7812 && !generic_force_reloc (fixP))
2f66722d
AM		 7813 {
7814 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7815 bfd_install_relocation subtracts them out again. I think
7816 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7817 it. FIXME. */
7818 value += fixP->fx_where + fixP->fx_frag->fr_address;
7819 }
252b5132
RH		 7820 }
7821#endif
7822#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7823 /* For some reason, the PE format does not store a
7824 section address offset for a PC relative symbol. */
7825 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7826 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7827 value += md_pcrel_from (fixP);
7828#endif
7829 }
fbeb56a4
DK		 7830#if defined (OBJ_COFF) && defined (TE_PE)
7831 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7832 {
7833 value -= S_GET_VALUE (fixP->fx_addsy);
7834 }
7835#endif
252b5132
RH		 7836
7837 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7838 and we must not disappoint it. */
252b5132 7839#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7840 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7841 switch (fixP->fx_r_type)
7842 {
7843 case BFD_RELOC_386_PLT32:
3e73aa7c 7844 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7845 /* Make the jump instruction point to the address of the operand. At
7846 runtime we merely add the offset to the actual PLT entry. */
7847 value = -4;
7848 break;
31312f95 7849
13ae64f3
JJ		 7850 case BFD_RELOC_386_TLS_GD:
7851 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7852 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7853 case BFD_RELOC_386_TLS_IE:
7854 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7855 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7856 case BFD_RELOC_X86_64_TLSGD:
7857 case BFD_RELOC_X86_64_TLSLD:
7858 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7859 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7860 value = 0; /* Fully resolved at runtime. No addend. */
7861 /* Fallthrough */
7862 case BFD_RELOC_386_TLS_LE:
7863 case BFD_RELOC_386_TLS_LDO_32:
7864 case BFD_RELOC_386_TLS_LE_32:
7865 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7866 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7867 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7868 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7869 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7870 break;
7871
67a4f2b7
AO		 7872 case BFD_RELOC_386_TLS_DESC_CALL:
7873 case BFD_RELOC_X86_64_TLSDESC_CALL:
7874 value = 0; /* Fully resolved at runtime. No addend. */
7875 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7876 fixP->fx_done = 0;
7877 return;
7878
00f7efb6
JJ		 7879 case BFD_RELOC_386_GOT32:
7880 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7881 value = 0; /* Fully resolved at runtime. No addend. */
7882 break;
47926f60
KH		 7883
7884 case BFD_RELOC_VTABLE_INHERIT:
7885 case BFD_RELOC_VTABLE_ENTRY:
7886 fixP->fx_done = 0;
94f592af 7887 return;
47926f60
KH		 7888
7889 default:
7890 break;
7891 }
7892#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7893 *valP = value;
f86103b7 7894#endif /* !defined (TE_Mach) */
3e73aa7c 7895
3e73aa7c 7896 /* Are we finished with this relocation now? */
c6682705 7897 if (fixP->fx_addsy == NULL)
3e73aa7c 7898 fixP->fx_done = 1;
fbeb56a4
DK		 7899#if defined (OBJ_COFF) && defined (TE_PE)
7900 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7901 {
7902 fixP->fx_done = 0;
7903 /* Remember value for tc_gen_reloc. */
7904 fixP->fx_addnumber = value;
7905 /* Clear out the frag for now. */
7906 value = 0;
7907 }
7908#endif
3e73aa7c
JH		 7909 else if (use_rela_relocations)
7910 {
7911 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7912 /* Remember value for tc_gen_reloc. */
7913 fixP->fx_addnumber = value;
3e73aa7c
JH		 7914 value = 0;
7915 }
f86103b7 7916
94f592af 7917 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7918}
252b5132 7919\f
252b5132 7920char *
499ac353 7921md_atof (int type, char *litP, int *sizeP)
252b5132 7922{
499ac353
NC		 7923 /* This outputs the LITTLENUMs in REVERSE order;
7924 in accord with the bigendian 386. */
7925 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7926}
7927\f
2d545b82 7928static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7929
252b5132 7930static char *
e3bb37b5 7931output_invalid (int c)
252b5132 7932{
3882b010 7933 if (ISPRINT (c))
f9f21a03
L		 7934 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7935 "'%c'", c);
252b5132 7936 else
f9f21a03 7937 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7938 "(0x%x)", (unsigned char) c);
252b5132
RH		 7939 return output_invalid_buf;
7940}
7941
af6bdddf 7942/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7943
7944static const reg_entry *
4d1bb795 7945parse_real_register (char *reg_string, char **end_op)
252b5132 7946{
af6bdddf
AM		 7947 char *s = reg_string;
7948 char *p;
252b5132
RH		 7949 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7950 const reg_entry *r;
7951
7952 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7953 if (*s == REGISTER_PREFIX)
7954 ++s;
7955
7956 if (is_space_char (*s))
7957 ++s;
7958
7959 p = reg_name_given;
af6bdddf 7960 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7961 {
7962 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7963 return (const reg_entry *) NULL;
7964 s++;
252b5132
RH		 7965 }
7966
6588847e
DN		 7967 /* For naked regs, make sure that we are not dealing with an identifier.
7968 This prevents confusing an identifier like `eax_var' with register
7969 `eax'. */
7970 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7971 return (const reg_entry *) NULL;
7972
af6bdddf 7973 *end_op = s;
252b5132
RH		 7974
7975 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7976
5f47d35b 7977 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7978 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7979 {
5f47d35b
AM		 7980 if (is_space_char (*s))
7981 ++s;
7982 if (*s == '(')
7983 {
af6bdddf 7984 ++s;
5f47d35b
AM		 7985 if (is_space_char (*s))
7986 ++s;
7987 if (*s >= '0' && *s <= '7')
7988 {
db557034 7989 int fpr = *s - '0';
af6bdddf 7990 ++s;
5f47d35b
AM		 7991 if (is_space_char (*s))
7992 ++s;
7993 if (*s == ')')
7994 {
7995 *end_op = s + 1;
1e9cc1c2 7996 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7997 know (r);
7998 return r + fpr;
5f47d35b 7999 }
5f47d35b 8000 }
47926f60 8001 /* We have "%st(" then garbage. */
5f47d35b
AM		 8002 return (const reg_entry *) NULL;
8003 }
8004 }
8005
a60de03c
JB		 8006 if (r == NULL || allow_pseudo_reg)
8007 return r;
8008
0dfbf9d7 8009 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8010 return (const reg_entry *) NULL;
8011
192dc9c6
JB		 8012 if ((r->reg_type.bitfield.reg32
8013 || r->reg_type.bitfield.sreg3
8014 || r->reg_type.bitfield.control
8015 || r->reg_type.bitfield.debug
8016 || r->reg_type.bitfield.test)
8017 && !cpu_arch_flags.bitfield.cpui386)
8018 return (const reg_entry *) NULL;
8019
309d3373
JB		 8020 if (r->reg_type.bitfield.floatreg
8021 && !cpu_arch_flags.bitfield.cpu8087
8022 && !cpu_arch_flags.bitfield.cpu287
8023 && !cpu_arch_flags.bitfield.cpu387)
8024 return (const reg_entry *) NULL;
8025
192dc9c6
JB		 8026 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8027 return (const reg_entry *) NULL;
8028
8029 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8030 return (const reg_entry *) NULL;
8031
40f12533
L		 8032 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8033 return (const reg_entry *) NULL;
8034
db51cc60 8035 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8036 if (!allow_index_reg
db51cc60
L		 8037 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8038 return (const reg_entry *) NULL;
8039
a60de03c
JB		 8040 if (((r->reg_flags & (RegRex64 | RegRex))
8041 || r->reg_type.bitfield.reg64)
40fb9820 8042 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8043 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8044 && flag_code != CODE_64BIT)
20f0a1fc 8045 return (const reg_entry *) NULL;
1ae00879 8046
b7240065
JB		 8047 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8048 return (const reg_entry *) NULL;
8049
252b5132
RH		 8050 return r;
8051}
4d1bb795
JB		 8052
8053/* REG_STRING starts *before* REGISTER_PREFIX. */
8054
8055static const reg_entry *
8056parse_register (char *reg_string, char **end_op)
8057{
8058 const reg_entry *r;
8059
8060 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8061 r = parse_real_register (reg_string, end_op);
8062 else
8063 r = NULL;
8064 if (!r)
8065 {
8066 char *save = input_line_pointer;
8067 char c;
8068 symbolS *symbolP;
8069
8070 input_line_pointer = reg_string;
8071 c = get_symbol_end ();
8072 symbolP = symbol_find (reg_string);
8073 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8074 {
8075 const expressionS *e = symbol_get_value_expression (symbolP);
8076
0398aac5 8077 know (e->X_op == O_register);
4eed87de 8078 know (e->X_add_number >= 0
c3fe08fa 8079 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8080 r = i386_regtab + e->X_add_number;
8081 *end_op = input_line_pointer;
8082 }
8083 *input_line_pointer = c;
8084 input_line_pointer = save;
8085 }
8086 return r;
8087}
8088
8089int
8090i386_parse_name (char *name, expressionS *e, char *nextcharP)
8091{
8092 const reg_entry *r;
8093 char *end = input_line_pointer;
8094
8095 *end = *nextcharP;
8096 r = parse_register (name, &input_line_pointer);
8097 if (r && end <= input_line_pointer)
8098 {
8099 *nextcharP = *input_line_pointer;
8100 *input_line_pointer = 0;
8101 e->X_op = O_register;
8102 e->X_add_number = r - i386_regtab;
8103 return 1;
8104 }
8105 input_line_pointer = end;
8106 *end = 0;
ee86248c 8107 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8108}
8109
8110void
8111md_operand (expressionS *e)
8112{
ee86248c
JB		 8113 char *end;
8114 const reg_entry *r;
4d1bb795 8115
ee86248c
JB		 8116 switch (*input_line_pointer)
8117 {
8118 case REGISTER_PREFIX:
8119 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8120 if (r)
8121 {
8122 e->X_op = O_register;
8123 e->X_add_number = r - i386_regtab;
8124 input_line_pointer = end;
8125 }
ee86248c
JB		 8126 break;
8127
8128 case '[':
9c2799c2 8129 gas_assert (intel_syntax);
ee86248c
JB		 8130 end = input_line_pointer++;
8131 expression (e);
8132 if (*input_line_pointer == ']')
8133 {
8134 ++input_line_pointer;
8135 e->X_op_symbol = make_expr_symbol (e);
8136 e->X_add_symbol = NULL;
8137 e->X_add_number = 0;
8138 e->X_op = O_index;
8139 }
8140 else
8141 {
8142 e->X_op = O_absent;
8143 input_line_pointer = end;
8144 }
8145 break;
4d1bb795
JB		 8146 }
8147}
8148
252b5132 8149\f
4cc782b5 8150#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8151const char *md_shortopts = "kVQ:sqn";
252b5132 8152#else
12b55ccc 8153const char *md_shortopts = "qn";
252b5132 8154#endif
6e0b89ee 8155
3e73aa7c 8156#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8157#define OPTION_64 (OPTION_MD_BASE + 1)
8158#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8159#define OPTION_MARCH (OPTION_MD_BASE + 3)
8160#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8161#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8162#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8163#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8164#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8165#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8166#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8167#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8168#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8169#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8170
99ad8390
NC		 8171struct option md_longopts[] =
8172{
3e73aa7c 8173 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8174#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8175 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8176 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8177#endif
8178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8179 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8180#endif
b3b91714 8181 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8182 {"march", required_argument, NULL, OPTION_MARCH},
8183 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8184 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8185 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8186 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8187 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8188 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8189 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8190 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8191 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8192 {NULL, no_argument, NULL, 0}
8193};
8194size_t md_longopts_size = sizeof (md_longopts);
8195
8196int
9103f4f4 8197md_parse_option (int c, char *arg)
252b5132 8198{
91d6fa6a 8199 unsigned int j;
6305a203 8200 char *arch, *next;
9103f4f4 8201
252b5132
RH		 8202 switch (c)
8203 {
12b55ccc
L		 8204 case 'n':
8205 optimize_align_code = 0;
8206 break;
8207
a38cf1db
AM		 8208 case 'q':
8209 quiet_warnings = 1;
252b5132
RH		 8210 break;
8211
8212#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8213 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8214 should be emitted or not. FIXME: Not implemented. */
8215 case 'Q':
252b5132
RH		 8216 break;
8217
8218 /* -V: SVR4 argument to print version ID. */
8219 case 'V':
8220 print_version_id ();
8221 break;
8222
a38cf1db
AM		 8223 /* -k: Ignore for FreeBSD compatibility. */
8224 case 'k':
252b5132 8225 break;
4cc782b5
ILT		 8226
8227 case 's':
8228 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8229 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8230 break;
99ad8390 8231#endif
321098a5
L		 8232#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8233 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8234 case OPTION_64:
8235 {
8236 const char **list, **l;
8237
3e73aa7c
JH		 8238 list = bfd_target_list ();
8239 for (l = list; *l != NULL; l++)
8620418b 8240 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8241 || strcmp (*l, "coff-x86-64") == 0
8242 || strcmp (*l, "pe-x86-64") == 0
8243 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8244 {
8245 default_arch = "x86_64";
8246 break;
8247 }
3e73aa7c 8248 if (*l == NULL)
2b5d6a91 8249 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8250 free (list);
8251 }
8252 break;
8253#endif
252b5132 8254
351f65ca 8255#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8256 case OPTION_X32:
351f65ca
L		 8257 if (IS_ELF)
8258 {
8259 const char **list, **l;
8260
8261 list = bfd_target_list ();
8262 for (l = list; *l != NULL; l++)
8263 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8264 {
8265 default_arch = "x86_64:32";
8266 break;
8267 }
8268 if (*l == NULL)
2b5d6a91 8269 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8270 free (list);
8271 }
8272 else
8273 as_fatal (_("32bit x86_64 is only supported for ELF"));
8274 break;
8275#endif
8276
6e0b89ee
AM		 8277 case OPTION_32:
8278 default_arch = "i386";
8279 break;
8280
b3b91714
AM		 8281 case OPTION_DIVIDE:
8282#ifdef SVR4_COMMENT_CHARS
8283 {
8284 char *n, *t;
8285 const char *s;
8286
8287 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8288 t = n;
8289 for (s = i386_comment_chars; *s != '\0'; s++)
8290 if (*s != '/')
8291 *t++ = *s;
8292 *t = '\0';
8293 i386_comment_chars = n;
8294 }
8295#endif
8296 break;
8297
9103f4f4 8298 case OPTION_MARCH:
6305a203
L		 8299 arch = xstrdup (arg);
8300 do
9103f4f4 8301 {
6305a203 8302 if (*arch == '.')
2b5d6a91 8303 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8304 next = strchr (arch, '+');
8305 if (next)
8306 *next++ = '\0';
91d6fa6a 8307 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8308 {
91d6fa6a 8309 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8310 {
6305a203 8311 /* Processor. */
1ded5609
JB		 8312 if (! cpu_arch[j].flags.bitfield.cpui386)
8313 continue;
8314
91d6fa6a 8315 cpu_arch_name = cpu_arch[j].name;
6305a203 8316 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8317 cpu_arch_flags = cpu_arch[j].flags;
8318 cpu_arch_isa = cpu_arch[j].type;
8319 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8320 if (!cpu_arch_tune_set)
8321 {
8322 cpu_arch_tune = cpu_arch_isa;
8323 cpu_arch_tune_flags = cpu_arch_isa_flags;
8324 }
8325 break;
8326 }
91d6fa6a
NC		 8327 else if (*cpu_arch [j].name == '.'
8328 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8329 {
8330 /* ISA entension. */
8331 i386_cpu_flags flags;
309d3373 8332
49021df2 8333 if (!cpu_arch[j].negated)
309d3373 8334 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8335 cpu_arch[j].flags);
309d3373
JB		 8336 else
8337 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8338 cpu_arch[j].flags);
0dfbf9d7 8339 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8340 {
8341 if (cpu_sub_arch_name)
8342 {
8343 char *name = cpu_sub_arch_name;
8344 cpu_sub_arch_name = concat (name,
91d6fa6a 8345 cpu_arch[j].name,
1bf57e9f 8346 (const char *) NULL);
6305a203
L		 8347 free (name);
8348 }
8349 else
91d6fa6a 8350 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8351 cpu_arch_flags = flags;
a586129e 8352 cpu_arch_isa_flags = flags;
6305a203
L		 8353 }
8354 break;
ccc9c027 8355 }
9103f4f4 8356 }
6305a203 8357
91d6fa6a 8358 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8359 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8360
8361 arch = next;
9103f4f4 8362 }
6305a203 8363 while (next != NULL );
9103f4f4
L		 8364 break;
8365
8366 case OPTION_MTUNE:
8367 if (*arg == '.')
2b5d6a91 8368 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8369 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8370 {
91d6fa6a 8371 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8372 {
ccc9c027 8373 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8374 cpu_arch_tune = cpu_arch [j].type;
8375 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8376 break;
8377 }
8378 }
91d6fa6a 8379 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8380 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8381 break;
8382
1efbbeb4
L		 8383 case OPTION_MMNEMONIC:
8384 if (strcasecmp (arg, "att") == 0)
8385 intel_mnemonic = 0;
8386 else if (strcasecmp (arg, "intel") == 0)
8387 intel_mnemonic = 1;
8388 else
2b5d6a91 8389 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8390 break;
8391
8392 case OPTION_MSYNTAX:
8393 if (strcasecmp (arg, "att") == 0)
8394 intel_syntax = 0;
8395 else if (strcasecmp (arg, "intel") == 0)
8396 intel_syntax = 1;
8397 else
2b5d6a91 8398 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8399 break;
8400
8401 case OPTION_MINDEX_REG:
8402 allow_index_reg = 1;
8403 break;
8404
8405 case OPTION_MNAKED_REG:
8406 allow_naked_reg = 1;
8407 break;
8408
8409 case OPTION_MOLD_GCC:
8410 old_gcc = 1;
1efbbeb4
L		 8411 break;
8412
c0f3af97
L		 8413 case OPTION_MSSE2AVX:
8414 sse2avx = 1;
8415 break;
8416
daf50ae7
L		 8417 case OPTION_MSSE_CHECK:
8418 if (strcasecmp (arg, "error") == 0)
8419 sse_check = sse_check_error;
8420 else if (strcasecmp (arg, "warning") == 0)
8421 sse_check = sse_check_warning;
8422 else if (strcasecmp (arg, "none") == 0)
8423 sse_check = sse_check_none;
8424 else
2b5d6a91 8425 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8426 break;
8427
539f890d
L		 8428 case OPTION_MAVXSCALAR:
8429 if (strcasecmp (arg, "128") == 0)
8430 avxscalar = vex128;
8431 else if (strcasecmp (arg, "256") == 0)
8432 avxscalar = vex256;
8433 else
2b5d6a91 8434 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8435 break;
8436
252b5132
RH		 8437 default:
8438 return 0;
8439 }
8440 return 1;
8441}
8442
8a2c8fef
L		 8443#define MESSAGE_TEMPLATE \
8444" "
8445
8446static void
1ded5609 8447show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8448{
8449 static char message[] = MESSAGE_TEMPLATE;
8450 char *start = message + 27;
8451 char *p;
8452 int size = sizeof (MESSAGE_TEMPLATE);
8453 int left;
8454 const char *name;
8455 int len;
8456 unsigned int j;
8457
8458 p = start;
8459 left = size - (start - message);
8460 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8461 {
8462 /* Should it be skipped? */
8463 if (cpu_arch [j].skip)
8464 continue;
8465
8466 name = cpu_arch [j].name;
8467 len = cpu_arch [j].len;
8468 if (*name == '.')
8469 {
8470 /* It is an extension. Skip if we aren't asked to show it. */
8471 if (ext)
8472 {
8473 name++;
8474 len--;
8475 }
8476 else
8477 continue;
8478 }
8479 else if (ext)
8480 {
8481 /* It is an processor. Skip if we show only extension. */
8482 continue;
8483 }
1ded5609
JB		 8484 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8485 {
8486 /* It is an impossible processor - skip. */
8487 continue;
8488 }
8a2c8fef
L		 8489
8490 /* Reserve 2 spaces for ", " or ",\0" */
8491 left -= len + 2;
8492
8493 /* Check if there is any room. */
8494 if (left >= 0)
8495 {
8496 if (p != start)
8497 {
8498 *p++ = ',';
8499 *p++ = ' ';
8500 }
8501 p = mempcpy (p, name, len);
8502 }
8503 else
8504 {
8505 /* Output the current message now and start a new one. */
8506 *p++ = ',';
8507 *p = '\0';
8508 fprintf (stream, "%s\n", message);
8509 p = start;
8510 left = size - (start - message) - len - 2;
8511
8512 gas_assert (left >= 0);
8513
8514 p = mempcpy (p, name, len);
8515 }
8516 }
8517
8518 *p = '\0';
8519 fprintf (stream, "%s\n", message);
8520}
8521
252b5132 8522void
8a2c8fef 8523md_show_usage (FILE *stream)
252b5132 8524{
4cc782b5
ILT		 8525#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8526 fprintf (stream, _("\
a38cf1db
AM		 8527 -Q ignored\n\
8528 -V print assembler version number\n\
b3b91714
AM		 8529 -k ignored\n"));
8530#endif
8531 fprintf (stream, _("\
12b55ccc 8532 -n Do not optimize code alignment\n\
b3b91714
AM		 8533 -q quieten some warnings\n"));
8534#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8535 fprintf (stream, _("\
a38cf1db 8536 -s ignored\n"));
b3b91714 8537#endif
321098a5
L		 8538#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8539 || defined (TE_PE) || defined (TE_PEP))
751d281c 8540 fprintf (stream, _("\
570561f7 8541 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8542#endif
b3b91714
AM		 8543#ifdef SVR4_COMMENT_CHARS
8544 fprintf (stream, _("\
8545 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8546#else
8547 fprintf (stream, _("\
b3b91714 8548 --divide ignored\n"));
4cc782b5 8549#endif
9103f4f4 8550 fprintf (stream, _("\
6305a203 8551 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8552 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8553 show_arch (stream, 0, 1);
8a2c8fef
L		 8554 fprintf (stream, _("\
8555 EXTENSION is combination of:\n"));
1ded5609 8556 show_arch (stream, 1, 0);
6305a203 8557 fprintf (stream, _("\
8a2c8fef 8558 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8559 show_arch (stream, 0, 0);
ba104c83 8560 fprintf (stream, _("\
c0f3af97
L		 8561 -msse2avx encode SSE instructions with VEX prefix\n"));
8562 fprintf (stream, _("\
daf50ae7
L		 8563 -msse-check=[none|error|warning]\n\
8564 check SSE instructions\n"));
8565 fprintf (stream, _("\
539f890d
L		 8566 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8567 length\n"));
8568 fprintf (stream, _("\
ba104c83
L		 8569 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8570 fprintf (stream, _("\
8571 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8572 fprintf (stream, _("\
8573 -mindex-reg support pseudo index registers\n"));
8574 fprintf (stream, _("\
8575 -mnaked-reg don't require `%%' prefix for registers\n"));
8576 fprintf (stream, _("\
8577 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8578}
8579
3e73aa7c 8580#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8581 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8583
8584/* Pick the target format to use. */
8585
47926f60 8586const char *
e3bb37b5 8587i386_target_format (void)
252b5132 8588{
351f65ca
L		 8589 if (!strncmp (default_arch, "x86_64", 6))
8590 {
8591 update_code_flag (CODE_64BIT, 1);
8592 if (default_arch[6] == '\0')
7f56bc95 8593 x86_elf_abi = X86_64_ABI;
351f65ca 8594 else
7f56bc95 8595 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8596 }
3e73aa7c 8597 else if (!strcmp (default_arch, "i386"))
78f12dd3 8598 update_code_flag (CODE_32BIT, 1);
3e73aa7c 8599 else
2b5d6a91 8600 as_fatal (_("unknown architecture"));
89507696
JB		 8601
8602 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8603 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8604 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8605 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8606
252b5132
RH		 8607 switch (OUTPUT_FLAVOR)
8608 {
9384f2ff 8609#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8610 case bfd_target_aout_flavour:
47926f60 8611 return AOUT_TARGET_FORMAT;
4c63da97 8612#endif
9384f2ff
AM		 8613#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8614# if defined (TE_PE) || defined (TE_PEP)
8615 case bfd_target_coff_flavour:
8616 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8617# elif defined (TE_GO32)
0561d57c
JK		 8618 case bfd_target_coff_flavour:
8619 return "coff-go32";
9384f2ff 8620# else
252b5132
RH		 8621 case bfd_target_coff_flavour:
8622 return "coff-i386";
9384f2ff 8623# endif
4c63da97 8624#endif
3e73aa7c 8625#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8626 case bfd_target_elf_flavour:
3e73aa7c 8627 {
351f65ca
L		 8628 const char *format;
8629
8630 switch (x86_elf_abi)
4fa24527 8631 {
351f65ca
L		 8632 default:
8633 format = ELF_TARGET_FORMAT;
8634 break;
7f56bc95 8635 case X86_64_ABI:
351f65ca 8636 use_rela_relocations = 1;
4fa24527 8637 object_64bit = 1;
351f65ca
L		 8638 format = ELF_TARGET_FORMAT64;
8639 break;
7f56bc95 8640 case X86_64_X32_ABI:
4fa24527 8641 use_rela_relocations = 1;
351f65ca 8642 object_64bit = 1;
862be3fb 8643 disallow_64bit_reloc = 1;
351f65ca
L		 8644 format = ELF_TARGET_FORMAT32;
8645 break;
4fa24527 8646 }
3632d14b 8647 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8648 {
7f56bc95 8649 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 8650 as_fatal (_("Intel L1OM is 64bit only"));
8651 return ELF_TARGET_L1OM_FORMAT;
8652 }
8653 else
351f65ca 8654 return format;
3e73aa7c 8655 }
e57f8c65
TG		 8656#endif
8657#if defined (OBJ_MACH_O)
8658 case bfd_target_mach_o_flavour:
8659 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8660#endif
252b5132
RH		 8661 default:
8662 abort ();
8663 return NULL;
8664 }
8665}
8666
47926f60 8667#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8668
8669#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8670void
8671i386_elf_emit_arch_note (void)
a847613f 8672{
718ddfc0 8673 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8674 {
8675 char *p;
8676 asection *seg = now_seg;
8677 subsegT subseg = now_subseg;
8678 Elf_Internal_Note i_note;
8679 Elf_External_Note e_note;
8680 asection *note_secp;
8681 int len;
8682
8683 /* Create the .note section. */
8684 note_secp = subseg_new (".note", 0);
8685 bfd_set_section_flags (stdoutput,
8686 note_secp,
8687 SEC_HAS_CONTENTS | SEC_READONLY);
8688
8689 /* Process the arch string. */
8690 len = strlen (cpu_arch_name);
8691
8692 i_note.namesz = len + 1;
8693 i_note.descsz = 0;
8694 i_note.type = NT_ARCH;
8695 p = frag_more (sizeof (e_note.namesz));
8696 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8697 p = frag_more (sizeof (e_note.descsz));
8698 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8699 p = frag_more (sizeof (e_note.type));
8700 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8701 p = frag_more (len + 1);
8702 strcpy (p, cpu_arch_name);
8703
8704 frag_align (2, 0, 0);
8705
8706 subseg_set (seg, subseg);
8707 }
8708}
8709#endif
252b5132 8710\f
252b5132
RH		 8711symbolS *
8712md_undefined_symbol (name)
8713 char *name;
8714{
18dc2407
ILT		 8715 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8716 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8717 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8718 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8719 {
8720 if (!GOT_symbol)
8721 {
8722 if (symbol_find (name))
8723 as_bad (_("GOT already in symbol table"));
8724 GOT_symbol = symbol_new (name, undefined_section,
8725 (valueT) 0, &zero_address_frag);
8726 };
8727 return GOT_symbol;
8728 }
252b5132
RH		 8729 return 0;
8730}
8731
8732/* Round up a section size to the appropriate boundary. */
47926f60 8733
252b5132
RH		 8734valueT
8735md_section_align (segment, size)
ab9da554 8736 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8737 valueT size;
8738{
4c63da97
AM		 8739#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8740 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8741 {
8742 /* For a.out, force the section size to be aligned. If we don't do
8743 this, BFD will align it for us, but it will not write out the
8744 final bytes of the section. This may be a bug in BFD, but it is
8745 easier to fix it here since that is how the other a.out targets
8746 work. */
8747 int align;
8748
8749 align = bfd_get_section_alignment (stdoutput, segment);
8750 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8751 }
252b5132
RH		 8752#endif
8753
8754 return size;
8755}
8756
8757/* On the i386, PC-relative offsets are relative to the start of the
8758 next instruction. That is, the address of the offset, plus its
8759 size, since the offset is always the last part of the insn. */
8760
8761long
e3bb37b5 8762md_pcrel_from (fixS *fixP)
252b5132
RH		 8763{
8764 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8765}
8766
8767#ifndef I386COFF
8768
8769static void
e3bb37b5 8770s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8771{
29b0f896 8772 int temp;
252b5132 8773
8a75718c
JB		 8774#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8775 if (IS_ELF)
8776 obj_elf_section_change_hook ();
8777#endif
252b5132
RH		 8778 temp = get_absolute_expression ();
8779 subseg_set (bss_section, (subsegT) temp);
8780 demand_empty_rest_of_line ();
8781}
8782
8783#endif
8784
252b5132 8785void
e3bb37b5 8786i386_validate_fix (fixS *fixp)
252b5132
RH		 8787{
8788 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8789 {
23df1078
JH		 8790 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8791 {
4fa24527 8792 if (!object_64bit)
23df1078
JH		 8793 abort ();
8794 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8795 }
8796 else
8797 {
4fa24527 8798 if (!object_64bit)
d6ab8113
JB		 8799 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8800 else
8801 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8802 }
252b5132
RH		 8803 fixp->fx_subsy = 0;
8804 }
8805}
8806
252b5132
RH		 8807arelent *
8808tc_gen_reloc (section, fixp)
ab9da554 8809 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8810 fixS *fixp;
8811{
8812 arelent *rel;
8813 bfd_reloc_code_real_type code;
8814
8815 switch (fixp->fx_r_type)
8816 {
3e73aa7c
JH		 8817 case BFD_RELOC_X86_64_PLT32:
8818 case BFD_RELOC_X86_64_GOT32:
8819 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8820 case BFD_RELOC_386_PLT32:
8821 case BFD_RELOC_386_GOT32:
8822 case BFD_RELOC_386_GOTOFF:
8823 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8824 case BFD_RELOC_386_TLS_GD:
8825 case BFD_RELOC_386_TLS_LDM:
8826 case BFD_RELOC_386_TLS_LDO_32:
8827 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8828 case BFD_RELOC_386_TLS_IE:
8829 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8830 case BFD_RELOC_386_TLS_LE_32:
8831 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8832 case BFD_RELOC_386_TLS_GOTDESC:
8833 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8834 case BFD_RELOC_X86_64_TLSGD:
8835 case BFD_RELOC_X86_64_TLSLD:
8836 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8837 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8838 case BFD_RELOC_X86_64_GOTTPOFF:
8839 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8840 case BFD_RELOC_X86_64_TPOFF64:
8841 case BFD_RELOC_X86_64_GOTOFF64:
8842 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8843 case BFD_RELOC_X86_64_GOT64:
8844 case BFD_RELOC_X86_64_GOTPCREL64:
8845 case BFD_RELOC_X86_64_GOTPC64:
8846 case BFD_RELOC_X86_64_GOTPLT64:
8847 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8848 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8849 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8850 case BFD_RELOC_RVA:
8851 case BFD_RELOC_VTABLE_ENTRY:
8852 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8853#ifdef TE_PE
8854 case BFD_RELOC_32_SECREL:
8855#endif
252b5132
RH		 8856 code = fixp->fx_r_type;
8857 break;
dbbaec26
L		 8858 case BFD_RELOC_X86_64_32S:
8859 if (!fixp->fx_pcrel)
8860 {
8861 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8862 code = fixp->fx_r_type;
8863 break;
8864 }
252b5132 8865 default:
93382f6d 8866 if (fixp->fx_pcrel)
252b5132 8867 {
93382f6d
AM		 8868 switch (fixp->fx_size)
8869 {
8870 default:
b091f402
AM		 8871 as_bad_where (fixp->fx_file, fixp->fx_line,
8872 _("can not do %d byte pc-relative relocation"),
8873 fixp->fx_size);
93382f6d
AM		 8874 code = BFD_RELOC_32_PCREL;
8875 break;
8876 case 1: code = BFD_RELOC_8_PCREL; break;
8877 case 2: code = BFD_RELOC_16_PCREL; break;
8878 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8879#ifdef BFD64
8880 case 8: code = BFD_RELOC_64_PCREL; break;
8881#endif
93382f6d
AM		 8882 }
8883 }
8884 else
8885 {
8886 switch (fixp->fx_size)
8887 {
8888 default:
b091f402
AM		 8889 as_bad_where (fixp->fx_file, fixp->fx_line,
8890 _("can not do %d byte relocation"),
8891 fixp->fx_size);
93382f6d
AM		 8892 code = BFD_RELOC_32;
8893 break;
8894 case 1: code = BFD_RELOC_8; break;
8895 case 2: code = BFD_RELOC_16; break;
8896 case 4: code = BFD_RELOC_32; break;
937149dd 8897#ifdef BFD64
3e73aa7c 8898 case 8: code = BFD_RELOC_64; break;
937149dd 8899#endif
93382f6d 8900 }
252b5132
RH		 8901 }
8902 break;
8903 }
252b5132 8904
d182319b
JB		 8905 if ((code == BFD_RELOC_32
8906 || code == BFD_RELOC_32_PCREL
8907 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8908 && GOT_symbol
8909 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8910 {
4fa24527 8911 if (!object_64bit)
d6ab8113
JB		 8912 code = BFD_RELOC_386_GOTPC;
8913 else
8914 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8915 }
7b81dfbb
AJ		 8916 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8917 && GOT_symbol
8918 && fixp->fx_addsy == GOT_symbol)
8919 {
8920 code = BFD_RELOC_X86_64_GOTPC64;
8921 }
252b5132
RH		 8922
8923 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8924 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8925 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8926
8927 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8928
3e73aa7c
JH		 8929 if (!use_rela_relocations)
8930 {
8931 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8932 vtable entry to be used in the relocation's section offset. */
8933 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8934 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8935#if defined (OBJ_COFF) && defined (TE_PE)
8936 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8937 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8938 else
8939#endif
c6682705 8940 rel->addend = 0;
3e73aa7c
JH		 8941 }
8942 /* Use the rela in 64bit mode. */
252b5132 8943 else
3e73aa7c 8944 {
862be3fb
L		 8945 if (disallow_64bit_reloc)
8946 switch (code)
8947 {
8948 case BFD_RELOC_64:
8949 case BFD_RELOC_X86_64_DTPOFF64:
8950 case BFD_RELOC_X86_64_TPOFF64:
8951 case BFD_RELOC_64_PCREL:
8952 case BFD_RELOC_X86_64_GOTOFF64:
8953 case BFD_RELOC_X86_64_GOT64:
8954 case BFD_RELOC_X86_64_GOTPCREL64:
8955 case BFD_RELOC_X86_64_GOTPC64:
8956 case BFD_RELOC_X86_64_GOTPLT64:
8957 case BFD_RELOC_X86_64_PLTOFF64:
8958 as_bad_where (fixp->fx_file, fixp->fx_line,
8959 _("cannot represent relocation type %s in x32 mode"),
8960 bfd_get_reloc_code_name (code));
8961 break;
8962 default:
8963 break;
8964 }
8965
062cd5e7
AS		 8966 if (!fixp->fx_pcrel)
8967 rel->addend = fixp->fx_offset;
8968 else
8969 switch (code)
8970 {
8971 case BFD_RELOC_X86_64_PLT32:
8972 case BFD_RELOC_X86_64_GOT32:
8973 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8974 case BFD_RELOC_X86_64_TLSGD:
8975 case BFD_RELOC_X86_64_TLSLD:
8976 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8977 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8978 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8979 rel->addend = fixp->fx_offset - fixp->fx_size;
8980 break;
8981 default:
8982 rel->addend = (section->vma
8983 - fixp->fx_size
8984 + fixp->fx_addnumber
8985 + md_pcrel_from (fixp));
8986 break;
8987 }
3e73aa7c
JH		 8988 }
8989
252b5132
RH		 8990 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8991 if (rel->howto == NULL)
8992 {
8993 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8994 _("cannot represent relocation type %s"),
252b5132
RH		 8995 bfd_get_reloc_code_name (code));
8996 /* Set howto to a garbage value so that we can keep going. */
8997 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8998 gas_assert (rel->howto != NULL);
252b5132
RH		 8999 }
9000
9001 return rel;
9002}
9003
ee86248c 9004#include "tc-i386-intel.c"
54cfded0 9005
a60de03c
JB		 9006void
9007tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9008{
a60de03c
JB		 9009 int saved_naked_reg;
9010 char saved_register_dot;
54cfded0 9011
a60de03c
JB		 9012 saved_naked_reg = allow_naked_reg;
9013 allow_naked_reg = 1;
9014 saved_register_dot = register_chars['.'];
9015 register_chars['.'] = '.';
9016 allow_pseudo_reg = 1;
9017 expression_and_evaluate (exp);
9018 allow_pseudo_reg = 0;
9019 register_chars['.'] = saved_register_dot;
9020 allow_naked_reg = saved_naked_reg;
9021
e96d56a1 9022 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9023 {
a60de03c
JB		 9024 if ((addressT) exp->X_add_number < i386_regtab_size)
9025 {
9026 exp->X_op = O_constant;
9027 exp->X_add_number = i386_regtab[exp->X_add_number]
9028 .dw2_regnum[flag_code >> 1];
9029 }
9030 else
9031 exp->X_op = O_illegal;
54cfded0 9032 }
54cfded0
AM		 9033}
9034
9035void
9036tc_x86_frame_initial_instructions (void)
9037{
a60de03c
JB		 9038 static unsigned int sp_regno[2];
9039
9040 if (!sp_regno[flag_code >> 1])
9041 {
9042 char *saved_input = input_line_pointer;
9043 char sp[][4] = {"esp", "rsp"};
9044 expressionS exp;
a4447b93 9045
a60de03c
JB		 9046 input_line_pointer = sp[flag_code >> 1];
9047 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9048 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9049 sp_regno[flag_code >> 1] = exp.X_add_number;
9050 input_line_pointer = saved_input;
9051 }
a4447b93 9052
61ff971f
L		 9053 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9054 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9055}
d2b2c203
DJ		 9056
9057int
9058i386_elf_section_type (const char *str, size_t len)
9059{
9060 if (flag_code == CODE_64BIT
9061 && len == sizeof ("unwind") - 1
9062 && strncmp (str, "unwind", 6) == 0)
9063 return SHT_X86_64_UNWIND;
9064
9065 return -1;
9066}
bb41ade5 9067
ad5fec3b
EB		 9068#ifdef TE_SOLARIS
9069void
9070i386_solaris_fix_up_eh_frame (segT sec)
9071{
9072 if (flag_code == CODE_64BIT)
9073 elf_section_type (sec) = SHT_X86_64_UNWIND;
9074}
9075#endif
9076
bb41ade5
AM		 9077#ifdef TE_PE
9078void
9079tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9080{
91d6fa6a 9081 expressionS exp;
bb41ade5 9082
91d6fa6a
NC		 9083 exp.X_op = O_secrel;
9084 exp.X_add_symbol = symbol;
9085 exp.X_add_number = 0;
9086 emit_expr (&exp, size);
bb41ade5
AM		 9087}
9088#endif
3b22753a
L		 9089
9090#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9091/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9092
01e1a5bc 9093bfd_vma
3b22753a
L		 9094x86_64_section_letter (int letter, char **ptr_msg)
9095{
9096 if (flag_code == CODE_64BIT)
9097 {
9098 if (letter == 'l')
9099 return SHF_X86_64_LARGE;
9100
8f3bae45 9101 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9102 }
3b22753a 9103 else
8f3bae45 9104 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9105 return -1;
9106}
9107
01e1a5bc 9108bfd_vma
3b22753a
L		 9109x86_64_section_word (char *str, size_t len)
9110{
8620418b 9111 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9112 return SHF_X86_64_LARGE;
9113
9114 return -1;
9115}
9116
9117static void
9118handle_large_common (int small ATTRIBUTE_UNUSED)
9119{
9120 if (flag_code != CODE_64BIT)
9121 {
9122 s_comm_internal (0, elf_common_parse);
9123 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9124 }
9125 else
9126 {
9127 static segT lbss_section;
9128 asection *saved_com_section_ptr = elf_com_section_ptr;
9129 asection *saved_bss_section = bss_section;
9130
9131 if (lbss_section == NULL)
9132 {
9133 flagword applicable;
9134 segT seg = now_seg;
9135 subsegT subseg = now_subseg;
9136
9137 /* The .lbss section is for local .largecomm symbols. */
9138 lbss_section = subseg_new (".lbss", 0);
9139 applicable = bfd_applicable_section_flags (stdoutput);
9140 bfd_set_section_flags (stdoutput, lbss_section,
9141 applicable & SEC_ALLOC);
9142 seg_info (lbss_section)->bss = 1;
9143
9144 subseg_set (seg, subseg);
9145 }
9146
9147 elf_com_section_ptr = &_bfd_elf_large_com_section;
9148 bss_section = lbss_section;
9149
9150 s_comm_internal (0, elf_common_parse);
9151
9152 elf_com_section_ptr = saved_com_section_ptr;
9153 bss_section = saved_bss_section;
9154 }
9155}
314a59d5
L		 9156
9157static void
9158handle_quad (int nbytes)
9159{
9160 expressionS exp;
9161
9162 if (x86_elf_abi != X86_64_X32_ABI)
9163 {
9164 cons (nbytes);
9165 return;
9166 }
9167
9168 if (is_it_end_of_statement ())
9169 {
9170 demand_empty_rest_of_line ();
9171 return;
9172 }
9173
9174 do
9175 {
9176 if (*input_line_pointer == '"')
9177 {
9178 as_bad (_("unexpected `\"' in expression"));
9179 ignore_rest_of_line ();
9180 return;
9181 }
9182 x86_cons (&exp, nbytes);
9183 /* Output 4 bytes if not constant. */
9184 if (exp.X_op != O_constant)
9185 nbytes = 4;
9186 emit_expr (&exp, (unsigned int) nbytes);
75c1c785
L		 9187 /* Zero-extends to 8 bytes if not constant. */
9188 if (nbytes == 4)
9189 {
9190 memset (&exp, '\0', sizeof (exp));
9191 exp.X_op = O_constant;
9192 emit_expr (&exp, nbytes);
9193 }
9194 nbytes = 8;
314a59d5
L		 9195 }
9196 while (*input_line_pointer++ == ',');
9197
9198 input_line_pointer--; /* Put terminator back into stream. */
9199
9200 demand_empty_rest_of_line ();
314a59d5 9201}
3b22753a 9202#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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