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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
76bc74dc 434 {"i386", PROCESSOR_I386,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
381d071f
L		 503 {".sse4.2", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
505 {".sse4", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
9103f4f4
L		 507 {".3dnow", PROCESSOR_UNKNOWN,
508 CpuMMX|Cpu3dnow},
509 {".3dnowa", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
511 {".padlock", PROCESSOR_UNKNOWN,
512 CpuPadLock},
513 {".pacifica", PROCESSOR_UNKNOWN,
514 CpuSVME},
515 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 516 CpuSVME},
517 {".sse4a", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
519 {".abm", PROCESSOR_UNKNOWN,
520 CpuABM}
e413e4e9
AM		 521};
522
29b0f896
AM		 523const pseudo_typeS md_pseudo_table[] =
524{
525#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes, 0},
527#else
528 {"align", s_align_ptwo, 0},
529#endif
530 {"arch", set_cpu_arch, 0},
531#ifndef I386COFF
532 {"bss", s_bss, 0},
533#endif
534 {"ffloat", float_cons, 'f'},
535 {"dfloat", float_cons, 'd'},
536 {"tfloat", float_cons, 'x'},
537 {"value", cons, 2},
d182319b 538 {"slong", signed_cons, 4},
29b0f896
AM		 539 {"noopt", s_ignore, 0},
540 {"optim", s_ignore, 0},
541 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
542 {"code16", set_code_flag, CODE_16BIT},
543 {"code32", set_code_flag, CODE_32BIT},
544 {"code64", set_code_flag, CODE_64BIT},
545 {"intel_syntax", set_intel_syntax, 1},
546 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common, 0},
07a53e5c 549#else
e3bb37b5 550 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 551 {"loc", dwarf2_directive_loc, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 553#endif
6482c264
NC		 554#ifdef TE_PE
555 {"secrel32", pe_directive_secrel, 0},
556#endif
29b0f896
AM		 557 {0, 0, 0}
558};
559
560/* For interface with expression (). */
561extern char *input_line_pointer;
562
563/* Hash table for instruction mnemonic lookup. */
564static struct hash_control *op_hash;
565
566/* Hash table for register lookup. */
567static struct hash_control *reg_hash;
568\f
252b5132 569void
e3bb37b5 570i386_align_code (fragS *fragP, int count)
252b5132 571{
ce8a8b2f
AM		 572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
252b5132
RH		 575 static const char f32_1[] =
576 {0x90}; /* nop */
577 static const char f32_2[] =
ccc9c027 578 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 579 static const char f32_3[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5[] =
584 {0x90, /* nop */
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8[] =
591 {0x90, /* nop */
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 611 static const char f16_3[] =
612 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 613 static const char f16_4[] =
614 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_5[] =
616 {0x90, /* nop */
617 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_6[] =
619 {0x89,0xf6, /* mov %si,%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_7[] =
622 {0x8d,0x74,0x00, /* lea 0(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_8[] =
625 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 627 static const char jump_31[] =
628 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
631 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 632 static const char *const f32_patt[] = {
633 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 634 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 635 };
636 static const char *const f16_patt[] = {
76bc74dc 637 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 638 };
ccc9c027
L		 639 /* nopl (%[re]ax) */
640 static const char alt_3[] =
641 {0x0f,0x1f,0x00};
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
666 {0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
672 {0x66,
673 0x66,
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
675 /* data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 data16
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
690 {0x66,
691 0x66,
692 0x66,
693 0x66,
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 /* data16
696 data16
697 data16
698 data16
699 data16
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
702 {0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax) */
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 /* nopl 0L(%[re]ax)
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
737 };
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
742 };
252b5132 743
76bc74dc
L		 744 /* Only align for at least a positive non-zero boundary. */
745 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 746 return;
3e73aa7c 747
ccc9c027
L		 748 /* We need to decide which NOP sequence to use for 32bit and
749 64bit. When -mtune= is used:
4eed87de 750
76bc74dc
L		 751 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
752 PROCESSOR_GENERIC32, f32_patt will be used.
753 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
754 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
755 alt_long_patt will be used.
756 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
757 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 758
76bc74dc
L		 759 When -mtune= isn't used, alt_long_patt will be used if
760 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
761 be used.
ccc9c027
L		 762
763 When -march= or .arch is used, we can't use anything beyond
764 cpu_arch_isa_flags. */
765
766 if (flag_code == CODE_16BIT)
767 {
ccc9c027 768 if (count > 8)
33fef721 769 {
76bc74dc
L		 770 memcpy (fragP->fr_literal + fragP->fr_fix,
771 jump_31, count);
772 /* Adjust jump offset. */
773 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 774 }
76bc74dc
L		 775 else
776 memcpy (fragP->fr_literal + fragP->fr_fix,
777 f16_patt[count - 1], count);
252b5132 778 }
33fef721 779 else
ccc9c027
L		 780 {
781 const char *const *patt = NULL;
782
783 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
784 {
785 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
786 switch (cpu_arch_tune)
787 {
788 case PROCESSOR_UNKNOWN:
789 /* We use cpu_arch_isa_flags to check if we SHOULD
790 optimize for Cpu686. */
791 if ((cpu_arch_isa_flags & Cpu686) != 0)
76bc74dc 792 patt = alt_long_patt;
ccc9c027
L		 793 else
794 patt = f32_patt;
795 break;
ccc9c027
L		 796 case PROCESSOR_PENTIUMPRO:
797 case PROCESSOR_PENTIUM4:
798 case PROCESSOR_NOCONA:
ef05d495 799 case PROCESSOR_CORE:
76bc74dc
L		 800 case PROCESSOR_CORE2:
801 case PROCESSOR_GENERIC64:
802 patt = alt_long_patt;
803 break;
ccc9c027
L		 804 case PROCESSOR_K6:
805 case PROCESSOR_ATHLON:
806 case PROCESSOR_K8:
4eed87de 807 case PROCESSOR_AMDFAM10:
ccc9c027
L		 808 patt = alt_short_patt;
809 break;
76bc74dc 810 case PROCESSOR_I386:
ccc9c027
L		 811 case PROCESSOR_I486:
812 case PROCESSOR_PENTIUM:
813 case PROCESSOR_GENERIC32:
814 patt = f32_patt;
815 break;
4eed87de 816 }
ccc9c027
L		 817 }
818 else
819 {
820 switch (cpu_arch_tune)
821 {
822 case PROCESSOR_UNKNOWN:
823 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
824 PROCESSOR_UNKNOWN. */
825 abort ();
826 break;
827
76bc74dc 828 case PROCESSOR_I386:
ccc9c027
L		 829 case PROCESSOR_I486:
830 case PROCESSOR_PENTIUM:
ccc9c027
L		 831 case PROCESSOR_K6:
832 case PROCESSOR_ATHLON:
833 case PROCESSOR_K8:
4eed87de 834 case PROCESSOR_AMDFAM10:
ccc9c027
L		 835 case PROCESSOR_GENERIC32:
836 /* We use cpu_arch_isa_flags to check if we CAN optimize
837 for Cpu686. */
838 if ((cpu_arch_isa_flags & Cpu686) != 0)
839 patt = alt_short_patt;
840 else
841 patt = f32_patt;
842 break;
76bc74dc
L		 843 case PROCESSOR_PENTIUMPRO:
844 case PROCESSOR_PENTIUM4:
845 case PROCESSOR_NOCONA:
846 case PROCESSOR_CORE:
ef05d495 847 case PROCESSOR_CORE2:
ccc9c027
L		 848 if ((cpu_arch_isa_flags & Cpu686) != 0)
849 patt = alt_long_patt;
850 else
851 patt = f32_patt;
852 break;
853 case PROCESSOR_GENERIC64:
76bc74dc 854 patt = alt_long_patt;
ccc9c027 855 break;
4eed87de 856 }
ccc9c027
L		 857 }
858
76bc74dc
L		 859 if (patt == f32_patt)
860 {
861 /* If the padding is less than 15 bytes, we use the normal
862 ones. Otherwise, we use a jump instruction and adjust
863 its offset. */
864 if (count < 15)
865 memcpy (fragP->fr_literal + fragP->fr_fix,
866 patt[count - 1], count);
867 else
868 {
869 memcpy (fragP->fr_literal + fragP->fr_fix,
870 jump_31, count);
871 /* Adjust jump offset. */
872 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
873 }
874 }
875 else
876 {
877 /* Maximum length of an instruction is 15 byte. If the
878 padding is greater than 15 bytes and we don't use jump,
879 we have to break it into smaller pieces. */
880 int padding = count;
881 while (padding > 15)
882 {
883 padding -= 15;
884 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
885 patt [14], 15);
886 }
887
888 if (padding)
889 memcpy (fragP->fr_literal + fragP->fr_fix,
890 patt [padding - 1], padding);
891 }
ccc9c027 892 }
33fef721 893 fragP->fr_var = count;
252b5132
RH		 894}
895
252b5132 896static INLINE unsigned int
e3bb37b5 897mode_from_disp_size (unsigned int t)
252b5132 898{
3e73aa7c 899 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 900}
901
902static INLINE int
e3bb37b5 903fits_in_signed_byte (offsetT num)
252b5132
RH		 904{
905 return (num >= -128) && (num <= 127);
47926f60 906}
252b5132
RH		 907
908static INLINE int
e3bb37b5 909fits_in_unsigned_byte (offsetT num)
252b5132
RH		 910{
911 return (num & 0xff) == num;
47926f60 912}
252b5132
RH		 913
914static INLINE int
e3bb37b5 915fits_in_unsigned_word (offsetT num)
252b5132
RH		 916{
917 return (num & 0xffff) == num;
47926f60 918}
252b5132
RH		 919
920static INLINE int
e3bb37b5 921fits_in_signed_word (offsetT num)
252b5132
RH		 922{
923 return (-32768 <= num) && (num <= 32767);
47926f60 924}
2a962e6d 925
3e73aa7c 926static INLINE int
e3bb37b5 927fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 928{
929#ifndef BFD64
930 return 1;
931#else
932 return (!(((offsetT) -1 << 31) & num)
933 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
934#endif
935} /* fits_in_signed_long() */
2a962e6d 936
3e73aa7c 937static INLINE int
e3bb37b5 938fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 939{
940#ifndef BFD64
941 return 1;
942#else
943 return (num & (((offsetT) 2 << 31) - 1)) == num;
944#endif
945} /* fits_in_unsigned_long() */
252b5132 946
1509aa9a 947static unsigned int
e3bb37b5 948smallest_imm_type (offsetT num)
252b5132 949{
d32cad65 950 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 951 {
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
956 use that form. */
957 if (num == 1)
3e73aa7c 958 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 959 }
252b5132 960 return (fits_in_signed_byte (num)
3e73aa7c 961 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 962 : fits_in_unsigned_byte (num)
3e73aa7c 963 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 964 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 965 ? (Imm16 | Imm32 | Imm32S | Imm64)
966 : fits_in_signed_long (num)
967 ? (Imm32 | Imm32S | Imm64)
968 : fits_in_unsigned_long (num)
969 ? (Imm32 | Imm64)
970 : Imm64);
47926f60 971}
252b5132 972
847f7ad4 973static offsetT
e3bb37b5 974offset_in_range (offsetT val, int size)
847f7ad4 975{
508866be 976 addressT mask;
ba2adb93 977
847f7ad4
AM		 978 switch (size)
979 {
508866be
L		 980 case 1: mask = ((addressT) 1 << 8) - 1; break;
981 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 982 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 983#ifdef BFD64
984 case 8: mask = ((addressT) 2 << 63) - 1; break;
985#endif
47926f60 986 default: abort ();
847f7ad4
AM		 987 }
988
ba2adb93 989 /* If BFD64, sign extend val. */
3e73aa7c
JH		 990 if (!use_rela_relocations)
991 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
992 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 993
47926f60 994 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 995 {
996 char buf1[40], buf2[40];
997
998 sprint_value (buf1, val);
999 sprint_value (buf2, val & mask);
1000 as_warn (_("%s shortened to %s"), buf1, buf2);
1001 }
1002 return val & mask;
1003}
1004
252b5132
RH		 1005/* Returns 0 if attempting to add a prefix where one from the same
1006 class already exists, 1 if non rep/repne added, 2 if rep/repne
1007 added. */
1008static int
e3bb37b5 1009add_prefix (unsigned int prefix)
252b5132
RH		 1010{
1011 int ret = 1;
b1905489 1012 unsigned int q;
252b5132 1013
29b0f896
AM		 1014 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1015 && flag_code == CODE_64BIT)
b1905489 1016 {
161a04f6
L		 1017 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1018 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1019 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1020 ret = 0;
1021 q = REX_PREFIX;
1022 }
3e73aa7c 1023 else
b1905489
JB		 1024 {
1025 switch (prefix)
1026 {
1027 default:
1028 abort ();
1029
1030 case CS_PREFIX_OPCODE:
1031 case DS_PREFIX_OPCODE:
1032 case ES_PREFIX_OPCODE:
1033 case FS_PREFIX_OPCODE:
1034 case GS_PREFIX_OPCODE:
1035 case SS_PREFIX_OPCODE:
1036 q = SEG_PREFIX;
1037 break;
1038
1039 case REPNE_PREFIX_OPCODE:
1040 case REPE_PREFIX_OPCODE:
1041 ret = 2;
1042 /* fall thru */
1043 case LOCK_PREFIX_OPCODE:
1044 q = LOCKREP_PREFIX;
1045 break;
1046
1047 case FWAIT_OPCODE:
1048 q = WAIT_PREFIX;
1049 break;
1050
1051 case ADDR_PREFIX_OPCODE:
1052 q = ADDR_PREFIX;
1053 break;
1054
1055 case DATA_PREFIX_OPCODE:
1056 q = DATA_PREFIX;
1057 break;
1058 }
1059 if (i.prefix[q] != 0)
1060 ret = 0;
1061 }
252b5132 1062
b1905489 1063 if (ret)
252b5132 1064 {
b1905489
JB		 1065 if (!i.prefix[q])
1066 ++i.prefixes;
1067 i.prefix[q] |= prefix;
252b5132 1068 }
b1905489
JB		 1069 else
1070 as_bad (_("same type of prefix used twice"));
252b5132 1071
252b5132
RH		 1072 return ret;
1073}
1074
1075static void
e3bb37b5 1076set_code_flag (int value)
eecb386c 1077{
3e73aa7c
JH		 1078 flag_code = value;
1079 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1080 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1081 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1082 {
1083 as_bad (_("64bit mode not supported on this CPU."));
1084 }
1085 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1086 {
1087 as_bad (_("32bit mode not supported on this CPU."));
1088 }
eecb386c
AM		 1089 stackop_size = '\0';
1090}
1091
1092static void
e3bb37b5 1093set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1094{
3e73aa7c
JH		 1095 flag_code = new_code_flag;
1096 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1097 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1098 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1099}
1100
1101static void
e3bb37b5 1102set_intel_syntax (int syntax_flag)
252b5132
RH		 1103{
1104 /* Find out if register prefixing is specified. */
1105 int ask_naked_reg = 0;
1106
1107 SKIP_WHITESPACE ();
29b0f896 1108 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1109 {
1110 char *string = input_line_pointer;
1111 int e = get_symbol_end ();
1112
47926f60 1113 if (strcmp (string, "prefix") == 0)
252b5132 1114 ask_naked_reg = 1;
47926f60 1115 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1116 ask_naked_reg = -1;
1117 else
d0b47220 1118 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1119 *input_line_pointer = e;
1120 }
1121 demand_empty_rest_of_line ();
c3332e24 1122
252b5132
RH		 1123 intel_syntax = syntax_flag;
1124
1125 if (ask_naked_reg == 0)
f86103b7
AM		 1126 allow_naked_reg = (intel_syntax
1127 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1128 else
1129 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1130
e4a3b5a4 1131 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1132 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1133 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1134}
1135
e413e4e9 1136static void
e3bb37b5 1137set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1138{
47926f60 1139 SKIP_WHITESPACE ();
e413e4e9 1140
29b0f896 1141 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1142 {
1143 char *string = input_line_pointer;
1144 int e = get_symbol_end ();
9103f4f4 1145 unsigned int i;
e413e4e9 1146
9103f4f4 1147 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1148 {
1149 if (strcmp (string, cpu_arch[i].name) == 0)
1150 {
5c6af06e
JB		 1151 if (*string != '.')
1152 {
1153 cpu_arch_name = cpu_arch[i].name;
1154 cpu_sub_arch_name = NULL;
1155 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1156 | (flag_code == CODE_64BIT
1157 ? Cpu64 : CpuNo64));
ccc9c027 1158 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1159 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1160 if (!cpu_arch_tune_set)
1161 {
1162 cpu_arch_tune = cpu_arch_isa;
1163 cpu_arch_tune_flags = cpu_arch_isa_flags;
1164 }
5c6af06e
JB		 1165 break;
1166 }
1167 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1168 {
1169 cpu_sub_arch_name = cpu_arch[i].name;
1170 cpu_arch_flags |= cpu_arch[i].flags;
1171 }
1172 *input_line_pointer = e;
1173 demand_empty_rest_of_line ();
1174 return;
e413e4e9
AM		 1175 }
1176 }
9103f4f4 1177 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1178 as_bad (_("no such architecture: `%s'"), string);
1179
1180 *input_line_pointer = e;
1181 }
1182 else
1183 as_bad (_("missing cpu architecture"));
1184
fddf5b5b
AM		 1185 no_cond_jump_promotion = 0;
1186 if (*input_line_pointer == ','
29b0f896 1187 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1188 {
1189 char *string = ++input_line_pointer;
1190 int e = get_symbol_end ();
1191
1192 if (strcmp (string, "nojumps") == 0)
1193 no_cond_jump_promotion = 1;
1194 else if (strcmp (string, "jumps") == 0)
1195 ;
1196 else
1197 as_bad (_("no such architecture modifier: `%s'"), string);
1198
1199 *input_line_pointer = e;
1200 }
1201
e413e4e9
AM		 1202 demand_empty_rest_of_line ();
1203}
1204
b9d79e03
JH		 1205unsigned long
1206i386_mach ()
1207{
1208 if (!strcmp (default_arch, "x86_64"))
1209 return bfd_mach_x86_64;
1210 else if (!strcmp (default_arch, "i386"))
1211 return bfd_mach_i386_i386;
1212 else
1213 as_fatal (_("Unknown architecture"));
1214}
b9d79e03 1215\f
252b5132
RH		 1216void
1217md_begin ()
1218{
1219 const char *hash_err;
1220
47926f60 1221 /* Initialize op_hash hash table. */
252b5132
RH		 1222 op_hash = hash_new ();
1223
1224 {
29b0f896
AM		 1225 const template *optab;
1226 templates *core_optab;
252b5132 1227
47926f60
KH		 1228 /* Setup for loop. */
1229 optab = i386_optab;
252b5132
RH		 1230 core_optab = (templates *) xmalloc (sizeof (templates));
1231 core_optab->start = optab;
1232
1233 while (1)
1234 {
1235 ++optab;
1236 if (optab->name == NULL
1237 || strcmp (optab->name, (optab - 1)->name) != 0)
1238 {
1239 /* different name --> ship out current template list;
47926f60 1240 add to hash table; & begin anew. */
252b5132
RH		 1241 core_optab->end = optab;
1242 hash_err = hash_insert (op_hash,
1243 (optab - 1)->name,
1244 (PTR) core_optab);
1245 if (hash_err)
1246 {
252b5132
RH		 1247 as_fatal (_("Internal Error: Can't hash %s: %s"),
1248 (optab - 1)->name,
1249 hash_err);
1250 }
1251 if (optab->name == NULL)
1252 break;
1253 core_optab = (templates *) xmalloc (sizeof (templates));
1254 core_optab->start = optab;
1255 }
1256 }
1257 }
1258
47926f60 1259 /* Initialize reg_hash hash table. */
252b5132
RH		 1260 reg_hash = hash_new ();
1261 {
29b0f896 1262 const reg_entry *regtab;
c3fe08fa 1263 unsigned int regtab_size = i386_regtab_size;
252b5132 1264
c3fe08fa 1265 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1266 {
1267 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1268 if (hash_err)
3e73aa7c
JH		 1269 as_fatal (_("Internal Error: Can't hash %s: %s"),
1270 regtab->reg_name,
1271 hash_err);
252b5132
RH		 1272 }
1273 }
1274
47926f60 1275 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1276 {
29b0f896
AM		 1277 int c;
1278 char *p;
252b5132
RH		 1279
1280 for (c = 0; c < 256; c++)
1281 {
3882b010 1282 if (ISDIGIT (c))
252b5132
RH		 1283 {
1284 digit_chars[c] = c;
1285 mnemonic_chars[c] = c;
1286 register_chars[c] = c;
1287 operand_chars[c] = c;
1288 }
3882b010 1289 else if (ISLOWER (c))
252b5132
RH		 1290 {
1291 mnemonic_chars[c] = c;
1292 register_chars[c] = c;
1293 operand_chars[c] = c;
1294 }
3882b010 1295 else if (ISUPPER (c))
252b5132 1296 {
3882b010 1297 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1298 register_chars[c] = mnemonic_chars[c];
1299 operand_chars[c] = c;
1300 }
1301
3882b010 1302 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1303 identifier_chars[c] = c;
1304 else if (c >= 128)
1305 {
1306 identifier_chars[c] = c;
1307 operand_chars[c] = c;
1308 }
1309 }
1310
1311#ifdef LEX_AT
1312 identifier_chars['@'] = '@';
32137342
NC		 1313#endif
1314#ifdef LEX_QM
1315 identifier_chars['?'] = '?';
1316 operand_chars['?'] = '?';
252b5132 1317#endif
252b5132 1318 digit_chars['-'] = '-';
791fe849 1319 mnemonic_chars['-'] = '-';
0003779b 1320 mnemonic_chars['.'] = '.';
252b5132
RH		 1321 identifier_chars['_'] = '_';
1322 identifier_chars['.'] = '.';
1323
1324 for (p = operand_special_chars; *p != '\0'; p++)
1325 operand_chars[(unsigned char) *p] = *p;
1326 }
1327
1328#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1329 if (IS_ELF)
252b5132
RH		 1330 {
1331 record_alignment (text_section, 2);
1332 record_alignment (data_section, 2);
1333 record_alignment (bss_section, 2);
1334 }
1335#endif
a4447b93
RH		 1336
1337 if (flag_code == CODE_64BIT)
1338 {
1339 x86_dwarf2_return_column = 16;
1340 x86_cie_data_alignment = -8;
1341 }
1342 else
1343 {
1344 x86_dwarf2_return_column = 8;
1345 x86_cie_data_alignment = -4;
1346 }
252b5132
RH		 1347}
1348
1349void
e3bb37b5 1350i386_print_statistics (FILE *file)
252b5132
RH		 1351{
1352 hash_print_statistics (file, "i386 opcode", op_hash);
1353 hash_print_statistics (file, "i386 register", reg_hash);
1354}
1355\f
252b5132
RH		 1356#ifdef DEBUG386
1357
ce8a8b2f 1358/* Debugging routines for md_assemble. */
e3bb37b5
L		 1359static void pte (template *);
1360static void pt (unsigned int);
1361static void pe (expressionS *);
1362static void ps (symbolS *);
252b5132
RH		 1363
1364static void
e3bb37b5 1365pi (char *line, i386_insn *x)
252b5132 1366{
09f131f2 1367 unsigned int i;
252b5132
RH		 1368
1369 fprintf (stdout, "%s: template ", line);
1370 pte (&x->tm);
09f131f2
JH		 1371 fprintf (stdout, " address: base %s index %s scale %x\n",
1372 x->base_reg ? x->base_reg->reg_name : "none",
1373 x->index_reg ? x->index_reg->reg_name : "none",
1374 x->log2_scale_factor);
1375 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1376 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1377 fprintf (stdout, " sib: base %x index %x scale %x\n",
1378 x->sib.base, x->sib.index, x->sib.scale);
1379 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1380 (x->rex & REX_W) != 0,
1381 (x->rex & REX_R) != 0,
1382 (x->rex & REX_X) != 0,
1383 (x->rex & REX_B) != 0);
252b5132
RH		 1384 for (i = 0; i < x->operands; i++)
1385 {
1386 fprintf (stdout, " #%d: ", i + 1);
1387 pt (x->types[i]);
1388 fprintf (stdout, "\n");
1389 if (x->types[i]
3f4438ab 1390 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1391 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1392 if (x->types[i] & Imm)
520dc8e8 1393 pe (x->op[i].imms);
252b5132 1394 if (x->types[i] & Disp)
520dc8e8 1395 pe (x->op[i].disps);
252b5132
RH		 1396 }
1397}
1398
1399static void
e3bb37b5 1400pte (template *t)
252b5132 1401{
09f131f2 1402 unsigned int i;
252b5132 1403 fprintf (stdout, " %d operands ", t->operands);
47926f60 1404 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1405 if (t->extension_opcode != None)
1406 fprintf (stdout, "ext %x ", t->extension_opcode);
1407 if (t->opcode_modifier & D)
1408 fprintf (stdout, "D");
1409 if (t->opcode_modifier & W)
1410 fprintf (stdout, "W");
1411 fprintf (stdout, "\n");
1412 for (i = 0; i < t->operands; i++)
1413 {
1414 fprintf (stdout, " #%d type ", i + 1);
1415 pt (t->operand_types[i]);
1416 fprintf (stdout, "\n");
1417 }
1418}
1419
1420static void
e3bb37b5 1421pe (expressionS *e)
252b5132 1422{
24eab124 1423 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1426 if (e->X_add_symbol)
1427 {
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1431 }
1432 if (e->X_op_symbol)
1433 {
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1437 }
1438}
1439
1440static void
e3bb37b5 1441ps (symbolS *s)
252b5132
RH		 1442{
1443 fprintf (stdout, "%s type %s%s",
1444 S_GET_NAME (s),
1445 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1446 segment_name (S_GET_SEGMENT (s)));
1447}
1448
7b81dfbb 1449static struct type_name
252b5132
RH		 1450 {
1451 unsigned int mask;
1452 char *tname;
1453 }
7b81dfbb 1454const type_names[] =
252b5132
RH		 1455{
1456 { Reg8, "r8" },
1457 { Reg16, "r16" },
1458 { Reg32, "r32" },
09f131f2 1459 { Reg64, "r64" },
252b5132
RH		 1460 { Imm8, "i8" },
1461 { Imm8S, "i8s" },
1462 { Imm16, "i16" },
1463 { Imm32, "i32" },
09f131f2
JH		 1464 { Imm32S, "i32s" },
1465 { Imm64, "i64" },
252b5132
RH		 1466 { Imm1, "i1" },
1467 { BaseIndex, "BaseIndex" },
1468 { Disp8, "d8" },
1469 { Disp16, "d16" },
1470 { Disp32, "d32" },
09f131f2
JH		 1471 { Disp32S, "d32s" },
1472 { Disp64, "d64" },
252b5132
RH		 1473 { InOutPortReg, "InOutPortReg" },
1474 { ShiftCount, "ShiftCount" },
1475 { Control, "control reg" },
1476 { Test, "test reg" },
1477 { Debug, "debug reg" },
1478 { FloatReg, "FReg" },
1479 { FloatAcc, "FAcc" },
1480 { SReg2, "SReg2" },
1481 { SReg3, "SReg3" },
1482 { Acc, "Acc" },
1483 { JumpAbsolute, "Jump Absolute" },
1484 { RegMMX, "rMMX" },
3f4438ab 1485 { RegXMM, "rXMM" },
252b5132
RH		 1486 { EsSeg, "es" },
1487 { 0, "" }
1488};
1489
1490static void
1491pt (t)
1492 unsigned int t;
1493{
29b0f896 1494 const struct type_name *ty;
252b5132 1495
09f131f2
JH		 1496 for (ty = type_names; ty->mask; ty++)
1497 if (t & ty->mask)
1498 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1499 fflush (stdout);
1500}
1501
1502#endif /* DEBUG386 */
1503\f
252b5132 1504static bfd_reloc_code_real_type
3956db08 1505reloc (unsigned int size,
64e74474
AM		 1506 int pcrel,
1507 int sign,
1508 bfd_reloc_code_real_type other)
252b5132 1509{
47926f60 1510 if (other != NO_RELOC)
3956db08
JB		 1511 {
1512 reloc_howto_type *reloc;
1513
1514 if (size == 8)
1515 switch (other)
1516 {
64e74474
AM		 1517 case BFD_RELOC_X86_64_GOT32:
1518 return BFD_RELOC_X86_64_GOT64;
1519 break;
1520 case BFD_RELOC_X86_64_PLTOFF64:
1521 return BFD_RELOC_X86_64_PLTOFF64;
1522 break;
1523 case BFD_RELOC_X86_64_GOTPC32:
1524 other = BFD_RELOC_X86_64_GOTPC64;
1525 break;
1526 case BFD_RELOC_X86_64_GOTPCREL:
1527 other = BFD_RELOC_X86_64_GOTPCREL64;
1528 break;
1529 case BFD_RELOC_X86_64_TPOFF32:
1530 other = BFD_RELOC_X86_64_TPOFF64;
1531 break;
1532 case BFD_RELOC_X86_64_DTPOFF32:
1533 other = BFD_RELOC_X86_64_DTPOFF64;
1534 break;
1535 default:
1536 break;
3956db08 1537 }
e05278af
JB		 1538
1539 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1540 if (size == 4 && flag_code != CODE_64BIT)
1541 sign = -1;
1542
3956db08
JB		 1543 reloc = bfd_reloc_type_lookup (stdoutput, other);
1544 if (!reloc)
1545 as_bad (_("unknown relocation (%u)"), other);
1546 else if (size != bfd_get_reloc_size (reloc))
1547 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1548 bfd_get_reloc_size (reloc),
1549 size);
1550 else if (pcrel && !reloc->pc_relative)
1551 as_bad (_("non-pc-relative relocation for pc-relative field"));
1552 else if ((reloc->complain_on_overflow == complain_overflow_signed
1553 && !sign)
1554 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1555 && sign > 0))
3956db08
JB		 1556 as_bad (_("relocated field and relocation type differ in signedness"));
1557 else
1558 return other;
1559 return NO_RELOC;
1560 }
252b5132
RH		 1561
1562 if (pcrel)
1563 {
3e73aa7c 1564 if (!sign)
3956db08 1565 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1566 switch (size)
1567 {
1568 case 1: return BFD_RELOC_8_PCREL;
1569 case 2: return BFD_RELOC_16_PCREL;
1570 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1571 case 8: return BFD_RELOC_64_PCREL;
252b5132 1572 }
3956db08 1573 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1574 }
1575 else
1576 {
3956db08 1577 if (sign > 0)
e5cb08ac 1578 switch (size)
3e73aa7c
JH		 1579 {
1580 case 4: return BFD_RELOC_X86_64_32S;
1581 }
1582 else
1583 switch (size)
1584 {
1585 case 1: return BFD_RELOC_8;
1586 case 2: return BFD_RELOC_16;
1587 case 4: return BFD_RELOC_32;
1588 case 8: return BFD_RELOC_64;
1589 }
3956db08
JB		 1590 as_bad (_("cannot do %s %u byte relocation"),
1591 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1592 }
1593
bfb32b52 1594 abort ();
252b5132
RH		 1595 return BFD_RELOC_NONE;
1596}
1597
47926f60
KH		 1598/* Here we decide which fixups can be adjusted to make them relative to
1599 the beginning of the section instead of the symbol. Basically we need
1600 to make sure that the dynamic relocations are done correctly, so in
1601 some cases we force the original symbol to be used. */
1602
252b5132 1603int
e3bb37b5 1604tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1605{
6d249963 1606#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1607 if (!IS_ELF)
31312f95
AM		 1608 return 1;
1609
a161fe53
AM		 1610 /* Don't adjust pc-relative references to merge sections in 64-bit
1611 mode. */
1612 if (use_rela_relocations
1613 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1614 && fixP->fx_pcrel)
252b5132 1615 return 0;
31312f95 1616
8d01d9a9
AJ		 1617 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1618 and changed later by validate_fix. */
1619 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1620 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1621 return 0;
1622
ce8a8b2f 1623 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1624 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1625 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1626 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1627 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1628 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1637 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1638 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1639 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1640 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1641 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1642 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1643 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1644 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1645 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1646 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1648 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1650 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1651 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1652 return 0;
31312f95 1653#endif
252b5132
RH		 1654 return 1;
1655}
252b5132 1656
b4cac588 1657static int
e3bb37b5 1658intel_float_operand (const char *mnemonic)
252b5132 1659{
9306ca4a
JB		 1660 /* Note that the value returned is meaningful only for opcodes with (memory)
1661 operands, hence the code here is free to improperly handle opcodes that
1662 have no operands (for better performance and smaller code). */
1663
1664 if (mnemonic[0] != 'f')
1665 return 0; /* non-math */
1666
1667 switch (mnemonic[1])
1668 {
1669 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1670 the fs segment override prefix not currently handled because no
1671 call path can make opcodes without operands get here */
1672 case 'i':
1673 return 2 /* integer op */;
1674 case 'l':
1675 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1676 return 3; /* fldcw/fldenv */
1677 break;
1678 case 'n':
1679 if (mnemonic[2] != 'o' /* fnop */)
1680 return 3; /* non-waiting control op */
1681 break;
1682 case 'r':
1683 if (mnemonic[2] == 's')
1684 return 3; /* frstor/frstpm */
1685 break;
1686 case 's':
1687 if (mnemonic[2] == 'a')
1688 return 3; /* fsave */
1689 if (mnemonic[2] == 't')
1690 {
1691 switch (mnemonic[3])
1692 {
1693 case 'c': /* fstcw */
1694 case 'd': /* fstdw */
1695 case 'e': /* fstenv */
1696 case 's': /* fsts[gw] */
1697 return 3;
1698 }
1699 }
1700 break;
1701 case 'x':
1702 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1703 return 0; /* fxsave/fxrstor are not really math ops */
1704 break;
1705 }
252b5132 1706
9306ca4a 1707 return 1;
252b5132
RH		 1708}
1709
1710/* This is the guts of the machine-dependent assembler. LINE points to a
1711 machine dependent instruction. This function is supposed to emit
1712 the frags/bytes it assembles to. */
1713
1714void
1715md_assemble (line)
1716 char *line;
1717{
252b5132 1718 int j;
252b5132
RH		 1719 char mnemonic[MAX_MNEM_SIZE];
1720
47926f60 1721 /* Initialize globals. */
252b5132
RH		 1722 memset (&i, '\0', sizeof (i));
1723 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1724 i.reloc[j] = NO_RELOC;
252b5132
RH		 1725 memset (disp_expressions, '\0', sizeof (disp_expressions));
1726 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1727 save_stack_p = save_stack;
252b5132
RH		 1728
1729 /* First parse an instruction mnemonic & call i386_operand for the operands.
1730 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1731 start of a (possibly prefixed) mnemonic. */
252b5132 1732
29b0f896
AM		 1733 line = parse_insn (line, mnemonic);
1734 if (line == NULL)
1735 return;
252b5132 1736
29b0f896
AM		 1737 line = parse_operands (line, mnemonic);
1738 if (line == NULL)
1739 return;
252b5132 1740
4eed87de 1741 /* The order of the immediates should be reversed
050dfa73 1742 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1743 if ((i.imm_operands == 2)
1744 && ((strcmp (mnemonic, "extrq") == 0)
1745 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1746 {
4eed87de
AM		 1747 swap_2_operands (0, 1);
1748 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1749 have to be reversed even though they have two immediate operands.
1750 */
1751 if (intel_syntax)
1752 swap_operands ();
1753 }
1754
29b0f896
AM		 1755 /* Now we've parsed the mnemonic into a set of templates, and have the
1756 operands at hand. */
1757
1758 /* All intel opcodes have reversed operands except for "bound" and
1759 "enter". We also don't reverse intersegment "jmp" and "call"
1760 instructions with 2 immediate operands so that the immediate segment
050dfa73 1761 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1762 if (intel_syntax
1763 && i.operands > 1
29b0f896 1764 && (strcmp (mnemonic, "bound") != 0)
30123838 1765 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1766 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1767 swap_operands ();
1768
1769 if (i.imm_operands)
1770 optimize_imm ();
1771
b300c311
L		 1772 /* Don't optimize displacement for movabs since it only takes 64bit
1773 displacement. */
1774 if (i.disp_operands
1775 && (flag_code != CODE_64BIT
1776 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1777 optimize_disp ();
1778
1779 /* Next, we find a template that matches the given insn,
1780 making sure the overlap of the given operands types is consistent
1781 with the template operand types. */
252b5132 1782
29b0f896
AM		 1783 if (!match_template ())
1784 return;
252b5132 1785
cd61ebfe
AM		 1786 if (intel_syntax)
1787 {
1788 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1789 if (SYSV386_COMPAT
1790 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1791 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1792
1793 /* Zap movzx and movsx suffix. The suffix may have been set from
1794 "word ptr" or "byte ptr" on the source operand, but we'll use
1795 the suffix later to choose the destination register. */
1796 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1797 {
1798 if (i.reg_operands < 2
1799 && !i.suffix
1800 && (~i.tm.opcode_modifier
1801 & (No_bSuf
1802 | No_wSuf
1803 | No_lSuf
1804 | No_sSuf
1805 | No_xSuf
1806 | No_qSuf)))
1807 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1808
1809 i.suffix = 0;
1810 }
cd61ebfe 1811 }
24eab124 1812
29b0f896
AM		 1813 if (i.tm.opcode_modifier & FWait)
1814 if (!add_prefix (FWAIT_OPCODE))
1815 return;
252b5132 1816
29b0f896
AM		 1817 /* Check string instruction segment overrides. */
1818 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1819 {
1820 if (!check_string ())
5dd0794d 1821 return;
29b0f896 1822 }
5dd0794d 1823
29b0f896
AM		 1824 if (!process_suffix ())
1825 return;
e413e4e9 1826
29b0f896
AM		 1827 /* Make still unresolved immediate matches conform to size of immediate
1828 given in i.suffix. */
1829 if (!finalize_imm ())
1830 return;
252b5132 1831
29b0f896
AM		 1832 if (i.types[0] & Imm1)
1833 i.imm_operands = 0; /* kludge for shift insns. */
1834 if (i.types[0] & ImplicitRegister)
1835 i.reg_operands--;
1836 if (i.types[1] & ImplicitRegister)
1837 i.reg_operands--;
1838 if (i.types[2] & ImplicitRegister)
1839 i.reg_operands--;
252b5132 1840
29b0f896
AM		 1841 if (i.tm.opcode_modifier & ImmExt)
1842 {
02fc3089
L		 1843 expressionS *exp;
1844
b7d9ef37 1845 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1846 {
b7d9ef37 1847 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1848 operands with an opcode suffix which is coded in the same
1849 place as an 8-bit immediate field would be. Here we check
1850 those operands and remove them afterwards. */
1851 unsigned int x;
1852
a4622f40 1853 for (x = 0; x < i.operands; x++)
ca164297 1854 if (i.op[x].regs->reg_num != x)
a540244d
L		 1855 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1856 register_prefix,
1857 i.op[x].regs->reg_name,
1858 x + 1,
1859 i.tm.name);
ca164297
L		 1860 i.operands = 0;
1861 }
1862
29b0f896
AM		 1863 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1864 opcode suffix which is coded in the same place as an 8-bit
1865 immediate field would be. Here we fake an 8-bit immediate
1866 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1867
29b0f896 1868 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1869
29b0f896
AM		 1870 exp = &im_expressions[i.imm_operands++];
1871 i.op[i.operands].imms = exp;
1872 i.types[i.operands++] = Imm8;
1873 exp->X_op = O_constant;
1874 exp->X_add_number = i.tm.extension_opcode;
1875 i.tm.extension_opcode = None;
1876 }
252b5132 1877
29b0f896
AM		 1878 /* For insns with operands there are more diddles to do to the opcode. */
1879 if (i.operands)
1880 {
1881 if (!process_operands ())
1882 return;
1883 }
1884 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1885 {
1886 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1887 as_warn (_("translating to `%sp'"), i.tm.name);
1888 }
252b5132 1889
29b0f896
AM		 1890 /* Handle conversion of 'int $3' --> special int3 insn. */
1891 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1892 {
1893 i.tm.base_opcode = INT3_OPCODE;
1894 i.imm_operands = 0;
1895 }
252b5132 1896
29b0f896
AM		 1897 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1898 && i.op[0].disps->X_op == O_constant)
1899 {
1900 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1901 the absolute address given by the constant. Since ix86 jumps and
1902 calls are pc relative, we need to generate a reloc. */
1903 i.op[0].disps->X_add_symbol = &abs_symbol;
1904 i.op[0].disps->X_op = O_symbol;
1905 }
252b5132 1906
29b0f896 1907 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1908 i.rex |= REX_W;
252b5132 1909
29b0f896
AM		 1910 /* For 8 bit registers we need an empty rex prefix. Also if the
1911 instruction already has a prefix, we need to convert old
1912 registers to new ones. */
773f551c 1913
29b0f896
AM		 1914 if (((i.types[0] & Reg8) != 0
1915 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1916 || ((i.types[1] & Reg8) != 0
1917 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1918 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1919 && i.rex != 0))
1920 {
1921 int x;
726c5dcd 1922
29b0f896
AM		 1923 i.rex |= REX_OPCODE;
1924 for (x = 0; x < 2; x++)
1925 {
1926 /* Look for 8 bit operand that uses old registers. */
1927 if ((i.types[x] & Reg8) != 0
1928 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1929 {
29b0f896
AM		 1930 /* In case it is "hi" register, give up. */
1931 if (i.op[x].regs->reg_num > 3)
a540244d 1932 as_bad (_("can't encode register '%s%s' in an "
4eed87de 1933 "instruction requiring REX prefix."),
a540244d 1934 register_prefix, i.op[x].regs->reg_name);
773f551c 1935
29b0f896
AM		 1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1939
1940 i.op[x].regs = i.op[x].regs + 8;
773f551c 1941 }
29b0f896
AM		 1942 }
1943 }
773f551c 1944
29b0f896
AM		 1945 if (i.rex != 0)
1946 add_prefix (REX_OPCODE | i.rex);
1947
1948 /* We are ready to output the insn. */
1949 output_insn ();
1950}
1951
1952static char *
e3bb37b5 1953parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1954{
1955 char *l = line;
1956 char *token_start = l;
1957 char *mnem_p;
5c6af06e
JB		 1958 int supported;
1959 const template *t;
29b0f896
AM		 1960
1961 /* Non-zero if we found a prefix only acceptable with string insns. */
1962 const char *expecting_string_instruction = NULL;
45288df1 1963
29b0f896
AM		 1964 while (1)
1965 {
1966 mnem_p = mnemonic;
1967 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1968 {
1969 mnem_p++;
1970 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1971 {
29b0f896
AM		 1972 as_bad (_("no such instruction: `%s'"), token_start);
1973 return NULL;
1974 }
1975 l++;
1976 }
1977 if (!is_space_char (*l)
1978 && *l != END_OF_INSN
e44823cf
JB		 1979 && (intel_syntax
1980 || (*l != PREFIX_SEPARATOR
1981 && *l != ',')))
29b0f896
AM		 1982 {
1983 as_bad (_("invalid character %s in mnemonic"),
1984 output_invalid (*l));
1985 return NULL;
1986 }
1987 if (token_start == l)
1988 {
e44823cf 1989 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1990 as_bad (_("expecting prefix; got nothing"));
1991 else
1992 as_bad (_("expecting mnemonic; got nothing"));
1993 return NULL;
1994 }
45288df1 1995
29b0f896
AM		 1996 /* Look up instruction (or prefix) via hash table. */
1997 current_templates = hash_find (op_hash, mnemonic);
47926f60 1998
29b0f896
AM		 1999 if (*l != END_OF_INSN
2000 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2001 && current_templates
2002 && (current_templates->start->opcode_modifier & IsPrefix))
2003 {
2dd88dca
JB		 2004 if (current_templates->start->cpu_flags
2005 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2006 {
2007 as_bad ((flag_code != CODE_64BIT
2008 ? _("`%s' is only supported in 64-bit mode")
2009 : _("`%s' is not supported in 64-bit mode")),
2010 current_templates->start->name);
2011 return NULL;
2012 }
29b0f896
AM		 2013 /* If we are in 16-bit mode, do not allow addr16 or data16.
2014 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2015 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2016 && flag_code != CODE_64BIT
2017 && (((current_templates->start->opcode_modifier & Size32) != 0)
2018 ^ (flag_code == CODE_16BIT)))
2019 {
2020 as_bad (_("redundant %s prefix"),
2021 current_templates->start->name);
2022 return NULL;
45288df1 2023 }
29b0f896
AM		 2024 /* Add prefix, checking for repeated prefixes. */
2025 switch (add_prefix (current_templates->start->base_opcode))
2026 {
2027 case 0:
2028 return NULL;
2029 case 2:
2030 expecting_string_instruction = current_templates->start->name;
2031 break;
2032 }
2033 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2034 token_start = ++l;
2035 }
2036 else
2037 break;
2038 }
45288df1 2039
29b0f896
AM		 2040 if (!current_templates)
2041 {
2042 /* See if we can get a match by trimming off a suffix. */
2043 switch (mnem_p[-1])
2044 {
2045 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2046 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2047 i.suffix = SHORT_MNEM_SUFFIX;
2048 else
29b0f896
AM		 2049 case BYTE_MNEM_SUFFIX:
2050 case QWORD_MNEM_SUFFIX:
2051 i.suffix = mnem_p[-1];
2052 mnem_p[-1] = '\0';
2053 current_templates = hash_find (op_hash, mnemonic);
2054 break;
2055 case SHORT_MNEM_SUFFIX:
2056 case LONG_MNEM_SUFFIX:
2057 if (!intel_syntax)
2058 {
2059 i.suffix = mnem_p[-1];
2060 mnem_p[-1] = '\0';
2061 current_templates = hash_find (op_hash, mnemonic);
2062 }
2063 break;
252b5132 2064
29b0f896
AM		 2065 /* Intel Syntax. */
2066 case 'd':
2067 if (intel_syntax)
2068 {
9306ca4a 2069 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2070 i.suffix = SHORT_MNEM_SUFFIX;
2071 else
2072 i.suffix = LONG_MNEM_SUFFIX;
2073 mnem_p[-1] = '\0';
2074 current_templates = hash_find (op_hash, mnemonic);
2075 }
2076 break;
2077 }
2078 if (!current_templates)
2079 {
2080 as_bad (_("no such instruction: `%s'"), token_start);
2081 return NULL;
2082 }
2083 }
252b5132 2084
29b0f896
AM		 2085 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2086 {
2087 /* Check for a branch hint. We allow ",pt" and ",pn" for
2088 predict taken and predict not taken respectively.
2089 I'm not sure that branch hints actually do anything on loop
2090 and jcxz insns (JumpByte) for current Pentium4 chips. They
2091 may work in the future and it doesn't hurt to accept them
2092 now. */
2093 if (l[0] == ',' && l[1] == 'p')
2094 {
2095 if (l[2] == 't')
2096 {
2097 if (!add_prefix (DS_PREFIX_OPCODE))
2098 return NULL;
2099 l += 3;
2100 }
2101 else if (l[2] == 'n')
2102 {
2103 if (!add_prefix (CS_PREFIX_OPCODE))
2104 return NULL;
2105 l += 3;
2106 }
2107 }
2108 }
2109 /* Any other comma loses. */
2110 if (*l == ',')
2111 {
2112 as_bad (_("invalid character %s in mnemonic"),
2113 output_invalid (*l));
2114 return NULL;
2115 }
252b5132 2116
29b0f896 2117 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2118 supported = 0;
2119 for (t = current_templates->start; t < current_templates->end; ++t)
2120 {
2121 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2122 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2123 supported |= 1;
5c6af06e 2124 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2125 supported |= 2;
5c6af06e
JB		 2126 }
2127 if (!(supported & 2))
2128 {
2129 as_bad (flag_code == CODE_64BIT
2130 ? _("`%s' is not supported in 64-bit mode")
2131 : _("`%s' is only supported in 64-bit mode"),
2132 current_templates->start->name);
2133 return NULL;
2134 }
2135 if (!(supported & 1))
29b0f896 2136 {
5c6af06e
JB		 2137 as_warn (_("`%s' is not supported on `%s%s'"),
2138 current_templates->start->name,
2139 cpu_arch_name,
2140 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2141 }
2142 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2143 {
2144 as_warn (_("use .code16 to ensure correct addressing mode"));
2145 }
252b5132 2146
29b0f896 2147 /* Check for rep/repne without a string instruction. */
f41bbced 2148 if (expecting_string_instruction)
29b0f896 2149 {
f41bbced
JB		 2150 static templates override;
2151
2152 for (t = current_templates->start; t < current_templates->end; ++t)
2153 if (t->opcode_modifier & IsString)
2154 break;
2155 if (t >= current_templates->end)
2156 {
2157 as_bad (_("expecting string instruction after `%s'"),
64e74474 2158 expecting_string_instruction);
f41bbced
JB		 2159 return NULL;
2160 }
2161 for (override.start = t; t < current_templates->end; ++t)
2162 if (!(t->opcode_modifier & IsString))
2163 break;
2164 override.end = t;
2165 current_templates = &override;
29b0f896 2166 }
252b5132 2167
29b0f896
AM		 2168 return l;
2169}
252b5132 2170
29b0f896 2171static char *
e3bb37b5 2172parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2173{
2174 char *token_start;
3138f287 2175
29b0f896
AM		 2176 /* 1 if operand is pending after ','. */
2177 unsigned int expecting_operand = 0;
252b5132 2178
29b0f896
AM		 2179 /* Non-zero if operand parens not balanced. */
2180 unsigned int paren_not_balanced;
2181
2182 while (*l != END_OF_INSN)
2183 {
2184 /* Skip optional white space before operand. */
2185 if (is_space_char (*l))
2186 ++l;
2187 if (!is_operand_char (*l) && *l != END_OF_INSN)
2188 {
2189 as_bad (_("invalid character %s before operand %d"),
2190 output_invalid (*l),
2191 i.operands + 1);
2192 return NULL;
2193 }
2194 token_start = l; /* after white space */
2195 paren_not_balanced = 0;
2196 while (paren_not_balanced || *l != ',')
2197 {
2198 if (*l == END_OF_INSN)
2199 {
2200 if (paren_not_balanced)
2201 {
2202 if (!intel_syntax)
2203 as_bad (_("unbalanced parenthesis in operand %d."),
2204 i.operands + 1);
2205 else
2206 as_bad (_("unbalanced brackets in operand %d."),
2207 i.operands + 1);
2208 return NULL;
2209 }
2210 else
2211 break; /* we are done */
2212 }
2213 else if (!is_operand_char (*l) && !is_space_char (*l))
2214 {
2215 as_bad (_("invalid character %s in operand %d"),
2216 output_invalid (*l),
2217 i.operands + 1);
2218 return NULL;
2219 }
2220 if (!intel_syntax)
2221 {
2222 if (*l == '(')
2223 ++paren_not_balanced;
2224 if (*l == ')')
2225 --paren_not_balanced;
2226 }
2227 else
2228 {
2229 if (*l == '[')
2230 ++paren_not_balanced;
2231 if (*l == ']')
2232 --paren_not_balanced;
2233 }
2234 l++;
2235 }
2236 if (l != token_start)
2237 { /* Yes, we've read in another operand. */
2238 unsigned int operand_ok;
2239 this_operand = i.operands++;
2240 if (i.operands > MAX_OPERANDS)
2241 {
2242 as_bad (_("spurious operands; (%d operands/instruction max)"),
2243 MAX_OPERANDS);
2244 return NULL;
2245 }
2246 /* Now parse operand adding info to 'i' as we go along. */
2247 END_STRING_AND_SAVE (l);
2248
2249 if (intel_syntax)
2250 operand_ok =
2251 i386_intel_operand (token_start,
2252 intel_float_operand (mnemonic));
2253 else
2254 operand_ok = i386_operand (token_start);
2255
2256 RESTORE_END_STRING (l);
2257 if (!operand_ok)
2258 return NULL;
2259 }
2260 else
2261 {
2262 if (expecting_operand)
2263 {
2264 expecting_operand_after_comma:
2265 as_bad (_("expecting operand after ','; got nothing"));
2266 return NULL;
2267 }
2268 if (*l == ',')
2269 {
2270 as_bad (_("expecting operand before ','; got nothing"));
2271 return NULL;
2272 }
2273 }
7f3f1ea2 2274
29b0f896
AM		 2275 /* Now *l must be either ',' or END_OF_INSN. */
2276 if (*l == ',')
2277 {
2278 if (*++l == END_OF_INSN)
2279 {
2280 /* Just skip it, if it's \n complain. */
2281 goto expecting_operand_after_comma;
2282 }
2283 expecting_operand = 1;
2284 }
2285 }
2286 return l;
2287}
7f3f1ea2 2288
050dfa73 2289static void
4d456e3d 2290swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2291{
2292 union i386_op temp_op;
2293 unsigned int temp_type;
2294 enum bfd_reloc_code_real temp_reloc;
4eed87de 2295
050dfa73
MM		 2296 temp_type = i.types[xchg2];
2297 i.types[xchg2] = i.types[xchg1];
2298 i.types[xchg1] = temp_type;
2299 temp_op = i.op[xchg2];
2300 i.op[xchg2] = i.op[xchg1];
2301 i.op[xchg1] = temp_op;
2302 temp_reloc = i.reloc[xchg2];
2303 i.reloc[xchg2] = i.reloc[xchg1];
2304 i.reloc[xchg1] = temp_reloc;
2305}
2306
29b0f896 2307static void
e3bb37b5 2308swap_operands (void)
29b0f896 2309{
b7c61d9a 2310 switch (i.operands)
050dfa73 2311 {
b7c61d9a 2312 case 4:
4d456e3d 2313 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2314 case 3:
2315 case 2:
4d456e3d 2316 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2317 break;
2318 default:
2319 abort ();
29b0f896 2320 }
29b0f896
AM		 2321
2322 if (i.mem_operands == 2)
2323 {
2324 const seg_entry *temp_seg;
2325 temp_seg = i.seg[0];
2326 i.seg[0] = i.seg[1];
2327 i.seg[1] = temp_seg;
2328 }
2329}
252b5132 2330
29b0f896
AM		 2331/* Try to ensure constant immediates are represented in the smallest
2332 opcode possible. */
2333static void
e3bb37b5 2334optimize_imm (void)
29b0f896
AM		 2335{
2336 char guess_suffix = 0;
2337 int op;
252b5132 2338
29b0f896
AM		 2339 if (i.suffix)
2340 guess_suffix = i.suffix;
2341 else if (i.reg_operands)
2342 {
2343 /* Figure out a suffix from the last register operand specified.
2344 We can't do this properly yet, ie. excluding InOutPortReg,
2345 but the following works for instructions with immediates.
2346 In any case, we can't set i.suffix yet. */
2347 for (op = i.operands; --op >= 0;)
2348 if (i.types[op] & Reg)
252b5132 2349 {
29b0f896
AM		 2350 if (i.types[op] & Reg8)
2351 guess_suffix = BYTE_MNEM_SUFFIX;
2352 else if (i.types[op] & Reg16)
2353 guess_suffix = WORD_MNEM_SUFFIX;
2354 else if (i.types[op] & Reg32)
2355 guess_suffix = LONG_MNEM_SUFFIX;
2356 else if (i.types[op] & Reg64)
2357 guess_suffix = QWORD_MNEM_SUFFIX;
2358 break;
252b5132 2359 }
29b0f896
AM		 2360 }
2361 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2362 guess_suffix = WORD_MNEM_SUFFIX;
2363
2364 for (op = i.operands; --op >= 0;)
2365 if (i.types[op] & Imm)
2366 {
2367 switch (i.op[op].imms->X_op)
252b5132 2368 {
29b0f896
AM		 2369 case O_constant:
2370 /* If a suffix is given, this operand may be shortened. */
2371 switch (guess_suffix)
252b5132 2372 {
29b0f896
AM		 2373 case LONG_MNEM_SUFFIX:
2374 i.types[op] |= Imm32 | Imm64;
2375 break;
2376 case WORD_MNEM_SUFFIX:
2377 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2378 break;
2379 case BYTE_MNEM_SUFFIX:
2380 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2381 break;
252b5132 2382 }
252b5132 2383
29b0f896
AM		 2384 /* If this operand is at most 16 bits, convert it
2385 to a signed 16 bit number before trying to see
2386 whether it will fit in an even smaller size.
2387 This allows a 16-bit operand such as $0xffe0 to
2388 be recognised as within Imm8S range. */
2389 if ((i.types[op] & Imm16)
2390 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2391 {
29b0f896
AM		 2392 i.op[op].imms->X_add_number =
2393 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2394 }
2395 if ((i.types[op] & Imm32)
2396 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2397 == 0))
2398 {
2399 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2400 ^ ((offsetT) 1 << 31))
2401 - ((offsetT) 1 << 31));
2402 }
2403 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2404
29b0f896
AM		 2405 /* We must avoid matching of Imm32 templates when 64bit
2406 only immediate is available. */
2407 if (guess_suffix == QWORD_MNEM_SUFFIX)
2408 i.types[op] &= ~Imm32;
2409 break;
252b5132 2410
29b0f896
AM		 2411 case O_absent:
2412 case O_register:
2413 abort ();
2414
2415 /* Symbols and expressions. */
2416 default:
9cd96992
JB		 2417 /* Convert symbolic operand to proper sizes for matching, but don't
2418 prevent matching a set of insns that only supports sizes other
2419 than those matching the insn suffix. */
2420 {
2421 unsigned int mask, allowed = 0;
2422 const template *t;
2423
4eed87de
AM		 2424 for (t = current_templates->start;
2425 t < current_templates->end;
2426 ++t)
2427 allowed |= t->operand_types[op];
9cd96992
JB		 2428 switch (guess_suffix)
2429 {
2430 case QWORD_MNEM_SUFFIX:
2431 mask = Imm64 | Imm32S;
2432 break;
2433 case LONG_MNEM_SUFFIX:
2434 mask = Imm32;
2435 break;
2436 case WORD_MNEM_SUFFIX:
2437 mask = Imm16;
2438 break;
2439 case BYTE_MNEM_SUFFIX:
2440 mask = Imm8;
2441 break;
2442 default:
2443 mask = 0;
2444 break;
2445 }
64e74474
AM		 2446 if (mask & allowed)
2447 i.types[op] &= mask;
9cd96992 2448 }
29b0f896 2449 break;
252b5132 2450 }
29b0f896
AM		 2451 }
2452}
47926f60 2453
29b0f896
AM		 2454/* Try to use the smallest displacement type too. */
2455static void
e3bb37b5 2456optimize_disp (void)
29b0f896
AM		 2457{
2458 int op;
3e73aa7c 2459
29b0f896 2460 for (op = i.operands; --op >= 0;)
b300c311 2461 if (i.types[op] & Disp)
252b5132 2462 {
b300c311 2463 if (i.op[op].disps->X_op == O_constant)
252b5132 2464 {
b300c311 2465 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2466
b300c311
L		 2467 if ((i.types[op] & Disp16)
2468 && (disp & ~(offsetT) 0xffff) == 0)
2469 {
2470 /* If this operand is at most 16 bits, convert
2471 to a signed 16 bit number and don't use 64bit
2472 displacement. */
2473 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2474 i.types[op] &= ~Disp64;
2475 }
2476 if ((i.types[op] & Disp32)
2477 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2478 {
2479 /* If this operand is at most 32 bits, convert
2480 to a signed 32 bit number and don't use 64bit
2481 displacement. */
2482 disp &= (((offsetT) 2 << 31) - 1);
2483 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2484 i.types[op] &= ~Disp64;
2485 }
2486 if (!disp && (i.types[op] & BaseIndex))
2487 {
2488 i.types[op] &= ~Disp;
2489 i.op[op].disps = 0;
2490 i.disp_operands--;
2491 }
2492 else if (flag_code == CODE_64BIT)
2493 {
2494 if (fits_in_signed_long (disp))
28a9d8f5
L		 2495 {
2496 i.types[op] &= ~Disp64;
2497 i.types[op] |= Disp32S;
2498 }
b300c311
L		 2499 if (fits_in_unsigned_long (disp))
2500 i.types[op] |= Disp32;
2501 }
2502 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2503 && fits_in_signed_byte (disp))
2504 i.types[op] |= Disp8;
252b5132 2505 }
67a4f2b7
AO		 2506 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2507 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2508 {
2509 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2510 i.op[op].disps, 0, i.reloc[op]);
2511 i.types[op] &= ~Disp;
2512 }
2513 else
b300c311
L		 2514 /* We only support 64bit displacement on constants. */
2515 i.types[op] &= ~Disp64;
252b5132 2516 }
29b0f896
AM		 2517}
2518
2519static int
e3bb37b5 2520match_template (void)
29b0f896
AM		 2521{
2522 /* Points to template once we've found it. */
2523 const template *t;
f48ff2ae 2524 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2525 unsigned int found_reverse_match;
2526 int suffix_check;
f48ff2ae 2527 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2528 int addr_prefix_disp;
a5c311ca 2529 unsigned int j;
29b0f896 2530
f48ff2ae
L		 2531#if MAX_OPERANDS != 4
2532# error "MAX_OPERANDS must be 4."
2533#endif
2534
29b0f896
AM		 2535#define MATCH(overlap, given, template) \
2536 ((overlap & ~JumpAbsolute) \
2537 && (((given) & (BaseIndex | JumpAbsolute)) \
2538 == ((overlap) & (BaseIndex | JumpAbsolute))))
2539
2540 /* If given types r0 and r1 are registers they must be of the same type
2541 unless the expected operand type register overlap is null.
2542 Note that Acc in a template matches every size of reg. */
2543#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2544 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2545 || ((g0) & Reg) == ((g1) & Reg) \
2546 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2547
2548 overlap0 = 0;
2549 overlap1 = 0;
2550 overlap2 = 0;
f48ff2ae 2551 overlap3 = 0;
29b0f896 2552 found_reverse_match = 0;
a5c311ca
L		 2553 for (j = 0; j < MAX_OPERANDS; j++)
2554 operand_types [j] = 0;
539e75ad 2555 addr_prefix_disp = -1;
29b0f896
AM		 2556 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2557 ? No_bSuf
2558 : (i.suffix == WORD_MNEM_SUFFIX
2559 ? No_wSuf
2560 : (i.suffix == SHORT_MNEM_SUFFIX
2561 ? No_sSuf
2562 : (i.suffix == LONG_MNEM_SUFFIX
2563 ? No_lSuf
2564 : (i.suffix == QWORD_MNEM_SUFFIX
2565 ? No_qSuf
2566 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2567 ? No_xSuf : 0))))));
2568
45aa61fe 2569 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2570 {
539e75ad
L		 2571 addr_prefix_disp = -1;
2572
29b0f896
AM		 2573 /* Must have right number of operands. */
2574 if (i.operands != t->operands)
2575 continue;
2576
20592a94 2577 /* Check the suffix, except for some instructions in intel mode. */
29b0f896
AM		 2578 if ((t->opcode_modifier & suffix_check)
2579 && !(intel_syntax
9306ca4a 2580 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2581 continue;
2582
a5c311ca
L		 2583 for (j = 0; j < MAX_OPERANDS; j++)
2584 operand_types [j] = t->operand_types [j];
539e75ad 2585
45aa61fe
AM		 2586 /* In general, don't allow 64-bit operands in 32-bit mode. */
2587 if (i.suffix == QWORD_MNEM_SUFFIX
2588 && flag_code != CODE_64BIT
2589 && (intel_syntax
2590 ? (!(t->opcode_modifier & IgnoreSize)
2591 && !intel_float_operand (t->name))
2592 : intel_float_operand (t->name) != 2)
539e75ad
L		 2593 && (!(operand_types[0] & (RegMMX | RegXMM))
2594 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2595 && (t->base_opcode != 0x0fc7
2596 || t->extension_opcode != 1 /* cmpxchg8b */))
2597 continue;
2598
29b0f896
AM		 2599 /* Do not verify operands when there are none. */
2600 else if (!t->operands)
2601 {
2602 if (t->cpu_flags & ~cpu_arch_flags)
2603 continue;
2604 /* We've found a match; break out of loop. */
2605 break;
2606 }
252b5132 2607
539e75ad
L		 2608 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2609 into Disp32/Disp16/Disp32 operand. */
2610 if (i.prefix[ADDR_PREFIX] != 0)
2611 {
a5c311ca 2612 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2613
2614 switch (flag_code)
2615 {
2616 case CODE_16BIT:
2617 DispOn = Disp32;
2618 DispOff = Disp16;
2619 break;
2620 case CODE_32BIT:
2621 DispOn = Disp16;
2622 DispOff = Disp32;
2623 break;
2624 case CODE_64BIT:
2625 DispOn = Disp32;
2626 DispOff = Disp64;
2627 break;
2628 }
2629
f48ff2ae 2630 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2631 {
2632 /* There should be only one Disp operand. */
2633 if ((operand_types[j] & DispOff))
2634 {
2635 addr_prefix_disp = j;
2636 operand_types[j] |= DispOn;
2637 operand_types[j] &= ~DispOff;
2638 break;
2639 }
2640 }
2641 }
2642
2643 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2644 switch (t->operands)
2645 {
2646 case 1:
539e75ad 2647 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2648 continue;
2649 break;
2650 case 2:
8b38ad71
L		 2651 /* xchg %eax, %eax is a special case. It is an aliase for nop
2652 only in 32bit mode and we can use opcode 0x90. In 64bit
2653 mode, we can't use 0x90 for xchg %eax, %eax since it should
2654 zero-extend %eax to %rax. */
2655 if (flag_code == CODE_64BIT
2656 && t->base_opcode == 0x90
2657 && i.types [0] == (Acc | Reg32)
2658 && i.types [1] == (Acc | Reg32))
2659 continue;
29b0f896 2660 case 3:
f48ff2ae 2661 case 4:
539e75ad
L		 2662 overlap1 = i.types[1] & operand_types[1];
2663 if (!MATCH (overlap0, i.types[0], operand_types[0])
2664 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2665 /* monitor in SSE3 is a very special case. The first
708587a4 2666 register and the second register may have different
381d071f 2667 sizes. The same applies to crc32 in SSE4.2. */
cb712a9e
L		 2668 || !((t->base_opcode == 0x0f01
2669 && t->extension_opcode == 0xc8)
381d071f 2670 || t->base_opcode == 0xf20f38f1
cb712a9e 2671 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2672 operand_types[0],
cb712a9e 2673 overlap1, i.types[1],
539e75ad 2674 operand_types[1])))
29b0f896
AM		 2675 {
2676 /* Check if other direction is valid ... */
2677 if ((t->opcode_modifier & (D | FloatD)) == 0)
2678 continue;
2679
2680 /* Try reversing direction of operands. */
539e75ad
L		 2681 overlap0 = i.types[0] & operand_types[1];
2682 overlap1 = i.types[1] & operand_types[0];
2683 if (!MATCH (overlap0, i.types[0], operand_types[1])
2684 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2685 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2686 operand_types[1],
29b0f896 2687 overlap1, i.types[1],
539e75ad 2688 operand_types[0]))
29b0f896
AM		 2689 {
2690 /* Does not match either direction. */
2691 continue;
2692 }
2693 /* found_reverse_match holds which of D or FloatDR
2694 we've found. */
8a2ed489
L		 2695 if ((t->opcode_modifier & D))
2696 found_reverse_match = Opcode_D;
2697 else if ((t->opcode_modifier & FloatD))
2698 found_reverse_match = Opcode_FloatD;
2699 else
2700 found_reverse_match = 0;
2701 if ((t->opcode_modifier & FloatR))
2702 found_reverse_match |= Opcode_FloatR;
29b0f896 2703 }
f48ff2ae 2704 else
29b0f896 2705 {
f48ff2ae 2706 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2707 switch (t->operands)
2708 {
2709 case 4:
2710 overlap3 = i.types[3] & operand_types[3];
2711 case 3:
2712 overlap2 = i.types[2] & operand_types[2];
2713 break;
2714 }
29b0f896 2715
f48ff2ae
L		 2716 switch (t->operands)
2717 {
2718 case 4:
2719 if (!MATCH (overlap3, i.types[3], operand_types[3])
2720 || !CONSISTENT_REGISTER_MATCH (overlap2,
2721 i.types[2],
2722 operand_types[2],
2723 overlap3,
2724 i.types[3],
2725 operand_types[3]))
2726 continue;
2727 case 3:
2728 /* Here we make use of the fact that there are no
2729 reverse match 3 operand instructions, and all 3
2730 operand instructions only need to be checked for
2731 register consistency between operands 2 and 3. */
2732 if (!MATCH (overlap2, i.types[2], operand_types[2])
2733 || !CONSISTENT_REGISTER_MATCH (overlap1,
2734 i.types[1],
2735 operand_types[1],
2736 overlap2,
2737 i.types[2],
2738 operand_types[2]))
2739 continue;
2740 break;
2741 }
29b0f896 2742 }
f48ff2ae 2743 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2744 slip through to break. */
2745 }
2746 if (t->cpu_flags & ~cpu_arch_flags)
2747 {
2748 found_reverse_match = 0;
2749 continue;
2750 }
2751 /* We've found a match; break out of loop. */
2752 break;
2753 }
2754
2755 if (t == current_templates->end)
2756 {
2757 /* We found no match. */
2758 as_bad (_("suffix or operands invalid for `%s'"),
2759 current_templates->start->name);
2760 return 0;
2761 }
252b5132 2762
29b0f896
AM		 2763 if (!quiet_warnings)
2764 {
2765 if (!intel_syntax
2766 && ((i.types[0] & JumpAbsolute)
539e75ad 2767 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2768 {
2769 as_warn (_("indirect %s without `*'"), t->name);
2770 }
2771
2772 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2773 == (IsPrefix | IgnoreSize))
2774 {
2775 /* Warn them that a data or address size prefix doesn't
2776 affect assembly of the next line of code. */
2777 as_warn (_("stand-alone `%s' prefix"), t->name);
2778 }
2779 }
2780
2781 /* Copy the template we found. */
2782 i.tm = *t;
539e75ad
L		 2783
2784 if (addr_prefix_disp != -1)
2785 i.tm.operand_types[addr_prefix_disp]
2786 = operand_types[addr_prefix_disp];
2787
29b0f896
AM		 2788 if (found_reverse_match)
2789 {
2790 /* If we found a reverse match we must alter the opcode
2791 direction bit. found_reverse_match holds bits to change
2792 (different for int & float insns). */
2793
2794 i.tm.base_opcode ^= found_reverse_match;
2795
539e75ad
L		 2796 i.tm.operand_types[0] = operand_types[1];
2797 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2798 }
2799
2800 return 1;
2801}
2802
2803static int
e3bb37b5 2804check_string (void)
29b0f896
AM		 2805{
2806 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2807 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2808 {
2809 if (i.seg[0] != NULL && i.seg[0] != &es)
2810 {
2811 as_bad (_("`%s' operand %d must use `%%es' segment"),
2812 i.tm.name,
2813 mem_op + 1);
2814 return 0;
2815 }
2816 /* There's only ever one segment override allowed per instruction.
2817 This instruction possibly has a legal segment override on the
2818 second operand, so copy the segment to where non-string
2819 instructions store it, allowing common code. */
2820 i.seg[0] = i.seg[1];
2821 }
2822 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2823 {
2824 if (i.seg[1] != NULL && i.seg[1] != &es)
2825 {
2826 as_bad (_("`%s' operand %d must use `%%es' segment"),
2827 i.tm.name,
2828 mem_op + 2);
2829 return 0;
2830 }
2831 }
2832 return 1;
2833}
2834
2835static int
543613e9 2836process_suffix (void)
29b0f896
AM		 2837{
2838 /* If matched instruction specifies an explicit instruction mnemonic
2839 suffix, use it. */
2840 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2841 {
2842 if (i.tm.opcode_modifier & Size16)
2843 i.suffix = WORD_MNEM_SUFFIX;
2844 else if (i.tm.opcode_modifier & Size64)
2845 i.suffix = QWORD_MNEM_SUFFIX;
2846 else
2847 i.suffix = LONG_MNEM_SUFFIX;
2848 }
2849 else if (i.reg_operands)
2850 {
2851 /* If there's no instruction mnemonic suffix we try to invent one
2852 based on register operands. */
2853 if (!i.suffix)
2854 {
2855 /* We take i.suffix from the last register operand specified,
2856 Destination register type is more significant than source
381d071f
L		 2857 register type. crc32 in SSE4.2 prefers source register
2858 type. */
2859 if (i.tm.base_opcode == 0xf20f38f1)
2860 {
2861 if ((i.types[0] & Reg))
2862 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
29b0f896 2863 LONG_MNEM_SUFFIX);
381d071f 2864 }
9344ff29 2865 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94
L		 2866 {
2867 if ((i.types[0] & Reg8))
2868 i.suffix = BYTE_MNEM_SUFFIX;
2869 }
381d071f
L		 2870
2871 if (!i.suffix)
2872 {
2873 int op;
2874
20592a94
L		 2875 if (i.tm.base_opcode == 0xf20f38f1
2876 || i.tm.base_opcode == 0xf20f38f0)
2877 {
2878 /* We have to know the operand size for crc32. */
2879 as_bad (_("ambiguous memory operand size for `%s`"),
2880 i.tm.name);
2881 return 0;
2882 }
2883
381d071f
L		 2884 for (op = i.operands; --op >= 0;)
2885 if ((i.types[op] & Reg)
2886 && !(i.tm.operand_types[op] & InOutPortReg))
2887 {
2888 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2889 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2890 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2891 LONG_MNEM_SUFFIX);
2892 break;
2893 }
2894 }
29b0f896
AM		 2895 }
2896 else if (i.suffix == BYTE_MNEM_SUFFIX)
2897 {
2898 if (!check_byte_reg ())
2899 return 0;
2900 }
2901 else if (i.suffix == LONG_MNEM_SUFFIX)
2902 {
2903 if (!check_long_reg ())
2904 return 0;
2905 }
2906 else if (i.suffix == QWORD_MNEM_SUFFIX)
2907 {
2908 if (!check_qword_reg ())
2909 return 0;
2910 }
2911 else if (i.suffix == WORD_MNEM_SUFFIX)
2912 {
2913 if (!check_word_reg ())
2914 return 0;
2915 }
2916 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2917 /* Do nothing if the instruction is going to ignore the prefix. */
2918 ;
2919 else
2920 abort ();
2921 }
9306ca4a
JB		 2922 else if ((i.tm.opcode_modifier & DefaultSize)
2923 && !i.suffix
2924 /* exclude fldenv/frstor/fsave/fstenv */
2925 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2926 {
2927 i.suffix = stackop_size;
2928 }
9306ca4a
JB		 2929 else if (intel_syntax
2930 && !i.suffix
2931 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2932 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2933 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2934 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2935 {
2936 switch (flag_code)
2937 {
2938 case CODE_64BIT:
2939 if (!(i.tm.opcode_modifier & No_qSuf))
2940 {
2941 i.suffix = QWORD_MNEM_SUFFIX;
2942 break;
2943 }
2944 case CODE_32BIT:
2945 if (!(i.tm.opcode_modifier & No_lSuf))
2946 i.suffix = LONG_MNEM_SUFFIX;
2947 break;
2948 case CODE_16BIT:
2949 if (!(i.tm.opcode_modifier & No_wSuf))
2950 i.suffix = WORD_MNEM_SUFFIX;
2951 break;
2952 }
2953 }
252b5132 2954
9306ca4a 2955 if (!i.suffix)
29b0f896 2956 {
9306ca4a
JB		 2957 if (!intel_syntax)
2958 {
2959 if (i.tm.opcode_modifier & W)
2960 {
4eed87de
AM		 2961 as_bad (_("no instruction mnemonic suffix given and "
2962 "no register operands; can't size instruction"));
9306ca4a
JB		 2963 return 0;
2964 }
2965 }
2966 else
2967 {
64e74474
AM		 2968 unsigned int suffixes = (~i.tm.opcode_modifier
2969 & (No_bSuf
2970 | No_wSuf
2971 | No_lSuf
2972 | No_sSuf
2973 | No_xSuf
2974 | No_qSuf));
9306ca4a
JB		 2975
2976 if ((i.tm.opcode_modifier & W)
2977 || ((suffixes & (suffixes - 1))
2978 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2979 {
2980 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2981 return 0;
2982 }
2983 }
29b0f896 2984 }
252b5132 2985
9306ca4a
JB		 2986 /* Change the opcode based on the operand size given by i.suffix;
2987 We don't need to change things for byte insns. */
2988
29b0f896
AM		 2989 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2990 {
2991 /* It's not a byte, select word/dword operation. */
2992 if (i.tm.opcode_modifier & W)
2993 {
2994 if (i.tm.opcode_modifier & ShortForm)
2995 i.tm.base_opcode |= 8;
2996 else
2997 i.tm.base_opcode |= 1;
2998 }
0f3f3d8b 2999
29b0f896
AM		 3000 /* Now select between word & dword operations via the operand
3001 size prefix, except for instructions that will ignore this
3002 prefix anyway. */
cb712a9e
L		 3003 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3004 {
3005 /* monitor in SSE3 is a very special case. The default size
3006 of AX is the size of mode. The address size override
3007 prefix will change the size of AX. */
3008 if (i.op->regs[0].reg_type &
3009 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3010 if (!add_prefix (ADDR_PREFIX_OPCODE))
3011 return 0;
3012 }
3013 else if (i.suffix != QWORD_MNEM_SUFFIX
3014 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3015 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3016 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3017 || (flag_code == CODE_64BIT
3018 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3019 {
3020 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3021
29b0f896
AM		 3022 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3023 prefix = ADDR_PREFIX_OPCODE;
252b5132 3024
29b0f896
AM		 3025 if (!add_prefix (prefix))
3026 return 0;
24eab124 3027 }
252b5132 3028
29b0f896
AM		 3029 /* Set mode64 for an operand. */
3030 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3031 && flag_code == CODE_64BIT
29b0f896 3032 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3033 {
3034 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3035 need rex64. */
3036 if (i.operands != 2
3037 || i.types [0] != (Acc | Reg64)
3038 || i.types [1] != (Acc | Reg64)
13a1e313 3039 || i.tm.base_opcode != 0x90)
f6bee062 3040 i.rex |= REX_W;
46e883c5 3041 }
3e73aa7c 3042
29b0f896
AM		 3043 /* Size floating point instruction. */
3044 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3045 if (i.tm.opcode_modifier & FloatMF)
3046 i.tm.base_opcode ^= 4;
29b0f896 3047 }
7ecd2f8b 3048
29b0f896
AM		 3049 return 1;
3050}
3e73aa7c 3051
29b0f896 3052static int
543613e9 3053check_byte_reg (void)
29b0f896
AM		 3054{
3055 int op;
543613e9 3056
29b0f896
AM		 3057 for (op = i.operands; --op >= 0;)
3058 {
3059 /* If this is an eight bit register, it's OK. If it's the 16 or
3060 32 bit version of an eight bit register, we will just use the
3061 low portion, and that's OK too. */
3062 if (i.types[op] & Reg8)
3063 continue;
3064
c3ad16c0
L		 3065 /* movzx, movsx, pextrb and pinsrb should not generate this
3066 warning. */
29b0f896
AM		 3067 if (intel_syntax
3068 && (i.tm.base_opcode == 0xfb7
3069 || i.tm.base_opcode == 0xfb6
3070 || i.tm.base_opcode == 0x63
3071 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3072 || i.tm.base_opcode == 0xfbf
3073 || i.tm.base_opcode == 0x660f3a14
3074 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3075 continue;
3076
9344ff29
L		 3077 /* crc32 doesn't generate this warning. */
3078 if (i.tm.base_opcode == 0xf20f38f0)
3079 continue;
3080
65ec77d2 3081 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3082 {
3083 /* Prohibit these changes in the 64bit mode, since the
3084 lowering is more complicated. */
3085 if (flag_code == CODE_64BIT
3086 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3087 {
2ca3ace5
L		 3088 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3089 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3090 i.suffix);
3091 return 0;
3092 }
3093#if REGISTER_WARNINGS
3094 if (!quiet_warnings
3095 && (i.tm.operand_types[op] & InOutPortReg) == 0)
a540244d
L		 3096 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3097 register_prefix,
29b0f896
AM		 3098 (i.op[op].regs + (i.types[op] & Reg16
3099 ? REGNAM_AL - REGNAM_AX
3100 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3101 register_prefix,
29b0f896
AM		 3102 i.op[op].regs->reg_name,
3103 i.suffix);
3104#endif
3105 continue;
3106 }
3107 /* Any other register is bad. */
3108 if (i.types[op] & (Reg | RegMMX | RegXMM
3109 | SReg2 | SReg3
3110 | Control | Debug | Test
3111 | FloatReg | FloatAcc))
3112 {
a540244d
L		 3113 as_bad (_("`%s%s' not allowed with `%s%c'"),
3114 register_prefix,
29b0f896
AM		 3115 i.op[op].regs->reg_name,
3116 i.tm.name,
3117 i.suffix);
3118 return 0;
3119 }
3120 }
3121 return 1;
3122}
3123
3124static int
e3bb37b5 3125check_long_reg (void)
29b0f896
AM		 3126{
3127 int op;
3128
3129 for (op = i.operands; --op >= 0;)
3130 /* Reject eight bit registers, except where the template requires
3131 them. (eg. movzb) */
3132 if ((i.types[op] & Reg8) != 0
3133 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3134 {
a540244d
L		 3135 as_bad (_("`%s%s' not allowed with `%s%c'"),
3136 register_prefix,
29b0f896
AM		 3137 i.op[op].regs->reg_name,
3138 i.tm.name,
3139 i.suffix);
3140 return 0;
3141 }
3142 /* Warn if the e prefix on a general reg is missing. */
3143 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3144 && (i.types[op] & Reg16) != 0
3145 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3146 {
3147 /* Prohibit these changes in the 64bit mode, since the
3148 lowering is more complicated. */
3149 if (flag_code == CODE_64BIT)
252b5132 3150 {
2ca3ace5
L		 3151 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3152 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3153 i.suffix);
3154 return 0;
252b5132 3155 }
29b0f896
AM		 3156#if REGISTER_WARNINGS
3157 else
a540244d
L		 3158 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3159 register_prefix,
29b0f896 3160 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3161 register_prefix,
29b0f896
AM		 3162 i.op[op].regs->reg_name,
3163 i.suffix);
3164#endif
252b5132 3165 }
29b0f896
AM		 3166 /* Warn if the r prefix on a general reg is missing. */
3167 else if ((i.types[op] & Reg64) != 0
3168 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3169 {
34828aad
L		 3170 if (intel_syntax
3171 && i.tm.base_opcode == 0xf30f2d
3172 && (i.types[0] & RegXMM) == 0)
3173 {
3174 /* cvtss2si converts DWORD memory to Reg64. We want
3175 REX byte. */
3176 i.suffix = QWORD_MNEM_SUFFIX;
3177 }
3178 else
3179 {
3180 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3181 register_prefix, i.op[op].regs->reg_name,
3182 i.suffix);
3183 return 0;
3184 }
29b0f896
AM		 3185 }
3186 return 1;
3187}
252b5132 3188
29b0f896 3189static int
e3bb37b5 3190check_qword_reg (void)
29b0f896
AM		 3191{
3192 int op;
252b5132 3193
29b0f896
AM		 3194 for (op = i.operands; --op >= 0; )
3195 /* Reject eight bit registers, except where the template requires
3196 them. (eg. movzb) */
3197 if ((i.types[op] & Reg8) != 0
3198 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3199 {
a540244d
L		 3200 as_bad (_("`%s%s' not allowed with `%s%c'"),
3201 register_prefix,
29b0f896
AM		 3202 i.op[op].regs->reg_name,
3203 i.tm.name,
3204 i.suffix);
3205 return 0;
3206 }
3207 /* Warn if the e prefix on a general reg is missing. */
34828aad 3208 else if ((i.types[op] & (Reg16 | Reg32)) != 0
29b0f896
AM		 3209 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3210 {
3211 /* Prohibit these changes in the 64bit mode, since the
3212 lowering is more complicated. */
34828aad
L		 3213 if (intel_syntax
3214 && i.tm.base_opcode == 0xf20f2d
3215 && (i.types[0] & RegXMM) == 0)
3216 {
3217 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3218 REX byte. */
3219 i.suffix = LONG_MNEM_SUFFIX;
3220 }
3221 else
3222 {
3223 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3224 register_prefix, i.op[op].regs->reg_name,
3225 i.suffix);
3226 return 0;
3227 }
252b5132 3228 }
29b0f896
AM		 3229 return 1;
3230}
252b5132 3231
29b0f896 3232static int
e3bb37b5 3233check_word_reg (void)
29b0f896
AM		 3234{
3235 int op;
3236 for (op = i.operands; --op >= 0;)
3237 /* Reject eight bit registers, except where the template requires
3238 them. (eg. movzb) */
3239 if ((i.types[op] & Reg8) != 0
3240 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3241 {
a540244d
L		 3242 as_bad (_("`%s%s' not allowed with `%s%c'"),
3243 register_prefix,
29b0f896
AM		 3244 i.op[op].regs->reg_name,
3245 i.tm.name,
3246 i.suffix);
3247 return 0;
3248 }
3249 /* Warn if the e prefix on a general reg is present. */
3250 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3251 && (i.types[op] & Reg32) != 0
3252 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3253 {
29b0f896
AM		 3254 /* Prohibit these changes in the 64bit mode, since the
3255 lowering is more complicated. */
3256 if (flag_code == CODE_64BIT)
252b5132 3257 {
2ca3ace5
L		 3258 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3259 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3260 i.suffix);
3261 return 0;
252b5132 3262 }
29b0f896
AM		 3263 else
3264#if REGISTER_WARNINGS
a540244d
L		 3265 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3266 register_prefix,
29b0f896 3267 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3268 register_prefix,
29b0f896
AM		 3269 i.op[op].regs->reg_name,
3270 i.suffix);
3271#endif
3272 }
3273 return 1;
3274}
252b5132 3275
29b0f896 3276static int
e3bb37b5 3277finalize_imm (void)
29b0f896
AM		 3278{
3279 unsigned int overlap0, overlap1, overlap2;
3280
3281 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3282 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3283 && overlap0 != Imm8 && overlap0 != Imm8S
3284 && overlap0 != Imm16 && overlap0 != Imm32S
3285 && overlap0 != Imm32 && overlap0 != Imm64)
3286 {
3287 if (i.suffix)
3288 {
3289 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3290 ? Imm8 | Imm8S
3291 : (i.suffix == WORD_MNEM_SUFFIX
3292 ? Imm16
3293 : (i.suffix == QWORD_MNEM_SUFFIX
3294 ? Imm64 | Imm32S
3295 : Imm32)));
3296 }
3297 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3298 || overlap0 == (Imm16 | Imm32)
3299 || overlap0 == (Imm16 | Imm32S))
3300 {
3301 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3302 ? Imm16 : Imm32S);
3303 }
3304 if (overlap0 != Imm8 && overlap0 != Imm8S
3305 && overlap0 != Imm16 && overlap0 != Imm32S
3306 && overlap0 != Imm32 && overlap0 != Imm64)
3307 {
4eed87de
AM		 3308 as_bad (_("no instruction mnemonic suffix given; "
3309 "can't determine immediate size"));
29b0f896
AM		 3310 return 0;
3311 }
3312 }
3313 i.types[0] = overlap0;
3314
3315 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3316 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3317 && overlap1 != Imm8 && overlap1 != Imm8S
3318 && overlap1 != Imm16 && overlap1 != Imm32S
3319 && overlap1 != Imm32 && overlap1 != Imm64)
3320 {
3321 if (i.suffix)
3322 {
3323 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3324 ? Imm8 | Imm8S
3325 : (i.suffix == WORD_MNEM_SUFFIX
3326 ? Imm16
3327 : (i.suffix == QWORD_MNEM_SUFFIX
3328 ? Imm64 | Imm32S
3329 : Imm32)));
3330 }
3331 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3332 || overlap1 == (Imm16 | Imm32)
3333 || overlap1 == (Imm16 | Imm32S))
3334 {
3335 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3336 ? Imm16 : Imm32S);
3337 }
3338 if (overlap1 != Imm8 && overlap1 != Imm8S
3339 && overlap1 != Imm16 && overlap1 != Imm32S
3340 && overlap1 != Imm32 && overlap1 != Imm64)
3341 {
4eed87de
AM		 3342 as_bad (_("no instruction mnemonic suffix given; "
3343 "can't determine immediate size %x %c"),
3344 overlap1, i.suffix);
29b0f896
AM		 3345 return 0;
3346 }
3347 }
3348 i.types[1] = overlap1;
3349
3350 overlap2 = i.types[2] & i.tm.operand_types[2];
3351 assert ((overlap2 & Imm) == 0);
3352 i.types[2] = overlap2;
3353
3354 return 1;
3355}
3356
3357static int
e3bb37b5 3358process_operands (void)
29b0f896
AM		 3359{
3360 /* Default segment register this instruction will use for memory
3361 accesses. 0 means unknown. This is only for optimizing out
3362 unnecessary segment overrides. */
3363 const seg_entry *default_seg = 0;
3364
3365 /* The imul $imm, %reg instruction is converted into
3366 imul $imm, %reg, %reg, and the clr %reg instruction
3367 is converted into xor %reg, %reg. */
5f15756d 3368 if (i.tm.opcode_modifier & RegKludge)
29b0f896 3369 {
42903f7f
L		 3370 if ((i.tm.cpu_flags & CpuSSE4_1))
3371 {
3372 /* The first operand in instruction blendvpd, blendvps and
3373 pblendvb in SSE4.1 is implicit and must be xmm0. */
3374 assert (i.operands == 3
3375 && i.reg_operands >= 2
3376 && i.types[0] == RegXMM);
3377 if (i.op[0].regs->reg_num != 0)
3378 {
3379 if (intel_syntax)
3380 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3381 i.tm.name, register_prefix);
3382 else
3383 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3384 i.tm.name, register_prefix);
3385 return 0;
3386 }
3387 i.op[0] = i.op[1];
3388 i.op[1] = i.op[2];
3389 i.types[0] = i.types[1];
3390 i.types[1] = i.types[2];
3391 i.operands--;
3392 i.reg_operands--;
3393
3394 /* We need to adjust fields in i.tm since they are used by
3395 build_modrm_byte. */
3396 i.tm.operand_types [0] = i.tm.operand_types [1];
3397 i.tm.operand_types [1] = i.tm.operand_types [2];
3398 i.tm.operands--;
3399 }
3400 else
3401 {
3402 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3403 /* Pretend we saw the extra register operand. */
3404 assert (i.reg_operands == 1
3405 && i.op[first_reg_op + 1].regs == 0);
3406 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3407 i.types[first_reg_op + 1] = i.types[first_reg_op];
3408 i.operands++;
3409 i.reg_operands++;
3410 }
29b0f896
AM		 3411 }
3412
3413 if (i.tm.opcode_modifier & ShortForm)
3414 {
4eed87de 3415 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3416 {
4eed87de
AM		 3417 if (i.tm.base_opcode == POP_SEG_SHORT
3418 && i.op[0].regs->reg_num == 1)
29b0f896 3419 {
4eed87de
AM		 3420 as_bad (_("you can't `pop %%cs'"));
3421 return 0;
29b0f896 3422 }
4eed87de
AM		 3423 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3424 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3425 i.rex |= REX_B;
4eed87de
AM		 3426 }
3427 else
3428 {
3429 /* The register or float register operand is in operand 0 or 1. */
3430 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3431 /* Register goes in low 3 bits of opcode. */
3432 i.tm.base_opcode |= i.op[op].regs->reg_num;
3433 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3434 i.rex |= REX_B;
4eed87de 3435 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3436 {
4eed87de
AM		 3437 /* Warn about some common errors, but press on regardless.
3438 The first case can be generated by gcc (<= 2.8.1). */
3439 if (i.operands == 2)
3440 {
3441 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3442 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3443 register_prefix, i.op[1].regs->reg_name,
3444 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3445 }
3446 else
3447 {
3448 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3449 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3450 register_prefix, i.op[0].regs->reg_name);
4eed87de 3451 }
29b0f896
AM		 3452 }
3453 }
3454 }
3455 else if (i.tm.opcode_modifier & Modrm)
3456 {
3457 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3458 must be put into the modrm byte). Now, we make the modrm and
3459 index base bytes based on all the info we've collected. */
29b0f896
AM		 3460
3461 default_seg = build_modrm_byte ();
3462 }
8a2ed489 3463 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3464 {
3465 default_seg = &ds;
3466 }
3467 else if ((i.tm.opcode_modifier & IsString) != 0)
3468 {
3469 /* For the string instructions that allow a segment override
3470 on one of their operands, the default segment is ds. */
3471 default_seg = &ds;
3472 }
3473
30123838
JB		 3474 if ((i.tm.base_opcode == 0x8d /* lea */
3475 || (i.tm.cpu_flags & CpuSVME))
3476 && i.seg[0] && !quiet_warnings)
3477 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3478
3479 /* If a segment was explicitly specified, and the specified segment
3480 is not the default, use an opcode prefix to select it. If we
3481 never figured out what the default segment is, then default_seg
3482 will be zero at this point, and the specified segment prefix will
3483 always be used. */
29b0f896
AM		 3484 if ((i.seg[0]) && (i.seg[0] != default_seg))
3485 {
3486 if (!add_prefix (i.seg[0]->seg_prefix))
3487 return 0;
3488 }
3489 return 1;
3490}
3491
3492static const seg_entry *
e3bb37b5 3493build_modrm_byte (void)
29b0f896
AM		 3494{
3495 const seg_entry *default_seg = 0;
3496
3497 /* i.reg_operands MUST be the number of real register operands;
3498 implicit registers do not count. */
3499 if (i.reg_operands == 2)
3500 {
3501 unsigned int source, dest;
cab737b9
L		 3502
3503 switch (i.operands)
3504 {
3505 case 2:
3506 source = 0;
3507 break;
3508 case 3:
c81128dc
L		 3509 /* When there are 3 operands, one of them may be immediate,
3510 which may be the first or the last operand. Otherwise,
3511 the first operand must be shift count register (cl). */
3512 assert (i.imm_operands == 1
3513 || (i.imm_operands == 0
3514 && (i.types[0] & ShiftCount)));
3515 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3516 break;
3517 case 4:
3518 /* When there are 4 operands, the first two must be immediate
3519 operands. The source operand will be the 3rd one. */
3520 assert (i.imm_operands == 2
3521 && (i.types[0] & Imm)
3522 && (i.types[1] & Imm));
3523 source = 2;
3524 break;
3525 default:
3526 abort ();
3527 }
3528
29b0f896
AM		 3529 dest = source + 1;
3530
3531 i.rm.mode = 3;
3532 /* One of the register operands will be encoded in the i.tm.reg
3533 field, the other in the combined i.tm.mode and i.tm.regmem
3534 fields. If no form of this instruction supports a memory
3535 destination operand, then we assume the source operand may
3536 sometimes be a memory operand and so we need to store the
3537 destination in the i.rm.reg field. */
e72cf3ec 3538 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3539 {
3540 i.rm.reg = i.op[dest].regs->reg_num;
3541 i.rm.regmem = i.op[source].regs->reg_num;
3542 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3543 i.rex |= REX_R;
29b0f896 3544 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3545 i.rex |= REX_B;
29b0f896
AM		 3546 }
3547 else
3548 {
3549 i.rm.reg = i.op[source].regs->reg_num;
3550 i.rm.regmem = i.op[dest].regs->reg_num;
3551 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3552 i.rex |= REX_B;
29b0f896 3553 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3554 i.rex |= REX_R;
29b0f896 3555 }
161a04f6 3556 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3557 {
3558 if (!((i.types[0] | i.types[1]) & Control))
3559 abort ();
161a04f6 3560 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3561 add_prefix (LOCK_PREFIX_OPCODE);
3562 }
29b0f896
AM		 3563 }
3564 else
3565 { /* If it's not 2 reg operands... */
3566 if (i.mem_operands)
3567 {
3568 unsigned int fake_zero_displacement = 0;
99018f42 3569 unsigned int op;
4eed87de 3570
99018f42
L		 3571 for (op = 0; op < i.operands; op++)
3572 if ((i.types[op] & AnyMem))
3573 break;
3574 assert (op < i.operands);
29b0f896
AM		 3575
3576 default_seg = &ds;
3577
3578 if (i.base_reg == 0)
3579 {
3580 i.rm.mode = 0;
3581 if (!i.disp_operands)
3582 fake_zero_displacement = 1;
3583 if (i.index_reg == 0)
3584 {
3585 /* Operand is just <disp> */
20f0a1fc 3586 if (flag_code == CODE_64BIT)
29b0f896
AM		 3587 {
3588 /* 64bit mode overwrites the 32bit absolute
3589 addressing by RIP relative addressing and
3590 absolute addressing is encoded by one of the
3591 redundant SIB forms. */
3592 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3593 i.sib.base = NO_BASE_REGISTER;
3594 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3595 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3596 ? Disp32S : Disp32);
20f0a1fc 3597 }
fc225355
L		 3598 else if ((flag_code == CODE_16BIT)
3599 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3600 {
3601 i.rm.regmem = NO_BASE_REGISTER_16;
3602 i.types[op] = Disp16;
3603 }
3604 else
3605 {
3606 i.rm.regmem = NO_BASE_REGISTER;
3607 i.types[op] = Disp32;
29b0f896
AM		 3608 }
3609 }
3610 else /* !i.base_reg && i.index_reg */
3611 {
3612 i.sib.index = i.index_reg->reg_num;
3613 i.sib.base = NO_BASE_REGISTER;
3614 i.sib.scale = i.log2_scale_factor;
3615 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3616 i.types[op] &= ~Disp;
3617 if (flag_code != CODE_64BIT)
3618 i.types[op] |= Disp32; /* Must be 32 bit */
3619 else
3620 i.types[op] |= Disp32S;
3621 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3622 i.rex |= REX_X;
29b0f896
AM		 3623 }
3624 }
3625 /* RIP addressing for 64bit mode. */
3626 else if (i.base_reg->reg_type == BaseIndex)
3627 {
3628 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3629 i.types[op] &= ~ Disp;
29b0f896 3630 i.types[op] |= Disp32S;
71903a11 3631 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3632 if (! i.disp_operands)
3633 fake_zero_displacement = 1;
29b0f896
AM		 3634 }
3635 else if (i.base_reg->reg_type & Reg16)
3636 {
3637 switch (i.base_reg->reg_num)
3638 {
3639 case 3: /* (%bx) */
3640 if (i.index_reg == 0)
3641 i.rm.regmem = 7;
3642 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3643 i.rm.regmem = i.index_reg->reg_num - 6;
3644 break;
3645 case 5: /* (%bp) */
3646 default_seg = &ss;
3647 if (i.index_reg == 0)
3648 {
3649 i.rm.regmem = 6;
3650 if ((i.types[op] & Disp) == 0)
3651 {
3652 /* fake (%bp) into 0(%bp) */
3653 i.types[op] |= Disp8;
252b5132 3654 fake_zero_displacement = 1;
29b0f896
AM		 3655 }
3656 }
3657 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3658 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3659 break;
3660 default: /* (%si) -> 4 or (%di) -> 5 */
3661 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3662 }
3663 i.rm.mode = mode_from_disp_size (i.types[op]);
3664 }
3665 else /* i.base_reg and 32/64 bit mode */
3666 {
3667 if (flag_code == CODE_64BIT
3668 && (i.types[op] & Disp))
fc225355
L		 3669 i.types[op] = ((i.types[op] & Disp8)
3670 | (i.prefix[ADDR_PREFIX] == 0
3671 ? Disp32S : Disp32));
20f0a1fc 3672
29b0f896
AM		 3673 i.rm.regmem = i.base_reg->reg_num;
3674 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3675 i.rex |= REX_B;
29b0f896
AM		 3676 i.sib.base = i.base_reg->reg_num;
3677 /* x86-64 ignores REX prefix bit here to avoid decoder
3678 complications. */
3679 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3680 {
3681 default_seg = &ss;
3682 if (i.disp_operands == 0)
3683 {
3684 fake_zero_displacement = 1;
3685 i.types[op] |= Disp8;
3686 }
3687 }
3688 else if (i.base_reg->reg_num == ESP_REG_NUM)
3689 {
3690 default_seg = &ss;
3691 }
3692 i.sib.scale = i.log2_scale_factor;
3693 if (i.index_reg == 0)
3694 {
3695 /* <disp>(%esp) becomes two byte modrm with no index
3696 register. We've already stored the code for esp
3697 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3698 Any base register besides %esp will not use the
3699 extra modrm byte. */
3700 i.sib.index = NO_INDEX_REGISTER;
3701#if !SCALE1_WHEN_NO_INDEX
3702 /* Another case where we force the second modrm byte. */
3703 if (i.log2_scale_factor)
3704 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3705#endif
29b0f896
AM		 3706 }
3707 else
3708 {
3709 i.sib.index = i.index_reg->reg_num;
3710 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3711 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3712 i.rex |= REX_X;
29b0f896 3713 }
67a4f2b7
AO		 3714
3715 if (i.disp_operands
3716 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3717 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3718 i.rm.mode = 0;
3719 else
3720 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3721 }
252b5132 3722
29b0f896
AM		 3723 if (fake_zero_displacement)
3724 {
3725 /* Fakes a zero displacement assuming that i.types[op]
3726 holds the correct displacement size. */
3727 expressionS *exp;
3728
3729 assert (i.op[op].disps == 0);
3730 exp = &disp_expressions[i.disp_operands++];
3731 i.op[op].disps = exp;
3732 exp->X_op = O_constant;
3733 exp->X_add_number = 0;
3734 exp->X_add_symbol = (symbolS *) 0;
3735 exp->X_op_symbol = (symbolS *) 0;
3736 }
3737 }
252b5132 3738
29b0f896
AM		 3739 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3740 (if any) based on i.tm.extension_opcode. Again, we must be
3741 careful to make sure that segment/control/debug/test/MMX
3742 registers are coded into the i.rm.reg field. */
3743 if (i.reg_operands)
3744 {
99018f42
L		 3745 unsigned int op;
3746
3747 for (op = 0; op < i.operands; op++)
3748 if ((i.types[op] & (Reg | RegMMX | RegXMM
3749 | SReg2 | SReg3
3750 | Control | Debug | Test)))
3751 break;
3752 assert (op < i.operands);
3753
29b0f896
AM		 3754 /* If there is an extension opcode to put here, the register
3755 number must be put into the regmem field. */
3756 if (i.tm.extension_opcode != None)
3757 {
3758 i.rm.regmem = i.op[op].regs->reg_num;
3759 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3760 i.rex |= REX_B;
29b0f896
AM		 3761 }
3762 else
3763 {
3764 i.rm.reg = i.op[op].regs->reg_num;
3765 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3766 i.rex |= REX_R;
29b0f896 3767 }
252b5132 3768
29b0f896
AM		 3769 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3770 must set it to 3 to indicate this is a register operand
3771 in the regmem field. */
3772 if (!i.mem_operands)
3773 i.rm.mode = 3;
3774 }
252b5132 3775
29b0f896
AM		 3776 /* Fill in i.rm.reg field with extension opcode (if any). */
3777 if (i.tm.extension_opcode != None)
3778 i.rm.reg = i.tm.extension_opcode;
3779 }
3780 return default_seg;
3781}
252b5132 3782
29b0f896 3783static void
e3bb37b5 3784output_branch (void)
29b0f896
AM		 3785{
3786 char *p;
3787 int code16;
3788 int prefix;
3789 relax_substateT subtype;
3790 symbolS *sym;
3791 offsetT off;
3792
3793 code16 = 0;
3794 if (flag_code == CODE_16BIT)
3795 code16 = CODE16;
3796
3797 prefix = 0;
3798 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3799 {
29b0f896
AM		 3800 prefix = 1;
3801 i.prefixes -= 1;
3802 code16 ^= CODE16;
252b5132 3803 }
29b0f896
AM		 3804 /* Pentium4 branch hints. */
3805 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3806 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3807 {
29b0f896
AM		 3808 prefix++;
3809 i.prefixes--;
3810 }
3811 if (i.prefix[REX_PREFIX] != 0)
3812 {
3813 prefix++;
3814 i.prefixes--;
2f66722d
AM		 3815 }
3816
29b0f896
AM		 3817 if (i.prefixes != 0 && !intel_syntax)
3818 as_warn (_("skipping prefixes on this instruction"));
3819
3820 /* It's always a symbol; End frag & setup for relax.
3821 Make sure there is enough room in this frag for the largest
3822 instruction we may generate in md_convert_frag. This is 2
3823 bytes for the opcode and room for the prefix and largest
3824 displacement. */
3825 frag_grow (prefix + 2 + 4);
3826 /* Prefix and 1 opcode byte go in fr_fix. */
3827 p = frag_more (prefix + 1);
3828 if (i.prefix[DATA_PREFIX] != 0)
3829 *p++ = DATA_PREFIX_OPCODE;
3830 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3831 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3832 *p++ = i.prefix[SEG_PREFIX];
3833 if (i.prefix[REX_PREFIX] != 0)
3834 *p++ = i.prefix[REX_PREFIX];
3835 *p = i.tm.base_opcode;
3836
3837 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3838 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3839 else if ((cpu_arch_flags & Cpu386) != 0)
3840 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3841 else
3842 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3843 subtype |= code16;
3e73aa7c 3844
29b0f896
AM		 3845 sym = i.op[0].disps->X_add_symbol;
3846 off = i.op[0].disps->X_add_number;
3e73aa7c 3847
29b0f896
AM		 3848 if (i.op[0].disps->X_op != O_constant
3849 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3850 {
29b0f896
AM		 3851 /* Handle complex expressions. */
3852 sym = make_expr_symbol (i.op[0].disps);
3853 off = 0;
3854 }
3e73aa7c 3855
29b0f896
AM		 3856 /* 1 possible extra opcode + 4 byte displacement go in var part.
3857 Pass reloc in fr_var. */
3858 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3859}
3e73aa7c 3860
29b0f896 3861static void
e3bb37b5 3862output_jump (void)
29b0f896
AM		 3863{
3864 char *p;
3865 int size;
3e02c1cc 3866 fixS *fixP;
29b0f896
AM		 3867
3868 if (i.tm.opcode_modifier & JumpByte)
3869 {
3870 /* This is a loop or jecxz type instruction. */
3871 size = 1;
3872 if (i.prefix[ADDR_PREFIX] != 0)
3873 {
3874 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3875 i.prefixes -= 1;
3876 }
3877 /* Pentium4 branch hints. */
3878 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3879 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3880 {
3881 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3882 i.prefixes--;
3e73aa7c
JH		 3883 }
3884 }
29b0f896
AM		 3885 else
3886 {
3887 int code16;
3e73aa7c 3888
29b0f896
AM		 3889 code16 = 0;
3890 if (flag_code == CODE_16BIT)
3891 code16 = CODE16;
3e73aa7c 3892
29b0f896
AM		 3893 if (i.prefix[DATA_PREFIX] != 0)
3894 {
3895 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3896 i.prefixes -= 1;
3897 code16 ^= CODE16;
3898 }
252b5132 3899
29b0f896
AM		 3900 size = 4;
3901 if (code16)
3902 size = 2;
3903 }
9fcc94b6 3904
29b0f896
AM		 3905 if (i.prefix[REX_PREFIX] != 0)
3906 {
3907 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3908 i.prefixes -= 1;
3909 }
252b5132 3910
29b0f896
AM		 3911 if (i.prefixes != 0 && !intel_syntax)
3912 as_warn (_("skipping prefixes on this instruction"));
e0890092 3913
29b0f896
AM		 3914 p = frag_more (1 + size);
3915 *p++ = i.tm.base_opcode;
e0890092 3916
3e02c1cc
AM		 3917 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3918 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3919
3920 /* All jumps handled here are signed, but don't use a signed limit
3921 check for 32 and 16 bit jumps as we want to allow wrap around at
3922 4G and 64k respectively. */
3923 if (size == 1)
3924 fixP->fx_signed = 1;
29b0f896 3925}
e0890092 3926
29b0f896 3927static void
e3bb37b5 3928output_interseg_jump (void)
29b0f896
AM		 3929{
3930 char *p;
3931 int size;
3932 int prefix;
3933 int code16;
252b5132 3934
29b0f896
AM		 3935 code16 = 0;
3936 if (flag_code == CODE_16BIT)
3937 code16 = CODE16;
a217f122 3938
29b0f896
AM		 3939 prefix = 0;
3940 if (i.prefix[DATA_PREFIX] != 0)
3941 {
3942 prefix = 1;
3943 i.prefixes -= 1;
3944 code16 ^= CODE16;
3945 }
3946 if (i.prefix[REX_PREFIX] != 0)
3947 {
3948 prefix++;
3949 i.prefixes -= 1;
3950 }
252b5132 3951
29b0f896
AM		 3952 size = 4;
3953 if (code16)
3954 size = 2;
252b5132 3955
29b0f896
AM		 3956 if (i.prefixes != 0 && !intel_syntax)
3957 as_warn (_("skipping prefixes on this instruction"));
252b5132 3958
29b0f896
AM		 3959 /* 1 opcode; 2 segment; offset */
3960 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3961
29b0f896
AM		 3962 if (i.prefix[DATA_PREFIX] != 0)
3963 *p++ = DATA_PREFIX_OPCODE;
252b5132 3964
29b0f896
AM		 3965 if (i.prefix[REX_PREFIX] != 0)
3966 *p++ = i.prefix[REX_PREFIX];
252b5132 3967
29b0f896
AM		 3968 *p++ = i.tm.base_opcode;
3969 if (i.op[1].imms->X_op == O_constant)
3970 {
3971 offsetT n = i.op[1].imms->X_add_number;
252b5132 3972
29b0f896
AM		 3973 if (size == 2
3974 && !fits_in_unsigned_word (n)
3975 && !fits_in_signed_word (n))
3976 {
3977 as_bad (_("16-bit jump out of range"));
3978 return;
3979 }
3980 md_number_to_chars (p, n, size);
3981 }
3982 else
3983 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3984 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3985 if (i.op[0].imms->X_op != O_constant)
3986 as_bad (_("can't handle non absolute segment in `%s'"),
3987 i.tm.name);
3988 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3989}
a217f122 3990
29b0f896 3991static void
e3bb37b5 3992output_insn (void)
29b0f896 3993{
2bbd9c25
JJ		 3994 fragS *insn_start_frag;
3995 offsetT insn_start_off;
3996
29b0f896
AM		 3997 /* Tie dwarf2 debug info to the address at the start of the insn.
3998 We can't do this after the insn has been output as the current
3999 frag may have been closed off. eg. by frag_var. */
4000 dwarf2_emit_insn (0);
4001
2bbd9c25
JJ		 4002 insn_start_frag = frag_now;
4003 insn_start_off = frag_now_fix ();
4004
29b0f896
AM		 4005 /* Output jumps. */
4006 if (i.tm.opcode_modifier & Jump)
4007 output_branch ();
4008 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
4009 output_jump ();
4010 else if (i.tm.opcode_modifier & JumpInterSegment)
4011 output_interseg_jump ();
4012 else
4013 {
4014 /* Output normal instructions here. */
4015 char *p;
4016 unsigned char *q;
331d2d0d 4017 unsigned int prefix;
252b5132 4018
42903f7f 4019 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 4020 SSE4 instructions have 3 bytes. We may use one more higher
4021 byte to specify a prefix the instruction requires. Exclude
4022 instructions which are in both SSE4 and ABM. */
4023 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4024 && (i.tm.cpu_flags & CpuABM) == 0)
bc4bd9ab 4025 {
331d2d0d
L		 4026 if (i.tm.base_opcode & 0xff000000)
4027 {
4028 prefix = (i.tm.base_opcode >> 24) & 0xff;
4029 goto check_prefix;
4030 }
4031 }
4032 else if ((i.tm.base_opcode & 0xff0000) != 0)
4033 {
4034 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 4035 if ((i.tm.cpu_flags & CpuPadLock) != 0)
4036 {
64e74474 4037 check_prefix:
bc4bd9ab
MK		 4038 if (prefix != REPE_PREFIX_OPCODE
4039 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4040 add_prefix (prefix);
4041 }
4042 else
331d2d0d 4043 add_prefix (prefix);
0f10071e 4044 }
252b5132 4045
29b0f896
AM		 4046 /* The prefix bytes. */
4047 for (q = i.prefix;
4048 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
4049 q++)
4050 {
4051 if (*q)
4052 {
4053 p = frag_more (1);
4054 md_number_to_chars (p, (valueT) *q, 1);
4055 }
4056 }
252b5132 4057
29b0f896
AM		 4058 /* Now the opcode; be careful about word order here! */
4059 if (fits_in_unsigned_byte (i.tm.base_opcode))
4060 {
4061 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4062 }
4063 else
4064 {
381d071f
L		 4065 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4066 && (i.tm.cpu_flags & CpuABM) == 0)
331d2d0d
L		 4067 {
4068 p = frag_more (3);
4069 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4070 }
4071 else
4072 p = frag_more (2);
0f10071e 4073
29b0f896
AM		 4074 /* Put out high byte first: can't use md_number_to_chars! */
4075 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4076 *p = i.tm.base_opcode & 0xff;
4077 }
3e73aa7c 4078
29b0f896
AM		 4079 /* Now the modrm byte and sib byte (if present). */
4080 if (i.tm.opcode_modifier & Modrm)
4081 {
4082 p = frag_more (1);
4083 md_number_to_chars (p,
4084 (valueT) (i.rm.regmem << 0
4085 | i.rm.reg << 3
4086 | i.rm.mode << 6),
4087 1);
4088 /* If i.rm.regmem == ESP (4)
4089 && i.rm.mode != (Register mode)
4090 && not 16 bit
4091 ==> need second modrm byte. */
4092 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4093 && i.rm.mode != 3
4094 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4095 {
4096 p = frag_more (1);
4097 md_number_to_chars (p,
4098 (valueT) (i.sib.base << 0
4099 | i.sib.index << 3
4100 | i.sib.scale << 6),
4101 1);
4102 }
4103 }
3e73aa7c 4104
29b0f896 4105 if (i.disp_operands)
2bbd9c25 4106 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4107
29b0f896 4108 if (i.imm_operands)
2bbd9c25 4109 output_imm (insn_start_frag, insn_start_off);
29b0f896 4110 }
252b5132 4111
29b0f896
AM		 4112#ifdef DEBUG386
4113 if (flag_debug)
4114 {
7b81dfbb 4115 pi ("" /*line*/, &i);
29b0f896
AM		 4116 }
4117#endif /* DEBUG386 */
4118}
252b5132 4119
e205caa7
L		 4120/* Return the size of the displacement operand N. */
4121
4122static int
4123disp_size (unsigned int n)
4124{
4125 int size = 4;
4126 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4127 {
4128 size = 2;
4129 if (i.types[n] & Disp8)
4130 size = 1;
4131 if (i.types[n] & Disp64)
4132 size = 8;
4133 }
4134 return size;
4135}
4136
4137/* Return the size of the immediate operand N. */
4138
4139static int
4140imm_size (unsigned int n)
4141{
4142 int size = 4;
4143 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4144 {
4145 size = 2;
4146 if (i.types[n] & (Imm8 | Imm8S))
4147 size = 1;
4148 if (i.types[n] & Imm64)
4149 size = 8;
4150 }
4151 return size;
4152}
4153
29b0f896 4154static void
64e74474 4155output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4156{
4157 char *p;
4158 unsigned int n;
252b5132 4159
29b0f896
AM		 4160 for (n = 0; n < i.operands; n++)
4161 {
4162 if (i.types[n] & Disp)
4163 {
4164 if (i.op[n].disps->X_op == O_constant)
4165 {
e205caa7 4166 int size = disp_size (n);
29b0f896 4167 offsetT val;
252b5132 4168
29b0f896
AM		 4169 val = offset_in_range (i.op[n].disps->X_add_number,
4170 size);
4171 p = frag_more (size);
4172 md_number_to_chars (p, val, size);
4173 }
4174 else
4175 {
f86103b7 4176 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4177 int size = disp_size (n);
4178 int sign = (i.types[n] & Disp32S) != 0;
29b0f896
AM		 4179 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4180
e205caa7
L		 4181 /* We can't have 8 bit displacement here. */
4182 assert ((i.types[n] & Disp8) == 0);
4183
29b0f896
AM		 4184 /* The PC relative address is computed relative
4185 to the instruction boundary, so in case immediate
4186 fields follows, we need to adjust the value. */
4187 if (pcrel && i.imm_operands)
4188 {
29b0f896 4189 unsigned int n1;
e205caa7 4190 int sz = 0;
252b5132 4191
29b0f896
AM		 4192 for (n1 = 0; n1 < i.operands; n1++)
4193 if (i.types[n1] & Imm)
252b5132 4194 {
e205caa7
L		 4195 /* Only one immediate is allowed for PC
4196 relative address. */
4197 assert (sz == 0);
4198 sz = imm_size (n1);
4199 i.op[n].disps->X_add_number -= sz;
252b5132 4200 }
29b0f896 4201 /* We should find the immediate. */
e205caa7 4202 assert (sz != 0);
29b0f896 4203 }
520dc8e8 4204
29b0f896 4205 p = frag_more (size);
2bbd9c25 4206 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4207 if (GOT_symbol
2bbd9c25 4208 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4209 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4210 || reloc_type == BFD_RELOC_X86_64_32S
4211 || (reloc_type == BFD_RELOC_64
4212 && object_64bit))
d6ab8113
JB		 4213 && (i.op[n].disps->X_op == O_symbol
4214 || (i.op[n].disps->X_op == O_add
4215 && ((symbol_get_value_expression
4216 (i.op[n].disps->X_op_symbol)->X_op)
4217 == O_subtract))))
4218 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4219 {
4220 offsetT add;
4221
4222 if (insn_start_frag == frag_now)
4223 add = (p - frag_now->fr_literal) - insn_start_off;
4224 else
4225 {
4226 fragS *fr;
4227
4228 add = insn_start_frag->fr_fix - insn_start_off;
4229 for (fr = insn_start_frag->fr_next;
4230 fr && fr != frag_now; fr = fr->fr_next)
4231 add += fr->fr_fix;
4232 add += p - frag_now->fr_literal;
4233 }
4234
4fa24527 4235 if (!object_64bit)
7b81dfbb
AJ		 4236 {
4237 reloc_type = BFD_RELOC_386_GOTPC;
4238 i.op[n].imms->X_add_number += add;
4239 }
4240 else if (reloc_type == BFD_RELOC_64)
4241 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4242 else
7b81dfbb
AJ		 4243 /* Don't do the adjustment for x86-64, as there
4244 the pcrel addressing is relative to the _next_
4245 insn, and that is taken care of in other code. */
d6ab8113 4246 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4247 }
062cd5e7 4248 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4249 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4250 }
4251 }
4252 }
4253}
252b5132 4254
29b0f896 4255static void
64e74474 4256output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4257{
4258 char *p;
4259 unsigned int n;
252b5132 4260
29b0f896
AM		 4261 for (n = 0; n < i.operands; n++)
4262 {
4263 if (i.types[n] & Imm)
4264 {
4265 if (i.op[n].imms->X_op == O_constant)
4266 {
e205caa7 4267 int size = imm_size (n);
29b0f896 4268 offsetT val;
b4cac588 4269
29b0f896
AM		 4270 val = offset_in_range (i.op[n].imms->X_add_number,
4271 size);
4272 p = frag_more (size);
4273 md_number_to_chars (p, val, size);
4274 }
4275 else
4276 {
4277 /* Not absolute_section.
4278 Need a 32-bit fixup (don't support 8bit
4279 non-absolute imms). Try to support other
4280 sizes ... */
f86103b7 4281 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4282 int size = imm_size (n);
4283 int sign;
29b0f896
AM		 4284
4285 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4286 && (i.suffix == QWORD_MNEM_SUFFIX
4287 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896 4288 sign = 1;
e205caa7
L		 4289 else
4290 sign = 0;
520dc8e8 4291
29b0f896
AM		 4292 p = frag_more (size);
4293 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4294
2bbd9c25
JJ		 4295 /* This is tough to explain. We end up with this one if we
4296 * have operands that look like
4297 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4298 * obtain the absolute address of the GOT, and it is strongly
4299 * preferable from a performance point of view to avoid using
4300 * a runtime relocation for this. The actual sequence of
4301 * instructions often look something like:
4302 *
4303 * call .L66
4304 * .L66:
4305 * popl %ebx
4306 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4307 *
4308 * The call and pop essentially return the absolute address
4309 * of the label .L66 and store it in %ebx. The linker itself
4310 * will ultimately change the first operand of the addl so
4311 * that %ebx points to the GOT, but to keep things simple, the
4312 * .o file must have this operand set so that it generates not
4313 * the absolute address of .L66, but the absolute address of
4314 * itself. This allows the linker itself simply treat a GOTPC
4315 * relocation as asking for a pcrel offset to the GOT to be
4316 * added in, and the addend of the relocation is stored in the
4317 * operand field for the instruction itself.
4318 *
4319 * Our job here is to fix the operand so that it would add
4320 * the correct offset so that %ebx would point to itself. The
4321 * thing that is tricky is that .-.L66 will point to the
4322 * beginning of the instruction, so we need to further modify
4323 * the operand so that it will point to itself. There are
4324 * other cases where you have something like:
4325 *
4326 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4327 *
4328 * and here no correction would be required. Internally in
4329 * the assembler we treat operands of this form as not being
4330 * pcrel since the '.' is explicitly mentioned, and I wonder
4331 * whether it would simplify matters to do it this way. Who
4332 * knows. In earlier versions of the PIC patches, the
4333 * pcrel_adjust field was used to store the correction, but
4334 * since the expression is not pcrel, I felt it would be
4335 * confusing to do it this way. */
4336
d6ab8113 4337 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4338 || reloc_type == BFD_RELOC_X86_64_32S
4339 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4340 && GOT_symbol
4341 && GOT_symbol == i.op[n].imms->X_add_symbol
4342 && (i.op[n].imms->X_op == O_symbol
4343 || (i.op[n].imms->X_op == O_add
4344 && ((symbol_get_value_expression
4345 (i.op[n].imms->X_op_symbol)->X_op)
4346 == O_subtract))))
4347 {
2bbd9c25
JJ		 4348 offsetT add;
4349
4350 if (insn_start_frag == frag_now)
4351 add = (p - frag_now->fr_literal) - insn_start_off;
4352 else
4353 {
4354 fragS *fr;
4355
4356 add = insn_start_frag->fr_fix - insn_start_off;
4357 for (fr = insn_start_frag->fr_next;
4358 fr && fr != frag_now; fr = fr->fr_next)
4359 add += fr->fr_fix;
4360 add += p - frag_now->fr_literal;
4361 }
4362
4fa24527 4363 if (!object_64bit)
d6ab8113 4364 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4365 else if (size == 4)
d6ab8113 4366 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4367 else if (size == 8)
4368 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4369 i.op[n].imms->X_add_number += add;
29b0f896 4370 }
29b0f896
AM		 4371 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4372 i.op[n].imms, 0, reloc_type);
4373 }
4374 }
4375 }
252b5132
RH		 4376}
4377\f
d182319b
JB		 4378/* x86_cons_fix_new is called via the expression parsing code when a
4379 reloc is needed. We use this hook to get the correct .got reloc. */
4380static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4381static int cons_sign = -1;
4382
4383void
e3bb37b5 4384x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4385 expressionS *exp)
d182319b
JB		 4386{
4387 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4388
4389 got_reloc = NO_RELOC;
4390
4391#ifdef TE_PE
4392 if (exp->X_op == O_secrel)
4393 {
4394 exp->X_op = O_symbol;
4395 r = BFD_RELOC_32_SECREL;
4396 }
4397#endif
4398
4399 fix_new_exp (frag, off, len, exp, 0, r);
4400}
4401
718ddfc0
JB		 4402#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4403# define lex_got(reloc, adjust, types) NULL
4404#else
f3c180ae
AM		 4405/* Parse operands of the form
4406 <symbol>@GOTOFF+<nnn>
4407 and similar .plt or .got references.
4408
4409 If we find one, set up the correct relocation in RELOC and copy the
4410 input string, minus the `@GOTOFF' into a malloc'd buffer for
4411 parsing by the calling routine. Return this buffer, and if ADJUST
4412 is non-null set it to the length of the string we removed from the
4413 input line. Otherwise return NULL. */
4414static char *
3956db08 4415lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4416 int *adjust,
4417 unsigned int *types)
f3c180ae 4418{
7b81dfbb
AJ		 4419 /* Some of the relocations depend on the size of what field is to
4420 be relocated. But in our callers i386_immediate and i386_displacement
4421 we don't yet know the operand size (this will be set by insn
4422 matching). Hence we record the word32 relocation here,
4423 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4424 static const struct {
4425 const char *str;
4fa24527 4426 const enum bfd_reloc_code_real rel[2];
3956db08 4427 const unsigned int types64;
f3c180ae 4428 } gotrel[] = {
4eed87de
AM		 4429 { "PLTOFF", { 0,
4430 BFD_RELOC_X86_64_PLTOFF64 },
4431 Imm64 },
4432 { "PLT", { BFD_RELOC_386_PLT32,
4433 BFD_RELOC_X86_64_PLT32 },
4434 Imm32 | Imm32S | Disp32 },
4435 { "GOTPLT", { 0,
4436 BFD_RELOC_X86_64_GOTPLT64 },
4437 Imm64 | Disp64 },
4438 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4439 BFD_RELOC_X86_64_GOTOFF64 },
4440 Imm64 | Disp64 },
4441 { "GOTPCREL", { 0,
4442 BFD_RELOC_X86_64_GOTPCREL },
4443 Imm32 | Imm32S | Disp32 },
4444 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4445 BFD_RELOC_X86_64_TLSGD },
4446 Imm32 | Imm32S | Disp32 },
4447 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4448 0 },
4449 0 },
4450 { "TLSLD", { 0,
4451 BFD_RELOC_X86_64_TLSLD },
4452 Imm32 | Imm32S | Disp32 },
4453 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4454 BFD_RELOC_X86_64_GOTTPOFF },
4455 Imm32 | Imm32S | Disp32 },
4456 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4457 BFD_RELOC_X86_64_TPOFF32 },
4458 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4459 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4460 0 },
4461 0 },
4462 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4463 BFD_RELOC_X86_64_DTPOFF32 },
4464 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4465 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4466 0 },
4467 0 },
4468 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4469 0 },
4470 0 },
4471 { "GOT", { BFD_RELOC_386_GOT32,
4472 BFD_RELOC_X86_64_GOT32 },
4473 Imm32 | Imm32S | Disp32 | Imm64 },
4474 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4475 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4476 Imm32 | Imm32S | Disp32 },
4477 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4478 BFD_RELOC_X86_64_TLSDESC_CALL },
4479 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4480 };
4481 char *cp;
4482 unsigned int j;
4483
718ddfc0
JB		 4484 if (!IS_ELF)
4485 return NULL;
4486
f3c180ae
AM		 4487 for (cp = input_line_pointer; *cp != '@'; cp++)
4488 if (is_end_of_line[(unsigned char) *cp])
4489 return NULL;
4490
4491 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4492 {
4493 int len;
4494
4495 len = strlen (gotrel[j].str);
28f81592 4496 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4497 {
4fa24527 4498 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4499 {
28f81592
AM		 4500 int first, second;
4501 char *tmpbuf, *past_reloc;
f3c180ae 4502
4fa24527 4503 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4504 if (adjust)
4505 *adjust = len;
f3c180ae 4506
3956db08
JB		 4507 if (types)
4508 {
4509 if (flag_code != CODE_64BIT)
4eed87de 4510 *types = Imm32 | Disp32;
3956db08
JB		 4511 else
4512 *types = gotrel[j].types64;
4513 }
4514
f3c180ae
AM		 4515 if (GOT_symbol == NULL)
4516 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4517
28f81592 4518 /* The length of the first part of our input line. */
f3c180ae 4519 first = cp - input_line_pointer;
28f81592
AM		 4520
4521 /* The second part goes from after the reloc token until
4522 (and including) an end_of_line char. Don't use strlen
4523 here as the end_of_line char may not be a NUL. */
4524 past_reloc = cp + 1 + len;
4525 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4526 ;
4527 second = cp - past_reloc;
4528
4529 /* Allocate and copy string. The trailing NUL shouldn't
4530 be necessary, but be safe. */
4531 tmpbuf = xmalloc (first + second + 2);
f3c180ae 4532 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 4533 if (second != 0 && *past_reloc != ' ')
4534 /* Replace the relocation token with ' ', so that
4535 errors like foo@GOTOFF1 will be detected. */
4536 tmpbuf[first++] = ' ';
4537 memcpy (tmpbuf + first, past_reloc, second);
4538 tmpbuf[first + second] = '\0';
f3c180ae
AM		 4539 return tmpbuf;
4540 }
4541
4fa24527
JB		 4542 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4543 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4544 return NULL;
4545 }
4546 }
4547
4548 /* Might be a symbol version string. Don't as_bad here. */
4549 return NULL;
4550}
4551
f3c180ae 4552void
e3bb37b5 4553x86_cons (expressionS *exp, int size)
f3c180ae 4554{
4fa24527 4555 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4556 {
4557 /* Handle @GOTOFF and the like in an expression. */
4558 char *save;
4559 char *gotfree_input_line;
4560 int adjust;
4561
4562 save = input_line_pointer;
3956db08 4563 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4564 if (gotfree_input_line)
4565 input_line_pointer = gotfree_input_line;
4566
4567 expression (exp);
4568
4569 if (gotfree_input_line)
4570 {
4571 /* expression () has merrily parsed up to the end of line,
4572 or a comma - in the wrong buffer. Transfer how far
4573 input_line_pointer has moved to the right buffer. */
4574 input_line_pointer = (save
4575 + (input_line_pointer - gotfree_input_line)
4576 + adjust);
4577 free (gotfree_input_line);
3992d3b7
AM		 4578 if (exp->X_op == O_constant
4579 || exp->X_op == O_absent
4580 || exp->X_op == O_illegal
4581 || exp->X_op == O_register
4582 || exp->X_op == O_big)
4583 {
4584 char c = *input_line_pointer;
4585 *input_line_pointer = 0;
4586 as_bad (_("missing or invalid expression `%s'"), save);
4587 *input_line_pointer = c;
4588 }
f3c180ae
AM		 4589 }
4590 }
4591 else
4592 expression (exp);
4593}
4594#endif
4595
d182319b 4596static void signed_cons (int size)
6482c264 4597{
d182319b
JB		 4598 if (flag_code == CODE_64BIT)
4599 cons_sign = 1;
4600 cons (size);
4601 cons_sign = -1;
6482c264
NC		 4602}
4603
d182319b 4604#ifdef TE_PE
6482c264
NC		 4605static void
4606pe_directive_secrel (dummy)
4607 int dummy ATTRIBUTE_UNUSED;
4608{
4609 expressionS exp;
4610
4611 do
4612 {
4613 expression (&exp);
4614 if (exp.X_op == O_symbol)
4615 exp.X_op = O_secrel;
4616
4617 emit_expr (&exp, 4);
4618 }
4619 while (*input_line_pointer++ == ',');
4620
4621 input_line_pointer--;
4622 demand_empty_rest_of_line ();
4623}
6482c264
NC		 4624#endif
4625
252b5132 4626static int
70e41ade 4627i386_immediate (char *imm_start)
252b5132
RH		 4628{
4629 char *save_input_line_pointer;
f3c180ae 4630 char *gotfree_input_line;
252b5132 4631 segT exp_seg = 0;
47926f60 4632 expressionS *exp;
3956db08 4633 unsigned int types = ~0U;
252b5132
RH		 4634
4635 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4636 {
31b2323c
L		 4637 as_bad (_("at most %d immediate operands are allowed"),
4638 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4639 return 0;
4640 }
4641
4642 exp = &im_expressions[i.imm_operands++];
520dc8e8 4643 i.op[this_operand].imms = exp;
252b5132
RH		 4644
4645 if (is_space_char (*imm_start))
4646 ++imm_start;
4647
4648 save_input_line_pointer = input_line_pointer;
4649 input_line_pointer = imm_start;
4650
3956db08 4651 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4652 if (gotfree_input_line)
4653 input_line_pointer = gotfree_input_line;
252b5132
RH		 4654
4655 exp_seg = expression (exp);
4656
83183c0c 4657 SKIP_WHITESPACE ();
252b5132 4658 if (*input_line_pointer)
f3c180ae 4659 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4660
4661 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4662 if (gotfree_input_line)
4663 free (gotfree_input_line);
252b5132 4664
3992d3b7
AM		 4665 if (exp->X_op == O_absent
4666 || exp->X_op == O_illegal
4667 || exp->X_op == O_big
4668 || (gotfree_input_line
4669 && (exp->X_op == O_constant
4670 || exp->X_op == O_register)))
252b5132 4671 {
3992d3b7 4672 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 4673 imm_start);
3992d3b7 4674 return 0;
252b5132 4675 }
3e73aa7c 4676 else if (exp->X_op == O_constant)
252b5132 4677 {
47926f60 4678 /* Size it properly later. */
3e73aa7c
JH		 4679 i.types[this_operand] |= Imm64;
4680 /* If BFD64, sign extend val. */
4eed87de
AM		 4681 if (!use_rela_relocations
4682 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4683 exp->X_add_number
4684 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4685 }
4c63da97 4686#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4687 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4688 && exp_seg != absolute_section
47926f60 4689 && exp_seg != text_section
24eab124
AM		 4690 && exp_seg != data_section
4691 && exp_seg != bss_section
4692 && exp_seg != undefined_section
f86103b7 4693 && !bfd_is_com_section (exp_seg))
252b5132 4694 {
d0b47220 4695 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4696 return 0;
4697 }
4698#endif
bb8f5920
L		 4699 else if (!intel_syntax && exp->X_op == O_register)
4700 {
4701 as_bad (_("illegal immediate register operand %s"), imm_start);
4702 return 0;
4703 }
252b5132
RH		 4704 else
4705 {
4706 /* This is an address. The size of the address will be
24eab124 4707 determined later, depending on destination register,
3e73aa7c
JH		 4708 suffix, or the default for the section. */
4709 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4710 i.types[this_operand] &= types;
252b5132
RH		 4711 }
4712
4713 return 1;
4714}
4715
551c1ca1 4716static char *
e3bb37b5 4717i386_scale (char *scale)
252b5132 4718{
551c1ca1
AM		 4719 offsetT val;
4720 char *save = input_line_pointer;
252b5132 4721
551c1ca1
AM		 4722 input_line_pointer = scale;
4723 val = get_absolute_expression ();
4724
4725 switch (val)
252b5132 4726 {
551c1ca1 4727 case 1:
252b5132
RH		 4728 i.log2_scale_factor = 0;
4729 break;
551c1ca1 4730 case 2:
252b5132
RH		 4731 i.log2_scale_factor = 1;
4732 break;
551c1ca1 4733 case 4:
252b5132
RH		 4734 i.log2_scale_factor = 2;
4735 break;
551c1ca1 4736 case 8:
252b5132
RH		 4737 i.log2_scale_factor = 3;
4738 break;
4739 default:
a724f0f4
JB		 4740 {
4741 char sep = *input_line_pointer;
4742
4743 *input_line_pointer = '\0';
4744 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4745 scale);
4746 *input_line_pointer = sep;
4747 input_line_pointer = save;
4748 return NULL;
4749 }
252b5132 4750 }
29b0f896 4751 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4752 {
4753 as_warn (_("scale factor of %d without an index register"),
24eab124 4754 1 << i.log2_scale_factor);
252b5132
RH		 4755#if SCALE1_WHEN_NO_INDEX
4756 i.log2_scale_factor = 0;
4757#endif
4758 }
551c1ca1
AM		 4759 scale = input_line_pointer;
4760 input_line_pointer = save;
4761 return scale;
252b5132
RH		 4762}
4763
252b5132 4764static int
e3bb37b5 4765i386_displacement (char *disp_start, char *disp_end)
252b5132 4766{
29b0f896 4767 expressionS *exp;
252b5132
RH		 4768 segT exp_seg = 0;
4769 char *save_input_line_pointer;
f3c180ae 4770 char *gotfree_input_line;
e05278af 4771 int bigdisp, override;
3956db08 4772 unsigned int types = Disp;
3992d3b7 4773 int ret;
252b5132 4774
31b2323c
L		 4775 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4776 {
4777 as_bad (_("at most %d displacement operands are allowed"),
4778 MAX_MEMORY_OPERANDS);
4779 return 0;
4780 }
4781
e05278af
JB		 4782 if ((i.types[this_operand] & JumpAbsolute)
4783 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4784 {
4785 bigdisp = Disp32;
4786 override = (i.prefix[ADDR_PREFIX] != 0);
4787 }
4788 else
4789 {
4790 /* For PC-relative branches, the width of the displacement
4791 is dependent upon data size, not address size. */
4792 bigdisp = 0;
4793 override = (i.prefix[DATA_PREFIX] != 0);
4794 }
3e73aa7c 4795 if (flag_code == CODE_64BIT)
7ecd2f8b 4796 {
e05278af 4797 if (!bigdisp)
64e74474
AM		 4798 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4799 ? Disp16
4800 : Disp32S | Disp32);
e05278af 4801 else if (!override)
3956db08 4802 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4803 }
e05278af
JB		 4804 else
4805 {
4806 if (!bigdisp)
4807 {
4808 if (!override)
4809 override = (i.suffix == (flag_code != CODE_16BIT
4810 ? WORD_MNEM_SUFFIX
4811 : LONG_MNEM_SUFFIX));
4812 bigdisp = Disp32;
4813 }
4814 if ((flag_code == CODE_16BIT) ^ override)
4815 bigdisp = Disp16;
4816 }
252b5132
RH		 4817 i.types[this_operand] |= bigdisp;
4818
4819 exp = &disp_expressions[i.disp_operands];
520dc8e8 4820 i.op[this_operand].disps = exp;
252b5132
RH		 4821 i.disp_operands++;
4822 save_input_line_pointer = input_line_pointer;
4823 input_line_pointer = disp_start;
4824 END_STRING_AND_SAVE (disp_end);
4825
4826#ifndef GCC_ASM_O_HACK
4827#define GCC_ASM_O_HACK 0
4828#endif
4829#if GCC_ASM_O_HACK
4830 END_STRING_AND_SAVE (disp_end + 1);
4831 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4832 && displacement_string_end[-1] == '+')
252b5132
RH		 4833 {
4834 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4835 constraint within gcc asm statements.
4836 For instance:
4837
4838 #define _set_tssldt_desc(n,addr,limit,type) \
4839 __asm__ __volatile__ ( \
4840 "movw %w2,%0\n\t" \
4841 "movw %w1,2+%0\n\t" \
4842 "rorl $16,%1\n\t" \
4843 "movb %b1,4+%0\n\t" \
4844 "movb %4,5+%0\n\t" \
4845 "movb $0,6+%0\n\t" \
4846 "movb %h1,7+%0\n\t" \
4847 "rorl $16,%1" \
4848 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4849
4850 This works great except that the output assembler ends
4851 up looking a bit weird if it turns out that there is
4852 no offset. You end up producing code that looks like:
4853
4854 #APP
4855 movw $235,(%eax)
4856 movw %dx,2+(%eax)
4857 rorl $16,%edx
4858 movb %dl,4+(%eax)
4859 movb $137,5+(%eax)
4860 movb $0,6+(%eax)
4861 movb %dh,7+(%eax)
4862 rorl $16,%edx
4863 #NO_APP
4864
47926f60 4865 So here we provide the missing zero. */
24eab124
AM		 4866
4867 *displacement_string_end = '0';
252b5132
RH		 4868 }
4869#endif
3956db08 4870 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4871 if (gotfree_input_line)
4872 input_line_pointer = gotfree_input_line;
252b5132 4873
24eab124 4874 exp_seg = expression (exp);
252b5132 4875
636c26b0
AM		 4876 SKIP_WHITESPACE ();
4877 if (*input_line_pointer)
4878 as_bad (_("junk `%s' after expression"), input_line_pointer);
4879#if GCC_ASM_O_HACK
4880 RESTORE_END_STRING (disp_end + 1);
4881#endif
636c26b0 4882 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4883 if (gotfree_input_line)
4884 free (gotfree_input_line);
3992d3b7 4885 ret = 1;
636c26b0 4886
24eab124
AM		 4887 /* We do this to make sure that the section symbol is in
4888 the symbol table. We will ultimately change the relocation
47926f60 4889 to be relative to the beginning of the section. */
1ae12ab7 4890 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4891 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4892 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4893 {
636c26b0 4894 if (exp->X_op != O_symbol)
3992d3b7 4895 goto inv_disp;
636c26b0 4896
e5cb08ac 4897 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4898 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4899 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4900 exp->X_op = O_subtract;
4901 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4902 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4903 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4904 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4905 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4906 else
29b0f896 4907 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4908 }
252b5132 4909
3992d3b7
AM		 4910 else if (exp->X_op == O_absent
4911 || exp->X_op == O_illegal
4912 || exp->X_op == O_big
4913 || (gotfree_input_line
4914 && (exp->X_op == O_constant
4915 || exp->X_op == O_register)))
2daf4fd8 4916 {
3992d3b7
AM		 4917 inv_disp:
4918 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 4919 disp_start);
3992d3b7 4920 ret = 0;
2daf4fd8
AM		 4921 }
4922
4c63da97 4923#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 4924 else if (exp->X_op != O_constant
4925 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4926 && exp_seg != absolute_section
4927 && exp_seg != text_section
4928 && exp_seg != data_section
4929 && exp_seg != bss_section
4930 && exp_seg != undefined_section
4931 && !bfd_is_com_section (exp_seg))
24eab124 4932 {
d0b47220 4933 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 4934 ret = 0;
24eab124 4935 }
252b5132 4936#endif
3956db08 4937
3992d3b7
AM		 4938 RESTORE_END_STRING (disp_end);
4939
3956db08
JB		 4940 if (!(i.types[this_operand] & ~Disp))
4941 i.types[this_operand] &= types;
4942
3992d3b7 4943 return ret;
252b5132
RH		 4944}
4945
eecb386c 4946/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4947 Return 1 on success, 0 on a failure. */
4948
252b5132 4949static int
e3bb37b5 4950i386_index_check (const char *operand_string)
252b5132 4951{
3e73aa7c 4952 int ok;
24eab124 4953#if INFER_ADDR_PREFIX
eecb386c
AM		 4954 int fudged = 0;
4955
24eab124
AM		 4956 tryprefix:
4957#endif
3e73aa7c 4958 ok = 1;
30123838
JB		 4959 if ((current_templates->start->cpu_flags & CpuSVME)
4960 && current_templates->end[-1].operand_types[0] == AnyMem)
4961 {
4962 /* Memory operands of SVME insns are special in that they only allow
4963 rAX as their memory address and ignore any segment override. */
4964 unsigned RegXX;
4965
4966 /* SKINIT is even more restrictive: it always requires EAX. */
4967 if (strcmp (current_templates->start->name, "skinit") == 0)
4968 RegXX = Reg32;
4969 else if (flag_code == CODE_64BIT)
4970 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4971 else
64e74474
AM		 4972 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4973 ? Reg16
4974 : Reg32);
30123838
JB		 4975 if (!i.base_reg
4976 || !(i.base_reg->reg_type & Acc)
4977 || !(i.base_reg->reg_type & RegXX)
4978 || i.index_reg
4979 || (i.types[0] & Disp))
4980 ok = 0;
4981 }
4982 else if (flag_code == CODE_64BIT)
64e74474
AM		 4983 {
4984 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4985
4986 if ((i.base_reg
4987 && ((i.base_reg->reg_type & RegXX) == 0)
4988 && (i.base_reg->reg_type != BaseIndex
4989 || i.index_reg))
4990 || (i.index_reg
4991 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4992 != (RegXX | BaseIndex))))
4993 ok = 0;
3e73aa7c
JH		 4994 }
4995 else
4996 {
4997 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4998 {
4999 /* 16bit checks. */
5000 if ((i.base_reg
29b0f896
AM		 5001 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
5002 != (Reg16 | BaseIndex)))
3e73aa7c 5003 || (i.index_reg
29b0f896
AM		 5004 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
5005 != (Reg16 | BaseIndex))
5006 || !(i.base_reg
5007 && i.base_reg->reg_num < 6
5008 && i.index_reg->reg_num >= 6
5009 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 5010 ok = 0;
5011 }
5012 else
e5cb08ac 5013 {
3e73aa7c
JH		 5014 /* 32bit checks. */
5015 if ((i.base_reg
5016 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
5017 || (i.index_reg
29b0f896
AM		 5018 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
5019 != (Reg32 | BaseIndex))))
e5cb08ac 5020 ok = 0;
3e73aa7c
JH		 5021 }
5022 }
5023 if (!ok)
24eab124
AM		 5024 {
5025#if INFER_ADDR_PREFIX
20f0a1fc 5026 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 5027 {
5028 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
5029 i.prefixes += 1;
b23bac36
AM		 5030 /* Change the size of any displacement too. At most one of
5031 Disp16 or Disp32 is set.
5032 FIXME. There doesn't seem to be any real need for separate
5033 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 5034 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 5035 if (flag_code != CODE_64BIT
5036 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 5037 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 5038 fudged = 1;
24eab124
AM		 5039 goto tryprefix;
5040 }
eecb386c
AM		 5041 if (fudged)
5042 as_bad (_("`%s' is not a valid base/index expression"),
5043 operand_string);
5044 else
c388dee8 5045#endif
eecb386c
AM		 5046 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5047 operand_string,
3e73aa7c 5048 flag_code_names[flag_code]);
24eab124 5049 }
20f0a1fc 5050 return ok;
24eab124 5051}
252b5132 5052
252b5132 5053/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 5054 on error. */
252b5132 5055
252b5132 5056static int
e3bb37b5 5057i386_operand (char *operand_string)
252b5132 5058{
af6bdddf
AM		 5059 const reg_entry *r;
5060 char *end_op;
24eab124 5061 char *op_string = operand_string;
252b5132 5062
24eab124 5063 if (is_space_char (*op_string))
252b5132
RH		 5064 ++op_string;
5065
24eab124 5066 /* We check for an absolute prefix (differentiating,
47926f60 5067 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5068 if (*op_string == ABSOLUTE_PREFIX)
5069 {
5070 ++op_string;
5071 if (is_space_char (*op_string))
5072 ++op_string;
5073 i.types[this_operand] |= JumpAbsolute;
5074 }
252b5132 5075
47926f60 5076 /* Check if operand is a register. */
4d1bb795 5077 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5078 {
24eab124
AM		 5079 /* Check for a segment override by searching for ':' after a
5080 segment register. */
5081 op_string = end_op;
5082 if (is_space_char (*op_string))
5083 ++op_string;
5084 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
5085 {
5086 switch (r->reg_num)
5087 {
5088 case 0:
5089 i.seg[i.mem_operands] = &es;
5090 break;
5091 case 1:
5092 i.seg[i.mem_operands] = &cs;
5093 break;
5094 case 2:
5095 i.seg[i.mem_operands] = &ss;
5096 break;
5097 case 3:
5098 i.seg[i.mem_operands] = &ds;
5099 break;
5100 case 4:
5101 i.seg[i.mem_operands] = &fs;
5102 break;
5103 case 5:
5104 i.seg[i.mem_operands] = &gs;
5105 break;
5106 }
252b5132 5107
24eab124 5108 /* Skip the ':' and whitespace. */
252b5132
RH		 5109 ++op_string;
5110 if (is_space_char (*op_string))
24eab124 5111 ++op_string;
252b5132 5112
24eab124
AM		 5113 if (!is_digit_char (*op_string)
5114 && !is_identifier_char (*op_string)
5115 && *op_string != '('
5116 && *op_string != ABSOLUTE_PREFIX)
5117 {
5118 as_bad (_("bad memory operand `%s'"), op_string);
5119 return 0;
5120 }
47926f60 5121 /* Handle case of %es:*foo. */
24eab124
AM		 5122 if (*op_string == ABSOLUTE_PREFIX)
5123 {
5124 ++op_string;
5125 if (is_space_char (*op_string))
5126 ++op_string;
5127 i.types[this_operand] |= JumpAbsolute;
5128 }
5129 goto do_memory_reference;
5130 }
5131 if (*op_string)
5132 {
d0b47220 5133 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5134 return 0;
5135 }
5136 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5137 i.op[this_operand].regs = r;
24eab124
AM		 5138 i.reg_operands++;
5139 }
af6bdddf
AM		 5140 else if (*op_string == REGISTER_PREFIX)
5141 {
5142 as_bad (_("bad register name `%s'"), op_string);
5143 return 0;
5144 }
24eab124 5145 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5146 {
24eab124
AM		 5147 ++op_string;
5148 if (i.types[this_operand] & JumpAbsolute)
5149 {
d0b47220 5150 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5151 return 0;
5152 }
5153 if (!i386_immediate (op_string))
5154 return 0;
5155 }
5156 else if (is_digit_char (*op_string)
5157 || is_identifier_char (*op_string)
e5cb08ac 5158 || *op_string == '(')
24eab124 5159 {
47926f60 5160 /* This is a memory reference of some sort. */
af6bdddf 5161 char *base_string;
252b5132 5162
47926f60 5163 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5164 char *displacement_string_start;
5165 char *displacement_string_end;
252b5132 5166
24eab124 5167 do_memory_reference:
24eab124
AM		 5168 if ((i.mem_operands == 1
5169 && (current_templates->start->opcode_modifier & IsString) == 0)
5170 || i.mem_operands == 2)
5171 {
5172 as_bad (_("too many memory references for `%s'"),
5173 current_templates->start->name);
5174 return 0;
5175 }
252b5132 5176
24eab124
AM		 5177 /* Check for base index form. We detect the base index form by
5178 looking for an ')' at the end of the operand, searching
5179 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5180 after the '('. */
af6bdddf 5181 base_string = op_string + strlen (op_string);
c3332e24 5182
af6bdddf
AM		 5183 --base_string;
5184 if (is_space_char (*base_string))
5185 --base_string;
252b5132 5186
47926f60 5187 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5188 displacement_string_start = op_string;
5189 displacement_string_end = base_string + 1;
252b5132 5190
24eab124
AM		 5191 if (*base_string == ')')
5192 {
af6bdddf 5193 char *temp_string;
24eab124
AM		 5194 unsigned int parens_balanced = 1;
5195 /* We've already checked that the number of left & right ()'s are
47926f60 5196 equal, so this loop will not be infinite. */
24eab124
AM		 5197 do
5198 {
5199 base_string--;
5200 if (*base_string == ')')
5201 parens_balanced++;
5202 if (*base_string == '(')
5203 parens_balanced--;
5204 }
5205 while (parens_balanced);
c3332e24 5206
af6bdddf 5207 temp_string = base_string;
c3332e24 5208
24eab124 5209 /* Skip past '(' and whitespace. */
252b5132
RH		 5210 ++base_string;
5211 if (is_space_char (*base_string))
24eab124 5212 ++base_string;
252b5132 5213
af6bdddf 5214 if (*base_string == ','
4eed87de
AM		 5215 || ((i.base_reg = parse_register (base_string, &end_op))
5216 != NULL))
252b5132 5217 {
af6bdddf 5218 displacement_string_end = temp_string;
252b5132 5219
af6bdddf 5220 i.types[this_operand] |= BaseIndex;
252b5132 5221
af6bdddf 5222 if (i.base_reg)
24eab124 5223 {
24eab124
AM		 5224 base_string = end_op;
5225 if (is_space_char (*base_string))
5226 ++base_string;
af6bdddf
AM		 5227 }
5228
5229 /* There may be an index reg or scale factor here. */
5230 if (*base_string == ',')
5231 {
5232 ++base_string;
5233 if (is_space_char (*base_string))
5234 ++base_string;
5235
4eed87de
AM		 5236 if ((i.index_reg = parse_register (base_string, &end_op))
5237 != NULL)
24eab124 5238 {
af6bdddf 5239 base_string = end_op;
24eab124
AM		 5240 if (is_space_char (*base_string))
5241 ++base_string;
af6bdddf
AM		 5242 if (*base_string == ',')
5243 {
5244 ++base_string;
5245 if (is_space_char (*base_string))
5246 ++base_string;
5247 }
e5cb08ac 5248 else if (*base_string != ')')
af6bdddf 5249 {
4eed87de
AM		 5250 as_bad (_("expecting `,' or `)' "
5251 "after index register in `%s'"),
af6bdddf
AM		 5252 operand_string);
5253 return 0;
5254 }
24eab124 5255 }
af6bdddf 5256 else if (*base_string == REGISTER_PREFIX)
24eab124 5257 {
af6bdddf 5258 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5259 return 0;
5260 }
252b5132 5261
47926f60 5262 /* Check for scale factor. */
551c1ca1 5263 if (*base_string != ')')
af6bdddf 5264 {
551c1ca1
AM		 5265 char *end_scale = i386_scale (base_string);
5266
5267 if (!end_scale)
af6bdddf 5268 return 0;
24eab124 5269
551c1ca1 5270 base_string = end_scale;
af6bdddf
AM		 5271 if (is_space_char (*base_string))
5272 ++base_string;
5273 if (*base_string != ')')
5274 {
4eed87de
AM		 5275 as_bad (_("expecting `)' "
5276 "after scale factor in `%s'"),
af6bdddf
AM		 5277 operand_string);
5278 return 0;
5279 }
5280 }
5281 else if (!i.index_reg)
24eab124 5282 {
4eed87de
AM		 5283 as_bad (_("expecting index register or scale factor "
5284 "after `,'; got '%c'"),
af6bdddf 5285 *base_string);
24eab124
AM		 5286 return 0;
5287 }
5288 }
af6bdddf 5289 else if (*base_string != ')')
24eab124 5290 {
4eed87de
AM		 5291 as_bad (_("expecting `,' or `)' "
5292 "after base register in `%s'"),
af6bdddf 5293 operand_string);
24eab124
AM		 5294 return 0;
5295 }
c3332e24 5296 }
af6bdddf 5297 else if (*base_string == REGISTER_PREFIX)
c3332e24 5298 {
af6bdddf 5299 as_bad (_("bad register name `%s'"), base_string);
24eab124 5300 return 0;
c3332e24 5301 }
24eab124
AM		 5302 }
5303
5304 /* If there's an expression beginning the operand, parse it,
5305 assuming displacement_string_start and
5306 displacement_string_end are meaningful. */
5307 if (displacement_string_start != displacement_string_end)
5308 {
5309 if (!i386_displacement (displacement_string_start,
5310 displacement_string_end))
5311 return 0;
5312 }
5313
5314 /* Special case for (%dx) while doing input/output op. */
5315 if (i.base_reg
5316 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5317 && i.index_reg == 0
5318 && i.log2_scale_factor == 0
5319 && i.seg[i.mem_operands] == 0
5320 && (i.types[this_operand] & Disp) == 0)
5321 {
5322 i.types[this_operand] = InOutPortReg;
5323 return 1;
5324 }
5325
eecb386c
AM		 5326 if (i386_index_check (operand_string) == 0)
5327 return 0;
24eab124
AM		 5328 i.mem_operands++;
5329 }
5330 else
ce8a8b2f
AM		 5331 {
5332 /* It's not a memory operand; argh! */
24eab124
AM		 5333 as_bad (_("invalid char %s beginning operand %d `%s'"),
5334 output_invalid (*op_string),
5335 this_operand + 1,
5336 op_string);
5337 return 0;
5338 }
47926f60 5339 return 1; /* Normal return. */
252b5132
RH		 5340}
5341\f
ee7fcc42
AM		 5342/* md_estimate_size_before_relax()
5343
5344 Called just before relax() for rs_machine_dependent frags. The x86
5345 assembler uses these frags to handle variable size jump
5346 instructions.
5347
5348 Any symbol that is now undefined will not become defined.
5349 Return the correct fr_subtype in the frag.
5350 Return the initial "guess for variable size of frag" to caller.
5351 The guess is actually the growth beyond the fixed part. Whatever
5352 we do to grow the fixed or variable part contributes to our
5353 returned value. */
5354
252b5132
RH		 5355int
5356md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5357 fragS *fragP;
5358 segT segment;
252b5132 5359{
252b5132 5360 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5361 check for un-relaxable symbols. On an ELF system, we can't relax
5362 an externally visible symbol, because it may be overridden by a
5363 shared library. */
5364 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5365#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5366 || (IS_ELF
31312f95
AM		 5367 && (S_IS_EXTERNAL (fragP->fr_symbol)
5368 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5369#endif
5370 )
252b5132 5371 {
b98ef147
AM		 5372 /* Symbol is undefined in this segment, or we need to keep a
5373 reloc so that weak symbols can be overridden. */
5374 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5375 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5376 unsigned char *opcode;
5377 int old_fr_fix;
f6af82bd 5378
ee7fcc42
AM		 5379 if (fragP->fr_var != NO_RELOC)
5380 reloc_type = fragP->fr_var;
b98ef147 5381 else if (size == 2)
f6af82bd
AM		 5382 reloc_type = BFD_RELOC_16_PCREL;
5383 else
5384 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5385
ee7fcc42
AM		 5386 old_fr_fix = fragP->fr_fix;
5387 opcode = (unsigned char *) fragP->fr_opcode;
5388
fddf5b5b 5389 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5390 {
fddf5b5b
AM		 5391 case UNCOND_JUMP:
5392 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5393 opcode[0] = 0xe9;
252b5132 5394 fragP->fr_fix += size;
062cd5e7
AS		 5395 fix_new (fragP, old_fr_fix, size,
5396 fragP->fr_symbol,
5397 fragP->fr_offset, 1,
5398 reloc_type);
252b5132
RH		 5399 break;
5400
fddf5b5b 5401 case COND_JUMP86:
412167cb
AM		 5402 if (size == 2
5403 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5404 {
5405 /* Negate the condition, and branch past an
5406 unconditional jump. */
5407 opcode[0] ^= 1;
5408 opcode[1] = 3;
5409 /* Insert an unconditional jump. */
5410 opcode[2] = 0xe9;
5411 /* We added two extra opcode bytes, and have a two byte
5412 offset. */
5413 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5414 fix_new (fragP, old_fr_fix + 2, 2,
5415 fragP->fr_symbol,
5416 fragP->fr_offset, 1,
5417 reloc_type);
fddf5b5b
AM		 5418 break;
5419 }
5420 /* Fall through. */
5421
5422 case COND_JUMP:
412167cb
AM		 5423 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5424 {
3e02c1cc
AM		 5425 fixS *fixP;
5426
412167cb 5427 fragP->fr_fix += 1;
3e02c1cc
AM		 5428 fixP = fix_new (fragP, old_fr_fix, 1,
5429 fragP->fr_symbol,
5430 fragP->fr_offset, 1,
5431 BFD_RELOC_8_PCREL);
5432 fixP->fx_signed = 1;
412167cb
AM		 5433 break;
5434 }
93c2a809 5435
24eab124 5436 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5437 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5438 opcode[1] = opcode[0] + 0x10;
f6af82bd 5439 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5440 /* We've added an opcode byte. */
5441 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5442 fix_new (fragP, old_fr_fix + 1, size,
5443 fragP->fr_symbol,
5444 fragP->fr_offset, 1,
5445 reloc_type);
252b5132 5446 break;
fddf5b5b
AM		 5447
5448 default:
5449 BAD_CASE (fragP->fr_subtype);
5450 break;
252b5132
RH		 5451 }
5452 frag_wane (fragP);
ee7fcc42 5453 return fragP->fr_fix - old_fr_fix;
252b5132 5454 }
93c2a809 5455
93c2a809
AM		 5456 /* Guess size depending on current relax state. Initially the relax
5457 state will correspond to a short jump and we return 1, because
5458 the variable part of the frag (the branch offset) is one byte
5459 long. However, we can relax a section more than once and in that
5460 case we must either set fr_subtype back to the unrelaxed state,
5461 or return the value for the appropriate branch. */
5462 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5463}
5464
47926f60
KH		 5465/* Called after relax() is finished.
5466
5467 In: Address of frag.
5468 fr_type == rs_machine_dependent.
5469 fr_subtype is what the address relaxed to.
5470
5471 Out: Any fixSs and constants are set up.
5472 Caller will turn frag into a ".space 0". */
5473
252b5132
RH		 5474void
5475md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5476 bfd *abfd ATTRIBUTE_UNUSED;
5477 segT sec ATTRIBUTE_UNUSED;
29b0f896 5478 fragS *fragP;
252b5132 5479{
29b0f896 5480 unsigned char *opcode;
252b5132 5481 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5482 offsetT target_address;
5483 offsetT opcode_address;
252b5132 5484 unsigned int extension = 0;
847f7ad4 5485 offsetT displacement_from_opcode_start;
252b5132
RH		 5486
5487 opcode = (unsigned char *) fragP->fr_opcode;
5488
47926f60 5489 /* Address we want to reach in file space. */
252b5132 5490 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5491
47926f60 5492 /* Address opcode resides at in file space. */
252b5132
RH		 5493 opcode_address = fragP->fr_address + fragP->fr_fix;
5494
47926f60 5495 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5496 displacement_from_opcode_start = target_address - opcode_address;
5497
fddf5b5b 5498 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5499 {
47926f60
KH		 5500 /* Don't have to change opcode. */
5501 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5502 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5503 }
5504 else
5505 {
5506 if (no_cond_jump_promotion
5507 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5508 as_warn_where (fragP->fr_file, fragP->fr_line,
5509 _("long jump required"));
252b5132 5510
fddf5b5b
AM		 5511 switch (fragP->fr_subtype)
5512 {
5513 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5514 extension = 4; /* 1 opcode + 4 displacement */
5515 opcode[0] = 0xe9;
5516 where_to_put_displacement = &opcode[1];
5517 break;
252b5132 5518
fddf5b5b
AM		 5519 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5520 extension = 2; /* 1 opcode + 2 displacement */
5521 opcode[0] = 0xe9;
5522 where_to_put_displacement = &opcode[1];
5523 break;
252b5132 5524
fddf5b5b
AM		 5525 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5526 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5527 extension = 5; /* 2 opcode + 4 displacement */
5528 opcode[1] = opcode[0] + 0x10;
5529 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5530 where_to_put_displacement = &opcode[2];
5531 break;
252b5132 5532
fddf5b5b
AM		 5533 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5534 extension = 3; /* 2 opcode + 2 displacement */
5535 opcode[1] = opcode[0] + 0x10;
5536 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5537 where_to_put_displacement = &opcode[2];
5538 break;
252b5132 5539
fddf5b5b
AM		 5540 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5541 extension = 4;
5542 opcode[0] ^= 1;
5543 opcode[1] = 3;
5544 opcode[2] = 0xe9;
5545 where_to_put_displacement = &opcode[3];
5546 break;
5547
5548 default:
5549 BAD_CASE (fragP->fr_subtype);
5550 break;
5551 }
252b5132 5552 }
fddf5b5b 5553
7b81dfbb
AJ		 5554 /* If size if less then four we are sure that the operand fits,
5555 but if it's 4, then it could be that the displacement is larger
5556 then -/+ 2GB. */
5557 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5558 && object_64bit
5559 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5560 + ((addressT) 1 << 31))
5561 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5562 {
5563 as_bad_where (fragP->fr_file, fragP->fr_line,
5564 _("jump target out of range"));
5565 /* Make us emit 0. */
5566 displacement_from_opcode_start = extension;
5567 }
47926f60 5568 /* Now put displacement after opcode. */
252b5132
RH		 5569 md_number_to_chars ((char *) where_to_put_displacement,
5570 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5571 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5572 fragP->fr_fix += extension;
5573}
5574\f
47926f60
KH		 5575/* Size of byte displacement jmp. */
5576int md_short_jump_size = 2;
5577
5578/* Size of dword displacement jmp. */
5579int md_long_jump_size = 5;
252b5132 5580
252b5132
RH		 5581void
5582md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5583 char *ptr;
5584 addressT from_addr, to_addr;
ab9da554
ILT		 5585 fragS *frag ATTRIBUTE_UNUSED;
5586 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5587{
847f7ad4 5588 offsetT offset;
252b5132
RH		 5589
5590 offset = to_addr - (from_addr + 2);
47926f60
KH		 5591 /* Opcode for byte-disp jump. */
5592 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5593 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5594}
5595
5596void
5597md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5598 char *ptr;
5599 addressT from_addr, to_addr;
a38cf1db
AM		 5600 fragS *frag ATTRIBUTE_UNUSED;
5601 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5602{
847f7ad4 5603 offsetT offset;
252b5132 5604
a38cf1db
AM		 5605 offset = to_addr - (from_addr + 5);
5606 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5607 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5608}
5609\f
5610/* Apply a fixup (fixS) to segment data, once it has been determined
5611 by our caller that we have all the info we need to fix it up.
5612
5613 On the 386, immediates, displacements, and data pointers are all in
5614 the same (little-endian) format, so we don't need to care about which
5615 we are handling. */
5616
94f592af 5617void
55cf6793 5618md_apply_fix (fixP, valP, seg)
47926f60
KH		 5619 /* The fix we're to put in. */
5620 fixS *fixP;
47926f60 5621 /* Pointer to the value of the bits. */
c6682705 5622 valueT *valP;
47926f60
KH		 5623 /* Segment fix is from. */
5624 segT seg ATTRIBUTE_UNUSED;
252b5132 5625{
94f592af 5626 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5627 valueT value = *valP;
252b5132 5628
f86103b7 5629#if !defined (TE_Mach)
93382f6d
AM		 5630 if (fixP->fx_pcrel)
5631 {
5632 switch (fixP->fx_r_type)
5633 {
5865bb77
ILT		 5634 default:
5635 break;
5636
d6ab8113
JB		 5637 case BFD_RELOC_64:
5638 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5639 break;
93382f6d 5640 case BFD_RELOC_32:
ae8887b5 5641 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5642 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5643 break;
5644 case BFD_RELOC_16:
5645 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5646 break;
5647 case BFD_RELOC_8:
5648 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5649 break;
5650 }
5651 }
252b5132 5652
a161fe53 5653 if (fixP->fx_addsy != NULL
31312f95 5654 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5655 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5656 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5657 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5658 && !use_rela_relocations)
252b5132 5659 {
31312f95
AM		 5660 /* This is a hack. There should be a better way to handle this.
5661 This covers for the fact that bfd_install_relocation will
5662 subtract the current location (for partial_inplace, PC relative
5663 relocations); see more below. */
252b5132 5664#ifndef OBJ_AOUT
718ddfc0 5665 if (IS_ELF
252b5132
RH		 5666#ifdef TE_PE
5667 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5668#endif
5669 )
5670 value += fixP->fx_where + fixP->fx_frag->fr_address;
5671#endif
5672#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5673 if (IS_ELF)
252b5132 5674 {
6539b54b 5675 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5676
6539b54b 5677 if ((sym_seg == seg
2f66722d 5678 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5679 && sym_seg != absolute_section))
ae6063d4 5680 && !generic_force_reloc (fixP))
2f66722d
AM		 5681 {
5682 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5683 bfd_install_relocation subtracts them out again. I think
5684 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5685 it. FIXME. */
5686 value += fixP->fx_where + fixP->fx_frag->fr_address;
5687 }
252b5132
RH		 5688 }
5689#endif
5690#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5691 /* For some reason, the PE format does not store a
5692 section address offset for a PC relative symbol. */
5693 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5694 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5695 value += md_pcrel_from (fixP);
5696#endif
5697 }
5698
5699 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5700 and we must not disappoint it. */
252b5132 5701#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5702 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5703 switch (fixP->fx_r_type)
5704 {
5705 case BFD_RELOC_386_PLT32:
3e73aa7c 5706 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5707 /* Make the jump instruction point to the address of the operand. At
5708 runtime we merely add the offset to the actual PLT entry. */
5709 value = -4;
5710 break;
31312f95 5711
13ae64f3
JJ		 5712 case BFD_RELOC_386_TLS_GD:
5713 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5714 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5715 case BFD_RELOC_386_TLS_IE:
5716 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5717 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5718 case BFD_RELOC_X86_64_TLSGD:
5719 case BFD_RELOC_X86_64_TLSLD:
5720 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5721 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5722 value = 0; /* Fully resolved at runtime. No addend. */
5723 /* Fallthrough */
5724 case BFD_RELOC_386_TLS_LE:
5725 case BFD_RELOC_386_TLS_LDO_32:
5726 case BFD_RELOC_386_TLS_LE_32:
5727 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5728 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5729 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5730 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5731 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5732 break;
5733
67a4f2b7
AO		 5734 case BFD_RELOC_386_TLS_DESC_CALL:
5735 case BFD_RELOC_X86_64_TLSDESC_CALL:
5736 value = 0; /* Fully resolved at runtime. No addend. */
5737 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5738 fixP->fx_done = 0;
5739 return;
5740
00f7efb6
JJ		 5741 case BFD_RELOC_386_GOT32:
5742 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5743 value = 0; /* Fully resolved at runtime. No addend. */
5744 break;
47926f60
KH		 5745
5746 case BFD_RELOC_VTABLE_INHERIT:
5747 case BFD_RELOC_VTABLE_ENTRY:
5748 fixP->fx_done = 0;
94f592af 5749 return;
47926f60
KH		 5750
5751 default:
5752 break;
5753 }
5754#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5755 *valP = value;
f86103b7 5756#endif /* !defined (TE_Mach) */
3e73aa7c 5757
3e73aa7c 5758 /* Are we finished with this relocation now? */
c6682705 5759 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5760 fixP->fx_done = 1;
5761 else if (use_rela_relocations)
5762 {
5763 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5764 /* Remember value for tc_gen_reloc. */
5765 fixP->fx_addnumber = value;
3e73aa7c
JH		 5766 value = 0;
5767 }
f86103b7 5768
94f592af 5769 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5770}
252b5132 5771\f
252b5132
RH		 5772#define MAX_LITTLENUMS 6
5773
47926f60
KH		 5774/* Turn the string pointed to by litP into a floating point constant
5775 of type TYPE, and emit the appropriate bytes. The number of
5776 LITTLENUMS emitted is stored in *SIZEP. An error message is
5777 returned, or NULL on OK. */
5778
252b5132
RH		 5779char *
5780md_atof (type, litP, sizeP)
2ab9b79e 5781 int type;
252b5132
RH		 5782 char *litP;
5783 int *sizeP;
5784{
5785 int prec;
5786 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5787 LITTLENUM_TYPE *wordP;
5788 char *t;
5789
5790 switch (type)
5791 {
5792 case 'f':
5793 case 'F':
5794 prec = 2;
5795 break;
5796
5797 case 'd':
5798 case 'D':
5799 prec = 4;
5800 break;
5801
5802 case 'x':
5803 case 'X':
5804 prec = 5;
5805 break;
5806
5807 default:
5808 *sizeP = 0;
5809 return _("Bad call to md_atof ()");
5810 }
5811 t = atof_ieee (input_line_pointer, type, words);
5812 if (t)
5813 input_line_pointer = t;
5814
5815 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5816 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5817 the bigendian 386. */
5818 for (wordP = words + prec - 1; prec--;)
5819 {
5820 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5821 litP += sizeof (LITTLENUM_TYPE);
5822 }
5823 return 0;
5824}
5825\f
2d545b82 5826static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5827
252b5132 5828static char *
e3bb37b5 5829output_invalid (int c)
252b5132 5830{
3882b010 5831 if (ISPRINT (c))
f9f21a03
L		 5832 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5833 "'%c'", c);
252b5132 5834 else
f9f21a03 5835 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5836 "(0x%x)", (unsigned char) c);
252b5132
RH		 5837 return output_invalid_buf;
5838}
5839
af6bdddf 5840/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5841
5842static const reg_entry *
4d1bb795 5843parse_real_register (char *reg_string, char **end_op)
252b5132 5844{
af6bdddf
AM		 5845 char *s = reg_string;
5846 char *p;
252b5132
RH		 5847 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5848 const reg_entry *r;
5849
5850 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5851 if (*s == REGISTER_PREFIX)
5852 ++s;
5853
5854 if (is_space_char (*s))
5855 ++s;
5856
5857 p = reg_name_given;
af6bdddf 5858 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5859 {
5860 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5861 return (const reg_entry *) NULL;
5862 s++;
252b5132
RH		 5863 }
5864
6588847e
DN		 5865 /* For naked regs, make sure that we are not dealing with an identifier.
5866 This prevents confusing an identifier like `eax_var' with register
5867 `eax'. */
5868 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5869 return (const reg_entry *) NULL;
5870
af6bdddf 5871 *end_op = s;
252b5132
RH		 5872
5873 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5874
5f47d35b 5875 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5876 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5877 {
5f47d35b
AM		 5878 if (is_space_char (*s))
5879 ++s;
5880 if (*s == '(')
5881 {
af6bdddf 5882 ++s;
5f47d35b
AM		 5883 if (is_space_char (*s))
5884 ++s;
5885 if (*s >= '0' && *s <= '7')
5886 {
db557034 5887 int fpr = *s - '0';
af6bdddf 5888 ++s;
5f47d35b
AM		 5889 if (is_space_char (*s))
5890 ++s;
5891 if (*s == ')')
5892 {
5893 *end_op = s + 1;
db557034
AM		 5894 r = hash_find (reg_hash, "st(0)");
5895 know (r);
5896 return r + fpr;
5f47d35b 5897 }
5f47d35b 5898 }
47926f60 5899 /* We have "%st(" then garbage. */
5f47d35b
AM		 5900 return (const reg_entry *) NULL;
5901 }
5902 }
5903
1ae00879 5904 if (r != NULL
20f0a1fc 5905 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5906 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5907 && flag_code != CODE_64BIT)
20f0a1fc 5908 return (const reg_entry *) NULL;
1ae00879 5909
252b5132
RH		 5910 return r;
5911}
4d1bb795
JB		 5912
5913/* REG_STRING starts *before* REGISTER_PREFIX. */
5914
5915static const reg_entry *
5916parse_register (char *reg_string, char **end_op)
5917{
5918 const reg_entry *r;
5919
5920 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5921 r = parse_real_register (reg_string, end_op);
5922 else
5923 r = NULL;
5924 if (!r)
5925 {
5926 char *save = input_line_pointer;
5927 char c;
5928 symbolS *symbolP;
5929
5930 input_line_pointer = reg_string;
5931 c = get_symbol_end ();
5932 symbolP = symbol_find (reg_string);
5933 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5934 {
5935 const expressionS *e = symbol_get_value_expression (symbolP);
5936
5937 know (e->X_op == O_register);
4eed87de 5938 know (e->X_add_number >= 0
c3fe08fa 5939 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5940 r = i386_regtab + e->X_add_number;
5941 *end_op = input_line_pointer;
5942 }
5943 *input_line_pointer = c;
5944 input_line_pointer = save;
5945 }
5946 return r;
5947}
5948
5949int
5950i386_parse_name (char *name, expressionS *e, char *nextcharP)
5951{
5952 const reg_entry *r;
5953 char *end = input_line_pointer;
5954
5955 *end = *nextcharP;
5956 r = parse_register (name, &input_line_pointer);
5957 if (r && end <= input_line_pointer)
5958 {
5959 *nextcharP = *input_line_pointer;
5960 *input_line_pointer = 0;
5961 e->X_op = O_register;
5962 e->X_add_number = r - i386_regtab;
5963 return 1;
5964 }
5965 input_line_pointer = end;
5966 *end = 0;
5967 return 0;
5968}
5969
5970void
5971md_operand (expressionS *e)
5972{
5973 if (*input_line_pointer == REGISTER_PREFIX)
5974 {
5975 char *end;
5976 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5977
5978 if (r)
5979 {
5980 e->X_op = O_register;
5981 e->X_add_number = r - i386_regtab;
5982 input_line_pointer = end;
5983 }
5984 }
5985}
5986
252b5132 5987\f
4cc782b5 5988#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5989const char *md_shortopts = "kVQ:sqn";
252b5132 5990#else
12b55ccc 5991const char *md_shortopts = "qn";
252b5132 5992#endif
6e0b89ee 5993
3e73aa7c 5994#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5995#define OPTION_64 (OPTION_MD_BASE + 1)
5996#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5997#define OPTION_MARCH (OPTION_MD_BASE + 3)
5998#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5999
99ad8390
NC		 6000struct option md_longopts[] =
6001{
3e73aa7c 6002 {"32", no_argument, NULL, OPTION_32},
99ad8390 6003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6004 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6005#endif
b3b91714 6006 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6007 {"march", required_argument, NULL, OPTION_MARCH},
6008 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 6009 {NULL, no_argument, NULL, 0}
6010};
6011size_t md_longopts_size = sizeof (md_longopts);
6012
6013int
9103f4f4 6014md_parse_option (int c, char *arg)
252b5132 6015{
9103f4f4
L		 6016 unsigned int i;
6017
252b5132
RH		 6018 switch (c)
6019 {
12b55ccc
L		 6020 case 'n':
6021 optimize_align_code = 0;
6022 break;
6023
a38cf1db
AM		 6024 case 'q':
6025 quiet_warnings = 1;
252b5132
RH		 6026 break;
6027
6028#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 6029 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6030 should be emitted or not. FIXME: Not implemented. */
6031 case 'Q':
252b5132
RH		 6032 break;
6033
6034 /* -V: SVR4 argument to print version ID. */
6035 case 'V':
6036 print_version_id ();
6037 break;
6038
a38cf1db
AM		 6039 /* -k: Ignore for FreeBSD compatibility. */
6040 case 'k':
252b5132 6041 break;
4cc782b5
ILT		 6042
6043 case 's':
6044 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 6045 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 6046 break;
99ad8390
NC		 6047#endif
6048#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 6049 case OPTION_64:
6050 {
6051 const char **list, **l;
6052
3e73aa7c
JH		 6053 list = bfd_target_list ();
6054 for (l = list; *l != NULL; l++)
8620418b 6055 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 6056 || strcmp (*l, "coff-x86-64") == 0
6057 || strcmp (*l, "pe-x86-64") == 0
6058 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6059 {
6060 default_arch = "x86_64";
6061 break;
6062 }
3e73aa7c 6063 if (*l == NULL)
6e0b89ee 6064 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6065 free (list);
6066 }
6067 break;
6068#endif
252b5132 6069
6e0b89ee
AM		 6070 case OPTION_32:
6071 default_arch = "i386";
6072 break;
6073
b3b91714
AM		 6074 case OPTION_DIVIDE:
6075#ifdef SVR4_COMMENT_CHARS
6076 {
6077 char *n, *t;
6078 const char *s;
6079
6080 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6081 t = n;
6082 for (s = i386_comment_chars; *s != '\0'; s++)
6083 if (*s != '/')
6084 *t++ = *s;
6085 *t = '\0';
6086 i386_comment_chars = n;
6087 }
6088#endif
6089 break;
6090
9103f4f4
L		 6091 case OPTION_MARCH:
6092 if (*arg == '.')
6093 as_fatal (_("Invalid -march= option: `%s'"), arg);
6094 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6095 {
6096 if (strcmp (arg, cpu_arch [i].name) == 0)
6097 {
ccc9c027 6098 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6099 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6100 if (!cpu_arch_tune_set)
6101 {
6102 cpu_arch_tune = cpu_arch_isa;
6103 cpu_arch_tune_flags = cpu_arch_isa_flags;
6104 }
9103f4f4
L		 6105 break;
6106 }
6107 }
6108 if (i >= ARRAY_SIZE (cpu_arch))
6109 as_fatal (_("Invalid -march= option: `%s'"), arg);
6110 break;
6111
6112 case OPTION_MTUNE:
6113 if (*arg == '.')
6114 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6115 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6116 {
6117 if (strcmp (arg, cpu_arch [i].name) == 0)
6118 {
ccc9c027 6119 cpu_arch_tune_set = 1;
9103f4f4
L		 6120 cpu_arch_tune = cpu_arch [i].type;
6121 cpu_arch_tune_flags = cpu_arch[i].flags;
6122 break;
6123 }
6124 }
6125 if (i >= ARRAY_SIZE (cpu_arch))
6126 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6127 break;
6128
252b5132
RH		 6129 default:
6130 return 0;
6131 }
6132 return 1;
6133}
6134
6135void
6136md_show_usage (stream)
6137 FILE *stream;
6138{
4cc782b5
ILT		 6139#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6140 fprintf (stream, _("\
a38cf1db
AM		 6141 -Q ignored\n\
6142 -V print assembler version number\n\
b3b91714
AM		 6143 -k ignored\n"));
6144#endif
6145 fprintf (stream, _("\
12b55ccc 6146 -n Do not optimize code alignment\n\
b3b91714
AM		 6147 -q quieten some warnings\n"));
6148#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6149 fprintf (stream, _("\
a38cf1db 6150 -s ignored\n"));
b3b91714 6151#endif
751d281c
L		 6152#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6153 fprintf (stream, _("\
6154 --32/--64 generate 32bit/64bit code\n"));
6155#endif
b3b91714
AM		 6156#ifdef SVR4_COMMENT_CHARS
6157 fprintf (stream, _("\
6158 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6159#else
6160 fprintf (stream, _("\
b3b91714 6161 --divide ignored\n"));
4cc782b5 6162#endif
9103f4f4
L		 6163 fprintf (stream, _("\
6164 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6165 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6166 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6167
252b5132
RH		 6168}
6169
3e73aa7c 6170#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 6171 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 6172
6173/* Pick the target format to use. */
6174
47926f60 6175const char *
e3bb37b5 6176i386_target_format (void)
252b5132 6177{
3e73aa7c 6178 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6179 {
6180 set_code_flag (CODE_64BIT);
6181 if (cpu_arch_isa_flags == 0)
d32cad65 6182 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6183 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6184 |CpuSSE|CpuSSE2;
ccc9c027 6185 if (cpu_arch_tune_flags == 0)
d32cad65 6186 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6187 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6188 |CpuSSE|CpuSSE2;
9103f4f4 6189 }
3e73aa7c 6190 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6191 {
6192 set_code_flag (CODE_32BIT);
6193 if (cpu_arch_isa_flags == 0)
d32cad65 6194 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6195 if (cpu_arch_tune_flags == 0)
d32cad65 6196 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6197 }
3e73aa7c
JH		 6198 else
6199 as_fatal (_("Unknown architecture"));
252b5132
RH		 6200 switch (OUTPUT_FLAVOR)
6201 {
872ce6ff
L		 6202#ifdef TE_PEP
6203 case bfd_target_coff_flavour:
6204 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
6205 break;
6206#endif
4c63da97
AM		 6207#ifdef OBJ_MAYBE_AOUT
6208 case bfd_target_aout_flavour:
47926f60 6209 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6210#endif
6211#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6212 case bfd_target_coff_flavour:
6213 return "coff-i386";
4c63da97 6214#endif
3e73aa7c 6215#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6216 case bfd_target_elf_flavour:
3e73aa7c 6217 {
e5cb08ac 6218 if (flag_code == CODE_64BIT)
4fa24527
JB		 6219 {
6220 object_64bit = 1;
6221 use_rela_relocations = 1;
6222 }
9d7cbccd 6223 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6224 }
4c63da97 6225#endif
252b5132
RH		 6226 default:
6227 abort ();
6228 return NULL;
6229 }
6230}
6231
47926f60 6232#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6233
6234#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6235void
6236i386_elf_emit_arch_note (void)
a847613f 6237{
718ddfc0 6238 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6239 {
6240 char *p;
6241 asection *seg = now_seg;
6242 subsegT subseg = now_subseg;
6243 Elf_Internal_Note i_note;
6244 Elf_External_Note e_note;
6245 asection *note_secp;
6246 int len;
6247
6248 /* Create the .note section. */
6249 note_secp = subseg_new (".note", 0);
6250 bfd_set_section_flags (stdoutput,
6251 note_secp,
6252 SEC_HAS_CONTENTS | SEC_READONLY);
6253
6254 /* Process the arch string. */
6255 len = strlen (cpu_arch_name);
6256
6257 i_note.namesz = len + 1;
6258 i_note.descsz = 0;
6259 i_note.type = NT_ARCH;
6260 p = frag_more (sizeof (e_note.namesz));
6261 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6262 p = frag_more (sizeof (e_note.descsz));
6263 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6264 p = frag_more (sizeof (e_note.type));
6265 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6266 p = frag_more (len + 1);
6267 strcpy (p, cpu_arch_name);
6268
6269 frag_align (2, 0, 0);
6270
6271 subseg_set (seg, subseg);
6272 }
6273}
6274#endif
252b5132 6275\f
252b5132
RH		 6276symbolS *
6277md_undefined_symbol (name)
6278 char *name;
6279{
18dc2407
ILT		 6280 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6281 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6282 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6283 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6284 {
6285 if (!GOT_symbol)
6286 {
6287 if (symbol_find (name))
6288 as_bad (_("GOT already in symbol table"));
6289 GOT_symbol = symbol_new (name, undefined_section,
6290 (valueT) 0, &zero_address_frag);
6291 };
6292 return GOT_symbol;
6293 }
252b5132
RH		 6294 return 0;
6295}
6296
6297/* Round up a section size to the appropriate boundary. */
47926f60 6298
252b5132
RH		 6299valueT
6300md_section_align (segment, size)
ab9da554 6301 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6302 valueT size;
6303{
4c63da97
AM		 6304#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6305 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6306 {
6307 /* For a.out, force the section size to be aligned. If we don't do
6308 this, BFD will align it for us, but it will not write out the
6309 final bytes of the section. This may be a bug in BFD, but it is
6310 easier to fix it here since that is how the other a.out targets
6311 work. */
6312 int align;
6313
6314 align = bfd_get_section_alignment (stdoutput, segment);
6315 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6316 }
252b5132
RH		 6317#endif
6318
6319 return size;
6320}
6321
6322/* On the i386, PC-relative offsets are relative to the start of the
6323 next instruction. That is, the address of the offset, plus its
6324 size, since the offset is always the last part of the insn. */
6325
6326long
e3bb37b5 6327md_pcrel_from (fixS *fixP)
252b5132
RH		 6328{
6329 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6330}
6331
6332#ifndef I386COFF
6333
6334static void
e3bb37b5 6335s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6336{
29b0f896 6337 int temp;
252b5132 6338
8a75718c
JB		 6339#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6340 if (IS_ELF)
6341 obj_elf_section_change_hook ();
6342#endif
252b5132
RH		 6343 temp = get_absolute_expression ();
6344 subseg_set (bss_section, (subsegT) temp);
6345 demand_empty_rest_of_line ();
6346}
6347
6348#endif
6349
252b5132 6350void
e3bb37b5 6351i386_validate_fix (fixS *fixp)
252b5132
RH		 6352{
6353 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6354 {
23df1078
JH		 6355 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6356 {
4fa24527 6357 if (!object_64bit)
23df1078
JH		 6358 abort ();
6359 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6360 }
6361 else
6362 {
4fa24527 6363 if (!object_64bit)
d6ab8113
JB		 6364 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6365 else
6366 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6367 }
252b5132
RH		 6368 fixp->fx_subsy = 0;
6369 }
6370}
6371
252b5132
RH		 6372arelent *
6373tc_gen_reloc (section, fixp)
ab9da554 6374 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6375 fixS *fixp;
6376{
6377 arelent *rel;
6378 bfd_reloc_code_real_type code;
6379
6380 switch (fixp->fx_r_type)
6381 {
3e73aa7c
JH		 6382 case BFD_RELOC_X86_64_PLT32:
6383 case BFD_RELOC_X86_64_GOT32:
6384 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6385 case BFD_RELOC_386_PLT32:
6386 case BFD_RELOC_386_GOT32:
6387 case BFD_RELOC_386_GOTOFF:
6388 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6389 case BFD_RELOC_386_TLS_GD:
6390 case BFD_RELOC_386_TLS_LDM:
6391 case BFD_RELOC_386_TLS_LDO_32:
6392 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6393 case BFD_RELOC_386_TLS_IE:
6394 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6395 case BFD_RELOC_386_TLS_LE_32:
6396 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6397 case BFD_RELOC_386_TLS_GOTDESC:
6398 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6399 case BFD_RELOC_X86_64_TLSGD:
6400 case BFD_RELOC_X86_64_TLSLD:
6401 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6402 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6403 case BFD_RELOC_X86_64_GOTTPOFF:
6404 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6405 case BFD_RELOC_X86_64_TPOFF64:
6406 case BFD_RELOC_X86_64_GOTOFF64:
6407 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6408 case BFD_RELOC_X86_64_GOT64:
6409 case BFD_RELOC_X86_64_GOTPCREL64:
6410 case BFD_RELOC_X86_64_GOTPC64:
6411 case BFD_RELOC_X86_64_GOTPLT64:
6412 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6413 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6414 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6415 case BFD_RELOC_RVA:
6416 case BFD_RELOC_VTABLE_ENTRY:
6417 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6418#ifdef TE_PE
6419 case BFD_RELOC_32_SECREL:
6420#endif
252b5132
RH		 6421 code = fixp->fx_r_type;
6422 break;
dbbaec26
L		 6423 case BFD_RELOC_X86_64_32S:
6424 if (!fixp->fx_pcrel)
6425 {
6426 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6427 code = fixp->fx_r_type;
6428 break;
6429 }
252b5132 6430 default:
93382f6d 6431 if (fixp->fx_pcrel)
252b5132 6432 {
93382f6d
AM		 6433 switch (fixp->fx_size)
6434 {
6435 default:
b091f402
AM		 6436 as_bad_where (fixp->fx_file, fixp->fx_line,
6437 _("can not do %d byte pc-relative relocation"),
6438 fixp->fx_size);
93382f6d
AM		 6439 code = BFD_RELOC_32_PCREL;
6440 break;
6441 case 1: code = BFD_RELOC_8_PCREL; break;
6442 case 2: code = BFD_RELOC_16_PCREL; break;
6443 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6444#ifdef BFD64
6445 case 8: code = BFD_RELOC_64_PCREL; break;
6446#endif
93382f6d
AM		 6447 }
6448 }
6449 else
6450 {
6451 switch (fixp->fx_size)
6452 {
6453 default:
b091f402
AM		 6454 as_bad_where (fixp->fx_file, fixp->fx_line,
6455 _("can not do %d byte relocation"),
6456 fixp->fx_size);
93382f6d
AM		 6457 code = BFD_RELOC_32;
6458 break;
6459 case 1: code = BFD_RELOC_8; break;
6460 case 2: code = BFD_RELOC_16; break;
6461 case 4: code = BFD_RELOC_32; break;
937149dd 6462#ifdef BFD64
3e73aa7c 6463 case 8: code = BFD_RELOC_64; break;
937149dd 6464#endif
93382f6d 6465 }
252b5132
RH		 6466 }
6467 break;
6468 }
252b5132 6469
d182319b
JB		 6470 if ((code == BFD_RELOC_32
6471 || code == BFD_RELOC_32_PCREL
6472 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6473 && GOT_symbol
6474 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6475 {
4fa24527 6476 if (!object_64bit)
d6ab8113
JB		 6477 code = BFD_RELOC_386_GOTPC;
6478 else
6479 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6480 }
7b81dfbb
AJ		 6481 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6482 && GOT_symbol
6483 && fixp->fx_addsy == GOT_symbol)
6484 {
6485 code = BFD_RELOC_X86_64_GOTPC64;
6486 }
252b5132
RH		 6487
6488 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6489 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6490 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6491
6492 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6493
3e73aa7c
JH		 6494 if (!use_rela_relocations)
6495 {
6496 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6497 vtable entry to be used in the relocation's section offset. */
6498 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6499 rel->address = fixp->fx_offset;
252b5132 6500
c6682705 6501 rel->addend = 0;
3e73aa7c
JH		 6502 }
6503 /* Use the rela in 64bit mode. */
252b5132 6504 else
3e73aa7c 6505 {
062cd5e7
AS		 6506 if (!fixp->fx_pcrel)
6507 rel->addend = fixp->fx_offset;
6508 else
6509 switch (code)
6510 {
6511 case BFD_RELOC_X86_64_PLT32:
6512 case BFD_RELOC_X86_64_GOT32:
6513 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6514 case BFD_RELOC_X86_64_TLSGD:
6515 case BFD_RELOC_X86_64_TLSLD:
6516 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6517 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6518 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6519 rel->addend = fixp->fx_offset - fixp->fx_size;
6520 break;
6521 default:
6522 rel->addend = (section->vma
6523 - fixp->fx_size
6524 + fixp->fx_addnumber
6525 + md_pcrel_from (fixp));
6526 break;
6527 }
3e73aa7c
JH		 6528 }
6529
252b5132
RH		 6530 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6531 if (rel->howto == NULL)
6532 {
6533 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6534 _("cannot represent relocation type %s"),
252b5132
RH		 6535 bfd_get_reloc_code_name (code));
6536 /* Set howto to a garbage value so that we can keep going. */
6537 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6538 assert (rel->howto != NULL);
6539 }
6540
6541 return rel;
6542}
6543
64a0c779
DN		 6544\f
6545/* Parse operands using Intel syntax. This implements a recursive descent
6546 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6547 Programmer's Guide.
6548
6549 FIXME: We do not recognize the full operand grammar defined in the MASM
6550 documentation. In particular, all the structure/union and
6551 high-level macro operands are missing.
6552
6553 Uppercase words are terminals, lower case words are non-terminals.
6554 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6555 bars '|' denote choices. Most grammar productions are implemented in
6556 functions called 'intel_<production>'.
6557
6558 Initial production is 'expr'.
6559
9306ca4a 6560 addOp + | -
64a0c779
DN		 6561
6562 alpha [a-zA-Z]
6563
9306ca4a
JB		 6564 binOp & | AND | \| | OR | ^ | XOR
6565
64a0c779
DN		 6566 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6567
6568 constant digits [[ radixOverride ]]
6569
9306ca4a 6570 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6571
6572 digits decdigit
b77a7acd
AJ		 6573 | digits decdigit
6574 | digits hexdigit
64a0c779
DN		 6575
6576 decdigit [0-9]
6577
9306ca4a
JB		 6578 e04 e04 addOp e05
6579 | e05
6580
6581 e05 e05 binOp e06
b77a7acd 6582 | e06
64a0c779
DN		 6583
6584 e06 e06 mulOp e09
b77a7acd 6585 | e09
64a0c779
DN		 6586
6587 e09 OFFSET e10
a724f0f4
JB		 6588 | SHORT e10
6589 | + e10
6590 | - e10
9306ca4a
JB		 6591 | ~ e10
6592 | NOT e10
64a0c779
DN		 6593 | e09 PTR e10
6594 | e09 : e10
6595 | e10
6596
6597 e10 e10 [ expr ]
b77a7acd 6598 | e11
64a0c779
DN		 6599
6600 e11 ( expr )
b77a7acd 6601 | [ expr ]
64a0c779
DN		 6602 | constant
6603 | dataType
6604 | id
6605 | $
6606 | register
6607
a724f0f4 6608 => expr expr cmpOp e04
9306ca4a 6609 | e04
64a0c779
DN		 6610
6611 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6612 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6613
6614 hexdigit a | b | c | d | e | f
b77a7acd 6615 | A | B | C | D | E | F
64a0c779
DN		 6616
6617 id alpha
b77a7acd 6618 | id alpha
64a0c779
DN		 6619 | id decdigit
6620
9306ca4a 6621 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6622
6623 quote " | '
6624
6625 register specialRegister
b77a7acd 6626 | gpRegister
64a0c779
DN		 6627 | byteRegister
6628
6629 segmentRegister CS | DS | ES | FS | GS | SS
6630
9306ca4a 6631 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6632 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6633 | TR3 | TR4 | TR5 | TR6 | TR7
6634
64a0c779
DN		 6635 We simplify the grammar in obvious places (e.g., register parsing is
6636 done by calling parse_register) and eliminate immediate left recursion
6637 to implement a recursive-descent parser.
6638
a724f0f4
JB		 6639 expr e04 expr'
6640
6641 expr' cmpOp e04 expr'
6642 | Empty
9306ca4a
JB		 6643
6644 e04 e05 e04'
6645
6646 e04' addOp e05 e04'
6647 | Empty
64a0c779
DN		 6648
6649 e05 e06 e05'
6650
9306ca4a 6651 e05' binOp e06 e05'
b77a7acd 6652 | Empty
64a0c779
DN		 6653
6654 e06 e09 e06'
6655
6656 e06' mulOp e09 e06'
b77a7acd 6657 | Empty
64a0c779
DN		 6658
6659 e09 OFFSET e10 e09'
a724f0f4
JB		 6660 | SHORT e10'
6661 | + e10'
6662 | - e10'
6663 | ~ e10'
6664 | NOT e10'
b77a7acd 6665 | e10 e09'
64a0c779
DN		 6666
6667 e09' PTR e10 e09'
b77a7acd 6668 | : e10 e09'
64a0c779
DN		 6669 | Empty
6670
6671 e10 e11 e10'
6672
6673 e10' [ expr ] e10'
b77a7acd 6674 | Empty
64a0c779
DN		 6675
6676 e11 ( expr )
b77a7acd 6677 | [ expr ]
64a0c779
DN		 6678 | BYTE
6679 | WORD
6680 | DWORD
9306ca4a 6681 | FWORD
64a0c779 6682 | QWORD
9306ca4a
JB		 6683 | TBYTE
6684 | OWORD
6685 | XMMWORD
64a0c779
DN		 6686 | .
6687 | $
6688 | register
6689 | id
6690 | constant */
6691
6692/* Parsing structure for the intel syntax parser. Used to implement the
6693 semantic actions for the operand grammar. */
6694struct intel_parser_s
6695 {
6696 char *op_string; /* The string being parsed. */
6697 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6698 int op_modifier; /* Operand modifier. */
64a0c779 6699 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6700 int in_offset; /* >=1 if parsing operand of offset. */
6701 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6702 const reg_entry *reg; /* Last register reference found. */
6703 char *disp; /* Displacement string being built. */
a724f0f4 6704 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6705 };
6706
6707static struct intel_parser_s intel_parser;
6708
6709/* Token structure for parsing intel syntax. */
6710struct intel_token
6711 {
6712 int code; /* Token code. */
6713 const reg_entry *reg; /* Register entry for register tokens. */
6714 char *str; /* String representation. */
6715 };
6716
6717static struct intel_token cur_token, prev_token;
6718
50705ef4
AM		 6719/* Token codes for the intel parser. Since T_SHORT is already used
6720 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6721#define T_NIL -1
6722#define T_CONST 1
6723#define T_REG 2
6724#define T_BYTE 3
6725#define T_WORD 4
9306ca4a
JB		 6726#define T_DWORD 5
6727#define T_FWORD 6
6728#define T_QWORD 7
6729#define T_TBYTE 8
6730#define T_XMMWORD 9
50705ef4 6731#undef T_SHORT
9306ca4a
JB		 6732#define T_SHORT 10
6733#define T_OFFSET 11
6734#define T_PTR 12
6735#define T_ID 13
6736#define T_SHL 14
6737#define T_SHR 15
64a0c779
DN		 6738
6739/* Prototypes for intel parser functions. */
e3bb37b5
L		 6740static int intel_match_token (int);
6741static void intel_putback_token (void);
6742static void intel_get_token (void);
6743static int intel_expr (void);
6744static int intel_e04 (void);
6745static int intel_e05 (void);
6746static int intel_e06 (void);
6747static int intel_e09 (void);
6748static int intel_e10 (void);
6749static int intel_e11 (void);
64a0c779 6750
64a0c779 6751static int
e3bb37b5 6752i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6753{
6754 int ret;
6755 char *p;
6756
a724f0f4
JB		 6757 p = intel_parser.op_string = xstrdup (operand_string);
6758 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6759
6760 for (;;)
64a0c779 6761 {
a724f0f4
JB		 6762 /* Initialize token holders. */
6763 cur_token.code = prev_token.code = T_NIL;
6764 cur_token.reg = prev_token.reg = NULL;
6765 cur_token.str = prev_token.str = NULL;
6766
6767 /* Initialize parser structure. */
6768 intel_parser.got_a_float = got_a_float;
6769 intel_parser.op_modifier = 0;
6770 intel_parser.is_mem = 0;
6771 intel_parser.in_offset = 0;
6772 intel_parser.in_bracket = 0;
6773 intel_parser.reg = NULL;
6774 intel_parser.disp[0] = '\0';
6775 intel_parser.next_operand = NULL;
6776
6777 /* Read the first token and start the parser. */
6778 intel_get_token ();
6779 ret = intel_expr ();
6780
6781 if (!ret)
6782 break;
6783
9306ca4a
JB		 6784 if (cur_token.code != T_NIL)
6785 {
6786 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6787 current_templates->start->name, cur_token.str);
6788 ret = 0;
6789 }
64a0c779
DN		 6790 /* If we found a memory reference, hand it over to i386_displacement
6791 to fill in the rest of the operand fields. */
9306ca4a 6792 else if (intel_parser.is_mem)
64a0c779
DN		 6793 {
6794 if ((i.mem_operands == 1
6795 && (current_templates->start->opcode_modifier & IsString) == 0)
6796 || i.mem_operands == 2)
6797 {
6798 as_bad (_("too many memory references for '%s'"),
6799 current_templates->start->name);
6800 ret = 0;
6801 }
6802 else
6803 {
6804 char *s = intel_parser.disp;
6805 i.mem_operands++;
6806
a724f0f4
JB		 6807 if (!quiet_warnings && intel_parser.is_mem < 0)
6808 /* See the comments in intel_bracket_expr. */
6809 as_warn (_("Treating `%s' as memory reference"), operand_string);
6810
64a0c779
DN		 6811 /* Add the displacement expression. */
6812 if (*s != '\0')
a4622f40
AM		 6813 ret = i386_displacement (s, s + strlen (s));
6814 if (ret)
a724f0f4
JB		 6815 {
6816 /* Swap base and index in 16-bit memory operands like
6817 [si+bx]. Since i386_index_check is also used in AT&T
6818 mode we have to do that here. */
6819 if (i.base_reg
6820 && i.index_reg
6821 && (i.base_reg->reg_type & Reg16)
6822 && (i.index_reg->reg_type & Reg16)
6823 && i.base_reg->reg_num >= 6
6824 && i.index_reg->reg_num < 6)
6825 {
6826 const reg_entry *base = i.index_reg;
6827
6828 i.index_reg = i.base_reg;
6829 i.base_reg = base;
6830 }
6831 ret = i386_index_check (operand_string);
6832 }
64a0c779
DN		 6833 }
6834 }
6835
6836 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6837 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6838 || intel_parser.reg == NULL)
6839 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6840
6841 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6842 ret = 0;
a724f0f4
JB		 6843 if (!ret || !intel_parser.next_operand)
6844 break;
6845 intel_parser.op_string = intel_parser.next_operand;
6846 this_operand = i.operands++;
64a0c779
DN		 6847 }
6848
6849 free (p);
6850 free (intel_parser.disp);
6851
6852 return ret;
6853}
6854
a724f0f4
JB		 6855#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6856
6857/* expr e04 expr'
6858
6859 expr' cmpOp e04 expr'
6860 | Empty */
64a0c779 6861static int
e3bb37b5 6862intel_expr (void)
64a0c779 6863{
a724f0f4
JB		 6864 /* XXX Implement the comparison operators. */
6865 return intel_e04 ();
9306ca4a
JB		 6866}
6867
a724f0f4 6868/* e04 e05 e04'
9306ca4a 6869
a724f0f4 6870 e04' addOp e05 e04'
9306ca4a
JB		 6871 | Empty */
6872static int
e3bb37b5 6873intel_e04 (void)
9306ca4a 6874{
a724f0f4 6875 int nregs = -1;
9306ca4a 6876
a724f0f4 6877 for (;;)
9306ca4a 6878 {
a724f0f4
JB		 6879 if (!intel_e05())
6880 return 0;
9306ca4a 6881
a724f0f4
JB		 6882 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6883 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6884
a724f0f4
JB		 6885 if (cur_token.code == '+')
6886 nregs = -1;
6887 else if (cur_token.code == '-')
6888 nregs = NUM_ADDRESS_REGS;
6889 else
6890 return 1;
64a0c779 6891
a724f0f4
JB		 6892 strcat (intel_parser.disp, cur_token.str);
6893 intel_match_token (cur_token.code);
6894 }
64a0c779
DN		 6895}
6896
64a0c779
DN		 6897/* e05 e06 e05'
6898
9306ca4a 6899 e05' binOp e06 e05'
64a0c779
DN		 6900 | Empty */
6901static int
e3bb37b5 6902intel_e05 (void)
64a0c779 6903{
a724f0f4 6904 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6905
a724f0f4 6906 for (;;)
64a0c779 6907 {
a724f0f4
JB		 6908 if (!intel_e06())
6909 return 0;
6910
4eed87de
AM		 6911 if (cur_token.code == '&'
6912 || cur_token.code == '|'
6913 || cur_token.code == '^')
a724f0f4
JB		 6914 {
6915 char str[2];
6916
6917 str[0] = cur_token.code;
6918 str[1] = 0;
6919 strcat (intel_parser.disp, str);
6920 }
6921 else
6922 break;
9306ca4a 6923
64a0c779
DN		 6924 intel_match_token (cur_token.code);
6925
a724f0f4
JB		 6926 if (nregs < 0)
6927 nregs = ~nregs;
64a0c779 6928 }
a724f0f4
JB		 6929 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6930 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6931 return 1;
4a1805b1 6932}
64a0c779
DN		 6933
6934/* e06 e09 e06'
6935
6936 e06' mulOp e09 e06'
b77a7acd 6937 | Empty */
64a0c779 6938static int
e3bb37b5 6939intel_e06 (void)
64a0c779 6940{
a724f0f4 6941 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6942
a724f0f4 6943 for (;;)
64a0c779 6944 {
a724f0f4
JB		 6945 if (!intel_e09())
6946 return 0;
9306ca4a 6947
4eed87de
AM		 6948 if (cur_token.code == '*'
6949 || cur_token.code == '/'
6950 || cur_token.code == '%')
a724f0f4
JB		 6951 {
6952 char str[2];
9306ca4a 6953
a724f0f4
JB		 6954 str[0] = cur_token.code;
6955 str[1] = 0;
6956 strcat (intel_parser.disp, str);
6957 }
6958 else if (cur_token.code == T_SHL)
6959 strcat (intel_parser.disp, "<<");
6960 else if (cur_token.code == T_SHR)
6961 strcat (intel_parser.disp, ">>");
6962 else
6963 break;
9306ca4a 6964
64e74474 6965 intel_match_token (cur_token.code);
64a0c779 6966
a724f0f4
JB		 6967 if (nregs < 0)
6968 nregs = ~nregs;
64a0c779 6969 }
a724f0f4
JB		 6970 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6971 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6972 return 1;
64a0c779
DN		 6973}
6974
a724f0f4
JB		 6975/* e09 OFFSET e09
6976 | SHORT e09
6977 | + e09
6978 | - e09
6979 | ~ e09
6980 | NOT e09
9306ca4a
JB		 6981 | e10 e09'
6982
64a0c779 6983 e09' PTR e10 e09'
b77a7acd 6984 | : e10 e09'
64a0c779
DN		 6985 | Empty */
6986static int
e3bb37b5 6987intel_e09 (void)
64a0c779 6988{
a724f0f4
JB		 6989 int nregs = ~NUM_ADDRESS_REGS;
6990 int in_offset = 0;
6991
6992 for (;;)
64a0c779 6993 {
a724f0f4
JB		 6994 /* Don't consume constants here. */
6995 if (cur_token.code == '+' || cur_token.code == '-')
6996 {
6997 /* Need to look one token ahead - if the next token
6998 is a constant, the current token is its sign. */
6999 int next_code;
7000
7001 intel_match_token (cur_token.code);
7002 next_code = cur_token.code;
7003 intel_putback_token ();
7004 if (next_code == T_CONST)
7005 break;
7006 }
7007
7008 /* e09 OFFSET e09 */
7009 if (cur_token.code == T_OFFSET)
7010 {
7011 if (!in_offset++)
7012 ++intel_parser.in_offset;
7013 }
7014
7015 /* e09 SHORT e09 */
7016 else if (cur_token.code == T_SHORT)
7017 intel_parser.op_modifier |= 1 << T_SHORT;
7018
7019 /* e09 + e09 */
7020 else if (cur_token.code == '+')
7021 strcat (intel_parser.disp, "+");
7022
7023 /* e09 - e09
7024 | ~ e09
7025 | NOT e09 */
7026 else if (cur_token.code == '-' || cur_token.code == '~')
7027 {
7028 char str[2];
64a0c779 7029
a724f0f4
JB		 7030 if (nregs < 0)
7031 nregs = ~nregs;
7032 str[0] = cur_token.code;
7033 str[1] = 0;
7034 strcat (intel_parser.disp, str);
7035 }
7036
7037 /* e09 e10 e09' */
7038 else
7039 break;
7040
7041 intel_match_token (cur_token.code);
64a0c779
DN		 7042 }
7043
a724f0f4 7044 for (;;)
9306ca4a 7045 {
a724f0f4
JB		 7046 if (!intel_e10 ())
7047 return 0;
9306ca4a 7048
a724f0f4
JB		 7049 /* e09' PTR e10 e09' */
7050 if (cur_token.code == T_PTR)
7051 {
7052 char suffix;
9306ca4a 7053
a724f0f4
JB		 7054 if (prev_token.code == T_BYTE)
7055 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7056
a724f0f4
JB		 7057 else if (prev_token.code == T_WORD)
7058 {
7059 if (current_templates->start->name[0] == 'l'
7060 && current_templates->start->name[2] == 's'
7061 && current_templates->start->name[3] == 0)
7062 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7063 else if (intel_parser.got_a_float == 2) /* "fi..." */
7064 suffix = SHORT_MNEM_SUFFIX;
7065 else
7066 suffix = WORD_MNEM_SUFFIX;
7067 }
64a0c779 7068
a724f0f4
JB		 7069 else if (prev_token.code == T_DWORD)
7070 {
7071 if (current_templates->start->name[0] == 'l'
7072 && current_templates->start->name[2] == 's'
7073 && current_templates->start->name[3] == 0)
7074 suffix = WORD_MNEM_SUFFIX;
7075 else if (flag_code == CODE_16BIT
7076 && (current_templates->start->opcode_modifier
435acd52 7077 & (Jump | JumpDword)))
a724f0f4
JB		 7078 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7079 else if (intel_parser.got_a_float == 1) /* "f..." */
7080 suffix = SHORT_MNEM_SUFFIX;
7081 else
7082 suffix = LONG_MNEM_SUFFIX;
7083 }
9306ca4a 7084
a724f0f4
JB		 7085 else if (prev_token.code == T_FWORD)
7086 {
7087 if (current_templates->start->name[0] == 'l'
7088 && current_templates->start->name[2] == 's'
7089 && current_templates->start->name[3] == 0)
7090 suffix = LONG_MNEM_SUFFIX;
7091 else if (!intel_parser.got_a_float)
7092 {
7093 if (flag_code == CODE_16BIT)
7094 add_prefix (DATA_PREFIX_OPCODE);
7095 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7096 }
7097 else
7098 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7099 }
64a0c779 7100
a724f0f4
JB		 7101 else if (prev_token.code == T_QWORD)
7102 {
7103 if (intel_parser.got_a_float == 1) /* "f..." */
7104 suffix = LONG_MNEM_SUFFIX;
7105 else
7106 suffix = QWORD_MNEM_SUFFIX;
7107 }
64a0c779 7108
a724f0f4
JB		 7109 else if (prev_token.code == T_TBYTE)
7110 {
7111 if (intel_parser.got_a_float == 1)
7112 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7113 else
7114 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7115 }
9306ca4a 7116
a724f0f4 7117 else if (prev_token.code == T_XMMWORD)
9306ca4a 7118 {
a724f0f4
JB		 7119 /* XXX ignored for now, but accepted since gcc uses it */
7120 suffix = 0;
9306ca4a 7121 }
64a0c779 7122
f16b83df 7123 else
a724f0f4
JB		 7124 {
7125 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7126 return 0;
7127 }
7128
435acd52
JB		 7129 /* Operands for jump/call using 'ptr' notation denote absolute
7130 addresses. */
7131 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7132 i.types[this_operand] |= JumpAbsolute;
7133
a724f0f4
JB		 7134 if (current_templates->start->base_opcode == 0x8d /* lea */)
7135 ;
7136 else if (!i.suffix)
7137 i.suffix = suffix;
7138 else if (i.suffix != suffix)
7139 {
7140 as_bad (_("Conflicting operand modifiers"));
7141 return 0;
7142 }
64a0c779 7143
9306ca4a
JB		 7144 }
7145
a724f0f4
JB		 7146 /* e09' : e10 e09' */
7147 else if (cur_token.code == ':')
9306ca4a 7148 {
a724f0f4
JB		 7149 if (prev_token.code != T_REG)
7150 {
7151 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7152 segment/group identifier (which we don't have), using comma
7153 as the operand separator there is even less consistent, since
7154 there all branches only have a single operand. */
7155 if (this_operand != 0
7156 || intel_parser.in_offset
7157 || intel_parser.in_bracket
7158 || (!(current_templates->start->opcode_modifier
7159 & (Jump|JumpDword|JumpInterSegment))
7160 && !(current_templates->start->operand_types[0]
7161 & JumpAbsolute)))
7162 return intel_match_token (T_NIL);
7163 /* Remember the start of the 2nd operand and terminate 1st
7164 operand here.
7165 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7166 another expression), but it gets at least the simplest case
7167 (a plain number or symbol on the left side) right. */
7168 intel_parser.next_operand = intel_parser.op_string;
7169 *--intel_parser.op_string = '\0';
7170 return intel_match_token (':');
7171 }
9306ca4a 7172 }
64a0c779 7173
a724f0f4 7174 /* e09' Empty */
64a0c779 7175 else
a724f0f4 7176 break;
64a0c779 7177
a724f0f4
JB		 7178 intel_match_token (cur_token.code);
7179
7180 }
7181
7182 if (in_offset)
7183 {
7184 --intel_parser.in_offset;
7185 if (nregs < 0)
7186 nregs = ~nregs;
7187 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7188 {
a724f0f4 7189 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7190 return 0;
7191 }
a724f0f4
JB		 7192 intel_parser.op_modifier |= 1 << T_OFFSET;
7193 }
9306ca4a 7194
a724f0f4
JB		 7195 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7196 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7197 return 1;
7198}
64a0c779 7199
a724f0f4 7200static int
e3bb37b5 7201intel_bracket_expr (void)
a724f0f4
JB		 7202{
7203 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7204 const char *start = intel_parser.op_string;
7205 int len;
7206
7207 if (i.op[this_operand].regs)
7208 return intel_match_token (T_NIL);
7209
7210 intel_match_token ('[');
7211
7212 /* Mark as a memory operand only if it's not already known to be an
7213 offset expression. If it's an offset expression, we need to keep
7214 the brace in. */
7215 if (!intel_parser.in_offset)
7216 {
7217 ++intel_parser.in_bracket;
435acd52
JB		 7218
7219 /* Operands for jump/call inside brackets denote absolute addresses. */
7220 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7221 i.types[this_operand] |= JumpAbsolute;
7222
a724f0f4
JB		 7223 /* Unfortunately gas always diverged from MASM in a respect that can't
7224 be easily fixed without risking to break code sequences likely to be
7225 encountered (the testsuite even check for this): MASM doesn't consider
7226 an expression inside brackets unconditionally as a memory reference.
7227 When that is e.g. a constant, an offset expression, or the sum of the
7228 two, this is still taken as a constant load. gas, however, always
7229 treated these as memory references. As a compromise, we'll try to make
7230 offset expressions inside brackets work the MASM way (since that's
7231 less likely to be found in real world code), but make constants alone
7232 continue to work the traditional gas way. In either case, issue a
7233 warning. */
7234 intel_parser.op_modifier &= ~was_offset;
64a0c779 7235 }
a724f0f4 7236 else
64e74474 7237 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7238
7239 /* Add a '+' to the displacement string if necessary. */
7240 if (*intel_parser.disp != '\0'
7241 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7242 strcat (intel_parser.disp, "+");
64a0c779 7243
a724f0f4
JB		 7244 if (intel_expr ()
7245 && (len = intel_parser.op_string - start - 1,
7246 intel_match_token (']')))
64a0c779 7247 {
a724f0f4
JB		 7248 /* Preserve brackets when the operand is an offset expression. */
7249 if (intel_parser.in_offset)
7250 strcat (intel_parser.disp, "]");
7251 else
7252 {
7253 --intel_parser.in_bracket;
7254 if (i.base_reg || i.index_reg)
7255 intel_parser.is_mem = 1;
7256 if (!intel_parser.is_mem)
7257 {
7258 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7259 /* Defer the warning until all of the operand was parsed. */
7260 intel_parser.is_mem = -1;
7261 else if (!quiet_warnings)
4eed87de
AM		 7262 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7263 len, start, len, start);
a724f0f4
JB		 7264 }
7265 }
7266 intel_parser.op_modifier |= was_offset;
64a0c779 7267
a724f0f4 7268 return 1;
64a0c779 7269 }
a724f0f4 7270 return 0;
64a0c779
DN		 7271}
7272
7273/* e10 e11 e10'
7274
7275 e10' [ expr ] e10'
b77a7acd 7276 | Empty */
64a0c779 7277static int
e3bb37b5 7278intel_e10 (void)
64a0c779 7279{
a724f0f4
JB		 7280 if (!intel_e11 ())
7281 return 0;
64a0c779 7282
a724f0f4 7283 while (cur_token.code == '[')
64a0c779 7284 {
a724f0f4 7285 if (!intel_bracket_expr ())
21d6c4af 7286 return 0;
64a0c779
DN		 7287 }
7288
a724f0f4 7289 return 1;
64a0c779
DN		 7290}
7291
64a0c779 7292/* e11 ( expr )
b77a7acd 7293 | [ expr ]
64a0c779
DN		 7294 | BYTE
7295 | WORD
7296 | DWORD
9306ca4a 7297 | FWORD
64a0c779 7298 | QWORD
9306ca4a
JB		 7299 | TBYTE
7300 | OWORD
7301 | XMMWORD
4a1805b1 7302 | $
64a0c779
DN		 7303 | .
7304 | register
7305 | id
7306 | constant */
7307static int
e3bb37b5 7308intel_e11 (void)
64a0c779 7309{
a724f0f4 7310 switch (cur_token.code)
64a0c779 7311 {
a724f0f4
JB		 7312 /* e11 ( expr ) */
7313 case '(':
64a0c779
DN		 7314 intel_match_token ('(');
7315 strcat (intel_parser.disp, "(");
7316
7317 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7318 {
7319 strcat (intel_parser.disp, ")");
7320 return 1;
7321 }
a724f0f4 7322 return 0;
4a1805b1 7323
a724f0f4
JB		 7324 /* e11 [ expr ] */
7325 case '[':
a724f0f4 7326 return intel_bracket_expr ();
64a0c779 7327
a724f0f4
JB		 7328 /* e11 $
7329 | . */
7330 case '.':
64a0c779
DN		 7331 strcat (intel_parser.disp, cur_token.str);
7332 intel_match_token (cur_token.code);
21d6c4af
DN		 7333
7334 /* Mark as a memory operand only if it's not already known to be an
7335 offset expression. */
a724f0f4 7336 if (!intel_parser.in_offset)
21d6c4af 7337 intel_parser.is_mem = 1;
64a0c779
DN		 7338
7339 return 1;
64a0c779 7340
a724f0f4
JB		 7341 /* e11 register */
7342 case T_REG:
7343 {
7344 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7345
a724f0f4 7346 intel_match_token (T_REG);
64a0c779 7347
a724f0f4
JB		 7348 /* Check for segment change. */
7349 if (cur_token.code == ':')
7350 {
7351 if (!(reg->reg_type & (SReg2 | SReg3)))
7352 {
4eed87de
AM		 7353 as_bad (_("`%s' is not a valid segment register"),
7354 reg->reg_name);
a724f0f4
JB		 7355 return 0;
7356 }
7357 else if (i.seg[i.mem_operands])
7358 as_warn (_("Extra segment override ignored"));
7359 else
7360 {
7361 if (!intel_parser.in_offset)
7362 intel_parser.is_mem = 1;
7363 switch (reg->reg_num)
7364 {
7365 case 0:
7366 i.seg[i.mem_operands] = &es;
7367 break;
7368 case 1:
7369 i.seg[i.mem_operands] = &cs;
7370 break;
7371 case 2:
7372 i.seg[i.mem_operands] = &ss;
7373 break;
7374 case 3:
7375 i.seg[i.mem_operands] = &ds;
7376 break;
7377 case 4:
7378 i.seg[i.mem_operands] = &fs;
7379 break;
7380 case 5:
7381 i.seg[i.mem_operands] = &gs;
7382 break;
7383 }
7384 }
7385 }
64a0c779 7386
a724f0f4
JB		 7387 /* Not a segment register. Check for register scaling. */
7388 else if (cur_token.code == '*')
7389 {
7390 if (!intel_parser.in_bracket)
7391 {
7392 as_bad (_("Register scaling only allowed in memory operands"));
7393 return 0;
7394 }
64a0c779 7395
a724f0f4
JB		 7396 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7397 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7398 else if (i.index_reg)
7399 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7400
a724f0f4
JB		 7401 /* What follows must be a valid scale. */
7402 intel_match_token ('*');
7403 i.index_reg = reg;
7404 i.types[this_operand] |= BaseIndex;
64a0c779 7405
a724f0f4
JB		 7406 /* Set the scale after setting the register (otherwise,
7407 i386_scale will complain) */
7408 if (cur_token.code == '+' || cur_token.code == '-')
7409 {
7410 char *str, sign = cur_token.code;
7411 intel_match_token (cur_token.code);
7412 if (cur_token.code != T_CONST)
7413 {
7414 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7415 cur_token.str);
7416 return 0;
7417 }
7418 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7419 strcpy (str + 1, cur_token.str);
7420 *str = sign;
7421 if (!i386_scale (str))
7422 return 0;
7423 free (str);
7424 }
7425 else if (!i386_scale (cur_token.str))
64a0c779 7426 return 0;
a724f0f4
JB		 7427 intel_match_token (cur_token.code);
7428 }
64a0c779 7429
a724f0f4
JB		 7430 /* No scaling. If this is a memory operand, the register is either a
7431 base register (first occurrence) or an index register (second
7432 occurrence). */
7b0441f6 7433 else if (intel_parser.in_bracket)
a724f0f4 7434 {
64a0c779 7435
a724f0f4
JB		 7436 if (!i.base_reg)
7437 i.base_reg = reg;
7438 else if (!i.index_reg)
7439 i.index_reg = reg;
7440 else
7441 {
7442 as_bad (_("Too many register references in memory operand"));
7443 return 0;
7444 }
64a0c779 7445
a724f0f4
JB		 7446 i.types[this_operand] |= BaseIndex;
7447 }
4a1805b1 7448
4d1bb795
JB		 7449 /* It's neither base nor index. */
7450 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7451 {
7452 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7453 i.op[this_operand].regs = reg;
7454 i.reg_operands++;
7455 }
7456 else
7457 {
7458 as_bad (_("Invalid use of register"));
7459 return 0;
7460 }
64a0c779 7461
a724f0f4
JB		 7462 /* Since registers are not part of the displacement string (except
7463 when we're parsing offset operands), we may need to remove any
7464 preceding '+' from the displacement string. */
7465 if (*intel_parser.disp != '\0'
7466 && !intel_parser.in_offset)
7467 {
7468 char *s = intel_parser.disp;
7469 s += strlen (s) - 1;
7470 if (*s == '+')
7471 *s = '\0';
7472 }
4a1805b1 7473
a724f0f4
JB		 7474 return 1;
7475 }
7476
7477 /* e11 BYTE
7478 | WORD
7479 | DWORD
7480 | FWORD
7481 | QWORD
7482 | TBYTE
7483 | OWORD
7484 | XMMWORD */
7485 case T_BYTE:
7486 case T_WORD:
7487 case T_DWORD:
7488 case T_FWORD:
7489 case T_QWORD:
7490 case T_TBYTE:
7491 case T_XMMWORD:
7492 intel_match_token (cur_token.code);
64a0c779 7493
a724f0f4
JB		 7494 if (cur_token.code == T_PTR)
7495 return 1;
7496
7497 /* It must have been an identifier. */
7498 intel_putback_token ();
7499 cur_token.code = T_ID;
7500 /* FALLTHRU */
7501
7502 /* e11 id
7503 | constant */
7504 case T_ID:
7505 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7506 {
7507 symbolS *symbolP;
7508
a724f0f4
JB		 7509 /* The identifier represents a memory reference only if it's not
7510 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7511 symbolP = symbol_find(cur_token.str);
7512 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7513 intel_parser.is_mem = 1;
7514 }
a724f0f4 7515 /* FALLTHRU */
64a0c779 7516
a724f0f4
JB		 7517 case T_CONST:
7518 case '-':
7519 case '+':
7520 {
7521 char *save_str, sign = 0;
64a0c779 7522
a724f0f4
JB		 7523 /* Allow constants that start with `+' or `-'. */
7524 if (cur_token.code == '-' || cur_token.code == '+')
7525 {
7526 sign = cur_token.code;
7527 intel_match_token (cur_token.code);
7528 if (cur_token.code != T_CONST)
7529 {
7530 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7531 cur_token.str);
7532 return 0;
7533 }
7534 }
64a0c779 7535
a724f0f4
JB		 7536 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7537 strcpy (save_str + !!sign, cur_token.str);
7538 if (sign)
7539 *save_str = sign;
64a0c779 7540
a724f0f4
JB		 7541 /* Get the next token to check for register scaling. */
7542 intel_match_token (cur_token.code);
64a0c779 7543
4eed87de
AM		 7544 /* Check if this constant is a scaling factor for an
7545 index register. */
a724f0f4
JB		 7546 if (cur_token.code == '*')
7547 {
7548 if (intel_match_token ('*') && cur_token.code == T_REG)
7549 {
7550 const reg_entry *reg = cur_token.reg;
7551
7552 if (!intel_parser.in_bracket)
7553 {
4eed87de
AM		 7554 as_bad (_("Register scaling only allowed "
7555 "in memory operands"));
a724f0f4
JB		 7556 return 0;
7557 }
7558
4eed87de
AM		 7559 /* Disallow things like [1*si].
7560 sp and esp are invalid as index. */
7561 if (reg->reg_type & Reg16)
7562 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7563 else if (i.index_reg)
4eed87de 7564 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7565
7566 /* The constant is followed by `* reg', so it must be
7567 a valid scale. */
7568 i.index_reg = reg;
7569 i.types[this_operand] |= BaseIndex;
7570
7571 /* Set the scale after setting the register (otherwise,
7572 i386_scale will complain) */
7573 if (!i386_scale (save_str))
64a0c779 7574 return 0;
a724f0f4
JB		 7575 intel_match_token (T_REG);
7576
7577 /* Since registers are not part of the displacement
7578 string, we may need to remove any preceding '+' from
7579 the displacement string. */
7580 if (*intel_parser.disp != '\0')
7581 {
7582 char *s = intel_parser.disp;
7583 s += strlen (s) - 1;
7584 if (*s == '+')
7585 *s = '\0';
7586 }
7587
7588 free (save_str);
7589
7590 return 1;
7591 }
64a0c779 7592
a724f0f4
JB		 7593 /* The constant was not used for register scaling. Since we have
7594 already consumed the token following `*' we now need to put it
7595 back in the stream. */
64a0c779 7596 intel_putback_token ();
a724f0f4 7597 }
64a0c779 7598
a724f0f4
JB		 7599 /* Add the constant to the displacement string. */
7600 strcat (intel_parser.disp, save_str);
7601 free (save_str);
64a0c779 7602
a724f0f4
JB		 7603 return 1;
7604 }
64a0c779
DN		 7605 }
7606
64a0c779
DN		 7607 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7608 return 0;
7609}
7610
64a0c779
DN		 7611/* Match the given token against cur_token. If they match, read the next
7612 token from the operand string. */
7613static int
e3bb37b5 7614intel_match_token (int code)
64a0c779
DN		 7615{
7616 if (cur_token.code == code)
7617 {
7618 intel_get_token ();
7619 return 1;
7620 }
7621 else
7622 {
0477af35 7623 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7624 return 0;
7625 }
7626}
7627
64a0c779
DN		 7628/* Read a new token from intel_parser.op_string and store it in cur_token. */
7629static void
e3bb37b5 7630intel_get_token (void)
64a0c779
DN		 7631{
7632 char *end_op;
7633 const reg_entry *reg;
7634 struct intel_token new_token;
7635
7636 new_token.code = T_NIL;
7637 new_token.reg = NULL;
7638 new_token.str = NULL;
7639
4a1805b1 7640 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7641 cur_token to prev_token. */
7642 if (prev_token.str)
7643 free (prev_token.str);
7644
7645 prev_token = cur_token;
7646
7647 /* Skip whitespace. */
7648 while (is_space_char (*intel_parser.op_string))
7649 intel_parser.op_string++;
7650
7651 /* Return an empty token if we find nothing else on the line. */
7652 if (*intel_parser.op_string == '\0')
7653 {
7654 cur_token = new_token;
7655 return;
7656 }
7657
7658 /* The new token cannot be larger than the remainder of the operand
7659 string. */
a724f0f4 7660 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7661 new_token.str[0] = '\0';
7662
7663 if (strchr ("0123456789", *intel_parser.op_string))
7664 {
7665 char *p = new_token.str;
7666 char *q = intel_parser.op_string;
7667 new_token.code = T_CONST;
7668
7669 /* Allow any kind of identifier char to encompass floating point and
7670 hexadecimal numbers. */
7671 while (is_identifier_char (*q))
7672 *p++ = *q++;
7673 *p = '\0';
7674
7675 /* Recognize special symbol names [0-9][bf]. */
7676 if (strlen (intel_parser.op_string) == 2
4a1805b1 7677 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7678 || intel_parser.op_string[1] == 'f'))
7679 new_token.code = T_ID;
7680 }
7681
4d1bb795 7682 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7683 {
4d1bb795
JB		 7684 size_t len = end_op - intel_parser.op_string;
7685
64a0c779
DN		 7686 new_token.code = T_REG;
7687 new_token.reg = reg;
7688
4d1bb795
JB		 7689 memcpy (new_token.str, intel_parser.op_string, len);
7690 new_token.str[len] = '\0';
64a0c779
DN		 7691 }
7692
7693 else if (is_identifier_char (*intel_parser.op_string))
7694 {
7695 char *p = new_token.str;
7696 char *q = intel_parser.op_string;
7697
7698 /* A '.' or '$' followed by an identifier char is an identifier.
7699 Otherwise, it's operator '.' followed by an expression. */
7700 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7701 {
9306ca4a
JB		 7702 new_token.code = '.';
7703 new_token.str[0] = '.';
64a0c779
DN		 7704 new_token.str[1] = '\0';
7705 }
7706 else
7707 {
7708 while (is_identifier_char (*q) || *q == '@')
7709 *p++ = *q++;
7710 *p = '\0';
7711
9306ca4a
JB		 7712 if (strcasecmp (new_token.str, "NOT") == 0)
7713 new_token.code = '~';
7714
7715 else if (strcasecmp (new_token.str, "MOD") == 0)
7716 new_token.code = '%';
7717
7718 else if (strcasecmp (new_token.str, "AND") == 0)
7719 new_token.code = '&';
7720
7721 else if (strcasecmp (new_token.str, "OR") == 0)
7722 new_token.code = '|';
7723
7724 else if (strcasecmp (new_token.str, "XOR") == 0)
7725 new_token.code = '^';
7726
7727 else if (strcasecmp (new_token.str, "SHL") == 0)
7728 new_token.code = T_SHL;
7729
7730 else if (strcasecmp (new_token.str, "SHR") == 0)
7731 new_token.code = T_SHR;
7732
7733 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7734 new_token.code = T_BYTE;
7735
7736 else if (strcasecmp (new_token.str, "WORD") == 0)
7737 new_token.code = T_WORD;
7738
7739 else if (strcasecmp (new_token.str, "DWORD") == 0)
7740 new_token.code = T_DWORD;
7741
9306ca4a
JB		 7742 else if (strcasecmp (new_token.str, "FWORD") == 0)
7743 new_token.code = T_FWORD;
7744
64a0c779
DN		 7745 else if (strcasecmp (new_token.str, "QWORD") == 0)
7746 new_token.code = T_QWORD;
7747
9306ca4a
JB		 7748 else if (strcasecmp (new_token.str, "TBYTE") == 0
7749 /* XXX remove (gcc still uses it) */
7750 || strcasecmp (new_token.str, "XWORD") == 0)
7751 new_token.code = T_TBYTE;
7752
7753 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7754 || strcasecmp (new_token.str, "OWORD") == 0)
7755 new_token.code = T_XMMWORD;
64a0c779
DN		 7756
7757 else if (strcasecmp (new_token.str, "PTR") == 0)
7758 new_token.code = T_PTR;
7759
7760 else if (strcasecmp (new_token.str, "SHORT") == 0)
7761 new_token.code = T_SHORT;
7762
7763 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7764 {
7765 new_token.code = T_OFFSET;
7766
7767 /* ??? This is not mentioned in the MASM grammar but gcc
7768 makes use of it with -mintel-syntax. OFFSET may be
7769 followed by FLAT: */
7770 if (strncasecmp (q, " FLAT:", 6) == 0)
7771 strcat (new_token.str, " FLAT:");
7772 }
7773
7774 /* ??? This is not mentioned in the MASM grammar. */
7775 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7776 {
7777 new_token.code = T_OFFSET;
7778 if (*q == ':')
7779 strcat (new_token.str, ":");
7780 else
7781 as_bad (_("`:' expected"));
7782 }
64a0c779
DN		 7783
7784 else
7785 new_token.code = T_ID;
7786 }
7787 }
7788
9306ca4a
JB		 7789 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7790 {
7791 new_token.code = *intel_parser.op_string;
7792 new_token.str[0] = *intel_parser.op_string;
7793 new_token.str[1] = '\0';
7794 }
7795
7796 else if (strchr ("<>", *intel_parser.op_string)
7797 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7798 {
7799 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7800 new_token.str[0] = *intel_parser.op_string;
7801 new_token.str[1] = *intel_parser.op_string;
7802 new_token.str[2] = '\0';
7803 }
7804
64a0c779 7805 else
0477af35 7806 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7807
7808 intel_parser.op_string += strlen (new_token.str);
7809 cur_token = new_token;
7810}
7811
64a0c779
DN		 7812/* Put cur_token back into the token stream and make cur_token point to
7813 prev_token. */
7814static void
e3bb37b5 7815intel_putback_token (void)
64a0c779 7816{
a724f0f4
JB		 7817 if (cur_token.code != T_NIL)
7818 {
7819 intel_parser.op_string -= strlen (cur_token.str);
7820 free (cur_token.str);
7821 }
64a0c779 7822 cur_token = prev_token;
4a1805b1 7823
64a0c779
DN		 7824 /* Forget prev_token. */
7825 prev_token.code = T_NIL;
7826 prev_token.reg = NULL;
7827 prev_token.str = NULL;
7828}
54cfded0 7829
a4447b93 7830int
1df69f4f 7831tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7832{
7833 unsigned int regnum;
7834 unsigned int regnames_count;
089dfecd 7835 static const char *const regnames_32[] =
54cfded0 7836 {
a4447b93
RH		 7837 "eax", "ecx", "edx", "ebx",
7838 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7839 "eip", "eflags", NULL,
7840 "st0", "st1", "st2", "st3",
7841 "st4", "st5", "st6", "st7",
7842 NULL, NULL,
7843 "xmm0", "xmm1", "xmm2", "xmm3",
7844 "xmm4", "xmm5", "xmm6", "xmm7",
7845 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7846 "mm4", "mm5", "mm6", "mm7",
7847 "fcw", "fsw", "mxcsr",
7848 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7849 "tr", "ldtr"
54cfded0 7850 };
089dfecd 7851 static const char *const regnames_64[] =
54cfded0 7852 {
089dfecd
JB		 7853 "rax", "rdx", "rcx", "rbx",
7854 "rsi", "rdi", "rbp", "rsp",
7855 "r8", "r9", "r10", "r11",
54cfded0 7856 "r12", "r13", "r14", "r15",
089dfecd
JB		 7857 "rip",
7858 "xmm0", "xmm1", "xmm2", "xmm3",
7859 "xmm4", "xmm5", "xmm6", "xmm7",
7860 "xmm8", "xmm9", "xmm10", "xmm11",
7861 "xmm12", "xmm13", "xmm14", "xmm15",
7862 "st0", "st1", "st2", "st3",
7863 "st4", "st5", "st6", "st7",
7864 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7865 "mm4", "mm5", "mm6", "mm7",
7866 "rflags",
7867 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7868 "fs.base", "gs.base", NULL, NULL,
7869 "tr", "ldtr",
7870 "mxcsr", "fcw", "fsw"
54cfded0 7871 };
089dfecd 7872 const char *const *regnames;
54cfded0
AM		 7873
7874 if (flag_code == CODE_64BIT)
7875 {
7876 regnames = regnames_64;
0cea6190 7877 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7878 }
7879 else
7880 {
7881 regnames = regnames_32;
0cea6190 7882 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7883 }
7884
7885 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7886 if (regnames[regnum] != NULL
7887 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7888 return regnum;
7889
54cfded0
AM		 7890 return -1;
7891}
7892
7893void
7894tc_x86_frame_initial_instructions (void)
7895{
a4447b93
RH		 7896 static unsigned int sp_regno;
7897
7898 if (!sp_regno)
7899 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7900 ? "rsp" : "esp");
7901
7902 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7903 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7904}
d2b2c203
DJ		 7905
7906int
7907i386_elf_section_type (const char *str, size_t len)
7908{
7909 if (flag_code == CODE_64BIT
7910 && len == sizeof ("unwind") - 1
7911 && strncmp (str, "unwind", 6) == 0)
7912 return SHT_X86_64_UNWIND;
7913
7914 return -1;
7915}
bb41ade5
AM		 7916
7917#ifdef TE_PE
7918void
7919tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7920{
7921 expressionS expr;
7922
7923 expr.X_op = O_secrel;
7924 expr.X_add_symbol = symbol;
7925 expr.X_add_number = 0;
7926 emit_expr (&expr, size);
7927}
7928#endif
3b22753a
L		 7929
7930#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7931/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7932
7933int
7934x86_64_section_letter (int letter, char **ptr_msg)
7935{
7936 if (flag_code == CODE_64BIT)
7937 {
7938 if (letter == 'l')
7939 return SHF_X86_64_LARGE;
7940
7941 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7942 }
3b22753a 7943 else
64e74474 7944 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7945 return -1;
7946}
7947
7948int
7949x86_64_section_word (char *str, size_t len)
7950{
8620418b 7951 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7952 return SHF_X86_64_LARGE;
7953
7954 return -1;
7955}
7956
7957static void
7958handle_large_common (int small ATTRIBUTE_UNUSED)
7959{
7960 if (flag_code != CODE_64BIT)
7961 {
7962 s_comm_internal (0, elf_common_parse);
7963 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7964 }
7965 else
7966 {
7967 static segT lbss_section;
7968 asection *saved_com_section_ptr = elf_com_section_ptr;
7969 asection *saved_bss_section = bss_section;
7970
7971 if (lbss_section == NULL)
7972 {
7973 flagword applicable;
7974 segT seg = now_seg;
7975 subsegT subseg = now_subseg;
7976
7977 /* The .lbss section is for local .largecomm symbols. */
7978 lbss_section = subseg_new (".lbss", 0);
7979 applicable = bfd_applicable_section_flags (stdoutput);
7980 bfd_set_section_flags (stdoutput, lbss_section,
7981 applicable & SEC_ALLOC);
7982 seg_info (lbss_section)->bss = 1;
7983
7984 subseg_set (seg, subseg);
7985 }
7986
7987 elf_com_section_ptr = &_bfd_elf_large_com_section;
7988 bss_section = lbss_section;
7989
7990 s_comm_internal (0, elf_common_parse);
7991
7992 elf_com_section_ptr = saved_com_section_ptr;
7993 bss_section = saved_bss_section;
7994 }
7995}
7996#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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